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i386/kvm: expose HV_CPUID_ENLIGHTMENT_INFO.EAX and HV_CPUID_NESTED_FEATURES.EAX as...
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
c6dc6f63
AP		 24
25#include "cpu.h"
63c91552 26#include "exec/exec-all.h"
9c17d615 27#include "sysemu/kvm.h"
d6dcc558 28#include "sysemu/hvf.h"
8932cfdf 29#include "sysemu/cpus.h"
50a2c6e5 30#include "kvm_i386.h"
6cb8f2a6 31#include "sev_i386.h"
c6dc6f63 32
d49b6836 33#include "qemu/error-report.h"
1de7afc9
PB		 34#include "qemu/option.h"
35#include "qemu/config-file.h"
e688df6b 36#include "qapi/error.h"
112ed241
MA		 37#include "qapi/qapi-visit-misc.h"
38#include "qapi/qapi-visit-run-state.h"
452fcdbc 39#include "qapi/qmp/qdict.h"
7b1b5d19 40#include "qapi/qmp/qerror.h"
7b1b5d19 41#include "qapi/visitor.h"
f99fd7ca 42#include "qom/qom-qobject.h"
9c17d615 43#include "sysemu/arch_init.h"
71ad61d3 44
1814eab6 45#include "standard-headers/asm-x86/kvm_para.h"
65dee380 46
9c17d615 47#include "sysemu/sysemu.h"
53a89e26 48#include "hw/qdev-properties.h"
5232d00a 49#include "hw/i386/topology.h"
bdeec802 50#ifndef CONFIG_USER_ONLY
2001d0cd 51#include "exec/address-spaces.h"
741da0d3 52#include "hw/hw.h"
0d09e41a 53#include "hw/xen/xen.h"
0d09e41a 54#include "hw/i386/apic_internal.h"
bdeec802
IM		 55#endif
56
b666d2a4
RH		 57#include "disas/capstone.h"
58
7e3482f8
EH		 59/* Helpers for building CPUID[2] descriptors: */
60
61struct CPUID2CacheDescriptorInfo {
62 enum CacheType type;
63 int level;
64 int size;
65 int line_size;
66 int associativity;
67};
5e891bf8 68
7e3482f8
EH		 69/*
70 * Known CPUID 2 cache descriptors.
71 * From Intel SDM Volume 2A, CPUID instruction
72 */
73struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 74 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 64, },
5f00335a 80 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 32, },
5f00335a 82 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 32, },
5f00335a 84 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 64, },
5f00335a 86 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 87 .associativity = 6, .line_size = 64, },
5f00335a 88 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 89 .associativity = 2, .line_size = 64, },
5f00335a 90 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 91 .associativity = 8, .line_size = 64, },
92 /* lines per sector is not supported cpuid2_cache_descriptor(),
93 * so descriptors 0x22, 0x23 are not included
94 */
5f00335a 95 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 96 .associativity = 16, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x25, 0x20 are not included
99 */
5f00335a 100 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 101 .associativity = 8, .line_size = 64, },
5f00335a 102 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 64, },
5f00335a 116 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 117 .associativity = 8, .line_size = 64, },
5f00335a 118 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 119 .associativity = 12, .line_size = 64, },
120 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 121 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 12, .line_size = 64, },
5f00335a 123 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 124 .associativity = 16, .line_size = 64, },
5f00335a 125 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 130 .associativity = 24, .line_size = 64, },
5f00335a 131 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 134 .associativity = 4, .line_size = 64, },
5f00335a 135 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 140 .associativity = 4, .line_size = 64, },
141 /* lines per sector is not supported cpuid2_cache_descriptor(),
142 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
143 */
5f00335a 144 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 64, },
5f00335a 146 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 2, .line_size = 64, },
5f00335a 148 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 32, },
5f00335a 152 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 8, .line_size = 64, },
5f00335a 170 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 175 .associativity = 12, .line_size = 64, },
5f00335a 176 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 181 .associativity = 16, .line_size = 64, },
5f00335a 182 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 187 .associativity = 24, .line_size = 64, },
5f00335a 188 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 191 .associativity = 24, .line_size = 64, },
192};
193
194/*
195 * "CPUID leaf 2 does not report cache descriptor information,
196 * use CPUID leaf 4 to query cache parameters"
197 */
198#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 199
7e3482f8
EH		 200/*
201 * Return a CPUID 2 cache descriptor for a given cache.
202 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
203 */
204static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
205{
206 int i;
207
208 assert(cache->size > 0);
209 assert(cache->level > 0);
210 assert(cache->line_size > 0);
211 assert(cache->associativity > 0);
212 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
213 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
214 if (d->level == cache->level && d->type == cache->type &&
215 d->size == cache->size && d->line_size == cache->line_size &&
216 d->associativity == cache->associativity) {
217 return i;
218 }
219 }
5e891bf8 220
7e3482f8
EH		 221 return CACHE_DESCRIPTOR_UNAVAILABLE;
222}
5e891bf8
EH		 223
224/* CPUID Leaf 4 constants: */
225
226/* EAX: */
7e3482f8
EH		 227#define CACHE_TYPE_D 1
228#define CACHE_TYPE_I 2
229#define CACHE_TYPE_UNIFIED 3
5e891bf8 230
7e3482f8 231#define CACHE_LEVEL(l) (l << 5)
5e891bf8 232
7e3482f8 233#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 234
235/* EDX: */
7e3482f8
EH		 236#define CACHE_NO_INVD_SHARING (1 << 0)
237#define CACHE_INCLUSIVE (1 << 1)
238#define CACHE_COMPLEX_IDX (1 << 2)
239
240/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 241#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
242 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
243 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
244 0 /* Invalid value */)
7e3482f8
EH		 245
246
247/* Encode cache info for CPUID[4] */
248static void encode_cache_cpuid4(CPUCacheInfo *cache,
249 int num_apic_ids, int num_cores,
250 uint32_t *eax, uint32_t *ebx,
251 uint32_t *ecx, uint32_t *edx)
252{
253 assert(cache->size == cache->line_size * cache->associativity *
254 cache->partitions * cache->sets);
255
256 assert(num_apic_ids > 0);
257 *eax = CACHE_TYPE(cache->type) |
258 CACHE_LEVEL(cache->level) |
259 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
260 ((num_cores - 1) << 26) |
261 ((num_apic_ids - 1) << 14);
262
263 assert(cache->line_size > 0);
264 assert(cache->partitions > 0);
265 assert(cache->associativity > 0);
266 /* We don't implement fully-associative caches */
267 assert(cache->associativity < cache->sets);
268 *ebx = (cache->line_size - 1) |
269 ((cache->partitions - 1) << 12) |
270 ((cache->associativity - 1) << 22);
271
272 assert(cache->sets > 0);
273 *ecx = cache->sets - 1;
274
275 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
276 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
277 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
278}
279
280/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
281static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
282{
283 assert(cache->size % 1024 == 0);
284 assert(cache->lines_per_tag > 0);
285 assert(cache->associativity > 0);
286 assert(cache->line_size > 0);
287 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
288 (cache->lines_per_tag << 8) | (cache->line_size);
289}
5e891bf8
EH		 290
291#define ASSOC_FULL 0xFF
292
293/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
294#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == 2 ? 0x2 : \
296 a == 4 ? 0x4 : \
297 a == 8 ? 0x6 : \
298 a == 16 ? 0x8 : \
299 a == 32 ? 0xA : \
300 a == 48 ? 0xB : \
301 a == 64 ? 0xC : \
302 a == 96 ? 0xD : \
303 a == 128 ? 0xE : \
304 a == ASSOC_FULL ? 0xF : \
305 0 /* invalid value */)
306
7e3482f8
EH		 307/*
308 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
309 * @l3 can be NULL.
310 */
311static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
312 CPUCacheInfo *l3,
313 uint32_t *ecx, uint32_t *edx)
314{
315 assert(l2->size % 1024 == 0);
316 assert(l2->associativity > 0);
317 assert(l2->lines_per_tag > 0);
318 assert(l2->line_size > 0);
319 *ecx = ((l2->size / 1024) << 16) |
320 (AMD_ENC_ASSOC(l2->associativity) << 12) |
321 (l2->lines_per_tag << 8) | (l2->line_size);
322
323 if (l3) {
324 assert(l3->size % (512 * 1024) == 0);
325 assert(l3->associativity > 0);
326 assert(l3->lines_per_tag > 0);
327 assert(l3->line_size > 0);
328 *edx = ((l3->size / (512 * 1024)) << 18) |
329 (AMD_ENC_ASSOC(l3->associativity) << 12) |
330 (l3->lines_per_tag << 8) | (l3->line_size);
331 } else {
332 *edx = 0;
333 }
334}
5e891bf8 335
8f4202fb
BM		 336/*
337 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
338 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
339 * Define the constants to build the cpu topology. Right now, TOPOEXT
340 * feature is enabled only on EPYC. So, these constants are based on
341 * EPYC supported configurations. We may need to handle the cases if
342 * these values change in future.
343 */
344/* Maximum core complexes in a node */
345#define MAX_CCX 2
346/* Maximum cores in a core complex */
347#define MAX_CORES_IN_CCX 4
348/* Maximum cores in a node */
349#define MAX_CORES_IN_NODE 8
350/* Maximum nodes in a socket */
351#define MAX_NODES_PER_SOCKET 4
352
353/*
354 * Figure out the number of nodes required to build this config.
355 * Max cores in a node is 8
356 */
357static int nodes_in_socket(int nr_cores)
358{
359 int nodes;
360
361 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
362
363 /* Hardware does not support config with 3 nodes, return 4 in that case */
364 return (nodes == 3) ? 4 : nodes;
365}
366
367/*
368 * Decide the number of cores in a core complex with the given nr_cores using
369 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
370 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
371 * L3 cache is shared across all cores in a core complex. So, this will also
372 * tell us how many cores are sharing the L3 cache.
373 */
374static int cores_in_core_complex(int nr_cores)
375{
376 int nodes;
377
378 /* Check if we can fit all the cores in one core complex */
379 if (nr_cores <= MAX_CORES_IN_CCX) {
380 return nr_cores;
381 }
382 /* Get the number of nodes required to build this config */
383 nodes = nodes_in_socket(nr_cores);
384
385 /*
386 * Divide the cores accros all the core complexes
387 * Return rounded up value
388 */
389 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
390}
391
392/* Encode cache info for CPUID[8000001D] */
393static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
394 uint32_t *eax, uint32_t *ebx,
395 uint32_t *ecx, uint32_t *edx)
396{
397 uint32_t l3_cores;
398 assert(cache->size == cache->line_size * cache->associativity *
399 cache->partitions * cache->sets);
400
401 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
402 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
403
404 /* L3 is shared among multiple cores */
405 if (cache->level == 3) {
406 l3_cores = cores_in_core_complex(cs->nr_cores);
407 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
408 } else {
409 *eax |= ((cs->nr_threads - 1) << 14);
410 }
411
412 assert(cache->line_size > 0);
413 assert(cache->partitions > 0);
414 assert(cache->associativity > 0);
415 /* We don't implement fully-associative caches */
416 assert(cache->associativity < cache->sets);
417 *ebx = (cache->line_size - 1) |
418 ((cache->partitions - 1) << 12) |
419 ((cache->associativity - 1) << 22);
420
421 assert(cache->sets > 0);
422 *ecx = cache->sets - 1;
423
424 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
425 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
426 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
427}
428
ed78467a
BM		 429/* Data structure to hold the configuration info for a given core index */
430struct core_topology {
431 /* core complex id of the current core index */
432 int ccx_id;
433 /*
434 * Adjusted core index for this core in the topology
435 * This can be 0,1,2,3 with max 4 cores in a core complex
436 */
437 int core_id;
438 /* Node id for this core index */
439 int node_id;
440 /* Number of nodes in this config */
441 int num_nodes;
442};
443
444/*
445 * Build the configuration closely match the EPYC hardware. Using the EPYC
446 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
447 * right now. This could change in future.
448 * nr_cores : Total number of cores in the config
449 * core_id : Core index of the current CPU
450 * topo : Data structure to hold all the config info for this core index
451 */
452static void build_core_topology(int nr_cores, int core_id,
453 struct core_topology *topo)
454{
455 int nodes, cores_in_ccx;
456
457 /* First get the number of nodes required */
458 nodes = nodes_in_socket(nr_cores);
459
460 cores_in_ccx = cores_in_core_complex(nr_cores);
461
462 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
463 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
464 topo->core_id = core_id % cores_in_ccx;
465 topo->num_nodes = nodes;
466}
467
468/* Encode cache info for CPUID[8000001E] */
469static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
470 uint32_t *eax, uint32_t *ebx,
471 uint32_t *ecx, uint32_t *edx)
472{
473 struct core_topology topo = {0};
631be321
BM		 474 unsigned long nodes;
475 int shift;
ed78467a
BM		 476
477 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
478 *eax = cpu->apic_id;
479 /*
480 * CPUID_Fn8000001E_EBX
481 * 31:16 Reserved
482 * 15:8 Threads per core (The number of threads per core is
483 * Threads per core + 1)
484 * 7:0 Core id (see bit decoding below)
485 * SMT:
486 * 4:3 node id
487 * 2 Core complex id
488 * 1:0 Core id
489 * Non SMT:
490 * 5:4 node id
491 * 3 Core complex id
492 * 1:0 Core id
493 */
494 if (cs->nr_threads - 1) {
495 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
496 (topo.ccx_id << 2) | topo.core_id;
497 } else {
498 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
499 }
500 /*
501 * CPUID_Fn8000001E_ECX
502 * 31:11 Reserved
503 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
504 * 7:0 Node id (see bit decoding below)
505 * 2 Socket id
506 * 1:0 Node id
507 */
631be321
BM		 508 if (topo.num_nodes <= 4) {
509 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
510 topo.node_id;
511 } else {
512 /*
513 * Node id fix up. Actual hardware supports up to 4 nodes. But with
514 * more than 32 cores, we may end up with more than 4 nodes.
515 * Node id is a combination of socket id and node id. Only requirement
516 * here is that this number should be unique accross the system.
517 * Shift the socket id to accommodate more nodes. We dont expect both
518 * socket id and node id to be big number at the same time. This is not
519 * an ideal config but we need to to support it. Max nodes we can have
520 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
521 * 5 bits for nodes. Find the left most set bit to represent the total
522 * number of nodes. find_last_bit returns last set bit(0 based). Left
523 * shift(+1) the socket id to represent all the nodes.
524 */
525 nodes = topo.num_nodes - 1;
526 shift = find_last_bit(&nodes, 8);
527 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
528 topo.node_id;
529 }
ed78467a
BM		 530 *edx = 0;
531}
532
ab8f992e
BM		 533/*
534 * Definitions of the hardcoded cache entries we expose:
535 * These are legacy cache values. If there is a need to change any
536 * of these values please use builtin_x86_defs
537 */
5e891bf8
EH		 538
539/* L1 data cache: */
ab8f992e 540static CPUCacheInfo legacy_l1d_cache = {
5f00335a 541 .type = DATA_CACHE,
7e3482f8
EH		 542 .level = 1,
543 .size = 32 * KiB,
544 .self_init = 1,
545 .line_size = 64,
546 .associativity = 8,
547 .sets = 64,
548 .partitions = 1,
549 .no_invd_sharing = true,
550};
551
5e891bf8 552/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 553static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 554 .type = DATA_CACHE,
7e3482f8
EH		 555 .level = 1,
556 .size = 64 * KiB,
557 .self_init = 1,
558 .line_size = 64,
559 .associativity = 2,
560 .sets = 512,
561 .partitions = 1,
562 .lines_per_tag = 1,
563 .no_invd_sharing = true,
564};
5e891bf8
EH		 565
566/* L1 instruction cache: */
ab8f992e 567static CPUCacheInfo legacy_l1i_cache = {
5f00335a 568 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 569 .level = 1,
570 .size = 32 * KiB,
571 .self_init = 1,
572 .line_size = 64,
573 .associativity = 8,
574 .sets = 64,
575 .partitions = 1,
576 .no_invd_sharing = true,
577};
578
5e891bf8 579/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 580static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 581 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 582 .level = 1,
583 .size = 64 * KiB,
584 .self_init = 1,
585 .line_size = 64,
586 .associativity = 2,
587 .sets = 512,
588 .partitions = 1,
589 .lines_per_tag = 1,
590 .no_invd_sharing = true,
591};
5e891bf8
EH		 592
593/* Level 2 unified cache: */
ab8f992e 594static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 595 .type = UNIFIED_CACHE,
596 .level = 2,
597 .size = 4 * MiB,
598 .self_init = 1,
599 .line_size = 64,
600 .associativity = 16,
601 .sets = 4096,
602 .partitions = 1,
603 .no_invd_sharing = true,
604};
605
5e891bf8 606/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 607static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 608 .type = UNIFIED_CACHE,
609 .level = 2,
610 .size = 2 * MiB,
611 .line_size = 64,
612 .associativity = 8,
613};
614
615
5e891bf8 616/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 617static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 618 .type = UNIFIED_CACHE,
619 .level = 2,
620 .size = 512 * KiB,
621 .line_size = 64,
622 .lines_per_tag = 1,
623 .associativity = 16,
624 .sets = 512,
625 .partitions = 1,
626};
5e891bf8 627
14c985cf 628/* Level 3 unified cache: */
ab8f992e 629static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 630 .type = UNIFIED_CACHE,
631 .level = 3,
632 .size = 16 * MiB,
633 .line_size = 64,
634 .associativity = 16,
635 .sets = 16384,
636 .partitions = 1,
637 .lines_per_tag = 1,
638 .self_init = true,
639 .inclusive = true,
640 .complex_indexing = true,
641};
5e891bf8
EH		 642
643/* TLB definitions: */
644
645#define L1_DTLB_2M_ASSOC 1
646#define L1_DTLB_2M_ENTRIES 255
647#define L1_DTLB_4K_ASSOC 1
648#define L1_DTLB_4K_ENTRIES 255
649
650#define L1_ITLB_2M_ASSOC 1
651#define L1_ITLB_2M_ENTRIES 255
652#define L1_ITLB_4K_ASSOC 1
653#define L1_ITLB_4K_ENTRIES 255
654
655#define L2_DTLB_2M_ASSOC 0 /* disabled */
656#define L2_DTLB_2M_ENTRIES 0 /* disabled */
657#define L2_DTLB_4K_ASSOC 4
658#define L2_DTLB_4K_ENTRIES 512
659
660#define L2_ITLB_2M_ASSOC 0 /* disabled */
661#define L2_ITLB_2M_ENTRIES 0 /* disabled */
662#define L2_ITLB_4K_ASSOC 4
663#define L2_ITLB_4K_ENTRIES 512
664
e37a5c7f
CP		 665/* CPUID Leaf 0x14 constants: */
666#define INTEL_PT_MAX_SUBLEAF 0x1
667/*
668 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
669 * MSR can be accessed;
670 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
671 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
672 * of Intel PT MSRs across warm reset;
673 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
674 */
675#define INTEL_PT_MINIMAL_EBX 0xf
676/*
677 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
678 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
679 * accessed;
680 * bit[01]: ToPA tables can hold any number of output entries, up to the
681 * maximum allowed by the MaskOrTableOffset field of
682 * IA32_RTIT_OUTPUT_MASK_PTRS;
683 * bit[02]: Support Single-Range Output scheme;
684 */
685#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 686/* generated packets which contain IP payloads have LIP values */
687#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 688#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
689#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
690#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
691#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
692#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 693
99b88a17
IM		 694static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
695 uint32_t vendor2, uint32_t vendor3)
696{
697 int i;
698 for (i = 0; i < 4; i++) {
699 dst[i] = vendor1 >> (8 * i);
700 dst[i + 4] = vendor2 >> (8 * i);
701 dst[i + 8] = vendor3 >> (8 * i);
702 }
703 dst[CPUID_VENDOR_SZ] = '\0';
704}
705
621626ce
EH		 706#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
707#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
708 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
709#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
710 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
711 CPUID_PSE36 | CPUID_FXSR)
712#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
713#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
714 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
715 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
716 CPUID_PAE | CPUID_SEP | CPUID_APIC)
717
718#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
719 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
720 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
721 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 722 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 723 /* partly implemented:
724 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
725 /* missing:
726 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
727#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
728 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
729 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 730 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 731 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
732 /* missing:
733 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
734 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
735 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 736 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
737 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 738
739#ifdef TARGET_X86_64
740#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
741#else
742#define TCG_EXT2_X86_64_FEATURES 0
743#endif
744
745#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
746 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
747 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
748 TCG_EXT2_X86_64_FEATURES)
749#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
750 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
751#define TCG_EXT4_FEATURES 0
fe441054 752#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 753#define TCG_KVM_FEATURES 0
754#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 755 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
756 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 757 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
758 CPUID_7_0_EBX_ERMS)
621626ce 759 /* missing:
07929f2a 760 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 761 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 762 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 763#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
764 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 765 CPUID_7_0_ECX_LA57)
95ea69fb 766#define TCG_7_0_EDX_FEATURES 0
303752a9 767#define TCG_APM_FEATURES 0
28b8e4d0 768#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 769#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
770 /* missing:
771 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 772
07585923
RH		 773typedef enum FeatureWordType {
774 CPUID_FEATURE_WORD,
775 MSR_FEATURE_WORD,
776} FeatureWordType;
777
5ef57876 778typedef struct FeatureWordInfo {
07585923 779 FeatureWordType type;
2d5312da
EH		 780 /* feature flags names are taken from "Intel Processor Identification and
781 * the CPUID Instruction" and AMD's "CPUID Specification".
782 * In cases of disagreement between feature naming conventions,
783 * aliases may be added.
784 */
785 const char *feat_names[32];
07585923
RH		 786 union {
787 /* If type==CPUID_FEATURE_WORD */
788 struct {
789 uint32_t eax; /* Input EAX for CPUID */
790 bool needs_ecx; /* CPUID instruction uses ECX as input */
791 uint32_t ecx; /* Input ECX value for CPUID */
792 int reg; /* output register (R_* constant) */
793 } cpuid;
794 /* If type==MSR_FEATURE_WORD */
795 struct {
796 uint32_t index;
797 struct { /*CPUID that enumerate this MSR*/
798 FeatureWord cpuid_class;
799 uint32_t cpuid_flag;
800 } cpuid_dep;
801 } msr;
802 };
37ce3522 803 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 804 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 805 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 806 /* Features that shouldn't be auto-enabled by "-cpu host" */
807 uint32_t no_autoenable_flags;
5ef57876
EH		 808} FeatureWordInfo;
809
810static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 811 [FEAT_1_EDX] = {
07585923 812 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 813 .feat_names = {
814 "fpu", "vme", "de", "pse",
815 "tsc", "msr", "pae", "mce",
816 "cx8", "apic", NULL, "sep",
817 "mtrr", "pge", "mca", "cmov",
818 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
819 NULL, "ds" /* Intel dts */, "acpi", "mmx",
820 "fxsr", "sse", "sse2", "ss",
821 "ht" /* Intel htt */, "tm", "ia64", "pbe",
822 },
07585923 823 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 824 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 825 },
826 [FEAT_1_ECX] = {
07585923 827 .type = CPUID_FEATURE_WORD,
2d5312da 828 .feat_names = {
16d2fcaa 829 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 830 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 831 "tm2", "ssse3", "cid", NULL,
832 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 833 NULL, "pcid", "dca", "sse4.1",
834 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 835 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 836 "avx", "f16c", "rdrand", "hypervisor",
837 },
07585923 838 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 839 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 840 },
2d5312da
EH		 841 /* Feature names that are already defined on feature_name[] but
842 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
843 * names on feat_names below. They are copied automatically
844 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
845 */
bffd67b0 846 [FEAT_8000_0001_EDX] = {
07585923 847 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 848 .feat_names = {
849 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
850 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
851 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
852 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
853 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 854 "nx", NULL, "mmxext", NULL /* mmx */,
855 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
856 NULL, "lm", "3dnowext", "3dnow",
2d5312da 857 },
07585923 858 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 859 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 860 },
861 [FEAT_8000_0001_ECX] = {
07585923 862 .type = CPUID_FEATURE_WORD,
2d5312da 863 .feat_names = {
fc7dfd20 864 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 865 "cr8legacy", "abm", "sse4a", "misalignsse",
866 "3dnowprefetch", "osvw", "ibs", "xop",
867 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 868 "fma4", "tce", NULL, "nodeid-msr",
869 NULL, "tbm", "topoext", "perfctr-core",
870 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 871 NULL, NULL, NULL, NULL,
872 },
07585923 873 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 874 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 875 /*
876 * TOPOEXT is always allowed but can't be enabled blindly by
877 * "-cpu host", as it requires consistent cache topology info
878 * to be provided so it doesn't confuse guests.
879 */
880 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 881 },
89e49c8b 882 [FEAT_C000_0001_EDX] = {
07585923 883 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 884 .feat_names = {
885 NULL, NULL, "xstore", "xstore-en",
886 NULL, NULL, "xcrypt", "xcrypt-en",
887 "ace2", "ace2-en", "phe", "phe-en",
888 "pmm", "pmm-en", NULL, NULL,
889 NULL, NULL, NULL, NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 },
07585923 894 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 895 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 896 },
bffd67b0 897 [FEAT_KVM] = {
07585923 898 .type = CPUID_FEATURE_WORD,
2d5312da 899 .feat_names = {
fc7dfd20
EH		 900 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
901 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 902 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 903 NULL, NULL, NULL, NULL,
904 NULL, NULL, NULL, NULL,
905 NULL, NULL, NULL, NULL,
906 "kvmclock-stable-bit", NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 },
07585923 909 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 910 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 911 },
be777326 912 [FEAT_KVM_HINTS] = {
07585923 913 .type = CPUID_FEATURE_WORD,
be777326
WL		 914 .feat_names = {
915 "kvm-hint-dedicated", NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
07585923 924 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 925 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 926 /*
927 * KVM hints aren't auto-enabled by -cpu host, they need to be
928 * explicitly enabled in the command-line.
929 */
930 .no_autoenable_flags = ~0U,
be777326 931 },
c35bd19a 932 [FEAT_HYPERV_EAX] = {
07585923 933 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 934 .feat_names = {
935 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
936 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
937 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
938 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
939 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
940 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 941 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
942 NULL, NULL,
2d5312da
EH		 943 NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 },
07585923 948 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 949 },
950 [FEAT_HYPERV_EBX] = {
07585923 951 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 952 .feat_names = {
953 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
954 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
955 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
956 NULL /* hv_create_port */, NULL /* hv_connect_port */,
957 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
958 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
959 NULL, NULL,
960 NULL, NULL, NULL, NULL,
961 NULL, NULL, NULL, NULL,
962 NULL, NULL, NULL, NULL,
963 NULL, NULL, NULL, NULL,
964 },
07585923 965 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 966 },
967 [FEAT_HYPERV_EDX] = {
07585923 968 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 969 .feat_names = {
970 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
971 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
972 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
973 NULL, NULL,
974 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL,
980 },
07585923 981 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 982 },
a2b107db
VK		 983 [FEAT_HV_RECOMM_EAX] = {
984 .type = CPUID_FEATURE_WORD,
985 .feat_names = {
986 NULL /* hv_recommend_pv_as_switch */,
987 NULL /* hv_recommend_pv_tlbflush_local */,
988 NULL /* hv_recommend_pv_tlbflush_remote */,
989 NULL /* hv_recommend_msr_apic_access */,
990 NULL /* hv_recommend_msr_reset */,
991 NULL /* hv_recommend_relaxed_timing */,
992 NULL /* hv_recommend_dma_remapping */,
993 NULL /* hv_recommend_int_remapping */,
994 NULL /* hv_recommend_x2apic_msrs */,
995 NULL /* hv_recommend_autoeoi_deprecation */,
996 NULL /* hv_recommend_pv_ipi */,
997 NULL /* hv_recommend_ex_hypercalls */,
998 NULL /* hv_hypervisor_is_nested */,
999 NULL /* hv_recommend_int_mbec */,
1000 NULL /* hv_recommend_evmcs */,
1001 NULL,
1002 NULL, NULL, NULL, NULL,
1003 NULL, NULL, NULL, NULL,
1004 NULL, NULL, NULL, NULL,
1005 NULL, NULL, NULL, NULL,
1006 },
1007 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1008 },
1009 [FEAT_HV_NESTED_EAX] = {
1010 .type = CPUID_FEATURE_WORD,
1011 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1012 },
bffd67b0 1013 [FEAT_SVM] = {
07585923 1014 .type = CPUID_FEATURE_WORD,
2d5312da 1015 .feat_names = {
fc7dfd20
EH		 1016 "npt", "lbrv", "svm-lock", "nrip-save",
1017 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1018 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 1019 "pfthreshold", NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL,
1021 NULL, NULL, NULL, NULL,
1022 NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL,
1024 },
07585923 1025 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 1026 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 1027 },
1028 [FEAT_7_0_EBX] = {
07585923 1029 .type = CPUID_FEATURE_WORD,
2d5312da 1030 .feat_names = {
fc7dfd20 1031 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1032 "hle", "avx2", NULL, "smep",
1033 "bmi2", "erms", "invpcid", "rtm",
1034 NULL, NULL, "mpx", NULL,
1035 "avx512f", "avx512dq", "rdseed", "adx",
1036 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1037 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1038 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1039 },
07585923
RH		 1040 .cpuid = {
1041 .eax = 7,
1042 .needs_ecx = true, .ecx = 0,
1043 .reg = R_EBX,
1044 },
37ce3522 1045 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1046 },
f74eefe0 1047 [FEAT_7_0_ECX] = {
07585923 1048 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1049 .feat_names = {
1050 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1051 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1052 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1053 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1054 "la57", NULL, NULL, NULL,
2d5312da 1055 NULL, NULL, "rdpid", NULL,
24261de4 1056 NULL, "cldemote", NULL, "movdiri",
1c65775f 1057 "movdir64b", NULL, NULL, NULL,
2d5312da 1058 },
07585923
RH		 1059 .cpuid = {
1060 .eax = 7,
1061 .needs_ecx = true, .ecx = 0,
1062 .reg = R_ECX,
1063 },
f74eefe0
HH		 1064 .tcg_features = TCG_7_0_ECX_FEATURES,
1065 },
95ea69fb 1066 [FEAT_7_0_EDX] = {
07585923 1067 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1068 .feat_names = {
1069 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 NULL, NULL, NULL, NULL,
5131dc43 1073 NULL, NULL, "pconfig", NULL,
95ea69fb 1074 NULL, NULL, NULL, NULL,
0e891658 1075 NULL, NULL, "spec-ctrl", "stibp",
3fc7c731 1076 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1077 },
07585923
RH		 1078 .cpuid = {
1079 .eax = 7,
1080 .needs_ecx = true, .ecx = 0,
1081 .reg = R_EDX,
1082 },
95ea69fb 1083 .tcg_features = TCG_7_0_EDX_FEATURES,
3fc7c731 1084 .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
95ea69fb 1085 },
303752a9 1086 [FEAT_8000_0007_EDX] = {
07585923 1087 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1088 .feat_names = {
1089 NULL, NULL, NULL, NULL,
1090 NULL, NULL, NULL, NULL,
1091 "invtsc", NULL, NULL, NULL,
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 },
07585923 1098 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1099 .tcg_features = TCG_APM_FEATURES,
1100 .unmigratable_flags = CPUID_APM_INVTSC,
1101 },
1b3420e1 1102 [FEAT_8000_0008_EBX] = {
07585923 1103 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1104 .feat_names = {
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
59a80a19 1107 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1108 "ibpb", NULL, NULL, NULL,
1109 NULL, NULL, NULL, NULL,
1110 NULL, NULL, NULL, NULL,
254790a9 1111 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1112 NULL, NULL, NULL, NULL,
1113 },
07585923 1114 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1115 .tcg_features = 0,
1116 .unmigratable_flags = 0,
1117 },
0bb0b2d2 1118 [FEAT_XSAVE] = {
07585923 1119 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1120 .feat_names = {
1121 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL,
1126 NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL,
1128 NULL, NULL, NULL, NULL,
1129 },
07585923
RH		 1130 .cpuid = {
1131 .eax = 0xd,
1132 .needs_ecx = true, .ecx = 1,
1133 .reg = R_EAX,
1134 },
c9cfe8f9 1135 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1136 },
28b8e4d0 1137 [FEAT_6_EAX] = {
07585923 1138 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1139 .feat_names = {
1140 NULL, NULL, "arat", NULL,
1141 NULL, NULL, NULL, NULL,
1142 NULL, NULL, NULL, NULL,
1143 NULL, NULL, NULL, NULL,
1144 NULL, NULL, NULL, NULL,
1145 NULL, NULL, NULL, NULL,
1146 NULL, NULL, NULL, NULL,
1147 NULL, NULL, NULL, NULL,
1148 },
07585923 1149 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1150 .tcg_features = TCG_6_EAX_FEATURES,
1151 },
96193c22 1152 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1153 .type = CPUID_FEATURE_WORD,
1154 .cpuid = {
1155 .eax = 0xD,
1156 .needs_ecx = true, .ecx = 0,
1157 .reg = R_EAX,
1158 },
96193c22 1159 .tcg_features = ~0U,
6fb2fff7
EH		 1160 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1161 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1162 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1163 XSTATE_PKRU_MASK,
96193c22
EH		 1164 },
1165 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1166 .type = CPUID_FEATURE_WORD,
1167 .cpuid = {
1168 .eax = 0xD,
1169 .needs_ecx = true, .ecx = 0,
1170 .reg = R_EDX,
1171 },
96193c22
EH		 1172 .tcg_features = ~0U,
1173 },
d86f9636
RH		 1174 /*Below are MSR exposed features*/
1175 [FEAT_ARCH_CAPABILITIES] = {
1176 .type = MSR_FEATURE_WORD,
1177 .feat_names = {
1178 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1179 "ssb-no", NULL, NULL, NULL,
1180 NULL, NULL, NULL, NULL,
1181 NULL, NULL, NULL, NULL,
1182 NULL, NULL, NULL, NULL,
1183 NULL, NULL, NULL, NULL,
1184 NULL, NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 },
1187 .msr = {
1188 .index = MSR_IA32_ARCH_CAPABILITIES,
1189 .cpuid_dep = {
1190 FEAT_7_0_EDX,
1191 CPUID_7_0_EDX_ARCH_CAPABILITIES
1192 }
1193 },
1194 },
5ef57876
EH		 1195};
1196
8e8aba50
EH		 1197typedef struct X86RegisterInfo32 {
1198 /* Name of register */
1199 const char *name;
1200 /* QAPI enum value register */
1201 X86CPURegister32 qapi_enum;
1202} X86RegisterInfo32;
1203
1204#define REGISTER(reg) \
5d371f41 1205 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1206static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1207 REGISTER(EAX),
1208 REGISTER(ECX),
1209 REGISTER(EDX),
1210 REGISTER(EBX),
1211 REGISTER(ESP),
1212 REGISTER(EBP),
1213 REGISTER(ESI),
1214 REGISTER(EDI),
1215};
1216#undef REGISTER
1217
3f32bd21
RH		 1218typedef struct ExtSaveArea {
1219 uint32_t feature, bits;
1220 uint32_t offset, size;
1221} ExtSaveArea;
1222
1223static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1224 [XSTATE_FP_BIT] = {
1225 /* x87 FP state component is always enabled if XSAVE is supported */
1226 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1227 /* x87 state is in the legacy region of the XSAVE area */
1228 .offset = 0,
1229 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1230 },
1231 [XSTATE_SSE_BIT] = {
1232 /* SSE state component is always enabled if XSAVE is supported */
1233 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1234 /* SSE state is in the legacy region of the XSAVE area */
1235 .offset = 0,
1236 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1237 },
cfc3b074
PB		 1238 [XSTATE_YMM_BIT] =
1239 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1240 .offset = offsetof(X86XSaveArea, avx_state),
1241 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1242 [XSTATE_BNDREGS_BIT] =
1243 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1244 .offset = offsetof(X86XSaveArea, bndreg_state),
1245 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1246 [XSTATE_BNDCSR_BIT] =
1247 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1248 .offset = offsetof(X86XSaveArea, bndcsr_state),
1249 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1250 [XSTATE_OPMASK_BIT] =
1251 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1252 .offset = offsetof(X86XSaveArea, opmask_state),
1253 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1254 [XSTATE_ZMM_Hi256_BIT] =
1255 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1256 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1257 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1258 [XSTATE_Hi16_ZMM_BIT] =
1259 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1260 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1261 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1262 [XSTATE_PKRU_BIT] =
1263 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1264 .offset = offsetof(X86XSaveArea, pkru_state),
1265 .size = sizeof(XSavePKRU) },
2560f19f 1266};
8e8aba50 1267
1fda6198
EH		 1268static uint32_t xsave_area_size(uint64_t mask)
1269{
1270 int i;
e3c9022b 1271 uint64_t ret = 0;
1fda6198 1272
e3c9022b 1273 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1274 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1275 if ((mask >> i) & 1) {
1276 ret = MAX(ret, esa->offset + esa->size);
1277 }
1278 }
1279 return ret;
1280}
1281
d6dcc558
SAGDR		 1282static inline bool accel_uses_host_cpuid(void)
1283{
1284 return kvm_enabled() || hvf_enabled();
1285}
1286
96193c22
EH		 1287static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1288{
1289 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1290 cpu->env.features[FEAT_XSAVE_COMP_LO];
1291}
1292
8b4beddc
EH		 1293const char *get_register_name_32(unsigned int reg)
1294{
31ccdde2 1295 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1296 return NULL;
1297 }
8e8aba50 1298 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1299}
1300
84f1b92f
EH		 1301/*
1302 * Returns the set of feature flags that are supported and migratable by
1303 * QEMU, for a given FeatureWord.
1304 */
1305static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1306{
1307 FeatureWordInfo *wi = &feature_word_info[w];
1308 uint32_t r = 0;
1309 int i;
1310
1311 for (i = 0; i < 32; i++) {
1312 uint32_t f = 1U << i;
6fb2fff7
EH		 1313
1314 /* If the feature name is known, it is implicitly considered migratable,
1315 * unless it is explicitly set in unmigratable_flags */
1316 if ((wi->migratable_flags & f) ||
1317 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1318 r |= f;
84f1b92f 1319 }
84f1b92f
EH		 1320 }
1321 return r;
1322}
1323
bb44e0d1
JK		 1324void host_cpuid(uint32_t function, uint32_t count,
1325 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1326{
a1fd24af
AL		 1327 uint32_t vec[4];
1328
1329#ifdef __x86_64__
1330 asm volatile("cpuid"
1331 : "=a"(vec[0]), "=b"(vec[1]),
1332 "=c"(vec[2]), "=d"(vec[3])
1333 : "0"(function), "c"(count) : "cc");
c1f41226 1334#elif defined(__i386__)
a1fd24af
AL		 1335 asm volatile("pusha \n\t"
1336 "cpuid \n\t"
1337 "mov %%eax, 0(%2) \n\t"
1338 "mov %%ebx, 4(%2) \n\t"
1339 "mov %%ecx, 8(%2) \n\t"
1340 "mov %%edx, 12(%2) \n\t"
1341 "popa"
1342 : : "a"(function), "c"(count), "S"(vec)
1343 : "memory", "cc");
c1f41226
EH		 1344#else
1345 abort();
a1fd24af
AL		 1346#endif
1347
bdde476a 1348 if (eax)
a1fd24af 1349 *eax = vec[0];
bdde476a 1350 if (ebx)
a1fd24af 1351 *ebx = vec[1];
bdde476a 1352 if (ecx)
a1fd24af 1353 *ecx = vec[2];
bdde476a 1354 if (edx)
a1fd24af 1355 *edx = vec[3];
bdde476a 1356}
c6dc6f63 1357
20271d48
EH		 1358void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1359{
1360 uint32_t eax, ebx, ecx, edx;
1361
1362 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1363 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1364
1365 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1366 if (family) {
1367 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1368 }
1369 if (model) {
1370 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1371 }
1372 if (stepping) {
1373 *stepping = eax & 0x0F;
1374 }
1375}
1376
d940ee9b
EH		 1377/* CPU class name definitions: */
1378
d940ee9b
EH		 1379/* Return type name for a given CPU model name
1380 * Caller is responsible for freeing the returned string.
1381 */
1382static char *x86_cpu_type_name(const char *model_name)
1383{
1384 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1385}
1386
500050d1
AF		 1387static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1388{
d940ee9b 1389 ObjectClass *oc;
99193d8f 1390 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1391 oc = object_class_by_name(typename);
1392 g_free(typename);
1393 return oc;
500050d1
AF		 1394}
1395
104494ea
IM		 1396static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1397{
1398 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1399 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1400 return g_strndup(class_name,
1401 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1402}
1403
d940ee9b 1404struct X86CPUDefinition {
c6dc6f63
AP		 1405 const char *name;
1406 uint32_t level;
90e4b0c3 1407 uint32_t xlevel;
99b88a17
IM		 1408 /* vendor is zero-terminated, 12 character ASCII string */
1409 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1410 int family;
1411 int model;
1412 int stepping;
0514ef2f 1413 FeatureWordArray features;
807e9869 1414 const char *model_id;
6aaeb054 1415 CPUCaches *cache_info;
d940ee9b 1416};
c6dc6f63 1417
fe52acd2 1418static CPUCaches epyc_cache_info = {
a9f27ea9 1419 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1420 .type = DATA_CACHE,
fe52acd2
BM		 1421 .level = 1,
1422 .size = 32 * KiB,
1423 .line_size = 64,
1424 .associativity = 8,
1425 .partitions = 1,
1426 .sets = 64,
1427 .lines_per_tag = 1,
1428 .self_init = 1,
1429 .no_invd_sharing = true,
1430 },
a9f27ea9 1431 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1432 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1433 .level = 1,
1434 .size = 64 * KiB,
1435 .line_size = 64,
1436 .associativity = 4,
1437 .partitions = 1,
1438 .sets = 256,
1439 .lines_per_tag = 1,
1440 .self_init = 1,
1441 .no_invd_sharing = true,
1442 },
a9f27ea9 1443 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1444 .type = UNIFIED_CACHE,
1445 .level = 2,
1446 .size = 512 * KiB,
1447 .line_size = 64,
1448 .associativity = 8,
1449 .partitions = 1,
1450 .sets = 1024,
1451 .lines_per_tag = 1,
1452 },
a9f27ea9 1453 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1454 .type = UNIFIED_CACHE,
1455 .level = 3,
1456 .size = 8 * MiB,
1457 .line_size = 64,
1458 .associativity = 16,
1459 .partitions = 1,
1460 .sets = 8192,
1461 .lines_per_tag = 1,
1462 .self_init = true,
1463 .inclusive = true,
1464 .complex_indexing = true,
1465 },
1466};
1467
9576de75 1468static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1469 {
1470 .name = "qemu64",
3046bb5d 1471 .level = 0xd,
99b88a17 1472 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1473 .family = 6,
f8e6a11a 1474 .model = 6,
c6dc6f63 1475 .stepping = 3,
0514ef2f 1476 .features[FEAT_1_EDX] =
27861ecc 1477 PPRO_FEATURES |
c6dc6f63 1478 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1479 CPUID_PSE36,
0514ef2f 1480 .features[FEAT_1_ECX] =
6aa91e4a 1481 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1482 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1483 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1484 .features[FEAT_8000_0001_ECX] =
71195672 1485 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1486 .xlevel = 0x8000000A,
9cf2cc3d 1487 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1488 },
1489 {
1490 .name = "phenom",
1491 .level = 5,
99b88a17 1492 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1493 .family = 16,
1494 .model = 2,
1495 .stepping = 3,
b9fc20bc 1496 /* Missing: CPUID_HT */
0514ef2f 1497 .features[FEAT_1_EDX] =
27861ecc 1498 PPRO_FEATURES |
c6dc6f63 1499 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1500 CPUID_PSE36 | CPUID_VME,
0514ef2f 1501 .features[FEAT_1_ECX] =
27861ecc 1502 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1503 CPUID_EXT_POPCNT,
0514ef2f 1504 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1505 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1506 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1507 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1508 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1509 CPUID_EXT3_CR8LEG,
1510 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1511 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1512 .features[FEAT_8000_0001_ECX] =
27861ecc 1513 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1514 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1515 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1516 .features[FEAT_SVM] =
b9fc20bc 1517 CPUID_SVM_NPT,
c6dc6f63
AP		 1518 .xlevel = 0x8000001A,
1519 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1520 },
1521 {
1522 .name = "core2duo",
1523 .level = 10,
99b88a17 1524 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1525 .family = 6,
1526 .model = 15,
1527 .stepping = 11,
b9fc20bc 1528 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1529 .features[FEAT_1_EDX] =
27861ecc 1530 PPRO_FEATURES |
c6dc6f63 1531 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1532 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1533 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1534 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1535 .features[FEAT_1_ECX] =
27861ecc 1536 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1537 CPUID_EXT_CX16,
0514ef2f 1538 .features[FEAT_8000_0001_EDX] =
27861ecc 1539 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1540 .features[FEAT_8000_0001_ECX] =
27861ecc 1541 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1542 .xlevel = 0x80000008,
1543 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1544 },
1545 {
1546 .name = "kvm64",
3046bb5d 1547 .level = 0xd,
99b88a17 1548 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1549 .family = 15,
1550 .model = 6,
1551 .stepping = 1,
b3a4f0b1 1552 /* Missing: CPUID_HT */
0514ef2f 1553 .features[FEAT_1_EDX] =
b3a4f0b1 1554 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1555 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1556 CPUID_PSE36,
1557 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1558 .features[FEAT_1_ECX] =
27861ecc 1559 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1560 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1561 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1562 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1563 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1564 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1565 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1566 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1567 .features[FEAT_8000_0001_ECX] =
27861ecc 1568 0,
c6dc6f63
AP		 1569 .xlevel = 0x80000008,
1570 .model_id = "Common KVM processor"
1571 },
c6dc6f63
AP		 1572 {
1573 .name = "qemu32",
1574 .level = 4,
99b88a17 1575 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1576 .family = 6,
f8e6a11a 1577 .model = 6,
c6dc6f63 1578 .stepping = 3,
0514ef2f 1579 .features[FEAT_1_EDX] =
27861ecc 1580 PPRO_FEATURES,
0514ef2f 1581 .features[FEAT_1_ECX] =
6aa91e4a 1582 CPUID_EXT_SSE3,
58012d66 1583 .xlevel = 0x80000004,
9cf2cc3d 1584 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1585 },
eafaf1e5
AP		 1586 {
1587 .name = "kvm32",
1588 .level = 5,
99b88a17 1589 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1590 .family = 15,
1591 .model = 6,
1592 .stepping = 1,
0514ef2f 1593 .features[FEAT_1_EDX] =
b3a4f0b1 1594 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1595 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1596 .features[FEAT_1_ECX] =
27861ecc 1597 CPUID_EXT_SSE3,
0514ef2f 1598 .features[FEAT_8000_0001_ECX] =
27861ecc 1599 0,
eafaf1e5
AP		 1600 .xlevel = 0x80000008,
1601 .model_id = "Common 32-bit KVM processor"
1602 },
c6dc6f63
AP		 1603 {
1604 .name = "coreduo",
1605 .level = 10,
99b88a17 1606 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1607 .family = 6,
1608 .model = 14,
1609 .stepping = 8,
b9fc20bc 1610 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1611 .features[FEAT_1_EDX] =
27861ecc 1612 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1614 CPUID_SS,
1615 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1616 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1617 .features[FEAT_1_ECX] =
e93abc14 1618 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1619 .features[FEAT_8000_0001_EDX] =
27861ecc 1620 CPUID_EXT2_NX,
c6dc6f63
AP		 1621 .xlevel = 0x80000008,
1622 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1623 },
1624 {
1625 .name = "486",
58012d66 1626 .level = 1,
99b88a17 1627 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1628 .family = 4,
b2a856d9 1629 .model = 8,
c6dc6f63 1630 .stepping = 0,
0514ef2f 1631 .features[FEAT_1_EDX] =
27861ecc 1632 I486_FEATURES,
c6dc6f63 1633 .xlevel = 0,
807e9869 1634 .model_id = "",
c6dc6f63
AP		 1635 },
1636 {
1637 .name = "pentium",
1638 .level = 1,
99b88a17 1639 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1640 .family = 5,
1641 .model = 4,
1642 .stepping = 3,
0514ef2f 1643 .features[FEAT_1_EDX] =
27861ecc 1644 PENTIUM_FEATURES,
c6dc6f63 1645 .xlevel = 0,
807e9869 1646 .model_id = "",
c6dc6f63
AP		 1647 },
1648 {
1649 .name = "pentium2",
1650 .level = 2,
99b88a17 1651 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1652 .family = 6,
1653 .model = 5,
1654 .stepping = 2,
0514ef2f 1655 .features[FEAT_1_EDX] =
27861ecc 1656 PENTIUM2_FEATURES,
c6dc6f63 1657 .xlevel = 0,
807e9869 1658 .model_id = "",
c6dc6f63
AP		 1659 },
1660 {
1661 .name = "pentium3",
3046bb5d 1662 .level = 3,
99b88a17 1663 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1664 .family = 6,
1665 .model = 7,
1666 .stepping = 3,
0514ef2f 1667 .features[FEAT_1_EDX] =
27861ecc 1668 PENTIUM3_FEATURES,
c6dc6f63 1669 .xlevel = 0,
807e9869 1670 .model_id = "",
c6dc6f63
AP		 1671 },
1672 {
1673 .name = "athlon",
1674 .level = 2,
99b88a17 1675 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1676 .family = 6,
1677 .model = 2,
1678 .stepping = 3,
0514ef2f 1679 .features[FEAT_1_EDX] =
27861ecc 1680 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1681 CPUID_MCA,
0514ef2f 1682 .features[FEAT_8000_0001_EDX] =
60032ac0 1683 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1684 .xlevel = 0x80000008,
9cf2cc3d 1685 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1686 },
1687 {
1688 .name = "n270",
3046bb5d 1689 .level = 10,
99b88a17 1690 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1691 .family = 6,
1692 .model = 28,
1693 .stepping = 2,
b9fc20bc 1694 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1695 .features[FEAT_1_EDX] =
27861ecc 1696 PPRO_FEATURES |
b9fc20bc
EH		 1697 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1698 CPUID_ACPI | CPUID_SS,
c6dc6f63 1699 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1700 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1701 * CPUID_EXT_XTPR */
0514ef2f 1702 .features[FEAT_1_ECX] =
27861ecc 1703 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1704 CPUID_EXT_MOVBE,
0514ef2f 1705 .features[FEAT_8000_0001_EDX] =
60032ac0 1706 CPUID_EXT2_NX,
0514ef2f 1707 .features[FEAT_8000_0001_ECX] =
27861ecc 1708 CPUID_EXT3_LAHF_LM,
3046bb5d 1709 .xlevel = 0x80000008,
c6dc6f63
AP		 1710 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1711 },
3eca4642
EH		 1712 {
1713 .name = "Conroe",
3046bb5d 1714 .level = 10,
99b88a17 1715 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1716 .family = 6,
ffce9ebb 1717 .model = 15,
3eca4642 1718 .stepping = 3,
0514ef2f 1719 .features[FEAT_1_EDX] =
b3a4f0b1 1720 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1721 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1722 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1723 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1724 CPUID_DE | CPUID_FP87,
0514ef2f 1725 .features[FEAT_1_ECX] =
27861ecc 1726 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1727 .features[FEAT_8000_0001_EDX] =
27861ecc 1728 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1729 .features[FEAT_8000_0001_ECX] =
27861ecc 1730 CPUID_EXT3_LAHF_LM,
3046bb5d 1731 .xlevel = 0x80000008,
3eca4642
EH		 1732 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1733 },
1734 {
1735 .name = "Penryn",
3046bb5d 1736 .level = 10,
99b88a17 1737 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1738 .family = 6,
ffce9ebb 1739 .model = 23,
3eca4642 1740 .stepping = 3,
0514ef2f 1741 .features[FEAT_1_EDX] =
b3a4f0b1 1742 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1743 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1744 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1745 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1746 CPUID_DE | CPUID_FP87,
0514ef2f 1747 .features[FEAT_1_ECX] =
27861ecc 1748 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1749 CPUID_EXT_SSE3,
0514ef2f 1750 .features[FEAT_8000_0001_EDX] =
27861ecc 1751 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1752 .features[FEAT_8000_0001_ECX] =
27861ecc 1753 CPUID_EXT3_LAHF_LM,
3046bb5d 1754 .xlevel = 0x80000008,
3eca4642
EH		 1755 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1756 },
1757 {
1758 .name = "Nehalem",
3046bb5d 1759 .level = 11,
99b88a17 1760 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1761 .family = 6,
ffce9ebb 1762 .model = 26,
3eca4642 1763 .stepping = 3,
0514ef2f 1764 .features[FEAT_1_EDX] =
b3a4f0b1 1765 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1766 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1767 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1768 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1769 CPUID_DE | CPUID_FP87,
0514ef2f 1770 .features[FEAT_1_ECX] =
27861ecc 1771 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1772 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1773 .features[FEAT_8000_0001_EDX] =
27861ecc 1774 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1775 .features[FEAT_8000_0001_ECX] =
27861ecc 1776 CPUID_EXT3_LAHF_LM,
3046bb5d 1777 .xlevel = 0x80000008,
3eca4642
EH		 1778 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1779 },
ac96c413
EH		 1780 {
1781 .name = "Nehalem-IBRS",
1782 .level = 11,
1783 .vendor = CPUID_VENDOR_INTEL,
1784 .family = 6,
1785 .model = 26,
1786 .stepping = 3,
1787 .features[FEAT_1_EDX] =
1788 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1789 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1790 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1791 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1792 CPUID_DE | CPUID_FP87,
1793 .features[FEAT_1_ECX] =
1794 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1795 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1796 .features[FEAT_7_0_EDX] =
1797 CPUID_7_0_EDX_SPEC_CTRL,
1798 .features[FEAT_8000_0001_EDX] =
1799 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1800 .features[FEAT_8000_0001_ECX] =
1801 CPUID_EXT3_LAHF_LM,
1802 .xlevel = 0x80000008,
1803 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1804 },
3eca4642
EH		 1805 {
1806 .name = "Westmere",
1807 .level = 11,
99b88a17 1808 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1809 .family = 6,
1810 .model = 44,
1811 .stepping = 1,
0514ef2f 1812 .features[FEAT_1_EDX] =
b3a4f0b1 1813 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1817 CPUID_DE | CPUID_FP87,
0514ef2f 1818 .features[FEAT_1_ECX] =
27861ecc 1819 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1820 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1821 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1822 .features[FEAT_8000_0001_EDX] =
27861ecc 1823 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1824 .features[FEAT_8000_0001_ECX] =
27861ecc 1825 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1826 .features[FEAT_6_EAX] =
1827 CPUID_6_EAX_ARAT,
3046bb5d 1828 .xlevel = 0x80000008,
3eca4642
EH		 1829 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1830 },
ac96c413
EH		 1831 {
1832 .name = "Westmere-IBRS",
1833 .level = 11,
1834 .vendor = CPUID_VENDOR_INTEL,
1835 .family = 6,
1836 .model = 44,
1837 .stepping = 1,
1838 .features[FEAT_1_EDX] =
1839 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1840 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1841 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1842 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1843 CPUID_DE | CPUID_FP87,
1844 .features[FEAT_1_ECX] =
1845 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1846 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1847 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1848 .features[FEAT_8000_0001_EDX] =
1849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1850 .features[FEAT_8000_0001_ECX] =
1851 CPUID_EXT3_LAHF_LM,
1852 .features[FEAT_7_0_EDX] =
1853 CPUID_7_0_EDX_SPEC_CTRL,
1854 .features[FEAT_6_EAX] =
1855 CPUID_6_EAX_ARAT,
1856 .xlevel = 0x80000008,
1857 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1858 },
3eca4642
EH		 1859 {
1860 .name = "SandyBridge",
1861 .level = 0xd,
99b88a17 1862 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1863 .family = 6,
1864 .model = 42,
1865 .stepping = 1,
0514ef2f 1866 .features[FEAT_1_EDX] =
b3a4f0b1 1867 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1868 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1869 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1870 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1871 CPUID_DE | CPUID_FP87,
0514ef2f 1872 .features[FEAT_1_ECX] =
27861ecc 1873 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1874 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1875 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1876 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1877 CPUID_EXT_SSE3,
0514ef2f 1878 .features[FEAT_8000_0001_EDX] =
27861ecc 1879 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1880 CPUID_EXT2_SYSCALL,
0514ef2f 1881 .features[FEAT_8000_0001_ECX] =
27861ecc 1882 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1883 .features[FEAT_XSAVE] =
1884 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1885 .features[FEAT_6_EAX] =
1886 CPUID_6_EAX_ARAT,
3046bb5d 1887 .xlevel = 0x80000008,
3eca4642
EH		 1888 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1889 },
ac96c413
EH		 1890 {
1891 .name = "SandyBridge-IBRS",
1892 .level = 0xd,
1893 .vendor = CPUID_VENDOR_INTEL,
1894 .family = 6,
1895 .model = 42,
1896 .stepping = 1,
1897 .features[FEAT_1_EDX] =
1898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1902 CPUID_DE | CPUID_FP87,
1903 .features[FEAT_1_ECX] =
1904 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1905 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1906 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1907 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1908 CPUID_EXT_SSE3,
1909 .features[FEAT_8000_0001_EDX] =
1910 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1911 CPUID_EXT2_SYSCALL,
1912 .features[FEAT_8000_0001_ECX] =
1913 CPUID_EXT3_LAHF_LM,
1914 .features[FEAT_7_0_EDX] =
1915 CPUID_7_0_EDX_SPEC_CTRL,
1916 .features[FEAT_XSAVE] =
1917 CPUID_XSAVE_XSAVEOPT,
1918 .features[FEAT_6_EAX] =
1919 CPUID_6_EAX_ARAT,
1920 .xlevel = 0x80000008,
1921 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1922 },
2f9ac42a
PB		 1923 {
1924 .name = "IvyBridge",
1925 .level = 0xd,
1926 .vendor = CPUID_VENDOR_INTEL,
1927 .family = 6,
1928 .model = 58,
1929 .stepping = 9,
1930 .features[FEAT_1_EDX] =
1931 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1932 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1933 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1934 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1935 CPUID_DE | CPUID_FP87,
1936 .features[FEAT_1_ECX] =
1937 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1938 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1939 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1940 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1941 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1942 .features[FEAT_7_0_EBX] =
1943 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1944 CPUID_7_0_EBX_ERMS,
1945 .features[FEAT_8000_0001_EDX] =
1946 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1947 CPUID_EXT2_SYSCALL,
1948 .features[FEAT_8000_0001_ECX] =
1949 CPUID_EXT3_LAHF_LM,
1950 .features[FEAT_XSAVE] =
1951 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1952 .features[FEAT_6_EAX] =
1953 CPUID_6_EAX_ARAT,
3046bb5d 1954 .xlevel = 0x80000008,
2f9ac42a
PB		 1955 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1956 },
ac96c413
EH		 1957 {
1958 .name = "IvyBridge-IBRS",
1959 .level = 0xd,
1960 .vendor = CPUID_VENDOR_INTEL,
1961 .family = 6,
1962 .model = 58,
1963 .stepping = 9,
1964 .features[FEAT_1_EDX] =
1965 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1966 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1967 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1968 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1969 CPUID_DE | CPUID_FP87,
1970 .features[FEAT_1_ECX] =
1971 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1972 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1973 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1974 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1975 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1976 .features[FEAT_7_0_EBX] =
1977 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1978 CPUID_7_0_EBX_ERMS,
1979 .features[FEAT_8000_0001_EDX] =
1980 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1981 CPUID_EXT2_SYSCALL,
1982 .features[FEAT_8000_0001_ECX] =
1983 CPUID_EXT3_LAHF_LM,
1984 .features[FEAT_7_0_EDX] =
1985 CPUID_7_0_EDX_SPEC_CTRL,
1986 .features[FEAT_XSAVE] =
1987 CPUID_XSAVE_XSAVEOPT,
1988 .features[FEAT_6_EAX] =
1989 CPUID_6_EAX_ARAT,
1990 .xlevel = 0x80000008,
1991 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1992 },
37507094 1993 {
a356850b
EH		 1994 .name = "Haswell-noTSX",
1995 .level = 0xd,
1996 .vendor = CPUID_VENDOR_INTEL,
1997 .family = 6,
1998 .model = 60,
1999 .stepping = 1,
2000 .features[FEAT_1_EDX] =
2001 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2002 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2003 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2004 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2005 CPUID_DE | CPUID_FP87,
2006 .features[FEAT_1_ECX] =
2007 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2008 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2009 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2010 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2011 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2012 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2013 .features[FEAT_8000_0001_EDX] =
2014 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2015 CPUID_EXT2_SYSCALL,
2016 .features[FEAT_8000_0001_ECX] =
becb6667 2017 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 2018 .features[FEAT_7_0_EBX] =
2019 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2020 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2021 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2022 .features[FEAT_XSAVE] =
2023 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2024 .features[FEAT_6_EAX] =
2025 CPUID_6_EAX_ARAT,
3046bb5d 2026 .xlevel = 0x80000008,
a356850b 2027 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 2028 },
2029 {
2030 .name = "Haswell-noTSX-IBRS",
2031 .level = 0xd,
2032 .vendor = CPUID_VENDOR_INTEL,
2033 .family = 6,
2034 .model = 60,
2035 .stepping = 1,
2036 .features[FEAT_1_EDX] =
2037 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2041 CPUID_DE | CPUID_FP87,
2042 .features[FEAT_1_ECX] =
2043 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2044 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2045 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2046 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2047 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2048 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2049 .features[FEAT_8000_0001_EDX] =
2050 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2051 CPUID_EXT2_SYSCALL,
2052 .features[FEAT_8000_0001_ECX] =
2053 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2054 .features[FEAT_7_0_EDX] =
2055 CPUID_7_0_EDX_SPEC_CTRL,
2056 .features[FEAT_7_0_EBX] =
2057 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2058 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2059 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2060 .features[FEAT_XSAVE] =
2061 CPUID_XSAVE_XSAVEOPT,
2062 .features[FEAT_6_EAX] =
2063 CPUID_6_EAX_ARAT,
2064 .xlevel = 0x80000008,
2065 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2066 },
2067 {
37507094
EH		 2068 .name = "Haswell",
2069 .level = 0xd,
99b88a17 2070 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2071 .family = 6,
2072 .model = 60,
ec56a4a7 2073 .stepping = 4,
0514ef2f 2074 .features[FEAT_1_EDX] =
b3a4f0b1 2075 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2076 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2077 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2078 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2079 CPUID_DE | CPUID_FP87,
0514ef2f 2080 .features[FEAT_1_ECX] =
27861ecc 2081 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2082 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2083 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2084 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2085 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2086 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2087 .features[FEAT_8000_0001_EDX] =
27861ecc 2088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2089 CPUID_EXT2_SYSCALL,
0514ef2f 2090 .features[FEAT_8000_0001_ECX] =
becb6667 2091 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2092 .features[FEAT_7_0_EBX] =
27861ecc 2093 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2094 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2095 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2096 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2097 .features[FEAT_XSAVE] =
2098 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2099 .features[FEAT_6_EAX] =
2100 CPUID_6_EAX_ARAT,
3046bb5d 2101 .xlevel = 0x80000008,
37507094
EH		 2102 .model_id = "Intel Core Processor (Haswell)",
2103 },
ac96c413
EH		 2104 {
2105 .name = "Haswell-IBRS",
2106 .level = 0xd,
2107 .vendor = CPUID_VENDOR_INTEL,
2108 .family = 6,
2109 .model = 60,
2110 .stepping = 4,
2111 .features[FEAT_1_EDX] =
2112 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2113 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2114 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2115 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2116 CPUID_DE | CPUID_FP87,
2117 .features[FEAT_1_ECX] =
2118 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2119 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2120 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2121 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2122 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2123 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2124 .features[FEAT_8000_0001_EDX] =
2125 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2126 CPUID_EXT2_SYSCALL,
2127 .features[FEAT_8000_0001_ECX] =
2128 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2129 .features[FEAT_7_0_EDX] =
2130 CPUID_7_0_EDX_SPEC_CTRL,
2131 .features[FEAT_7_0_EBX] =
2132 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2133 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2134 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2135 CPUID_7_0_EBX_RTM,
2136 .features[FEAT_XSAVE] =
2137 CPUID_XSAVE_XSAVEOPT,
2138 .features[FEAT_6_EAX] =
2139 CPUID_6_EAX_ARAT,
2140 .xlevel = 0x80000008,
2141 .model_id = "Intel Core Processor (Haswell, IBRS)",
2142 },
a356850b
EH		 2143 {
2144 .name = "Broadwell-noTSX",
2145 .level = 0xd,
2146 .vendor = CPUID_VENDOR_INTEL,
2147 .family = 6,
2148 .model = 61,
2149 .stepping = 2,
2150 .features[FEAT_1_EDX] =
2151 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2152 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2153 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2154 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2155 CPUID_DE | CPUID_FP87,
2156 .features[FEAT_1_ECX] =
2157 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2158 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2159 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2160 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2161 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2162 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2163 .features[FEAT_8000_0001_EDX] =
2164 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2165 CPUID_EXT2_SYSCALL,
2166 .features[FEAT_8000_0001_ECX] =
becb6667 2167 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2168 .features[FEAT_7_0_EBX] =
2169 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2170 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2171 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2172 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2173 CPUID_7_0_EBX_SMAP,
2174 .features[FEAT_XSAVE] =
2175 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2176 .features[FEAT_6_EAX] =
2177 CPUID_6_EAX_ARAT,
3046bb5d 2178 .xlevel = 0x80000008,
a356850b
EH		 2179 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2180 },
ac96c413
EH		 2181 {
2182 .name = "Broadwell-noTSX-IBRS",
2183 .level = 0xd,
2184 .vendor = CPUID_VENDOR_INTEL,
2185 .family = 6,
2186 .model = 61,
2187 .stepping = 2,
2188 .features[FEAT_1_EDX] =
2189 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2190 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2191 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2192 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2193 CPUID_DE | CPUID_FP87,
2194 .features[FEAT_1_ECX] =
2195 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2196 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2197 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2198 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2199 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2200 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2201 .features[FEAT_8000_0001_EDX] =
2202 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2203 CPUID_EXT2_SYSCALL,
2204 .features[FEAT_8000_0001_ECX] =
2205 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2206 .features[FEAT_7_0_EDX] =
2207 CPUID_7_0_EDX_SPEC_CTRL,
2208 .features[FEAT_7_0_EBX] =
2209 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2210 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2211 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2212 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2213 CPUID_7_0_EBX_SMAP,
2214 .features[FEAT_XSAVE] =
2215 CPUID_XSAVE_XSAVEOPT,
2216 .features[FEAT_6_EAX] =
2217 CPUID_6_EAX_ARAT,
2218 .xlevel = 0x80000008,
2219 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2220 },
ece01354
EH		 2221 {
2222 .name = "Broadwell",
2223 .level = 0xd,
2224 .vendor = CPUID_VENDOR_INTEL,
2225 .family = 6,
2226 .model = 61,
2227 .stepping = 2,
2228 .features[FEAT_1_EDX] =
b3a4f0b1 2229 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2230 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2231 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2232 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2233 CPUID_DE | CPUID_FP87,
2234 .features[FEAT_1_ECX] =
2235 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2236 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2237 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2238 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2239 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2240 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2241 .features[FEAT_8000_0001_EDX] =
2242 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2243 CPUID_EXT2_SYSCALL,
2244 .features[FEAT_8000_0001_ECX] =
becb6667 2245 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2246 .features[FEAT_7_0_EBX] =
2247 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2248 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2249 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2250 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2251 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2252 .features[FEAT_XSAVE] =
2253 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2254 .features[FEAT_6_EAX] =
2255 CPUID_6_EAX_ARAT,
3046bb5d 2256 .xlevel = 0x80000008,
ece01354
EH		 2257 .model_id = "Intel Core Processor (Broadwell)",
2258 },
ac96c413
EH		 2259 {
2260 .name = "Broadwell-IBRS",
2261 .level = 0xd,
2262 .vendor = CPUID_VENDOR_INTEL,
2263 .family = 6,
2264 .model = 61,
2265 .stepping = 2,
2266 .features[FEAT_1_EDX] =
2267 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2268 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2269 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2270 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2271 CPUID_DE | CPUID_FP87,
2272 .features[FEAT_1_ECX] =
2273 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2274 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2275 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2276 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2277 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2278 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2279 .features[FEAT_8000_0001_EDX] =
2280 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2281 CPUID_EXT2_SYSCALL,
2282 .features[FEAT_8000_0001_ECX] =
2283 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2284 .features[FEAT_7_0_EDX] =
2285 CPUID_7_0_EDX_SPEC_CTRL,
2286 .features[FEAT_7_0_EBX] =
2287 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2288 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2289 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2290 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2291 CPUID_7_0_EBX_SMAP,
2292 .features[FEAT_XSAVE] =
2293 CPUID_XSAVE_XSAVEOPT,
2294 .features[FEAT_6_EAX] =
2295 CPUID_6_EAX_ARAT,
2296 .xlevel = 0x80000008,
2297 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2298 },
f6f949e9
EH		 2299 {
2300 .name = "Skylake-Client",
2301 .level = 0xd,
2302 .vendor = CPUID_VENDOR_INTEL,
2303 .family = 6,
2304 .model = 94,
2305 .stepping = 3,
2306 .features[FEAT_1_EDX] =
2307 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2308 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2309 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2310 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2311 CPUID_DE | CPUID_FP87,
2312 .features[FEAT_1_ECX] =
2313 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2314 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2315 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2316 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2317 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2318 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2319 .features[FEAT_8000_0001_EDX] =
2320 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2321 CPUID_EXT2_SYSCALL,
2322 .features[FEAT_8000_0001_ECX] =
2323 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2324 .features[FEAT_7_0_EBX] =
2325 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2326 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2327 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2328 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2329 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2330 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2331 * including v4.1 to v4.12).
f6f949e9
EH		 2332 * KVM doesn't yet expose any XSAVES state save component,
2333 * and the only one defined in Skylake (processor tracing)
2334 * probably will block migration anyway.
2335 */
2336 .features[FEAT_XSAVE] =
2337 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2338 CPUID_XSAVE_XGETBV1,
2339 .features[FEAT_6_EAX] =
2340 CPUID_6_EAX_ARAT,
2341 .xlevel = 0x80000008,
2342 .model_id = "Intel Core Processor (Skylake)",
2343 },
ac96c413
EH		 2344 {
2345 .name = "Skylake-Client-IBRS",
2346 .level = 0xd,
2347 .vendor = CPUID_VENDOR_INTEL,
2348 .family = 6,
2349 .model = 94,
2350 .stepping = 3,
2351 .features[FEAT_1_EDX] =
2352 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2353 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2354 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2355 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2356 CPUID_DE | CPUID_FP87,
2357 .features[FEAT_1_ECX] =
2358 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2359 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2360 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2361 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2362 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2363 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2364 .features[FEAT_8000_0001_EDX] =
2365 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2366 CPUID_EXT2_SYSCALL,
2367 .features[FEAT_8000_0001_ECX] =
2368 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2369 .features[FEAT_7_0_EDX] =
2370 CPUID_7_0_EDX_SPEC_CTRL,
2371 .features[FEAT_7_0_EBX] =
2372 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2373 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2374 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2375 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2376 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
2377 /* Missing: XSAVES (not supported by some Linux versions,
2378 * including v4.1 to v4.12).
2379 * KVM doesn't yet expose any XSAVES state save component,
2380 * and the only one defined in Skylake (processor tracing)
2381 * probably will block migration anyway.
2382 */
2383 .features[FEAT_XSAVE] =
2384 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2385 CPUID_XSAVE_XGETBV1,
2386 .features[FEAT_6_EAX] =
2387 CPUID_6_EAX_ARAT,
2388 .xlevel = 0x80000008,
2389 .model_id = "Intel Core Processor (Skylake, IBRS)",
2390 },
53f9a6f4
BF		 2391 {
2392 .name = "Skylake-Server",
2393 .level = 0xd,
2394 .vendor = CPUID_VENDOR_INTEL,
2395 .family = 6,
2396 .model = 85,
2397 .stepping = 4,
2398 .features[FEAT_1_EDX] =
2399 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2400 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2401 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2402 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2403 CPUID_DE | CPUID_FP87,
2404 .features[FEAT_1_ECX] =
2405 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2406 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2407 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2408 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2409 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2410 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2411 .features[FEAT_8000_0001_EDX] =
2412 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2413 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2414 .features[FEAT_8000_0001_ECX] =
2415 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2416 .features[FEAT_7_0_EBX] =
2417 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2418 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2419 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2420 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2421 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2422 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2423 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2424 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2425 .features[FEAT_7_0_ECX] =
2426 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2427 /* Missing: XSAVES (not supported by some Linux versions,
2428 * including v4.1 to v4.12).
2429 * KVM doesn't yet expose any XSAVES state save component,
2430 * and the only one defined in Skylake (processor tracing)
2431 * probably will block migration anyway.
2432 */
2433 .features[FEAT_XSAVE] =
2434 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2435 CPUID_XSAVE_XGETBV1,
2436 .features[FEAT_6_EAX] =
2437 CPUID_6_EAX_ARAT,
2438 .xlevel = 0x80000008,
2439 .model_id = "Intel Xeon Processor (Skylake)",
2440 },
ac96c413
EH		 2441 {
2442 .name = "Skylake-Server-IBRS",
2443 .level = 0xd,
2444 .vendor = CPUID_VENDOR_INTEL,
2445 .family = 6,
2446 .model = 85,
2447 .stepping = 4,
2448 .features[FEAT_1_EDX] =
2449 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2450 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2451 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2452 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2453 CPUID_DE | CPUID_FP87,
2454 .features[FEAT_1_ECX] =
2455 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2456 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2457 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2458 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2459 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2460 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2461 .features[FEAT_8000_0001_EDX] =
2462 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2463 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2464 .features[FEAT_8000_0001_ECX] =
2465 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2466 .features[FEAT_7_0_EDX] =
2467 CPUID_7_0_EDX_SPEC_CTRL,
2468 .features[FEAT_7_0_EBX] =
2469 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2470 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2471 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2472 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2473 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2474 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2475 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2476 CPUID_7_0_EBX_AVX512VL,
09b9ee64
TX		 2477 .features[FEAT_7_0_ECX] =
2478 CPUID_7_0_ECX_PKU,
ac96c413
EH		 2479 /* Missing: XSAVES (not supported by some Linux versions,
2480 * including v4.1 to v4.12).
2481 * KVM doesn't yet expose any XSAVES state save component,
2482 * and the only one defined in Skylake (processor tracing)
2483 * probably will block migration anyway.
2484 */
2485 .features[FEAT_XSAVE] =
2486 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2487 CPUID_XSAVE_XGETBV1,
2488 .features[FEAT_6_EAX] =
2489 CPUID_6_EAX_ARAT,
2490 .xlevel = 0x80000008,
2491 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2492 },
c7a88b52
TX		 2493 {
2494 .name = "Cascadelake-Server",
2495 .level = 0xd,
2496 .vendor = CPUID_VENDOR_INTEL,
2497 .family = 6,
2498 .model = 85,
2499 .stepping = 5,
2500 .features[FEAT_1_EDX] =
2501 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2502 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2503 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2504 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2505 CPUID_DE | CPUID_FP87,
2506 .features[FEAT_1_ECX] =
2507 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2508 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2509 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2510 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2511 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2512 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2513 .features[FEAT_8000_0001_EDX] =
2514 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2515 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2516 .features[FEAT_8000_0001_ECX] =
2517 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2518 .features[FEAT_7_0_EBX] =
2519 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2520 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2521 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2522 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2523 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2524 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2525 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2526 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2527 CPUID_7_0_EBX_INTEL_PT,
2528 .features[FEAT_7_0_ECX] =
2529 CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE |
2530 CPUID_7_0_ECX_AVX512VNNI,
2531 .features[FEAT_7_0_EDX] =
2532 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2533 /* Missing: XSAVES (not supported by some Linux versions,
2534 * including v4.1 to v4.12).
2535 * KVM doesn't yet expose any XSAVES state save component,
2536 * and the only one defined in Skylake (processor tracing)
2537 * probably will block migration anyway.
2538 */
2539 .features[FEAT_XSAVE] =
2540 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2541 CPUID_XSAVE_XGETBV1,
2542 .features[FEAT_6_EAX] =
2543 CPUID_6_EAX_ARAT,
2544 .xlevel = 0x80000008,
2545 .model_id = "Intel Xeon Processor (Cascadelake)",
2546 },
8a11c62d
RH		 2547 {
2548 .name = "Icelake-Client",
2549 .level = 0xd,
2550 .vendor = CPUID_VENDOR_INTEL,
2551 .family = 6,
2552 .model = 126,
2553 .stepping = 0,
2554 .features[FEAT_1_EDX] =
2555 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2556 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2557 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2558 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2559 CPUID_DE | CPUID_FP87,
2560 .features[FEAT_1_ECX] =
2561 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2562 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2563 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2564 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2565 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2566 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2567 .features[FEAT_8000_0001_EDX] =
2568 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2569 CPUID_EXT2_SYSCALL,
2570 .features[FEAT_8000_0001_ECX] =
2571 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2572 .features[FEAT_8000_0008_EBX] =
2573 CPUID_8000_0008_EBX_WBNOINVD,
2574 .features[FEAT_7_0_EBX] =
2575 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2576 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2577 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2578 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2579 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INTEL_PT,
2580 .features[FEAT_7_0_ECX] =
2581 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2582 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2583 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2584 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2585 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2586 .features[FEAT_7_0_EDX] =
2587 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2588 /* Missing: XSAVES (not supported by some Linux versions,
2589 * including v4.1 to v4.12).
2590 * KVM doesn't yet expose any XSAVES state save component,
2591 * and the only one defined in Skylake (processor tracing)
2592 * probably will block migration anyway.
2593 */
2594 .features[FEAT_XSAVE] =
2595 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2596 CPUID_XSAVE_XGETBV1,
2597 .features[FEAT_6_EAX] =
2598 CPUID_6_EAX_ARAT,
2599 .xlevel = 0x80000008,
2600 .model_id = "Intel Core Processor (Icelake)",
2601 },
2602 {
2603 .name = "Icelake-Server",
2604 .level = 0xd,
2605 .vendor = CPUID_VENDOR_INTEL,
2606 .family = 6,
2607 .model = 134,
2608 .stepping = 0,
2609 .features[FEAT_1_EDX] =
2610 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2611 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2612 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2613 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2614 CPUID_DE | CPUID_FP87,
2615 .features[FEAT_1_ECX] =
2616 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2617 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2618 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2619 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2620 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2621 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2622 .features[FEAT_8000_0001_EDX] =
2623 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2624 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2625 .features[FEAT_8000_0001_ECX] =
2626 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2627 .features[FEAT_8000_0008_EBX] =
2628 CPUID_8000_0008_EBX_WBNOINVD,
2629 .features[FEAT_7_0_EBX] =
2630 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2631 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2632 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2633 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2634 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_CLWB |
2635 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2636 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2637 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
2638 CPUID_7_0_EBX_INTEL_PT,
2639 .features[FEAT_7_0_ECX] =
2640 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2641 CPUID_7_0_ECX_OSPKE | CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2642 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2643 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2644 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2645 .features[FEAT_7_0_EDX] =
2646 CPUID_7_0_EDX_PCONFIG | CPUID_7_0_EDX_SPEC_CTRL |
2647 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2648 /* Missing: XSAVES (not supported by some Linux versions,
2649 * including v4.1 to v4.12).
2650 * KVM doesn't yet expose any XSAVES state save component,
2651 * and the only one defined in Skylake (processor tracing)
2652 * probably will block migration anyway.
2653 */
2654 .features[FEAT_XSAVE] =
2655 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2656 CPUID_XSAVE_XGETBV1,
2657 .features[FEAT_6_EAX] =
2658 CPUID_6_EAX_ARAT,
2659 .xlevel = 0x80000008,
2660 .model_id = "Intel Xeon Processor (Icelake)",
2661 },
a1849515
BF		 2662 {
2663 .name = "KnightsMill",
2664 .level = 0xd,
2665 .vendor = CPUID_VENDOR_INTEL,
2666 .family = 6,
2667 .model = 133,
2668 .stepping = 0,
2669 .features[FEAT_1_EDX] =
2670 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2671 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2672 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2673 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2674 CPUID_PSE | CPUID_DE | CPUID_FP87,
2675 .features[FEAT_1_ECX] =
2676 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2677 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2678 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2679 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2680 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2681 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2682 .features[FEAT_8000_0001_EDX] =
2683 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2684 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2685 .features[FEAT_8000_0001_ECX] =
2686 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2687 .features[FEAT_7_0_EBX] =
2688 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2689 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2690 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2691 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2692 CPUID_7_0_EBX_AVX512ER,
2693 .features[FEAT_7_0_ECX] =
2694 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2695 .features[FEAT_7_0_EDX] =
2696 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2697 .features[FEAT_XSAVE] =
2698 CPUID_XSAVE_XSAVEOPT,
2699 .features[FEAT_6_EAX] =
2700 CPUID_6_EAX_ARAT,
2701 .xlevel = 0x80000008,
2702 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2703 },
3eca4642
EH		 2704 {
2705 .name = "Opteron_G1",
2706 .level = 5,
99b88a17 2707 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2708 .family = 15,
2709 .model = 6,
2710 .stepping = 1,
0514ef2f 2711 .features[FEAT_1_EDX] =
b3a4f0b1 2712 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2713 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2714 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2715 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2716 CPUID_DE | CPUID_FP87,
0514ef2f 2717 .features[FEAT_1_ECX] =
27861ecc 2718 CPUID_EXT_SSE3,
0514ef2f 2719 .features[FEAT_8000_0001_EDX] =
2a923a29 2720 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2721 .xlevel = 0x80000008,
2722 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2723 },
2724 {
2725 .name = "Opteron_G2",
2726 .level = 5,
99b88a17 2727 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2728 .family = 15,
2729 .model = 6,
2730 .stepping = 1,
0514ef2f 2731 .features[FEAT_1_EDX] =
b3a4f0b1 2732 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2733 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2734 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2735 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2736 CPUID_DE | CPUID_FP87,
0514ef2f 2737 .features[FEAT_1_ECX] =
27861ecc 2738 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
33b5e8c0 2739 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2740 .features[FEAT_8000_0001_EDX] =
2a923a29 2741 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2742 .features[FEAT_8000_0001_ECX] =
27861ecc 2743 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2744 .xlevel = 0x80000008,
2745 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2746 },
2747 {
2748 .name = "Opteron_G3",
2749 .level = 5,
99b88a17 2750 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2751 .family = 16,
2752 .model = 2,
2753 .stepping = 3,
0514ef2f 2754 .features[FEAT_1_EDX] =
b3a4f0b1 2755 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2756 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2757 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2758 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2759 CPUID_DE | CPUID_FP87,
0514ef2f 2760 .features[FEAT_1_ECX] =
27861ecc 2761 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2762 CPUID_EXT_SSE3,
33b5e8c0 2763 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2764 .features[FEAT_8000_0001_EDX] =
2a923a29 2765 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2766 .features[FEAT_8000_0001_ECX] =
27861ecc 2767 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2768 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2769 .xlevel = 0x80000008,
2770 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2771 },
2772 {
2773 .name = "Opteron_G4",
2774 .level = 0xd,
99b88a17 2775 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2776 .family = 21,
2777 .model = 1,
2778 .stepping = 2,
0514ef2f 2779 .features[FEAT_1_EDX] =
b3a4f0b1 2780 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2781 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2782 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2783 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2784 CPUID_DE | CPUID_FP87,
0514ef2f 2785 .features[FEAT_1_ECX] =
27861ecc 2786 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2787 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2788 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2789 CPUID_EXT_SSE3,
33b5e8c0 2790 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2791 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2792 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2793 CPUID_EXT2_SYSCALL,
0514ef2f 2794 .features[FEAT_8000_0001_ECX] =
27861ecc 2795 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2796 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2797 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2798 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2799 /* no xsaveopt! */
3eca4642
EH		 2800 .xlevel = 0x8000001A,
2801 .model_id = "AMD Opteron 62xx class CPU",
2802 },
021941b9
AP		 2803 {
2804 .name = "Opteron_G5",
2805 .level = 0xd,
99b88a17 2806 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2807 .family = 21,
2808 .model = 2,
2809 .stepping = 0,
0514ef2f 2810 .features[FEAT_1_EDX] =
b3a4f0b1 2811 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2812 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2813 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2814 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2815 CPUID_DE | CPUID_FP87,
0514ef2f 2816 .features[FEAT_1_ECX] =
27861ecc 2817 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2818 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2819 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2820 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
33b5e8c0 2821 /* Missing: CPUID_EXT2_RDTSCP */
0514ef2f 2822 .features[FEAT_8000_0001_EDX] =
2a923a29
EH		 2823 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2824 CPUID_EXT2_SYSCALL,
0514ef2f 2825 .features[FEAT_8000_0001_ECX] =
27861ecc 2826 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2827 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2828 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2829 CPUID_EXT3_LAHF_LM,
0bb0b2d2 2830 /* no xsaveopt! */
021941b9
AP		 2831 .xlevel = 0x8000001A,
2832 .model_id = "AMD Opteron 63xx class CPU",
2833 },
2e2efc7d
BS		 2834 {
2835 .name = "EPYC",
2836 .level = 0xd,
2837 .vendor = CPUID_VENDOR_AMD,
2838 .family = 23,
2839 .model = 1,
2840 .stepping = 2,
2841 .features[FEAT_1_EDX] =
2842 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2843 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2844 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2845 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2846 CPUID_VME | CPUID_FP87,
2847 .features[FEAT_1_ECX] =
2848 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2849 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2850 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2851 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2852 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2853 .features[FEAT_8000_0001_EDX] =
2854 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2855 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2856 CPUID_EXT2_SYSCALL,
2857 .features[FEAT_8000_0001_ECX] =
2858 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2859 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2860 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2861 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2862 .features[FEAT_7_0_EBX] =
2863 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2864 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2865 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2866 CPUID_7_0_EBX_SHA_NI,
2867 /* Missing: XSAVES (not supported by some Linux versions,
2868 * including v4.1 to v4.12).
2869 * KVM doesn't yet expose any XSAVES state save component.
2870 */
2871 .features[FEAT_XSAVE] =
2872 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2873 CPUID_XSAVE_XGETBV1,
2874 .features[FEAT_6_EAX] =
2875 CPUID_6_EAX_ARAT,
e0051647 2876 .xlevel = 0x8000001E,
2e2efc7d 2877 .model_id = "AMD EPYC Processor",
fe52acd2 2878 .cache_info = &epyc_cache_info,
2e2efc7d 2879 },
6cfbc54e
EH		 2880 {
2881 .name = "EPYC-IBPB",
2882 .level = 0xd,
2883 .vendor = CPUID_VENDOR_AMD,
2884 .family = 23,
2885 .model = 1,
2886 .stepping = 2,
2887 .features[FEAT_1_EDX] =
2888 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2889 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2890 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2891 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2892 CPUID_VME | CPUID_FP87,
2893 .features[FEAT_1_ECX] =
2894 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2895 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2896 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2897 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2898 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2899 .features[FEAT_8000_0001_EDX] =
2900 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2901 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2902 CPUID_EXT2_SYSCALL,
2903 .features[FEAT_8000_0001_ECX] =
2904 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2905 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2906 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2907 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2908 .features[FEAT_8000_0008_EBX] =
2909 CPUID_8000_0008_EBX_IBPB,
2910 .features[FEAT_7_0_EBX] =
2911 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2912 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2913 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2914 CPUID_7_0_EBX_SHA_NI,
2915 /* Missing: XSAVES (not supported by some Linux versions,
2916 * including v4.1 to v4.12).
2917 * KVM doesn't yet expose any XSAVES state save component.
2918 */
2919 .features[FEAT_XSAVE] =
2920 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2921 CPUID_XSAVE_XGETBV1,
2922 .features[FEAT_6_EAX] =
2923 CPUID_6_EAX_ARAT,
e0051647 2924 .xlevel = 0x8000001E,
6cfbc54e 2925 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2926 .cache_info = &epyc_cache_info,
6cfbc54e 2927 },
c6dc6f63
AP		 2928};
2929
5114e842
EH		 2930typedef struct PropValue {
2931 const char *prop, *value;
2932} PropValue;
2933
2934/* KVM-specific features that are automatically added/removed
2935 * from all CPU models when KVM is enabled.
2936 */
2937static PropValue kvm_default_props[] = {
2938 { "kvmclock", "on" },
2939 { "kvm-nopiodelay", "on" },
2940 { "kvm-asyncpf", "on" },
2941 { "kvm-steal-time", "on" },
2942 { "kvm-pv-eoi", "on" },
2943 { "kvmclock-stable-bit", "on" },
2944 { "x2apic", "on" },
2945 { "acpi", "off" },
2946 { "monitor", "off" },
2947 { "svm", "off" },
2948 { NULL, NULL },
2949};
2950
04d99c3c
EH		 2951/* TCG-specific defaults that override all CPU models when using TCG
2952 */
2953static PropValue tcg_default_props[] = {
2954 { "vme", "off" },
2955 { NULL, NULL },
2956};
2957
2958
5114e842
EH		 2959void x86_cpu_change_kvm_default(const char *prop, const char *value)
2960{
2961 PropValue *pv;
2962 for (pv = kvm_default_props; pv->prop; pv++) {
2963 if (!strcmp(pv->prop, prop)) {
2964 pv->value = value;
2965 break;
2966 }
2967 }
2968
2969 /* It is valid to call this function only for properties that
2970 * are already present in the kvm_default_props table.
2971 */
2972 assert(pv->prop);
2973}
2974
4d1b279b
EH		 2975static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2976 bool migratable_only);
2977
40bfe48f
HZ		 2978static bool lmce_supported(void)
2979{
c62f2630 2980 uint64_t mce_cap = 0;
40bfe48f 2981
c62f2630 2982#ifdef CONFIG_KVM
40bfe48f
HZ		 2983 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2984 return false;
2985 }
c62f2630 2986#endif
40bfe48f
HZ		 2987
2988 return !!(mce_cap & MCG_LMCE_P);
2989}
2990
7d8050b5
EH		 2991#define CPUID_MODEL_ID_SZ 48
2992
2993/**
2994 * cpu_x86_fill_model_id:
2995 * Get CPUID model ID string from host CPU.
2996 *
2997 * @str should have at least CPUID_MODEL_ID_SZ bytes
2998 *
2999 * The function does NOT add a null terminator to the string
3000 * automatically.
3001 */
c6dc6f63
AP		 3002static int cpu_x86_fill_model_id(char *str)
3003{
3004 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3005 int i;
3006
3007 for (i = 0; i < 3; i++) {
3008 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3009 memcpy(str + i * 16 + 0, &eax, 4);
3010 memcpy(str + i * 16 + 4, &ebx, 4);
3011 memcpy(str + i * 16 + 8, &ecx, 4);
3012 memcpy(str + i * 16 + 12, &edx, 4);
3013 }
3014 return 0;
3015}
3016
c62f2630 3017static Property max_x86_cpu_properties[] = {
120eee7d 3018 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 3019 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 3020 DEFINE_PROP_END_OF_LIST()
3021};
3022
c62f2630 3023static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 3024{
84f1b92f 3025 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 3026 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 3027
f48c8837 3028 xcc->ordering = 9;
6e746f30 3029
ee465a3e 3030 xcc->model_description =
c62f2630 3031 "Enables all features supported by the accelerator in the current host";
d940ee9b 3032
c62f2630 3033 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3034}
3035
0bacd8b3
EH		 3036static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3037
c62f2630 3038static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3039{
3040 X86CPU *cpu = X86_CPU(obj);
3041 CPUX86State *env = &cpu->env;
3042 KVMState *s = kvm_state;
d940ee9b 3043
4d1b279b
EH		 3044 /* We can't fill the features array here because we don't know yet if
3045 * "migratable" is true or false.
3046 */
44bd8e53 3047 cpu->max_features = true;
4d1b279b 3048
d6dcc558 3049 if (accel_uses_host_cpuid()) {
bd182022
EH		 3050 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3051 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3052 int family, model, stepping;
d6dcc558
SAGDR		 3053 X86CPUDefinition host_cpudef = { };
3054 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3055
3056 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3057 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3058
bd182022 3059 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3060
bd182022 3061 cpu_x86_fill_model_id(model_id);
0bacd8b3 3062
bd182022
EH		 3063 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3064 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3065 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3066 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3067 &error_abort);
3068 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3069 &error_abort);
0bacd8b3 3070
d6dcc558
SAGDR		 3071 if (kvm_enabled()) {
3072 env->cpuid_min_level =
3073 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3074 env->cpuid_min_xlevel =
3075 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3076 env->cpuid_min_xlevel2 =
3077 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3078 } else {
3079 env->cpuid_min_level =
3080 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3081 env->cpuid_min_xlevel =
3082 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3083 env->cpuid_min_xlevel2 =
3084 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3085 }
40bfe48f
HZ		 3086
3087 if (lmce_supported()) {
3088 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3089 }
6900d1cc
EH		 3090 } else {
3091 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3092 "vendor", &error_abort);
3093 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3094 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3095 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3096 object_property_set_str(OBJECT(cpu),
3097 "QEMU TCG CPU version " QEMU_HW_VERSION,
3098 "model-id", &error_abort);
e4356010 3099 }
2a573259 3100
d940ee9b 3101 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3102}
3103
c62f2630
EH		 3104static const TypeInfo max_x86_cpu_type_info = {
3105 .name = X86_CPU_TYPE_NAME("max"),
3106 .parent = TYPE_X86_CPU,
3107 .instance_init = max_x86_cpu_initfn,
3108 .class_init = max_x86_cpu_class_init,
3109};
3110
d6dcc558 3111#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3112static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3113{
3114 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3115
d6dcc558 3116 xcc->host_cpuid_required = true;
c62f2630
EH		 3117 xcc->ordering = 8;
3118
02693cc4
GK		 3119#if defined(CONFIG_KVM)
3120 xcc->model_description =
3121 "KVM processor with all supported host features ";
3122#elif defined(CONFIG_HVF)
3123 xcc->model_description =
3124 "HVF processor with all supported host features ";
3125#endif
c62f2630
EH		 3126}
3127
d940ee9b
EH		 3128static const TypeInfo host_x86_cpu_type_info = {
3129 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3130 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3131 .class_init = host_x86_cpu_class_init,
3132};
3133
3134#endif
3135
07585923
RH		 3136static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3137{
3138 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3139
3140 switch (f->type) {
3141 case CPUID_FEATURE_WORD:
3142 {
3143 const char *reg = get_register_name_32(f->cpuid.reg);
3144 assert(reg);
3145 return g_strdup_printf("CPUID.%02XH:%s",
3146 f->cpuid.eax, reg);
3147 }
3148 case MSR_FEATURE_WORD:
3149 return g_strdup_printf("MSR(%02XH)",
3150 f->msr.index);
3151 }
3152
3153 return NULL;
3154}
3155
8459e396 3156static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3157{
8459e396 3158 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3159 int i;
07585923 3160 char *feat_word_str;
c6dc6f63 3161
857aee33 3162 for (i = 0; i < 32; ++i) {
72370dc1 3163 if ((1UL << i) & mask) {
07585923
RH		 3164 feat_word_str = feature_word_description(f, i);
3165 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3166 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3167 feat_word_str,
8297be80
AF		 3168 f->feat_names[i] ? "." : "",
3169 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3170 g_free(feat_word_str);
c6dc6f63 3171 }
857aee33 3172 }
c6dc6f63
AP		 3173}
3174
d7bce999
EB		 3175static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3176 const char *name, void *opaque,
3177 Error **errp)
95b8519d
AF		 3178{
3179 X86CPU *cpu = X86_CPU(obj);
3180 CPUX86State *env = &cpu->env;
3181 int64_t value;
3182
3183 value = (env->cpuid_version >> 8) & 0xf;
3184 if (value == 0xf) {
3185 value += (env->cpuid_version >> 20) & 0xff;
3186 }
51e72bc1 3187 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3188}
3189
d7bce999
EB		 3190static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3191 const char *name, void *opaque,
3192 Error **errp)
ed5e1ec3 3193{
71ad61d3
AF		 3194 X86CPU *cpu = X86_CPU(obj);
3195 CPUX86State *env = &cpu->env;
3196 const int64_t min = 0;
3197 const int64_t max = 0xff + 0xf;
65cd9064 3198 Error *local_err = NULL;
71ad61d3
AF		 3199 int64_t value;
3200
51e72bc1 3201 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3202 if (local_err) {
3203 error_propagate(errp, local_err);
71ad61d3
AF		 3204 return;
3205 }
3206 if (value < min || value > max) {
c6bd8c70
MA		 3207 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3208 name ? name : "null", value, min, max);
71ad61d3
AF		 3209 return;
3210 }
3211
ed5e1ec3 3212 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3213 if (value > 0x0f) {
3214 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3215 } else {
71ad61d3 3216 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3217 }
3218}
3219
d7bce999
EB		 3220static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3221 const char *name, void *opaque,
3222 Error **errp)
67e30c83
AF		 3223{
3224 X86CPU *cpu = X86_CPU(obj);
3225 CPUX86State *env = &cpu->env;
3226 int64_t value;
3227
3228 value = (env->cpuid_version >> 4) & 0xf;
3229 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3230 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3231}
3232
d7bce999
EB		 3233static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3234 const char *name, void *opaque,
3235 Error **errp)
b0704cbd 3236{
c5291a4f
AF		 3237 X86CPU *cpu = X86_CPU(obj);
3238 CPUX86State *env = &cpu->env;
3239 const int64_t min = 0;
3240 const int64_t max = 0xff;
65cd9064 3241 Error *local_err = NULL;
c5291a4f
AF		 3242 int64_t value;
3243
51e72bc1 3244 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3245 if (local_err) {
3246 error_propagate(errp, local_err);
c5291a4f
AF		 3247 return;
3248 }
3249 if (value < min || value > max) {
c6bd8c70
MA		 3250 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3251 name ? name : "null", value, min, max);
c5291a4f
AF		 3252 return;
3253 }
3254
b0704cbd 3255 env->cpuid_version &= ~0xf00f0;
c5291a4f 3256 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3257}
3258
35112e41 3259static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3260 const char *name, void *opaque,
35112e41
AF		 3261 Error **errp)
3262{
3263 X86CPU *cpu = X86_CPU(obj);
3264 CPUX86State *env = &cpu->env;
3265 int64_t value;
3266
3267 value = env->cpuid_version & 0xf;
51e72bc1 3268 visit_type_int(v, name, &value, errp);
35112e41
AF		 3269}
3270
036e2222 3271static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3272 const char *name, void *opaque,
036e2222 3273 Error **errp)
38c3dc46 3274{
036e2222
AF		 3275 X86CPU *cpu = X86_CPU(obj);
3276 CPUX86State *env = &cpu->env;
3277 const int64_t min = 0;
3278 const int64_t max = 0xf;
65cd9064 3279 Error *local_err = NULL;
036e2222
AF		 3280 int64_t value;
3281
51e72bc1 3282 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3283 if (local_err) {
3284 error_propagate(errp, local_err);
036e2222
AF		 3285 return;
3286 }
3287 if (value < min || value > max) {
c6bd8c70
MA		 3288 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3289 name ? name : "null", value, min, max);
036e2222
AF		 3290 return;
3291 }
3292
38c3dc46 3293 env->cpuid_version &= ~0xf;
036e2222 3294 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3295}
3296
d480e1af
AF		 3297static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3298{
3299 X86CPU *cpu = X86_CPU(obj);
3300 CPUX86State *env = &cpu->env;
3301 char *value;
d480e1af 3302
e42a92ae 3303 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3304 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3305 env->cpuid_vendor3);
d480e1af
AF		 3306 return value;
3307}
3308
3309static void x86_cpuid_set_vendor(Object *obj, const char *value,
3310 Error **errp)
3311{
3312 X86CPU *cpu = X86_CPU(obj);
3313 CPUX86State *env = &cpu->env;
3314 int i;
3315
9df694ee 3316 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3317 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3318 return;
3319 }
3320
3321 env->cpuid_vendor1 = 0;
3322 env->cpuid_vendor2 = 0;
3323 env->cpuid_vendor3 = 0;
3324 for (i = 0; i < 4; i++) {
3325 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3326 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3327 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3328 }
d480e1af
AF		 3329}
3330
63e886eb
AF		 3331static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3332{
3333 X86CPU *cpu = X86_CPU(obj);
3334 CPUX86State *env = &cpu->env;
3335 char *value;
3336 int i;
3337
3338 value = g_malloc(48 + 1);
3339 for (i = 0; i < 48; i++) {
3340 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3341 }
3342 value[48] = '\0';
3343 return value;
3344}
3345
938d4c25
AF		 3346static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3347 Error **errp)
dcce6675 3348{
938d4c25
AF		 3349 X86CPU *cpu = X86_CPU(obj);
3350 CPUX86State *env = &cpu->env;
dcce6675
AF		 3351 int c, len, i;
3352
3353 if (model_id == NULL) {
3354 model_id = "";
3355 }
3356 len = strlen(model_id);
d0a6acf4 3357 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3358 for (i = 0; i < 48; i++) {
3359 if (i >= len) {
3360 c = '\0';
3361 } else {
3362 c = (uint8_t)model_id[i];
3363 }
3364 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3365 }
3366}
3367
d7bce999
EB		 3368static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3369 void *opaque, Error **errp)
89e48965
AF		 3370{
3371 X86CPU *cpu = X86_CPU(obj);
3372 int64_t value;
3373
3374 value = cpu->env.tsc_khz * 1000;
51e72bc1 3375 visit_type_int(v, name, &value, errp);
89e48965
AF		 3376}
3377
d7bce999
EB		 3378static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3379 void *opaque, Error **errp)
89e48965
AF		 3380{
3381 X86CPU *cpu = X86_CPU(obj);
3382 const int64_t min = 0;
2e84849a 3383 const int64_t max = INT64_MAX;
65cd9064 3384 Error *local_err = NULL;
89e48965
AF		 3385 int64_t value;
3386
51e72bc1 3387 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3388 if (local_err) {
3389 error_propagate(errp, local_err);
89e48965
AF		 3390 return;
3391 }
3392 if (value < min || value > max) {
c6bd8c70
MA		 3393 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3394 name ? name : "null", value, min, max);
89e48965
AF		 3395 return;
3396 }
3397
36f96c4b 3398 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3399}
3400
7e5292b5 3401/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3402static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3403 const char *name, void *opaque,
3404 Error **errp)
8e8aba50 3405{
7e5292b5 3406 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3407 FeatureWord w;
8e8aba50
EH		 3408 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3409 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3410 X86CPUFeatureWordInfoList *list = NULL;
3411
3412 for (w = 0; w < FEATURE_WORDS; w++) {
3413 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3414 /*
3415 * We didn't have MSR features when "feature-words" was
3416 * introduced. Therefore skipped other type entries.
3417 */
3418 if (wi->type != CPUID_FEATURE_WORD) {
3419 continue;
3420 }
8e8aba50 3421 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3422 qwi->cpuid_input_eax = wi->cpuid.eax;
3423 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3424 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3425 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3426 qwi->features = array[w];
8e8aba50
EH		 3427
3428 /* List will be in reverse order, but order shouldn't matter */
3429 list_entries[w].next = list;
3430 list_entries[w].value = &word_infos[w];
3431 list = &list_entries[w];
3432 }
3433
6b62d961 3434 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3435}
3436
d7bce999
EB		 3437static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3438 void *opaque, Error **errp)
c8f0f88e
IM		 3439{
3440 X86CPU *cpu = X86_CPU(obj);
3441 int64_t value = cpu->hyperv_spinlock_attempts;
3442
51e72bc1 3443 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3444}
3445
d7bce999
EB		 3446static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3447 void *opaque, Error **errp)
c8f0f88e
IM		 3448{
3449 const int64_t min = 0xFFF;
3450 const int64_t max = UINT_MAX;
3451 X86CPU *cpu = X86_CPU(obj);
3452 Error *err = NULL;
3453 int64_t value;
3454
51e72bc1 3455 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3456 if (err) {
3457 error_propagate(errp, err);
3458 return;
3459 }
3460
3461 if (value < min || value > max) {
3462 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3463 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3464 object_get_typename(obj), name ? name : "null",
3465 value, min, max);
c8f0f88e
IM		 3466 return;
3467 }
3468 cpu->hyperv_spinlock_attempts = value;
3469}
3470
1b6b7d10 3471static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3472 .name = "int",
3473 .get = x86_get_hv_spinlocks,
3474 .set = x86_set_hv_spinlocks,
3475};
3476
72ac2e87
IM		 3477/* Convert all '_' in a feature string option name to '-', to make feature
3478 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3479 */
3480static inline void feat2prop(char *s)
3481{
3482 while ((s = strchr(s, '_'))) {
3483 *s = '-';
3484 }
3485}
3486
b54c9377
EH		 3487/* Return the feature property name for a feature flag bit */
3488static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3489{
3490 /* XSAVE components are automatically enabled by other features,
3491 * so return the original feature name instead
3492 */
3493 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3494 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3495
3496 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3497 x86_ext_save_areas[comp].bits) {
3498 w = x86_ext_save_areas[comp].feature;
3499 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3500 }
3501 }
3502
3503 assert(bitnr < 32);
3504 assert(w < FEATURE_WORDS);
3505 return feature_word_info[w].feat_names[bitnr];
3506}
3507
dc15c051
IM		 3508/* Compatibily hack to maintain legacy +-feat semantic,
3509 * where +-feat overwrites any feature set by
3510 * feat=on|feat even if the later is parsed after +-feat
3511 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3512 */
2fae0d96 3513static GList *plus_features, *minus_features;
dc15c051 3514
83a00f60
EH		 3515static gint compare_string(gconstpointer a, gconstpointer b)
3516{
3517 return g_strcmp0(a, b);
3518}
3519
8f961357
EH		 3520/* Parse "+feature,-feature,feature=foo" CPU feature string
3521 */
62a48a2a 3522static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3523 Error **errp)
8f961357 3524{
8f961357 3525 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3526 static bool cpu_globals_initialized;
83a00f60 3527 bool ambiguous = false;
62a48a2a
IM		 3528
3529 if (cpu_globals_initialized) {
3530 return;
3531 }
3532 cpu_globals_initialized = true;
8f961357 3533
f6750e95
EH		 3534 if (!features) {
3535 return;
3536 }
3537
3538 for (featurestr = strtok(features, ",");
685479bd 3539 featurestr;
f6750e95
EH		 3540 featurestr = strtok(NULL, ",")) {
3541 const char *name;
3542 const char *val = NULL;
3543 char *eq = NULL;
cf2887c9 3544 char num[32];
62a48a2a 3545 GlobalProperty *prop;
c6dc6f63 3546
f6750e95 3547 /* Compatibility syntax: */
c6dc6f63 3548 if (featurestr[0] == '+') {
2fae0d96
EH		 3549 plus_features = g_list_append(plus_features,
3550 g_strdup(featurestr + 1));
f6750e95 3551 continue;
c6dc6f63 3552 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3553 minus_features = g_list_append(minus_features,
3554 g_strdup(featurestr + 1));
f6750e95
EH		 3555 continue;
3556 }
3557
3558 eq = strchr(featurestr, '=');
3559 if (eq) {
3560 *eq++ = 0;
3561 val = eq;
c6dc6f63 3562 } else {
f6750e95 3563 val = "on";
a91987c2 3564 }
f6750e95
EH		 3565
3566 feat2prop(featurestr);
3567 name = featurestr;
3568
83a00f60 3569 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3570 warn_report("Ambiguous CPU model string. "
3571 "Don't mix both \"+%s\" and \"%s=%s\"",
3572 name, name, val);
83a00f60
EH		 3573 ambiguous = true;
3574 }
3575 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3576 warn_report("Ambiguous CPU model string. "
3577 "Don't mix both \"-%s\" and \"%s=%s\"",
3578 name, name, val);
83a00f60
EH		 3579 ambiguous = true;
3580 }
3581
f6750e95
EH		 3582 /* Special case: */
3583 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3584 int ret;
f46bfdbf 3585 uint64_t tsc_freq;
f6750e95 3586
f17fd4fd 3587 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3588 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3589 error_setg(errp, "bad numerical value %s", val);
3590 return;
3591 }
3592 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3593 val = num;
3594 name = "tsc-frequency";
c6dc6f63 3595 }
f6750e95 3596
62a48a2a
IM		 3597 prop = g_new0(typeof(*prop), 1);
3598 prop->driver = typename;
3599 prop->property = g_strdup(name);
3600 prop->value = g_strdup(val);
62a48a2a 3601 qdev_prop_register_global(prop);
f6750e95
EH		 3602 }
3603
83a00f60 3604 if (ambiguous) {
3dc6f869
AF		 3605 warn_report("Compatibility of ambiguous CPU model "
3606 "strings won't be kept on future QEMU versions");
83a00f60 3607 }
c6dc6f63
AP		 3608}
3609
b8d834a0 3610static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3611static int x86_cpu_filter_features(X86CPU *cpu);
3612
3613/* Check for missing features that may prevent the CPU class from
3614 * running using the current machine and accelerator.
3615 */
3616static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3617 strList **missing_feats)
3618{
3619 X86CPU *xc;
3620 FeatureWord w;
3621 Error *err = NULL;
3622 strList **next = missing_feats;
3623
d6dcc558 3624 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3625 strList *new = g_new0(strList, 1);
3c254ab8 3626 new->value = g_strdup("kvm");
b54c9377
EH		 3627 *missing_feats = new;
3628 return;
3629 }
3630
3631 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3632
b8d834a0 3633 x86_cpu_expand_features(xc, &err);
b54c9377 3634 if (err) {
b8d834a0 3635 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3636 * but in case it does, just report the model as not
3637 * runnable at all using the "type" property.
3638 */
3639 strList *new = g_new0(strList, 1);
3640 new->value = g_strdup("type");
3641 *next = new;
3642 next = &new->next;
3643 }
3644
3645 x86_cpu_filter_features(xc);
3646
3647 for (w = 0; w < FEATURE_WORDS; w++) {
3648 uint32_t filtered = xc->filtered_features[w];
3649 int i;
3650 for (i = 0; i < 32; i++) {
3651 if (filtered & (1UL << i)) {
3652 strList *new = g_new0(strList, 1);
3653 new->value = g_strdup(x86_cpu_feature_name(w, i));
3654 *next = new;
3655 next = &new->next;
3656 }
3657 }
3658 }
3659
3660 object_unref(OBJECT(xc));
3661}
3662
8c3329e5 3663/* Print all cpuid feature names in featureset
c6dc6f63 3664 */
cc643b1e 3665static void listflags(FILE *f, fprintf_function print, GList *features)
0856579c 3666{
cc643b1e
DB		 3667 size_t len = 0;
3668 GList *tmp;
3669
3670 for (tmp = features; tmp; tmp = tmp->next) {
3671 const char *name = tmp->data;
3672 if ((len + strlen(name) + 1) >= 75) {
3673 print(f, "\n");
3674 len = 0;
c6dc6f63 3675 }
cc643b1e
DB		 3676 print(f, "%s%s", len == 0 ? " " : " ", name);
3677 len += strlen(name) + 1;
8c3329e5 3678 }
cc643b1e 3679 print(f, "\n");
c6dc6f63
AP		 3680}
3681
f48c8837 3682/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3683static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3684{
3685 ObjectClass *class_a = (ObjectClass *)a;
3686 ObjectClass *class_b = (ObjectClass *)b;
3687 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3688 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3689 char *name_a, *name_b;
3690 int ret;
ee465a3e 3691
f48c8837 3692 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3693 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3694 } else {
c7dbff4b
DB		 3695 name_a = x86_cpu_class_get_model_name(cc_a);
3696 name_b = x86_cpu_class_get_model_name(cc_b);
3697 ret = strcmp(name_a, name_b);
3698 g_free(name_a);
3699 g_free(name_b);
ee465a3e 3700 }
c7dbff4b 3701 return ret;
ee465a3e
EH		 3702}
3703
3704static GSList *get_sorted_cpu_model_list(void)
3705{
3706 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3707 list = g_slist_sort(list, x86_cpu_list_compare);
3708 return list;
3709}
3710
3711static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3712{
3713 ObjectClass *oc = data;
3714 X86CPUClass *cc = X86_CPU_CLASS(oc);
3715 CPUListState *s = user_data;
3716 char *name = x86_cpu_class_get_model_name(cc);
3717 const char *desc = cc->model_description;
0bacd8b3 3718 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3719 desc = cc->cpu_def->model_id;
3720 }
3721
081492ca 3722 (*s->cpu_fprintf)(s->file, "x86 %-20s %-48s\n",
ee465a3e
EH		 3723 name, desc);
3724 g_free(name);
3725}
3726
3727/* list available CPU models and flags */
e916cbf8 3728void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
c6dc6f63 3729{
cc643b1e 3730 int i, j;
ee465a3e
EH		 3731 CPUListState s = {
3732 .file = f,
3733 .cpu_fprintf = cpu_fprintf,
3734 };
3735 GSList *list;
cc643b1e 3736 GList *names = NULL;
c6dc6f63 3737
ee465a3e
EH		 3738 (*cpu_fprintf)(f, "Available CPUs:\n");
3739 list = get_sorted_cpu_model_list();
3740 g_slist_foreach(list, x86_cpu_list_entry, &s);
3741 g_slist_free(list);
21ad7789 3742
cc643b1e 3743 names = NULL;
3af60be2
JK		 3744 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3745 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3746 for (j = 0; j < 32; j++) {
3747 if (fw->feat_names[j]) {
3748 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3749 }
3750 }
3af60be2 3751 }
cc643b1e
DB		 3752
3753 names = g_list_sort(names, (GCompareFunc)strcmp);
3754
3755 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
3756 listflags(f, cpu_fprintf, names);
3757 (*cpu_fprintf)(f, "\n");
3758 g_list_free(names);
c6dc6f63
AP		 3759}
3760
ee465a3e
EH		 3761static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3762{
3763 ObjectClass *oc = data;
3764 X86CPUClass *cc = X86_CPU_CLASS(oc);
3765 CpuDefinitionInfoList **cpu_list = user_data;
3766 CpuDefinitionInfoList *entry;
3767 CpuDefinitionInfo *info;
3768
3769 info = g_malloc0(sizeof(*info));
3770 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3771 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3772 info->has_unavailable_features = true;
8ed877b7 3773 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3774 info->migration_safe = cc->migration_safe;
3775 info->has_migration_safe = true;
5adbed30 3776 info->q_static = cc->static_model;
ee465a3e
EH		 3777
3778 entry = g_malloc0(sizeof(*entry));
3779 entry->value = info;
3780 entry->next = *cpu_list;
3781 *cpu_list = entry;
3782}
3783
76b64a7a 3784CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
e3966126
AL		 3785{
3786 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3787 GSList *list = get_sorted_cpu_model_list();
3788 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3789 g_slist_free(list);
e3966126
AL		 3790 return cpu_list;
3791}
3792
84f1b92f
EH		 3793static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3794 bool migratable_only)
27418adf
EH		 3795{
3796 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3797 uint32_t r = 0;
27418adf 3798
fefb41bf 3799 if (kvm_enabled()) {
07585923
RH		 3800 switch (wi->type) {
3801 case CPUID_FEATURE_WORD:
3802 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3803 wi->cpuid.ecx,
3804 wi->cpuid.reg);
3805 break;
3806 case MSR_FEATURE_WORD:
d86f9636
RH		 3807 r = kvm_arch_get_supported_msr_feature(kvm_state,
3808 wi->msr.index);
07585923
RH		 3809 break;
3810 }
d6dcc558 3811 } else if (hvf_enabled()) {
07585923
RH		 3812 if (wi->type != CPUID_FEATURE_WORD) {
3813 return 0;
3814 }
3815 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3816 wi->cpuid.ecx,
3817 wi->cpuid.reg);
fefb41bf 3818 } else if (tcg_enabled()) {
84f1b92f 3819 r = wi->tcg_features;
fefb41bf
EH		 3820 } else {
3821 return ~0;
3822 }
84f1b92f
EH		 3823 if (migratable_only) {
3824 r &= x86_cpu_get_migratable_flags(w);
3825 }
3826 return r;
27418adf
EH		 3827}
3828
8ca30e86
EH		 3829static void x86_cpu_report_filtered_features(X86CPU *cpu)
3830{
3831 FeatureWord w;
3832
3833 for (w = 0; w < FEATURE_WORDS; w++) {
3834 report_unavailable_features(w, cpu->filtered_features[w]);
3835 }
3836}
3837
5114e842
EH		 3838static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3839{
3840 PropValue *pv;
3841 for (pv = props; pv->prop; pv++) {
3842 if (!pv->value) {
3843 continue;
3844 }
3845 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3846 &error_abort);
3847 }
3848}
3849
f99fd7ca 3850/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3851 */
d940ee9b 3852static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3853{
61dcd775 3854 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3855 const char *vendor;
3856 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3857 FeatureWord w;
c6dc6f63 3858
f99fd7ca
EH		 3859 /*NOTE: any property set by this function should be returned by
3860 * x86_cpu_static_props(), so static expansion of
3861 * query-cpu-model-expansion is always complete.
3862 */
3863
c39c0edf 3864 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3865 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3866 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3867
2d64255b
AF		 3868 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3869 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3870 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3871 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3872 for (w = 0; w < FEATURE_WORDS; w++) {
3873 env->features[w] = def->features[w];
3874 }
82beb536 3875
a9f27ea9
EH		 3876 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3877 cpu->legacy_cache = !def->cache_info;
ab8f992e 3878
9576de75 3879 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3880 /* TODO: in-kernel irqchip for hvf */
82beb536 3881 if (kvm_enabled()) {
492a4c94
LT		 3882 if (!kvm_irqchip_in_kernel()) {
3883 x86_cpu_change_kvm_default("x2apic", "off");
3884 }
3885
5114e842 3886 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3887 } else if (tcg_enabled()) {
3888 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3889 }
5fcca9ff 3890
82beb536 3891 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3892
3893 /* sysenter isn't supported in compatibility mode on AMD,
3894 * syscall isn't supported in compatibility mode on Intel.
3895 * Normally we advertise the actual CPU vendor, but you can
3896 * override this using the 'vendor' property if you want to use
3897 * KVM's sysenter/syscall emulation in compatibility mode and
3898 * when doing cross vendor migration
3899 */
74f54bc4 3900 vendor = def->vendor;
d6dcc558 3901 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3902 uint32_t ebx = 0, ecx = 0, edx = 0;
3903 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3904 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3905 vendor = host_vendor;
3906 }
3907
3908 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3909
c6dc6f63
AP		 3910}
3911
f99fd7ca
EH		 3912/* Return a QDict containing keys for all properties that can be included
3913 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3914 * must be included in the dictionary.
3915 */
3916static QDict *x86_cpu_static_props(void)
3917{
3918 FeatureWord w;
3919 int i;
3920 static const char *props[] = {
3921 "min-level",
3922 "min-xlevel",
3923 "family",
3924 "model",
3925 "stepping",
3926 "model-id",
3927 "vendor",
3928 "lmce",
3929 NULL,
3930 };
3931 static QDict *d;
3932
3933 if (d) {
3934 return d;
3935 }
3936
3937 d = qdict_new();
3938 for (i = 0; props[i]; i++) {
0f9afc2a 3939 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3940 }
3941
3942 for (w = 0; w < FEATURE_WORDS; w++) {
3943 FeatureWordInfo *fi = &feature_word_info[w];
3944 int bit;
3945 for (bit = 0; bit < 32; bit++) {
3946 if (!fi->feat_names[bit]) {
3947 continue;
3948 }
0f9afc2a 3949 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3950 }
3951 }
3952
3953 return d;
3954}
3955
3956/* Add an entry to @props dict, with the value for property. */
3957static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3958{
3959 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3960 &error_abort);
3961
3962 qdict_put_obj(props, prop, value);
3963}
3964
3965/* Convert CPU model data from X86CPU object to a property dictionary
3966 * that can recreate exactly the same CPU model.
3967 */
3968static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3969{
3970 QDict *sprops = x86_cpu_static_props();
3971 const QDictEntry *e;
3972
3973 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3974 const char *prop = qdict_entry_key(e);
3975 x86_cpu_expand_prop(cpu, props, prop);
3976 }
3977}
3978
b8097deb
EH		 3979/* Convert CPU model data from X86CPU object to a property dictionary
3980 * that can recreate exactly the same CPU model, including every
3981 * writeable QOM property.
3982 */
3983static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3984{
3985 ObjectPropertyIterator iter;
3986 ObjectProperty *prop;
3987
3988 object_property_iter_init(&iter, OBJECT(cpu));
3989 while ((prop = object_property_iter_next(&iter))) {
3990 /* skip read-only or write-only properties */
3991 if (!prop->get || !prop->set) {
3992 continue;
3993 }
3994
3995 /* "hotplugged" is the only property that is configurable
3996 * on the command-line but will be set differently on CPUs
3997 * created using "-cpu ... -smp ..." and by CPUs created
3998 * on the fly by x86_cpu_from_model() for querying. Skip it.
3999 */
4000 if (!strcmp(prop->name, "hotplugged")) {
4001 continue;
4002 }
4003 x86_cpu_expand_prop(cpu, props, prop->name);
4004 }
4005}
4006
f99fd7ca
EH		 4007static void object_apply_props(Object *obj, QDict *props, Error **errp)
4008{
4009 const QDictEntry *prop;
4010 Error *err = NULL;
4011
4012 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4013 object_property_set_qobject(obj, qdict_entry_value(prop),
4014 qdict_entry_key(prop), &err);
4015 if (err) {
4016 break;
4017 }
4018 }
4019
4020 error_propagate(errp, err);
4021}
4022
4023/* Create X86CPU object according to model+props specification */
4024static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4025{
4026 X86CPU *xc = NULL;
4027 X86CPUClass *xcc;
4028 Error *err = NULL;
4029
4030 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4031 if (xcc == NULL) {
4032 error_setg(&err, "CPU model '%s' not found", model);
4033 goto out;
4034 }
4035
4036 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4037 if (props) {
4038 object_apply_props(OBJECT(xc), props, &err);
4039 if (err) {
4040 goto out;
4041 }
4042 }
4043
4044 x86_cpu_expand_features(xc, &err);
4045 if (err) {
4046 goto out;
4047 }
4048
4049out:
4050 if (err) {
4051 error_propagate(errp, err);
4052 object_unref(OBJECT(xc));
4053 xc = NULL;
4054 }
4055 return xc;
4056}
4057
4058CpuModelExpansionInfo *
4059arch_query_cpu_model_expansion(CpuModelExpansionType type,
4060 CpuModelInfo *model,
4061 Error **errp)
4062{
4063 X86CPU *xc = NULL;
4064 Error *err = NULL;
4065 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4066 QDict *props = NULL;
4067 const char *base_name;
4068
4069 xc = x86_cpu_from_model(model->name,
4070 model->has_props ?
7dc847eb 4071 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4072 NULL, &err);
4073 if (err) {
4074 goto out;
4075 }
4076
b8097deb 4077 props = qdict_new();
e38bf612
EH		 4078 ret->model = g_new0(CpuModelInfo, 1);
4079 ret->model->props = QOBJECT(props);
4080 ret->model->has_props = true;
f99fd7ca
EH		 4081
4082 switch (type) {
4083 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4084 /* Static expansion will be based on "base" only */
4085 base_name = "base";
b8097deb 4086 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4087 break;
4088 case CPU_MODEL_EXPANSION_TYPE_FULL:
4089 /* As we don't return every single property, full expansion needs
4090 * to keep the original model name+props, and add extra
4091 * properties on top of that.
4092 */
4093 base_name = model->name;
b8097deb 4094 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4095 break;
4096 default:
df68a7f3 4097 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 4098 goto out;
4099 }
4100
f99fd7ca
EH		 4101 x86_cpu_to_dict(xc, props);
4102
f99fd7ca 4103 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4104
4105out:
4106 object_unref(OBJECT(xc));
4107 if (err) {
4108 error_propagate(errp, err);
4109 qapi_free_CpuModelExpansionInfo(ret);
4110 ret = NULL;
4111 }
4112 return ret;
4113}
4114
00fcd100
AB		 4115static gchar *x86_gdb_arch_name(CPUState *cs)
4116{
4117#ifdef TARGET_X86_64
4118 return g_strdup("i386:x86-64");
4119#else
4120 return g_strdup("i386");
4121#endif
4122}
4123
d940ee9b
EH		 4124static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4125{
4126 X86CPUDefinition *cpudef = data;
4127 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4128
4129 xcc->cpu_def = cpudef;
bd72159d 4130 xcc->migration_safe = true;
d940ee9b
EH		 4131}
4132
4133static void x86_register_cpudef_type(X86CPUDefinition *def)
4134{
4135 char *typename = x86_cpu_type_name(def->name);
4136 TypeInfo ti = {
4137 .name = typename,
4138 .parent = TYPE_X86_CPU,
4139 .class_init = x86_cpu_cpudef_class_init,
4140 .class_data = def,
4141 };
4142
2a923a29
EH		 4143 /* AMD aliases are handled at runtime based on CPUID vendor, so
4144 * they shouldn't be set on the CPU model table.
4145 */
4146 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4147 /* catch mistakes instead of silently truncating model_id when too long */
4148 assert(def->model_id && strlen(def->model_id) <= 48);
4149
2a923a29 4150
d940ee9b
EH		 4151 type_register(&ti);
4152 g_free(typename);
4153}
4154
c6dc6f63 4155#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4156
0e26b7b8
BS		 4157void cpu_clear_apic_feature(CPUX86State *env)
4158{
0514ef2f 4159 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4160}
4161
c6dc6f63
AP		 4162#endif /* !CONFIG_USER_ONLY */
4163
c6dc6f63
AP		 4164void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4165 uint32_t *eax, uint32_t *ebx,
4166 uint32_t *ecx, uint32_t *edx)
4167{
a60f24b5
AF		 4168 X86CPU *cpu = x86_env_get_cpu(env);
4169 CPUState *cs = CPU(cpu);
14c985cf 4170 uint32_t pkg_offset;
4ed3d478 4171 uint32_t limit;
1ce36bfe 4172 uint32_t signature[3];
a60f24b5 4173
4ed3d478
DB		 4174 /* Calculate & apply limits for different index ranges */
4175 if (index >= 0xC0000000) {
4176 limit = env->cpuid_xlevel2;
4177 } else if (index >= 0x80000000) {
4178 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4179 } else if (index >= 0x40000000) {
4180 limit = 0x40000001;
c6dc6f63 4181 } else {
4ed3d478
DB		 4182 limit = env->cpuid_level;
4183 }
4184
4185 if (index > limit) {
4186 /* Intel documentation states that invalid EAX input will
4187 * return the same information as EAX=cpuid_level
4188 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4189 */
4190 index = env->cpuid_level;
c6dc6f63
AP		 4191 }
4192
4193 switch(index) {
4194 case 0:
4195 *eax = env->cpuid_level;
5eb2f7a4
EH		 4196 *ebx = env->cpuid_vendor1;
4197 *edx = env->cpuid_vendor2;
4198 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4199 break;
4200 case 1:
4201 *eax = env->cpuid_version;
7e72a45c
EH		 4202 *ebx = (cpu->apic_id << 24) |
4203 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4204 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4205 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4206 *ecx |= CPUID_EXT_OSXSAVE;
4207 }
0514ef2f 4208 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4209 if (cs->nr_cores * cs->nr_threads > 1) {
4210 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4211 *edx |= CPUID_HT;
c6dc6f63
AP		 4212 }
4213 break;
4214 case 2:
4215 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4216 if (cpu->cache_info_passthrough) {
4217 host_cpuid(index, 0, eax, ebx, ecx, edx);
4218 break;
4219 }
5e891bf8 4220 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4221 *ebx = 0;
14c985cf
LM		 4222 if (!cpu->enable_l3_cache) {
4223 *ecx = 0;
4224 } else {
a9f27ea9 4225 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4226 }
a9f27ea9
EH		 4227 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4228 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4229 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4230 break;
4231 case 4:
4232 /* cache info: needed for Core compatibility */
787aaf57
BC		 4233 if (cpu->cache_info_passthrough) {
4234 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4235 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4236 *eax &= ~0xFC000000;
7e3482f8
EH		 4237 if ((*eax & 31) && cs->nr_cores > 1) {
4238 *eax |= (cs->nr_cores - 1) << 26;
4239 }
c6dc6f63 4240 } else {
2f7a21c4 4241 *eax = 0;
76c2975a 4242 switch (count) {
c6dc6f63 4243 case 0: /* L1 dcache info */
a9f27ea9
EH		 4244 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4245 1, cs->nr_cores,
7e3482f8 4246 eax, ebx, ecx, edx);
c6dc6f63
AP		 4247 break;
4248 case 1: /* L1 icache info */
a9f27ea9
EH		 4249 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4250 1, cs->nr_cores,
7e3482f8 4251 eax, ebx, ecx, edx);
c6dc6f63
AP		 4252 break;
4253 case 2: /* L2 cache info */
a9f27ea9
EH		 4254 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4255 cs->nr_threads, cs->nr_cores,
7e3482f8 4256 eax, ebx, ecx, edx);
c6dc6f63 4257 break;
14c985cf 4258 case 3: /* L3 cache info */
7e3482f8
EH		 4259 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4260 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4261 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4262 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4263 eax, ebx, ecx, edx);
14c985cf
LM		 4264 break;
4265 }
7e3482f8 4266 /* fall through */
c6dc6f63 4267 default: /* end of info */
7e3482f8 4268 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4269 break;
76c2975a
PB		 4270 }
4271 }
c6dc6f63
AP		 4272 break;
4273 case 5:
2266d443
MT		 4274 /* MONITOR/MWAIT Leaf */
4275 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4276 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4277 *ecx = cpu->mwait.ecx; /* flags */
4278 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4279 break;
4280 case 6:
4281 /* Thermal and Power Leaf */
28b8e4d0 4282 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4283 *ebx = 0;
4284 *ecx = 0;
4285 *edx = 0;
4286 break;
f7911686 4287 case 7:
13526728
EH		 4288 /* Structured Extended Feature Flags Enumeration Leaf */
4289 if (count == 0) {
4290 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4291 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4292 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4293 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4294 *ecx |= CPUID_7_0_ECX_OSPKE;
4295 }
95ea69fb 4296 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4297 } else {
4298 *eax = 0;
4299 *ebx = 0;
4300 *ecx = 0;
4301 *edx = 0;
4302 }
4303 break;
c6dc6f63
AP		 4304 case 9:
4305 /* Direct Cache Access Information Leaf */
4306 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4307 *ebx = 0;
4308 *ecx = 0;
4309 *edx = 0;
4310 break;
4311 case 0xA:
4312 /* Architectural Performance Monitoring Leaf */
9337e3b6 4313 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4314 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4315
4316 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4317 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4318 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4319 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4320 } else if (hvf_enabled() && cpu->enable_pmu) {
4321 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4322 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4323 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4324 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4325 } else {
4326 *eax = 0;
4327 *ebx = 0;
4328 *ecx = 0;
4329 *edx = 0;
4330 }
c6dc6f63 4331 break;
5232d00a
RK		 4332 case 0xB:
4333 /* Extended Topology Enumeration Leaf */
4334 if (!cpu->enable_cpuid_0xb) {
4335 *eax = *ebx = *ecx = *edx = 0;
4336 break;
4337 }
4338
4339 *ecx = count & 0xff;
4340 *edx = cpu->apic_id;
4341
4342 switch (count) {
4343 case 0:
eab60fb9
MAL		 4344 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4345 *ebx = cs->nr_threads;
5232d00a
RK		 4346 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4347 break;
4348 case 1:
eab60fb9
MAL		 4349 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4350 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4351 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4352 break;
4353 default:
4354 *eax = 0;
4355 *ebx = 0;
4356 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4357 }
4358
4359 assert(!(*eax & ~0x1f));
4360 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4361 break;
2560f19f 4362 case 0xD: {
51e49430 4363 /* Processor Extended State */
2560f19f
PB		 4364 *eax = 0;
4365 *ebx = 0;
4366 *ecx = 0;
4367 *edx = 0;
19dc85db 4368 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4369 break;
4370 }
4928cd6d 4371
2560f19f 4372 if (count == 0) {
96193c22
EH		 4373 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4374 *eax = env->features[FEAT_XSAVE_COMP_LO];
4375 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4376 *ebx = xsave_area_size(env->xcr0);
2560f19f 4377 } else if (count == 1) {
0bb0b2d2 4378 *eax = env->features[FEAT_XSAVE];
f4f1110e 4379 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4380 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4381 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4382 *eax = esa->size;
4383 *ebx = esa->offset;
2560f19f 4384 }
51e49430
SY		 4385 }
4386 break;
2560f19f 4387 }
e37a5c7f
CP		 4388 case 0x14: {
4389 /* Intel Processor Trace Enumeration */
4390 *eax = 0;
4391 *ebx = 0;
4392 *ecx = 0;
4393 *edx = 0;
4394 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4395 !kvm_enabled()) {
4396 break;
4397 }
4398
4399 if (count == 0) {
4400 *eax = INTEL_PT_MAX_SUBLEAF;
4401 *ebx = INTEL_PT_MINIMAL_EBX;
4402 *ecx = INTEL_PT_MINIMAL_ECX;
4403 } else if (count == 1) {
4404 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4405 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4406 }
4407 break;
4408 }
1ce36bfe
DB		 4409 case 0x40000000:
4410 /*
4411 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4412 * set here, but we restrict to TCG none the less.
4413 */
4414 if (tcg_enabled() && cpu->expose_tcg) {
4415 memcpy(signature, "TCGTCGTCGTCG", 12);
4416 *eax = 0x40000001;
4417 *ebx = signature[0];
4418 *ecx = signature[1];
4419 *edx = signature[2];
4420 } else {
4421 *eax = 0;
4422 *ebx = 0;
4423 *ecx = 0;
4424 *edx = 0;
4425 }
4426 break;
4427 case 0x40000001:
4428 *eax = 0;
4429 *ebx = 0;
4430 *ecx = 0;
4431 *edx = 0;
4432 break;
c6dc6f63
AP		 4433 case 0x80000000:
4434 *eax = env->cpuid_xlevel;
4435 *ebx = env->cpuid_vendor1;
4436 *edx = env->cpuid_vendor2;
4437 *ecx = env->cpuid_vendor3;
4438 break;
4439 case 0x80000001:
4440 *eax = env->cpuid_version;
4441 *ebx = 0;
0514ef2f
EH		 4442 *ecx = env->features[FEAT_8000_0001_ECX];
4443 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4444
4445 /* The Linux kernel checks for the CMPLegacy bit and
4446 * discards multiple thread information if it is set.
cb8d4c8f 4447 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4448 */
ce3960eb 4449 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4450 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4451 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4452 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4453 *ecx |= 1 << 1; /* CmpLegacy bit */
4454 }
4455 }
c6dc6f63
AP		 4456 break;
4457 case 0x80000002:
4458 case 0x80000003:
4459 case 0x80000004:
4460 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4461 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4462 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4463 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4464 break;
4465 case 0x80000005:
4466 /* cache info (L1 cache) */
787aaf57
BC		 4467 if (cpu->cache_info_passthrough) {
4468 host_cpuid(index, 0, eax, ebx, ecx, edx);
4469 break;
4470 }
5e891bf8
EH		 4471 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4472 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4473 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4474 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4475 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4476 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4477 break;
4478 case 0x80000006:
4479 /* cache info (L2 cache) */
787aaf57
BC		 4480 if (cpu->cache_info_passthrough) {
4481 host_cpuid(index, 0, eax, ebx, ecx, edx);
4482 break;
4483 }
5e891bf8
EH		 4484 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4485 (L2_DTLB_2M_ENTRIES << 16) | \
4486 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4487 (L2_ITLB_2M_ENTRIES);
4488 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4489 (L2_DTLB_4K_ENTRIES << 16) | \
4490 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4491 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4492 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4493 cpu->enable_l3_cache ?
4494 env->cache_info_amd.l3_cache : NULL,
4495 ecx, edx);
c6dc6f63 4496 break;
303752a9
MT		 4497 case 0x80000007:
4498 *eax = 0;
4499 *ebx = 0;
4500 *ecx = 0;
4501 *edx = env->features[FEAT_8000_0007_EDX];
4502 break;
c6dc6f63
AP		 4503 case 0x80000008:
4504 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4505 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4506 /* 64 bit processor */
4507 *eax = cpu->phys_bits; /* configurable physical bits */
4508 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4509 *eax |= 0x00003900; /* 57 bits virtual */
4510 } else {
4511 *eax |= 0x00003000; /* 48 bits virtual */
4512 }
c6dc6f63 4513 } else {
af45907a 4514 *eax = cpu->phys_bits;
c6dc6f63 4515 }
1b3420e1 4516 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4517 *ecx = 0;
4518 *edx = 0;
ce3960eb
AF		 4519 if (cs->nr_cores * cs->nr_threads > 1) {
4520 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4521 }
4522 break;
4523 case 0x8000000A:
0514ef2f 4524 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4525 *eax = 0x00000001; /* SVM Revision */
4526 *ebx = 0x00000010; /* nr of ASIDs */
4527 *ecx = 0;
0514ef2f 4528 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4529 } else {
4530 *eax = 0;
4531 *ebx = 0;
4532 *ecx = 0;
4533 *edx = 0;
4534 }
c6dc6f63 4535 break;
8f4202fb
BM		 4536 case 0x8000001D:
4537 *eax = 0;
4538 switch (count) {
4539 case 0: /* L1 dcache info */
4540 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4541 eax, ebx, ecx, edx);
4542 break;
4543 case 1: /* L1 icache info */
4544 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4545 eax, ebx, ecx, edx);
4546 break;
4547 case 2: /* L2 cache info */
4548 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4549 eax, ebx, ecx, edx);
4550 break;
4551 case 3: /* L3 cache info */
4552 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4553 eax, ebx, ecx, edx);
4554 break;
4555 default: /* end of info */
4556 *eax = *ebx = *ecx = *edx = 0;
4557 break;
4558 }
4559 break;
ed78467a
BM		 4560 case 0x8000001E:
4561 assert(cpu->core_id <= 255);
4562 encode_topo_cpuid8000001e(cs, cpu,
4563 eax, ebx, ecx, edx);
4564 break;
b3baa152
BW		 4565 case 0xC0000000:
4566 *eax = env->cpuid_xlevel2;
4567 *ebx = 0;
4568 *ecx = 0;
4569 *edx = 0;
4570 break;
4571 case 0xC0000001:
4572 /* Support for VIA CPU's CPUID instruction */
4573 *eax = env->cpuid_version;
4574 *ebx = 0;
4575 *ecx = 0;
0514ef2f 4576 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4577 break;
4578 case 0xC0000002:
4579 case 0xC0000003:
4580 case 0xC0000004:
4581 /* Reserved for the future, and now filled with zero */
4582 *eax = 0;
4583 *ebx = 0;
4584 *ecx = 0;
4585 *edx = 0;
4586 break;
6cb8f2a6
BS		 4587 case 0x8000001F:
4588 *eax = sev_enabled() ? 0x2 : 0;
4589 *ebx = sev_get_cbit_position();
4590 *ebx |= sev_get_reduced_phys_bits() << 6;
4591 *ecx = 0;
4592 *edx = 0;
4593 break;
c6dc6f63
AP		 4594 default:
4595 /* reserved values: zero */
4596 *eax = 0;
4597 *ebx = 0;
4598 *ecx = 0;
4599 *edx = 0;
4600 break;
4601 }
4602}
5fd2087a
AF		 4603
4604/* CPUClass::reset() */
4605static void x86_cpu_reset(CPUState *s)
4606{
4607 X86CPU *cpu = X86_CPU(s);
4608 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4609 CPUX86State *env = &cpu->env;
a114d25d
RH		 4610 target_ulong cr4;
4611 uint64_t xcr0;
c1958aea
AF		 4612 int i;
4613
5fd2087a
AF		 4614 xcc->parent_reset(s);
4615
5e992a8e 4616 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4617
c1958aea
AF		 4618 env->old_exception = -1;
4619
4620 /* init to reset state */
4621
c1958aea
AF		 4622 env->hflags2 |= HF2_GIF_MASK;
4623
4624 cpu_x86_update_cr0(env, 0x60000010);
4625 env->a20_mask = ~0x0;
4626 env->smbase = 0x30000;
e13713db 4627 env->msr_smi_count = 0;
c1958aea
AF		 4628
4629 env->idt.limit = 0xffff;
4630 env->gdt.limit = 0xffff;
4631 env->ldt.limit = 0xffff;
4632 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4633 env->tr.limit = 0xffff;
4634 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4635
4636 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4637 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4638 DESC_R_MASK | DESC_A_MASK);
4639 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4640 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4641 DESC_A_MASK);
4642 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4643 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4644 DESC_A_MASK);
4645 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4646 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4647 DESC_A_MASK);
4648 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4649 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4650 DESC_A_MASK);
4651 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4652 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4653 DESC_A_MASK);
4654
4655 env->eip = 0xfff0;
4656 env->regs[R_EDX] = env->cpuid_version;
4657
4658 env->eflags = 0x2;
4659
4660 /* FPU init */
4661 for (i = 0; i < 8; i++) {
4662 env->fptags[i] = 1;
4663 }
5bde1407 4664 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4665
4666 env->mxcsr = 0x1f80;
a114d25d
RH		 4667 /* All units are in INIT state. */
4668 env->xstate_bv = 0;
c1958aea
AF		 4669
4670 env->pat = 0x0007040600070406ULL;
4671 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4672
4673 memset(env->dr, 0, sizeof(env->dr));
4674 env->dr[6] = DR6_FIXED_1;
4675 env->dr[7] = DR7_FIXED_1;
b3310ab3 4676 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4677 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4678
a114d25d 4679 cr4 = 0;
cfc3b074 4680 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4681
4682#ifdef CONFIG_USER_ONLY
4683 /* Enable all the features for user-mode. */
4684 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4685 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4686 }
0f70ed47
PB		 4687 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4688 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4689 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4690 xcr0 |= 1ull << i;
4691 }
a114d25d 4692 }
0f70ed47 4693
a114d25d
RH		 4694 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4695 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4696 }
07929f2a
RH		 4697 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4698 cr4 |= CR4_FSGSBASE_MASK;
4699 }
a114d25d
RH		 4700#endif
4701
4702 env->xcr0 = xcr0;
4703 cpu_x86_update_cr4(env, cr4);
0522604b 4704
9db2efd9
AW		 4705 /*
4706 * SDM 11.11.5 requires:
4707 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4708 * - IA32_MTRR_PHYSMASKn.V = 0
4709 * All other bits are undefined. For simplification, zero it all.
4710 */
4711 env->mtrr_deftype = 0;
4712 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4713 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4714
b7394c83
SAGDR		 4715 env->interrupt_injected = -1;
4716 env->exception_injected = -1;
4717 env->nmi_injected = false;
dd673288
IM		 4718#if !defined(CONFIG_USER_ONLY)
4719 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4720 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4721
259186a7 4722 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4723
4724 if (kvm_enabled()) {
4725 kvm_arch_reset_vcpu(cpu);
4726 }
d6dcc558
SAGDR		 4727 else if (hvf_enabled()) {
4728 hvf_reset_vcpu(s);
4729 }
dd673288 4730#endif
5fd2087a
AF		 4731}
4732
dd673288
IM		 4733#ifndef CONFIG_USER_ONLY
4734bool cpu_is_bsp(X86CPU *cpu)
4735{
02e51483 4736 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4737}
65dee380
IM		 4738
4739/* TODO: remove me, when reset over QOM tree is implemented */
4740static void x86_cpu_machine_reset_cb(void *opaque)
4741{
4742 X86CPU *cpu = opaque;
4743 cpu_reset(CPU(cpu));
4744}
dd673288
IM		 4745#endif
4746
de024815
AF		 4747static void mce_init(X86CPU *cpu)
4748{
4749 CPUX86State *cenv = &cpu->env;
4750 unsigned int bank;
4751
4752 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4753 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4754 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4755 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4756 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4757 cenv->mcg_ctl = ~(uint64_t)0;
4758 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4759 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4760 }
4761 }
4762}
4763
bdeec802 4764#ifndef CONFIG_USER_ONLY
2f114315 4765APICCommonClass *apic_get_class(void)
bdeec802 4766{
bdeec802
IM		 4767 const char *apic_type = "apic";
4768
d6dcc558 4769 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4770 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4771 apic_type = "kvm-apic";
4772 } else if (xen_enabled()) {
4773 apic_type = "xen-apic";
4774 }
4775
2f114315
RK		 4776 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4777}
4778
4779static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4780{
4781 APICCommonState *apic;
4782 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4783
4784 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4785
6816b1b3
IM		 4786 object_property_add_child(OBJECT(cpu), "lapic",
4787 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4788 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4789
33d7a288 4790 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4791 /* TODO: convert to link<> */
02e51483 4792 apic = APIC_COMMON(cpu->apic_state);
60671e58 4793 apic->cpu = cpu;
8d42d2d3 4794 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4795}
4796
4797static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4798{
8d42d2d3
CF		 4799 APICCommonState *apic;
4800 static bool apic_mmio_map_once;
4801
02e51483 4802 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4803 return;
4804 }
6e8e2651
MA		 4805 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4806 errp);
8d42d2d3
CF		 4807
4808 /* Map APIC MMIO area */
4809 apic = APIC_COMMON(cpu->apic_state);
4810 if (!apic_mmio_map_once) {
4811 memory_region_add_subregion_overlap(get_system_memory(),
4812 apic->apicbase &
4813 MSR_IA32_APICBASE_BASE,
4814 &apic->io_memory,
4815 0x1000);
4816 apic_mmio_map_once = true;
4817 }
bdeec802 4818}
f809c605
PB		 4819
4820static void x86_cpu_machine_done(Notifier *n, void *unused)
4821{
4822 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4823 MemoryRegion *smram =
4824 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4825
4826 if (smram) {
4827 cpu->smram = g_new(MemoryRegion, 1);
4828 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4829 smram, 0, 1ull << 32);
f8c45c65 4830 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4831 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4832 }
4833}
d3c64d6a
IM		 4834#else
4835static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4836{
4837}
bdeec802
IM		 4838#endif
4839
11f6fee5
DDAG		 4840/* Note: Only safe for use on x86(-64) hosts */
4841static uint32_t x86_host_phys_bits(void)
4842{
4843 uint32_t eax;
4844 uint32_t host_phys_bits;
4845
4846 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4847 if (eax >= 0x80000008) {
4848 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4849 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4850 * at 23:16 that can specify a maximum physical address bits for
4851 * the guest that can override this value; but I've not seen
4852 * anything with that set.
4853 */
4854 host_phys_bits = eax & 0xff;
4855 } else {
4856 /* It's an odd 64 bit machine that doesn't have the leaf for
4857 * physical address bits; fall back to 36 that's most older
4858 * Intel.
4859 */
4860 host_phys_bits = 36;
4861 }
4862
4863 return host_phys_bits;
4864}
e48638fd 4865
c39c0edf
EH		 4866static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4867{
4868 if (*min < value) {
4869 *min = value;
4870 }
4871}
4872
4873/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4874static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4875{
4876 CPUX86State *env = &cpu->env;
4877 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4878 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4879 uint32_t region = eax & 0xF0000000;
4880
07585923 4881 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4882 if (!env->features[w]) {
4883 return;
4884 }
4885
4886 switch (region) {
4887 case 0x00000000:
4888 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4889 break;
4890 case 0x80000000:
4891 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4892 break;
4893 case 0xC0000000:
4894 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4895 break;
4896 }
4897}
4898
2ca8a8be
EH		 4899/* Calculate XSAVE components based on the configured CPU feature flags */
4900static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4901{
4902 CPUX86State *env = &cpu->env;
4903 int i;
96193c22 4904 uint64_t mask;
2ca8a8be
EH		 4905
4906 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4907 return;
4908 }
4909
e3c9022b
EH		 4910 mask = 0;
4911 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4912 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4913 if (env->features[esa->feature] & esa->bits) {
96193c22 4914 mask |= (1ULL << i);
2ca8a8be
EH		 4915 }
4916 }
4917
96193c22
EH		 4918 env->features[FEAT_XSAVE_COMP_LO] = mask;
4919 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4920}
4921
b8d834a0
EH		 4922/***** Steps involved on loading and filtering CPUID data
4923 *
4924 * When initializing and realizing a CPU object, the steps
4925 * involved in setting up CPUID data are:
4926 *
4927 * 1) Loading CPU model definition (X86CPUDefinition). This is
4928 * implemented by x86_cpu_load_def() and should be completely
4929 * transparent, as it is done automatically by instance_init.
4930 * No code should need to look at X86CPUDefinition structs
4931 * outside instance_init.
4932 *
4933 * 2) CPU expansion. This is done by realize before CPUID
4934 * filtering, and will make sure host/accelerator data is
4935 * loaded for CPU models that depend on host capabilities
4936 * (e.g. "host"). Done by x86_cpu_expand_features().
4937 *
4938 * 3) CPUID filtering. This initializes extra data related to
4939 * CPUID, and checks if the host supports all capabilities
4940 * required by the CPU. Runnability of a CPU model is
4941 * determined at this step. Done by x86_cpu_filter_features().
4942 *
4943 * Some operations don't require all steps to be performed.
4944 * More precisely:
4945 *
4946 * - CPU instance creation (instance_init) will run only CPU
4947 * model loading. CPU expansion can't run at instance_init-time
4948 * because host/accelerator data may be not available yet.
4949 * - CPU realization will perform both CPU model expansion and CPUID
4950 * filtering, and return an error in case one of them fails.
4951 * - query-cpu-definitions needs to run all 3 steps. It needs
4952 * to run CPUID filtering, as the 'unavailable-features'
4953 * field is set based on the filtering results.
4954 * - The query-cpu-model-expansion QMP command only needs to run
4955 * CPU model loading and CPU expansion. It should not filter
4956 * any CPUID data based on host capabilities.
4957 */
4958
4959/* Expand CPU configuration data, based on configured features
4960 * and host/accelerator capabilities when appropriate.
4961 */
4962static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4963{
b34d12d1 4964 CPUX86State *env = &cpu->env;
dc15c051 4965 FeatureWord w;
2fae0d96 4966 GList *l;
41f3d4d6 4967 Error *local_err = NULL;
9886e834 4968
d4a606b3
EH		 4969 /*TODO: Now cpu->max_features doesn't overwrite features
4970 * set using QOM properties, and we can convert
dc15c051
IM		 4971 * plus_features & minus_features to global properties
4972 * inside x86_cpu_parse_featurestr() too.
4973 */
44bd8e53 4974 if (cpu->max_features) {
dc15c051 4975 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4976 /* Override only features that weren't set explicitly
4977 * by the user.
4978 */
4979 env->features[w] |=
4980 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4981 ~env->user_features[w] & \
4982 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4983 }
4984 }
4985
2fae0d96
EH		 4986 for (l = plus_features; l; l = l->next) {
4987 const char *prop = l->data;
4988 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4989 if (local_err) {
4990 goto out;
4991 }
4992 }
4993
4994 for (l = minus_features; l; l = l->next) {
4995 const char *prop = l->data;
4996 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
4997 if (local_err) {
4998 goto out;
4999 }
dc15c051
IM		 5000 }
5001
aec661de
EH		 5002 if (!kvm_enabled() || !cpu->expose_kvm) {
5003 env->features[FEAT_KVM] = 0;
5004 }
5005
2ca8a8be 5006 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5007
5008 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5009 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5010 if (cpu->full_cpuid_auto_level) {
5011 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5012 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5013 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5014 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5015 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5016 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5017 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5018 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5019 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5020 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5021 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
0c3d7c00
EH		 5022 /* SVM requires CPUID[0x8000000A] */
5023 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5024 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5025 }
6cb8f2a6
BS		 5026
5027 /* SEV requires CPUID[0x8000001F] */
5028 if (sev_enabled()) {
5029 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5030 }
c39c0edf
EH		 5031 }
5032
5033 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5034 if (env->cpuid_level == UINT32_MAX) {
5035 env->cpuid_level = env->cpuid_min_level;
5036 }
5037 if (env->cpuid_xlevel == UINT32_MAX) {
5038 env->cpuid_xlevel = env->cpuid_min_xlevel;
5039 }
5040 if (env->cpuid_xlevel2 == UINT32_MAX) {
5041 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5042 }
7a059953 5043
41f3d4d6
EH		 5044out:
5045 if (local_err != NULL) {
5046 error_propagate(errp, local_err);
5047 }
5048}
5049
b8d834a0
EH		 5050/*
5051 * Finishes initialization of CPUID data, filters CPU feature
5052 * words based on host availability of each feature.
5053 *
5054 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5055 */
5056static int x86_cpu_filter_features(X86CPU *cpu)
5057{
5058 CPUX86State *env = &cpu->env;
5059 FeatureWord w;
5060 int rv = 0;
5061
5062 for (w = 0; w < FEATURE_WORDS; w++) {
5063 uint32_t host_feat =
5064 x86_cpu_get_supported_feature_word(w, false);
5065 uint32_t requested_features = env->features[w];
5066 env->features[w] &= host_feat;
5067 cpu->filtered_features[w] = requested_features & ~env->features[w];
5068 if (cpu->filtered_features[w]) {
5069 rv = 1;
5070 }
5071 }
5072
e37a5c7f
CP		 5073 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5074 kvm_enabled()) {
5075 KVMState *s = CPU(cpu)->kvm_state;
5076 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5077 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5078 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5079 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5080 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5081
5082 if (!eax_0 ||
5083 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5084 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5085 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5086 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5087 INTEL_PT_ADDR_RANGES_NUM) ||
5088 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5089 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5090 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5091 /*
5092 * Processor Trace capabilities aren't configurable, so if the
5093 * host can't emulate the capabilities we report on
5094 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5095 */
5096 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5097 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5098 rv = 1;
5099 }
5100 }
5101
b8d834a0
EH		 5102 return rv;
5103}
5104
41f3d4d6
EH		 5105#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5106 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5107 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5108#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5109 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5110 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5111static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5112{
5113 CPUState *cs = CPU(dev);
5114 X86CPU *cpu = X86_CPU(dev);
5115 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5116 CPUX86State *env = &cpu->env;
5117 Error *local_err = NULL;
5118 static bool ht_warned;
5119
2266d443
MT		 5120 if (xcc->host_cpuid_required) {
5121 if (!accel_uses_host_cpuid()) {
5122 char *name = x86_cpu_class_get_model_name(xcc);
5123 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5124 g_free(name);
5125 goto out;
5126 }
5127
5128 if (enable_cpu_pm) {
5129 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5130 &cpu->mwait.ecx, &cpu->mwait.edx);
5131 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5132 }
41f3d4d6
EH		 5133 }
5134
2266d443
MT		 5135 /* mwait extended info: needed for Core compatibility */
5136 /* We always wake on interrupt even if host does not have the capability */
5137 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5138
41f3d4d6
EH		 5139 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5140 error_setg(errp, "apic-id property was not initialized properly");
5141 return;
5142 }
5143
b8d834a0 5144 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5145 if (local_err) {
5146 goto out;
5147 }
5148
8ca30e86
EH		 5149 if (x86_cpu_filter_features(cpu) &&
5150 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5151 x86_cpu_report_filtered_features(cpu);
5152 if (cpu->enforce_cpuid) {
5153 error_setg(&local_err,
d6dcc558 5154 accel_uses_host_cpuid() ?
8ca30e86
EH		 5155 "Host doesn't support requested features" :
5156 "TCG doesn't support requested features");
5157 goto out;
5158 }
9997cf7b
EH		 5159 }
5160
9b15cd9e
IM		 5161 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5162 * CPUID[1].EDX.
5163 */
e48638fd 5164 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5165 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5166 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5167 & CPUID_EXT2_AMD_ALIASES);
5168 }
5169
11f6fee5
DDAG		 5170 /* For 64bit systems think about the number of physical bits to present.
5171 * ideally this should be the same as the host; anything other than matching
5172 * the host can cause incorrect guest behaviour.
5173 * QEMU used to pick the magic value of 40 bits that corresponds to
5174 * consumer AMD devices but nothing else.
5175 */
af45907a 5176 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5177 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5178 uint32_t host_phys_bits = x86_host_phys_bits();
5179 static bool warned;
5180
5181 if (cpu->host_phys_bits) {
5182 /* The user asked for us to use the host physical bits */
5183 cpu->phys_bits = host_phys_bits;
5184 }
5185
5186 /* Print a warning if the user set it to a value that's not the
5187 * host value.
5188 */
5189 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5190 !warned) {
3dc6f869
AF		 5191 warn_report("Host physical bits (%u)"
5192 " does not match phys-bits property (%u)",
5193 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5194 warned = true;
5195 }
5196
5197 if (cpu->phys_bits &&
5198 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5199 cpu->phys_bits < 32)) {
af45907a
DDAG		 5200 error_setg(errp, "phys-bits should be between 32 and %u "
5201 " (but is %u)",
5202 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5203 return;
5204 }
5205 } else {
11f6fee5 5206 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5207 error_setg(errp, "TCG only supports phys-bits=%u",
5208 TCG_PHYS_ADDR_BITS);
5209 return;
5210 }
5211 }
11f6fee5
DDAG		 5212 /* 0 means it was not explicitly set by the user (or by machine
5213 * compat_props or by the host code above). In this case, the default
5214 * is the value used by TCG (40).
5215 */
5216 if (cpu->phys_bits == 0) {
5217 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5218 }
af45907a
DDAG		 5219 } else {
5220 /* For 32 bit systems don't use the user set value, but keep
5221 * phys_bits consistent with what we tell the guest.
5222 */
5223 if (cpu->phys_bits != 0) {
5224 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5225 return;
5226 }
fefb41bf 5227
af45907a
DDAG		 5228 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5229 cpu->phys_bits = 36;
5230 } else {
5231 cpu->phys_bits = 32;
5232 }
5233 }
a9f27ea9
EH		 5234
5235 /* Cache information initialization */
5236 if (!cpu->legacy_cache) {
5237 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5238 char *name = x86_cpu_class_get_model_name(xcc);
5239 error_setg(errp,
5240 "CPU model '%s' doesn't support legacy-cache=off", name);
5241 g_free(name);
5242 return;
5243 }
5244 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5245 *xcc->cpu_def->cache_info;
5246 } else {
5247 /* Build legacy cache information */
5248 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5249 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5250 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5251 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5252
5253 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5254 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5255 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5256 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5257
5258 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5259 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5260 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5261 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5262 }
5263
5264
ce5b1bbf
LV		 5265 cpu_exec_realizefn(cs, &local_err);
5266 if (local_err != NULL) {
5267 error_propagate(errp, local_err);
5268 return;
5269 }
42ecabaa 5270
65dee380
IM		 5271#ifndef CONFIG_USER_ONLY
5272 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5273
0514ef2f 5274 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5275 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5276 if (local_err != NULL) {
4dc1f449 5277 goto out;
bdeec802
IM		 5278 }
5279 }
65dee380
IM		 5280#endif
5281
7a059953 5282 mce_init(cpu);
2001d0cd
PB		 5283
5284#ifndef CONFIG_USER_ONLY
5285 if (tcg_enabled()) {
f809c605 5286 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5287 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5288
5289 /* Outer container... */
5290 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5291 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5292
5293 /* ... with two regions inside: normal system memory with low
5294 * priority, and...
5295 */
5296 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5297 get_system_memory(), 0, ~0ull);
5298 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5299 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5300
5301 cs->num_ases = 2;
80ceb07a
PX		 5302 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5303 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5304
5305 /* ... SMRAM with higher priority, linked from /machine/smram. */
5306 cpu->machine_done.notify = x86_cpu_machine_done;
5307 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5308 }
5309#endif
5310
14a10fc3 5311 qemu_init_vcpu(cs);
d3c64d6a 5312
6b2942f9
BM		 5313 /*
5314 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5315 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5316 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5317 * users a warning.
5318 *
5319 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5320 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5321 */
0765691e
MA		 5322 if (IS_AMD_CPU(env) &&
5323 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5324 cs->nr_threads > 1 && !ht_warned) {
5325 warn_report("This family of AMD CPU doesn't support "
5326 "hyperthreading(%d)",
5327 cs->nr_threads);
5328 error_printf("Please configure -smp options properly"
5329 " or try enabling topoext feature.\n");
5330 ht_warned = true;
e48638fd
WH		 5331 }
5332
d3c64d6a
IM		 5333 x86_cpu_apic_realize(cpu, &local_err);
5334 if (local_err != NULL) {
5335 goto out;
5336 }
14a10fc3 5337 cpu_reset(cs);
2b6f294c 5338
4dc1f449 5339 xcc->parent_realize(dev, &local_err);
2001d0cd 5340
4dc1f449
IM		 5341out:
5342 if (local_err != NULL) {
5343 error_propagate(errp, local_err);
5344 return;
5345 }
7a059953
AF		 5346}
5347
c884776e
IM		 5348static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5349{
5350 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5351 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5352 Error *local_err = NULL;
c884776e
IM		 5353
5354#ifndef CONFIG_USER_ONLY
5355 cpu_remove_sync(CPU(dev));
5356 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5357#endif
5358
5359 if (cpu->apic_state) {
5360 object_unparent(OBJECT(cpu->apic_state));
5361 cpu->apic_state = NULL;
5362 }
7bbc124e
LV		 5363
5364 xcc->parent_unrealize(dev, &local_err);
5365 if (local_err != NULL) {
5366 error_propagate(errp, local_err);
5367 return;
5368 }
c884776e
IM		 5369}
5370
38e5c119 5371typedef struct BitProperty {
a7b0ffac 5372 FeatureWord w;
38e5c119
EH		 5373 uint32_t mask;
5374} BitProperty;
5375
d7bce999
EB		 5376static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5377 void *opaque, Error **errp)
38e5c119 5378{
a7b0ffac 5379 X86CPU *cpu = X86_CPU(obj);
38e5c119 5380 BitProperty *fp = opaque;
a7b0ffac
EH		 5381 uint32_t f = cpu->env.features[fp->w];
5382 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5383 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5384}
5385
d7bce999
EB		 5386static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5387 void *opaque, Error **errp)
38e5c119
EH		 5388{
5389 DeviceState *dev = DEVICE(obj);
a7b0ffac 5390 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5391 BitProperty *fp = opaque;
5392 Error *local_err = NULL;
5393 bool value;
5394
5395 if (dev->realized) {
5396 qdev_prop_set_after_realize(dev, name, errp);
5397 return;
5398 }
5399
51e72bc1 5400 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5401 if (local_err) {
5402 error_propagate(errp, local_err);
5403 return;
5404 }
5405
5406 if (value) {
a7b0ffac 5407 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5408 } else {
a7b0ffac 5409 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5410 }
d4a606b3 5411 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5412}
5413
5414static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5415 void *opaque)
5416{
5417 BitProperty *prop = opaque;
5418 g_free(prop);
5419}
5420
5421/* Register a boolean property to get/set a single bit in a uint32_t field.
5422 *
5423 * The same property name can be registered multiple times to make it affect
5424 * multiple bits in the same FeatureWord. In that case, the getter will return
5425 * true only if all bits are set.
5426 */
5427static void x86_cpu_register_bit_prop(X86CPU *cpu,
5428 const char *prop_name,
a7b0ffac 5429 FeatureWord w,
38e5c119
EH		 5430 int bitnr)
5431{
5432 BitProperty *fp;
5433 ObjectProperty *op;
5434 uint32_t mask = (1UL << bitnr);
5435
5436 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5437 if (op) {
5438 fp = op->opaque;
a7b0ffac 5439 assert(fp->w == w);
38e5c119
EH		 5440 fp->mask |= mask;
5441 } else {
5442 fp = g_new0(BitProperty, 1);
a7b0ffac 5443 fp->w = w;
38e5c119
EH		 5444 fp->mask = mask;
5445 object_property_add(OBJECT(cpu), prop_name, "bool",
5446 x86_cpu_get_bit_prop,
5447 x86_cpu_set_bit_prop,
5448 x86_cpu_release_bit_prop, fp, &error_abort);
5449 }
5450}
5451
5452static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5453 FeatureWord w,
5454 int bitnr)
5455{
38e5c119 5456 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5457 const char *name = fi->feat_names[bitnr];
38e5c119 5458
16d2fcaa 5459 if (!name) {
38e5c119
EH		 5460 return;
5461 }
5462
fc7dfd20
EH		 5463 /* Property names should use "-" instead of "_".
5464 * Old names containing underscores are registered as aliases
5465 * using object_property_add_alias()
5466 */
16d2fcaa
EH		 5467 assert(!strchr(name, '_'));
5468 /* aliases don't use "|" delimiters anymore, they are registered
5469 * manually using object_property_add_alias() */
5470 assert(!strchr(name, '|'));
a7b0ffac 5471 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5472}
5473
d187e08d
AN		 5474static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5475{
5476 X86CPU *cpu = X86_CPU(cs);
5477 CPUX86State *env = &cpu->env;
5478 GuestPanicInformation *panic_info = NULL;
5479
5e953812 5480 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5481 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5482
e8ed97a6 5483 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5484
5e953812 5485 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5486 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5487 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5488 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5489 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5490 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5491 }
5492
5493 return panic_info;
5494}
5495static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5496 const char *name, void *opaque,
5497 Error **errp)
5498{
5499 CPUState *cs = CPU(obj);
5500 GuestPanicInformation *panic_info;
5501
5502 if (!cs->crash_occurred) {
5503 error_setg(errp, "No crash occured");
5504 return;
5505 }
5506
5507 panic_info = x86_cpu_get_crash_info(cs);
5508 if (panic_info == NULL) {
5509 error_setg(errp, "No crash information");
5510 return;
5511 }
5512
5513 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5514 errp);
5515 qapi_free_GuestPanicInformation(panic_info);
5516}
5517
de024815
AF		 5518static void x86_cpu_initfn(Object *obj)
5519{
55e5c285 5520 CPUState *cs = CPU(obj);
de024815 5521 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5522 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5523 CPUX86State *env = &cpu->env;
38e5c119 5524 FeatureWord w;
de024815 5525
c05efcb1 5526 cs->env_ptr = env;
71ad61d3
AF		 5527
5528 object_property_add(obj, "family", "int",
95b8519d 5529 x86_cpuid_version_get_family,
71ad61d3 5530 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5531 object_property_add(obj, "model", "int",
67e30c83 5532 x86_cpuid_version_get_model,
c5291a4f 5533 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5534 object_property_add(obj, "stepping", "int",
35112e41 5535 x86_cpuid_version_get_stepping,
036e2222 5536 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5537 object_property_add_str(obj, "vendor",
5538 x86_cpuid_get_vendor,
5539 x86_cpuid_set_vendor, NULL);
938d4c25 5540 object_property_add_str(obj, "model-id",
63e886eb 5541 x86_cpuid_get_model_id,
938d4c25 5542 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5543 object_property_add(obj, "tsc-frequency", "int",
5544 x86_cpuid_get_tsc_freq,
5545 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5546 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5547 x86_cpu_get_feature_words,
7e5292b5
EH		 5548 NULL, NULL, (void *)env->features, NULL);
5549 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5550 x86_cpu_get_feature_words,
5551 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5552
d187e08d
AN		 5553 object_property_add(obj, "crash-information", "GuestPanicInformation",
5554 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5555
92067bf4 5556 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5557
38e5c119
EH		 5558 for (w = 0; w < FEATURE_WORDS; w++) {
5559 int bitnr;
5560
5561 for (bitnr = 0; bitnr < 32; bitnr++) {
5562 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5563 }
5564 }
5565
16d2fcaa
EH		 5566 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5567 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5568 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5569 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5570 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5571 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5572 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5573
54b8dc7c
EH		 5574 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5575 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5576 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5577 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5578 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5579 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5580 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5581 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5582 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5583 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5584 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5585 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5586 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5587 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5588 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5589 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5590 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5591 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5592 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5593 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5594 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5595
0bacd8b3
EH		 5596 if (xcc->cpu_def) {
5597 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5598 }
de024815
AF		 5599}
5600
997395d3
IM		 5601static int64_t x86_cpu_get_arch_id(CPUState *cs)
5602{
5603 X86CPU *cpu = X86_CPU(cs);
997395d3 5604
7e72a45c 5605 return cpu->apic_id;
997395d3
IM		 5606}
5607
444d5590
AF		 5608static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5609{
5610 X86CPU *cpu = X86_CPU(cs);
5611
5612 return cpu->env.cr[0] & CR0_PG_MASK;
5613}
5614
f45748f1
AF		 5615static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5616{
5617 X86CPU *cpu = X86_CPU(cs);
5618
5619 cpu->env.eip = value;
5620}
5621
bdf7ae5b
AF		 5622static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5623{
5624 X86CPU *cpu = X86_CPU(cs);
5625
5626 cpu->env.eip = tb->pc - tb->cs_base;
5627}
5628
92d5f1a4 5629int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5630{
5631 X86CPU *cpu = X86_CPU(cs);
5632 CPUX86State *env = &cpu->env;
5633
92d5f1a4
PB		 5634#if !defined(CONFIG_USER_ONLY)
5635 if (interrupt_request & CPU_INTERRUPT_POLL) {
5636 return CPU_INTERRUPT_POLL;
5637 }
5638#endif
5639 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5640 return CPU_INTERRUPT_SIPI;
5641 }
5642
5643 if (env->hflags2 & HF2_GIF_MASK) {
5644 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5645 !(env->hflags & HF_SMM_MASK)) {
5646 return CPU_INTERRUPT_SMI;
5647 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5648 !(env->hflags2 & HF2_NMI_MASK)) {
5649 return CPU_INTERRUPT_NMI;
5650 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5651 return CPU_INTERRUPT_MCE;
5652 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5653 (((env->hflags2 & HF2_VINTR_MASK) &&
5654 (env->hflags2 & HF2_HIF_MASK)) ||
5655 (!(env->hflags2 & HF2_VINTR_MASK) &&
5656 (env->eflags & IF_MASK &&
5657 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5658 return CPU_INTERRUPT_HARD;
5659#if !defined(CONFIG_USER_ONLY)
5660 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5661 (env->eflags & IF_MASK) &&
5662 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5663 return CPU_INTERRUPT_VIRQ;
5664#endif
5665 }
5666 }
5667
5668 return 0;
5669}
5670
5671static bool x86_cpu_has_work(CPUState *cs)
5672{
5673 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5674}
5675
f50f3dd5
RH		 5676static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5677{
5678 X86CPU *cpu = X86_CPU(cs);
5679 CPUX86State *env = &cpu->env;
5680
5681 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5682 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5683 : bfd_mach_i386_i8086);
5684 info->print_insn = print_insn_i386;
b666d2a4
RH		 5685
5686 info->cap_arch = CS_ARCH_X86;
5687 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5688 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5689 : CS_MODE_16);
15fa1a0a
RH		 5690 info->cap_insn_unit = 1;
5691 info->cap_insn_split = 8;
f50f3dd5
RH		 5692}
5693
35b1b927
TW		 5694void x86_update_hflags(CPUX86State *env)
5695{
5696 uint32_t hflags;
5697#define HFLAG_COPY_MASK \
5698 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5699 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5700 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5701 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5702
5703 hflags = env->hflags & HFLAG_COPY_MASK;
5704 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5705 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5706 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5707 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5708 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5709
5710 if (env->cr[4] & CR4_OSFXSR_MASK) {
5711 hflags |= HF_OSFXSR_MASK;
5712 }
5713
5714 if (env->efer & MSR_EFER_LMA) {
5715 hflags |= HF_LMA_MASK;
5716 }
5717
5718 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5719 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5720 } else {
5721 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5722 (DESC_B_SHIFT - HF_CS32_SHIFT);
5723 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5724 (DESC_B_SHIFT - HF_SS32_SHIFT);
5725 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5726 !(hflags & HF_CS32_MASK)) {
5727 hflags |= HF_ADDSEG_MASK;
5728 } else {
5729 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5730 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5731 }
5732 }
5733 env->hflags = hflags;
5734}
5735
9337e3b6 5736static Property x86_cpu_properties[] = {
2da00e31
IM		 5737#ifdef CONFIG_USER_ONLY
5738 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5739 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5740 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5741 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5742 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5743#else
5744 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5745 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5746 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5747 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5748#endif
15f8b142 5749 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5750 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5751 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5752 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5753 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5754 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5755 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5756 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5757 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5758 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5759 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5760 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5761 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5762 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5763 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
e204ac61 5764 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
6b7a9830 5765 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5766 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5767 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5768 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5769 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5770 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
fcc35e7c 5771 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5772 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5773 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5774 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5775 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5776 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5777 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5778 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5779 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5780 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5781 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5782 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5783 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5784 false),
0b564e6f 5785 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5786 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5787 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5788 true),
ab8f992e 5789 /*
a9f27ea9
EH		 5790 * lecacy_cache defaults to true unless the CPU model provides its
5791 * own cache information (see x86_cpu_load_def()).
ab8f992e 5792 */
a9f27ea9 5793 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5794
5795 /*
5796 * From "Requirements for Implementing the Microsoft
5797 * Hypervisor Interface":
5798 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5799 *
5800 * "Starting with Windows Server 2012 and Windows 8, if
5801 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5802 * the hypervisor imposes no specific limit to the number of VPs.
5803 * In this case, Windows Server 2012 guest VMs may use more than
5804 * 64 VPs, up to the maximum supported number of processors applicable
5805 * to the specific Windows version being used."
5806 */
5807 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5808 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5809 false),
9337e3b6
EH		 5810 DEFINE_PROP_END_OF_LIST()
5811};
5812
5fd2087a
AF		 5813static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5814{
5815 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5816 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5817 DeviceClass *dc = DEVICE_CLASS(oc);
5818
bf853881
PMD		 5819 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5820 &xcc->parent_realize);
5821 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5822 &xcc->parent_unrealize);
9337e3b6 5823 dc->props = x86_cpu_properties;
5fd2087a
AF		 5824
5825 xcc->parent_reset = cc->reset;
5826 cc->reset = x86_cpu_reset;
91b1df8c 5827 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5828
500050d1 5829 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5830 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5831 cc->has_work = x86_cpu_has_work;
79c664f6 5832#ifdef CONFIG_TCG
97a8ea5a 5833 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5834 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5835#endif
878096ee 5836 cc->dump_state = x86_cpu_dump_state;
c86f106b 5837 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5838 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5839 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5840 cc->gdb_read_register = x86_cpu_gdb_read_register;
5841 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5842 cc->get_arch_id = x86_cpu_get_arch_id;
5843 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5844#ifdef CONFIG_USER_ONLY
5845 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5846#else
f8c45c65 5847 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5848 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5849 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5850 cc->write_elf64_note = x86_cpu_write_elf64_note;
5851 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5852 cc->write_elf32_note = x86_cpu_write_elf32_note;
5853 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5854 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5855#endif
00fcd100
AB		 5856 cc->gdb_arch_name = x86_gdb_arch_name;
5857#ifdef TARGET_X86_64
b8158192
AB		 5858 cc->gdb_core_xml_file = "i386-64bit.xml";
5859 cc->gdb_num_core_regs = 57;
00fcd100 5860#else
b8158192
AB		 5861 cc->gdb_core_xml_file = "i386-32bit.xml";
5862 cc->gdb_num_core_regs = 41;
00fcd100 5863#endif
79c664f6 5864#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5865 cc->debug_excp_handler = breakpoint_handler;
5866#endif
374e0cd4
RH		 5867 cc->cpu_exec_enter = x86_cpu_exec_enter;
5868 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5869#ifdef CONFIG_TCG
55c3ceef 5870 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5871#endif
f50f3dd5 5872 cc->disas_set_info = x86_disas_set_info;
4c315c27 5873
e90f2a8c 5874 dc->user_creatable = true;
5fd2087a
AF		 5875}
5876
5877static const TypeInfo x86_cpu_type_info = {
5878 .name = TYPE_X86_CPU,
5879 .parent = TYPE_CPU,
5880 .instance_size = sizeof(X86CPU),
de024815 5881 .instance_init = x86_cpu_initfn,
d940ee9b 5882 .abstract = true,
5fd2087a
AF		 5883 .class_size = sizeof(X86CPUClass),
5884 .class_init = x86_cpu_common_class_init,
5885};
5886
5adbed30
EH		 5887
5888/* "base" CPU model, used by query-cpu-model-expansion */
5889static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5890{
5891 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5892
5893 xcc->static_model = true;
5894 xcc->migration_safe = true;
5895 xcc->model_description = "base CPU model type with no features enabled";
5896 xcc->ordering = 8;
5897}
5898
5899static const TypeInfo x86_base_cpu_type_info = {
5900 .name = X86_CPU_TYPE_NAME("base"),
5901 .parent = TYPE_X86_CPU,
5902 .class_init = x86_cpu_base_class_init,
5903};
5904
5fd2087a
AF		 5905static void x86_cpu_register_types(void)
5906{
d940ee9b
EH		 5907 int i;
5908
5fd2087a 5909 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5910 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5911 x86_register_cpudef_type(&builtin_x86_defs[i]);
5912 }
c62f2630 5913 type_register_static(&max_x86_cpu_type_info);
5adbed30 5914 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5915#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5916 type_register_static(&host_x86_cpu_type_info);
5917#endif
5fd2087a
AF		 5918}
5919
5920type_init(x86_cpu_register_types)
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