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i386/kvm: document existing Hyper-V enlightenments
[mirror_qemu.git] / target / i386 / cpu.c
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c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
0442428a 24#include "qemu/qemu-print.h"
c6dc6f63
AP		 25
26#include "cpu.h"
63c91552 27#include "exec/exec-all.h"
9c17d615 28#include "sysemu/kvm.h"
d6dcc558 29#include "sysemu/hvf.h"
8932cfdf 30#include "sysemu/cpus.h"
50a2c6e5 31#include "kvm_i386.h"
6cb8f2a6 32#include "sev_i386.h"
c6dc6f63 33
d49b6836 34#include "qemu/error-report.h"
0b8fa32f 35#include "qemu/module.h"
1de7afc9
PB		 36#include "qemu/option.h"
37#include "qemu/config-file.h"
e688df6b 38#include "qapi/error.h"
112ed241
MA		 39#include "qapi/qapi-visit-misc.h"
40#include "qapi/qapi-visit-run-state.h"
452fcdbc 41#include "qapi/qmp/qdict.h"
7b1b5d19 42#include "qapi/qmp/qerror.h"
7b1b5d19 43#include "qapi/visitor.h"
f99fd7ca 44#include "qom/qom-qobject.h"
9c17d615 45#include "sysemu/arch_init.h"
96f75b59 46#include "qapi/qapi-commands-target.h"
71ad61d3 47
1814eab6 48#include "standard-headers/asm-x86/kvm_para.h"
65dee380 49
9c17d615 50#include "sysemu/sysemu.h"
14a48c1d 51#include "sysemu/tcg.h"
53a89e26 52#include "hw/qdev-properties.h"
5232d00a 53#include "hw/i386/topology.h"
bdeec802 54#ifndef CONFIG_USER_ONLY
2001d0cd 55#include "exec/address-spaces.h"
741da0d3 56#include "hw/hw.h"
0d09e41a 57#include "hw/xen/xen.h"
0d09e41a 58#include "hw/i386/apic_internal.h"
bdeec802
IM		 59#endif
60
b666d2a4
RH		 61#include "disas/capstone.h"
62
7e3482f8
EH		 63/* Helpers for building CPUID[2] descriptors: */
64
65struct CPUID2CacheDescriptorInfo {
66 enum CacheType type;
67 int level;
68 int size;
69 int line_size;
70 int associativity;
71};
5e891bf8 72
7e3482f8
EH		 73/*
74 * Known CPUID 2 cache descriptors.
75 * From Intel SDM Volume 2A, CPUID instruction
76 */
77struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 78 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 32, },
5f00335a 80 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 81 .associativity = 4, .line_size = 32, },
5f00335a 82 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 83 .associativity = 4, .line_size = 64, },
5f00335a 84 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 85 .associativity = 2, .line_size = 32, },
5f00335a 86 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 87 .associativity = 4, .line_size = 32, },
5f00335a 88 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 89 .associativity = 4, .line_size = 64, },
5f00335a 90 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 91 .associativity = 6, .line_size = 64, },
5f00335a 92 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 93 .associativity = 2, .line_size = 64, },
5f00335a 94 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 95 .associativity = 8, .line_size = 64, },
96 /* lines per sector is not supported cpuid2_cache_descriptor(),
97 * so descriptors 0x22, 0x23 are not included
98 */
5f00335a 99 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 100 .associativity = 16, .line_size = 64, },
101 /* lines per sector is not supported cpuid2_cache_descriptor(),
102 * so descriptors 0x25, 0x20 are not included
103 */
5f00335a 104 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 105 .associativity = 8, .line_size = 64, },
5f00335a 106 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 107 .associativity = 8, .line_size = 64, },
5f00335a 108 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 32, },
5f00335a 116 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 117 .associativity = 4, .line_size = 32, },
5f00335a 118 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 119 .associativity = 4, .line_size = 64, },
5f00335a 120 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 121 .associativity = 8, .line_size = 64, },
5f00335a 122 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 123 .associativity = 12, .line_size = 64, },
124 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 125 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 126 .associativity = 12, .line_size = 64, },
5f00335a 127 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 128 .associativity = 16, .line_size = 64, },
5f00335a 129 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 130 .associativity = 12, .line_size = 64, },
5f00335a 131 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 132 .associativity = 16, .line_size = 64, },
5f00335a 133 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 134 .associativity = 24, .line_size = 64, },
5f00335a 135 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 136 .associativity = 8, .line_size = 64, },
5f00335a 137 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 140 .associativity = 4, .line_size = 64, },
5f00335a 141 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 142 .associativity = 4, .line_size = 64, },
5f00335a 143 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 144 .associativity = 4, .line_size = 64, },
145 /* lines per sector is not supported cpuid2_cache_descriptor(),
146 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
147 */
5f00335a 148 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 2, .line_size = 64, },
5f00335a 152 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 64, },
5f00335a 154 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 159 .associativity = 8, .line_size = 32, },
5f00335a 160 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 32, },
5f00335a 162 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 163 .associativity = 4, .line_size = 64, },
5f00335a 164 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 165 .associativity = 8, .line_size = 64, },
5f00335a 166 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 169 .associativity = 4, .line_size = 64, },
5f00335a 170 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 171 .associativity = 4, .line_size = 64, },
5f00335a 172 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 175 .associativity = 8, .line_size = 64, },
5f00335a 176 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 177 .associativity = 8, .line_size = 64, },
5f00335a 178 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 181 .associativity = 12, .line_size = 64, },
5f00335a 182 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 183 .associativity = 12, .line_size = 64, },
5f00335a 184 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 187 .associativity = 16, .line_size = 64, },
5f00335a 188 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 189 .associativity = 16, .line_size = 64, },
5f00335a 190 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 191 .associativity = 24, .line_size = 64, },
5f00335a 192 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 193 .associativity = 24, .line_size = 64, },
5f00335a 194 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 195 .associativity = 24, .line_size = 64, },
196};
197
198/*
199 * "CPUID leaf 2 does not report cache descriptor information,
200 * use CPUID leaf 4 to query cache parameters"
201 */
202#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 203
7e3482f8
EH		 204/*
205 * Return a CPUID 2 cache descriptor for a given cache.
206 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
207 */
208static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
209{
210 int i;
211
212 assert(cache->size > 0);
213 assert(cache->level > 0);
214 assert(cache->line_size > 0);
215 assert(cache->associativity > 0);
216 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
217 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
218 if (d->level == cache->level && d->type == cache->type &&
219 d->size == cache->size && d->line_size == cache->line_size &&
220 d->associativity == cache->associativity) {
221 return i;
222 }
223 }
5e891bf8 224
7e3482f8
EH		 225 return CACHE_DESCRIPTOR_UNAVAILABLE;
226}
5e891bf8
EH		 227
228/* CPUID Leaf 4 constants: */
229
230/* EAX: */
7e3482f8
EH		 231#define CACHE_TYPE_D 1
232#define CACHE_TYPE_I 2
233#define CACHE_TYPE_UNIFIED 3
5e891bf8 234
7e3482f8 235#define CACHE_LEVEL(l) (l << 5)
5e891bf8 236
7e3482f8 237#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 238
239/* EDX: */
7e3482f8
EH		 240#define CACHE_NO_INVD_SHARING (1 << 0)
241#define CACHE_INCLUSIVE (1 << 1)
242#define CACHE_COMPLEX_IDX (1 << 2)
243
244/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 245#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
246 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
247 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
248 0 /* Invalid value */)
7e3482f8
EH		 249
250
251/* Encode cache info for CPUID[4] */
252static void encode_cache_cpuid4(CPUCacheInfo *cache,
253 int num_apic_ids, int num_cores,
254 uint32_t *eax, uint32_t *ebx,
255 uint32_t *ecx, uint32_t *edx)
256{
257 assert(cache->size == cache->line_size * cache->associativity *
258 cache->partitions * cache->sets);
259
260 assert(num_apic_ids > 0);
261 *eax = CACHE_TYPE(cache->type) |
262 CACHE_LEVEL(cache->level) |
263 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
264 ((num_cores - 1) << 26) |
265 ((num_apic_ids - 1) << 14);
266
267 assert(cache->line_size > 0);
268 assert(cache->partitions > 0);
269 assert(cache->associativity > 0);
270 /* We don't implement fully-associative caches */
271 assert(cache->associativity < cache->sets);
272 *ebx = (cache->line_size - 1) |
273 ((cache->partitions - 1) << 12) |
274 ((cache->associativity - 1) << 22);
275
276 assert(cache->sets > 0);
277 *ecx = cache->sets - 1;
278
279 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
280 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
281 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
282}
283
284/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
285static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
286{
287 assert(cache->size % 1024 == 0);
288 assert(cache->lines_per_tag > 0);
289 assert(cache->associativity > 0);
290 assert(cache->line_size > 0);
291 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
292 (cache->lines_per_tag << 8) | (cache->line_size);
293}
5e891bf8
EH		 294
295#define ASSOC_FULL 0xFF
296
297/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
298#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
299 a == 2 ? 0x2 : \
300 a == 4 ? 0x4 : \
301 a == 8 ? 0x6 : \
302 a == 16 ? 0x8 : \
303 a == 32 ? 0xA : \
304 a == 48 ? 0xB : \
305 a == 64 ? 0xC : \
306 a == 96 ? 0xD : \
307 a == 128 ? 0xE : \
308 a == ASSOC_FULL ? 0xF : \
309 0 /* invalid value */)
310
7e3482f8
EH		 311/*
312 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
313 * @l3 can be NULL.
314 */
315static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
316 CPUCacheInfo *l3,
317 uint32_t *ecx, uint32_t *edx)
318{
319 assert(l2->size % 1024 == 0);
320 assert(l2->associativity > 0);
321 assert(l2->lines_per_tag > 0);
322 assert(l2->line_size > 0);
323 *ecx = ((l2->size / 1024) << 16) |
324 (AMD_ENC_ASSOC(l2->associativity) << 12) |
325 (l2->lines_per_tag << 8) | (l2->line_size);
326
327 if (l3) {
328 assert(l3->size % (512 * 1024) == 0);
329 assert(l3->associativity > 0);
330 assert(l3->lines_per_tag > 0);
331 assert(l3->line_size > 0);
332 *edx = ((l3->size / (512 * 1024)) << 18) |
333 (AMD_ENC_ASSOC(l3->associativity) << 12) |
334 (l3->lines_per_tag << 8) | (l3->line_size);
335 } else {
336 *edx = 0;
337 }
338}
5e891bf8 339
8f4202fb
BM		 340/*
341 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
342 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
343 * Define the constants to build the cpu topology. Right now, TOPOEXT
344 * feature is enabled only on EPYC. So, these constants are based on
345 * EPYC supported configurations. We may need to handle the cases if
346 * these values change in future.
347 */
348/* Maximum core complexes in a node */
349#define MAX_CCX 2
350/* Maximum cores in a core complex */
351#define MAX_CORES_IN_CCX 4
352/* Maximum cores in a node */
353#define MAX_CORES_IN_NODE 8
354/* Maximum nodes in a socket */
355#define MAX_NODES_PER_SOCKET 4
356
357/*
358 * Figure out the number of nodes required to build this config.
359 * Max cores in a node is 8
360 */
361static int nodes_in_socket(int nr_cores)
362{
363 int nodes;
364
365 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
366
367 /* Hardware does not support config with 3 nodes, return 4 in that case */
368 return (nodes == 3) ? 4 : nodes;
369}
370
371/*
372 * Decide the number of cores in a core complex with the given nr_cores using
373 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
374 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
375 * L3 cache is shared across all cores in a core complex. So, this will also
376 * tell us how many cores are sharing the L3 cache.
377 */
378static int cores_in_core_complex(int nr_cores)
379{
380 int nodes;
381
382 /* Check if we can fit all the cores in one core complex */
383 if (nr_cores <= MAX_CORES_IN_CCX) {
384 return nr_cores;
385 }
386 /* Get the number of nodes required to build this config */
387 nodes = nodes_in_socket(nr_cores);
388
389 /*
390 * Divide the cores accros all the core complexes
391 * Return rounded up value
392 */
393 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
394}
395
396/* Encode cache info for CPUID[8000001D] */
397static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
398 uint32_t *eax, uint32_t *ebx,
399 uint32_t *ecx, uint32_t *edx)
400{
401 uint32_t l3_cores;
402 assert(cache->size == cache->line_size * cache->associativity *
403 cache->partitions * cache->sets);
404
405 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
406 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
407
408 /* L3 is shared among multiple cores */
409 if (cache->level == 3) {
410 l3_cores = cores_in_core_complex(cs->nr_cores);
411 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
412 } else {
413 *eax |= ((cs->nr_threads - 1) << 14);
414 }
415
416 assert(cache->line_size > 0);
417 assert(cache->partitions > 0);
418 assert(cache->associativity > 0);
419 /* We don't implement fully-associative caches */
420 assert(cache->associativity < cache->sets);
421 *ebx = (cache->line_size - 1) |
422 ((cache->partitions - 1) << 12) |
423 ((cache->associativity - 1) << 22);
424
425 assert(cache->sets > 0);
426 *ecx = cache->sets - 1;
427
428 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
429 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
430 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
431}
432
ed78467a
BM		 433/* Data structure to hold the configuration info for a given core index */
434struct core_topology {
435 /* core complex id of the current core index */
436 int ccx_id;
437 /*
438 * Adjusted core index for this core in the topology
439 * This can be 0,1,2,3 with max 4 cores in a core complex
440 */
441 int core_id;
442 /* Node id for this core index */
443 int node_id;
444 /* Number of nodes in this config */
445 int num_nodes;
446};
447
448/*
449 * Build the configuration closely match the EPYC hardware. Using the EPYC
450 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
451 * right now. This could change in future.
452 * nr_cores : Total number of cores in the config
453 * core_id : Core index of the current CPU
454 * topo : Data structure to hold all the config info for this core index
455 */
456static void build_core_topology(int nr_cores, int core_id,
457 struct core_topology *topo)
458{
459 int nodes, cores_in_ccx;
460
461 /* First get the number of nodes required */
462 nodes = nodes_in_socket(nr_cores);
463
464 cores_in_ccx = cores_in_core_complex(nr_cores);
465
466 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
467 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
468 topo->core_id = core_id % cores_in_ccx;
469 topo->num_nodes = nodes;
470}
471
472/* Encode cache info for CPUID[8000001E] */
473static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
474 uint32_t *eax, uint32_t *ebx,
475 uint32_t *ecx, uint32_t *edx)
476{
477 struct core_topology topo = {0};
631be321
BM		 478 unsigned long nodes;
479 int shift;
ed78467a
BM		 480
481 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
482 *eax = cpu->apic_id;
483 /*
484 * CPUID_Fn8000001E_EBX
485 * 31:16 Reserved
486 * 15:8 Threads per core (The number of threads per core is
487 * Threads per core + 1)
488 * 7:0 Core id (see bit decoding below)
489 * SMT:
490 * 4:3 node id
491 * 2 Core complex id
492 * 1:0 Core id
493 * Non SMT:
494 * 5:4 node id
495 * 3 Core complex id
496 * 1:0 Core id
497 */
498 if (cs->nr_threads - 1) {
499 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
500 (topo.ccx_id << 2) | topo.core_id;
501 } else {
502 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
503 }
504 /*
505 * CPUID_Fn8000001E_ECX
506 * 31:11 Reserved
507 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
508 * 7:0 Node id (see bit decoding below)
509 * 2 Socket id
510 * 1:0 Node id
511 */
631be321
BM		 512 if (topo.num_nodes <= 4) {
513 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
514 topo.node_id;
515 } else {
516 /*
517 * Node id fix up. Actual hardware supports up to 4 nodes. But with
518 * more than 32 cores, we may end up with more than 4 nodes.
519 * Node id is a combination of socket id and node id. Only requirement
520 * here is that this number should be unique accross the system.
521 * Shift the socket id to accommodate more nodes. We dont expect both
522 * socket id and node id to be big number at the same time. This is not
523 * an ideal config but we need to to support it. Max nodes we can have
524 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
525 * 5 bits for nodes. Find the left most set bit to represent the total
526 * number of nodes. find_last_bit returns last set bit(0 based). Left
527 * shift(+1) the socket id to represent all the nodes.
528 */
529 nodes = topo.num_nodes - 1;
530 shift = find_last_bit(&nodes, 8);
531 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
532 topo.node_id;
533 }
ed78467a
BM		 534 *edx = 0;
535}
536
ab8f992e
BM		 537/*
538 * Definitions of the hardcoded cache entries we expose:
539 * These are legacy cache values. If there is a need to change any
540 * of these values please use builtin_x86_defs
541 */
5e891bf8
EH		 542
543/* L1 data cache: */
ab8f992e 544static CPUCacheInfo legacy_l1d_cache = {
5f00335a 545 .type = DATA_CACHE,
7e3482f8
EH		 546 .level = 1,
547 .size = 32 * KiB,
548 .self_init = 1,
549 .line_size = 64,
550 .associativity = 8,
551 .sets = 64,
552 .partitions = 1,
553 .no_invd_sharing = true,
554};
555
5e891bf8 556/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 557static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 558 .type = DATA_CACHE,
7e3482f8
EH		 559 .level = 1,
560 .size = 64 * KiB,
561 .self_init = 1,
562 .line_size = 64,
563 .associativity = 2,
564 .sets = 512,
565 .partitions = 1,
566 .lines_per_tag = 1,
567 .no_invd_sharing = true,
568};
5e891bf8
EH		 569
570/* L1 instruction cache: */
ab8f992e 571static CPUCacheInfo legacy_l1i_cache = {
5f00335a 572 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 573 .level = 1,
574 .size = 32 * KiB,
575 .self_init = 1,
576 .line_size = 64,
577 .associativity = 8,
578 .sets = 64,
579 .partitions = 1,
580 .no_invd_sharing = true,
581};
582
5e891bf8 583/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 584static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 585 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 586 .level = 1,
587 .size = 64 * KiB,
588 .self_init = 1,
589 .line_size = 64,
590 .associativity = 2,
591 .sets = 512,
592 .partitions = 1,
593 .lines_per_tag = 1,
594 .no_invd_sharing = true,
595};
5e891bf8
EH		 596
597/* Level 2 unified cache: */
ab8f992e 598static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 599 .type = UNIFIED_CACHE,
600 .level = 2,
601 .size = 4 * MiB,
602 .self_init = 1,
603 .line_size = 64,
604 .associativity = 16,
605 .sets = 4096,
606 .partitions = 1,
607 .no_invd_sharing = true,
608};
609
5e891bf8 610/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 611static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 612 .type = UNIFIED_CACHE,
613 .level = 2,
614 .size = 2 * MiB,
615 .line_size = 64,
616 .associativity = 8,
617};
618
619
5e891bf8 620/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 621static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 622 .type = UNIFIED_CACHE,
623 .level = 2,
624 .size = 512 * KiB,
625 .line_size = 64,
626 .lines_per_tag = 1,
627 .associativity = 16,
628 .sets = 512,
629 .partitions = 1,
630};
5e891bf8 631
14c985cf 632/* Level 3 unified cache: */
ab8f992e 633static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 634 .type = UNIFIED_CACHE,
635 .level = 3,
636 .size = 16 * MiB,
637 .line_size = 64,
638 .associativity = 16,
639 .sets = 16384,
640 .partitions = 1,
641 .lines_per_tag = 1,
642 .self_init = true,
643 .inclusive = true,
644 .complex_indexing = true,
645};
5e891bf8
EH		 646
647/* TLB definitions: */
648
649#define L1_DTLB_2M_ASSOC 1
650#define L1_DTLB_2M_ENTRIES 255
651#define L1_DTLB_4K_ASSOC 1
652#define L1_DTLB_4K_ENTRIES 255
653
654#define L1_ITLB_2M_ASSOC 1
655#define L1_ITLB_2M_ENTRIES 255
656#define L1_ITLB_4K_ASSOC 1
657#define L1_ITLB_4K_ENTRIES 255
658
659#define L2_DTLB_2M_ASSOC 0 /* disabled */
660#define L2_DTLB_2M_ENTRIES 0 /* disabled */
661#define L2_DTLB_4K_ASSOC 4
662#define L2_DTLB_4K_ENTRIES 512
663
664#define L2_ITLB_2M_ASSOC 0 /* disabled */
665#define L2_ITLB_2M_ENTRIES 0 /* disabled */
666#define L2_ITLB_4K_ASSOC 4
667#define L2_ITLB_4K_ENTRIES 512
668
e37a5c7f
CP		 669/* CPUID Leaf 0x14 constants: */
670#define INTEL_PT_MAX_SUBLEAF 0x1
671/*
672 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
673 * MSR can be accessed;
674 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
675 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
676 * of Intel PT MSRs across warm reset;
677 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
678 */
679#define INTEL_PT_MINIMAL_EBX 0xf
680/*
681 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
682 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
683 * accessed;
684 * bit[01]: ToPA tables can hold any number of output entries, up to the
685 * maximum allowed by the MaskOrTableOffset field of
686 * IA32_RTIT_OUTPUT_MASK_PTRS;
687 * bit[02]: Support Single-Range Output scheme;
688 */
689#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 690/* generated packets which contain IP payloads have LIP values */
691#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 692#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
693#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
694#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
695#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
696#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 697
99b88a17
IM		 698static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
699 uint32_t vendor2, uint32_t vendor3)
700{
701 int i;
702 for (i = 0; i < 4; i++) {
703 dst[i] = vendor1 >> (8 * i);
704 dst[i + 4] = vendor2 >> (8 * i);
705 dst[i + 8] = vendor3 >> (8 * i);
706 }
707 dst[CPUID_VENDOR_SZ] = '\0';
708}
709
621626ce
EH		 710#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
711#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
712 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
713#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
714 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
715 CPUID_PSE36 | CPUID_FXSR)
716#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
717#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
718 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
719 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
720 CPUID_PAE | CPUID_SEP | CPUID_APIC)
721
722#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
723 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
724 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
725 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 726 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 727 /* partly implemented:
728 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
729 /* missing:
730 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
731#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
732 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
733 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 734 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 735 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
736 CPUID_EXT_RDRAND)
621626ce
EH		 737 /* missing:
738 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
739 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
740 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 741 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 742 CPUID_EXT_F16C */
621626ce
EH		 743
744#ifdef TARGET_X86_64
745#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
746#else
747#define TCG_EXT2_X86_64_FEATURES 0
748#endif
749
750#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
751 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
752 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
753 TCG_EXT2_X86_64_FEATURES)
754#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
755 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
756#define TCG_EXT4_FEATURES 0
fe441054 757#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 758#define TCG_KVM_FEATURES 0
759#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 760 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
761 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 762 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
763 CPUID_7_0_EBX_ERMS)
621626ce 764 /* missing:
07929f2a 765 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 766 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 767 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 768#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
769 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 770 CPUID_7_0_ECX_LA57)
95ea69fb 771#define TCG_7_0_EDX_FEATURES 0
303752a9 772#define TCG_APM_FEATURES 0
28b8e4d0 773#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 774#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
775 /* missing:
776 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 777
07585923
RH		 778typedef enum FeatureWordType {
779 CPUID_FEATURE_WORD,
780 MSR_FEATURE_WORD,
781} FeatureWordType;
782
5ef57876 783typedef struct FeatureWordInfo {
07585923 784 FeatureWordType type;
2d5312da
EH		 785 /* feature flags names are taken from "Intel Processor Identification and
786 * the CPUID Instruction" and AMD's "CPUID Specification".
787 * In cases of disagreement between feature naming conventions,
788 * aliases may be added.
789 */
790 const char *feat_names[32];
07585923
RH		 791 union {
792 /* If type==CPUID_FEATURE_WORD */
793 struct {
794 uint32_t eax; /* Input EAX for CPUID */
795 bool needs_ecx; /* CPUID instruction uses ECX as input */
796 uint32_t ecx; /* Input ECX value for CPUID */
797 int reg; /* output register (R_* constant) */
798 } cpuid;
799 /* If type==MSR_FEATURE_WORD */
800 struct {
801 uint32_t index;
802 struct { /*CPUID that enumerate this MSR*/
803 FeatureWord cpuid_class;
804 uint32_t cpuid_flag;
805 } cpuid_dep;
806 } msr;
807 };
37ce3522 808 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 809 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 810 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 811 /* Features that shouldn't be auto-enabled by "-cpu host" */
812 uint32_t no_autoenable_flags;
5ef57876
EH		 813} FeatureWordInfo;
814
815static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 816 [FEAT_1_EDX] = {
07585923 817 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 818 .feat_names = {
819 "fpu", "vme", "de", "pse",
820 "tsc", "msr", "pae", "mce",
821 "cx8", "apic", NULL, "sep",
822 "mtrr", "pge", "mca", "cmov",
823 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
824 NULL, "ds" /* Intel dts */, "acpi", "mmx",
825 "fxsr", "sse", "sse2", "ss",
826 "ht" /* Intel htt */, "tm", "ia64", "pbe",
827 },
07585923 828 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 829 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 830 },
831 [FEAT_1_ECX] = {
07585923 832 .type = CPUID_FEATURE_WORD,
2d5312da 833 .feat_names = {
16d2fcaa 834 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 835 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 836 "tm2", "ssse3", "cid", NULL,
837 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 838 NULL, "pcid", "dca", "sse4.1",
839 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 840 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 841 "avx", "f16c", "rdrand", "hypervisor",
842 },
07585923 843 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 844 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 845 },
2d5312da
EH		 846 /* Feature names that are already defined on feature_name[] but
847 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
848 * names on feat_names below. They are copied automatically
849 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
850 */
bffd67b0 851 [FEAT_8000_0001_EDX] = {
07585923 852 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 853 .feat_names = {
854 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
855 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
856 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
857 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
858 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 859 "nx", NULL, "mmxext", NULL /* mmx */,
860 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
861 NULL, "lm", "3dnowext", "3dnow",
2d5312da 862 },
07585923 863 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 864 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 865 },
866 [FEAT_8000_0001_ECX] = {
07585923 867 .type = CPUID_FEATURE_WORD,
2d5312da 868 .feat_names = {
fc7dfd20 869 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 870 "cr8legacy", "abm", "sse4a", "misalignsse",
871 "3dnowprefetch", "osvw", "ibs", "xop",
872 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 873 "fma4", "tce", NULL, "nodeid-msr",
874 NULL, "tbm", "topoext", "perfctr-core",
875 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 876 NULL, NULL, NULL, NULL,
877 },
07585923 878 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 879 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 880 /*
881 * TOPOEXT is always allowed but can't be enabled blindly by
882 * "-cpu host", as it requires consistent cache topology info
883 * to be provided so it doesn't confuse guests.
884 */
885 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 886 },
89e49c8b 887 [FEAT_C000_0001_EDX] = {
07585923 888 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 889 .feat_names = {
890 NULL, NULL, "xstore", "xstore-en",
891 NULL, NULL, "xcrypt", "xcrypt-en",
892 "ace2", "ace2-en", "phe", "phe-en",
893 "pmm", "pmm-en", NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, NULL, NULL, NULL,
898 },
07585923 899 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 900 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 901 },
bffd67b0 902 [FEAT_KVM] = {
07585923 903 .type = CPUID_FEATURE_WORD,
2d5312da 904 .feat_names = {
fc7dfd20
EH		 905 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
906 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 907 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 "kvmclock-stable-bit", NULL, NULL, NULL,
912 NULL, NULL, NULL, NULL,
913 },
07585923 914 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 915 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 916 },
be777326 917 [FEAT_KVM_HINTS] = {
07585923 918 .type = CPUID_FEATURE_WORD,
be777326
WL		 919 .feat_names = {
920 "kvm-hint-dedicated", NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 },
07585923 929 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 930 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 931 /*
932 * KVM hints aren't auto-enabled by -cpu host, they need to be
933 * explicitly enabled in the command-line.
934 */
935 .no_autoenable_flags = ~0U,
be777326 936 },
abd5fc4c
VK		 937 /*
938 * .feat_names are commented out for Hyper-V enlightenments because we
939 * don't want to have two different ways for enabling them on QEMU command
940 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
941 * enabling several feature bits simultaneously, exposing these bits
942 * individually may just confuse guests.
943 */
c35bd19a 944 [FEAT_HYPERV_EAX] = {
07585923 945 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 946 .feat_names = {
947 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
948 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
949 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
950 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
951 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
952 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 953 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
954 NULL, NULL,
2d5312da
EH		 955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 NULL, NULL, NULL, NULL,
958 NULL, NULL, NULL, NULL,
959 },
07585923 960 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 961 },
962 [FEAT_HYPERV_EBX] = {
07585923 963 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 964 .feat_names = {
965 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
966 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
967 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
968 NULL /* hv_create_port */, NULL /* hv_connect_port */,
969 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
970 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
971 NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 },
07585923 977 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 978 },
979 [FEAT_HYPERV_EDX] = {
07585923 980 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 981 .feat_names = {
982 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
983 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
984 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
985 NULL, NULL,
986 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
07585923 993 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 994 },
a2b107db
VK		 995 [FEAT_HV_RECOMM_EAX] = {
996 .type = CPUID_FEATURE_WORD,
997 .feat_names = {
998 NULL /* hv_recommend_pv_as_switch */,
999 NULL /* hv_recommend_pv_tlbflush_local */,
1000 NULL /* hv_recommend_pv_tlbflush_remote */,
1001 NULL /* hv_recommend_msr_apic_access */,
1002 NULL /* hv_recommend_msr_reset */,
1003 NULL /* hv_recommend_relaxed_timing */,
1004 NULL /* hv_recommend_dma_remapping */,
1005 NULL /* hv_recommend_int_remapping */,
1006 NULL /* hv_recommend_x2apic_msrs */,
1007 NULL /* hv_recommend_autoeoi_deprecation */,
1008 NULL /* hv_recommend_pv_ipi */,
1009 NULL /* hv_recommend_ex_hypercalls */,
1010 NULL /* hv_hypervisor_is_nested */,
1011 NULL /* hv_recommend_int_mbec */,
1012 NULL /* hv_recommend_evmcs */,
1013 NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 },
1019 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1020 },
1021 [FEAT_HV_NESTED_EAX] = {
1022 .type = CPUID_FEATURE_WORD,
1023 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1024 },
bffd67b0 1025 [FEAT_SVM] = {
07585923 1026 .type = CPUID_FEATURE_WORD,
2d5312da 1027 .feat_names = {
fc7dfd20
EH		 1028 "npt", "lbrv", "svm-lock", "nrip-save",
1029 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1030 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 1031 "pfthreshold", NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 NULL, NULL, NULL, NULL,
1036 },
07585923 1037 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 1038 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 1039 },
1040 [FEAT_7_0_EBX] = {
07585923 1041 .type = CPUID_FEATURE_WORD,
2d5312da 1042 .feat_names = {
fc7dfd20 1043 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1044 "hle", "avx2", NULL, "smep",
1045 "bmi2", "erms", "invpcid", "rtm",
1046 NULL, NULL, "mpx", NULL,
1047 "avx512f", "avx512dq", "rdseed", "adx",
1048 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1049 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1050 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1051 },
07585923
RH		 1052 .cpuid = {
1053 .eax = 7,
1054 .needs_ecx = true, .ecx = 0,
1055 .reg = R_EBX,
1056 },
37ce3522 1057 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1058 },
f74eefe0 1059 [FEAT_7_0_ECX] = {
07585923 1060 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1061 .feat_names = {
1062 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1063 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1064 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1065 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1066 "la57", NULL, NULL, NULL,
2d5312da 1067 NULL, NULL, "rdpid", NULL,
24261de4 1068 NULL, "cldemote", NULL, "movdiri",
1c65775f 1069 "movdir64b", NULL, NULL, NULL,
2d5312da 1070 },
07585923
RH		 1071 .cpuid = {
1072 .eax = 7,
1073 .needs_ecx = true, .ecx = 0,
1074 .reg = R_ECX,
1075 },
f74eefe0
HH		 1076 .tcg_features = TCG_7_0_ECX_FEATURES,
1077 },
95ea69fb 1078 [FEAT_7_0_EDX] = {
07585923 1079 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1080 .feat_names = {
1081 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1082 NULL, NULL, NULL, NULL,
b2ae5210 1083 NULL, NULL, "md-clear", NULL,
95ea69fb 1084 NULL, NULL, NULL, NULL,
712f807e 1085 NULL, NULL, NULL, NULL,
95ea69fb 1086 NULL, NULL, NULL, NULL,
0e891658 1087 NULL, NULL, "spec-ctrl", "stibp",
3fc7c731 1088 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1089 },
07585923
RH		 1090 .cpuid = {
1091 .eax = 7,
1092 .needs_ecx = true, .ecx = 0,
1093 .reg = R_EDX,
1094 },
95ea69fb
LK		 1095 .tcg_features = TCG_7_0_EDX_FEATURES,
1096 },
303752a9 1097 [FEAT_8000_0007_EDX] = {
07585923 1098 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1099 .feat_names = {
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 "invtsc", NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 },
07585923 1109 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1110 .tcg_features = TCG_APM_FEATURES,
1111 .unmigratable_flags = CPUID_APM_INVTSC,
1112 },
1b3420e1 1113 [FEAT_8000_0008_EBX] = {
07585923 1114 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1115 .feat_names = {
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
59a80a19 1118 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1119 "ibpb", NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
254790a9 1122 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1123 NULL, NULL, NULL, NULL,
1124 },
07585923 1125 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1126 .tcg_features = 0,
1127 .unmigratable_flags = 0,
1128 },
0bb0b2d2 1129 [FEAT_XSAVE] = {
07585923 1130 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1131 .feat_names = {
1132 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 },
07585923
RH		 1141 .cpuid = {
1142 .eax = 0xd,
1143 .needs_ecx = true, .ecx = 1,
1144 .reg = R_EAX,
1145 },
c9cfe8f9 1146 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1147 },
28b8e4d0 1148 [FEAT_6_EAX] = {
07585923 1149 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1150 .feat_names = {
1151 NULL, NULL, "arat", NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 NULL, NULL, NULL, NULL,
1158 NULL, NULL, NULL, NULL,
1159 },
07585923 1160 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1161 .tcg_features = TCG_6_EAX_FEATURES,
1162 },
96193c22 1163 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1164 .type = CPUID_FEATURE_WORD,
1165 .cpuid = {
1166 .eax = 0xD,
1167 .needs_ecx = true, .ecx = 0,
1168 .reg = R_EAX,
1169 },
96193c22 1170 .tcg_features = ~0U,
6fb2fff7
EH		 1171 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1172 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1173 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1174 XSTATE_PKRU_MASK,
96193c22
EH		 1175 },
1176 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1177 .type = CPUID_FEATURE_WORD,
1178 .cpuid = {
1179 .eax = 0xD,
1180 .needs_ecx = true, .ecx = 0,
1181 .reg = R_EDX,
1182 },
96193c22
EH		 1183 .tcg_features = ~0U,
1184 },
d86f9636
RH		 1185 /*Below are MSR exposed features*/
1186 [FEAT_ARCH_CAPABILITIES] = {
1187 .type = MSR_FEATURE_WORD,
1188 .feat_names = {
1189 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
20140a82 1190 "ssb-no", "mds-no", NULL, NULL,
d86f9636
RH		 1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 },
1198 .msr = {
1199 .index = MSR_IA32_ARCH_CAPABILITIES,
1200 .cpuid_dep = {
1201 FEAT_7_0_EDX,
1202 CPUID_7_0_EDX_ARCH_CAPABILITIES
1203 }
1204 },
1205 },
5ef57876
EH		 1206};
1207
8e8aba50
EH		 1208typedef struct X86RegisterInfo32 {
1209 /* Name of register */
1210 const char *name;
1211 /* QAPI enum value register */
1212 X86CPURegister32 qapi_enum;
1213} X86RegisterInfo32;
1214
1215#define REGISTER(reg) \
5d371f41 1216 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1217static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1218 REGISTER(EAX),
1219 REGISTER(ECX),
1220 REGISTER(EDX),
1221 REGISTER(EBX),
1222 REGISTER(ESP),
1223 REGISTER(EBP),
1224 REGISTER(ESI),
1225 REGISTER(EDI),
1226};
1227#undef REGISTER
1228
3f32bd21
RH		 1229typedef struct ExtSaveArea {
1230 uint32_t feature, bits;
1231 uint32_t offset, size;
1232} ExtSaveArea;
1233
1234static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1235 [XSTATE_FP_BIT] = {
1236 /* x87 FP state component is always enabled if XSAVE is supported */
1237 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1238 /* x87 state is in the legacy region of the XSAVE area */
1239 .offset = 0,
1240 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1241 },
1242 [XSTATE_SSE_BIT] = {
1243 /* SSE state component is always enabled if XSAVE is supported */
1244 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1245 /* SSE state is in the legacy region of the XSAVE area */
1246 .offset = 0,
1247 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1248 },
cfc3b074
PB		 1249 [XSTATE_YMM_BIT] =
1250 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1251 .offset = offsetof(X86XSaveArea, avx_state),
1252 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1253 [XSTATE_BNDREGS_BIT] =
1254 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1255 .offset = offsetof(X86XSaveArea, bndreg_state),
1256 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1257 [XSTATE_BNDCSR_BIT] =
1258 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1259 .offset = offsetof(X86XSaveArea, bndcsr_state),
1260 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1261 [XSTATE_OPMASK_BIT] =
1262 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1263 .offset = offsetof(X86XSaveArea, opmask_state),
1264 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1265 [XSTATE_ZMM_Hi256_BIT] =
1266 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1267 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1268 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1269 [XSTATE_Hi16_ZMM_BIT] =
1270 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1271 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1272 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1273 [XSTATE_PKRU_BIT] =
1274 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1275 .offset = offsetof(X86XSaveArea, pkru_state),
1276 .size = sizeof(XSavePKRU) },
2560f19f 1277};
8e8aba50 1278
1fda6198
EH		 1279static uint32_t xsave_area_size(uint64_t mask)
1280{
1281 int i;
e3c9022b 1282 uint64_t ret = 0;
1fda6198 1283
e3c9022b 1284 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1285 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1286 if ((mask >> i) & 1) {
1287 ret = MAX(ret, esa->offset + esa->size);
1288 }
1289 }
1290 return ret;
1291}
1292
d6dcc558
SAGDR		 1293static inline bool accel_uses_host_cpuid(void)
1294{
1295 return kvm_enabled() || hvf_enabled();
1296}
1297
96193c22
EH		 1298static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1299{
1300 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1301 cpu->env.features[FEAT_XSAVE_COMP_LO];
1302}
1303
8b4beddc
EH		 1304const char *get_register_name_32(unsigned int reg)
1305{
31ccdde2 1306 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1307 return NULL;
1308 }
8e8aba50 1309 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1310}
1311
84f1b92f
EH		 1312/*
1313 * Returns the set of feature flags that are supported and migratable by
1314 * QEMU, for a given FeatureWord.
1315 */
1316static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1317{
1318 FeatureWordInfo *wi = &feature_word_info[w];
1319 uint32_t r = 0;
1320 int i;
1321
1322 for (i = 0; i < 32; i++) {
1323 uint32_t f = 1U << i;
6fb2fff7
EH		 1324
1325 /* If the feature name is known, it is implicitly considered migratable,
1326 * unless it is explicitly set in unmigratable_flags */
1327 if ((wi->migratable_flags & f) ||
1328 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1329 r |= f;
84f1b92f 1330 }
84f1b92f
EH		 1331 }
1332 return r;
1333}
1334
bb44e0d1
JK		 1335void host_cpuid(uint32_t function, uint32_t count,
1336 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1337{
a1fd24af
AL		 1338 uint32_t vec[4];
1339
1340#ifdef __x86_64__
1341 asm volatile("cpuid"
1342 : "=a"(vec[0]), "=b"(vec[1]),
1343 "=c"(vec[2]), "=d"(vec[3])
1344 : "0"(function), "c"(count) : "cc");
c1f41226 1345#elif defined(__i386__)
a1fd24af
AL		 1346 asm volatile("pusha \n\t"
1347 "cpuid \n\t"
1348 "mov %%eax, 0(%2) \n\t"
1349 "mov %%ebx, 4(%2) \n\t"
1350 "mov %%ecx, 8(%2) \n\t"
1351 "mov %%edx, 12(%2) \n\t"
1352 "popa"
1353 : : "a"(function), "c"(count), "S"(vec)
1354 : "memory", "cc");
c1f41226
EH		 1355#else
1356 abort();
a1fd24af
AL		 1357#endif
1358
bdde476a 1359 if (eax)
a1fd24af 1360 *eax = vec[0];
bdde476a 1361 if (ebx)
a1fd24af 1362 *ebx = vec[1];
bdde476a 1363 if (ecx)
a1fd24af 1364 *ecx = vec[2];
bdde476a 1365 if (edx)
a1fd24af 1366 *edx = vec[3];
bdde476a 1367}
c6dc6f63 1368
20271d48
EH		 1369void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1370{
1371 uint32_t eax, ebx, ecx, edx;
1372
1373 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1374 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1375
1376 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1377 if (family) {
1378 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1379 }
1380 if (model) {
1381 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1382 }
1383 if (stepping) {
1384 *stepping = eax & 0x0F;
1385 }
1386}
1387
d940ee9b
EH		 1388/* CPU class name definitions: */
1389
d940ee9b
EH		 1390/* Return type name for a given CPU model name
1391 * Caller is responsible for freeing the returned string.
1392 */
1393static char *x86_cpu_type_name(const char *model_name)
1394{
1395 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1396}
1397
500050d1
AF		 1398static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1399{
d940ee9b 1400 ObjectClass *oc;
99193d8f 1401 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1402 oc = object_class_by_name(typename);
1403 g_free(typename);
1404 return oc;
500050d1
AF		 1405}
1406
104494ea
IM		 1407static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1408{
1409 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1410 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1411 return g_strndup(class_name,
1412 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1413}
1414
d940ee9b 1415struct X86CPUDefinition {
c6dc6f63
AP		 1416 const char *name;
1417 uint32_t level;
90e4b0c3 1418 uint32_t xlevel;
99b88a17
IM		 1419 /* vendor is zero-terminated, 12 character ASCII string */
1420 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1421 int family;
1422 int model;
1423 int stepping;
0514ef2f 1424 FeatureWordArray features;
807e9869 1425 const char *model_id;
6aaeb054 1426 CPUCaches *cache_info;
d940ee9b 1427};
c6dc6f63 1428
fe52acd2 1429static CPUCaches epyc_cache_info = {
a9f27ea9 1430 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1431 .type = DATA_CACHE,
fe52acd2
BM		 1432 .level = 1,
1433 .size = 32 * KiB,
1434 .line_size = 64,
1435 .associativity = 8,
1436 .partitions = 1,
1437 .sets = 64,
1438 .lines_per_tag = 1,
1439 .self_init = 1,
1440 .no_invd_sharing = true,
1441 },
a9f27ea9 1442 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1443 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1444 .level = 1,
1445 .size = 64 * KiB,
1446 .line_size = 64,
1447 .associativity = 4,
1448 .partitions = 1,
1449 .sets = 256,
1450 .lines_per_tag = 1,
1451 .self_init = 1,
1452 .no_invd_sharing = true,
1453 },
a9f27ea9 1454 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1455 .type = UNIFIED_CACHE,
1456 .level = 2,
1457 .size = 512 * KiB,
1458 .line_size = 64,
1459 .associativity = 8,
1460 .partitions = 1,
1461 .sets = 1024,
1462 .lines_per_tag = 1,
1463 },
a9f27ea9 1464 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1465 .type = UNIFIED_CACHE,
1466 .level = 3,
1467 .size = 8 * MiB,
1468 .line_size = 64,
1469 .associativity = 16,
1470 .partitions = 1,
1471 .sets = 8192,
1472 .lines_per_tag = 1,
1473 .self_init = true,
1474 .inclusive = true,
1475 .complex_indexing = true,
1476 },
1477};
1478
9576de75 1479static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1480 {
1481 .name = "qemu64",
3046bb5d 1482 .level = 0xd,
99b88a17 1483 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1484 .family = 6,
f8e6a11a 1485 .model = 6,
c6dc6f63 1486 .stepping = 3,
0514ef2f 1487 .features[FEAT_1_EDX] =
27861ecc 1488 PPRO_FEATURES |
c6dc6f63 1489 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1490 CPUID_PSE36,
0514ef2f 1491 .features[FEAT_1_ECX] =
6aa91e4a 1492 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1493 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1494 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1495 .features[FEAT_8000_0001_ECX] =
71195672 1496 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1497 .xlevel = 0x8000000A,
9cf2cc3d 1498 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1499 },
1500 {
1501 .name = "phenom",
1502 .level = 5,
99b88a17 1503 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1504 .family = 16,
1505 .model = 2,
1506 .stepping = 3,
b9fc20bc 1507 /* Missing: CPUID_HT */
0514ef2f 1508 .features[FEAT_1_EDX] =
27861ecc 1509 PPRO_FEATURES |
c6dc6f63 1510 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1511 CPUID_PSE36 | CPUID_VME,
0514ef2f 1512 .features[FEAT_1_ECX] =
27861ecc 1513 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1514 CPUID_EXT_POPCNT,
0514ef2f 1515 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1516 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1517 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1518 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1519 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1520 CPUID_EXT3_CR8LEG,
1521 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1522 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1523 .features[FEAT_8000_0001_ECX] =
27861ecc 1524 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1525 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1526 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1527 .features[FEAT_SVM] =
b9fc20bc 1528 CPUID_SVM_NPT,
c6dc6f63
AP		 1529 .xlevel = 0x8000001A,
1530 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1531 },
1532 {
1533 .name = "core2duo",
1534 .level = 10,
99b88a17 1535 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1536 .family = 6,
1537 .model = 15,
1538 .stepping = 11,
b9fc20bc 1539 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1540 .features[FEAT_1_EDX] =
27861ecc 1541 PPRO_FEATURES |
c6dc6f63 1542 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1543 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1544 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1545 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1546 .features[FEAT_1_ECX] =
27861ecc 1547 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1548 CPUID_EXT_CX16,
0514ef2f 1549 .features[FEAT_8000_0001_EDX] =
27861ecc 1550 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1551 .features[FEAT_8000_0001_ECX] =
27861ecc 1552 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1553 .xlevel = 0x80000008,
1554 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1555 },
1556 {
1557 .name = "kvm64",
3046bb5d 1558 .level = 0xd,
99b88a17 1559 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1560 .family = 15,
1561 .model = 6,
1562 .stepping = 1,
b3a4f0b1 1563 /* Missing: CPUID_HT */
0514ef2f 1564 .features[FEAT_1_EDX] =
b3a4f0b1 1565 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1566 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1567 CPUID_PSE36,
1568 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1569 .features[FEAT_1_ECX] =
27861ecc 1570 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1571 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1572 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1573 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1574 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1575 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1576 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1577 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1578 .features[FEAT_8000_0001_ECX] =
27861ecc 1579 0,
c6dc6f63
AP		 1580 .xlevel = 0x80000008,
1581 .model_id = "Common KVM processor"
1582 },
c6dc6f63
AP		 1583 {
1584 .name = "qemu32",
1585 .level = 4,
99b88a17 1586 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1587 .family = 6,
f8e6a11a 1588 .model = 6,
c6dc6f63 1589 .stepping = 3,
0514ef2f 1590 .features[FEAT_1_EDX] =
27861ecc 1591 PPRO_FEATURES,
0514ef2f 1592 .features[FEAT_1_ECX] =
6aa91e4a 1593 CPUID_EXT_SSE3,
58012d66 1594 .xlevel = 0x80000004,
9cf2cc3d 1595 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1596 },
eafaf1e5
AP		 1597 {
1598 .name = "kvm32",
1599 .level = 5,
99b88a17 1600 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1601 .family = 15,
1602 .model = 6,
1603 .stepping = 1,
0514ef2f 1604 .features[FEAT_1_EDX] =
b3a4f0b1 1605 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1606 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1607 .features[FEAT_1_ECX] =
27861ecc 1608 CPUID_EXT_SSE3,
0514ef2f 1609 .features[FEAT_8000_0001_ECX] =
27861ecc 1610 0,
eafaf1e5
AP		 1611 .xlevel = 0x80000008,
1612 .model_id = "Common 32-bit KVM processor"
1613 },
c6dc6f63
AP		 1614 {
1615 .name = "coreduo",
1616 .level = 10,
99b88a17 1617 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1618 .family = 6,
1619 .model = 14,
1620 .stepping = 8,
b9fc20bc 1621 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1622 .features[FEAT_1_EDX] =
27861ecc 1623 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1624 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1625 CPUID_SS,
1626 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1627 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1628 .features[FEAT_1_ECX] =
e93abc14 1629 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1630 .features[FEAT_8000_0001_EDX] =
27861ecc 1631 CPUID_EXT2_NX,
c6dc6f63
AP		 1632 .xlevel = 0x80000008,
1633 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1634 },
1635 {
1636 .name = "486",
58012d66 1637 .level = 1,
99b88a17 1638 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1639 .family = 4,
b2a856d9 1640 .model = 8,
c6dc6f63 1641 .stepping = 0,
0514ef2f 1642 .features[FEAT_1_EDX] =
27861ecc 1643 I486_FEATURES,
c6dc6f63 1644 .xlevel = 0,
807e9869 1645 .model_id = "",
c6dc6f63
AP		 1646 },
1647 {
1648 .name = "pentium",
1649 .level = 1,
99b88a17 1650 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1651 .family = 5,
1652 .model = 4,
1653 .stepping = 3,
0514ef2f 1654 .features[FEAT_1_EDX] =
27861ecc 1655 PENTIUM_FEATURES,
c6dc6f63 1656 .xlevel = 0,
807e9869 1657 .model_id = "",
c6dc6f63
AP		 1658 },
1659 {
1660 .name = "pentium2",
1661 .level = 2,
99b88a17 1662 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1663 .family = 6,
1664 .model = 5,
1665 .stepping = 2,
0514ef2f 1666 .features[FEAT_1_EDX] =
27861ecc 1667 PENTIUM2_FEATURES,
c6dc6f63 1668 .xlevel = 0,
807e9869 1669 .model_id = "",
c6dc6f63
AP		 1670 },
1671 {
1672 .name = "pentium3",
3046bb5d 1673 .level = 3,
99b88a17 1674 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1675 .family = 6,
1676 .model = 7,
1677 .stepping = 3,
0514ef2f 1678 .features[FEAT_1_EDX] =
27861ecc 1679 PENTIUM3_FEATURES,
c6dc6f63 1680 .xlevel = 0,
807e9869 1681 .model_id = "",
c6dc6f63
AP		 1682 },
1683 {
1684 .name = "athlon",
1685 .level = 2,
99b88a17 1686 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1687 .family = 6,
1688 .model = 2,
1689 .stepping = 3,
0514ef2f 1690 .features[FEAT_1_EDX] =
27861ecc 1691 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1692 CPUID_MCA,
0514ef2f 1693 .features[FEAT_8000_0001_EDX] =
60032ac0 1694 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1695 .xlevel = 0x80000008,
9cf2cc3d 1696 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1697 },
1698 {
1699 .name = "n270",
3046bb5d 1700 .level = 10,
99b88a17 1701 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1702 .family = 6,
1703 .model = 28,
1704 .stepping = 2,
b9fc20bc 1705 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1706 .features[FEAT_1_EDX] =
27861ecc 1707 PPRO_FEATURES |
b9fc20bc
EH		 1708 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1709 CPUID_ACPI | CPUID_SS,
c6dc6f63 1710 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1711 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1712 * CPUID_EXT_XTPR */
0514ef2f 1713 .features[FEAT_1_ECX] =
27861ecc 1714 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1715 CPUID_EXT_MOVBE,
0514ef2f 1716 .features[FEAT_8000_0001_EDX] =
60032ac0 1717 CPUID_EXT2_NX,
0514ef2f 1718 .features[FEAT_8000_0001_ECX] =
27861ecc 1719 CPUID_EXT3_LAHF_LM,
3046bb5d 1720 .xlevel = 0x80000008,
c6dc6f63
AP		 1721 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1722 },
3eca4642
EH		 1723 {
1724 .name = "Conroe",
3046bb5d 1725 .level = 10,
99b88a17 1726 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1727 .family = 6,
ffce9ebb 1728 .model = 15,
3eca4642 1729 .stepping = 3,
0514ef2f 1730 .features[FEAT_1_EDX] =
b3a4f0b1 1731 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1732 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1733 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1734 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1735 CPUID_DE | CPUID_FP87,
0514ef2f 1736 .features[FEAT_1_ECX] =
27861ecc 1737 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1738 .features[FEAT_8000_0001_EDX] =
27861ecc 1739 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1740 .features[FEAT_8000_0001_ECX] =
27861ecc 1741 CPUID_EXT3_LAHF_LM,
3046bb5d 1742 .xlevel = 0x80000008,
3eca4642
EH		 1743 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1744 },
1745 {
1746 .name = "Penryn",
3046bb5d 1747 .level = 10,
99b88a17 1748 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1749 .family = 6,
ffce9ebb 1750 .model = 23,
3eca4642 1751 .stepping = 3,
0514ef2f 1752 .features[FEAT_1_EDX] =
b3a4f0b1 1753 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1754 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1755 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1756 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1757 CPUID_DE | CPUID_FP87,
0514ef2f 1758 .features[FEAT_1_ECX] =
27861ecc 1759 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1760 CPUID_EXT_SSE3,
0514ef2f 1761 .features[FEAT_8000_0001_EDX] =
27861ecc 1762 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1763 .features[FEAT_8000_0001_ECX] =
27861ecc 1764 CPUID_EXT3_LAHF_LM,
3046bb5d 1765 .xlevel = 0x80000008,
3eca4642
EH		 1766 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1767 },
1768 {
1769 .name = "Nehalem",
3046bb5d 1770 .level = 11,
99b88a17 1771 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1772 .family = 6,
ffce9ebb 1773 .model = 26,
3eca4642 1774 .stepping = 3,
0514ef2f 1775 .features[FEAT_1_EDX] =
b3a4f0b1 1776 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1777 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1778 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1779 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1780 CPUID_DE | CPUID_FP87,
0514ef2f 1781 .features[FEAT_1_ECX] =
27861ecc 1782 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1783 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1784 .features[FEAT_8000_0001_EDX] =
27861ecc 1785 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1786 .features[FEAT_8000_0001_ECX] =
27861ecc 1787 CPUID_EXT3_LAHF_LM,
3046bb5d 1788 .xlevel = 0x80000008,
3eca4642
EH		 1789 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1790 },
ac96c413
EH		 1791 {
1792 .name = "Nehalem-IBRS",
1793 .level = 11,
1794 .vendor = CPUID_VENDOR_INTEL,
1795 .family = 6,
1796 .model = 26,
1797 .stepping = 3,
1798 .features[FEAT_1_EDX] =
1799 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1800 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1801 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1802 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1803 CPUID_DE | CPUID_FP87,
1804 .features[FEAT_1_ECX] =
1805 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1806 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1807 .features[FEAT_7_0_EDX] =
1808 CPUID_7_0_EDX_SPEC_CTRL,
1809 .features[FEAT_8000_0001_EDX] =
1810 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1811 .features[FEAT_8000_0001_ECX] =
1812 CPUID_EXT3_LAHF_LM,
1813 .xlevel = 0x80000008,
1814 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1815 },
3eca4642
EH		 1816 {
1817 .name = "Westmere",
1818 .level = 11,
99b88a17 1819 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1820 .family = 6,
1821 .model = 44,
1822 .stepping = 1,
0514ef2f 1823 .features[FEAT_1_EDX] =
b3a4f0b1 1824 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1825 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1826 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1827 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1828 CPUID_DE | CPUID_FP87,
0514ef2f 1829 .features[FEAT_1_ECX] =
27861ecc 1830 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1831 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1832 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1833 .features[FEAT_8000_0001_EDX] =
27861ecc 1834 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1835 .features[FEAT_8000_0001_ECX] =
27861ecc 1836 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1837 .features[FEAT_6_EAX] =
1838 CPUID_6_EAX_ARAT,
3046bb5d 1839 .xlevel = 0x80000008,
3eca4642
EH		 1840 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1841 },
ac96c413
EH		 1842 {
1843 .name = "Westmere-IBRS",
1844 .level = 11,
1845 .vendor = CPUID_VENDOR_INTEL,
1846 .family = 6,
1847 .model = 44,
1848 .stepping = 1,
1849 .features[FEAT_1_EDX] =
1850 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1851 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1852 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1853 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1854 CPUID_DE | CPUID_FP87,
1855 .features[FEAT_1_ECX] =
1856 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1857 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1858 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1859 .features[FEAT_8000_0001_EDX] =
1860 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1861 .features[FEAT_8000_0001_ECX] =
1862 CPUID_EXT3_LAHF_LM,
1863 .features[FEAT_7_0_EDX] =
1864 CPUID_7_0_EDX_SPEC_CTRL,
1865 .features[FEAT_6_EAX] =
1866 CPUID_6_EAX_ARAT,
1867 .xlevel = 0x80000008,
1868 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1869 },
3eca4642
EH		 1870 {
1871 .name = "SandyBridge",
1872 .level = 0xd,
99b88a17 1873 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1874 .family = 6,
1875 .model = 42,
1876 .stepping = 1,
0514ef2f 1877 .features[FEAT_1_EDX] =
b3a4f0b1 1878 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1879 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1880 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1881 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1882 CPUID_DE | CPUID_FP87,
0514ef2f 1883 .features[FEAT_1_ECX] =
27861ecc 1884 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1885 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1886 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1887 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1888 CPUID_EXT_SSE3,
0514ef2f 1889 .features[FEAT_8000_0001_EDX] =
27861ecc 1890 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1891 CPUID_EXT2_SYSCALL,
0514ef2f 1892 .features[FEAT_8000_0001_ECX] =
27861ecc 1893 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1894 .features[FEAT_XSAVE] =
1895 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1896 .features[FEAT_6_EAX] =
1897 CPUID_6_EAX_ARAT,
3046bb5d 1898 .xlevel = 0x80000008,
3eca4642
EH		 1899 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1900 },
ac96c413
EH		 1901 {
1902 .name = "SandyBridge-IBRS",
1903 .level = 0xd,
1904 .vendor = CPUID_VENDOR_INTEL,
1905 .family = 6,
1906 .model = 42,
1907 .stepping = 1,
1908 .features[FEAT_1_EDX] =
1909 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1910 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1911 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1912 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1913 CPUID_DE | CPUID_FP87,
1914 .features[FEAT_1_ECX] =
1915 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1916 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1917 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1918 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1919 CPUID_EXT_SSE3,
1920 .features[FEAT_8000_0001_EDX] =
1921 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1922 CPUID_EXT2_SYSCALL,
1923 .features[FEAT_8000_0001_ECX] =
1924 CPUID_EXT3_LAHF_LM,
1925 .features[FEAT_7_0_EDX] =
1926 CPUID_7_0_EDX_SPEC_CTRL,
1927 .features[FEAT_XSAVE] =
1928 CPUID_XSAVE_XSAVEOPT,
1929 .features[FEAT_6_EAX] =
1930 CPUID_6_EAX_ARAT,
1931 .xlevel = 0x80000008,
1932 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1933 },
2f9ac42a
PB		 1934 {
1935 .name = "IvyBridge",
1936 .level = 0xd,
1937 .vendor = CPUID_VENDOR_INTEL,
1938 .family = 6,
1939 .model = 58,
1940 .stepping = 9,
1941 .features[FEAT_1_EDX] =
1942 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1943 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1944 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1945 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1946 CPUID_DE | CPUID_FP87,
1947 .features[FEAT_1_ECX] =
1948 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1949 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1950 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1951 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1952 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1953 .features[FEAT_7_0_EBX] =
1954 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1955 CPUID_7_0_EBX_ERMS,
1956 .features[FEAT_8000_0001_EDX] =
1957 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1958 CPUID_EXT2_SYSCALL,
1959 .features[FEAT_8000_0001_ECX] =
1960 CPUID_EXT3_LAHF_LM,
1961 .features[FEAT_XSAVE] =
1962 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1963 .features[FEAT_6_EAX] =
1964 CPUID_6_EAX_ARAT,
3046bb5d 1965 .xlevel = 0x80000008,
2f9ac42a
PB		 1966 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1967 },
ac96c413
EH		 1968 {
1969 .name = "IvyBridge-IBRS",
1970 .level = 0xd,
1971 .vendor = CPUID_VENDOR_INTEL,
1972 .family = 6,
1973 .model = 58,
1974 .stepping = 9,
1975 .features[FEAT_1_EDX] =
1976 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1977 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1978 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1979 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1980 CPUID_DE | CPUID_FP87,
1981 .features[FEAT_1_ECX] =
1982 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1983 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1984 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1985 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1986 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1987 .features[FEAT_7_0_EBX] =
1988 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1989 CPUID_7_0_EBX_ERMS,
1990 .features[FEAT_8000_0001_EDX] =
1991 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1992 CPUID_EXT2_SYSCALL,
1993 .features[FEAT_8000_0001_ECX] =
1994 CPUID_EXT3_LAHF_LM,
1995 .features[FEAT_7_0_EDX] =
1996 CPUID_7_0_EDX_SPEC_CTRL,
1997 .features[FEAT_XSAVE] =
1998 CPUID_XSAVE_XSAVEOPT,
1999 .features[FEAT_6_EAX] =
2000 CPUID_6_EAX_ARAT,
2001 .xlevel = 0x80000008,
2002 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2003 },
37507094 2004 {
a356850b
EH		 2005 .name = "Haswell-noTSX",
2006 .level = 0xd,
2007 .vendor = CPUID_VENDOR_INTEL,
2008 .family = 6,
2009 .model = 60,
2010 .stepping = 1,
2011 .features[FEAT_1_EDX] =
2012 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2013 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2014 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2015 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2016 CPUID_DE | CPUID_FP87,
2017 .features[FEAT_1_ECX] =
2018 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2019 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2020 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2021 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2022 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2023 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2024 .features[FEAT_8000_0001_EDX] =
2025 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2026 CPUID_EXT2_SYSCALL,
2027 .features[FEAT_8000_0001_ECX] =
becb6667 2028 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 2029 .features[FEAT_7_0_EBX] =
2030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2031 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2032 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2033 .features[FEAT_XSAVE] =
2034 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2035 .features[FEAT_6_EAX] =
2036 CPUID_6_EAX_ARAT,
3046bb5d 2037 .xlevel = 0x80000008,
a356850b 2038 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 2039 },
2040 {
2041 .name = "Haswell-noTSX-IBRS",
2042 .level = 0xd,
2043 .vendor = CPUID_VENDOR_INTEL,
2044 .family = 6,
2045 .model = 60,
2046 .stepping = 1,
2047 .features[FEAT_1_EDX] =
2048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2052 CPUID_DE | CPUID_FP87,
2053 .features[FEAT_1_ECX] =
2054 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2055 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2056 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2057 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2058 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2059 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2060 .features[FEAT_8000_0001_EDX] =
2061 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2062 CPUID_EXT2_SYSCALL,
2063 .features[FEAT_8000_0001_ECX] =
2064 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2065 .features[FEAT_7_0_EDX] =
2066 CPUID_7_0_EDX_SPEC_CTRL,
2067 .features[FEAT_7_0_EBX] =
2068 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2069 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2070 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2071 .features[FEAT_XSAVE] =
2072 CPUID_XSAVE_XSAVEOPT,
2073 .features[FEAT_6_EAX] =
2074 CPUID_6_EAX_ARAT,
2075 .xlevel = 0x80000008,
2076 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2077 },
2078 {
37507094
EH		 2079 .name = "Haswell",
2080 .level = 0xd,
99b88a17 2081 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2082 .family = 6,
2083 .model = 60,
ec56a4a7 2084 .stepping = 4,
0514ef2f 2085 .features[FEAT_1_EDX] =
b3a4f0b1 2086 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2087 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2088 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2089 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2090 CPUID_DE | CPUID_FP87,
0514ef2f 2091 .features[FEAT_1_ECX] =
27861ecc 2092 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2093 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2094 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2095 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2096 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2097 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2098 .features[FEAT_8000_0001_EDX] =
27861ecc 2099 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2100 CPUID_EXT2_SYSCALL,
0514ef2f 2101 .features[FEAT_8000_0001_ECX] =
becb6667 2102 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2103 .features[FEAT_7_0_EBX] =
27861ecc 2104 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2105 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2106 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2107 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2108 .features[FEAT_XSAVE] =
2109 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2110 .features[FEAT_6_EAX] =
2111 CPUID_6_EAX_ARAT,
3046bb5d 2112 .xlevel = 0x80000008,
37507094
EH		 2113 .model_id = "Intel Core Processor (Haswell)",
2114 },
ac96c413
EH		 2115 {
2116 .name = "Haswell-IBRS",
2117 .level = 0xd,
2118 .vendor = CPUID_VENDOR_INTEL,
2119 .family = 6,
2120 .model = 60,
2121 .stepping = 4,
2122 .features[FEAT_1_EDX] =
2123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2127 CPUID_DE | CPUID_FP87,
2128 .features[FEAT_1_ECX] =
2129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2130 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2131 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2132 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2133 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2134 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2135 .features[FEAT_8000_0001_EDX] =
2136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2137 CPUID_EXT2_SYSCALL,
2138 .features[FEAT_8000_0001_ECX] =
2139 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2140 .features[FEAT_7_0_EDX] =
2141 CPUID_7_0_EDX_SPEC_CTRL,
2142 .features[FEAT_7_0_EBX] =
2143 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2144 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2145 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2146 CPUID_7_0_EBX_RTM,
2147 .features[FEAT_XSAVE] =
2148 CPUID_XSAVE_XSAVEOPT,
2149 .features[FEAT_6_EAX] =
2150 CPUID_6_EAX_ARAT,
2151 .xlevel = 0x80000008,
2152 .model_id = "Intel Core Processor (Haswell, IBRS)",
2153 },
a356850b
EH		 2154 {
2155 .name = "Broadwell-noTSX",
2156 .level = 0xd,
2157 .vendor = CPUID_VENDOR_INTEL,
2158 .family = 6,
2159 .model = 61,
2160 .stepping = 2,
2161 .features[FEAT_1_EDX] =
2162 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2163 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2164 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2165 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2166 CPUID_DE | CPUID_FP87,
2167 .features[FEAT_1_ECX] =
2168 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2169 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2170 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2171 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2172 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2173 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2174 .features[FEAT_8000_0001_EDX] =
2175 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2176 CPUID_EXT2_SYSCALL,
2177 .features[FEAT_8000_0001_ECX] =
becb6667 2178 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2179 .features[FEAT_7_0_EBX] =
2180 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2181 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2182 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2183 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2184 CPUID_7_0_EBX_SMAP,
2185 .features[FEAT_XSAVE] =
2186 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2187 .features[FEAT_6_EAX] =
2188 CPUID_6_EAX_ARAT,
3046bb5d 2189 .xlevel = 0x80000008,
a356850b
EH		 2190 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2191 },
ac96c413
EH		 2192 {
2193 .name = "Broadwell-noTSX-IBRS",
2194 .level = 0xd,
2195 .vendor = CPUID_VENDOR_INTEL,
2196 .family = 6,
2197 .model = 61,
2198 .stepping = 2,
2199 .features[FEAT_1_EDX] =
2200 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2201 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2202 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2203 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2204 CPUID_DE | CPUID_FP87,
2205 .features[FEAT_1_ECX] =
2206 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2207 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2208 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2209 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2210 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2211 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2212 .features[FEAT_8000_0001_EDX] =
2213 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2214 CPUID_EXT2_SYSCALL,
2215 .features[FEAT_8000_0001_ECX] =
2216 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2217 .features[FEAT_7_0_EDX] =
2218 CPUID_7_0_EDX_SPEC_CTRL,
2219 .features[FEAT_7_0_EBX] =
2220 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2221 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2222 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2223 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2224 CPUID_7_0_EBX_SMAP,
2225 .features[FEAT_XSAVE] =
2226 CPUID_XSAVE_XSAVEOPT,
2227 .features[FEAT_6_EAX] =
2228 CPUID_6_EAX_ARAT,
2229 .xlevel = 0x80000008,
2230 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2231 },
ece01354
EH		 2232 {
2233 .name = "Broadwell",
2234 .level = 0xd,
2235 .vendor = CPUID_VENDOR_INTEL,
2236 .family = 6,
2237 .model = 61,
2238 .stepping = 2,
2239 .features[FEAT_1_EDX] =
b3a4f0b1 2240 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2241 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2242 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2243 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2244 CPUID_DE | CPUID_FP87,
2245 .features[FEAT_1_ECX] =
2246 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2247 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2248 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2249 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2250 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2251 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2252 .features[FEAT_8000_0001_EDX] =
2253 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2254 CPUID_EXT2_SYSCALL,
2255 .features[FEAT_8000_0001_ECX] =
becb6667 2256 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2257 .features[FEAT_7_0_EBX] =
2258 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2259 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2260 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2261 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2262 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2263 .features[FEAT_XSAVE] =
2264 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2265 .features[FEAT_6_EAX] =
2266 CPUID_6_EAX_ARAT,
3046bb5d 2267 .xlevel = 0x80000008,
ece01354
EH		 2268 .model_id = "Intel Core Processor (Broadwell)",
2269 },
ac96c413
EH		 2270 {
2271 .name = "Broadwell-IBRS",
2272 .level = 0xd,
2273 .vendor = CPUID_VENDOR_INTEL,
2274 .family = 6,
2275 .model = 61,
2276 .stepping = 2,
2277 .features[FEAT_1_EDX] =
2278 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2279 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2280 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2281 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2282 CPUID_DE | CPUID_FP87,
2283 .features[FEAT_1_ECX] =
2284 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2285 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2286 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2287 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2288 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2289 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2290 .features[FEAT_8000_0001_EDX] =
2291 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2292 CPUID_EXT2_SYSCALL,
2293 .features[FEAT_8000_0001_ECX] =
2294 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2295 .features[FEAT_7_0_EDX] =
2296 CPUID_7_0_EDX_SPEC_CTRL,
2297 .features[FEAT_7_0_EBX] =
2298 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2299 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2300 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2301 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2302 CPUID_7_0_EBX_SMAP,
2303 .features[FEAT_XSAVE] =
2304 CPUID_XSAVE_XSAVEOPT,
2305 .features[FEAT_6_EAX] =
2306 CPUID_6_EAX_ARAT,
2307 .xlevel = 0x80000008,
2308 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2309 },
f6f949e9
EH		 2310 {
2311 .name = "Skylake-Client",
2312 .level = 0xd,
2313 .vendor = CPUID_VENDOR_INTEL,
2314 .family = 6,
2315 .model = 94,
2316 .stepping = 3,
2317 .features[FEAT_1_EDX] =
2318 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2319 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2320 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2321 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2322 CPUID_DE | CPUID_FP87,
2323 .features[FEAT_1_ECX] =
2324 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2325 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2326 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2327 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2328 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2329 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2330 .features[FEAT_8000_0001_EDX] =
2331 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2332 CPUID_EXT2_SYSCALL,
2333 .features[FEAT_8000_0001_ECX] =
2334 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2335 .features[FEAT_7_0_EBX] =
2336 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2337 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2338 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2339 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2340 CPUID_7_0_EBX_SMAP,
f6f949e9 2341 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2342 * including v4.1 to v4.12).
f6f949e9
EH		 2343 * KVM doesn't yet expose any XSAVES state save component,
2344 * and the only one defined in Skylake (processor tracing)
2345 * probably will block migration anyway.
2346 */
2347 .features[FEAT_XSAVE] =
2348 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2349 CPUID_XSAVE_XGETBV1,
2350 .features[FEAT_6_EAX] =
2351 CPUID_6_EAX_ARAT,
2352 .xlevel = 0x80000008,
2353 .model_id = "Intel Core Processor (Skylake)",
2354 },
ac96c413
EH		 2355 {
2356 .name = "Skylake-Client-IBRS",
2357 .level = 0xd,
2358 .vendor = CPUID_VENDOR_INTEL,
2359 .family = 6,
2360 .model = 94,
2361 .stepping = 3,
2362 .features[FEAT_1_EDX] =
2363 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2364 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2365 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2366 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2367 CPUID_DE | CPUID_FP87,
2368 .features[FEAT_1_ECX] =
2369 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2370 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2371 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2372 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2373 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2374 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2375 .features[FEAT_8000_0001_EDX] =
2376 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2377 CPUID_EXT2_SYSCALL,
2378 .features[FEAT_8000_0001_ECX] =
2379 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2380 .features[FEAT_7_0_EDX] =
2381 CPUID_7_0_EDX_SPEC_CTRL,
2382 .features[FEAT_7_0_EBX] =
2383 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2384 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2385 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2386 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2387 CPUID_7_0_EBX_SMAP,
ac96c413
EH		 2388 /* Missing: XSAVES (not supported by some Linux versions,
2389 * including v4.1 to v4.12).
2390 * KVM doesn't yet expose any XSAVES state save component,
2391 * and the only one defined in Skylake (processor tracing)
2392 * probably will block migration anyway.
2393 */
2394 .features[FEAT_XSAVE] =
2395 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2396 CPUID_XSAVE_XGETBV1,
2397 .features[FEAT_6_EAX] =
2398 CPUID_6_EAX_ARAT,
2399 .xlevel = 0x80000008,
2400 .model_id = "Intel Core Processor (Skylake, IBRS)",
2401 },
53f9a6f4
BF		 2402 {
2403 .name = "Skylake-Server",
2404 .level = 0xd,
2405 .vendor = CPUID_VENDOR_INTEL,
2406 .family = 6,
2407 .model = 85,
2408 .stepping = 4,
2409 .features[FEAT_1_EDX] =
2410 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2411 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2412 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2413 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2414 CPUID_DE | CPUID_FP87,
2415 .features[FEAT_1_ECX] =
2416 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2417 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2418 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2419 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2420 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2421 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2422 .features[FEAT_8000_0001_EDX] =
2423 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2424 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2425 .features[FEAT_8000_0001_ECX] =
2426 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2427 .features[FEAT_7_0_EBX] =
2428 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2429 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2430 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2431 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2432 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2433 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2434 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2435 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2436 .features[FEAT_7_0_ECX] =
2437 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2438 /* Missing: XSAVES (not supported by some Linux versions,
2439 * including v4.1 to v4.12).
2440 * KVM doesn't yet expose any XSAVES state save component,
2441 * and the only one defined in Skylake (processor tracing)
2442 * probably will block migration anyway.
2443 */
2444 .features[FEAT_XSAVE] =
2445 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2446 CPUID_XSAVE_XGETBV1,
2447 .features[FEAT_6_EAX] =
2448 CPUID_6_EAX_ARAT,
2449 .xlevel = 0x80000008,
2450 .model_id = "Intel Xeon Processor (Skylake)",
2451 },
ac96c413
EH		 2452 {
2453 .name = "Skylake-Server-IBRS",
2454 .level = 0xd,
2455 .vendor = CPUID_VENDOR_INTEL,
2456 .family = 6,
2457 .model = 85,
2458 .stepping = 4,
2459 .features[FEAT_1_EDX] =
2460 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2461 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2462 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2463 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2464 CPUID_DE | CPUID_FP87,
2465 .features[FEAT_1_ECX] =
2466 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2467 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2468 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2469 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2470 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2471 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2472 .features[FEAT_8000_0001_EDX] =
2473 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2474 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2475 .features[FEAT_8000_0001_ECX] =
2476 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2477 .features[FEAT_7_0_EDX] =
2478 CPUID_7_0_EDX_SPEC_CTRL,
2479 .features[FEAT_7_0_EBX] =
2480 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2481 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2482 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2483 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2484 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
ac96c413
EH		 2485 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2486 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2487 CPUID_7_0_EBX_AVX512VL,
09b9ee64
TX		 2488 .features[FEAT_7_0_ECX] =
2489 CPUID_7_0_ECX_PKU,
ac96c413
EH		 2490 /* Missing: XSAVES (not supported by some Linux versions,
2491 * including v4.1 to v4.12).
2492 * KVM doesn't yet expose any XSAVES state save component,
2493 * and the only one defined in Skylake (processor tracing)
2494 * probably will block migration anyway.
2495 */
2496 .features[FEAT_XSAVE] =
2497 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2498 CPUID_XSAVE_XGETBV1,
2499 .features[FEAT_6_EAX] =
2500 CPUID_6_EAX_ARAT,
2501 .xlevel = 0x80000008,
2502 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2503 },
c7a88b52
TX		 2504 {
2505 .name = "Cascadelake-Server",
2506 .level = 0xd,
2507 .vendor = CPUID_VENDOR_INTEL,
2508 .family = 6,
2509 .model = 85,
b0a19803 2510 .stepping = 6,
c7a88b52
TX		 2511 .features[FEAT_1_EDX] =
2512 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2513 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2514 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2515 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2516 CPUID_DE | CPUID_FP87,
2517 .features[FEAT_1_ECX] =
2518 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2519 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2520 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2521 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2522 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2523 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2524 .features[FEAT_8000_0001_EDX] =
2525 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2526 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2527 .features[FEAT_8000_0001_ECX] =
2528 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2529 .features[FEAT_7_0_EBX] =
2530 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2531 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2532 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2533 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2534 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 2535 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2536 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2537 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 2538 .features[FEAT_7_0_ECX] =
bb4928c7 2539 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 2540 CPUID_7_0_ECX_AVX512VNNI,
2541 .features[FEAT_7_0_EDX] =
2542 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2543 /* Missing: XSAVES (not supported by some Linux versions,
2544 * including v4.1 to v4.12).
2545 * KVM doesn't yet expose any XSAVES state save component,
2546 * and the only one defined in Skylake (processor tracing)
2547 * probably will block migration anyway.
2548 */
2549 .features[FEAT_XSAVE] =
2550 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2551 CPUID_XSAVE_XGETBV1,
2552 .features[FEAT_6_EAX] =
2553 CPUID_6_EAX_ARAT,
2554 .xlevel = 0x80000008,
2555 .model_id = "Intel Xeon Processor (Cascadelake)",
2556 },
8a11c62d
RH		 2557 {
2558 .name = "Icelake-Client",
2559 .level = 0xd,
2560 .vendor = CPUID_VENDOR_INTEL,
2561 .family = 6,
2562 .model = 126,
2563 .stepping = 0,
2564 .features[FEAT_1_EDX] =
2565 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2566 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2567 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2568 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2569 CPUID_DE | CPUID_FP87,
2570 .features[FEAT_1_ECX] =
2571 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2572 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2573 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2574 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2575 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2576 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2577 .features[FEAT_8000_0001_EDX] =
2578 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2579 CPUID_EXT2_SYSCALL,
2580 .features[FEAT_8000_0001_ECX] =
2581 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2582 .features[FEAT_8000_0008_EBX] =
2583 CPUID_8000_0008_EBX_WBNOINVD,
2584 .features[FEAT_7_0_EBX] =
2585 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2586 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2587 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2588 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 2589 CPUID_7_0_EBX_SMAP,
8a11c62d
RH		 2590 .features[FEAT_7_0_ECX] =
2591 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2592 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2593 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2594 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2595 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2596 .features[FEAT_7_0_EDX] =
2597 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2598 /* Missing: XSAVES (not supported by some Linux versions,
2599 * including v4.1 to v4.12).
2600 * KVM doesn't yet expose any XSAVES state save component,
2601 * and the only one defined in Skylake (processor tracing)
2602 * probably will block migration anyway.
2603 */
2604 .features[FEAT_XSAVE] =
2605 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2606 CPUID_XSAVE_XGETBV1,
2607 .features[FEAT_6_EAX] =
2608 CPUID_6_EAX_ARAT,
2609 .xlevel = 0x80000008,
2610 .model_id = "Intel Core Processor (Icelake)",
2611 },
2612 {
2613 .name = "Icelake-Server",
2614 .level = 0xd,
2615 .vendor = CPUID_VENDOR_INTEL,
2616 .family = 6,
2617 .model = 134,
2618 .stepping = 0,
2619 .features[FEAT_1_EDX] =
2620 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2621 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2622 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2623 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2624 CPUID_DE | CPUID_FP87,
2625 .features[FEAT_1_ECX] =
2626 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2627 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2628 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2629 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2630 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2631 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2632 .features[FEAT_8000_0001_EDX] =
2633 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2634 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2635 .features[FEAT_8000_0001_ECX] =
2636 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2637 .features[FEAT_8000_0008_EBX] =
2638 CPUID_8000_0008_EBX_WBNOINVD,
2639 .features[FEAT_7_0_EBX] =
2640 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2641 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2642 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2643 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2644 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 2645 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2646 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2647 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d
RH		 2648 .features[FEAT_7_0_ECX] =
2649 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2650 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2651 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2652 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2653 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2654 .features[FEAT_7_0_EDX] =
76e5a4d5 2655 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 2656 /* Missing: XSAVES (not supported by some Linux versions,
2657 * including v4.1 to v4.12).
2658 * KVM doesn't yet expose any XSAVES state save component,
2659 * and the only one defined in Skylake (processor tracing)
2660 * probably will block migration anyway.
2661 */
2662 .features[FEAT_XSAVE] =
2663 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2664 CPUID_XSAVE_XGETBV1,
2665 .features[FEAT_6_EAX] =
2666 CPUID_6_EAX_ARAT,
2667 .xlevel = 0x80000008,
2668 .model_id = "Intel Xeon Processor (Icelake)",
2669 },
a1849515
BF		 2670 {
2671 .name = "KnightsMill",
2672 .level = 0xd,
2673 .vendor = CPUID_VENDOR_INTEL,
2674 .family = 6,
2675 .model = 133,
2676 .stepping = 0,
2677 .features[FEAT_1_EDX] =
2678 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2679 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2680 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2681 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2682 CPUID_PSE | CPUID_DE | CPUID_FP87,
2683 .features[FEAT_1_ECX] =
2684 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2685 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2686 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2687 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2688 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2689 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2690 .features[FEAT_8000_0001_EDX] =
2691 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2692 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2693 .features[FEAT_8000_0001_ECX] =
2694 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2695 .features[FEAT_7_0_EBX] =
2696 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2697 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2698 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2699 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2700 CPUID_7_0_EBX_AVX512ER,
2701 .features[FEAT_7_0_ECX] =
2702 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2703 .features[FEAT_7_0_EDX] =
2704 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2705 .features[FEAT_XSAVE] =
2706 CPUID_XSAVE_XSAVEOPT,
2707 .features[FEAT_6_EAX] =
2708 CPUID_6_EAX_ARAT,
2709 .xlevel = 0x80000008,
2710 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2711 },
3eca4642
EH		 2712 {
2713 .name = "Opteron_G1",
2714 .level = 5,
99b88a17 2715 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2716 .family = 15,
2717 .model = 6,
2718 .stepping = 1,
0514ef2f 2719 .features[FEAT_1_EDX] =
b3a4f0b1 2720 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2721 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2722 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2723 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2724 CPUID_DE | CPUID_FP87,
0514ef2f 2725 .features[FEAT_1_ECX] =
27861ecc 2726 CPUID_EXT_SSE3,
0514ef2f 2727 .features[FEAT_8000_0001_EDX] =
2a923a29 2728 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2729 .xlevel = 0x80000008,
2730 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2731 },
2732 {
2733 .name = "Opteron_G2",
2734 .level = 5,
99b88a17 2735 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2736 .family = 15,
2737 .model = 6,
2738 .stepping = 1,
0514ef2f 2739 .features[FEAT_1_EDX] =
b3a4f0b1 2740 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2741 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2742 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2743 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2744 CPUID_DE | CPUID_FP87,
0514ef2f 2745 .features[FEAT_1_ECX] =
27861ecc 2746 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 2747 .features[FEAT_8000_0001_EDX] =
2a923a29 2748 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2749 .features[FEAT_8000_0001_ECX] =
27861ecc 2750 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2751 .xlevel = 0x80000008,
2752 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2753 },
2754 {
2755 .name = "Opteron_G3",
2756 .level = 5,
99b88a17 2757 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2758 .family = 16,
2759 .model = 2,
2760 .stepping = 3,
0514ef2f 2761 .features[FEAT_1_EDX] =
b3a4f0b1 2762 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2763 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2764 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2765 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2766 CPUID_DE | CPUID_FP87,
0514ef2f 2767 .features[FEAT_1_ECX] =
27861ecc 2768 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2769 CPUID_EXT_SSE3,
0514ef2f 2770 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 2771 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2772 CPUID_EXT2_RDTSCP,
0514ef2f 2773 .features[FEAT_8000_0001_ECX] =
27861ecc 2774 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2775 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2776 .xlevel = 0x80000008,
2777 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2778 },
2779 {
2780 .name = "Opteron_G4",
2781 .level = 0xd,
99b88a17 2782 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2783 .family = 21,
2784 .model = 1,
2785 .stepping = 2,
0514ef2f 2786 .features[FEAT_1_EDX] =
b3a4f0b1 2787 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2788 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2789 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2790 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2791 CPUID_DE | CPUID_FP87,
0514ef2f 2792 .features[FEAT_1_ECX] =
27861ecc 2793 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2794 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2795 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2796 CPUID_EXT_SSE3,
0514ef2f 2797 .features[FEAT_8000_0001_EDX] =
2a923a29 2798 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2799 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2800 .features[FEAT_8000_0001_ECX] =
27861ecc 2801 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2802 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2803 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2804 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2805 .features[FEAT_SVM] =
2806 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2807 /* no xsaveopt! */
3eca4642
EH		 2808 .xlevel = 0x8000001A,
2809 .model_id = "AMD Opteron 62xx class CPU",
2810 },
021941b9
AP		 2811 {
2812 .name = "Opteron_G5",
2813 .level = 0xd,
99b88a17 2814 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2815 .family = 21,
2816 .model = 2,
2817 .stepping = 0,
0514ef2f 2818 .features[FEAT_1_EDX] =
b3a4f0b1 2819 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2823 CPUID_DE | CPUID_FP87,
0514ef2f 2824 .features[FEAT_1_ECX] =
27861ecc 2825 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2826 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2827 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2828 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2829 .features[FEAT_8000_0001_EDX] =
2a923a29 2830 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2831 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2832 .features[FEAT_8000_0001_ECX] =
27861ecc 2833 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2834 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2835 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2836 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2837 .features[FEAT_SVM] =
2838 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2839 /* no xsaveopt! */
021941b9
AP		 2840 .xlevel = 0x8000001A,
2841 .model_id = "AMD Opteron 63xx class CPU",
2842 },
2e2efc7d
BS		 2843 {
2844 .name = "EPYC",
2845 .level = 0xd,
2846 .vendor = CPUID_VENDOR_AMD,
2847 .family = 23,
2848 .model = 1,
2849 .stepping = 2,
2850 .features[FEAT_1_EDX] =
2851 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2852 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2853 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2854 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2855 CPUID_VME | CPUID_FP87,
2856 .features[FEAT_1_ECX] =
2857 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2858 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2859 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2860 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2861 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2862 .features[FEAT_8000_0001_EDX] =
2863 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2864 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2865 CPUID_EXT2_SYSCALL,
2866 .features[FEAT_8000_0001_ECX] =
2867 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2868 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2869 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2870 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2871 .features[FEAT_7_0_EBX] =
2872 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2873 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2874 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2875 CPUID_7_0_EBX_SHA_NI,
2876 /* Missing: XSAVES (not supported by some Linux versions,
2877 * including v4.1 to v4.12).
2878 * KVM doesn't yet expose any XSAVES state save component.
2879 */
2880 .features[FEAT_XSAVE] =
2881 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2882 CPUID_XSAVE_XGETBV1,
2883 .features[FEAT_6_EAX] =
2884 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2885 .features[FEAT_SVM] =
2886 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2887 .xlevel = 0x8000001E,
2e2efc7d 2888 .model_id = "AMD EPYC Processor",
fe52acd2 2889 .cache_info = &epyc_cache_info,
2e2efc7d 2890 },
6cfbc54e
EH		 2891 {
2892 .name = "EPYC-IBPB",
2893 .level = 0xd,
2894 .vendor = CPUID_VENDOR_AMD,
2895 .family = 23,
2896 .model = 1,
2897 .stepping = 2,
2898 .features[FEAT_1_EDX] =
2899 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2900 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2901 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2902 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2903 CPUID_VME | CPUID_FP87,
2904 .features[FEAT_1_ECX] =
2905 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2906 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2907 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2908 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2909 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2910 .features[FEAT_8000_0001_EDX] =
2911 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2912 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2913 CPUID_EXT2_SYSCALL,
2914 .features[FEAT_8000_0001_ECX] =
2915 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2916 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2917 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2918 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2919 .features[FEAT_8000_0008_EBX] =
2920 CPUID_8000_0008_EBX_IBPB,
2921 .features[FEAT_7_0_EBX] =
2922 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2923 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2924 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2925 CPUID_7_0_EBX_SHA_NI,
2926 /* Missing: XSAVES (not supported by some Linux versions,
2927 * including v4.1 to v4.12).
2928 * KVM doesn't yet expose any XSAVES state save component.
2929 */
2930 .features[FEAT_XSAVE] =
2931 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2932 CPUID_XSAVE_XGETBV1,
2933 .features[FEAT_6_EAX] =
2934 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2935 .features[FEAT_SVM] =
2936 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2937 .xlevel = 0x8000001E,
6cfbc54e 2938 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2939 .cache_info = &epyc_cache_info,
6cfbc54e 2940 },
8d031cec
PW		 2941 {
2942 .name = "Dhyana",
2943 .level = 0xd,
2944 .vendor = CPUID_VENDOR_HYGON,
2945 .family = 24,
2946 .model = 0,
2947 .stepping = 1,
2948 .features[FEAT_1_EDX] =
2949 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2950 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2951 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2952 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2953 CPUID_VME | CPUID_FP87,
2954 .features[FEAT_1_ECX] =
2955 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2956 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2957 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2958 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2959 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2960 .features[FEAT_8000_0001_EDX] =
2961 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2962 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2963 CPUID_EXT2_SYSCALL,
2964 .features[FEAT_8000_0001_ECX] =
2965 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2966 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2967 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2968 CPUID_EXT3_TOPOEXT,
2969 .features[FEAT_8000_0008_EBX] =
2970 CPUID_8000_0008_EBX_IBPB,
2971 .features[FEAT_7_0_EBX] =
2972 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2973 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2974 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2975 /*
2976 * Missing: XSAVES (not supported by some Linux versions,
2977 * including v4.1 to v4.12).
2978 * KVM doesn't yet expose any XSAVES state save component.
2979 */
2980 .features[FEAT_XSAVE] =
2981 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2982 CPUID_XSAVE_XGETBV1,
2983 .features[FEAT_6_EAX] =
2984 CPUID_6_EAX_ARAT,
2985 .features[FEAT_SVM] =
2986 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2987 .xlevel = 0x8000001E,
2988 .model_id = "Hygon Dhyana Processor",
2989 .cache_info = &epyc_cache_info,
2990 },
c6dc6f63
AP		 2991};
2992
5114e842
EH		 2993typedef struct PropValue {
2994 const char *prop, *value;
2995} PropValue;
2996
2997/* KVM-specific features that are automatically added/removed
2998 * from all CPU models when KVM is enabled.
2999 */
3000static PropValue kvm_default_props[] = {
3001 { "kvmclock", "on" },
3002 { "kvm-nopiodelay", "on" },
3003 { "kvm-asyncpf", "on" },
3004 { "kvm-steal-time", "on" },
3005 { "kvm-pv-eoi", "on" },
3006 { "kvmclock-stable-bit", "on" },
3007 { "x2apic", "on" },
3008 { "acpi", "off" },
3009 { "monitor", "off" },
3010 { "svm", "off" },
3011 { NULL, NULL },
3012};
3013
04d99c3c
EH		 3014/* TCG-specific defaults that override all CPU models when using TCG
3015 */
3016static PropValue tcg_default_props[] = {
3017 { "vme", "off" },
3018 { NULL, NULL },
3019};
3020
3021
5114e842
EH		 3022void x86_cpu_change_kvm_default(const char *prop, const char *value)
3023{
3024 PropValue *pv;
3025 for (pv = kvm_default_props; pv->prop; pv++) {
3026 if (!strcmp(pv->prop, prop)) {
3027 pv->value = value;
3028 break;
3029 }
3030 }
3031
3032 /* It is valid to call this function only for properties that
3033 * are already present in the kvm_default_props table.
3034 */
3035 assert(pv->prop);
3036}
3037
4d1b279b
EH		 3038static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3039 bool migratable_only);
3040
40bfe48f
HZ		 3041static bool lmce_supported(void)
3042{
c62f2630 3043 uint64_t mce_cap = 0;
40bfe48f 3044
c62f2630 3045#ifdef CONFIG_KVM
40bfe48f
HZ		 3046 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
3047 return false;
3048 }
c62f2630 3049#endif
40bfe48f
HZ		 3050
3051 return !!(mce_cap & MCG_LMCE_P);
3052}
3053
7d8050b5
EH		 3054#define CPUID_MODEL_ID_SZ 48
3055
3056/**
3057 * cpu_x86_fill_model_id:
3058 * Get CPUID model ID string from host CPU.
3059 *
3060 * @str should have at least CPUID_MODEL_ID_SZ bytes
3061 *
3062 * The function does NOT add a null terminator to the string
3063 * automatically.
3064 */
c6dc6f63
AP		 3065static int cpu_x86_fill_model_id(char *str)
3066{
3067 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3068 int i;
3069
3070 for (i = 0; i < 3; i++) {
3071 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3072 memcpy(str + i * 16 + 0, &eax, 4);
3073 memcpy(str + i * 16 + 4, &ebx, 4);
3074 memcpy(str + i * 16 + 8, &ecx, 4);
3075 memcpy(str + i * 16 + 12, &edx, 4);
3076 }
3077 return 0;
3078}
3079
c62f2630 3080static Property max_x86_cpu_properties[] = {
120eee7d 3081 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 3082 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 3083 DEFINE_PROP_END_OF_LIST()
3084};
3085
c62f2630 3086static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 3087{
84f1b92f 3088 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 3089 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 3090
f48c8837 3091 xcc->ordering = 9;
6e746f30 3092
ee465a3e 3093 xcc->model_description =
c62f2630 3094 "Enables all features supported by the accelerator in the current host";
d940ee9b 3095
c62f2630 3096 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3097}
3098
0bacd8b3
EH		 3099static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3100
c62f2630 3101static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3102{
3103 X86CPU *cpu = X86_CPU(obj);
3104 CPUX86State *env = &cpu->env;
3105 KVMState *s = kvm_state;
d940ee9b 3106
4d1b279b
EH		 3107 /* We can't fill the features array here because we don't know yet if
3108 * "migratable" is true or false.
3109 */
44bd8e53 3110 cpu->max_features = true;
4d1b279b 3111
d6dcc558 3112 if (accel_uses_host_cpuid()) {
bd182022
EH		 3113 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3114 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3115 int family, model, stepping;
d6dcc558
SAGDR		 3116 X86CPUDefinition host_cpudef = { };
3117 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3118
3119 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3120 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3121
bd182022 3122 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3123
bd182022 3124 cpu_x86_fill_model_id(model_id);
0bacd8b3 3125
bd182022
EH		 3126 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3127 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3128 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3129 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3130 &error_abort);
3131 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3132 &error_abort);
0bacd8b3 3133
d6dcc558
SAGDR		 3134 if (kvm_enabled()) {
3135 env->cpuid_min_level =
3136 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3137 env->cpuid_min_xlevel =
3138 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3139 env->cpuid_min_xlevel2 =
3140 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3141 } else {
3142 env->cpuid_min_level =
3143 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3144 env->cpuid_min_xlevel =
3145 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3146 env->cpuid_min_xlevel2 =
3147 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3148 }
40bfe48f
HZ		 3149
3150 if (lmce_supported()) {
3151 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3152 }
6900d1cc
EH		 3153 } else {
3154 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3155 "vendor", &error_abort);
3156 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3157 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3158 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3159 object_property_set_str(OBJECT(cpu),
3160 "QEMU TCG CPU version " QEMU_HW_VERSION,
3161 "model-id", &error_abort);
e4356010 3162 }
2a573259 3163
d940ee9b 3164 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3165}
3166
c62f2630
EH		 3167static const TypeInfo max_x86_cpu_type_info = {
3168 .name = X86_CPU_TYPE_NAME("max"),
3169 .parent = TYPE_X86_CPU,
3170 .instance_init = max_x86_cpu_initfn,
3171 .class_init = max_x86_cpu_class_init,
3172};
3173
d6dcc558 3174#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3175static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3176{
3177 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3178
d6dcc558 3179 xcc->host_cpuid_required = true;
c62f2630
EH		 3180 xcc->ordering = 8;
3181
02693cc4
GK		 3182#if defined(CONFIG_KVM)
3183 xcc->model_description =
3184 "KVM processor with all supported host features ";
3185#elif defined(CONFIG_HVF)
3186 xcc->model_description =
3187 "HVF processor with all supported host features ";
3188#endif
c62f2630
EH		 3189}
3190
d940ee9b
EH		 3191static const TypeInfo host_x86_cpu_type_info = {
3192 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3193 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3194 .class_init = host_x86_cpu_class_init,
3195};
3196
3197#endif
3198
07585923
RH		 3199static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3200{
3201 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3202
3203 switch (f->type) {
3204 case CPUID_FEATURE_WORD:
3205 {
3206 const char *reg = get_register_name_32(f->cpuid.reg);
3207 assert(reg);
3208 return g_strdup_printf("CPUID.%02XH:%s",
3209 f->cpuid.eax, reg);
3210 }
3211 case MSR_FEATURE_WORD:
3212 return g_strdup_printf("MSR(%02XH)",
3213 f->msr.index);
3214 }
3215
3216 return NULL;
3217}
3218
8459e396 3219static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3220{
8459e396 3221 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3222 int i;
07585923 3223 char *feat_word_str;
c6dc6f63 3224
857aee33 3225 for (i = 0; i < 32; ++i) {
72370dc1 3226 if ((1UL << i) & mask) {
07585923
RH		 3227 feat_word_str = feature_word_description(f, i);
3228 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3229 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3230 feat_word_str,
8297be80
AF		 3231 f->feat_names[i] ? "." : "",
3232 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3233 g_free(feat_word_str);
c6dc6f63 3234 }
857aee33 3235 }
c6dc6f63
AP		 3236}
3237
d7bce999
EB		 3238static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3239 const char *name, void *opaque,
3240 Error **errp)
95b8519d
AF		 3241{
3242 X86CPU *cpu = X86_CPU(obj);
3243 CPUX86State *env = &cpu->env;
3244 int64_t value;
3245
3246 value = (env->cpuid_version >> 8) & 0xf;
3247 if (value == 0xf) {
3248 value += (env->cpuid_version >> 20) & 0xff;
3249 }
51e72bc1 3250 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3251}
3252
d7bce999
EB		 3253static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3254 const char *name, void *opaque,
3255 Error **errp)
ed5e1ec3 3256{
71ad61d3
AF		 3257 X86CPU *cpu = X86_CPU(obj);
3258 CPUX86State *env = &cpu->env;
3259 const int64_t min = 0;
3260 const int64_t max = 0xff + 0xf;
65cd9064 3261 Error *local_err = NULL;
71ad61d3
AF		 3262 int64_t value;
3263
51e72bc1 3264 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3265 if (local_err) {
3266 error_propagate(errp, local_err);
71ad61d3
AF		 3267 return;
3268 }
3269 if (value < min || value > max) {
c6bd8c70
MA		 3270 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3271 name ? name : "null", value, min, max);
71ad61d3
AF		 3272 return;
3273 }
3274
ed5e1ec3 3275 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3276 if (value > 0x0f) {
3277 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3278 } else {
71ad61d3 3279 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3280 }
3281}
3282
d7bce999
EB		 3283static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3284 const char *name, void *opaque,
3285 Error **errp)
67e30c83
AF		 3286{
3287 X86CPU *cpu = X86_CPU(obj);
3288 CPUX86State *env = &cpu->env;
3289 int64_t value;
3290
3291 value = (env->cpuid_version >> 4) & 0xf;
3292 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3293 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3294}
3295
d7bce999
EB		 3296static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3297 const char *name, void *opaque,
3298 Error **errp)
b0704cbd 3299{
c5291a4f
AF		 3300 X86CPU *cpu = X86_CPU(obj);
3301 CPUX86State *env = &cpu->env;
3302 const int64_t min = 0;
3303 const int64_t max = 0xff;
65cd9064 3304 Error *local_err = NULL;
c5291a4f
AF		 3305 int64_t value;
3306
51e72bc1 3307 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3308 if (local_err) {
3309 error_propagate(errp, local_err);
c5291a4f
AF		 3310 return;
3311 }
3312 if (value < min || value > max) {
c6bd8c70
MA		 3313 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3314 name ? name : "null", value, min, max);
c5291a4f
AF		 3315 return;
3316 }
3317
b0704cbd 3318 env->cpuid_version &= ~0xf00f0;
c5291a4f 3319 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3320}
3321
35112e41 3322static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3323 const char *name, void *opaque,
35112e41
AF		 3324 Error **errp)
3325{
3326 X86CPU *cpu = X86_CPU(obj);
3327 CPUX86State *env = &cpu->env;
3328 int64_t value;
3329
3330 value = env->cpuid_version & 0xf;
51e72bc1 3331 visit_type_int(v, name, &value, errp);
35112e41
AF		 3332}
3333
036e2222 3334static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3335 const char *name, void *opaque,
036e2222 3336 Error **errp)
38c3dc46 3337{
036e2222
AF		 3338 X86CPU *cpu = X86_CPU(obj);
3339 CPUX86State *env = &cpu->env;
3340 const int64_t min = 0;
3341 const int64_t max = 0xf;
65cd9064 3342 Error *local_err = NULL;
036e2222
AF		 3343 int64_t value;
3344
51e72bc1 3345 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3346 if (local_err) {
3347 error_propagate(errp, local_err);
036e2222
AF		 3348 return;
3349 }
3350 if (value < min || value > max) {
c6bd8c70
MA		 3351 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3352 name ? name : "null", value, min, max);
036e2222
AF		 3353 return;
3354 }
3355
38c3dc46 3356 env->cpuid_version &= ~0xf;
036e2222 3357 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3358}
3359
d480e1af
AF		 3360static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3361{
3362 X86CPU *cpu = X86_CPU(obj);
3363 CPUX86State *env = &cpu->env;
3364 char *value;
d480e1af 3365
e42a92ae 3366 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3367 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3368 env->cpuid_vendor3);
d480e1af
AF		 3369 return value;
3370}
3371
3372static void x86_cpuid_set_vendor(Object *obj, const char *value,
3373 Error **errp)
3374{
3375 X86CPU *cpu = X86_CPU(obj);
3376 CPUX86State *env = &cpu->env;
3377 int i;
3378
9df694ee 3379 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3380 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3381 return;
3382 }
3383
3384 env->cpuid_vendor1 = 0;
3385 env->cpuid_vendor2 = 0;
3386 env->cpuid_vendor3 = 0;
3387 for (i = 0; i < 4; i++) {
3388 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3389 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3390 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3391 }
d480e1af
AF		 3392}
3393
63e886eb
AF		 3394static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3395{
3396 X86CPU *cpu = X86_CPU(obj);
3397 CPUX86State *env = &cpu->env;
3398 char *value;
3399 int i;
3400
3401 value = g_malloc(48 + 1);
3402 for (i = 0; i < 48; i++) {
3403 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3404 }
3405 value[48] = '\0';
3406 return value;
3407}
3408
938d4c25
AF		 3409static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3410 Error **errp)
dcce6675 3411{
938d4c25
AF		 3412 X86CPU *cpu = X86_CPU(obj);
3413 CPUX86State *env = &cpu->env;
dcce6675
AF		 3414 int c, len, i;
3415
3416 if (model_id == NULL) {
3417 model_id = "";
3418 }
3419 len = strlen(model_id);
d0a6acf4 3420 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3421 for (i = 0; i < 48; i++) {
3422 if (i >= len) {
3423 c = '\0';
3424 } else {
3425 c = (uint8_t)model_id[i];
3426 }
3427 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3428 }
3429}
3430
d7bce999
EB		 3431static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3432 void *opaque, Error **errp)
89e48965
AF		 3433{
3434 X86CPU *cpu = X86_CPU(obj);
3435 int64_t value;
3436
3437 value = cpu->env.tsc_khz * 1000;
51e72bc1 3438 visit_type_int(v, name, &value, errp);
89e48965
AF		 3439}
3440
d7bce999
EB		 3441static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3442 void *opaque, Error **errp)
89e48965
AF		 3443{
3444 X86CPU *cpu = X86_CPU(obj);
3445 const int64_t min = 0;
2e84849a 3446 const int64_t max = INT64_MAX;
65cd9064 3447 Error *local_err = NULL;
89e48965
AF		 3448 int64_t value;
3449
51e72bc1 3450 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3451 if (local_err) {
3452 error_propagate(errp, local_err);
89e48965
AF		 3453 return;
3454 }
3455 if (value < min || value > max) {
c6bd8c70
MA		 3456 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3457 name ? name : "null", value, min, max);
89e48965
AF		 3458 return;
3459 }
3460
36f96c4b 3461 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3462}
3463
7e5292b5 3464/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3465static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3466 const char *name, void *opaque,
3467 Error **errp)
8e8aba50 3468{
7e5292b5 3469 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3470 FeatureWord w;
8e8aba50
EH		 3471 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3472 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3473 X86CPUFeatureWordInfoList *list = NULL;
3474
3475 for (w = 0; w < FEATURE_WORDS; w++) {
3476 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3477 /*
3478 * We didn't have MSR features when "feature-words" was
3479 * introduced. Therefore skipped other type entries.
3480 */
3481 if (wi->type != CPUID_FEATURE_WORD) {
3482 continue;
3483 }
8e8aba50 3484 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3485 qwi->cpuid_input_eax = wi->cpuid.eax;
3486 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3487 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3488 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3489 qwi->features = array[w];
8e8aba50
EH		 3490
3491 /* List will be in reverse order, but order shouldn't matter */
3492 list_entries[w].next = list;
3493 list_entries[w].value = &word_infos[w];
3494 list = &list_entries[w];
3495 }
3496
6b62d961 3497 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3498}
3499
d7bce999
EB		 3500static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3501 void *opaque, Error **errp)
c8f0f88e
IM		 3502{
3503 X86CPU *cpu = X86_CPU(obj);
3504 int64_t value = cpu->hyperv_spinlock_attempts;
3505
51e72bc1 3506 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3507}
3508
d7bce999
EB		 3509static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3510 void *opaque, Error **errp)
c8f0f88e
IM		 3511{
3512 const int64_t min = 0xFFF;
3513 const int64_t max = UINT_MAX;
3514 X86CPU *cpu = X86_CPU(obj);
3515 Error *err = NULL;
3516 int64_t value;
3517
51e72bc1 3518 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3519 if (err) {
3520 error_propagate(errp, err);
3521 return;
3522 }
3523
3524 if (value < min || value > max) {
3525 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3526 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3527 object_get_typename(obj), name ? name : "null",
3528 value, min, max);
c8f0f88e
IM		 3529 return;
3530 }
3531 cpu->hyperv_spinlock_attempts = value;
3532}
3533
1b6b7d10 3534static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3535 .name = "int",
3536 .get = x86_get_hv_spinlocks,
3537 .set = x86_set_hv_spinlocks,
3538};
3539
72ac2e87
IM		 3540/* Convert all '_' in a feature string option name to '-', to make feature
3541 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3542 */
3543static inline void feat2prop(char *s)
3544{
3545 while ((s = strchr(s, '_'))) {
3546 *s = '-';
3547 }
3548}
3549
b54c9377
EH		 3550/* Return the feature property name for a feature flag bit */
3551static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3552{
3553 /* XSAVE components are automatically enabled by other features,
3554 * so return the original feature name instead
3555 */
3556 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3557 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3558
3559 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3560 x86_ext_save_areas[comp].bits) {
3561 w = x86_ext_save_areas[comp].feature;
3562 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3563 }
3564 }
3565
3566 assert(bitnr < 32);
3567 assert(w < FEATURE_WORDS);
3568 return feature_word_info[w].feat_names[bitnr];
3569}
3570
dc15c051
IM		 3571/* Compatibily hack to maintain legacy +-feat semantic,
3572 * where +-feat overwrites any feature set by
3573 * feat=on|feat even if the later is parsed after +-feat
3574 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3575 */
2fae0d96 3576static GList *plus_features, *minus_features;
dc15c051 3577
83a00f60
EH		 3578static gint compare_string(gconstpointer a, gconstpointer b)
3579{
3580 return g_strcmp0(a, b);
3581}
3582
8f961357
EH		 3583/* Parse "+feature,-feature,feature=foo" CPU feature string
3584 */
62a48a2a 3585static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3586 Error **errp)
8f961357 3587{
8f961357 3588 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3589 static bool cpu_globals_initialized;
83a00f60 3590 bool ambiguous = false;
62a48a2a
IM		 3591
3592 if (cpu_globals_initialized) {
3593 return;
3594 }
3595 cpu_globals_initialized = true;
8f961357 3596
f6750e95
EH		 3597 if (!features) {
3598 return;
3599 }
3600
3601 for (featurestr = strtok(features, ",");
685479bd 3602 featurestr;
f6750e95
EH		 3603 featurestr = strtok(NULL, ",")) {
3604 const char *name;
3605 const char *val = NULL;
3606 char *eq = NULL;
cf2887c9 3607 char num[32];
62a48a2a 3608 GlobalProperty *prop;
c6dc6f63 3609
f6750e95 3610 /* Compatibility syntax: */
c6dc6f63 3611 if (featurestr[0] == '+') {
2fae0d96
EH		 3612 plus_features = g_list_append(plus_features,
3613 g_strdup(featurestr + 1));
f6750e95 3614 continue;
c6dc6f63 3615 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3616 minus_features = g_list_append(minus_features,
3617 g_strdup(featurestr + 1));
f6750e95
EH		 3618 continue;
3619 }
3620
3621 eq = strchr(featurestr, '=');
3622 if (eq) {
3623 *eq++ = 0;
3624 val = eq;
c6dc6f63 3625 } else {
f6750e95 3626 val = "on";
a91987c2 3627 }
f6750e95
EH		 3628
3629 feat2prop(featurestr);
3630 name = featurestr;
3631
83a00f60 3632 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3633 warn_report("Ambiguous CPU model string. "
3634 "Don't mix both \"+%s\" and \"%s=%s\"",
3635 name, name, val);
83a00f60
EH		 3636 ambiguous = true;
3637 }
3638 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3639 warn_report("Ambiguous CPU model string. "
3640 "Don't mix both \"-%s\" and \"%s=%s\"",
3641 name, name, val);
83a00f60
EH		 3642 ambiguous = true;
3643 }
3644
f6750e95
EH		 3645 /* Special case: */
3646 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3647 int ret;
f46bfdbf 3648 uint64_t tsc_freq;
f6750e95 3649
f17fd4fd 3650 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3651 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3652 error_setg(errp, "bad numerical value %s", val);
3653 return;
3654 }
3655 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3656 val = num;
3657 name = "tsc-frequency";
c6dc6f63 3658 }
f6750e95 3659
62a48a2a
IM		 3660 prop = g_new0(typeof(*prop), 1);
3661 prop->driver = typename;
3662 prop->property = g_strdup(name);
3663 prop->value = g_strdup(val);
62a48a2a 3664 qdev_prop_register_global(prop);
f6750e95
EH		 3665 }
3666
83a00f60 3667 if (ambiguous) {
3dc6f869
AF		 3668 warn_report("Compatibility of ambiguous CPU model "
3669 "strings won't be kept on future QEMU versions");
83a00f60 3670 }
c6dc6f63
AP		 3671}
3672
b8d834a0 3673static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3674static int x86_cpu_filter_features(X86CPU *cpu);
3675
5a853fc5
EH		 3676/* Build a list with the name of all features on a feature word array */
3677static void x86_cpu_list_feature_names(FeatureWordArray features,
3678 strList **feat_names)
3679{
3680 FeatureWord w;
3681 strList **next = feat_names;
3682
3683 for (w = 0; w < FEATURE_WORDS; w++) {
3684 uint32_t filtered = features[w];
3685 int i;
3686 for (i = 0; i < 32; i++) {
3687 if (filtered & (1UL << i)) {
3688 strList *new = g_new0(strList, 1);
3689 new->value = g_strdup(x86_cpu_feature_name(w, i));
3690 *next = new;
3691 next = &new->next;
3692 }
3693 }
3694 }
3695}
3696
506174bf
EH		 3697static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
3698 const char *name, void *opaque,
3699 Error **errp)
3700{
3701 X86CPU *xc = X86_CPU(obj);
3702 strList *result = NULL;
3703
3704 x86_cpu_list_feature_names(xc->filtered_features, &result);
3705 visit_type_strList(v, "unavailable-features", &result, errp);
3706}
3707
b54c9377
EH		 3708/* Check for missing features that may prevent the CPU class from
3709 * running using the current machine and accelerator.
3710 */
3711static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3712 strList **missing_feats)
3713{
3714 X86CPU *xc;
b54c9377
EH		 3715 Error *err = NULL;
3716 strList **next = missing_feats;
3717
d6dcc558 3718 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3719 strList *new = g_new0(strList, 1);
3c254ab8 3720 new->value = g_strdup("kvm");
b54c9377
EH		 3721 *missing_feats = new;
3722 return;
3723 }
3724
3725 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3726
b8d834a0 3727 x86_cpu_expand_features(xc, &err);
b54c9377 3728 if (err) {
b8d834a0 3729 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3730 * but in case it does, just report the model as not
3731 * runnable at all using the "type" property.
3732 */
3733 strList *new = g_new0(strList, 1);
3734 new->value = g_strdup("type");
3735 *next = new;
3736 next = &new->next;
3737 }
3738
3739 x86_cpu_filter_features(xc);
3740
5a853fc5 3741 x86_cpu_list_feature_names(xc->filtered_features, next);
b54c9377
EH		 3742
3743 object_unref(OBJECT(xc));
3744}
3745
8c3329e5 3746/* Print all cpuid feature names in featureset
c6dc6f63 3747 */
0442428a 3748static void listflags(GList *features)
0856579c 3749{
cc643b1e
DB		 3750 size_t len = 0;
3751 GList *tmp;
3752
3753 for (tmp = features; tmp; tmp = tmp->next) {
3754 const char *name = tmp->data;
3755 if ((len + strlen(name) + 1) >= 75) {
0442428a 3756 qemu_printf("\n");
cc643b1e 3757 len = 0;
c6dc6f63 3758 }
0442428a 3759 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 3760 len += strlen(name) + 1;
8c3329e5 3761 }
0442428a 3762 qemu_printf("\n");
c6dc6f63
AP		 3763}
3764
f48c8837 3765/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3766static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3767{
3768 ObjectClass *class_a = (ObjectClass *)a;
3769 ObjectClass *class_b = (ObjectClass *)b;
3770 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3771 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3772 char *name_a, *name_b;
3773 int ret;
ee465a3e 3774
f48c8837 3775 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3776 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3777 } else {
c7dbff4b
DB		 3778 name_a = x86_cpu_class_get_model_name(cc_a);
3779 name_b = x86_cpu_class_get_model_name(cc_b);
3780 ret = strcmp(name_a, name_b);
3781 g_free(name_a);
3782 g_free(name_b);
ee465a3e 3783 }
c7dbff4b 3784 return ret;
ee465a3e
EH		 3785}
3786
3787static GSList *get_sorted_cpu_model_list(void)
3788{
3789 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3790 list = g_slist_sort(list, x86_cpu_list_compare);
3791 return list;
3792}
3793
3794static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3795{
3796 ObjectClass *oc = data;
3797 X86CPUClass *cc = X86_CPU_CLASS(oc);
ee465a3e
EH		 3798 char *name = x86_cpu_class_get_model_name(cc);
3799 const char *desc = cc->model_description;
0bacd8b3 3800 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3801 desc = cc->cpu_def->model_id;
3802 }
3803
0442428a 3804 qemu_printf("x86 %-20s %-48s\n", name, desc);
ee465a3e
EH		 3805 g_free(name);
3806}
3807
3808/* list available CPU models and flags */
0442428a 3809void x86_cpu_list(void)
c6dc6f63 3810{
cc643b1e 3811 int i, j;
ee465a3e 3812 GSList *list;
cc643b1e 3813 GList *names = NULL;
c6dc6f63 3814
0442428a 3815 qemu_printf("Available CPUs:\n");
ee465a3e 3816 list = get_sorted_cpu_model_list();
0442428a 3817 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 3818 g_slist_free(list);
21ad7789 3819
cc643b1e 3820 names = NULL;
3af60be2
JK		 3821 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3822 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3823 for (j = 0; j < 32; j++) {
3824 if (fw->feat_names[j]) {
3825 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3826 }
3827 }
3af60be2 3828 }
cc643b1e
DB		 3829
3830 names = g_list_sort(names, (GCompareFunc)strcmp);
3831
0442428a
MA		 3832 qemu_printf("\nRecognized CPUID flags:\n");
3833 listflags(names);
3834 qemu_printf("\n");
cc643b1e 3835 g_list_free(names);
c6dc6f63
AP		 3836}
3837
ee465a3e
EH		 3838static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3839{
3840 ObjectClass *oc = data;
3841 X86CPUClass *cc = X86_CPU_CLASS(oc);
3842 CpuDefinitionInfoList **cpu_list = user_data;
3843 CpuDefinitionInfoList *entry;
3844 CpuDefinitionInfo *info;
3845
3846 info = g_malloc0(sizeof(*info));
3847 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3848 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3849 info->has_unavailable_features = true;
8ed877b7 3850 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3851 info->migration_safe = cc->migration_safe;
3852 info->has_migration_safe = true;
5adbed30 3853 info->q_static = cc->static_model;
ee465a3e
EH		 3854
3855 entry = g_malloc0(sizeof(*entry));
3856 entry->value = info;
3857 entry->next = *cpu_list;
3858 *cpu_list = entry;
3859}
3860
25a9d6ca 3861CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 3862{
3863 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3864 GSList *list = get_sorted_cpu_model_list();
3865 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3866 g_slist_free(list);
e3966126
AL		 3867 return cpu_list;
3868}
3869
84f1b92f
EH		 3870static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3871 bool migratable_only)
27418adf
EH		 3872{
3873 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3874 uint32_t r = 0;
27418adf 3875
fefb41bf 3876 if (kvm_enabled()) {
07585923
RH		 3877 switch (wi->type) {
3878 case CPUID_FEATURE_WORD:
3879 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3880 wi->cpuid.ecx,
3881 wi->cpuid.reg);
3882 break;
3883 case MSR_FEATURE_WORD:
d86f9636
RH		 3884 r = kvm_arch_get_supported_msr_feature(kvm_state,
3885 wi->msr.index);
07585923
RH		 3886 break;
3887 }
d6dcc558 3888 } else if (hvf_enabled()) {
07585923
RH		 3889 if (wi->type != CPUID_FEATURE_WORD) {
3890 return 0;
3891 }
3892 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3893 wi->cpuid.ecx,
3894 wi->cpuid.reg);
fefb41bf 3895 } else if (tcg_enabled()) {
84f1b92f 3896 r = wi->tcg_features;
fefb41bf
EH		 3897 } else {
3898 return ~0;
3899 }
84f1b92f
EH		 3900 if (migratable_only) {
3901 r &= x86_cpu_get_migratable_flags(w);
3902 }
3903 return r;
27418adf
EH		 3904}
3905
8ca30e86
EH		 3906static void x86_cpu_report_filtered_features(X86CPU *cpu)
3907{
3908 FeatureWord w;
3909
3910 for (w = 0; w < FEATURE_WORDS; w++) {
3911 report_unavailable_features(w, cpu->filtered_features[w]);
3912 }
3913}
3914
5114e842
EH		 3915static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3916{
3917 PropValue *pv;
3918 for (pv = props; pv->prop; pv++) {
3919 if (!pv->value) {
3920 continue;
3921 }
3922 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3923 &error_abort);
3924 }
3925}
3926
f99fd7ca 3927/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3928 */
d940ee9b 3929static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3930{
61dcd775 3931 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3932 const char *vendor;
3933 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3934 FeatureWord w;
c6dc6f63 3935
f99fd7ca
EH		 3936 /*NOTE: any property set by this function should be returned by
3937 * x86_cpu_static_props(), so static expansion of
3938 * query-cpu-model-expansion is always complete.
3939 */
3940
c39c0edf 3941 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3942 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3943 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3944
2d64255b
AF		 3945 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3946 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3947 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3948 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3949 for (w = 0; w < FEATURE_WORDS; w++) {
3950 env->features[w] = def->features[w];
3951 }
82beb536 3952
a9f27ea9
EH		 3953 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3954 cpu->legacy_cache = !def->cache_info;
ab8f992e 3955
9576de75 3956 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3957 /* TODO: in-kernel irqchip for hvf */
82beb536 3958 if (kvm_enabled()) {
492a4c94
LT		 3959 if (!kvm_irqchip_in_kernel()) {
3960 x86_cpu_change_kvm_default("x2apic", "off");
3961 }
3962
5114e842 3963 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3964 } else if (tcg_enabled()) {
3965 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3966 }
5fcca9ff 3967
82beb536 3968 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3969
3970 /* sysenter isn't supported in compatibility mode on AMD,
3971 * syscall isn't supported in compatibility mode on Intel.
3972 * Normally we advertise the actual CPU vendor, but you can
3973 * override this using the 'vendor' property if you want to use
3974 * KVM's sysenter/syscall emulation in compatibility mode and
3975 * when doing cross vendor migration
3976 */
74f54bc4 3977 vendor = def->vendor;
d6dcc558 3978 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3979 uint32_t ebx = 0, ecx = 0, edx = 0;
3980 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3981 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3982 vendor = host_vendor;
3983 }
3984
3985 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3986
c6dc6f63
AP		 3987}
3988
96f75b59 3989#ifndef CONFIG_USER_ONLY
f99fd7ca
EH		 3990/* Return a QDict containing keys for all properties that can be included
3991 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3992 * must be included in the dictionary.
3993 */
3994static QDict *x86_cpu_static_props(void)
3995{
3996 FeatureWord w;
3997 int i;
3998 static const char *props[] = {
3999 "min-level",
4000 "min-xlevel",
4001 "family",
4002 "model",
4003 "stepping",
4004 "model-id",
4005 "vendor",
4006 "lmce",
4007 NULL,
4008 };
4009 static QDict *d;
4010
4011 if (d) {
4012 return d;
4013 }
4014
4015 d = qdict_new();
4016 for (i = 0; props[i]; i++) {
0f9afc2a 4017 qdict_put_null(d, props[i]);
f99fd7ca
EH		 4018 }
4019
4020 for (w = 0; w < FEATURE_WORDS; w++) {
4021 FeatureWordInfo *fi = &feature_word_info[w];
4022 int bit;
4023 for (bit = 0; bit < 32; bit++) {
4024 if (!fi->feat_names[bit]) {
4025 continue;
4026 }
0f9afc2a 4027 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 4028 }
4029 }
4030
4031 return d;
4032}
4033
4034/* Add an entry to @props dict, with the value for property. */
4035static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
4036{
4037 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
4038 &error_abort);
4039
4040 qdict_put_obj(props, prop, value);
4041}
4042
4043/* Convert CPU model data from X86CPU object to a property dictionary
4044 * that can recreate exactly the same CPU model.
4045 */
4046static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
4047{
4048 QDict *sprops = x86_cpu_static_props();
4049 const QDictEntry *e;
4050
4051 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
4052 const char *prop = qdict_entry_key(e);
4053 x86_cpu_expand_prop(cpu, props, prop);
4054 }
4055}
4056
b8097deb
EH		 4057/* Convert CPU model data from X86CPU object to a property dictionary
4058 * that can recreate exactly the same CPU model, including every
4059 * writeable QOM property.
4060 */
4061static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
4062{
4063 ObjectPropertyIterator iter;
4064 ObjectProperty *prop;
4065
4066 object_property_iter_init(&iter, OBJECT(cpu));
4067 while ((prop = object_property_iter_next(&iter))) {
4068 /* skip read-only or write-only properties */
4069 if (!prop->get || !prop->set) {
4070 continue;
4071 }
4072
4073 /* "hotplugged" is the only property that is configurable
4074 * on the command-line but will be set differently on CPUs
4075 * created using "-cpu ... -smp ..." and by CPUs created
4076 * on the fly by x86_cpu_from_model() for querying. Skip it.
4077 */
4078 if (!strcmp(prop->name, "hotplugged")) {
4079 continue;
4080 }
4081 x86_cpu_expand_prop(cpu, props, prop->name);
4082 }
4083}
4084
f99fd7ca
EH		 4085static void object_apply_props(Object *obj, QDict *props, Error **errp)
4086{
4087 const QDictEntry *prop;
4088 Error *err = NULL;
4089
4090 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4091 object_property_set_qobject(obj, qdict_entry_value(prop),
4092 qdict_entry_key(prop), &err);
4093 if (err) {
4094 break;
4095 }
4096 }
4097
4098 error_propagate(errp, err);
4099}
4100
4101/* Create X86CPU object according to model+props specification */
4102static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4103{
4104 X86CPU *xc = NULL;
4105 X86CPUClass *xcc;
4106 Error *err = NULL;
4107
4108 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4109 if (xcc == NULL) {
4110 error_setg(&err, "CPU model '%s' not found", model);
4111 goto out;
4112 }
4113
4114 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4115 if (props) {
4116 object_apply_props(OBJECT(xc), props, &err);
4117 if (err) {
4118 goto out;
4119 }
4120 }
4121
4122 x86_cpu_expand_features(xc, &err);
4123 if (err) {
4124 goto out;
4125 }
4126
4127out:
4128 if (err) {
4129 error_propagate(errp, err);
4130 object_unref(OBJECT(xc));
4131 xc = NULL;
4132 }
4133 return xc;
4134}
4135
4136CpuModelExpansionInfo *
96f75b59 4137qmp_query_cpu_model_expansion(CpuModelExpansionType type,
f99fd7ca
EH		 4138 CpuModelInfo *model,
4139 Error **errp)
4140{
4141 X86CPU *xc = NULL;
4142 Error *err = NULL;
4143 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4144 QDict *props = NULL;
4145 const char *base_name;
4146
4147 xc = x86_cpu_from_model(model->name,
4148 model->has_props ?
7dc847eb 4149 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4150 NULL, &err);
4151 if (err) {
4152 goto out;
4153 }
4154
b8097deb 4155 props = qdict_new();
e38bf612
EH		 4156 ret->model = g_new0(CpuModelInfo, 1);
4157 ret->model->props = QOBJECT(props);
4158 ret->model->has_props = true;
f99fd7ca
EH		 4159
4160 switch (type) {
4161 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4162 /* Static expansion will be based on "base" only */
4163 base_name = "base";
b8097deb 4164 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4165 break;
4166 case CPU_MODEL_EXPANSION_TYPE_FULL:
4167 /* As we don't return every single property, full expansion needs
4168 * to keep the original model name+props, and add extra
4169 * properties on top of that.
4170 */
4171 base_name = model->name;
b8097deb 4172 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4173 break;
4174 default:
df68a7f3 4175 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 4176 goto out;
4177 }
4178
f99fd7ca
EH		 4179 x86_cpu_to_dict(xc, props);
4180
f99fd7ca 4181 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4182
4183out:
4184 object_unref(OBJECT(xc));
4185 if (err) {
4186 error_propagate(errp, err);
4187 qapi_free_CpuModelExpansionInfo(ret);
4188 ret = NULL;
4189 }
4190 return ret;
4191}
96f75b59 4192#endif /* !CONFIG_USER_ONLY */
f99fd7ca 4193
00fcd100
AB		 4194static gchar *x86_gdb_arch_name(CPUState *cs)
4195{
4196#ifdef TARGET_X86_64
4197 return g_strdup("i386:x86-64");
4198#else
4199 return g_strdup("i386");
4200#endif
4201}
4202
d940ee9b
EH		 4203static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4204{
4205 X86CPUDefinition *cpudef = data;
4206 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4207
4208 xcc->cpu_def = cpudef;
bd72159d 4209 xcc->migration_safe = true;
d940ee9b
EH		 4210}
4211
4212static void x86_register_cpudef_type(X86CPUDefinition *def)
4213{
4214 char *typename = x86_cpu_type_name(def->name);
4215 TypeInfo ti = {
4216 .name = typename,
4217 .parent = TYPE_X86_CPU,
4218 .class_init = x86_cpu_cpudef_class_init,
4219 .class_data = def,
4220 };
4221
2a923a29
EH		 4222 /* AMD aliases are handled at runtime based on CPUID vendor, so
4223 * they shouldn't be set on the CPU model table.
4224 */
4225 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4226 /* catch mistakes instead of silently truncating model_id when too long */
4227 assert(def->model_id && strlen(def->model_id) <= 48);
4228
2a923a29 4229
d940ee9b
EH		 4230 type_register(&ti);
4231 g_free(typename);
4232}
4233
c6dc6f63 4234#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4235
0e26b7b8
BS		 4236void cpu_clear_apic_feature(CPUX86State *env)
4237{
0514ef2f 4238 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4239}
4240
c6dc6f63
AP		 4241#endif /* !CONFIG_USER_ONLY */
4242
c6dc6f63
AP		 4243void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4244 uint32_t *eax, uint32_t *ebx,
4245 uint32_t *ecx, uint32_t *edx)
4246{
6aa9e42f
RH		 4247 X86CPU *cpu = env_archcpu(env);
4248 CPUState *cs = env_cpu(env);
14c985cf 4249 uint32_t pkg_offset;
4ed3d478 4250 uint32_t limit;
1ce36bfe 4251 uint32_t signature[3];
a60f24b5 4252
4ed3d478
DB		 4253 /* Calculate & apply limits for different index ranges */
4254 if (index >= 0xC0000000) {
4255 limit = env->cpuid_xlevel2;
4256 } else if (index >= 0x80000000) {
4257 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4258 } else if (index >= 0x40000000) {
4259 limit = 0x40000001;
c6dc6f63 4260 } else {
4ed3d478
DB		 4261 limit = env->cpuid_level;
4262 }
4263
4264 if (index > limit) {
4265 /* Intel documentation states that invalid EAX input will
4266 * return the same information as EAX=cpuid_level
4267 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4268 */
4269 index = env->cpuid_level;
c6dc6f63
AP		 4270 }
4271
4272 switch(index) {
4273 case 0:
4274 *eax = env->cpuid_level;
5eb2f7a4
EH		 4275 *ebx = env->cpuid_vendor1;
4276 *edx = env->cpuid_vendor2;
4277 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4278 break;
4279 case 1:
4280 *eax = env->cpuid_version;
7e72a45c
EH		 4281 *ebx = (cpu->apic_id << 24) |
4282 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4283 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4284 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4285 *ecx |= CPUID_EXT_OSXSAVE;
4286 }
0514ef2f 4287 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4288 if (cs->nr_cores * cs->nr_threads > 1) {
4289 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4290 *edx |= CPUID_HT;
c6dc6f63
AP		 4291 }
4292 break;
4293 case 2:
4294 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4295 if (cpu->cache_info_passthrough) {
4296 host_cpuid(index, 0, eax, ebx, ecx, edx);
4297 break;
4298 }
5e891bf8 4299 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4300 *ebx = 0;
14c985cf
LM		 4301 if (!cpu->enable_l3_cache) {
4302 *ecx = 0;
4303 } else {
a9f27ea9 4304 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4305 }
a9f27ea9
EH		 4306 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4307 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4308 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4309 break;
4310 case 4:
4311 /* cache info: needed for Core compatibility */
787aaf57
BC		 4312 if (cpu->cache_info_passthrough) {
4313 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4314 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4315 *eax &= ~0xFC000000;
7e3482f8
EH		 4316 if ((*eax & 31) && cs->nr_cores > 1) {
4317 *eax |= (cs->nr_cores - 1) << 26;
4318 }
c6dc6f63 4319 } else {
2f7a21c4 4320 *eax = 0;
76c2975a 4321 switch (count) {
c6dc6f63 4322 case 0: /* L1 dcache info */
a9f27ea9
EH		 4323 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4324 1, cs->nr_cores,
7e3482f8 4325 eax, ebx, ecx, edx);
c6dc6f63
AP		 4326 break;
4327 case 1: /* L1 icache info */
a9f27ea9
EH		 4328 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4329 1, cs->nr_cores,
7e3482f8 4330 eax, ebx, ecx, edx);
c6dc6f63
AP		 4331 break;
4332 case 2: /* L2 cache info */
a9f27ea9
EH		 4333 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4334 cs->nr_threads, cs->nr_cores,
7e3482f8 4335 eax, ebx, ecx, edx);
c6dc6f63 4336 break;
14c985cf 4337 case 3: /* L3 cache info */
7e3482f8
EH		 4338 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4339 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4340 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4341 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4342 eax, ebx, ecx, edx);
14c985cf
LM		 4343 break;
4344 }
7e3482f8 4345 /* fall through */
c6dc6f63 4346 default: /* end of info */
7e3482f8 4347 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4348 break;
76c2975a
PB		 4349 }
4350 }
c6dc6f63
AP		 4351 break;
4352 case 5:
2266d443
MT		 4353 /* MONITOR/MWAIT Leaf */
4354 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4355 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4356 *ecx = cpu->mwait.ecx; /* flags */
4357 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4358 break;
4359 case 6:
4360 /* Thermal and Power Leaf */
28b8e4d0 4361 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4362 *ebx = 0;
4363 *ecx = 0;
4364 *edx = 0;
4365 break;
f7911686 4366 case 7:
13526728
EH		 4367 /* Structured Extended Feature Flags Enumeration Leaf */
4368 if (count == 0) {
4369 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4370 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4371 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4372 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4373 *ecx |= CPUID_7_0_ECX_OSPKE;
4374 }
95ea69fb 4375 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4376 } else {
4377 *eax = 0;
4378 *ebx = 0;
4379 *ecx = 0;
4380 *edx = 0;
4381 }
4382 break;
c6dc6f63
AP		 4383 case 9:
4384 /* Direct Cache Access Information Leaf */
4385 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4386 *ebx = 0;
4387 *ecx = 0;
4388 *edx = 0;
4389 break;
4390 case 0xA:
4391 /* Architectural Performance Monitoring Leaf */
9337e3b6 4392 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4393 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4394
4395 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4396 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4397 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4398 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4399 } else if (hvf_enabled() && cpu->enable_pmu) {
4400 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4401 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4402 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4403 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4404 } else {
4405 *eax = 0;
4406 *ebx = 0;
4407 *ecx = 0;
4408 *edx = 0;
4409 }
c6dc6f63 4410 break;
5232d00a
RK		 4411 case 0xB:
4412 /* Extended Topology Enumeration Leaf */
4413 if (!cpu->enable_cpuid_0xb) {
4414 *eax = *ebx = *ecx = *edx = 0;
4415 break;
4416 }
4417
4418 *ecx = count & 0xff;
4419 *edx = cpu->apic_id;
4420
4421 switch (count) {
4422 case 0:
eab60fb9
MAL		 4423 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4424 *ebx = cs->nr_threads;
5232d00a
RK		 4425 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4426 break;
4427 case 1:
eab60fb9
MAL		 4428 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4429 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4430 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4431 break;
4432 default:
4433 *eax = 0;
4434 *ebx = 0;
4435 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4436 }
4437
4438 assert(!(*eax & ~0x1f));
4439 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4440 break;
2560f19f 4441 case 0xD: {
51e49430 4442 /* Processor Extended State */
2560f19f
PB		 4443 *eax = 0;
4444 *ebx = 0;
4445 *ecx = 0;
4446 *edx = 0;
19dc85db 4447 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4448 break;
4449 }
4928cd6d 4450
2560f19f 4451 if (count == 0) {
96193c22
EH		 4452 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4453 *eax = env->features[FEAT_XSAVE_COMP_LO];
4454 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4455 *ebx = xsave_area_size(env->xcr0);
2560f19f 4456 } else if (count == 1) {
0bb0b2d2 4457 *eax = env->features[FEAT_XSAVE];
f4f1110e 4458 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4459 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4460 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4461 *eax = esa->size;
4462 *ebx = esa->offset;
2560f19f 4463 }
51e49430
SY		 4464 }
4465 break;
2560f19f 4466 }
e37a5c7f
CP		 4467 case 0x14: {
4468 /* Intel Processor Trace Enumeration */
4469 *eax = 0;
4470 *ebx = 0;
4471 *ecx = 0;
4472 *edx = 0;
4473 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4474 !kvm_enabled()) {
4475 break;
4476 }
4477
4478 if (count == 0) {
4479 *eax = INTEL_PT_MAX_SUBLEAF;
4480 *ebx = INTEL_PT_MINIMAL_EBX;
4481 *ecx = INTEL_PT_MINIMAL_ECX;
4482 } else if (count == 1) {
4483 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4484 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4485 }
4486 break;
4487 }
1ce36bfe
DB		 4488 case 0x40000000:
4489 /*
4490 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4491 * set here, but we restrict to TCG none the less.
4492 */
4493 if (tcg_enabled() && cpu->expose_tcg) {
4494 memcpy(signature, "TCGTCGTCGTCG", 12);
4495 *eax = 0x40000001;
4496 *ebx = signature[0];
4497 *ecx = signature[1];
4498 *edx = signature[2];
4499 } else {
4500 *eax = 0;
4501 *ebx = 0;
4502 *ecx = 0;
4503 *edx = 0;
4504 }
4505 break;
4506 case 0x40000001:
4507 *eax = 0;
4508 *ebx = 0;
4509 *ecx = 0;
4510 *edx = 0;
4511 break;
c6dc6f63
AP		 4512 case 0x80000000:
4513 *eax = env->cpuid_xlevel;
4514 *ebx = env->cpuid_vendor1;
4515 *edx = env->cpuid_vendor2;
4516 *ecx = env->cpuid_vendor3;
4517 break;
4518 case 0x80000001:
4519 *eax = env->cpuid_version;
4520 *ebx = 0;
0514ef2f
EH		 4521 *ecx = env->features[FEAT_8000_0001_ECX];
4522 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4523
4524 /* The Linux kernel checks for the CMPLegacy bit and
4525 * discards multiple thread information if it is set.
cb8d4c8f 4526 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4527 */
ce3960eb 4528 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4529 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4530 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4531 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4532 *ecx |= 1 << 1; /* CmpLegacy bit */
4533 }
4534 }
c6dc6f63
AP		 4535 break;
4536 case 0x80000002:
4537 case 0x80000003:
4538 case 0x80000004:
4539 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4540 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4541 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4542 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4543 break;
4544 case 0x80000005:
4545 /* cache info (L1 cache) */
787aaf57
BC		 4546 if (cpu->cache_info_passthrough) {
4547 host_cpuid(index, 0, eax, ebx, ecx, edx);
4548 break;
4549 }
5e891bf8
EH		 4550 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4551 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4552 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4553 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4554 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4555 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4556 break;
4557 case 0x80000006:
4558 /* cache info (L2 cache) */
787aaf57
BC		 4559 if (cpu->cache_info_passthrough) {
4560 host_cpuid(index, 0, eax, ebx, ecx, edx);
4561 break;
4562 }
5e891bf8
EH		 4563 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4564 (L2_DTLB_2M_ENTRIES << 16) | \
4565 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4566 (L2_ITLB_2M_ENTRIES);
4567 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4568 (L2_DTLB_4K_ENTRIES << 16) | \
4569 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4570 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4571 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4572 cpu->enable_l3_cache ?
4573 env->cache_info_amd.l3_cache : NULL,
4574 ecx, edx);
c6dc6f63 4575 break;
303752a9
MT		 4576 case 0x80000007:
4577 *eax = 0;
4578 *ebx = 0;
4579 *ecx = 0;
4580 *edx = env->features[FEAT_8000_0007_EDX];
4581 break;
c6dc6f63
AP		 4582 case 0x80000008:
4583 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4584 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4585 /* 64 bit processor */
4586 *eax = cpu->phys_bits; /* configurable physical bits */
4587 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4588 *eax |= 0x00003900; /* 57 bits virtual */
4589 } else {
4590 *eax |= 0x00003000; /* 48 bits virtual */
4591 }
c6dc6f63 4592 } else {
af45907a 4593 *eax = cpu->phys_bits;
c6dc6f63 4594 }
1b3420e1 4595 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4596 *ecx = 0;
4597 *edx = 0;
ce3960eb
AF		 4598 if (cs->nr_cores * cs->nr_threads > 1) {
4599 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4600 }
4601 break;
4602 case 0x8000000A:
0514ef2f 4603 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4604 *eax = 0x00000001; /* SVM Revision */
4605 *ebx = 0x00000010; /* nr of ASIDs */
4606 *ecx = 0;
0514ef2f 4607 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4608 } else {
4609 *eax = 0;
4610 *ebx = 0;
4611 *ecx = 0;
4612 *edx = 0;
4613 }
c6dc6f63 4614 break;
8f4202fb
BM		 4615 case 0x8000001D:
4616 *eax = 0;
a4e0b436
SL		 4617 if (cpu->cache_info_passthrough) {
4618 host_cpuid(index, count, eax, ebx, ecx, edx);
4619 break;
4620 }
8f4202fb
BM		 4621 switch (count) {
4622 case 0: /* L1 dcache info */
4623 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4624 eax, ebx, ecx, edx);
4625 break;
4626 case 1: /* L1 icache info */
4627 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4628 eax, ebx, ecx, edx);
4629 break;
4630 case 2: /* L2 cache info */
4631 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4632 eax, ebx, ecx, edx);
4633 break;
4634 case 3: /* L3 cache info */
4635 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4636 eax, ebx, ecx, edx);
4637 break;
4638 default: /* end of info */
4639 *eax = *ebx = *ecx = *edx = 0;
4640 break;
4641 }
4642 break;
ed78467a
BM		 4643 case 0x8000001E:
4644 assert(cpu->core_id <= 255);
4645 encode_topo_cpuid8000001e(cs, cpu,
4646 eax, ebx, ecx, edx);
4647 break;
b3baa152
BW		 4648 case 0xC0000000:
4649 *eax = env->cpuid_xlevel2;
4650 *ebx = 0;
4651 *ecx = 0;
4652 *edx = 0;
4653 break;
4654 case 0xC0000001:
4655 /* Support for VIA CPU's CPUID instruction */
4656 *eax = env->cpuid_version;
4657 *ebx = 0;
4658 *ecx = 0;
0514ef2f 4659 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4660 break;
4661 case 0xC0000002:
4662 case 0xC0000003:
4663 case 0xC0000004:
4664 /* Reserved for the future, and now filled with zero */
4665 *eax = 0;
4666 *ebx = 0;
4667 *ecx = 0;
4668 *edx = 0;
4669 break;
6cb8f2a6
BS		 4670 case 0x8000001F:
4671 *eax = sev_enabled() ? 0x2 : 0;
4672 *ebx = sev_get_cbit_position();
4673 *ebx |= sev_get_reduced_phys_bits() << 6;
4674 *ecx = 0;
4675 *edx = 0;
4676 break;
c6dc6f63
AP		 4677 default:
4678 /* reserved values: zero */
4679 *eax = 0;
4680 *ebx = 0;
4681 *ecx = 0;
4682 *edx = 0;
4683 break;
4684 }
4685}
5fd2087a
AF		 4686
4687/* CPUClass::reset() */
4688static void x86_cpu_reset(CPUState *s)
4689{
4690 X86CPU *cpu = X86_CPU(s);
4691 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4692 CPUX86State *env = &cpu->env;
a114d25d
RH		 4693 target_ulong cr4;
4694 uint64_t xcr0;
c1958aea
AF		 4695 int i;
4696
5fd2087a
AF		 4697 xcc->parent_reset(s);
4698
5e992a8e 4699 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4700
c1958aea
AF		 4701 env->old_exception = -1;
4702
4703 /* init to reset state */
4704
c1958aea
AF		 4705 env->hflags2 |= HF2_GIF_MASK;
4706
4707 cpu_x86_update_cr0(env, 0x60000010);
4708 env->a20_mask = ~0x0;
4709 env->smbase = 0x30000;
e13713db 4710 env->msr_smi_count = 0;
c1958aea
AF		 4711
4712 env->idt.limit = 0xffff;
4713 env->gdt.limit = 0xffff;
4714 env->ldt.limit = 0xffff;
4715 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4716 env->tr.limit = 0xffff;
4717 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4718
4719 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4720 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4721 DESC_R_MASK | DESC_A_MASK);
4722 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4723 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4724 DESC_A_MASK);
4725 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4726 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4727 DESC_A_MASK);
4728 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4729 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4730 DESC_A_MASK);
4731 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4732 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4733 DESC_A_MASK);
4734 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4735 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4736 DESC_A_MASK);
4737
4738 env->eip = 0xfff0;
4739 env->regs[R_EDX] = env->cpuid_version;
4740
4741 env->eflags = 0x2;
4742
4743 /* FPU init */
4744 for (i = 0; i < 8; i++) {
4745 env->fptags[i] = 1;
4746 }
5bde1407 4747 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4748
4749 env->mxcsr = 0x1f80;
a114d25d
RH		 4750 /* All units are in INIT state. */
4751 env->xstate_bv = 0;
c1958aea
AF		 4752
4753 env->pat = 0x0007040600070406ULL;
4754 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 4755 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
4756 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
4757 }
c1958aea
AF		 4758
4759 memset(env->dr, 0, sizeof(env->dr));
4760 env->dr[6] = DR6_FIXED_1;
4761 env->dr[7] = DR7_FIXED_1;
b3310ab3 4762 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4763 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4764
a114d25d 4765 cr4 = 0;
cfc3b074 4766 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4767
4768#ifdef CONFIG_USER_ONLY
4769 /* Enable all the features for user-mode. */
4770 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4771 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4772 }
0f70ed47
PB		 4773 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4774 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4775 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4776 xcr0 |= 1ull << i;
4777 }
a114d25d 4778 }
0f70ed47 4779
a114d25d
RH		 4780 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4781 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4782 }
07929f2a
RH		 4783 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4784 cr4 |= CR4_FSGSBASE_MASK;
4785 }
a114d25d
RH		 4786#endif
4787
4788 env->xcr0 = xcr0;
4789 cpu_x86_update_cr4(env, cr4);
0522604b 4790
9db2efd9
AW		 4791 /*
4792 * SDM 11.11.5 requires:
4793 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4794 * - IA32_MTRR_PHYSMASKn.V = 0
4795 * All other bits are undefined. For simplification, zero it all.
4796 */
4797 env->mtrr_deftype = 0;
4798 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4799 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4800
b7394c83
SAGDR		 4801 env->interrupt_injected = -1;
4802 env->exception_injected = -1;
4803 env->nmi_injected = false;
dd673288
IM		 4804#if !defined(CONFIG_USER_ONLY)
4805 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4806 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4807
259186a7 4808 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4809
4810 if (kvm_enabled()) {
4811 kvm_arch_reset_vcpu(cpu);
4812 }
d6dcc558
SAGDR		 4813 else if (hvf_enabled()) {
4814 hvf_reset_vcpu(s);
4815 }
dd673288 4816#endif
5fd2087a
AF		 4817}
4818
dd673288
IM		 4819#ifndef CONFIG_USER_ONLY
4820bool cpu_is_bsp(X86CPU *cpu)
4821{
02e51483 4822 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4823}
65dee380
IM		 4824
4825/* TODO: remove me, when reset over QOM tree is implemented */
4826static void x86_cpu_machine_reset_cb(void *opaque)
4827{
4828 X86CPU *cpu = opaque;
4829 cpu_reset(CPU(cpu));
4830}
dd673288
IM		 4831#endif
4832
de024815
AF		 4833static void mce_init(X86CPU *cpu)
4834{
4835 CPUX86State *cenv = &cpu->env;
4836 unsigned int bank;
4837
4838 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4839 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4840 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4841 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4842 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4843 cenv->mcg_ctl = ~(uint64_t)0;
4844 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4845 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4846 }
4847 }
4848}
4849
bdeec802 4850#ifndef CONFIG_USER_ONLY
2f114315 4851APICCommonClass *apic_get_class(void)
bdeec802 4852{
bdeec802
IM		 4853 const char *apic_type = "apic";
4854
d6dcc558 4855 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4856 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4857 apic_type = "kvm-apic";
4858 } else if (xen_enabled()) {
4859 apic_type = "xen-apic";
4860 }
4861
2f114315
RK		 4862 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4863}
4864
4865static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4866{
4867 APICCommonState *apic;
4868 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4869
4870 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4871
6816b1b3
IM		 4872 object_property_add_child(OBJECT(cpu), "lapic",
4873 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4874 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4875
33d7a288 4876 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4877 /* TODO: convert to link<> */
02e51483 4878 apic = APIC_COMMON(cpu->apic_state);
60671e58 4879 apic->cpu = cpu;
8d42d2d3 4880 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4881}
4882
4883static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4884{
8d42d2d3
CF		 4885 APICCommonState *apic;
4886 static bool apic_mmio_map_once;
4887
02e51483 4888 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4889 return;
4890 }
6e8e2651
MA		 4891 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4892 errp);
8d42d2d3
CF		 4893
4894 /* Map APIC MMIO area */
4895 apic = APIC_COMMON(cpu->apic_state);
4896 if (!apic_mmio_map_once) {
4897 memory_region_add_subregion_overlap(get_system_memory(),
4898 apic->apicbase &
4899 MSR_IA32_APICBASE_BASE,
4900 &apic->io_memory,
4901 0x1000);
4902 apic_mmio_map_once = true;
4903 }
bdeec802 4904}
f809c605
PB		 4905
4906static void x86_cpu_machine_done(Notifier *n, void *unused)
4907{
4908 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4909 MemoryRegion *smram =
4910 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4911
4912 if (smram) {
4913 cpu->smram = g_new(MemoryRegion, 1);
4914 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4915 smram, 0, 1ull << 32);
f8c45c65 4916 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4917 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4918 }
4919}
d3c64d6a
IM		 4920#else
4921static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4922{
4923}
bdeec802
IM		 4924#endif
4925
11f6fee5
DDAG		 4926/* Note: Only safe for use on x86(-64) hosts */
4927static uint32_t x86_host_phys_bits(void)
4928{
4929 uint32_t eax;
4930 uint32_t host_phys_bits;
4931
4932 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4933 if (eax >= 0x80000008) {
4934 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4935 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4936 * at 23:16 that can specify a maximum physical address bits for
4937 * the guest that can override this value; but I've not seen
4938 * anything with that set.
4939 */
4940 host_phys_bits = eax & 0xff;
4941 } else {
4942 /* It's an odd 64 bit machine that doesn't have the leaf for
4943 * physical address bits; fall back to 36 that's most older
4944 * Intel.
4945 */
4946 host_phys_bits = 36;
4947 }
4948
4949 return host_phys_bits;
4950}
e48638fd 4951
c39c0edf
EH		 4952static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4953{
4954 if (*min < value) {
4955 *min = value;
4956 }
4957}
4958
4959/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4960static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4961{
4962 CPUX86State *env = &cpu->env;
4963 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4964 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4965 uint32_t region = eax & 0xF0000000;
4966
07585923 4967 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4968 if (!env->features[w]) {
4969 return;
4970 }
4971
4972 switch (region) {
4973 case 0x00000000:
4974 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4975 break;
4976 case 0x80000000:
4977 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4978 break;
4979 case 0xC0000000:
4980 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4981 break;
4982 }
4983}
4984
2ca8a8be
EH		 4985/* Calculate XSAVE components based on the configured CPU feature flags */
4986static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4987{
4988 CPUX86State *env = &cpu->env;
4989 int i;
96193c22 4990 uint64_t mask;
2ca8a8be
EH		 4991
4992 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4993 return;
4994 }
4995
e3c9022b
EH		 4996 mask = 0;
4997 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4998 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4999 if (env->features[esa->feature] & esa->bits) {
96193c22 5000 mask |= (1ULL << i);
2ca8a8be
EH		 5001 }
5002 }
5003
96193c22
EH		 5004 env->features[FEAT_XSAVE_COMP_LO] = mask;
5005 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 5006}
5007
b8d834a0
EH		 5008/***** Steps involved on loading and filtering CPUID data
5009 *
5010 * When initializing and realizing a CPU object, the steps
5011 * involved in setting up CPUID data are:
5012 *
5013 * 1) Loading CPU model definition (X86CPUDefinition). This is
5014 * implemented by x86_cpu_load_def() and should be completely
5015 * transparent, as it is done automatically by instance_init.
5016 * No code should need to look at X86CPUDefinition structs
5017 * outside instance_init.
5018 *
5019 * 2) CPU expansion. This is done by realize before CPUID
5020 * filtering, and will make sure host/accelerator data is
5021 * loaded for CPU models that depend on host capabilities
5022 * (e.g. "host"). Done by x86_cpu_expand_features().
5023 *
5024 * 3) CPUID filtering. This initializes extra data related to
5025 * CPUID, and checks if the host supports all capabilities
5026 * required by the CPU. Runnability of a CPU model is
5027 * determined at this step. Done by x86_cpu_filter_features().
5028 *
5029 * Some operations don't require all steps to be performed.
5030 * More precisely:
5031 *
5032 * - CPU instance creation (instance_init) will run only CPU
5033 * model loading. CPU expansion can't run at instance_init-time
5034 * because host/accelerator data may be not available yet.
5035 * - CPU realization will perform both CPU model expansion and CPUID
5036 * filtering, and return an error in case one of them fails.
5037 * - query-cpu-definitions needs to run all 3 steps. It needs
5038 * to run CPUID filtering, as the 'unavailable-features'
5039 * field is set based on the filtering results.
5040 * - The query-cpu-model-expansion QMP command only needs to run
5041 * CPU model loading and CPU expansion. It should not filter
5042 * any CPUID data based on host capabilities.
5043 */
5044
5045/* Expand CPU configuration data, based on configured features
5046 * and host/accelerator capabilities when appropriate.
5047 */
5048static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 5049{
b34d12d1 5050 CPUX86State *env = &cpu->env;
dc15c051 5051 FeatureWord w;
2fae0d96 5052 GList *l;
41f3d4d6 5053 Error *local_err = NULL;
9886e834 5054
d4a606b3
EH		 5055 /*TODO: Now cpu->max_features doesn't overwrite features
5056 * set using QOM properties, and we can convert
dc15c051
IM		 5057 * plus_features & minus_features to global properties
5058 * inside x86_cpu_parse_featurestr() too.
5059 */
44bd8e53 5060 if (cpu->max_features) {
dc15c051 5061 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 5062 /* Override only features that weren't set explicitly
5063 * by the user.
5064 */
5065 env->features[w] |=
5066 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 5067 ~env->user_features[w] & \
5068 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 5069 }
5070 }
5071
2fae0d96
EH		 5072 for (l = plus_features; l; l = l->next) {
5073 const char *prop = l->data;
5074 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5075 if (local_err) {
5076 goto out;
5077 }
5078 }
5079
5080 for (l = minus_features; l; l = l->next) {
5081 const char *prop = l->data;
5082 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5083 if (local_err) {
5084 goto out;
5085 }
dc15c051
IM		 5086 }
5087
aec661de
EH		 5088 if (!kvm_enabled() || !cpu->expose_kvm) {
5089 env->features[FEAT_KVM] = 0;
5090 }
5091
2ca8a8be 5092 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5093
5094 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5095 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5096 if (cpu->full_cpuid_auto_level) {
5097 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5098 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5099 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5100 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5101 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5102 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5103 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5104 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5105 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5106 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5107 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 5108
5109 /* Intel Processor Trace requires CPUID[0x14] */
5110 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5111 kvm_enabled() && cpu->intel_pt_auto_level) {
5112 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5113 }
5114
0c3d7c00
EH		 5115 /* SVM requires CPUID[0x8000000A] */
5116 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5117 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5118 }
6cb8f2a6
BS		 5119
5120 /* SEV requires CPUID[0x8000001F] */
5121 if (sev_enabled()) {
5122 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5123 }
c39c0edf
EH		 5124 }
5125
5126 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5127 if (env->cpuid_level == UINT32_MAX) {
5128 env->cpuid_level = env->cpuid_min_level;
5129 }
5130 if (env->cpuid_xlevel == UINT32_MAX) {
5131 env->cpuid_xlevel = env->cpuid_min_xlevel;
5132 }
5133 if (env->cpuid_xlevel2 == UINT32_MAX) {
5134 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5135 }
7a059953 5136
41f3d4d6
EH		 5137out:
5138 if (local_err != NULL) {
5139 error_propagate(errp, local_err);
5140 }
5141}
5142
b8d834a0
EH		 5143/*
5144 * Finishes initialization of CPUID data, filters CPU feature
5145 * words based on host availability of each feature.
5146 *
5147 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5148 */
5149static int x86_cpu_filter_features(X86CPU *cpu)
5150{
5151 CPUX86State *env = &cpu->env;
5152 FeatureWord w;
5153 int rv = 0;
5154
5155 for (w = 0; w < FEATURE_WORDS; w++) {
5156 uint32_t host_feat =
5157 x86_cpu_get_supported_feature_word(w, false);
5158 uint32_t requested_features = env->features[w];
5159 env->features[w] &= host_feat;
5160 cpu->filtered_features[w] = requested_features & ~env->features[w];
5161 if (cpu->filtered_features[w]) {
5162 rv = 1;
5163 }
5164 }
5165
e37a5c7f
CP		 5166 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5167 kvm_enabled()) {
5168 KVMState *s = CPU(cpu)->kvm_state;
5169 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5170 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5171 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5172 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5173 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5174
5175 if (!eax_0 ||
5176 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5177 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5178 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5179 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5180 INTEL_PT_ADDR_RANGES_NUM) ||
5181 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5182 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5183 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5184 /*
5185 * Processor Trace capabilities aren't configurable, so if the
5186 * host can't emulate the capabilities we report on
5187 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5188 */
5189 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5190 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5191 rv = 1;
5192 }
5193 }
5194
b8d834a0
EH		 5195 return rv;
5196}
5197
41f3d4d6
EH		 5198#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5199 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5200 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5201#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5202 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5203 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5204static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5205{
5206 CPUState *cs = CPU(dev);
5207 X86CPU *cpu = X86_CPU(dev);
5208 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5209 CPUX86State *env = &cpu->env;
5210 Error *local_err = NULL;
5211 static bool ht_warned;
5212
2266d443
MT		 5213 if (xcc->host_cpuid_required) {
5214 if (!accel_uses_host_cpuid()) {
5215 char *name = x86_cpu_class_get_model_name(xcc);
5216 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5217 g_free(name);
5218 goto out;
5219 }
5220
5221 if (enable_cpu_pm) {
5222 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5223 &cpu->mwait.ecx, &cpu->mwait.edx);
5224 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5225 }
41f3d4d6
EH		 5226 }
5227
2266d443
MT		 5228 /* mwait extended info: needed for Core compatibility */
5229 /* We always wake on interrupt even if host does not have the capability */
5230 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5231
41f3d4d6
EH		 5232 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5233 error_setg(errp, "apic-id property was not initialized properly");
5234 return;
5235 }
5236
b8d834a0 5237 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5238 if (local_err) {
5239 goto out;
5240 }
5241
8ca30e86
EH		 5242 if (x86_cpu_filter_features(cpu) &&
5243 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5244 x86_cpu_report_filtered_features(cpu);
5245 if (cpu->enforce_cpuid) {
5246 error_setg(&local_err,
d6dcc558 5247 accel_uses_host_cpuid() ?
8ca30e86
EH		 5248 "Host doesn't support requested features" :
5249 "TCG doesn't support requested features");
5250 goto out;
5251 }
9997cf7b
EH		 5252 }
5253
9b15cd9e
IM		 5254 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5255 * CPUID[1].EDX.
5256 */
e48638fd 5257 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5258 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5259 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5260 & CPUID_EXT2_AMD_ALIASES);
5261 }
5262
11f6fee5
DDAG		 5263 /* For 64bit systems think about the number of physical bits to present.
5264 * ideally this should be the same as the host; anything other than matching
5265 * the host can cause incorrect guest behaviour.
5266 * QEMU used to pick the magic value of 40 bits that corresponds to
5267 * consumer AMD devices but nothing else.
5268 */
af45907a 5269 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5270 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5271 uint32_t host_phys_bits = x86_host_phys_bits();
5272 static bool warned;
5273
5274 if (cpu->host_phys_bits) {
5275 /* The user asked for us to use the host physical bits */
5276 cpu->phys_bits = host_phys_bits;
258fe08b
EH		 5277 if (cpu->host_phys_bits_limit &&
5278 cpu->phys_bits > cpu->host_phys_bits_limit) {
5279 cpu->phys_bits = cpu->host_phys_bits_limit;
5280 }
11f6fee5
DDAG		 5281 }
5282
5283 /* Print a warning if the user set it to a value that's not the
5284 * host value.
5285 */
5286 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5287 !warned) {
3dc6f869
AF		 5288 warn_report("Host physical bits (%u)"
5289 " does not match phys-bits property (%u)",
5290 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5291 warned = true;
5292 }
5293
5294 if (cpu->phys_bits &&
5295 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5296 cpu->phys_bits < 32)) {
af45907a
DDAG		 5297 error_setg(errp, "phys-bits should be between 32 and %u "
5298 " (but is %u)",
5299 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5300 return;
5301 }
5302 } else {
11f6fee5 5303 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5304 error_setg(errp, "TCG only supports phys-bits=%u",
5305 TCG_PHYS_ADDR_BITS);
5306 return;
5307 }
5308 }
11f6fee5
DDAG		 5309 /* 0 means it was not explicitly set by the user (or by machine
5310 * compat_props or by the host code above). In this case, the default
5311 * is the value used by TCG (40).
5312 */
5313 if (cpu->phys_bits == 0) {
5314 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5315 }
af45907a
DDAG		 5316 } else {
5317 /* For 32 bit systems don't use the user set value, but keep
5318 * phys_bits consistent with what we tell the guest.
5319 */
5320 if (cpu->phys_bits != 0) {
5321 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5322 return;
5323 }
fefb41bf 5324
af45907a
DDAG		 5325 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5326 cpu->phys_bits = 36;
5327 } else {
5328 cpu->phys_bits = 32;
5329 }
5330 }
a9f27ea9
EH		 5331
5332 /* Cache information initialization */
5333 if (!cpu->legacy_cache) {
5334 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5335 char *name = x86_cpu_class_get_model_name(xcc);
5336 error_setg(errp,
5337 "CPU model '%s' doesn't support legacy-cache=off", name);
5338 g_free(name);
5339 return;
5340 }
5341 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5342 *xcc->cpu_def->cache_info;
5343 } else {
5344 /* Build legacy cache information */
5345 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5346 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5347 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5348 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5349
5350 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5351 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5352 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5353 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5354
5355 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5356 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5357 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5358 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5359 }
5360
5361
ce5b1bbf
LV		 5362 cpu_exec_realizefn(cs, &local_err);
5363 if (local_err != NULL) {
5364 error_propagate(errp, local_err);
5365 return;
5366 }
42ecabaa 5367
65dee380
IM		 5368#ifndef CONFIG_USER_ONLY
5369 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5370
0514ef2f 5371 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5372 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5373 if (local_err != NULL) {
4dc1f449 5374 goto out;
bdeec802
IM		 5375 }
5376 }
65dee380
IM		 5377#endif
5378
7a059953 5379 mce_init(cpu);
2001d0cd
PB		 5380
5381#ifndef CONFIG_USER_ONLY
5382 if (tcg_enabled()) {
f809c605 5383 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5384 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5385
5386 /* Outer container... */
5387 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5388 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5389
5390 /* ... with two regions inside: normal system memory with low
5391 * priority, and...
5392 */
5393 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5394 get_system_memory(), 0, ~0ull);
5395 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5396 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5397
5398 cs->num_ases = 2;
80ceb07a
PX		 5399 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5400 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5401
5402 /* ... SMRAM with higher priority, linked from /machine/smram. */
5403 cpu->machine_done.notify = x86_cpu_machine_done;
5404 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5405 }
5406#endif
5407
14a10fc3 5408 qemu_init_vcpu(cs);
d3c64d6a 5409
6b2942f9
BM		 5410 /*
5411 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5412 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5413 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5414 * users a warning.
5415 *
5416 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5417 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5418 */
0765691e
MA		 5419 if (IS_AMD_CPU(env) &&
5420 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5421 cs->nr_threads > 1 && !ht_warned) {
5422 warn_report("This family of AMD CPU doesn't support "
5423 "hyperthreading(%d)",
5424 cs->nr_threads);
5425 error_printf("Please configure -smp options properly"
5426 " or try enabling topoext feature.\n");
5427 ht_warned = true;
e48638fd
WH		 5428 }
5429
d3c64d6a
IM		 5430 x86_cpu_apic_realize(cpu, &local_err);
5431 if (local_err != NULL) {
5432 goto out;
5433 }
14a10fc3 5434 cpu_reset(cs);
2b6f294c 5435
4dc1f449 5436 xcc->parent_realize(dev, &local_err);
2001d0cd 5437
4dc1f449
IM		 5438out:
5439 if (local_err != NULL) {
5440 error_propagate(errp, local_err);
5441 return;
5442 }
7a059953
AF		 5443}
5444
c884776e
IM		 5445static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5446{
5447 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5448 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5449 Error *local_err = NULL;
c884776e
IM		 5450
5451#ifndef CONFIG_USER_ONLY
5452 cpu_remove_sync(CPU(dev));
5453 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5454#endif
5455
5456 if (cpu->apic_state) {
5457 object_unparent(OBJECT(cpu->apic_state));
5458 cpu->apic_state = NULL;
5459 }
7bbc124e
LV		 5460
5461 xcc->parent_unrealize(dev, &local_err);
5462 if (local_err != NULL) {
5463 error_propagate(errp, local_err);
5464 return;
5465 }
c884776e
IM		 5466}
5467
38e5c119 5468typedef struct BitProperty {
a7b0ffac 5469 FeatureWord w;
38e5c119
EH		 5470 uint32_t mask;
5471} BitProperty;
5472
d7bce999
EB		 5473static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5474 void *opaque, Error **errp)
38e5c119 5475{
a7b0ffac 5476 X86CPU *cpu = X86_CPU(obj);
38e5c119 5477 BitProperty *fp = opaque;
a7b0ffac
EH		 5478 uint32_t f = cpu->env.features[fp->w];
5479 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5480 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5481}
5482
d7bce999
EB		 5483static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5484 void *opaque, Error **errp)
38e5c119
EH		 5485{
5486 DeviceState *dev = DEVICE(obj);
a7b0ffac 5487 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5488 BitProperty *fp = opaque;
5489 Error *local_err = NULL;
5490 bool value;
5491
5492 if (dev->realized) {
5493 qdev_prop_set_after_realize(dev, name, errp);
5494 return;
5495 }
5496
51e72bc1 5497 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5498 if (local_err) {
5499 error_propagate(errp, local_err);
5500 return;
5501 }
5502
5503 if (value) {
a7b0ffac 5504 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5505 } else {
a7b0ffac 5506 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5507 }
d4a606b3 5508 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5509}
5510
5511static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5512 void *opaque)
5513{
5514 BitProperty *prop = opaque;
5515 g_free(prop);
5516}
5517
5518/* Register a boolean property to get/set a single bit in a uint32_t field.
5519 *
5520 * The same property name can be registered multiple times to make it affect
5521 * multiple bits in the same FeatureWord. In that case, the getter will return
5522 * true only if all bits are set.
5523 */
5524static void x86_cpu_register_bit_prop(X86CPU *cpu,
5525 const char *prop_name,
a7b0ffac 5526 FeatureWord w,
38e5c119
EH		 5527 int bitnr)
5528{
5529 BitProperty *fp;
5530 ObjectProperty *op;
5531 uint32_t mask = (1UL << bitnr);
5532
5533 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5534 if (op) {
5535 fp = op->opaque;
a7b0ffac 5536 assert(fp->w == w);
38e5c119
EH		 5537 fp->mask |= mask;
5538 } else {
5539 fp = g_new0(BitProperty, 1);
a7b0ffac 5540 fp->w = w;
38e5c119
EH		 5541 fp->mask = mask;
5542 object_property_add(OBJECT(cpu), prop_name, "bool",
5543 x86_cpu_get_bit_prop,
5544 x86_cpu_set_bit_prop,
5545 x86_cpu_release_bit_prop, fp, &error_abort);
5546 }
5547}
5548
5549static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5550 FeatureWord w,
5551 int bitnr)
5552{
38e5c119 5553 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5554 const char *name = fi->feat_names[bitnr];
38e5c119 5555
16d2fcaa 5556 if (!name) {
38e5c119
EH		 5557 return;
5558 }
5559
fc7dfd20
EH		 5560 /* Property names should use "-" instead of "_".
5561 * Old names containing underscores are registered as aliases
5562 * using object_property_add_alias()
5563 */
16d2fcaa
EH		 5564 assert(!strchr(name, '_'));
5565 /* aliases don't use "|" delimiters anymore, they are registered
5566 * manually using object_property_add_alias() */
5567 assert(!strchr(name, '|'));
a7b0ffac 5568 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5569}
5570
d187e08d
AN		 5571static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5572{
5573 X86CPU *cpu = X86_CPU(cs);
5574 CPUX86State *env = &cpu->env;
5575 GuestPanicInformation *panic_info = NULL;
5576
5e953812 5577 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5578 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5579
e8ed97a6 5580 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5581
5e953812 5582 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5583 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5584 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5585 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5586 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5587 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5588 }
5589
5590 return panic_info;
5591}
5592static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5593 const char *name, void *opaque,
5594 Error **errp)
5595{
5596 CPUState *cs = CPU(obj);
5597 GuestPanicInformation *panic_info;
5598
5599 if (!cs->crash_occurred) {
5600 error_setg(errp, "No crash occured");
5601 return;
5602 }
5603
5604 panic_info = x86_cpu_get_crash_info(cs);
5605 if (panic_info == NULL) {
5606 error_setg(errp, "No crash information");
5607 return;
5608 }
5609
5610 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5611 errp);
5612 qapi_free_GuestPanicInformation(panic_info);
5613}
5614
de024815
AF		 5615static void x86_cpu_initfn(Object *obj)
5616{
5617 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5618 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5619 CPUX86State *env = &cpu->env;
38e5c119 5620 FeatureWord w;
de024815 5621
7506ed90 5622 cpu_set_cpustate_pointers(cpu);
71ad61d3
AF		 5623
5624 object_property_add(obj, "family", "int",
95b8519d 5625 x86_cpuid_version_get_family,
71ad61d3 5626 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5627 object_property_add(obj, "model", "int",
67e30c83 5628 x86_cpuid_version_get_model,
c5291a4f 5629 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5630 object_property_add(obj, "stepping", "int",
35112e41 5631 x86_cpuid_version_get_stepping,
036e2222 5632 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5633 object_property_add_str(obj, "vendor",
5634 x86_cpuid_get_vendor,
5635 x86_cpuid_set_vendor, NULL);
938d4c25 5636 object_property_add_str(obj, "model-id",
63e886eb 5637 x86_cpuid_get_model_id,
938d4c25 5638 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5639 object_property_add(obj, "tsc-frequency", "int",
5640 x86_cpuid_get_tsc_freq,
5641 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5642 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5643 x86_cpu_get_feature_words,
7e5292b5
EH		 5644 NULL, NULL, (void *)env->features, NULL);
5645 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5646 x86_cpu_get_feature_words,
5647 NULL, NULL, (void *)cpu->filtered_features, NULL);
506174bf
EH		 5648 /*
5649 * The "unavailable-features" property has the same semantics as
5650 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
5651 * QMP command: they list the features that would have prevented the
5652 * CPU from running if the "enforce" flag was set.
5653 */
5654 object_property_add(obj, "unavailable-features", "strList",
5655 x86_cpu_get_unavailable_features,
5656 NULL, NULL, NULL, &error_abort);
71ad61d3 5657
d187e08d
AN		 5658 object_property_add(obj, "crash-information", "GuestPanicInformation",
5659 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5660
92067bf4 5661 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5662
38e5c119
EH		 5663 for (w = 0; w < FEATURE_WORDS; w++) {
5664 int bitnr;
5665
5666 for (bitnr = 0; bitnr < 32; bitnr++) {
5667 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5668 }
5669 }
5670
16d2fcaa
EH		 5671 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5672 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5673 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5674 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5675 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5676 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5677 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5678
54b8dc7c
EH		 5679 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5680 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5681 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5682 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5683 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5684 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5685 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5686 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5687 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5688 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5689 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5690 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5691 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5692 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5693 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5694 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5695 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5696 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5697 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5698 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5699 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5700
0bacd8b3
EH		 5701 if (xcc->cpu_def) {
5702 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5703 }
de024815
AF		 5704}
5705
997395d3
IM		 5706static int64_t x86_cpu_get_arch_id(CPUState *cs)
5707{
5708 X86CPU *cpu = X86_CPU(cs);
997395d3 5709
7e72a45c 5710 return cpu->apic_id;
997395d3
IM		 5711}
5712
444d5590
AF		 5713static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5714{
5715 X86CPU *cpu = X86_CPU(cs);
5716
5717 return cpu->env.cr[0] & CR0_PG_MASK;
5718}
5719
f45748f1
AF		 5720static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5721{
5722 X86CPU *cpu = X86_CPU(cs);
5723
5724 cpu->env.eip = value;
5725}
5726
bdf7ae5b
AF		 5727static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5728{
5729 X86CPU *cpu = X86_CPU(cs);
5730
5731 cpu->env.eip = tb->pc - tb->cs_base;
5732}
5733
92d5f1a4 5734int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5735{
5736 X86CPU *cpu = X86_CPU(cs);
5737 CPUX86State *env = &cpu->env;
5738
92d5f1a4
PB		 5739#if !defined(CONFIG_USER_ONLY)
5740 if (interrupt_request & CPU_INTERRUPT_POLL) {
5741 return CPU_INTERRUPT_POLL;
5742 }
5743#endif
5744 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5745 return CPU_INTERRUPT_SIPI;
5746 }
5747
5748 if (env->hflags2 & HF2_GIF_MASK) {
5749 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5750 !(env->hflags & HF_SMM_MASK)) {
5751 return CPU_INTERRUPT_SMI;
5752 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5753 !(env->hflags2 & HF2_NMI_MASK)) {
5754 return CPU_INTERRUPT_NMI;
5755 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5756 return CPU_INTERRUPT_MCE;
5757 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5758 (((env->hflags2 & HF2_VINTR_MASK) &&
5759 (env->hflags2 & HF2_HIF_MASK)) ||
5760 (!(env->hflags2 & HF2_VINTR_MASK) &&
5761 (env->eflags & IF_MASK &&
5762 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5763 return CPU_INTERRUPT_HARD;
5764#if !defined(CONFIG_USER_ONLY)
5765 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5766 (env->eflags & IF_MASK) &&
5767 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5768 return CPU_INTERRUPT_VIRQ;
5769#endif
5770 }
5771 }
5772
5773 return 0;
5774}
5775
5776static bool x86_cpu_has_work(CPUState *cs)
5777{
5778 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5779}
5780
f50f3dd5
RH		 5781static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5782{
5783 X86CPU *cpu = X86_CPU(cs);
5784 CPUX86State *env = &cpu->env;
5785
5786 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5787 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5788 : bfd_mach_i386_i8086);
5789 info->print_insn = print_insn_i386;
b666d2a4
RH		 5790
5791 info->cap_arch = CS_ARCH_X86;
5792 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5793 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5794 : CS_MODE_16);
15fa1a0a
RH		 5795 info->cap_insn_unit = 1;
5796 info->cap_insn_split = 8;
f50f3dd5
RH		 5797}
5798
35b1b927
TW		 5799void x86_update_hflags(CPUX86State *env)
5800{
5801 uint32_t hflags;
5802#define HFLAG_COPY_MASK \
5803 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5804 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5805 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5806 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5807
5808 hflags = env->hflags & HFLAG_COPY_MASK;
5809 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5810 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5811 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5812 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5813 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5814
5815 if (env->cr[4] & CR4_OSFXSR_MASK) {
5816 hflags |= HF_OSFXSR_MASK;
5817 }
5818
5819 if (env->efer & MSR_EFER_LMA) {
5820 hflags |= HF_LMA_MASK;
5821 }
5822
5823 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5824 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5825 } else {
5826 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5827 (DESC_B_SHIFT - HF_CS32_SHIFT);
5828 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5829 (DESC_B_SHIFT - HF_SS32_SHIFT);
5830 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5831 !(hflags & HF_CS32_MASK)) {
5832 hflags |= HF_ADDSEG_MASK;
5833 } else {
5834 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5835 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5836 }
5837 }
5838 env->hflags = hflags;
5839}
5840
9337e3b6 5841static Property x86_cpu_properties[] = {
2da00e31
IM		 5842#ifdef CONFIG_USER_ONLY
5843 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5844 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5845 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5846 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5847 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5848#else
5849 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5850 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5851 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5852 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5853#endif
15f8b142 5854 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5855 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 5856
c8f0f88e 5857 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2d384d7c
VK		 5858 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
5859 HYPERV_FEAT_RELAXED, 0),
5860 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
5861 HYPERV_FEAT_VAPIC, 0),
5862 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
5863 HYPERV_FEAT_TIME, 0),
5864 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
5865 HYPERV_FEAT_CRASH, 0),
5866 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
5867 HYPERV_FEAT_RESET, 0),
5868 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
5869 HYPERV_FEAT_VPINDEX, 0),
5870 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
5871 HYPERV_FEAT_RUNTIME, 0),
5872 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
5873 HYPERV_FEAT_SYNIC, 0),
5874 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
5875 HYPERV_FEAT_STIMER, 0),
5876 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
5877 HYPERV_FEAT_FREQUENCIES, 0),
5878 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
5879 HYPERV_FEAT_REENLIGHTENMENT, 0),
5880 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
5881 HYPERV_FEAT_TLBFLUSH, 0),
5882 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
5883 HYPERV_FEAT_EVMCS, 0),
5884 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
5885 HYPERV_FEAT_IPI, 0),
5886
15e41345 5887 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5888 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5889 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5890 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5891 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 5892 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 5893 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5894 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5895 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5896 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5897 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5898 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5899 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5900 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5901 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5902 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5903 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5904 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5905 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5906 false),
0b564e6f 5907 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5908 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5909 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5910 true),
ab8f992e 5911 /*
a9f27ea9
EH		 5912 * lecacy_cache defaults to true unless the CPU model provides its
5913 * own cache information (see x86_cpu_load_def()).
ab8f992e 5914 */
a9f27ea9 5915 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5916
5917 /*
5918 * From "Requirements for Implementing the Microsoft
5919 * Hypervisor Interface":
5920 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5921 *
5922 * "Starting with Windows Server 2012 and Windows 8, if
5923 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5924 * the hypervisor imposes no specific limit to the number of VPs.
5925 * In this case, Windows Server 2012 guest VMs may use more than
5926 * 64 VPs, up to the maximum supported number of processors applicable
5927 * to the specific Windows version being used."
5928 */
5929 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5930 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5931 false),
f24c3a79
LK		 5932 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5933 true),
9337e3b6
EH		 5934 DEFINE_PROP_END_OF_LIST()
5935};
5936
5fd2087a
AF		 5937static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5938{
5939 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5940 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5941 DeviceClass *dc = DEVICE_CLASS(oc);
5942
bf853881
PMD		 5943 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5944 &xcc->parent_realize);
5945 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5946 &xcc->parent_unrealize);
9337e3b6 5947 dc->props = x86_cpu_properties;
5fd2087a
AF		 5948
5949 xcc->parent_reset = cc->reset;
5950 cc->reset = x86_cpu_reset;
91b1df8c 5951 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5952
500050d1 5953 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5954 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5955 cc->has_work = x86_cpu_has_work;
79c664f6 5956#ifdef CONFIG_TCG
97a8ea5a 5957 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5958 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5959#endif
878096ee 5960 cc->dump_state = x86_cpu_dump_state;
c86f106b 5961 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5962 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5963 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5964 cc->gdb_read_register = x86_cpu_gdb_read_register;
5965 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5966 cc->get_arch_id = x86_cpu_get_arch_id;
5967 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5d004421 5968#ifndef CONFIG_USER_ONLY
f8c45c65 5969 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5970 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5971 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5972 cc->write_elf64_note = x86_cpu_write_elf64_note;
5973 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5974 cc->write_elf32_note = x86_cpu_write_elf32_note;
5975 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5976 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5977#endif
00fcd100
AB		 5978 cc->gdb_arch_name = x86_gdb_arch_name;
5979#ifdef TARGET_X86_64
b8158192 5980 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 5981 cc->gdb_num_core_regs = 66;
00fcd100 5982#else
b8158192 5983 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 5984 cc->gdb_num_core_regs = 50;
00fcd100 5985#endif
79c664f6 5986#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5987 cc->debug_excp_handler = breakpoint_handler;
5988#endif
374e0cd4
RH		 5989 cc->cpu_exec_enter = x86_cpu_exec_enter;
5990 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5991#ifdef CONFIG_TCG
55c3ceef 5992 cc->tcg_initialize = tcg_x86_init;
5d004421 5993 cc->tlb_fill = x86_cpu_tlb_fill;
74d7fc7f 5994#endif
f50f3dd5 5995 cc->disas_set_info = x86_disas_set_info;
4c315c27 5996
e90f2a8c 5997 dc->user_creatable = true;
5fd2087a
AF		 5998}
5999
6000static const TypeInfo x86_cpu_type_info = {
6001 .name = TYPE_X86_CPU,
6002 .parent = TYPE_CPU,
6003 .instance_size = sizeof(X86CPU),
de024815 6004 .instance_init = x86_cpu_initfn,
d940ee9b 6005 .abstract = true,
5fd2087a
AF		 6006 .class_size = sizeof(X86CPUClass),
6007 .class_init = x86_cpu_common_class_init,
6008};
6009
5adbed30
EH		 6010
6011/* "base" CPU model, used by query-cpu-model-expansion */
6012static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
6013{
6014 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6015
6016 xcc->static_model = true;
6017 xcc->migration_safe = true;
6018 xcc->model_description = "base CPU model type with no features enabled";
6019 xcc->ordering = 8;
6020}
6021
6022static const TypeInfo x86_base_cpu_type_info = {
6023 .name = X86_CPU_TYPE_NAME("base"),
6024 .parent = TYPE_X86_CPU,
6025 .class_init = x86_cpu_base_class_init,
6026};
6027
5fd2087a
AF		 6028static void x86_cpu_register_types(void)
6029{
d940ee9b
EH		 6030 int i;
6031
5fd2087a 6032 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 6033 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
6034 x86_register_cpudef_type(&builtin_x86_defs[i]);
6035 }
c62f2630 6036 type_register_static(&max_x86_cpu_type_info);
5adbed30 6037 type_register_static(&x86_base_cpu_type_info);
d6dcc558 6038#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 6039 type_register_static(&host_x86_cpu_type_info);
6040#endif
5fd2087a
AF		 6041}
6042
6043type_init(x86_cpu_register_types)
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