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i386: x86_cpu_list_feature_names() function
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
0442428a 24#include "qemu/qemu-print.h"
c6dc6f63
AP		 25
26#include "cpu.h"
63c91552 27#include "exec/exec-all.h"
9c17d615 28#include "sysemu/kvm.h"
d6dcc558 29#include "sysemu/hvf.h"
8932cfdf 30#include "sysemu/cpus.h"
50a2c6e5 31#include "kvm_i386.h"
6cb8f2a6 32#include "sev_i386.h"
c6dc6f63 33
d49b6836 34#include "qemu/error-report.h"
1de7afc9
PB		 35#include "qemu/option.h"
36#include "qemu/config-file.h"
e688df6b 37#include "qapi/error.h"
112ed241
MA		 38#include "qapi/qapi-visit-misc.h"
39#include "qapi/qapi-visit-run-state.h"
452fcdbc 40#include "qapi/qmp/qdict.h"
7b1b5d19 41#include "qapi/qmp/qerror.h"
7b1b5d19 42#include "qapi/visitor.h"
f99fd7ca 43#include "qom/qom-qobject.h"
9c17d615 44#include "sysemu/arch_init.h"
96f75b59 45#include "qapi/qapi-commands-target.h"
71ad61d3 46
1814eab6 47#include "standard-headers/asm-x86/kvm_para.h"
65dee380 48
9c17d615 49#include "sysemu/sysemu.h"
53a89e26 50#include "hw/qdev-properties.h"
5232d00a 51#include "hw/i386/topology.h"
bdeec802 52#ifndef CONFIG_USER_ONLY
2001d0cd 53#include "exec/address-spaces.h"
741da0d3 54#include "hw/hw.h"
0d09e41a 55#include "hw/xen/xen.h"
0d09e41a 56#include "hw/i386/apic_internal.h"
bdeec802
IM		 57#endif
58
b666d2a4
RH		 59#include "disas/capstone.h"
60
7e3482f8
EH		 61/* Helpers for building CPUID[2] descriptors: */
62
63struct CPUID2CacheDescriptorInfo {
64 enum CacheType type;
65 int level;
66 int size;
67 int line_size;
68 int associativity;
69};
5e891bf8 70
7e3482f8
EH		 71/*
72 * Known CPUID 2 cache descriptors.
73 * From Intel SDM Volume 2A, CPUID instruction
74 */
75struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 76 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 32, },
5f00335a 80 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 81 .associativity = 4, .line_size = 64, },
5f00335a 82 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 83 .associativity = 2, .line_size = 32, },
5f00335a 84 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 32, },
5f00335a 86 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 87 .associativity = 4, .line_size = 64, },
5f00335a 88 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 89 .associativity = 6, .line_size = 64, },
5f00335a 90 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 91 .associativity = 2, .line_size = 64, },
5f00335a 92 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 93 .associativity = 8, .line_size = 64, },
94 /* lines per sector is not supported cpuid2_cache_descriptor(),
95 * so descriptors 0x22, 0x23 are not included
96 */
5f00335a 97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 98 .associativity = 16, .line_size = 64, },
99 /* lines per sector is not supported cpuid2_cache_descriptor(),
100 * so descriptors 0x25, 0x20 are not included
101 */
5f00335a 102 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 105 .associativity = 8, .line_size = 64, },
5f00335a 106 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 32, },
5f00335a 116 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 117 .associativity = 4, .line_size = 64, },
5f00335a 118 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 119 .associativity = 8, .line_size = 64, },
5f00335a 120 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 121 .associativity = 12, .line_size = 64, },
122 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 123 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 124 .associativity = 12, .line_size = 64, },
5f00335a 125 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 126 .associativity = 16, .line_size = 64, },
5f00335a 127 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 128 .associativity = 12, .line_size = 64, },
5f00335a 129 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 130 .associativity = 16, .line_size = 64, },
5f00335a 131 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 132 .associativity = 24, .line_size = 64, },
5f00335a 133 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 134 .associativity = 8, .line_size = 64, },
5f00335a 135 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 140 .associativity = 4, .line_size = 64, },
5f00335a 141 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 142 .associativity = 4, .line_size = 64, },
143 /* lines per sector is not supported cpuid2_cache_descriptor(),
144 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
145 */
5f00335a 146 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 147 .associativity = 8, .line_size = 64, },
5f00335a 148 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 2, .line_size = 64, },
5f00335a 150 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 64, },
5f00335a 152 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 8, .line_size = 32, },
5f00335a 160 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 161 .associativity = 4, .line_size = 64, },
5f00335a 162 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 163 .associativity = 8, .line_size = 64, },
5f00335a 164 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 169 .associativity = 4, .line_size = 64, },
5f00335a 170 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 175 .associativity = 8, .line_size = 64, },
5f00335a 176 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 181 .associativity = 12, .line_size = 64, },
5f00335a 182 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 187 .associativity = 16, .line_size = 64, },
5f00335a 188 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 191 .associativity = 24, .line_size = 64, },
5f00335a 192 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 193 .associativity = 24, .line_size = 64, },
194};
195
196/*
197 * "CPUID leaf 2 does not report cache descriptor information,
198 * use CPUID leaf 4 to query cache parameters"
199 */
200#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 201
7e3482f8
EH		 202/*
203 * Return a CPUID 2 cache descriptor for a given cache.
204 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
205 */
206static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
207{
208 int i;
209
210 assert(cache->size > 0);
211 assert(cache->level > 0);
212 assert(cache->line_size > 0);
213 assert(cache->associativity > 0);
214 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
215 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
216 if (d->level == cache->level && d->type == cache->type &&
217 d->size == cache->size && d->line_size == cache->line_size &&
218 d->associativity == cache->associativity) {
219 return i;
220 }
221 }
5e891bf8 222
7e3482f8
EH		 223 return CACHE_DESCRIPTOR_UNAVAILABLE;
224}
5e891bf8
EH		 225
226/* CPUID Leaf 4 constants: */
227
228/* EAX: */
7e3482f8
EH		 229#define CACHE_TYPE_D 1
230#define CACHE_TYPE_I 2
231#define CACHE_TYPE_UNIFIED 3
5e891bf8 232
7e3482f8 233#define CACHE_LEVEL(l) (l << 5)
5e891bf8 234
7e3482f8 235#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 236
237/* EDX: */
7e3482f8
EH		 238#define CACHE_NO_INVD_SHARING (1 << 0)
239#define CACHE_INCLUSIVE (1 << 1)
240#define CACHE_COMPLEX_IDX (1 << 2)
241
242/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 243#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
244 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
245 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
246 0 /* Invalid value */)
7e3482f8
EH		 247
248
249/* Encode cache info for CPUID[4] */
250static void encode_cache_cpuid4(CPUCacheInfo *cache,
251 int num_apic_ids, int num_cores,
252 uint32_t *eax, uint32_t *ebx,
253 uint32_t *ecx, uint32_t *edx)
254{
255 assert(cache->size == cache->line_size * cache->associativity *
256 cache->partitions * cache->sets);
257
258 assert(num_apic_ids > 0);
259 *eax = CACHE_TYPE(cache->type) |
260 CACHE_LEVEL(cache->level) |
261 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
262 ((num_cores - 1) << 26) |
263 ((num_apic_ids - 1) << 14);
264
265 assert(cache->line_size > 0);
266 assert(cache->partitions > 0);
267 assert(cache->associativity > 0);
268 /* We don't implement fully-associative caches */
269 assert(cache->associativity < cache->sets);
270 *ebx = (cache->line_size - 1) |
271 ((cache->partitions - 1) << 12) |
272 ((cache->associativity - 1) << 22);
273
274 assert(cache->sets > 0);
275 *ecx = cache->sets - 1;
276
277 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
278 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
279 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
280}
281
282/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
283static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
284{
285 assert(cache->size % 1024 == 0);
286 assert(cache->lines_per_tag > 0);
287 assert(cache->associativity > 0);
288 assert(cache->line_size > 0);
289 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
290 (cache->lines_per_tag << 8) | (cache->line_size);
291}
5e891bf8
EH		 292
293#define ASSOC_FULL 0xFF
294
295/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
296#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
297 a == 2 ? 0x2 : \
298 a == 4 ? 0x4 : \
299 a == 8 ? 0x6 : \
300 a == 16 ? 0x8 : \
301 a == 32 ? 0xA : \
302 a == 48 ? 0xB : \
303 a == 64 ? 0xC : \
304 a == 96 ? 0xD : \
305 a == 128 ? 0xE : \
306 a == ASSOC_FULL ? 0xF : \
307 0 /* invalid value */)
308
7e3482f8
EH		 309/*
310 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
311 * @l3 can be NULL.
312 */
313static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
314 CPUCacheInfo *l3,
315 uint32_t *ecx, uint32_t *edx)
316{
317 assert(l2->size % 1024 == 0);
318 assert(l2->associativity > 0);
319 assert(l2->lines_per_tag > 0);
320 assert(l2->line_size > 0);
321 *ecx = ((l2->size / 1024) << 16) |
322 (AMD_ENC_ASSOC(l2->associativity) << 12) |
323 (l2->lines_per_tag << 8) | (l2->line_size);
324
325 if (l3) {
326 assert(l3->size % (512 * 1024) == 0);
327 assert(l3->associativity > 0);
328 assert(l3->lines_per_tag > 0);
329 assert(l3->line_size > 0);
330 *edx = ((l3->size / (512 * 1024)) << 18) |
331 (AMD_ENC_ASSOC(l3->associativity) << 12) |
332 (l3->lines_per_tag << 8) | (l3->line_size);
333 } else {
334 *edx = 0;
335 }
336}
5e891bf8 337
8f4202fb
BM		 338/*
339 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
340 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
341 * Define the constants to build the cpu topology. Right now, TOPOEXT
342 * feature is enabled only on EPYC. So, these constants are based on
343 * EPYC supported configurations. We may need to handle the cases if
344 * these values change in future.
345 */
346/* Maximum core complexes in a node */
347#define MAX_CCX 2
348/* Maximum cores in a core complex */
349#define MAX_CORES_IN_CCX 4
350/* Maximum cores in a node */
351#define MAX_CORES_IN_NODE 8
352/* Maximum nodes in a socket */
353#define MAX_NODES_PER_SOCKET 4
354
355/*
356 * Figure out the number of nodes required to build this config.
357 * Max cores in a node is 8
358 */
359static int nodes_in_socket(int nr_cores)
360{
361 int nodes;
362
363 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
364
365 /* Hardware does not support config with 3 nodes, return 4 in that case */
366 return (nodes == 3) ? 4 : nodes;
367}
368
369/*
370 * Decide the number of cores in a core complex with the given nr_cores using
371 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
372 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
373 * L3 cache is shared across all cores in a core complex. So, this will also
374 * tell us how many cores are sharing the L3 cache.
375 */
376static int cores_in_core_complex(int nr_cores)
377{
378 int nodes;
379
380 /* Check if we can fit all the cores in one core complex */
381 if (nr_cores <= MAX_CORES_IN_CCX) {
382 return nr_cores;
383 }
384 /* Get the number of nodes required to build this config */
385 nodes = nodes_in_socket(nr_cores);
386
387 /*
388 * Divide the cores accros all the core complexes
389 * Return rounded up value
390 */
391 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
392}
393
394/* Encode cache info for CPUID[8000001D] */
395static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
396 uint32_t *eax, uint32_t *ebx,
397 uint32_t *ecx, uint32_t *edx)
398{
399 uint32_t l3_cores;
400 assert(cache->size == cache->line_size * cache->associativity *
401 cache->partitions * cache->sets);
402
403 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
404 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
405
406 /* L3 is shared among multiple cores */
407 if (cache->level == 3) {
408 l3_cores = cores_in_core_complex(cs->nr_cores);
409 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
410 } else {
411 *eax |= ((cs->nr_threads - 1) << 14);
412 }
413
414 assert(cache->line_size > 0);
415 assert(cache->partitions > 0);
416 assert(cache->associativity > 0);
417 /* We don't implement fully-associative caches */
418 assert(cache->associativity < cache->sets);
419 *ebx = (cache->line_size - 1) |
420 ((cache->partitions - 1) << 12) |
421 ((cache->associativity - 1) << 22);
422
423 assert(cache->sets > 0);
424 *ecx = cache->sets - 1;
425
426 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
427 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
428 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
429}
430
ed78467a
BM		 431/* Data structure to hold the configuration info for a given core index */
432struct core_topology {
433 /* core complex id of the current core index */
434 int ccx_id;
435 /*
436 * Adjusted core index for this core in the topology
437 * This can be 0,1,2,3 with max 4 cores in a core complex
438 */
439 int core_id;
440 /* Node id for this core index */
441 int node_id;
442 /* Number of nodes in this config */
443 int num_nodes;
444};
445
446/*
447 * Build the configuration closely match the EPYC hardware. Using the EPYC
448 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
449 * right now. This could change in future.
450 * nr_cores : Total number of cores in the config
451 * core_id : Core index of the current CPU
452 * topo : Data structure to hold all the config info for this core index
453 */
454static void build_core_topology(int nr_cores, int core_id,
455 struct core_topology *topo)
456{
457 int nodes, cores_in_ccx;
458
459 /* First get the number of nodes required */
460 nodes = nodes_in_socket(nr_cores);
461
462 cores_in_ccx = cores_in_core_complex(nr_cores);
463
464 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
465 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
466 topo->core_id = core_id % cores_in_ccx;
467 topo->num_nodes = nodes;
468}
469
470/* Encode cache info for CPUID[8000001E] */
471static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
472 uint32_t *eax, uint32_t *ebx,
473 uint32_t *ecx, uint32_t *edx)
474{
475 struct core_topology topo = {0};
631be321
BM		 476 unsigned long nodes;
477 int shift;
ed78467a
BM		 478
479 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
480 *eax = cpu->apic_id;
481 /*
482 * CPUID_Fn8000001E_EBX
483 * 31:16 Reserved
484 * 15:8 Threads per core (The number of threads per core is
485 * Threads per core + 1)
486 * 7:0 Core id (see bit decoding below)
487 * SMT:
488 * 4:3 node id
489 * 2 Core complex id
490 * 1:0 Core id
491 * Non SMT:
492 * 5:4 node id
493 * 3 Core complex id
494 * 1:0 Core id
495 */
496 if (cs->nr_threads - 1) {
497 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
498 (topo.ccx_id << 2) | topo.core_id;
499 } else {
500 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
501 }
502 /*
503 * CPUID_Fn8000001E_ECX
504 * 31:11 Reserved
505 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
506 * 7:0 Node id (see bit decoding below)
507 * 2 Socket id
508 * 1:0 Node id
509 */
631be321
BM		 510 if (topo.num_nodes <= 4) {
511 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
512 topo.node_id;
513 } else {
514 /*
515 * Node id fix up. Actual hardware supports up to 4 nodes. But with
516 * more than 32 cores, we may end up with more than 4 nodes.
517 * Node id is a combination of socket id and node id. Only requirement
518 * here is that this number should be unique accross the system.
519 * Shift the socket id to accommodate more nodes. We dont expect both
520 * socket id and node id to be big number at the same time. This is not
521 * an ideal config but we need to to support it. Max nodes we can have
522 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
523 * 5 bits for nodes. Find the left most set bit to represent the total
524 * number of nodes. find_last_bit returns last set bit(0 based). Left
525 * shift(+1) the socket id to represent all the nodes.
526 */
527 nodes = topo.num_nodes - 1;
528 shift = find_last_bit(&nodes, 8);
529 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
530 topo.node_id;
531 }
ed78467a
BM		 532 *edx = 0;
533}
534
ab8f992e
BM		 535/*
536 * Definitions of the hardcoded cache entries we expose:
537 * These are legacy cache values. If there is a need to change any
538 * of these values please use builtin_x86_defs
539 */
5e891bf8
EH		 540
541/* L1 data cache: */
ab8f992e 542static CPUCacheInfo legacy_l1d_cache = {
5f00335a 543 .type = DATA_CACHE,
7e3482f8
EH		 544 .level = 1,
545 .size = 32 * KiB,
546 .self_init = 1,
547 .line_size = 64,
548 .associativity = 8,
549 .sets = 64,
550 .partitions = 1,
551 .no_invd_sharing = true,
552};
553
5e891bf8 554/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 555static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 556 .type = DATA_CACHE,
7e3482f8
EH		 557 .level = 1,
558 .size = 64 * KiB,
559 .self_init = 1,
560 .line_size = 64,
561 .associativity = 2,
562 .sets = 512,
563 .partitions = 1,
564 .lines_per_tag = 1,
565 .no_invd_sharing = true,
566};
5e891bf8
EH		 567
568/* L1 instruction cache: */
ab8f992e 569static CPUCacheInfo legacy_l1i_cache = {
5f00335a 570 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 571 .level = 1,
572 .size = 32 * KiB,
573 .self_init = 1,
574 .line_size = 64,
575 .associativity = 8,
576 .sets = 64,
577 .partitions = 1,
578 .no_invd_sharing = true,
579};
580
5e891bf8 581/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 582static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 583 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 584 .level = 1,
585 .size = 64 * KiB,
586 .self_init = 1,
587 .line_size = 64,
588 .associativity = 2,
589 .sets = 512,
590 .partitions = 1,
591 .lines_per_tag = 1,
592 .no_invd_sharing = true,
593};
5e891bf8
EH		 594
595/* Level 2 unified cache: */
ab8f992e 596static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 597 .type = UNIFIED_CACHE,
598 .level = 2,
599 .size = 4 * MiB,
600 .self_init = 1,
601 .line_size = 64,
602 .associativity = 16,
603 .sets = 4096,
604 .partitions = 1,
605 .no_invd_sharing = true,
606};
607
5e891bf8 608/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 609static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 610 .type = UNIFIED_CACHE,
611 .level = 2,
612 .size = 2 * MiB,
613 .line_size = 64,
614 .associativity = 8,
615};
616
617
5e891bf8 618/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 619static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 620 .type = UNIFIED_CACHE,
621 .level = 2,
622 .size = 512 * KiB,
623 .line_size = 64,
624 .lines_per_tag = 1,
625 .associativity = 16,
626 .sets = 512,
627 .partitions = 1,
628};
5e891bf8 629
14c985cf 630/* Level 3 unified cache: */
ab8f992e 631static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 632 .type = UNIFIED_CACHE,
633 .level = 3,
634 .size = 16 * MiB,
635 .line_size = 64,
636 .associativity = 16,
637 .sets = 16384,
638 .partitions = 1,
639 .lines_per_tag = 1,
640 .self_init = true,
641 .inclusive = true,
642 .complex_indexing = true,
643};
5e891bf8
EH		 644
645/* TLB definitions: */
646
647#define L1_DTLB_2M_ASSOC 1
648#define L1_DTLB_2M_ENTRIES 255
649#define L1_DTLB_4K_ASSOC 1
650#define L1_DTLB_4K_ENTRIES 255
651
652#define L1_ITLB_2M_ASSOC 1
653#define L1_ITLB_2M_ENTRIES 255
654#define L1_ITLB_4K_ASSOC 1
655#define L1_ITLB_4K_ENTRIES 255
656
657#define L2_DTLB_2M_ASSOC 0 /* disabled */
658#define L2_DTLB_2M_ENTRIES 0 /* disabled */
659#define L2_DTLB_4K_ASSOC 4
660#define L2_DTLB_4K_ENTRIES 512
661
662#define L2_ITLB_2M_ASSOC 0 /* disabled */
663#define L2_ITLB_2M_ENTRIES 0 /* disabled */
664#define L2_ITLB_4K_ASSOC 4
665#define L2_ITLB_4K_ENTRIES 512
666
e37a5c7f
CP		 667/* CPUID Leaf 0x14 constants: */
668#define INTEL_PT_MAX_SUBLEAF 0x1
669/*
670 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
671 * MSR can be accessed;
672 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
673 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
674 * of Intel PT MSRs across warm reset;
675 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
676 */
677#define INTEL_PT_MINIMAL_EBX 0xf
678/*
679 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
680 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
681 * accessed;
682 * bit[01]: ToPA tables can hold any number of output entries, up to the
683 * maximum allowed by the MaskOrTableOffset field of
684 * IA32_RTIT_OUTPUT_MASK_PTRS;
685 * bit[02]: Support Single-Range Output scheme;
686 */
687#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 688/* generated packets which contain IP payloads have LIP values */
689#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 690#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
691#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
692#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
693#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
694#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 695
99b88a17
IM		 696static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
697 uint32_t vendor2, uint32_t vendor3)
698{
699 int i;
700 for (i = 0; i < 4; i++) {
701 dst[i] = vendor1 >> (8 * i);
702 dst[i + 4] = vendor2 >> (8 * i);
703 dst[i + 8] = vendor3 >> (8 * i);
704 }
705 dst[CPUID_VENDOR_SZ] = '\0';
706}
707
621626ce
EH		 708#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
709#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
710 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
711#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
712 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
713 CPUID_PSE36 | CPUID_FXSR)
714#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
715#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
716 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
717 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
718 CPUID_PAE | CPUID_SEP | CPUID_APIC)
719
720#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
721 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
722 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
723 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 724 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 725 /* partly implemented:
726 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
727 /* missing:
728 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
729#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
730 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
731 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 732 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 733 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
734 CPUID_EXT_RDRAND)
621626ce
EH		 735 /* missing:
736 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
737 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
738 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 739 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 740 CPUID_EXT_F16C */
621626ce
EH		 741
742#ifdef TARGET_X86_64
743#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
744#else
745#define TCG_EXT2_X86_64_FEATURES 0
746#endif
747
748#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
749 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
750 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
751 TCG_EXT2_X86_64_FEATURES)
752#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
753 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
754#define TCG_EXT4_FEATURES 0
fe441054 755#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 756#define TCG_KVM_FEATURES 0
757#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 758 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
759 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 760 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
761 CPUID_7_0_EBX_ERMS)
621626ce 762 /* missing:
07929f2a 763 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 764 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 765 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 766#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
767 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 768 CPUID_7_0_ECX_LA57)
95ea69fb 769#define TCG_7_0_EDX_FEATURES 0
303752a9 770#define TCG_APM_FEATURES 0
28b8e4d0 771#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 772#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
773 /* missing:
774 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 775
07585923
RH		 776typedef enum FeatureWordType {
777 CPUID_FEATURE_WORD,
778 MSR_FEATURE_WORD,
779} FeatureWordType;
780
5ef57876 781typedef struct FeatureWordInfo {
07585923 782 FeatureWordType type;
2d5312da
EH		 783 /* feature flags names are taken from "Intel Processor Identification and
784 * the CPUID Instruction" and AMD's "CPUID Specification".
785 * In cases of disagreement between feature naming conventions,
786 * aliases may be added.
787 */
788 const char *feat_names[32];
07585923
RH		 789 union {
790 /* If type==CPUID_FEATURE_WORD */
791 struct {
792 uint32_t eax; /* Input EAX for CPUID */
793 bool needs_ecx; /* CPUID instruction uses ECX as input */
794 uint32_t ecx; /* Input ECX value for CPUID */
795 int reg; /* output register (R_* constant) */
796 } cpuid;
797 /* If type==MSR_FEATURE_WORD */
798 struct {
799 uint32_t index;
800 struct { /*CPUID that enumerate this MSR*/
801 FeatureWord cpuid_class;
802 uint32_t cpuid_flag;
803 } cpuid_dep;
804 } msr;
805 };
37ce3522 806 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 807 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 808 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint32_t no_autoenable_flags;
5ef57876
EH		 811} FeatureWordInfo;
812
813static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 814 [FEAT_1_EDX] = {
07585923 815 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 816 .feat_names = {
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
825 },
07585923 826 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 827 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 828 },
829 [FEAT_1_ECX] = {
07585923 830 .type = CPUID_FEATURE_WORD,
2d5312da 831 .feat_names = {
16d2fcaa 832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 833 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 834 "tm2", "ssse3", "cid", NULL,
835 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 836 NULL, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 839 "avx", "f16c", "rdrand", "hypervisor",
840 },
07585923 841 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 842 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 843 },
2d5312da
EH		 844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
848 */
bffd67b0 849 [FEAT_8000_0001_EDX] = {
07585923 850 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 851 .feat_names = {
852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 857 "nx", NULL, "mmxext", NULL /* mmx */,
858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL, "lm", "3dnowext", "3dnow",
2d5312da 860 },
07585923 861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 862 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 863 },
864 [FEAT_8000_0001_ECX] = {
07585923 865 .type = CPUID_FEATURE_WORD,
2d5312da 866 .feat_names = {
fc7dfd20 867 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 871 "fma4", "tce", NULL, "nodeid-msr",
872 NULL, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 874 NULL, NULL, NULL, NULL,
875 },
07585923 876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 877 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 878 /*
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
882 */
883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 884 },
89e49c8b 885 [FEAT_C000_0001_EDX] = {
07585923 886 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 887 .feat_names = {
888 NULL, NULL, "xstore", "xstore-en",
889 NULL, NULL, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 },
07585923 897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 898 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 899 },
bffd67b0 900 [FEAT_KVM] = {
07585923 901 .type = CPUID_FEATURE_WORD,
2d5312da 902 .feat_names = {
fc7dfd20
EH		 903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 "kvmclock-stable-bit", NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 },
07585923 912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 913 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 914 },
be777326 915 [FEAT_KVM_HINTS] = {
07585923 916 .type = CPUID_FEATURE_WORD,
be777326
WL		 917 .feat_names = {
918 "kvm-hint-dedicated", NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 },
07585923 927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 928 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 929 /*
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
932 */
933 .no_autoenable_flags = ~0U,
be777326 934 },
abd5fc4c
VK		 935 /*
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
941 */
c35bd19a 942 [FEAT_HYPERV_EAX] = {
07585923 943 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 944 .feat_names = {
945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
952 NULL, NULL,
2d5312da
EH		 953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 },
07585923 958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 959 },
960 [FEAT_HYPERV_EBX] = {
07585923 961 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 962 .feat_names = {
963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
965 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
966 NULL /* hv_create_port */, NULL /* hv_connect_port */,
967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
969 NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 },
07585923 975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 976 },
977 [FEAT_HYPERV_EDX] = {
07585923 978 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 979 .feat_names = {
980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
983 NULL, NULL,
984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 },
07585923 991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 992 },
a2b107db
VK		 993 [FEAT_HV_RECOMM_EAX] = {
994 .type = CPUID_FEATURE_WORD,
995 .feat_names = {
996 NULL /* hv_recommend_pv_as_switch */,
997 NULL /* hv_recommend_pv_tlbflush_local */,
998 NULL /* hv_recommend_pv_tlbflush_remote */,
999 NULL /* hv_recommend_msr_apic_access */,
1000 NULL /* hv_recommend_msr_reset */,
1001 NULL /* hv_recommend_relaxed_timing */,
1002 NULL /* hv_recommend_dma_remapping */,
1003 NULL /* hv_recommend_int_remapping */,
1004 NULL /* hv_recommend_x2apic_msrs */,
1005 NULL /* hv_recommend_autoeoi_deprecation */,
1006 NULL /* hv_recommend_pv_ipi */,
1007 NULL /* hv_recommend_ex_hypercalls */,
1008 NULL /* hv_hypervisor_is_nested */,
1009 NULL /* hv_recommend_int_mbec */,
1010 NULL /* hv_recommend_evmcs */,
1011 NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 },
1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1018 },
1019 [FEAT_HV_NESTED_EAX] = {
1020 .type = CPUID_FEATURE_WORD,
1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1022 },
bffd67b0 1023 [FEAT_SVM] = {
07585923 1024 .type = CPUID_FEATURE_WORD,
2d5312da 1025 .feat_names = {
fc7dfd20
EH		 1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 1029 "pfthreshold", NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 },
07585923 1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 1036 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 1037 },
1038 [FEAT_7_0_EBX] = {
07585923 1039 .type = CPUID_FEATURE_WORD,
2d5312da 1040 .feat_names = {
fc7dfd20 1041 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1042 "hle", "avx2", NULL, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL, NULL, "mpx", NULL,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1047 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1049 },
07585923
RH		 1050 .cpuid = {
1051 .eax = 7,
1052 .needs_ecx = true, .ecx = 0,
1053 .reg = R_EBX,
1054 },
37ce3522 1055 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1056 },
f74eefe0 1057 [FEAT_7_0_ECX] = {
07585923 1058 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1059 .feat_names = {
1060 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1061 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1064 "la57", NULL, NULL, NULL,
2d5312da 1065 NULL, NULL, "rdpid", NULL,
24261de4 1066 NULL, "cldemote", NULL, "movdiri",
1c65775f 1067 "movdir64b", NULL, NULL, NULL,
2d5312da 1068 },
07585923
RH		 1069 .cpuid = {
1070 .eax = 7,
1071 .needs_ecx = true, .ecx = 0,
1072 .reg = R_ECX,
1073 },
f74eefe0
HH		 1074 .tcg_features = TCG_7_0_ECX_FEATURES,
1075 },
95ea69fb 1076 [FEAT_7_0_EDX] = {
07585923 1077 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1078 .feat_names = {
1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1080 NULL, NULL, NULL, NULL,
b2ae5210 1081 NULL, NULL, "md-clear", NULL,
95ea69fb 1082 NULL, NULL, NULL, NULL,
712f807e 1083 NULL, NULL, NULL, NULL,
95ea69fb 1084 NULL, NULL, NULL, NULL,
0e891658 1085 NULL, NULL, "spec-ctrl", "stibp",
3fc7c731 1086 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1087 },
07585923
RH		 1088 .cpuid = {
1089 .eax = 7,
1090 .needs_ecx = true, .ecx = 0,
1091 .reg = R_EDX,
1092 },
95ea69fb
LK		 1093 .tcg_features = TCG_7_0_EDX_FEATURES,
1094 },
303752a9 1095 [FEAT_8000_0007_EDX] = {
07585923 1096 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1097 .feat_names = {
1098 NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL,
1100 "invtsc", NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 },
07585923 1107 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1108 .tcg_features = TCG_APM_FEATURES,
1109 .unmigratable_flags = CPUID_APM_INVTSC,
1110 },
1b3420e1 1111 [FEAT_8000_0008_EBX] = {
07585923 1112 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1113 .feat_names = {
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL, NULL, NULL,
59a80a19 1116 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1117 "ibpb", NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
254790a9 1120 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1121 NULL, NULL, NULL, NULL,
1122 },
07585923 1123 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1124 .tcg_features = 0,
1125 .unmigratable_flags = 0,
1126 },
0bb0b2d2 1127 [FEAT_XSAVE] = {
07585923 1128 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1129 .feat_names = {
1130 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 },
07585923
RH		 1139 .cpuid = {
1140 .eax = 0xd,
1141 .needs_ecx = true, .ecx = 1,
1142 .reg = R_EAX,
1143 },
c9cfe8f9 1144 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1145 },
28b8e4d0 1146 [FEAT_6_EAX] = {
07585923 1147 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1148 .feat_names = {
1149 NULL, NULL, "arat", NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 },
07585923 1158 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1159 .tcg_features = TCG_6_EAX_FEATURES,
1160 },
96193c22 1161 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1162 .type = CPUID_FEATURE_WORD,
1163 .cpuid = {
1164 .eax = 0xD,
1165 .needs_ecx = true, .ecx = 0,
1166 .reg = R_EAX,
1167 },
96193c22 1168 .tcg_features = ~0U,
6fb2fff7
EH		 1169 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1170 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1171 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1172 XSTATE_PKRU_MASK,
96193c22
EH		 1173 },
1174 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1175 .type = CPUID_FEATURE_WORD,
1176 .cpuid = {
1177 .eax = 0xD,
1178 .needs_ecx = true, .ecx = 0,
1179 .reg = R_EDX,
1180 },
96193c22
EH		 1181 .tcg_features = ~0U,
1182 },
d86f9636
RH		 1183 /*Below are MSR exposed features*/
1184 [FEAT_ARCH_CAPABILITIES] = {
1185 .type = MSR_FEATURE_WORD,
1186 .feat_names = {
1187 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
20140a82 1188 "ssb-no", "mds-no", NULL, NULL,
d86f9636
RH		 1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 },
1196 .msr = {
1197 .index = MSR_IA32_ARCH_CAPABILITIES,
1198 .cpuid_dep = {
1199 FEAT_7_0_EDX,
1200 CPUID_7_0_EDX_ARCH_CAPABILITIES
1201 }
1202 },
1203 },
5ef57876
EH		 1204};
1205
8e8aba50
EH		 1206typedef struct X86RegisterInfo32 {
1207 /* Name of register */
1208 const char *name;
1209 /* QAPI enum value register */
1210 X86CPURegister32 qapi_enum;
1211} X86RegisterInfo32;
1212
1213#define REGISTER(reg) \
5d371f41 1214 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1215static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1216 REGISTER(EAX),
1217 REGISTER(ECX),
1218 REGISTER(EDX),
1219 REGISTER(EBX),
1220 REGISTER(ESP),
1221 REGISTER(EBP),
1222 REGISTER(ESI),
1223 REGISTER(EDI),
1224};
1225#undef REGISTER
1226
3f32bd21
RH		 1227typedef struct ExtSaveArea {
1228 uint32_t feature, bits;
1229 uint32_t offset, size;
1230} ExtSaveArea;
1231
1232static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1233 [XSTATE_FP_BIT] = {
1234 /* x87 FP state component is always enabled if XSAVE is supported */
1235 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1236 /* x87 state is in the legacy region of the XSAVE area */
1237 .offset = 0,
1238 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1239 },
1240 [XSTATE_SSE_BIT] = {
1241 /* SSE state component is always enabled if XSAVE is supported */
1242 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1243 /* SSE state is in the legacy region of the XSAVE area */
1244 .offset = 0,
1245 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1246 },
cfc3b074
PB		 1247 [XSTATE_YMM_BIT] =
1248 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1249 .offset = offsetof(X86XSaveArea, avx_state),
1250 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1251 [XSTATE_BNDREGS_BIT] =
1252 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1253 .offset = offsetof(X86XSaveArea, bndreg_state),
1254 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1255 [XSTATE_BNDCSR_BIT] =
1256 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1257 .offset = offsetof(X86XSaveArea, bndcsr_state),
1258 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1259 [XSTATE_OPMASK_BIT] =
1260 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1261 .offset = offsetof(X86XSaveArea, opmask_state),
1262 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1263 [XSTATE_ZMM_Hi256_BIT] =
1264 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1265 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1266 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1267 [XSTATE_Hi16_ZMM_BIT] =
1268 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1269 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1270 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1271 [XSTATE_PKRU_BIT] =
1272 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1273 .offset = offsetof(X86XSaveArea, pkru_state),
1274 .size = sizeof(XSavePKRU) },
2560f19f 1275};
8e8aba50 1276
1fda6198
EH		 1277static uint32_t xsave_area_size(uint64_t mask)
1278{
1279 int i;
e3c9022b 1280 uint64_t ret = 0;
1fda6198 1281
e3c9022b 1282 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1283 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1284 if ((mask >> i) & 1) {
1285 ret = MAX(ret, esa->offset + esa->size);
1286 }
1287 }
1288 return ret;
1289}
1290
d6dcc558
SAGDR		 1291static inline bool accel_uses_host_cpuid(void)
1292{
1293 return kvm_enabled() || hvf_enabled();
1294}
1295
96193c22
EH		 1296static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1297{
1298 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1299 cpu->env.features[FEAT_XSAVE_COMP_LO];
1300}
1301
8b4beddc
EH		 1302const char *get_register_name_32(unsigned int reg)
1303{
31ccdde2 1304 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1305 return NULL;
1306 }
8e8aba50 1307 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1308}
1309
84f1b92f
EH		 1310/*
1311 * Returns the set of feature flags that are supported and migratable by
1312 * QEMU, for a given FeatureWord.
1313 */
1314static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1315{
1316 FeatureWordInfo *wi = &feature_word_info[w];
1317 uint32_t r = 0;
1318 int i;
1319
1320 for (i = 0; i < 32; i++) {
1321 uint32_t f = 1U << i;
6fb2fff7
EH		 1322
1323 /* If the feature name is known, it is implicitly considered migratable,
1324 * unless it is explicitly set in unmigratable_flags */
1325 if ((wi->migratable_flags & f) ||
1326 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1327 r |= f;
84f1b92f 1328 }
84f1b92f
EH		 1329 }
1330 return r;
1331}
1332
bb44e0d1
JK		 1333void host_cpuid(uint32_t function, uint32_t count,
1334 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1335{
a1fd24af
AL		 1336 uint32_t vec[4];
1337
1338#ifdef __x86_64__
1339 asm volatile("cpuid"
1340 : "=a"(vec[0]), "=b"(vec[1]),
1341 "=c"(vec[2]), "=d"(vec[3])
1342 : "0"(function), "c"(count) : "cc");
c1f41226 1343#elif defined(__i386__)
a1fd24af
AL		 1344 asm volatile("pusha \n\t"
1345 "cpuid \n\t"
1346 "mov %%eax, 0(%2) \n\t"
1347 "mov %%ebx, 4(%2) \n\t"
1348 "mov %%ecx, 8(%2) \n\t"
1349 "mov %%edx, 12(%2) \n\t"
1350 "popa"
1351 : : "a"(function), "c"(count), "S"(vec)
1352 : "memory", "cc");
c1f41226
EH		 1353#else
1354 abort();
a1fd24af
AL		 1355#endif
1356
bdde476a 1357 if (eax)
a1fd24af 1358 *eax = vec[0];
bdde476a 1359 if (ebx)
a1fd24af 1360 *ebx = vec[1];
bdde476a 1361 if (ecx)
a1fd24af 1362 *ecx = vec[2];
bdde476a 1363 if (edx)
a1fd24af 1364 *edx = vec[3];
bdde476a 1365}
c6dc6f63 1366
20271d48
EH		 1367void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1368{
1369 uint32_t eax, ebx, ecx, edx;
1370
1371 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1372 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1373
1374 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1375 if (family) {
1376 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1377 }
1378 if (model) {
1379 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1380 }
1381 if (stepping) {
1382 *stepping = eax & 0x0F;
1383 }
1384}
1385
d940ee9b
EH		 1386/* CPU class name definitions: */
1387
d940ee9b
EH		 1388/* Return type name for a given CPU model name
1389 * Caller is responsible for freeing the returned string.
1390 */
1391static char *x86_cpu_type_name(const char *model_name)
1392{
1393 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1394}
1395
500050d1
AF		 1396static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1397{
d940ee9b 1398 ObjectClass *oc;
99193d8f 1399 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1400 oc = object_class_by_name(typename);
1401 g_free(typename);
1402 return oc;
500050d1
AF		 1403}
1404
104494ea
IM		 1405static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1406{
1407 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1408 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1409 return g_strndup(class_name,
1410 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1411}
1412
d940ee9b 1413struct X86CPUDefinition {
c6dc6f63
AP		 1414 const char *name;
1415 uint32_t level;
90e4b0c3 1416 uint32_t xlevel;
99b88a17
IM		 1417 /* vendor is zero-terminated, 12 character ASCII string */
1418 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1419 int family;
1420 int model;
1421 int stepping;
0514ef2f 1422 FeatureWordArray features;
807e9869 1423 const char *model_id;
6aaeb054 1424 CPUCaches *cache_info;
d940ee9b 1425};
c6dc6f63 1426
fe52acd2 1427static CPUCaches epyc_cache_info = {
a9f27ea9 1428 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1429 .type = DATA_CACHE,
fe52acd2
BM		 1430 .level = 1,
1431 .size = 32 * KiB,
1432 .line_size = 64,
1433 .associativity = 8,
1434 .partitions = 1,
1435 .sets = 64,
1436 .lines_per_tag = 1,
1437 .self_init = 1,
1438 .no_invd_sharing = true,
1439 },
a9f27ea9 1440 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1441 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1442 .level = 1,
1443 .size = 64 * KiB,
1444 .line_size = 64,
1445 .associativity = 4,
1446 .partitions = 1,
1447 .sets = 256,
1448 .lines_per_tag = 1,
1449 .self_init = 1,
1450 .no_invd_sharing = true,
1451 },
a9f27ea9 1452 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1453 .type = UNIFIED_CACHE,
1454 .level = 2,
1455 .size = 512 * KiB,
1456 .line_size = 64,
1457 .associativity = 8,
1458 .partitions = 1,
1459 .sets = 1024,
1460 .lines_per_tag = 1,
1461 },
a9f27ea9 1462 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1463 .type = UNIFIED_CACHE,
1464 .level = 3,
1465 .size = 8 * MiB,
1466 .line_size = 64,
1467 .associativity = 16,
1468 .partitions = 1,
1469 .sets = 8192,
1470 .lines_per_tag = 1,
1471 .self_init = true,
1472 .inclusive = true,
1473 .complex_indexing = true,
1474 },
1475};
1476
9576de75 1477static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1478 {
1479 .name = "qemu64",
3046bb5d 1480 .level = 0xd,
99b88a17 1481 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1482 .family = 6,
f8e6a11a 1483 .model = 6,
c6dc6f63 1484 .stepping = 3,
0514ef2f 1485 .features[FEAT_1_EDX] =
27861ecc 1486 PPRO_FEATURES |
c6dc6f63 1487 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1488 CPUID_PSE36,
0514ef2f 1489 .features[FEAT_1_ECX] =
6aa91e4a 1490 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1491 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1492 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1493 .features[FEAT_8000_0001_ECX] =
71195672 1494 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1495 .xlevel = 0x8000000A,
9cf2cc3d 1496 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1497 },
1498 {
1499 .name = "phenom",
1500 .level = 5,
99b88a17 1501 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1502 .family = 16,
1503 .model = 2,
1504 .stepping = 3,
b9fc20bc 1505 /* Missing: CPUID_HT */
0514ef2f 1506 .features[FEAT_1_EDX] =
27861ecc 1507 PPRO_FEATURES |
c6dc6f63 1508 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1509 CPUID_PSE36 | CPUID_VME,
0514ef2f 1510 .features[FEAT_1_ECX] =
27861ecc 1511 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1512 CPUID_EXT_POPCNT,
0514ef2f 1513 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1514 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1515 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1516 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1517 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1518 CPUID_EXT3_CR8LEG,
1519 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1520 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1521 .features[FEAT_8000_0001_ECX] =
27861ecc 1522 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1523 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1524 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1525 .features[FEAT_SVM] =
b9fc20bc 1526 CPUID_SVM_NPT,
c6dc6f63
AP		 1527 .xlevel = 0x8000001A,
1528 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1529 },
1530 {
1531 .name = "core2duo",
1532 .level = 10,
99b88a17 1533 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1534 .family = 6,
1535 .model = 15,
1536 .stepping = 11,
b9fc20bc 1537 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1538 .features[FEAT_1_EDX] =
27861ecc 1539 PPRO_FEATURES |
c6dc6f63 1540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1541 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1542 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1543 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1544 .features[FEAT_1_ECX] =
27861ecc 1545 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1546 CPUID_EXT_CX16,
0514ef2f 1547 .features[FEAT_8000_0001_EDX] =
27861ecc 1548 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1549 .features[FEAT_8000_0001_ECX] =
27861ecc 1550 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1551 .xlevel = 0x80000008,
1552 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1553 },
1554 {
1555 .name = "kvm64",
3046bb5d 1556 .level = 0xd,
99b88a17 1557 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1558 .family = 15,
1559 .model = 6,
1560 .stepping = 1,
b3a4f0b1 1561 /* Missing: CPUID_HT */
0514ef2f 1562 .features[FEAT_1_EDX] =
b3a4f0b1 1563 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1564 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1565 CPUID_PSE36,
1566 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1567 .features[FEAT_1_ECX] =
27861ecc 1568 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1569 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1570 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1571 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1572 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1573 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1574 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1575 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1576 .features[FEAT_8000_0001_ECX] =
27861ecc 1577 0,
c6dc6f63
AP		 1578 .xlevel = 0x80000008,
1579 .model_id = "Common KVM processor"
1580 },
c6dc6f63
AP		 1581 {
1582 .name = "qemu32",
1583 .level = 4,
99b88a17 1584 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1585 .family = 6,
f8e6a11a 1586 .model = 6,
c6dc6f63 1587 .stepping = 3,
0514ef2f 1588 .features[FEAT_1_EDX] =
27861ecc 1589 PPRO_FEATURES,
0514ef2f 1590 .features[FEAT_1_ECX] =
6aa91e4a 1591 CPUID_EXT_SSE3,
58012d66 1592 .xlevel = 0x80000004,
9cf2cc3d 1593 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1594 },
eafaf1e5
AP		 1595 {
1596 .name = "kvm32",
1597 .level = 5,
99b88a17 1598 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1599 .family = 15,
1600 .model = 6,
1601 .stepping = 1,
0514ef2f 1602 .features[FEAT_1_EDX] =
b3a4f0b1 1603 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1604 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1605 .features[FEAT_1_ECX] =
27861ecc 1606 CPUID_EXT_SSE3,
0514ef2f 1607 .features[FEAT_8000_0001_ECX] =
27861ecc 1608 0,
eafaf1e5
AP		 1609 .xlevel = 0x80000008,
1610 .model_id = "Common 32-bit KVM processor"
1611 },
c6dc6f63
AP		 1612 {
1613 .name = "coreduo",
1614 .level = 10,
99b88a17 1615 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1616 .family = 6,
1617 .model = 14,
1618 .stepping = 8,
b9fc20bc 1619 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1620 .features[FEAT_1_EDX] =
27861ecc 1621 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1622 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1623 CPUID_SS,
1624 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1625 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1626 .features[FEAT_1_ECX] =
e93abc14 1627 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1628 .features[FEAT_8000_0001_EDX] =
27861ecc 1629 CPUID_EXT2_NX,
c6dc6f63
AP		 1630 .xlevel = 0x80000008,
1631 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1632 },
1633 {
1634 .name = "486",
58012d66 1635 .level = 1,
99b88a17 1636 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1637 .family = 4,
b2a856d9 1638 .model = 8,
c6dc6f63 1639 .stepping = 0,
0514ef2f 1640 .features[FEAT_1_EDX] =
27861ecc 1641 I486_FEATURES,
c6dc6f63 1642 .xlevel = 0,
807e9869 1643 .model_id = "",
c6dc6f63
AP		 1644 },
1645 {
1646 .name = "pentium",
1647 .level = 1,
99b88a17 1648 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1649 .family = 5,
1650 .model = 4,
1651 .stepping = 3,
0514ef2f 1652 .features[FEAT_1_EDX] =
27861ecc 1653 PENTIUM_FEATURES,
c6dc6f63 1654 .xlevel = 0,
807e9869 1655 .model_id = "",
c6dc6f63
AP		 1656 },
1657 {
1658 .name = "pentium2",
1659 .level = 2,
99b88a17 1660 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1661 .family = 6,
1662 .model = 5,
1663 .stepping = 2,
0514ef2f 1664 .features[FEAT_1_EDX] =
27861ecc 1665 PENTIUM2_FEATURES,
c6dc6f63 1666 .xlevel = 0,
807e9869 1667 .model_id = "",
c6dc6f63
AP		 1668 },
1669 {
1670 .name = "pentium3",
3046bb5d 1671 .level = 3,
99b88a17 1672 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1673 .family = 6,
1674 .model = 7,
1675 .stepping = 3,
0514ef2f 1676 .features[FEAT_1_EDX] =
27861ecc 1677 PENTIUM3_FEATURES,
c6dc6f63 1678 .xlevel = 0,
807e9869 1679 .model_id = "",
c6dc6f63
AP		 1680 },
1681 {
1682 .name = "athlon",
1683 .level = 2,
99b88a17 1684 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1685 .family = 6,
1686 .model = 2,
1687 .stepping = 3,
0514ef2f 1688 .features[FEAT_1_EDX] =
27861ecc 1689 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1690 CPUID_MCA,
0514ef2f 1691 .features[FEAT_8000_0001_EDX] =
60032ac0 1692 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1693 .xlevel = 0x80000008,
9cf2cc3d 1694 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1695 },
1696 {
1697 .name = "n270",
3046bb5d 1698 .level = 10,
99b88a17 1699 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1700 .family = 6,
1701 .model = 28,
1702 .stepping = 2,
b9fc20bc 1703 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1704 .features[FEAT_1_EDX] =
27861ecc 1705 PPRO_FEATURES |
b9fc20bc
EH		 1706 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1707 CPUID_ACPI | CPUID_SS,
c6dc6f63 1708 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1709 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1710 * CPUID_EXT_XTPR */
0514ef2f 1711 .features[FEAT_1_ECX] =
27861ecc 1712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1713 CPUID_EXT_MOVBE,
0514ef2f 1714 .features[FEAT_8000_0001_EDX] =
60032ac0 1715 CPUID_EXT2_NX,
0514ef2f 1716 .features[FEAT_8000_0001_ECX] =
27861ecc 1717 CPUID_EXT3_LAHF_LM,
3046bb5d 1718 .xlevel = 0x80000008,
c6dc6f63
AP		 1719 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1720 },
3eca4642
EH		 1721 {
1722 .name = "Conroe",
3046bb5d 1723 .level = 10,
99b88a17 1724 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1725 .family = 6,
ffce9ebb 1726 .model = 15,
3eca4642 1727 .stepping = 3,
0514ef2f 1728 .features[FEAT_1_EDX] =
b3a4f0b1 1729 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1730 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1731 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1732 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1733 CPUID_DE | CPUID_FP87,
0514ef2f 1734 .features[FEAT_1_ECX] =
27861ecc 1735 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1736 .features[FEAT_8000_0001_EDX] =
27861ecc 1737 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1738 .features[FEAT_8000_0001_ECX] =
27861ecc 1739 CPUID_EXT3_LAHF_LM,
3046bb5d 1740 .xlevel = 0x80000008,
3eca4642
EH		 1741 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1742 },
1743 {
1744 .name = "Penryn",
3046bb5d 1745 .level = 10,
99b88a17 1746 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1747 .family = 6,
ffce9ebb 1748 .model = 23,
3eca4642 1749 .stepping = 3,
0514ef2f 1750 .features[FEAT_1_EDX] =
b3a4f0b1 1751 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1755 CPUID_DE | CPUID_FP87,
0514ef2f 1756 .features[FEAT_1_ECX] =
27861ecc 1757 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1758 CPUID_EXT_SSE3,
0514ef2f 1759 .features[FEAT_8000_0001_EDX] =
27861ecc 1760 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1761 .features[FEAT_8000_0001_ECX] =
27861ecc 1762 CPUID_EXT3_LAHF_LM,
3046bb5d 1763 .xlevel = 0x80000008,
3eca4642
EH		 1764 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1765 },
1766 {
1767 .name = "Nehalem",
3046bb5d 1768 .level = 11,
99b88a17 1769 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1770 .family = 6,
ffce9ebb 1771 .model = 26,
3eca4642 1772 .stepping = 3,
0514ef2f 1773 .features[FEAT_1_EDX] =
b3a4f0b1 1774 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1775 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1776 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1777 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1778 CPUID_DE | CPUID_FP87,
0514ef2f 1779 .features[FEAT_1_ECX] =
27861ecc 1780 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1781 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1782 .features[FEAT_8000_0001_EDX] =
27861ecc 1783 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1784 .features[FEAT_8000_0001_ECX] =
27861ecc 1785 CPUID_EXT3_LAHF_LM,
3046bb5d 1786 .xlevel = 0x80000008,
3eca4642
EH		 1787 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1788 },
ac96c413
EH		 1789 {
1790 .name = "Nehalem-IBRS",
1791 .level = 11,
1792 .vendor = CPUID_VENDOR_INTEL,
1793 .family = 6,
1794 .model = 26,
1795 .stepping = 3,
1796 .features[FEAT_1_EDX] =
1797 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1801 CPUID_DE | CPUID_FP87,
1802 .features[FEAT_1_ECX] =
1803 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1804 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1805 .features[FEAT_7_0_EDX] =
1806 CPUID_7_0_EDX_SPEC_CTRL,
1807 .features[FEAT_8000_0001_EDX] =
1808 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1809 .features[FEAT_8000_0001_ECX] =
1810 CPUID_EXT3_LAHF_LM,
1811 .xlevel = 0x80000008,
1812 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1813 },
3eca4642
EH		 1814 {
1815 .name = "Westmere",
1816 .level = 11,
99b88a17 1817 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1818 .family = 6,
1819 .model = 44,
1820 .stepping = 1,
0514ef2f 1821 .features[FEAT_1_EDX] =
b3a4f0b1 1822 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1823 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1824 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1825 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1826 CPUID_DE | CPUID_FP87,
0514ef2f 1827 .features[FEAT_1_ECX] =
27861ecc 1828 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1829 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1830 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1831 .features[FEAT_8000_0001_EDX] =
27861ecc 1832 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1833 .features[FEAT_8000_0001_ECX] =
27861ecc 1834 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1835 .features[FEAT_6_EAX] =
1836 CPUID_6_EAX_ARAT,
3046bb5d 1837 .xlevel = 0x80000008,
3eca4642
EH		 1838 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1839 },
ac96c413
EH		 1840 {
1841 .name = "Westmere-IBRS",
1842 .level = 11,
1843 .vendor = CPUID_VENDOR_INTEL,
1844 .family = 6,
1845 .model = 44,
1846 .stepping = 1,
1847 .features[FEAT_1_EDX] =
1848 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1849 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1850 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1851 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1852 CPUID_DE | CPUID_FP87,
1853 .features[FEAT_1_ECX] =
1854 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1855 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1856 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1857 .features[FEAT_8000_0001_EDX] =
1858 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1859 .features[FEAT_8000_0001_ECX] =
1860 CPUID_EXT3_LAHF_LM,
1861 .features[FEAT_7_0_EDX] =
1862 CPUID_7_0_EDX_SPEC_CTRL,
1863 .features[FEAT_6_EAX] =
1864 CPUID_6_EAX_ARAT,
1865 .xlevel = 0x80000008,
1866 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1867 },
3eca4642
EH		 1868 {
1869 .name = "SandyBridge",
1870 .level = 0xd,
99b88a17 1871 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1872 .family = 6,
1873 .model = 42,
1874 .stepping = 1,
0514ef2f 1875 .features[FEAT_1_EDX] =
b3a4f0b1 1876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1880 CPUID_DE | CPUID_FP87,
0514ef2f 1881 .features[FEAT_1_ECX] =
27861ecc 1882 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1883 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1884 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1885 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1886 CPUID_EXT_SSE3,
0514ef2f 1887 .features[FEAT_8000_0001_EDX] =
27861ecc 1888 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1889 CPUID_EXT2_SYSCALL,
0514ef2f 1890 .features[FEAT_8000_0001_ECX] =
27861ecc 1891 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1892 .features[FEAT_XSAVE] =
1893 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1894 .features[FEAT_6_EAX] =
1895 CPUID_6_EAX_ARAT,
3046bb5d 1896 .xlevel = 0x80000008,
3eca4642
EH		 1897 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1898 },
ac96c413
EH		 1899 {
1900 .name = "SandyBridge-IBRS",
1901 .level = 0xd,
1902 .vendor = CPUID_VENDOR_INTEL,
1903 .family = 6,
1904 .model = 42,
1905 .stepping = 1,
1906 .features[FEAT_1_EDX] =
1907 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1911 CPUID_DE | CPUID_FP87,
1912 .features[FEAT_1_ECX] =
1913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1914 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1915 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1916 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1917 CPUID_EXT_SSE3,
1918 .features[FEAT_8000_0001_EDX] =
1919 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1920 CPUID_EXT2_SYSCALL,
1921 .features[FEAT_8000_0001_ECX] =
1922 CPUID_EXT3_LAHF_LM,
1923 .features[FEAT_7_0_EDX] =
1924 CPUID_7_0_EDX_SPEC_CTRL,
1925 .features[FEAT_XSAVE] =
1926 CPUID_XSAVE_XSAVEOPT,
1927 .features[FEAT_6_EAX] =
1928 CPUID_6_EAX_ARAT,
1929 .xlevel = 0x80000008,
1930 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1931 },
2f9ac42a
PB		 1932 {
1933 .name = "IvyBridge",
1934 .level = 0xd,
1935 .vendor = CPUID_VENDOR_INTEL,
1936 .family = 6,
1937 .model = 58,
1938 .stepping = 9,
1939 .features[FEAT_1_EDX] =
1940 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1941 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1942 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1943 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1944 CPUID_DE | CPUID_FP87,
1945 .features[FEAT_1_ECX] =
1946 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1947 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1948 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1949 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1950 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1951 .features[FEAT_7_0_EBX] =
1952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1953 CPUID_7_0_EBX_ERMS,
1954 .features[FEAT_8000_0001_EDX] =
1955 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1956 CPUID_EXT2_SYSCALL,
1957 .features[FEAT_8000_0001_ECX] =
1958 CPUID_EXT3_LAHF_LM,
1959 .features[FEAT_XSAVE] =
1960 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1961 .features[FEAT_6_EAX] =
1962 CPUID_6_EAX_ARAT,
3046bb5d 1963 .xlevel = 0x80000008,
2f9ac42a
PB		 1964 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1965 },
ac96c413
EH		 1966 {
1967 .name = "IvyBridge-IBRS",
1968 .level = 0xd,
1969 .vendor = CPUID_VENDOR_INTEL,
1970 .family = 6,
1971 .model = 58,
1972 .stepping = 9,
1973 .features[FEAT_1_EDX] =
1974 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1975 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1976 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1977 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1978 CPUID_DE | CPUID_FP87,
1979 .features[FEAT_1_ECX] =
1980 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1982 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1983 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1984 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1985 .features[FEAT_7_0_EBX] =
1986 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1987 CPUID_7_0_EBX_ERMS,
1988 .features[FEAT_8000_0001_EDX] =
1989 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1990 CPUID_EXT2_SYSCALL,
1991 .features[FEAT_8000_0001_ECX] =
1992 CPUID_EXT3_LAHF_LM,
1993 .features[FEAT_7_0_EDX] =
1994 CPUID_7_0_EDX_SPEC_CTRL,
1995 .features[FEAT_XSAVE] =
1996 CPUID_XSAVE_XSAVEOPT,
1997 .features[FEAT_6_EAX] =
1998 CPUID_6_EAX_ARAT,
1999 .xlevel = 0x80000008,
2000 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2001 },
37507094 2002 {
a356850b
EH		 2003 .name = "Haswell-noTSX",
2004 .level = 0xd,
2005 .vendor = CPUID_VENDOR_INTEL,
2006 .family = 6,
2007 .model = 60,
2008 .stepping = 1,
2009 .features[FEAT_1_EDX] =
2010 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2011 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2012 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2013 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2014 CPUID_DE | CPUID_FP87,
2015 .features[FEAT_1_ECX] =
2016 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2017 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2018 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2019 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2020 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2021 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2022 .features[FEAT_8000_0001_EDX] =
2023 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2024 CPUID_EXT2_SYSCALL,
2025 .features[FEAT_8000_0001_ECX] =
becb6667 2026 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 2027 .features[FEAT_7_0_EBX] =
2028 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2029 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2030 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2031 .features[FEAT_XSAVE] =
2032 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2033 .features[FEAT_6_EAX] =
2034 CPUID_6_EAX_ARAT,
3046bb5d 2035 .xlevel = 0x80000008,
a356850b 2036 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 2037 },
2038 {
2039 .name = "Haswell-noTSX-IBRS",
2040 .level = 0xd,
2041 .vendor = CPUID_VENDOR_INTEL,
2042 .family = 6,
2043 .model = 60,
2044 .stepping = 1,
2045 .features[FEAT_1_EDX] =
2046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2050 CPUID_DE | CPUID_FP87,
2051 .features[FEAT_1_ECX] =
2052 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2053 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2054 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2055 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2056 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2057 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2058 .features[FEAT_8000_0001_EDX] =
2059 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2060 CPUID_EXT2_SYSCALL,
2061 .features[FEAT_8000_0001_ECX] =
2062 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2063 .features[FEAT_7_0_EDX] =
2064 CPUID_7_0_EDX_SPEC_CTRL,
2065 .features[FEAT_7_0_EBX] =
2066 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2067 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2068 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2069 .features[FEAT_XSAVE] =
2070 CPUID_XSAVE_XSAVEOPT,
2071 .features[FEAT_6_EAX] =
2072 CPUID_6_EAX_ARAT,
2073 .xlevel = 0x80000008,
2074 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2075 },
2076 {
37507094
EH		 2077 .name = "Haswell",
2078 .level = 0xd,
99b88a17 2079 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2080 .family = 6,
2081 .model = 60,
ec56a4a7 2082 .stepping = 4,
0514ef2f 2083 .features[FEAT_1_EDX] =
b3a4f0b1 2084 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2085 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2086 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2087 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2088 CPUID_DE | CPUID_FP87,
0514ef2f 2089 .features[FEAT_1_ECX] =
27861ecc 2090 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2091 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2092 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2093 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2094 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2095 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2096 .features[FEAT_8000_0001_EDX] =
27861ecc 2097 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2098 CPUID_EXT2_SYSCALL,
0514ef2f 2099 .features[FEAT_8000_0001_ECX] =
becb6667 2100 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2101 .features[FEAT_7_0_EBX] =
27861ecc 2102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2103 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2105 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2106 .features[FEAT_XSAVE] =
2107 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2108 .features[FEAT_6_EAX] =
2109 CPUID_6_EAX_ARAT,
3046bb5d 2110 .xlevel = 0x80000008,
37507094
EH		 2111 .model_id = "Intel Core Processor (Haswell)",
2112 },
ac96c413
EH		 2113 {
2114 .name = "Haswell-IBRS",
2115 .level = 0xd,
2116 .vendor = CPUID_VENDOR_INTEL,
2117 .family = 6,
2118 .model = 60,
2119 .stepping = 4,
2120 .features[FEAT_1_EDX] =
2121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2125 CPUID_DE | CPUID_FP87,
2126 .features[FEAT_1_ECX] =
2127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2128 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2129 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2130 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2131 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2132 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2133 .features[FEAT_8000_0001_EDX] =
2134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2135 CPUID_EXT2_SYSCALL,
2136 .features[FEAT_8000_0001_ECX] =
2137 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2138 .features[FEAT_7_0_EDX] =
2139 CPUID_7_0_EDX_SPEC_CTRL,
2140 .features[FEAT_7_0_EBX] =
2141 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2142 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2143 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2144 CPUID_7_0_EBX_RTM,
2145 .features[FEAT_XSAVE] =
2146 CPUID_XSAVE_XSAVEOPT,
2147 .features[FEAT_6_EAX] =
2148 CPUID_6_EAX_ARAT,
2149 .xlevel = 0x80000008,
2150 .model_id = "Intel Core Processor (Haswell, IBRS)",
2151 },
a356850b
EH		 2152 {
2153 .name = "Broadwell-noTSX",
2154 .level = 0xd,
2155 .vendor = CPUID_VENDOR_INTEL,
2156 .family = 6,
2157 .model = 61,
2158 .stepping = 2,
2159 .features[FEAT_1_EDX] =
2160 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2161 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2162 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2163 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2164 CPUID_DE | CPUID_FP87,
2165 .features[FEAT_1_ECX] =
2166 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2167 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2168 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2169 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2170 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2171 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2172 .features[FEAT_8000_0001_EDX] =
2173 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2174 CPUID_EXT2_SYSCALL,
2175 .features[FEAT_8000_0001_ECX] =
becb6667 2176 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2177 .features[FEAT_7_0_EBX] =
2178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2179 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2180 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2181 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2182 CPUID_7_0_EBX_SMAP,
2183 .features[FEAT_XSAVE] =
2184 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2185 .features[FEAT_6_EAX] =
2186 CPUID_6_EAX_ARAT,
3046bb5d 2187 .xlevel = 0x80000008,
a356850b
EH		 2188 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2189 },
ac96c413
EH		 2190 {
2191 .name = "Broadwell-noTSX-IBRS",
2192 .level = 0xd,
2193 .vendor = CPUID_VENDOR_INTEL,
2194 .family = 6,
2195 .model = 61,
2196 .stepping = 2,
2197 .features[FEAT_1_EDX] =
2198 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2199 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2200 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2201 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2202 CPUID_DE | CPUID_FP87,
2203 .features[FEAT_1_ECX] =
2204 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2205 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2206 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2207 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2208 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2209 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2210 .features[FEAT_8000_0001_EDX] =
2211 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2212 CPUID_EXT2_SYSCALL,
2213 .features[FEAT_8000_0001_ECX] =
2214 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2215 .features[FEAT_7_0_EDX] =
2216 CPUID_7_0_EDX_SPEC_CTRL,
2217 .features[FEAT_7_0_EBX] =
2218 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2219 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2220 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2221 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2222 CPUID_7_0_EBX_SMAP,
2223 .features[FEAT_XSAVE] =
2224 CPUID_XSAVE_XSAVEOPT,
2225 .features[FEAT_6_EAX] =
2226 CPUID_6_EAX_ARAT,
2227 .xlevel = 0x80000008,
2228 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2229 },
ece01354
EH		 2230 {
2231 .name = "Broadwell",
2232 .level = 0xd,
2233 .vendor = CPUID_VENDOR_INTEL,
2234 .family = 6,
2235 .model = 61,
2236 .stepping = 2,
2237 .features[FEAT_1_EDX] =
b3a4f0b1 2238 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2239 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2240 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2241 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2242 CPUID_DE | CPUID_FP87,
2243 .features[FEAT_1_ECX] =
2244 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2245 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2246 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2247 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2248 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2249 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2250 .features[FEAT_8000_0001_EDX] =
2251 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2252 CPUID_EXT2_SYSCALL,
2253 .features[FEAT_8000_0001_ECX] =
becb6667 2254 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2255 .features[FEAT_7_0_EBX] =
2256 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2257 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2258 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2259 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2260 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2261 .features[FEAT_XSAVE] =
2262 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2263 .features[FEAT_6_EAX] =
2264 CPUID_6_EAX_ARAT,
3046bb5d 2265 .xlevel = 0x80000008,
ece01354
EH		 2266 .model_id = "Intel Core Processor (Broadwell)",
2267 },
ac96c413
EH		 2268 {
2269 .name = "Broadwell-IBRS",
2270 .level = 0xd,
2271 .vendor = CPUID_VENDOR_INTEL,
2272 .family = 6,
2273 .model = 61,
2274 .stepping = 2,
2275 .features[FEAT_1_EDX] =
2276 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2277 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2278 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2279 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2280 CPUID_DE | CPUID_FP87,
2281 .features[FEAT_1_ECX] =
2282 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2283 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2284 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2285 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2286 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2287 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2288 .features[FEAT_8000_0001_EDX] =
2289 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2290 CPUID_EXT2_SYSCALL,
2291 .features[FEAT_8000_0001_ECX] =
2292 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2293 .features[FEAT_7_0_EDX] =
2294 CPUID_7_0_EDX_SPEC_CTRL,
2295 .features[FEAT_7_0_EBX] =
2296 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2297 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2298 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2299 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2300 CPUID_7_0_EBX_SMAP,
2301 .features[FEAT_XSAVE] =
2302 CPUID_XSAVE_XSAVEOPT,
2303 .features[FEAT_6_EAX] =
2304 CPUID_6_EAX_ARAT,
2305 .xlevel = 0x80000008,
2306 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2307 },
f6f949e9
EH		 2308 {
2309 .name = "Skylake-Client",
2310 .level = 0xd,
2311 .vendor = CPUID_VENDOR_INTEL,
2312 .family = 6,
2313 .model = 94,
2314 .stepping = 3,
2315 .features[FEAT_1_EDX] =
2316 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2317 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2318 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2319 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2320 CPUID_DE | CPUID_FP87,
2321 .features[FEAT_1_ECX] =
2322 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2323 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2324 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2325 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2326 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2327 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2328 .features[FEAT_8000_0001_EDX] =
2329 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2330 CPUID_EXT2_SYSCALL,
2331 .features[FEAT_8000_0001_ECX] =
2332 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2333 .features[FEAT_7_0_EBX] =
2334 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2335 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2336 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2337 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2338 CPUID_7_0_EBX_SMAP,
f6f949e9 2339 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2340 * including v4.1 to v4.12).
f6f949e9
EH		 2341 * KVM doesn't yet expose any XSAVES state save component,
2342 * and the only one defined in Skylake (processor tracing)
2343 * probably will block migration anyway.
2344 */
2345 .features[FEAT_XSAVE] =
2346 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2347 CPUID_XSAVE_XGETBV1,
2348 .features[FEAT_6_EAX] =
2349 CPUID_6_EAX_ARAT,
2350 .xlevel = 0x80000008,
2351 .model_id = "Intel Core Processor (Skylake)",
2352 },
ac96c413
EH		 2353 {
2354 .name = "Skylake-Client-IBRS",
2355 .level = 0xd,
2356 .vendor = CPUID_VENDOR_INTEL,
2357 .family = 6,
2358 .model = 94,
2359 .stepping = 3,
2360 .features[FEAT_1_EDX] =
2361 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2362 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2363 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2364 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2365 CPUID_DE | CPUID_FP87,
2366 .features[FEAT_1_ECX] =
2367 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2368 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2369 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2370 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2371 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2372 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2373 .features[FEAT_8000_0001_EDX] =
2374 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2375 CPUID_EXT2_SYSCALL,
2376 .features[FEAT_8000_0001_ECX] =
2377 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2378 .features[FEAT_7_0_EDX] =
2379 CPUID_7_0_EDX_SPEC_CTRL,
2380 .features[FEAT_7_0_EBX] =
2381 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2382 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2383 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2384 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2385 CPUID_7_0_EBX_SMAP,
ac96c413
EH		 2386 /* Missing: XSAVES (not supported by some Linux versions,
2387 * including v4.1 to v4.12).
2388 * KVM doesn't yet expose any XSAVES state save component,
2389 * and the only one defined in Skylake (processor tracing)
2390 * probably will block migration anyway.
2391 */
2392 .features[FEAT_XSAVE] =
2393 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2394 CPUID_XSAVE_XGETBV1,
2395 .features[FEAT_6_EAX] =
2396 CPUID_6_EAX_ARAT,
2397 .xlevel = 0x80000008,
2398 .model_id = "Intel Core Processor (Skylake, IBRS)",
2399 },
53f9a6f4
BF		 2400 {
2401 .name = "Skylake-Server",
2402 .level = 0xd,
2403 .vendor = CPUID_VENDOR_INTEL,
2404 .family = 6,
2405 .model = 85,
2406 .stepping = 4,
2407 .features[FEAT_1_EDX] =
2408 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2409 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2410 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2411 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2412 CPUID_DE | CPUID_FP87,
2413 .features[FEAT_1_ECX] =
2414 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2415 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2416 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2417 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2418 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2419 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2420 .features[FEAT_8000_0001_EDX] =
2421 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2422 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2423 .features[FEAT_8000_0001_ECX] =
2424 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2425 .features[FEAT_7_0_EBX] =
2426 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2427 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2428 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2429 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2430 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2431 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2432 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2433 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2434 .features[FEAT_7_0_ECX] =
2435 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2436 /* Missing: XSAVES (not supported by some Linux versions,
2437 * including v4.1 to v4.12).
2438 * KVM doesn't yet expose any XSAVES state save component,
2439 * and the only one defined in Skylake (processor tracing)
2440 * probably will block migration anyway.
2441 */
2442 .features[FEAT_XSAVE] =
2443 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2444 CPUID_XSAVE_XGETBV1,
2445 .features[FEAT_6_EAX] =
2446 CPUID_6_EAX_ARAT,
2447 .xlevel = 0x80000008,
2448 .model_id = "Intel Xeon Processor (Skylake)",
2449 },
ac96c413
EH		 2450 {
2451 .name = "Skylake-Server-IBRS",
2452 .level = 0xd,
2453 .vendor = CPUID_VENDOR_INTEL,
2454 .family = 6,
2455 .model = 85,
2456 .stepping = 4,
2457 .features[FEAT_1_EDX] =
2458 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2459 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2460 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2461 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2462 CPUID_DE | CPUID_FP87,
2463 .features[FEAT_1_ECX] =
2464 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2465 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2466 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2467 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2468 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2469 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2470 .features[FEAT_8000_0001_EDX] =
2471 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2472 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2473 .features[FEAT_8000_0001_ECX] =
2474 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2475 .features[FEAT_7_0_EDX] =
2476 CPUID_7_0_EDX_SPEC_CTRL,
2477 .features[FEAT_7_0_EBX] =
2478 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2479 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2480 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2481 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2482 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
ac96c413
EH		 2483 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2484 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2485 CPUID_7_0_EBX_AVX512VL,
09b9ee64
TX		 2486 .features[FEAT_7_0_ECX] =
2487 CPUID_7_0_ECX_PKU,
ac96c413
EH		 2488 /* Missing: XSAVES (not supported by some Linux versions,
2489 * including v4.1 to v4.12).
2490 * KVM doesn't yet expose any XSAVES state save component,
2491 * and the only one defined in Skylake (processor tracing)
2492 * probably will block migration anyway.
2493 */
2494 .features[FEAT_XSAVE] =
2495 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2496 CPUID_XSAVE_XGETBV1,
2497 .features[FEAT_6_EAX] =
2498 CPUID_6_EAX_ARAT,
2499 .xlevel = 0x80000008,
2500 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2501 },
c7a88b52
TX		 2502 {
2503 .name = "Cascadelake-Server",
2504 .level = 0xd,
2505 .vendor = CPUID_VENDOR_INTEL,
2506 .family = 6,
2507 .model = 85,
b0a19803 2508 .stepping = 6,
c7a88b52
TX		 2509 .features[FEAT_1_EDX] =
2510 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2511 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2512 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2513 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2514 CPUID_DE | CPUID_FP87,
2515 .features[FEAT_1_ECX] =
2516 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2517 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2518 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2519 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2520 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2521 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2522 .features[FEAT_8000_0001_EDX] =
2523 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2524 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2525 .features[FEAT_8000_0001_ECX] =
2526 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2527 .features[FEAT_7_0_EBX] =
2528 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2529 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2530 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2531 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2532 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 2533 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2534 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2535 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 2536 .features[FEAT_7_0_ECX] =
bb4928c7 2537 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 2538 CPUID_7_0_ECX_AVX512VNNI,
2539 .features[FEAT_7_0_EDX] =
2540 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2541 /* Missing: XSAVES (not supported by some Linux versions,
2542 * including v4.1 to v4.12).
2543 * KVM doesn't yet expose any XSAVES state save component,
2544 * and the only one defined in Skylake (processor tracing)
2545 * probably will block migration anyway.
2546 */
2547 .features[FEAT_XSAVE] =
2548 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2549 CPUID_XSAVE_XGETBV1,
2550 .features[FEAT_6_EAX] =
2551 CPUID_6_EAX_ARAT,
2552 .xlevel = 0x80000008,
2553 .model_id = "Intel Xeon Processor (Cascadelake)",
2554 },
8a11c62d
RH		 2555 {
2556 .name = "Icelake-Client",
2557 .level = 0xd,
2558 .vendor = CPUID_VENDOR_INTEL,
2559 .family = 6,
2560 .model = 126,
2561 .stepping = 0,
2562 .features[FEAT_1_EDX] =
2563 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2564 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2565 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2566 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2567 CPUID_DE | CPUID_FP87,
2568 .features[FEAT_1_ECX] =
2569 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2570 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2571 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2572 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2573 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2574 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2575 .features[FEAT_8000_0001_EDX] =
2576 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2577 CPUID_EXT2_SYSCALL,
2578 .features[FEAT_8000_0001_ECX] =
2579 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2580 .features[FEAT_8000_0008_EBX] =
2581 CPUID_8000_0008_EBX_WBNOINVD,
2582 .features[FEAT_7_0_EBX] =
2583 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2584 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2585 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2586 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 2587 CPUID_7_0_EBX_SMAP,
8a11c62d
RH		 2588 .features[FEAT_7_0_ECX] =
2589 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2590 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2591 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2592 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2593 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2594 .features[FEAT_7_0_EDX] =
2595 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2596 /* Missing: XSAVES (not supported by some Linux versions,
2597 * including v4.1 to v4.12).
2598 * KVM doesn't yet expose any XSAVES state save component,
2599 * and the only one defined in Skylake (processor tracing)
2600 * probably will block migration anyway.
2601 */
2602 .features[FEAT_XSAVE] =
2603 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2604 CPUID_XSAVE_XGETBV1,
2605 .features[FEAT_6_EAX] =
2606 CPUID_6_EAX_ARAT,
2607 .xlevel = 0x80000008,
2608 .model_id = "Intel Core Processor (Icelake)",
2609 },
2610 {
2611 .name = "Icelake-Server",
2612 .level = 0xd,
2613 .vendor = CPUID_VENDOR_INTEL,
2614 .family = 6,
2615 .model = 134,
2616 .stepping = 0,
2617 .features[FEAT_1_EDX] =
2618 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2619 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2620 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2621 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2622 CPUID_DE | CPUID_FP87,
2623 .features[FEAT_1_ECX] =
2624 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2625 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2626 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2627 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2628 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2629 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2630 .features[FEAT_8000_0001_EDX] =
2631 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2632 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2633 .features[FEAT_8000_0001_ECX] =
2634 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2635 .features[FEAT_8000_0008_EBX] =
2636 CPUID_8000_0008_EBX_WBNOINVD,
2637 .features[FEAT_7_0_EBX] =
2638 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2639 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2640 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2641 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2642 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 2643 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2644 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2645 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d
RH		 2646 .features[FEAT_7_0_ECX] =
2647 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2648 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2649 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2650 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2651 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2652 .features[FEAT_7_0_EDX] =
76e5a4d5 2653 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 2654 /* Missing: XSAVES (not supported by some Linux versions,
2655 * including v4.1 to v4.12).
2656 * KVM doesn't yet expose any XSAVES state save component,
2657 * and the only one defined in Skylake (processor tracing)
2658 * probably will block migration anyway.
2659 */
2660 .features[FEAT_XSAVE] =
2661 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2662 CPUID_XSAVE_XGETBV1,
2663 .features[FEAT_6_EAX] =
2664 CPUID_6_EAX_ARAT,
2665 .xlevel = 0x80000008,
2666 .model_id = "Intel Xeon Processor (Icelake)",
2667 },
a1849515
BF		 2668 {
2669 .name = "KnightsMill",
2670 .level = 0xd,
2671 .vendor = CPUID_VENDOR_INTEL,
2672 .family = 6,
2673 .model = 133,
2674 .stepping = 0,
2675 .features[FEAT_1_EDX] =
2676 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2677 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2678 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2679 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2680 CPUID_PSE | CPUID_DE | CPUID_FP87,
2681 .features[FEAT_1_ECX] =
2682 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2683 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2684 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2685 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2686 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2687 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2688 .features[FEAT_8000_0001_EDX] =
2689 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2690 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2691 .features[FEAT_8000_0001_ECX] =
2692 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2693 .features[FEAT_7_0_EBX] =
2694 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2695 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2696 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2697 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2698 CPUID_7_0_EBX_AVX512ER,
2699 .features[FEAT_7_0_ECX] =
2700 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2701 .features[FEAT_7_0_EDX] =
2702 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2703 .features[FEAT_XSAVE] =
2704 CPUID_XSAVE_XSAVEOPT,
2705 .features[FEAT_6_EAX] =
2706 CPUID_6_EAX_ARAT,
2707 .xlevel = 0x80000008,
2708 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2709 },
3eca4642
EH		 2710 {
2711 .name = "Opteron_G1",
2712 .level = 5,
99b88a17 2713 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2714 .family = 15,
2715 .model = 6,
2716 .stepping = 1,
0514ef2f 2717 .features[FEAT_1_EDX] =
b3a4f0b1 2718 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2722 CPUID_DE | CPUID_FP87,
0514ef2f 2723 .features[FEAT_1_ECX] =
27861ecc 2724 CPUID_EXT_SSE3,
0514ef2f 2725 .features[FEAT_8000_0001_EDX] =
2a923a29 2726 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2727 .xlevel = 0x80000008,
2728 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2729 },
2730 {
2731 .name = "Opteron_G2",
2732 .level = 5,
99b88a17 2733 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2734 .family = 15,
2735 .model = 6,
2736 .stepping = 1,
0514ef2f 2737 .features[FEAT_1_EDX] =
b3a4f0b1 2738 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2742 CPUID_DE | CPUID_FP87,
0514ef2f 2743 .features[FEAT_1_ECX] =
27861ecc 2744 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 2745 .features[FEAT_8000_0001_EDX] =
2a923a29 2746 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2747 .features[FEAT_8000_0001_ECX] =
27861ecc 2748 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2749 .xlevel = 0x80000008,
2750 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2751 },
2752 {
2753 .name = "Opteron_G3",
2754 .level = 5,
99b88a17 2755 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2756 .family = 16,
2757 .model = 2,
2758 .stepping = 3,
0514ef2f 2759 .features[FEAT_1_EDX] =
b3a4f0b1 2760 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2761 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2762 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2763 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2764 CPUID_DE | CPUID_FP87,
0514ef2f 2765 .features[FEAT_1_ECX] =
27861ecc 2766 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2767 CPUID_EXT_SSE3,
0514ef2f 2768 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 2769 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2770 CPUID_EXT2_RDTSCP,
0514ef2f 2771 .features[FEAT_8000_0001_ECX] =
27861ecc 2772 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2773 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2774 .xlevel = 0x80000008,
2775 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2776 },
2777 {
2778 .name = "Opteron_G4",
2779 .level = 0xd,
99b88a17 2780 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2781 .family = 21,
2782 .model = 1,
2783 .stepping = 2,
0514ef2f 2784 .features[FEAT_1_EDX] =
b3a4f0b1 2785 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2786 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2787 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2788 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2789 CPUID_DE | CPUID_FP87,
0514ef2f 2790 .features[FEAT_1_ECX] =
27861ecc 2791 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2792 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2793 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2794 CPUID_EXT_SSE3,
0514ef2f 2795 .features[FEAT_8000_0001_EDX] =
2a923a29 2796 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2797 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2798 .features[FEAT_8000_0001_ECX] =
27861ecc 2799 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2800 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2801 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2802 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2803 .features[FEAT_SVM] =
2804 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2805 /* no xsaveopt! */
3eca4642
EH		 2806 .xlevel = 0x8000001A,
2807 .model_id = "AMD Opteron 62xx class CPU",
2808 },
021941b9
AP		 2809 {
2810 .name = "Opteron_G5",
2811 .level = 0xd,
99b88a17 2812 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2813 .family = 21,
2814 .model = 2,
2815 .stepping = 0,
0514ef2f 2816 .features[FEAT_1_EDX] =
b3a4f0b1 2817 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2821 CPUID_DE | CPUID_FP87,
0514ef2f 2822 .features[FEAT_1_ECX] =
27861ecc 2823 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2824 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2825 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2826 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2827 .features[FEAT_8000_0001_EDX] =
2a923a29 2828 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2829 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2830 .features[FEAT_8000_0001_ECX] =
27861ecc 2831 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2832 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2833 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2834 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2835 .features[FEAT_SVM] =
2836 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2837 /* no xsaveopt! */
021941b9
AP		 2838 .xlevel = 0x8000001A,
2839 .model_id = "AMD Opteron 63xx class CPU",
2840 },
2e2efc7d
BS		 2841 {
2842 .name = "EPYC",
2843 .level = 0xd,
2844 .vendor = CPUID_VENDOR_AMD,
2845 .family = 23,
2846 .model = 1,
2847 .stepping = 2,
2848 .features[FEAT_1_EDX] =
2849 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2850 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2851 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2852 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2853 CPUID_VME | CPUID_FP87,
2854 .features[FEAT_1_ECX] =
2855 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2856 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2857 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2858 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2859 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2860 .features[FEAT_8000_0001_EDX] =
2861 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2862 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2863 CPUID_EXT2_SYSCALL,
2864 .features[FEAT_8000_0001_ECX] =
2865 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2866 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2867 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2868 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2869 .features[FEAT_7_0_EBX] =
2870 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2871 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2872 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2873 CPUID_7_0_EBX_SHA_NI,
2874 /* Missing: XSAVES (not supported by some Linux versions,
2875 * including v4.1 to v4.12).
2876 * KVM doesn't yet expose any XSAVES state save component.
2877 */
2878 .features[FEAT_XSAVE] =
2879 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2880 CPUID_XSAVE_XGETBV1,
2881 .features[FEAT_6_EAX] =
2882 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2883 .features[FEAT_SVM] =
2884 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2885 .xlevel = 0x8000001E,
2e2efc7d 2886 .model_id = "AMD EPYC Processor",
fe52acd2 2887 .cache_info = &epyc_cache_info,
2e2efc7d 2888 },
6cfbc54e
EH		 2889 {
2890 .name = "EPYC-IBPB",
2891 .level = 0xd,
2892 .vendor = CPUID_VENDOR_AMD,
2893 .family = 23,
2894 .model = 1,
2895 .stepping = 2,
2896 .features[FEAT_1_EDX] =
2897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2898 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2899 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2900 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2901 CPUID_VME | CPUID_FP87,
2902 .features[FEAT_1_ECX] =
2903 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2904 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2905 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2906 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2907 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2908 .features[FEAT_8000_0001_EDX] =
2909 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2910 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2911 CPUID_EXT2_SYSCALL,
2912 .features[FEAT_8000_0001_ECX] =
2913 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2914 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2915 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2916 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2917 .features[FEAT_8000_0008_EBX] =
2918 CPUID_8000_0008_EBX_IBPB,
2919 .features[FEAT_7_0_EBX] =
2920 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2921 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2922 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2923 CPUID_7_0_EBX_SHA_NI,
2924 /* Missing: XSAVES (not supported by some Linux versions,
2925 * including v4.1 to v4.12).
2926 * KVM doesn't yet expose any XSAVES state save component.
2927 */
2928 .features[FEAT_XSAVE] =
2929 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2930 CPUID_XSAVE_XGETBV1,
2931 .features[FEAT_6_EAX] =
2932 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2933 .features[FEAT_SVM] =
2934 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2935 .xlevel = 0x8000001E,
6cfbc54e 2936 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2937 .cache_info = &epyc_cache_info,
6cfbc54e 2938 },
8d031cec
PW		 2939 {
2940 .name = "Dhyana",
2941 .level = 0xd,
2942 .vendor = CPUID_VENDOR_HYGON,
2943 .family = 24,
2944 .model = 0,
2945 .stepping = 1,
2946 .features[FEAT_1_EDX] =
2947 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2948 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2949 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2950 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2951 CPUID_VME | CPUID_FP87,
2952 .features[FEAT_1_ECX] =
2953 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2954 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2955 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2956 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2957 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2958 .features[FEAT_8000_0001_EDX] =
2959 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2960 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2961 CPUID_EXT2_SYSCALL,
2962 .features[FEAT_8000_0001_ECX] =
2963 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2964 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2965 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2966 CPUID_EXT3_TOPOEXT,
2967 .features[FEAT_8000_0008_EBX] =
2968 CPUID_8000_0008_EBX_IBPB,
2969 .features[FEAT_7_0_EBX] =
2970 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2971 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2972 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2973 /*
2974 * Missing: XSAVES (not supported by some Linux versions,
2975 * including v4.1 to v4.12).
2976 * KVM doesn't yet expose any XSAVES state save component.
2977 */
2978 .features[FEAT_XSAVE] =
2979 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2980 CPUID_XSAVE_XGETBV1,
2981 .features[FEAT_6_EAX] =
2982 CPUID_6_EAX_ARAT,
2983 .features[FEAT_SVM] =
2984 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2985 .xlevel = 0x8000001E,
2986 .model_id = "Hygon Dhyana Processor",
2987 .cache_info = &epyc_cache_info,
2988 },
c6dc6f63
AP		 2989};
2990
5114e842
EH		 2991typedef struct PropValue {
2992 const char *prop, *value;
2993} PropValue;
2994
2995/* KVM-specific features that are automatically added/removed
2996 * from all CPU models when KVM is enabled.
2997 */
2998static PropValue kvm_default_props[] = {
2999 { "kvmclock", "on" },
3000 { "kvm-nopiodelay", "on" },
3001 { "kvm-asyncpf", "on" },
3002 { "kvm-steal-time", "on" },
3003 { "kvm-pv-eoi", "on" },
3004 { "kvmclock-stable-bit", "on" },
3005 { "x2apic", "on" },
3006 { "acpi", "off" },
3007 { "monitor", "off" },
3008 { "svm", "off" },
3009 { NULL, NULL },
3010};
3011
04d99c3c
EH		 3012/* TCG-specific defaults that override all CPU models when using TCG
3013 */
3014static PropValue tcg_default_props[] = {
3015 { "vme", "off" },
3016 { NULL, NULL },
3017};
3018
3019
5114e842
EH		 3020void x86_cpu_change_kvm_default(const char *prop, const char *value)
3021{
3022 PropValue *pv;
3023 for (pv = kvm_default_props; pv->prop; pv++) {
3024 if (!strcmp(pv->prop, prop)) {
3025 pv->value = value;
3026 break;
3027 }
3028 }
3029
3030 /* It is valid to call this function only for properties that
3031 * are already present in the kvm_default_props table.
3032 */
3033 assert(pv->prop);
3034}
3035
4d1b279b
EH		 3036static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3037 bool migratable_only);
3038
40bfe48f
HZ		 3039static bool lmce_supported(void)
3040{
c62f2630 3041 uint64_t mce_cap = 0;
40bfe48f 3042
c62f2630 3043#ifdef CONFIG_KVM
40bfe48f
HZ		 3044 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
3045 return false;
3046 }
c62f2630 3047#endif
40bfe48f
HZ		 3048
3049 return !!(mce_cap & MCG_LMCE_P);
3050}
3051
7d8050b5
EH		 3052#define CPUID_MODEL_ID_SZ 48
3053
3054/**
3055 * cpu_x86_fill_model_id:
3056 * Get CPUID model ID string from host CPU.
3057 *
3058 * @str should have at least CPUID_MODEL_ID_SZ bytes
3059 *
3060 * The function does NOT add a null terminator to the string
3061 * automatically.
3062 */
c6dc6f63
AP		 3063static int cpu_x86_fill_model_id(char *str)
3064{
3065 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3066 int i;
3067
3068 for (i = 0; i < 3; i++) {
3069 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3070 memcpy(str + i * 16 + 0, &eax, 4);
3071 memcpy(str + i * 16 + 4, &ebx, 4);
3072 memcpy(str + i * 16 + 8, &ecx, 4);
3073 memcpy(str + i * 16 + 12, &edx, 4);
3074 }
3075 return 0;
3076}
3077
c62f2630 3078static Property max_x86_cpu_properties[] = {
120eee7d 3079 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 3080 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 3081 DEFINE_PROP_END_OF_LIST()
3082};
3083
c62f2630 3084static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 3085{
84f1b92f 3086 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 3087 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 3088
f48c8837 3089 xcc->ordering = 9;
6e746f30 3090
ee465a3e 3091 xcc->model_description =
c62f2630 3092 "Enables all features supported by the accelerator in the current host";
d940ee9b 3093
c62f2630 3094 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3095}
3096
0bacd8b3
EH		 3097static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3098
c62f2630 3099static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3100{
3101 X86CPU *cpu = X86_CPU(obj);
3102 CPUX86State *env = &cpu->env;
3103 KVMState *s = kvm_state;
d940ee9b 3104
4d1b279b
EH		 3105 /* We can't fill the features array here because we don't know yet if
3106 * "migratable" is true or false.
3107 */
44bd8e53 3108 cpu->max_features = true;
4d1b279b 3109
d6dcc558 3110 if (accel_uses_host_cpuid()) {
bd182022
EH		 3111 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3112 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3113 int family, model, stepping;
d6dcc558
SAGDR		 3114 X86CPUDefinition host_cpudef = { };
3115 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3116
3117 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3118 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3119
bd182022 3120 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3121
bd182022 3122 cpu_x86_fill_model_id(model_id);
0bacd8b3 3123
bd182022
EH		 3124 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3125 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3126 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3127 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3128 &error_abort);
3129 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3130 &error_abort);
0bacd8b3 3131
d6dcc558
SAGDR		 3132 if (kvm_enabled()) {
3133 env->cpuid_min_level =
3134 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3135 env->cpuid_min_xlevel =
3136 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3137 env->cpuid_min_xlevel2 =
3138 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3139 } else {
3140 env->cpuid_min_level =
3141 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3142 env->cpuid_min_xlevel =
3143 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3144 env->cpuid_min_xlevel2 =
3145 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3146 }
40bfe48f
HZ		 3147
3148 if (lmce_supported()) {
3149 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3150 }
6900d1cc
EH		 3151 } else {
3152 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3153 "vendor", &error_abort);
3154 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3155 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3156 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3157 object_property_set_str(OBJECT(cpu),
3158 "QEMU TCG CPU version " QEMU_HW_VERSION,
3159 "model-id", &error_abort);
e4356010 3160 }
2a573259 3161
d940ee9b 3162 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3163}
3164
c62f2630
EH		 3165static const TypeInfo max_x86_cpu_type_info = {
3166 .name = X86_CPU_TYPE_NAME("max"),
3167 .parent = TYPE_X86_CPU,
3168 .instance_init = max_x86_cpu_initfn,
3169 .class_init = max_x86_cpu_class_init,
3170};
3171
d6dcc558 3172#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3173static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3174{
3175 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3176
d6dcc558 3177 xcc->host_cpuid_required = true;
c62f2630
EH		 3178 xcc->ordering = 8;
3179
02693cc4
GK		 3180#if defined(CONFIG_KVM)
3181 xcc->model_description =
3182 "KVM processor with all supported host features ";
3183#elif defined(CONFIG_HVF)
3184 xcc->model_description =
3185 "HVF processor with all supported host features ";
3186#endif
c62f2630
EH		 3187}
3188
d940ee9b
EH		 3189static const TypeInfo host_x86_cpu_type_info = {
3190 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3191 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3192 .class_init = host_x86_cpu_class_init,
3193};
3194
3195#endif
3196
07585923
RH		 3197static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3198{
3199 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3200
3201 switch (f->type) {
3202 case CPUID_FEATURE_WORD:
3203 {
3204 const char *reg = get_register_name_32(f->cpuid.reg);
3205 assert(reg);
3206 return g_strdup_printf("CPUID.%02XH:%s",
3207 f->cpuid.eax, reg);
3208 }
3209 case MSR_FEATURE_WORD:
3210 return g_strdup_printf("MSR(%02XH)",
3211 f->msr.index);
3212 }
3213
3214 return NULL;
3215}
3216
8459e396 3217static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3218{
8459e396 3219 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3220 int i;
07585923 3221 char *feat_word_str;
c6dc6f63 3222
857aee33 3223 for (i = 0; i < 32; ++i) {
72370dc1 3224 if ((1UL << i) & mask) {
07585923
RH		 3225 feat_word_str = feature_word_description(f, i);
3226 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3227 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3228 feat_word_str,
8297be80
AF		 3229 f->feat_names[i] ? "." : "",
3230 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3231 g_free(feat_word_str);
c6dc6f63 3232 }
857aee33 3233 }
c6dc6f63
AP		 3234}
3235
d7bce999
EB		 3236static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3237 const char *name, void *opaque,
3238 Error **errp)
95b8519d
AF		 3239{
3240 X86CPU *cpu = X86_CPU(obj);
3241 CPUX86State *env = &cpu->env;
3242 int64_t value;
3243
3244 value = (env->cpuid_version >> 8) & 0xf;
3245 if (value == 0xf) {
3246 value += (env->cpuid_version >> 20) & 0xff;
3247 }
51e72bc1 3248 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3249}
3250
d7bce999
EB		 3251static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3252 const char *name, void *opaque,
3253 Error **errp)
ed5e1ec3 3254{
71ad61d3
AF		 3255 X86CPU *cpu = X86_CPU(obj);
3256 CPUX86State *env = &cpu->env;
3257 const int64_t min = 0;
3258 const int64_t max = 0xff + 0xf;
65cd9064 3259 Error *local_err = NULL;
71ad61d3
AF		 3260 int64_t value;
3261
51e72bc1 3262 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3263 if (local_err) {
3264 error_propagate(errp, local_err);
71ad61d3
AF		 3265 return;
3266 }
3267 if (value < min || value > max) {
c6bd8c70
MA		 3268 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3269 name ? name : "null", value, min, max);
71ad61d3
AF		 3270 return;
3271 }
3272
ed5e1ec3 3273 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3274 if (value > 0x0f) {
3275 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3276 } else {
71ad61d3 3277 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3278 }
3279}
3280
d7bce999
EB		 3281static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3282 const char *name, void *opaque,
3283 Error **errp)
67e30c83
AF		 3284{
3285 X86CPU *cpu = X86_CPU(obj);
3286 CPUX86State *env = &cpu->env;
3287 int64_t value;
3288
3289 value = (env->cpuid_version >> 4) & 0xf;
3290 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3291 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3292}
3293
d7bce999
EB		 3294static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3295 const char *name, void *opaque,
3296 Error **errp)
b0704cbd 3297{
c5291a4f
AF		 3298 X86CPU *cpu = X86_CPU(obj);
3299 CPUX86State *env = &cpu->env;
3300 const int64_t min = 0;
3301 const int64_t max = 0xff;
65cd9064 3302 Error *local_err = NULL;
c5291a4f
AF		 3303 int64_t value;
3304
51e72bc1 3305 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3306 if (local_err) {
3307 error_propagate(errp, local_err);
c5291a4f
AF		 3308 return;
3309 }
3310 if (value < min || value > max) {
c6bd8c70
MA		 3311 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3312 name ? name : "null", value, min, max);
c5291a4f
AF		 3313 return;
3314 }
3315
b0704cbd 3316 env->cpuid_version &= ~0xf00f0;
c5291a4f 3317 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3318}
3319
35112e41 3320static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3321 const char *name, void *opaque,
35112e41
AF		 3322 Error **errp)
3323{
3324 X86CPU *cpu = X86_CPU(obj);
3325 CPUX86State *env = &cpu->env;
3326 int64_t value;
3327
3328 value = env->cpuid_version & 0xf;
51e72bc1 3329 visit_type_int(v, name, &value, errp);
35112e41
AF		 3330}
3331
036e2222 3332static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3333 const char *name, void *opaque,
036e2222 3334 Error **errp)
38c3dc46 3335{
036e2222
AF		 3336 X86CPU *cpu = X86_CPU(obj);
3337 CPUX86State *env = &cpu->env;
3338 const int64_t min = 0;
3339 const int64_t max = 0xf;
65cd9064 3340 Error *local_err = NULL;
036e2222
AF		 3341 int64_t value;
3342
51e72bc1 3343 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3344 if (local_err) {
3345 error_propagate(errp, local_err);
036e2222
AF		 3346 return;
3347 }
3348 if (value < min || value > max) {
c6bd8c70
MA		 3349 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3350 name ? name : "null", value, min, max);
036e2222
AF		 3351 return;
3352 }
3353
38c3dc46 3354 env->cpuid_version &= ~0xf;
036e2222 3355 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3356}
3357
d480e1af
AF		 3358static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3359{
3360 X86CPU *cpu = X86_CPU(obj);
3361 CPUX86State *env = &cpu->env;
3362 char *value;
d480e1af 3363
e42a92ae 3364 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3365 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3366 env->cpuid_vendor3);
d480e1af
AF		 3367 return value;
3368}
3369
3370static void x86_cpuid_set_vendor(Object *obj, const char *value,
3371 Error **errp)
3372{
3373 X86CPU *cpu = X86_CPU(obj);
3374 CPUX86State *env = &cpu->env;
3375 int i;
3376
9df694ee 3377 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3378 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3379 return;
3380 }
3381
3382 env->cpuid_vendor1 = 0;
3383 env->cpuid_vendor2 = 0;
3384 env->cpuid_vendor3 = 0;
3385 for (i = 0; i < 4; i++) {
3386 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3387 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3388 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3389 }
d480e1af
AF		 3390}
3391
63e886eb
AF		 3392static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3393{
3394 X86CPU *cpu = X86_CPU(obj);
3395 CPUX86State *env = &cpu->env;
3396 char *value;
3397 int i;
3398
3399 value = g_malloc(48 + 1);
3400 for (i = 0; i < 48; i++) {
3401 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3402 }
3403 value[48] = '\0';
3404 return value;
3405}
3406
938d4c25
AF		 3407static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3408 Error **errp)
dcce6675 3409{
938d4c25
AF		 3410 X86CPU *cpu = X86_CPU(obj);
3411 CPUX86State *env = &cpu->env;
dcce6675
AF		 3412 int c, len, i;
3413
3414 if (model_id == NULL) {
3415 model_id = "";
3416 }
3417 len = strlen(model_id);
d0a6acf4 3418 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3419 for (i = 0; i < 48; i++) {
3420 if (i >= len) {
3421 c = '\0';
3422 } else {
3423 c = (uint8_t)model_id[i];
3424 }
3425 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3426 }
3427}
3428
d7bce999
EB		 3429static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3430 void *opaque, Error **errp)
89e48965
AF		 3431{
3432 X86CPU *cpu = X86_CPU(obj);
3433 int64_t value;
3434
3435 value = cpu->env.tsc_khz * 1000;
51e72bc1 3436 visit_type_int(v, name, &value, errp);
89e48965
AF		 3437}
3438
d7bce999
EB		 3439static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3440 void *opaque, Error **errp)
89e48965
AF		 3441{
3442 X86CPU *cpu = X86_CPU(obj);
3443 const int64_t min = 0;
2e84849a 3444 const int64_t max = INT64_MAX;
65cd9064 3445 Error *local_err = NULL;
89e48965
AF		 3446 int64_t value;
3447
51e72bc1 3448 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3449 if (local_err) {
3450 error_propagate(errp, local_err);
89e48965
AF		 3451 return;
3452 }
3453 if (value < min || value > max) {
c6bd8c70
MA		 3454 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3455 name ? name : "null", value, min, max);
89e48965
AF		 3456 return;
3457 }
3458
36f96c4b 3459 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3460}
3461
7e5292b5 3462/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3463static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3464 const char *name, void *opaque,
3465 Error **errp)
8e8aba50 3466{
7e5292b5 3467 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3468 FeatureWord w;
8e8aba50
EH		 3469 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3470 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3471 X86CPUFeatureWordInfoList *list = NULL;
3472
3473 for (w = 0; w < FEATURE_WORDS; w++) {
3474 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3475 /*
3476 * We didn't have MSR features when "feature-words" was
3477 * introduced. Therefore skipped other type entries.
3478 */
3479 if (wi->type != CPUID_FEATURE_WORD) {
3480 continue;
3481 }
8e8aba50 3482 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3483 qwi->cpuid_input_eax = wi->cpuid.eax;
3484 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3485 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3486 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3487 qwi->features = array[w];
8e8aba50
EH		 3488
3489 /* List will be in reverse order, but order shouldn't matter */
3490 list_entries[w].next = list;
3491 list_entries[w].value = &word_infos[w];
3492 list = &list_entries[w];
3493 }
3494
6b62d961 3495 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3496}
3497
d7bce999
EB		 3498static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3499 void *opaque, Error **errp)
c8f0f88e
IM		 3500{
3501 X86CPU *cpu = X86_CPU(obj);
3502 int64_t value = cpu->hyperv_spinlock_attempts;
3503
51e72bc1 3504 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3505}
3506
d7bce999
EB		 3507static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3508 void *opaque, Error **errp)
c8f0f88e
IM		 3509{
3510 const int64_t min = 0xFFF;
3511 const int64_t max = UINT_MAX;
3512 X86CPU *cpu = X86_CPU(obj);
3513 Error *err = NULL;
3514 int64_t value;
3515
51e72bc1 3516 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3517 if (err) {
3518 error_propagate(errp, err);
3519 return;
3520 }
3521
3522 if (value < min || value > max) {
3523 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3524 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3525 object_get_typename(obj), name ? name : "null",
3526 value, min, max);
c8f0f88e
IM		 3527 return;
3528 }
3529 cpu->hyperv_spinlock_attempts = value;
3530}
3531
1b6b7d10 3532static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3533 .name = "int",
3534 .get = x86_get_hv_spinlocks,
3535 .set = x86_set_hv_spinlocks,
3536};
3537
72ac2e87
IM		 3538/* Convert all '_' in a feature string option name to '-', to make feature
3539 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3540 */
3541static inline void feat2prop(char *s)
3542{
3543 while ((s = strchr(s, '_'))) {
3544 *s = '-';
3545 }
3546}
3547
b54c9377
EH		 3548/* Return the feature property name for a feature flag bit */
3549static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3550{
3551 /* XSAVE components are automatically enabled by other features,
3552 * so return the original feature name instead
3553 */
3554 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3555 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3556
3557 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3558 x86_ext_save_areas[comp].bits) {
3559 w = x86_ext_save_areas[comp].feature;
3560 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3561 }
3562 }
3563
3564 assert(bitnr < 32);
3565 assert(w < FEATURE_WORDS);
3566 return feature_word_info[w].feat_names[bitnr];
3567}
3568
dc15c051
IM		 3569/* Compatibily hack to maintain legacy +-feat semantic,
3570 * where +-feat overwrites any feature set by
3571 * feat=on|feat even if the later is parsed after +-feat
3572 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3573 */
2fae0d96 3574static GList *plus_features, *minus_features;
dc15c051 3575
83a00f60
EH		 3576static gint compare_string(gconstpointer a, gconstpointer b)
3577{
3578 return g_strcmp0(a, b);
3579}
3580
8f961357
EH		 3581/* Parse "+feature,-feature,feature=foo" CPU feature string
3582 */
62a48a2a 3583static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3584 Error **errp)
8f961357 3585{
8f961357 3586 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3587 static bool cpu_globals_initialized;
83a00f60 3588 bool ambiguous = false;
62a48a2a
IM		 3589
3590 if (cpu_globals_initialized) {
3591 return;
3592 }
3593 cpu_globals_initialized = true;
8f961357 3594
f6750e95
EH		 3595 if (!features) {
3596 return;
3597 }
3598
3599 for (featurestr = strtok(features, ",");
685479bd 3600 featurestr;
f6750e95
EH		 3601 featurestr = strtok(NULL, ",")) {
3602 const char *name;
3603 const char *val = NULL;
3604 char *eq = NULL;
cf2887c9 3605 char num[32];
62a48a2a 3606 GlobalProperty *prop;
c6dc6f63 3607
f6750e95 3608 /* Compatibility syntax: */
c6dc6f63 3609 if (featurestr[0] == '+') {
2fae0d96
EH		 3610 plus_features = g_list_append(plus_features,
3611 g_strdup(featurestr + 1));
f6750e95 3612 continue;
c6dc6f63 3613 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3614 minus_features = g_list_append(minus_features,
3615 g_strdup(featurestr + 1));
f6750e95
EH		 3616 continue;
3617 }
3618
3619 eq = strchr(featurestr, '=');
3620 if (eq) {
3621 *eq++ = 0;
3622 val = eq;
c6dc6f63 3623 } else {
f6750e95 3624 val = "on";
a91987c2 3625 }
f6750e95
EH		 3626
3627 feat2prop(featurestr);
3628 name = featurestr;
3629
83a00f60 3630 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3631 warn_report("Ambiguous CPU model string. "
3632 "Don't mix both \"+%s\" and \"%s=%s\"",
3633 name, name, val);
83a00f60
EH		 3634 ambiguous = true;
3635 }
3636 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3637 warn_report("Ambiguous CPU model string. "
3638 "Don't mix both \"-%s\" and \"%s=%s\"",
3639 name, name, val);
83a00f60
EH		 3640 ambiguous = true;
3641 }
3642
f6750e95
EH		 3643 /* Special case: */
3644 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3645 int ret;
f46bfdbf 3646 uint64_t tsc_freq;
f6750e95 3647
f17fd4fd 3648 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3649 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3650 error_setg(errp, "bad numerical value %s", val);
3651 return;
3652 }
3653 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3654 val = num;
3655 name = "tsc-frequency";
c6dc6f63 3656 }
f6750e95 3657
62a48a2a
IM		 3658 prop = g_new0(typeof(*prop), 1);
3659 prop->driver = typename;
3660 prop->property = g_strdup(name);
3661 prop->value = g_strdup(val);
62a48a2a 3662 qdev_prop_register_global(prop);
f6750e95
EH		 3663 }
3664
83a00f60 3665 if (ambiguous) {
3dc6f869
AF		 3666 warn_report("Compatibility of ambiguous CPU model "
3667 "strings won't be kept on future QEMU versions");
83a00f60 3668 }
c6dc6f63
AP		 3669}
3670
b8d834a0 3671static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3672static int x86_cpu_filter_features(X86CPU *cpu);
3673
5a853fc5
EH		 3674/* Build a list with the name of all features on a feature word array */
3675static void x86_cpu_list_feature_names(FeatureWordArray features,
3676 strList **feat_names)
3677{
3678 FeatureWord w;
3679 strList **next = feat_names;
3680
3681 for (w = 0; w < FEATURE_WORDS; w++) {
3682 uint32_t filtered = features[w];
3683 int i;
3684 for (i = 0; i < 32; i++) {
3685 if (filtered & (1UL << i)) {
3686 strList *new = g_new0(strList, 1);
3687 new->value = g_strdup(x86_cpu_feature_name(w, i));
3688 *next = new;
3689 next = &new->next;
3690 }
3691 }
3692 }
3693}
3694
b54c9377
EH		 3695/* Check for missing features that may prevent the CPU class from
3696 * running using the current machine and accelerator.
3697 */
3698static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3699 strList **missing_feats)
3700{
3701 X86CPU *xc;
b54c9377
EH		 3702 Error *err = NULL;
3703 strList **next = missing_feats;
3704
d6dcc558 3705 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3706 strList *new = g_new0(strList, 1);
3c254ab8 3707 new->value = g_strdup("kvm");
b54c9377
EH		 3708 *missing_feats = new;
3709 return;
3710 }
3711
3712 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3713
b8d834a0 3714 x86_cpu_expand_features(xc, &err);
b54c9377 3715 if (err) {
b8d834a0 3716 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3717 * but in case it does, just report the model as not
3718 * runnable at all using the "type" property.
3719 */
3720 strList *new = g_new0(strList, 1);
3721 new->value = g_strdup("type");
3722 *next = new;
3723 next = &new->next;
3724 }
3725
3726 x86_cpu_filter_features(xc);
3727
5a853fc5 3728 x86_cpu_list_feature_names(xc->filtered_features, next);
b54c9377
EH		 3729
3730 object_unref(OBJECT(xc));
3731}
3732
8c3329e5 3733/* Print all cpuid feature names in featureset
c6dc6f63 3734 */
0442428a 3735static void listflags(GList *features)
0856579c 3736{
cc643b1e
DB		 3737 size_t len = 0;
3738 GList *tmp;
3739
3740 for (tmp = features; tmp; tmp = tmp->next) {
3741 const char *name = tmp->data;
3742 if ((len + strlen(name) + 1) >= 75) {
0442428a 3743 qemu_printf("\n");
cc643b1e 3744 len = 0;
c6dc6f63 3745 }
0442428a 3746 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 3747 len += strlen(name) + 1;
8c3329e5 3748 }
0442428a 3749 qemu_printf("\n");
c6dc6f63
AP		 3750}
3751
f48c8837 3752/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3753static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3754{
3755 ObjectClass *class_a = (ObjectClass *)a;
3756 ObjectClass *class_b = (ObjectClass *)b;
3757 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3758 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3759 char *name_a, *name_b;
3760 int ret;
ee465a3e 3761
f48c8837 3762 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3763 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3764 } else {
c7dbff4b
DB		 3765 name_a = x86_cpu_class_get_model_name(cc_a);
3766 name_b = x86_cpu_class_get_model_name(cc_b);
3767 ret = strcmp(name_a, name_b);
3768 g_free(name_a);
3769 g_free(name_b);
ee465a3e 3770 }
c7dbff4b 3771 return ret;
ee465a3e
EH		 3772}
3773
3774static GSList *get_sorted_cpu_model_list(void)
3775{
3776 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3777 list = g_slist_sort(list, x86_cpu_list_compare);
3778 return list;
3779}
3780
3781static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3782{
3783 ObjectClass *oc = data;
3784 X86CPUClass *cc = X86_CPU_CLASS(oc);
ee465a3e
EH		 3785 char *name = x86_cpu_class_get_model_name(cc);
3786 const char *desc = cc->model_description;
0bacd8b3 3787 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3788 desc = cc->cpu_def->model_id;
3789 }
3790
0442428a 3791 qemu_printf("x86 %-20s %-48s\n", name, desc);
ee465a3e
EH		 3792 g_free(name);
3793}
3794
3795/* list available CPU models and flags */
0442428a 3796void x86_cpu_list(void)
c6dc6f63 3797{
cc643b1e 3798 int i, j;
ee465a3e 3799 GSList *list;
cc643b1e 3800 GList *names = NULL;
c6dc6f63 3801
0442428a 3802 qemu_printf("Available CPUs:\n");
ee465a3e 3803 list = get_sorted_cpu_model_list();
0442428a 3804 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 3805 g_slist_free(list);
21ad7789 3806
cc643b1e 3807 names = NULL;
3af60be2
JK		 3808 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3809 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3810 for (j = 0; j < 32; j++) {
3811 if (fw->feat_names[j]) {
3812 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3813 }
3814 }
3af60be2 3815 }
cc643b1e
DB		 3816
3817 names = g_list_sort(names, (GCompareFunc)strcmp);
3818
0442428a
MA		 3819 qemu_printf("\nRecognized CPUID flags:\n");
3820 listflags(names);
3821 qemu_printf("\n");
cc643b1e 3822 g_list_free(names);
c6dc6f63
AP		 3823}
3824
ee465a3e
EH		 3825static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3826{
3827 ObjectClass *oc = data;
3828 X86CPUClass *cc = X86_CPU_CLASS(oc);
3829 CpuDefinitionInfoList **cpu_list = user_data;
3830 CpuDefinitionInfoList *entry;
3831 CpuDefinitionInfo *info;
3832
3833 info = g_malloc0(sizeof(*info));
3834 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3835 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3836 info->has_unavailable_features = true;
8ed877b7 3837 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3838 info->migration_safe = cc->migration_safe;
3839 info->has_migration_safe = true;
5adbed30 3840 info->q_static = cc->static_model;
ee465a3e
EH		 3841
3842 entry = g_malloc0(sizeof(*entry));
3843 entry->value = info;
3844 entry->next = *cpu_list;
3845 *cpu_list = entry;
3846}
3847
25a9d6ca 3848CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 3849{
3850 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3851 GSList *list = get_sorted_cpu_model_list();
3852 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3853 g_slist_free(list);
e3966126
AL		 3854 return cpu_list;
3855}
3856
84f1b92f
EH		 3857static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3858 bool migratable_only)
27418adf
EH		 3859{
3860 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3861 uint32_t r = 0;
27418adf 3862
fefb41bf 3863 if (kvm_enabled()) {
07585923
RH		 3864 switch (wi->type) {
3865 case CPUID_FEATURE_WORD:
3866 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3867 wi->cpuid.ecx,
3868 wi->cpuid.reg);
3869 break;
3870 case MSR_FEATURE_WORD:
d86f9636
RH		 3871 r = kvm_arch_get_supported_msr_feature(kvm_state,
3872 wi->msr.index);
07585923
RH		 3873 break;
3874 }
d6dcc558 3875 } else if (hvf_enabled()) {
07585923
RH		 3876 if (wi->type != CPUID_FEATURE_WORD) {
3877 return 0;
3878 }
3879 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3880 wi->cpuid.ecx,
3881 wi->cpuid.reg);
fefb41bf 3882 } else if (tcg_enabled()) {
84f1b92f 3883 r = wi->tcg_features;
fefb41bf
EH		 3884 } else {
3885 return ~0;
3886 }
84f1b92f
EH		 3887 if (migratable_only) {
3888 r &= x86_cpu_get_migratable_flags(w);
3889 }
3890 return r;
27418adf
EH		 3891}
3892
8ca30e86
EH		 3893static void x86_cpu_report_filtered_features(X86CPU *cpu)
3894{
3895 FeatureWord w;
3896
3897 for (w = 0; w < FEATURE_WORDS; w++) {
3898 report_unavailable_features(w, cpu->filtered_features[w]);
3899 }
3900}
3901
5114e842
EH		 3902static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3903{
3904 PropValue *pv;
3905 for (pv = props; pv->prop; pv++) {
3906 if (!pv->value) {
3907 continue;
3908 }
3909 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3910 &error_abort);
3911 }
3912}
3913
f99fd7ca 3914/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3915 */
d940ee9b 3916static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3917{
61dcd775 3918 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3919 const char *vendor;
3920 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3921 FeatureWord w;
c6dc6f63 3922
f99fd7ca
EH		 3923 /*NOTE: any property set by this function should be returned by
3924 * x86_cpu_static_props(), so static expansion of
3925 * query-cpu-model-expansion is always complete.
3926 */
3927
c39c0edf 3928 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3929 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3930 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3931
2d64255b
AF		 3932 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3933 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3934 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3935 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3936 for (w = 0; w < FEATURE_WORDS; w++) {
3937 env->features[w] = def->features[w];
3938 }
82beb536 3939
a9f27ea9
EH		 3940 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3941 cpu->legacy_cache = !def->cache_info;
ab8f992e 3942
9576de75 3943 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3944 /* TODO: in-kernel irqchip for hvf */
82beb536 3945 if (kvm_enabled()) {
492a4c94
LT		 3946 if (!kvm_irqchip_in_kernel()) {
3947 x86_cpu_change_kvm_default("x2apic", "off");
3948 }
3949
5114e842 3950 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3951 } else if (tcg_enabled()) {
3952 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3953 }
5fcca9ff 3954
82beb536 3955 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3956
3957 /* sysenter isn't supported in compatibility mode on AMD,
3958 * syscall isn't supported in compatibility mode on Intel.
3959 * Normally we advertise the actual CPU vendor, but you can
3960 * override this using the 'vendor' property if you want to use
3961 * KVM's sysenter/syscall emulation in compatibility mode and
3962 * when doing cross vendor migration
3963 */
74f54bc4 3964 vendor = def->vendor;
d6dcc558 3965 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3966 uint32_t ebx = 0, ecx = 0, edx = 0;
3967 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3968 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3969 vendor = host_vendor;
3970 }
3971
3972 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3973
c6dc6f63
AP		 3974}
3975
96f75b59 3976#ifndef CONFIG_USER_ONLY
f99fd7ca
EH		 3977/* Return a QDict containing keys for all properties that can be included
3978 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3979 * must be included in the dictionary.
3980 */
3981static QDict *x86_cpu_static_props(void)
3982{
3983 FeatureWord w;
3984 int i;
3985 static const char *props[] = {
3986 "min-level",
3987 "min-xlevel",
3988 "family",
3989 "model",
3990 "stepping",
3991 "model-id",
3992 "vendor",
3993 "lmce",
3994 NULL,
3995 };
3996 static QDict *d;
3997
3998 if (d) {
3999 return d;
4000 }
4001
4002 d = qdict_new();
4003 for (i = 0; props[i]; i++) {
0f9afc2a 4004 qdict_put_null(d, props[i]);
f99fd7ca
EH		 4005 }
4006
4007 for (w = 0; w < FEATURE_WORDS; w++) {
4008 FeatureWordInfo *fi = &feature_word_info[w];
4009 int bit;
4010 for (bit = 0; bit < 32; bit++) {
4011 if (!fi->feat_names[bit]) {
4012 continue;
4013 }
0f9afc2a 4014 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 4015 }
4016 }
4017
4018 return d;
4019}
4020
4021/* Add an entry to @props dict, with the value for property. */
4022static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
4023{
4024 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
4025 &error_abort);
4026
4027 qdict_put_obj(props, prop, value);
4028}
4029
4030/* Convert CPU model data from X86CPU object to a property dictionary
4031 * that can recreate exactly the same CPU model.
4032 */
4033static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
4034{
4035 QDict *sprops = x86_cpu_static_props();
4036 const QDictEntry *e;
4037
4038 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
4039 const char *prop = qdict_entry_key(e);
4040 x86_cpu_expand_prop(cpu, props, prop);
4041 }
4042}
4043
b8097deb
EH		 4044/* Convert CPU model data from X86CPU object to a property dictionary
4045 * that can recreate exactly the same CPU model, including every
4046 * writeable QOM property.
4047 */
4048static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
4049{
4050 ObjectPropertyIterator iter;
4051 ObjectProperty *prop;
4052
4053 object_property_iter_init(&iter, OBJECT(cpu));
4054 while ((prop = object_property_iter_next(&iter))) {
4055 /* skip read-only or write-only properties */
4056 if (!prop->get || !prop->set) {
4057 continue;
4058 }
4059
4060 /* "hotplugged" is the only property that is configurable
4061 * on the command-line but will be set differently on CPUs
4062 * created using "-cpu ... -smp ..." and by CPUs created
4063 * on the fly by x86_cpu_from_model() for querying. Skip it.
4064 */
4065 if (!strcmp(prop->name, "hotplugged")) {
4066 continue;
4067 }
4068 x86_cpu_expand_prop(cpu, props, prop->name);
4069 }
4070}
4071
f99fd7ca
EH		 4072static void object_apply_props(Object *obj, QDict *props, Error **errp)
4073{
4074 const QDictEntry *prop;
4075 Error *err = NULL;
4076
4077 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4078 object_property_set_qobject(obj, qdict_entry_value(prop),
4079 qdict_entry_key(prop), &err);
4080 if (err) {
4081 break;
4082 }
4083 }
4084
4085 error_propagate(errp, err);
4086}
4087
4088/* Create X86CPU object according to model+props specification */
4089static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4090{
4091 X86CPU *xc = NULL;
4092 X86CPUClass *xcc;
4093 Error *err = NULL;
4094
4095 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4096 if (xcc == NULL) {
4097 error_setg(&err, "CPU model '%s' not found", model);
4098 goto out;
4099 }
4100
4101 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4102 if (props) {
4103 object_apply_props(OBJECT(xc), props, &err);
4104 if (err) {
4105 goto out;
4106 }
4107 }
4108
4109 x86_cpu_expand_features(xc, &err);
4110 if (err) {
4111 goto out;
4112 }
4113
4114out:
4115 if (err) {
4116 error_propagate(errp, err);
4117 object_unref(OBJECT(xc));
4118 xc = NULL;
4119 }
4120 return xc;
4121}
4122
4123CpuModelExpansionInfo *
96f75b59 4124qmp_query_cpu_model_expansion(CpuModelExpansionType type,
f99fd7ca
EH		 4125 CpuModelInfo *model,
4126 Error **errp)
4127{
4128 X86CPU *xc = NULL;
4129 Error *err = NULL;
4130 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4131 QDict *props = NULL;
4132 const char *base_name;
4133
4134 xc = x86_cpu_from_model(model->name,
4135 model->has_props ?
7dc847eb 4136 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4137 NULL, &err);
4138 if (err) {
4139 goto out;
4140 }
4141
b8097deb 4142 props = qdict_new();
e38bf612
EH		 4143 ret->model = g_new0(CpuModelInfo, 1);
4144 ret->model->props = QOBJECT(props);
4145 ret->model->has_props = true;
f99fd7ca
EH		 4146
4147 switch (type) {
4148 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4149 /* Static expansion will be based on "base" only */
4150 base_name = "base";
b8097deb 4151 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4152 break;
4153 case CPU_MODEL_EXPANSION_TYPE_FULL:
4154 /* As we don't return every single property, full expansion needs
4155 * to keep the original model name+props, and add extra
4156 * properties on top of that.
4157 */
4158 base_name = model->name;
b8097deb 4159 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4160 break;
4161 default:
df68a7f3 4162 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 4163 goto out;
4164 }
4165
f99fd7ca
EH		 4166 x86_cpu_to_dict(xc, props);
4167
f99fd7ca 4168 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4169
4170out:
4171 object_unref(OBJECT(xc));
4172 if (err) {
4173 error_propagate(errp, err);
4174 qapi_free_CpuModelExpansionInfo(ret);
4175 ret = NULL;
4176 }
4177 return ret;
4178}
96f75b59 4179#endif /* !CONFIG_USER_ONLY */
f99fd7ca 4180
00fcd100
AB		 4181static gchar *x86_gdb_arch_name(CPUState *cs)
4182{
4183#ifdef TARGET_X86_64
4184 return g_strdup("i386:x86-64");
4185#else
4186 return g_strdup("i386");
4187#endif
4188}
4189
d940ee9b
EH		 4190static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4191{
4192 X86CPUDefinition *cpudef = data;
4193 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4194
4195 xcc->cpu_def = cpudef;
bd72159d 4196 xcc->migration_safe = true;
d940ee9b
EH		 4197}
4198
4199static void x86_register_cpudef_type(X86CPUDefinition *def)
4200{
4201 char *typename = x86_cpu_type_name(def->name);
4202 TypeInfo ti = {
4203 .name = typename,
4204 .parent = TYPE_X86_CPU,
4205 .class_init = x86_cpu_cpudef_class_init,
4206 .class_data = def,
4207 };
4208
2a923a29
EH		 4209 /* AMD aliases are handled at runtime based on CPUID vendor, so
4210 * they shouldn't be set on the CPU model table.
4211 */
4212 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4213 /* catch mistakes instead of silently truncating model_id when too long */
4214 assert(def->model_id && strlen(def->model_id) <= 48);
4215
2a923a29 4216
d940ee9b
EH		 4217 type_register(&ti);
4218 g_free(typename);
4219}
4220
c6dc6f63 4221#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4222
0e26b7b8
BS		 4223void cpu_clear_apic_feature(CPUX86State *env)
4224{
0514ef2f 4225 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4226}
4227
c6dc6f63
AP		 4228#endif /* !CONFIG_USER_ONLY */
4229
c6dc6f63
AP		 4230void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4231 uint32_t *eax, uint32_t *ebx,
4232 uint32_t *ecx, uint32_t *edx)
4233{
6aa9e42f
RH		 4234 X86CPU *cpu = env_archcpu(env);
4235 CPUState *cs = env_cpu(env);
14c985cf 4236 uint32_t pkg_offset;
4ed3d478 4237 uint32_t limit;
1ce36bfe 4238 uint32_t signature[3];
a60f24b5 4239
4ed3d478
DB		 4240 /* Calculate & apply limits for different index ranges */
4241 if (index >= 0xC0000000) {
4242 limit = env->cpuid_xlevel2;
4243 } else if (index >= 0x80000000) {
4244 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4245 } else if (index >= 0x40000000) {
4246 limit = 0x40000001;
c6dc6f63 4247 } else {
4ed3d478
DB		 4248 limit = env->cpuid_level;
4249 }
4250
4251 if (index > limit) {
4252 /* Intel documentation states that invalid EAX input will
4253 * return the same information as EAX=cpuid_level
4254 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4255 */
4256 index = env->cpuid_level;
c6dc6f63
AP		 4257 }
4258
4259 switch(index) {
4260 case 0:
4261 *eax = env->cpuid_level;
5eb2f7a4
EH		 4262 *ebx = env->cpuid_vendor1;
4263 *edx = env->cpuid_vendor2;
4264 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4265 break;
4266 case 1:
4267 *eax = env->cpuid_version;
7e72a45c
EH		 4268 *ebx = (cpu->apic_id << 24) |
4269 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4270 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4271 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4272 *ecx |= CPUID_EXT_OSXSAVE;
4273 }
0514ef2f 4274 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4275 if (cs->nr_cores * cs->nr_threads > 1) {
4276 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4277 *edx |= CPUID_HT;
c6dc6f63
AP		 4278 }
4279 break;
4280 case 2:
4281 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4282 if (cpu->cache_info_passthrough) {
4283 host_cpuid(index, 0, eax, ebx, ecx, edx);
4284 break;
4285 }
5e891bf8 4286 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4287 *ebx = 0;
14c985cf
LM		 4288 if (!cpu->enable_l3_cache) {
4289 *ecx = 0;
4290 } else {
a9f27ea9 4291 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4292 }
a9f27ea9
EH		 4293 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4294 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4295 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4296 break;
4297 case 4:
4298 /* cache info: needed for Core compatibility */
787aaf57
BC		 4299 if (cpu->cache_info_passthrough) {
4300 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4301 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4302 *eax &= ~0xFC000000;
7e3482f8
EH		 4303 if ((*eax & 31) && cs->nr_cores > 1) {
4304 *eax |= (cs->nr_cores - 1) << 26;
4305 }
c6dc6f63 4306 } else {
2f7a21c4 4307 *eax = 0;
76c2975a 4308 switch (count) {
c6dc6f63 4309 case 0: /* L1 dcache info */
a9f27ea9
EH		 4310 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4311 1, cs->nr_cores,
7e3482f8 4312 eax, ebx, ecx, edx);
c6dc6f63
AP		 4313 break;
4314 case 1: /* L1 icache info */
a9f27ea9
EH		 4315 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4316 1, cs->nr_cores,
7e3482f8 4317 eax, ebx, ecx, edx);
c6dc6f63
AP		 4318 break;
4319 case 2: /* L2 cache info */
a9f27ea9
EH		 4320 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4321 cs->nr_threads, cs->nr_cores,
7e3482f8 4322 eax, ebx, ecx, edx);
c6dc6f63 4323 break;
14c985cf 4324 case 3: /* L3 cache info */
7e3482f8
EH		 4325 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4326 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4327 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4328 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4329 eax, ebx, ecx, edx);
14c985cf
LM		 4330 break;
4331 }
7e3482f8 4332 /* fall through */
c6dc6f63 4333 default: /* end of info */
7e3482f8 4334 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4335 break;
76c2975a
PB		 4336 }
4337 }
c6dc6f63
AP		 4338 break;
4339 case 5:
2266d443
MT		 4340 /* MONITOR/MWAIT Leaf */
4341 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4342 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4343 *ecx = cpu->mwait.ecx; /* flags */
4344 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4345 break;
4346 case 6:
4347 /* Thermal and Power Leaf */
28b8e4d0 4348 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4349 *ebx = 0;
4350 *ecx = 0;
4351 *edx = 0;
4352 break;
f7911686 4353 case 7:
13526728
EH		 4354 /* Structured Extended Feature Flags Enumeration Leaf */
4355 if (count == 0) {
4356 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4357 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4358 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4359 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4360 *ecx |= CPUID_7_0_ECX_OSPKE;
4361 }
95ea69fb 4362 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4363 } else {
4364 *eax = 0;
4365 *ebx = 0;
4366 *ecx = 0;
4367 *edx = 0;
4368 }
4369 break;
c6dc6f63
AP		 4370 case 9:
4371 /* Direct Cache Access Information Leaf */
4372 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4373 *ebx = 0;
4374 *ecx = 0;
4375 *edx = 0;
4376 break;
4377 case 0xA:
4378 /* Architectural Performance Monitoring Leaf */
9337e3b6 4379 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4380 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4381
4382 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4383 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4384 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4385 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4386 } else if (hvf_enabled() && cpu->enable_pmu) {
4387 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4388 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4389 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4390 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4391 } else {
4392 *eax = 0;
4393 *ebx = 0;
4394 *ecx = 0;
4395 *edx = 0;
4396 }
c6dc6f63 4397 break;
5232d00a
RK		 4398 case 0xB:
4399 /* Extended Topology Enumeration Leaf */
4400 if (!cpu->enable_cpuid_0xb) {
4401 *eax = *ebx = *ecx = *edx = 0;
4402 break;
4403 }
4404
4405 *ecx = count & 0xff;
4406 *edx = cpu->apic_id;
4407
4408 switch (count) {
4409 case 0:
eab60fb9
MAL		 4410 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4411 *ebx = cs->nr_threads;
5232d00a
RK		 4412 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4413 break;
4414 case 1:
eab60fb9
MAL		 4415 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4416 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4417 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4418 break;
4419 default:
4420 *eax = 0;
4421 *ebx = 0;
4422 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4423 }
4424
4425 assert(!(*eax & ~0x1f));
4426 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4427 break;
2560f19f 4428 case 0xD: {
51e49430 4429 /* Processor Extended State */
2560f19f
PB		 4430 *eax = 0;
4431 *ebx = 0;
4432 *ecx = 0;
4433 *edx = 0;
19dc85db 4434 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4435 break;
4436 }
4928cd6d 4437
2560f19f 4438 if (count == 0) {
96193c22
EH		 4439 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4440 *eax = env->features[FEAT_XSAVE_COMP_LO];
4441 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4442 *ebx = xsave_area_size(env->xcr0);
2560f19f 4443 } else if (count == 1) {
0bb0b2d2 4444 *eax = env->features[FEAT_XSAVE];
f4f1110e 4445 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4446 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4447 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4448 *eax = esa->size;
4449 *ebx = esa->offset;
2560f19f 4450 }
51e49430
SY		 4451 }
4452 break;
2560f19f 4453 }
e37a5c7f
CP		 4454 case 0x14: {
4455 /* Intel Processor Trace Enumeration */
4456 *eax = 0;
4457 *ebx = 0;
4458 *ecx = 0;
4459 *edx = 0;
4460 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4461 !kvm_enabled()) {
4462 break;
4463 }
4464
4465 if (count == 0) {
4466 *eax = INTEL_PT_MAX_SUBLEAF;
4467 *ebx = INTEL_PT_MINIMAL_EBX;
4468 *ecx = INTEL_PT_MINIMAL_ECX;
4469 } else if (count == 1) {
4470 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4471 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4472 }
4473 break;
4474 }
1ce36bfe
DB		 4475 case 0x40000000:
4476 /*
4477 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4478 * set here, but we restrict to TCG none the less.
4479 */
4480 if (tcg_enabled() && cpu->expose_tcg) {
4481 memcpy(signature, "TCGTCGTCGTCG", 12);
4482 *eax = 0x40000001;
4483 *ebx = signature[0];
4484 *ecx = signature[1];
4485 *edx = signature[2];
4486 } else {
4487 *eax = 0;
4488 *ebx = 0;
4489 *ecx = 0;
4490 *edx = 0;
4491 }
4492 break;
4493 case 0x40000001:
4494 *eax = 0;
4495 *ebx = 0;
4496 *ecx = 0;
4497 *edx = 0;
4498 break;
c6dc6f63
AP		 4499 case 0x80000000:
4500 *eax = env->cpuid_xlevel;
4501 *ebx = env->cpuid_vendor1;
4502 *edx = env->cpuid_vendor2;
4503 *ecx = env->cpuid_vendor3;
4504 break;
4505 case 0x80000001:
4506 *eax = env->cpuid_version;
4507 *ebx = 0;
0514ef2f
EH		 4508 *ecx = env->features[FEAT_8000_0001_ECX];
4509 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4510
4511 /* The Linux kernel checks for the CMPLegacy bit and
4512 * discards multiple thread information if it is set.
cb8d4c8f 4513 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4514 */
ce3960eb 4515 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4516 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4517 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4518 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4519 *ecx |= 1 << 1; /* CmpLegacy bit */
4520 }
4521 }
c6dc6f63
AP		 4522 break;
4523 case 0x80000002:
4524 case 0x80000003:
4525 case 0x80000004:
4526 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4527 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4528 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4529 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4530 break;
4531 case 0x80000005:
4532 /* cache info (L1 cache) */
787aaf57
BC		 4533 if (cpu->cache_info_passthrough) {
4534 host_cpuid(index, 0, eax, ebx, ecx, edx);
4535 break;
4536 }
5e891bf8
EH		 4537 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4538 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4539 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4540 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4541 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4542 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4543 break;
4544 case 0x80000006:
4545 /* cache info (L2 cache) */
787aaf57
BC		 4546 if (cpu->cache_info_passthrough) {
4547 host_cpuid(index, 0, eax, ebx, ecx, edx);
4548 break;
4549 }
5e891bf8
EH		 4550 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4551 (L2_DTLB_2M_ENTRIES << 16) | \
4552 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4553 (L2_ITLB_2M_ENTRIES);
4554 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4555 (L2_DTLB_4K_ENTRIES << 16) | \
4556 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4557 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4558 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4559 cpu->enable_l3_cache ?
4560 env->cache_info_amd.l3_cache : NULL,
4561 ecx, edx);
c6dc6f63 4562 break;
303752a9
MT		 4563 case 0x80000007:
4564 *eax = 0;
4565 *ebx = 0;
4566 *ecx = 0;
4567 *edx = env->features[FEAT_8000_0007_EDX];
4568 break;
c6dc6f63
AP		 4569 case 0x80000008:
4570 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4571 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4572 /* 64 bit processor */
4573 *eax = cpu->phys_bits; /* configurable physical bits */
4574 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4575 *eax |= 0x00003900; /* 57 bits virtual */
4576 } else {
4577 *eax |= 0x00003000; /* 48 bits virtual */
4578 }
c6dc6f63 4579 } else {
af45907a 4580 *eax = cpu->phys_bits;
c6dc6f63 4581 }
1b3420e1 4582 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4583 *ecx = 0;
4584 *edx = 0;
ce3960eb
AF		 4585 if (cs->nr_cores * cs->nr_threads > 1) {
4586 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4587 }
4588 break;
4589 case 0x8000000A:
0514ef2f 4590 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4591 *eax = 0x00000001; /* SVM Revision */
4592 *ebx = 0x00000010; /* nr of ASIDs */
4593 *ecx = 0;
0514ef2f 4594 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4595 } else {
4596 *eax = 0;
4597 *ebx = 0;
4598 *ecx = 0;
4599 *edx = 0;
4600 }
c6dc6f63 4601 break;
8f4202fb
BM		 4602 case 0x8000001D:
4603 *eax = 0;
a4e0b436
SL		 4604 if (cpu->cache_info_passthrough) {
4605 host_cpuid(index, count, eax, ebx, ecx, edx);
4606 break;
4607 }
8f4202fb
BM		 4608 switch (count) {
4609 case 0: /* L1 dcache info */
4610 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4611 eax, ebx, ecx, edx);
4612 break;
4613 case 1: /* L1 icache info */
4614 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4615 eax, ebx, ecx, edx);
4616 break;
4617 case 2: /* L2 cache info */
4618 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4619 eax, ebx, ecx, edx);
4620 break;
4621 case 3: /* L3 cache info */
4622 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4623 eax, ebx, ecx, edx);
4624 break;
4625 default: /* end of info */
4626 *eax = *ebx = *ecx = *edx = 0;
4627 break;
4628 }
4629 break;
ed78467a
BM		 4630 case 0x8000001E:
4631 assert(cpu->core_id <= 255);
4632 encode_topo_cpuid8000001e(cs, cpu,
4633 eax, ebx, ecx, edx);
4634 break;
b3baa152
BW		 4635 case 0xC0000000:
4636 *eax = env->cpuid_xlevel2;
4637 *ebx = 0;
4638 *ecx = 0;
4639 *edx = 0;
4640 break;
4641 case 0xC0000001:
4642 /* Support for VIA CPU's CPUID instruction */
4643 *eax = env->cpuid_version;
4644 *ebx = 0;
4645 *ecx = 0;
0514ef2f 4646 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4647 break;
4648 case 0xC0000002:
4649 case 0xC0000003:
4650 case 0xC0000004:
4651 /* Reserved for the future, and now filled with zero */
4652 *eax = 0;
4653 *ebx = 0;
4654 *ecx = 0;
4655 *edx = 0;
4656 break;
6cb8f2a6
BS		 4657 case 0x8000001F:
4658 *eax = sev_enabled() ? 0x2 : 0;
4659 *ebx = sev_get_cbit_position();
4660 *ebx |= sev_get_reduced_phys_bits() << 6;
4661 *ecx = 0;
4662 *edx = 0;
4663 break;
c6dc6f63
AP		 4664 default:
4665 /* reserved values: zero */
4666 *eax = 0;
4667 *ebx = 0;
4668 *ecx = 0;
4669 *edx = 0;
4670 break;
4671 }
4672}
5fd2087a
AF		 4673
4674/* CPUClass::reset() */
4675static void x86_cpu_reset(CPUState *s)
4676{
4677 X86CPU *cpu = X86_CPU(s);
4678 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4679 CPUX86State *env = &cpu->env;
a114d25d
RH		 4680 target_ulong cr4;
4681 uint64_t xcr0;
c1958aea
AF		 4682 int i;
4683
5fd2087a
AF		 4684 xcc->parent_reset(s);
4685
5e992a8e 4686 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4687
c1958aea
AF		 4688 env->old_exception = -1;
4689
4690 /* init to reset state */
4691
c1958aea
AF		 4692 env->hflags2 |= HF2_GIF_MASK;
4693
4694 cpu_x86_update_cr0(env, 0x60000010);
4695 env->a20_mask = ~0x0;
4696 env->smbase = 0x30000;
e13713db 4697 env->msr_smi_count = 0;
c1958aea
AF		 4698
4699 env->idt.limit = 0xffff;
4700 env->gdt.limit = 0xffff;
4701 env->ldt.limit = 0xffff;
4702 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4703 env->tr.limit = 0xffff;
4704 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4705
4706 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4707 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4708 DESC_R_MASK | DESC_A_MASK);
4709 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4710 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4711 DESC_A_MASK);
4712 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4713 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4714 DESC_A_MASK);
4715 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4716 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4717 DESC_A_MASK);
4718 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4719 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4720 DESC_A_MASK);
4721 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4722 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4723 DESC_A_MASK);
4724
4725 env->eip = 0xfff0;
4726 env->regs[R_EDX] = env->cpuid_version;
4727
4728 env->eflags = 0x2;
4729
4730 /* FPU init */
4731 for (i = 0; i < 8; i++) {
4732 env->fptags[i] = 1;
4733 }
5bde1407 4734 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4735
4736 env->mxcsr = 0x1f80;
a114d25d
RH		 4737 /* All units are in INIT state. */
4738 env->xstate_bv = 0;
c1958aea
AF		 4739
4740 env->pat = 0x0007040600070406ULL;
4741 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 4742 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
4743 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
4744 }
c1958aea
AF		 4745
4746 memset(env->dr, 0, sizeof(env->dr));
4747 env->dr[6] = DR6_FIXED_1;
4748 env->dr[7] = DR7_FIXED_1;
b3310ab3 4749 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4750 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4751
a114d25d 4752 cr4 = 0;
cfc3b074 4753 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4754
4755#ifdef CONFIG_USER_ONLY
4756 /* Enable all the features for user-mode. */
4757 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4758 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4759 }
0f70ed47
PB		 4760 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4761 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4762 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4763 xcr0 |= 1ull << i;
4764 }
a114d25d 4765 }
0f70ed47 4766
a114d25d
RH		 4767 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4768 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4769 }
07929f2a
RH		 4770 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4771 cr4 |= CR4_FSGSBASE_MASK;
4772 }
a114d25d
RH		 4773#endif
4774
4775 env->xcr0 = xcr0;
4776 cpu_x86_update_cr4(env, cr4);
0522604b 4777
9db2efd9
AW		 4778 /*
4779 * SDM 11.11.5 requires:
4780 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4781 * - IA32_MTRR_PHYSMASKn.V = 0
4782 * All other bits are undefined. For simplification, zero it all.
4783 */
4784 env->mtrr_deftype = 0;
4785 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4786 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4787
b7394c83
SAGDR		 4788 env->interrupt_injected = -1;
4789 env->exception_injected = -1;
4790 env->nmi_injected = false;
dd673288
IM		 4791#if !defined(CONFIG_USER_ONLY)
4792 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4793 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4794
259186a7 4795 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4796
4797 if (kvm_enabled()) {
4798 kvm_arch_reset_vcpu(cpu);
4799 }
d6dcc558
SAGDR		 4800 else if (hvf_enabled()) {
4801 hvf_reset_vcpu(s);
4802 }
dd673288 4803#endif
5fd2087a
AF		 4804}
4805
dd673288
IM		 4806#ifndef CONFIG_USER_ONLY
4807bool cpu_is_bsp(X86CPU *cpu)
4808{
02e51483 4809 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4810}
65dee380
IM		 4811
4812/* TODO: remove me, when reset over QOM tree is implemented */
4813static void x86_cpu_machine_reset_cb(void *opaque)
4814{
4815 X86CPU *cpu = opaque;
4816 cpu_reset(CPU(cpu));
4817}
dd673288
IM		 4818#endif
4819
de024815
AF		 4820static void mce_init(X86CPU *cpu)
4821{
4822 CPUX86State *cenv = &cpu->env;
4823 unsigned int bank;
4824
4825 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4826 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4827 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4828 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4829 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4830 cenv->mcg_ctl = ~(uint64_t)0;
4831 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4832 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4833 }
4834 }
4835}
4836
bdeec802 4837#ifndef CONFIG_USER_ONLY
2f114315 4838APICCommonClass *apic_get_class(void)
bdeec802 4839{
bdeec802
IM		 4840 const char *apic_type = "apic";
4841
d6dcc558 4842 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4843 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4844 apic_type = "kvm-apic";
4845 } else if (xen_enabled()) {
4846 apic_type = "xen-apic";
4847 }
4848
2f114315
RK		 4849 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4850}
4851
4852static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4853{
4854 APICCommonState *apic;
4855 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4856
4857 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4858
6816b1b3
IM		 4859 object_property_add_child(OBJECT(cpu), "lapic",
4860 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4861 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4862
33d7a288 4863 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4864 /* TODO: convert to link<> */
02e51483 4865 apic = APIC_COMMON(cpu->apic_state);
60671e58 4866 apic->cpu = cpu;
8d42d2d3 4867 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4868}
4869
4870static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4871{
8d42d2d3
CF		 4872 APICCommonState *apic;
4873 static bool apic_mmio_map_once;
4874
02e51483 4875 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4876 return;
4877 }
6e8e2651
MA		 4878 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4879 errp);
8d42d2d3
CF		 4880
4881 /* Map APIC MMIO area */
4882 apic = APIC_COMMON(cpu->apic_state);
4883 if (!apic_mmio_map_once) {
4884 memory_region_add_subregion_overlap(get_system_memory(),
4885 apic->apicbase &
4886 MSR_IA32_APICBASE_BASE,
4887 &apic->io_memory,
4888 0x1000);
4889 apic_mmio_map_once = true;
4890 }
bdeec802 4891}
f809c605
PB		 4892
4893static void x86_cpu_machine_done(Notifier *n, void *unused)
4894{
4895 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4896 MemoryRegion *smram =
4897 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4898
4899 if (smram) {
4900 cpu->smram = g_new(MemoryRegion, 1);
4901 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4902 smram, 0, 1ull << 32);
f8c45c65 4903 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4904 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4905 }
4906}
d3c64d6a
IM		 4907#else
4908static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4909{
4910}
bdeec802
IM		 4911#endif
4912
11f6fee5
DDAG		 4913/* Note: Only safe for use on x86(-64) hosts */
4914static uint32_t x86_host_phys_bits(void)
4915{
4916 uint32_t eax;
4917 uint32_t host_phys_bits;
4918
4919 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4920 if (eax >= 0x80000008) {
4921 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4922 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4923 * at 23:16 that can specify a maximum physical address bits for
4924 * the guest that can override this value; but I've not seen
4925 * anything with that set.
4926 */
4927 host_phys_bits = eax & 0xff;
4928 } else {
4929 /* It's an odd 64 bit machine that doesn't have the leaf for
4930 * physical address bits; fall back to 36 that's most older
4931 * Intel.
4932 */
4933 host_phys_bits = 36;
4934 }
4935
4936 return host_phys_bits;
4937}
e48638fd 4938
c39c0edf
EH		 4939static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4940{
4941 if (*min < value) {
4942 *min = value;
4943 }
4944}
4945
4946/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4947static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4948{
4949 CPUX86State *env = &cpu->env;
4950 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4951 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4952 uint32_t region = eax & 0xF0000000;
4953
07585923 4954 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4955 if (!env->features[w]) {
4956 return;
4957 }
4958
4959 switch (region) {
4960 case 0x00000000:
4961 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4962 break;
4963 case 0x80000000:
4964 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4965 break;
4966 case 0xC0000000:
4967 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4968 break;
4969 }
4970}
4971
2ca8a8be
EH		 4972/* Calculate XSAVE components based on the configured CPU feature flags */
4973static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4974{
4975 CPUX86State *env = &cpu->env;
4976 int i;
96193c22 4977 uint64_t mask;
2ca8a8be
EH		 4978
4979 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4980 return;
4981 }
4982
e3c9022b
EH		 4983 mask = 0;
4984 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4985 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4986 if (env->features[esa->feature] & esa->bits) {
96193c22 4987 mask |= (1ULL << i);
2ca8a8be
EH		 4988 }
4989 }
4990
96193c22
EH		 4991 env->features[FEAT_XSAVE_COMP_LO] = mask;
4992 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4993}
4994
b8d834a0
EH		 4995/***** Steps involved on loading and filtering CPUID data
4996 *
4997 * When initializing and realizing a CPU object, the steps
4998 * involved in setting up CPUID data are:
4999 *
5000 * 1) Loading CPU model definition (X86CPUDefinition). This is
5001 * implemented by x86_cpu_load_def() and should be completely
5002 * transparent, as it is done automatically by instance_init.
5003 * No code should need to look at X86CPUDefinition structs
5004 * outside instance_init.
5005 *
5006 * 2) CPU expansion. This is done by realize before CPUID
5007 * filtering, and will make sure host/accelerator data is
5008 * loaded for CPU models that depend on host capabilities
5009 * (e.g. "host"). Done by x86_cpu_expand_features().
5010 *
5011 * 3) CPUID filtering. This initializes extra data related to
5012 * CPUID, and checks if the host supports all capabilities
5013 * required by the CPU. Runnability of a CPU model is
5014 * determined at this step. Done by x86_cpu_filter_features().
5015 *
5016 * Some operations don't require all steps to be performed.
5017 * More precisely:
5018 *
5019 * - CPU instance creation (instance_init) will run only CPU
5020 * model loading. CPU expansion can't run at instance_init-time
5021 * because host/accelerator data may be not available yet.
5022 * - CPU realization will perform both CPU model expansion and CPUID
5023 * filtering, and return an error in case one of them fails.
5024 * - query-cpu-definitions needs to run all 3 steps. It needs
5025 * to run CPUID filtering, as the 'unavailable-features'
5026 * field is set based on the filtering results.
5027 * - The query-cpu-model-expansion QMP command only needs to run
5028 * CPU model loading and CPU expansion. It should not filter
5029 * any CPUID data based on host capabilities.
5030 */
5031
5032/* Expand CPU configuration data, based on configured features
5033 * and host/accelerator capabilities when appropriate.
5034 */
5035static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 5036{
b34d12d1 5037 CPUX86State *env = &cpu->env;
dc15c051 5038 FeatureWord w;
2fae0d96 5039 GList *l;
41f3d4d6 5040 Error *local_err = NULL;
9886e834 5041
d4a606b3
EH		 5042 /*TODO: Now cpu->max_features doesn't overwrite features
5043 * set using QOM properties, and we can convert
dc15c051
IM		 5044 * plus_features & minus_features to global properties
5045 * inside x86_cpu_parse_featurestr() too.
5046 */
44bd8e53 5047 if (cpu->max_features) {
dc15c051 5048 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 5049 /* Override only features that weren't set explicitly
5050 * by the user.
5051 */
5052 env->features[w] |=
5053 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 5054 ~env->user_features[w] & \
5055 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 5056 }
5057 }
5058
2fae0d96
EH		 5059 for (l = plus_features; l; l = l->next) {
5060 const char *prop = l->data;
5061 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5062 if (local_err) {
5063 goto out;
5064 }
5065 }
5066
5067 for (l = minus_features; l; l = l->next) {
5068 const char *prop = l->data;
5069 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5070 if (local_err) {
5071 goto out;
5072 }
dc15c051
IM		 5073 }
5074
aec661de
EH		 5075 if (!kvm_enabled() || !cpu->expose_kvm) {
5076 env->features[FEAT_KVM] = 0;
5077 }
5078
2ca8a8be 5079 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5080
5081 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5082 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5083 if (cpu->full_cpuid_auto_level) {
5084 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5085 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5086 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5087 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5088 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5089 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5090 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5091 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5092 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5093 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5094 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 5095
5096 /* Intel Processor Trace requires CPUID[0x14] */
5097 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5098 kvm_enabled() && cpu->intel_pt_auto_level) {
5099 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5100 }
5101
0c3d7c00
EH		 5102 /* SVM requires CPUID[0x8000000A] */
5103 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5104 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5105 }
6cb8f2a6
BS		 5106
5107 /* SEV requires CPUID[0x8000001F] */
5108 if (sev_enabled()) {
5109 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5110 }
c39c0edf
EH		 5111 }
5112
5113 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5114 if (env->cpuid_level == UINT32_MAX) {
5115 env->cpuid_level = env->cpuid_min_level;
5116 }
5117 if (env->cpuid_xlevel == UINT32_MAX) {
5118 env->cpuid_xlevel = env->cpuid_min_xlevel;
5119 }
5120 if (env->cpuid_xlevel2 == UINT32_MAX) {
5121 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5122 }
7a059953 5123
41f3d4d6
EH		 5124out:
5125 if (local_err != NULL) {
5126 error_propagate(errp, local_err);
5127 }
5128}
5129
b8d834a0
EH		 5130/*
5131 * Finishes initialization of CPUID data, filters CPU feature
5132 * words based on host availability of each feature.
5133 *
5134 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5135 */
5136static int x86_cpu_filter_features(X86CPU *cpu)
5137{
5138 CPUX86State *env = &cpu->env;
5139 FeatureWord w;
5140 int rv = 0;
5141
5142 for (w = 0; w < FEATURE_WORDS; w++) {
5143 uint32_t host_feat =
5144 x86_cpu_get_supported_feature_word(w, false);
5145 uint32_t requested_features = env->features[w];
5146 env->features[w] &= host_feat;
5147 cpu->filtered_features[w] = requested_features & ~env->features[w];
5148 if (cpu->filtered_features[w]) {
5149 rv = 1;
5150 }
5151 }
5152
e37a5c7f
CP		 5153 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5154 kvm_enabled()) {
5155 KVMState *s = CPU(cpu)->kvm_state;
5156 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5157 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5158 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5159 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5160 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5161
5162 if (!eax_0 ||
5163 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5164 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5165 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5166 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5167 INTEL_PT_ADDR_RANGES_NUM) ||
5168 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5169 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5170 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5171 /*
5172 * Processor Trace capabilities aren't configurable, so if the
5173 * host can't emulate the capabilities we report on
5174 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5175 */
5176 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5177 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5178 rv = 1;
5179 }
5180 }
5181
b8d834a0
EH		 5182 return rv;
5183}
5184
41f3d4d6
EH		 5185#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5186 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5187 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5188#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5189 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5190 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5191static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5192{
5193 CPUState *cs = CPU(dev);
5194 X86CPU *cpu = X86_CPU(dev);
5195 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5196 CPUX86State *env = &cpu->env;
5197 Error *local_err = NULL;
5198 static bool ht_warned;
5199
2266d443
MT		 5200 if (xcc->host_cpuid_required) {
5201 if (!accel_uses_host_cpuid()) {
5202 char *name = x86_cpu_class_get_model_name(xcc);
5203 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5204 g_free(name);
5205 goto out;
5206 }
5207
5208 if (enable_cpu_pm) {
5209 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5210 &cpu->mwait.ecx, &cpu->mwait.edx);
5211 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5212 }
41f3d4d6
EH		 5213 }
5214
2266d443
MT		 5215 /* mwait extended info: needed for Core compatibility */
5216 /* We always wake on interrupt even if host does not have the capability */
5217 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5218
41f3d4d6
EH		 5219 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5220 error_setg(errp, "apic-id property was not initialized properly");
5221 return;
5222 }
5223
b8d834a0 5224 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5225 if (local_err) {
5226 goto out;
5227 }
5228
8ca30e86
EH		 5229 if (x86_cpu_filter_features(cpu) &&
5230 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5231 x86_cpu_report_filtered_features(cpu);
5232 if (cpu->enforce_cpuid) {
5233 error_setg(&local_err,
d6dcc558 5234 accel_uses_host_cpuid() ?
8ca30e86
EH		 5235 "Host doesn't support requested features" :
5236 "TCG doesn't support requested features");
5237 goto out;
5238 }
9997cf7b
EH		 5239 }
5240
9b15cd9e
IM		 5241 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5242 * CPUID[1].EDX.
5243 */
e48638fd 5244 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5245 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5246 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5247 & CPUID_EXT2_AMD_ALIASES);
5248 }
5249
11f6fee5
DDAG		 5250 /* For 64bit systems think about the number of physical bits to present.
5251 * ideally this should be the same as the host; anything other than matching
5252 * the host can cause incorrect guest behaviour.
5253 * QEMU used to pick the magic value of 40 bits that corresponds to
5254 * consumer AMD devices but nothing else.
5255 */
af45907a 5256 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5257 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5258 uint32_t host_phys_bits = x86_host_phys_bits();
5259 static bool warned;
5260
5261 if (cpu->host_phys_bits) {
5262 /* The user asked for us to use the host physical bits */
5263 cpu->phys_bits = host_phys_bits;
258fe08b
EH		 5264 if (cpu->host_phys_bits_limit &&
5265 cpu->phys_bits > cpu->host_phys_bits_limit) {
5266 cpu->phys_bits = cpu->host_phys_bits_limit;
5267 }
11f6fee5
DDAG		 5268 }
5269
5270 /* Print a warning if the user set it to a value that's not the
5271 * host value.
5272 */
5273 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5274 !warned) {
3dc6f869
AF		 5275 warn_report("Host physical bits (%u)"
5276 " does not match phys-bits property (%u)",
5277 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5278 warned = true;
5279 }
5280
5281 if (cpu->phys_bits &&
5282 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5283 cpu->phys_bits < 32)) {
af45907a
DDAG		 5284 error_setg(errp, "phys-bits should be between 32 and %u "
5285 " (but is %u)",
5286 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5287 return;
5288 }
5289 } else {
11f6fee5 5290 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5291 error_setg(errp, "TCG only supports phys-bits=%u",
5292 TCG_PHYS_ADDR_BITS);
5293 return;
5294 }
5295 }
11f6fee5
DDAG		 5296 /* 0 means it was not explicitly set by the user (or by machine
5297 * compat_props or by the host code above). In this case, the default
5298 * is the value used by TCG (40).
5299 */
5300 if (cpu->phys_bits == 0) {
5301 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5302 }
af45907a
DDAG		 5303 } else {
5304 /* For 32 bit systems don't use the user set value, but keep
5305 * phys_bits consistent with what we tell the guest.
5306 */
5307 if (cpu->phys_bits != 0) {
5308 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5309 return;
5310 }
fefb41bf 5311
af45907a
DDAG		 5312 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5313 cpu->phys_bits = 36;
5314 } else {
5315 cpu->phys_bits = 32;
5316 }
5317 }
a9f27ea9
EH		 5318
5319 /* Cache information initialization */
5320 if (!cpu->legacy_cache) {
5321 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5322 char *name = x86_cpu_class_get_model_name(xcc);
5323 error_setg(errp,
5324 "CPU model '%s' doesn't support legacy-cache=off", name);
5325 g_free(name);
5326 return;
5327 }
5328 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5329 *xcc->cpu_def->cache_info;
5330 } else {
5331 /* Build legacy cache information */
5332 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5333 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5334 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5335 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5336
5337 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5338 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5339 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5340 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5341
5342 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5343 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5344 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5345 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5346 }
5347
5348
ce5b1bbf
LV		 5349 cpu_exec_realizefn(cs, &local_err);
5350 if (local_err != NULL) {
5351 error_propagate(errp, local_err);
5352 return;
5353 }
42ecabaa 5354
65dee380
IM		 5355#ifndef CONFIG_USER_ONLY
5356 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5357
0514ef2f 5358 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5359 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5360 if (local_err != NULL) {
4dc1f449 5361 goto out;
bdeec802
IM		 5362 }
5363 }
65dee380
IM		 5364#endif
5365
7a059953 5366 mce_init(cpu);
2001d0cd
PB		 5367
5368#ifndef CONFIG_USER_ONLY
5369 if (tcg_enabled()) {
f809c605 5370 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5371 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5372
5373 /* Outer container... */
5374 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5375 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5376
5377 /* ... with two regions inside: normal system memory with low
5378 * priority, and...
5379 */
5380 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5381 get_system_memory(), 0, ~0ull);
5382 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5383 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5384
5385 cs->num_ases = 2;
80ceb07a
PX		 5386 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5387 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5388
5389 /* ... SMRAM with higher priority, linked from /machine/smram. */
5390 cpu->machine_done.notify = x86_cpu_machine_done;
5391 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5392 }
5393#endif
5394
14a10fc3 5395 qemu_init_vcpu(cs);
d3c64d6a 5396
6b2942f9
BM		 5397 /*
5398 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5399 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5400 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5401 * users a warning.
5402 *
5403 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5404 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5405 */
0765691e
MA		 5406 if (IS_AMD_CPU(env) &&
5407 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5408 cs->nr_threads > 1 && !ht_warned) {
5409 warn_report("This family of AMD CPU doesn't support "
5410 "hyperthreading(%d)",
5411 cs->nr_threads);
5412 error_printf("Please configure -smp options properly"
5413 " or try enabling topoext feature.\n");
5414 ht_warned = true;
e48638fd
WH		 5415 }
5416
d3c64d6a
IM		 5417 x86_cpu_apic_realize(cpu, &local_err);
5418 if (local_err != NULL) {
5419 goto out;
5420 }
14a10fc3 5421 cpu_reset(cs);
2b6f294c 5422
4dc1f449 5423 xcc->parent_realize(dev, &local_err);
2001d0cd 5424
4dc1f449
IM		 5425out:
5426 if (local_err != NULL) {
5427 error_propagate(errp, local_err);
5428 return;
5429 }
7a059953
AF		 5430}
5431
c884776e
IM		 5432static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5433{
5434 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5435 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5436 Error *local_err = NULL;
c884776e
IM		 5437
5438#ifndef CONFIG_USER_ONLY
5439 cpu_remove_sync(CPU(dev));
5440 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5441#endif
5442
5443 if (cpu->apic_state) {
5444 object_unparent(OBJECT(cpu->apic_state));
5445 cpu->apic_state = NULL;
5446 }
7bbc124e
LV		 5447
5448 xcc->parent_unrealize(dev, &local_err);
5449 if (local_err != NULL) {
5450 error_propagate(errp, local_err);
5451 return;
5452 }
c884776e
IM		 5453}
5454
38e5c119 5455typedef struct BitProperty {
a7b0ffac 5456 FeatureWord w;
38e5c119
EH		 5457 uint32_t mask;
5458} BitProperty;
5459
d7bce999
EB		 5460static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5461 void *opaque, Error **errp)
38e5c119 5462{
a7b0ffac 5463 X86CPU *cpu = X86_CPU(obj);
38e5c119 5464 BitProperty *fp = opaque;
a7b0ffac
EH		 5465 uint32_t f = cpu->env.features[fp->w];
5466 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5467 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5468}
5469
d7bce999
EB		 5470static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5471 void *opaque, Error **errp)
38e5c119
EH		 5472{
5473 DeviceState *dev = DEVICE(obj);
a7b0ffac 5474 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5475 BitProperty *fp = opaque;
5476 Error *local_err = NULL;
5477 bool value;
5478
5479 if (dev->realized) {
5480 qdev_prop_set_after_realize(dev, name, errp);
5481 return;
5482 }
5483
51e72bc1 5484 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5485 if (local_err) {
5486 error_propagate(errp, local_err);
5487 return;
5488 }
5489
5490 if (value) {
a7b0ffac 5491 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5492 } else {
a7b0ffac 5493 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5494 }
d4a606b3 5495 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5496}
5497
5498static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5499 void *opaque)
5500{
5501 BitProperty *prop = opaque;
5502 g_free(prop);
5503}
5504
5505/* Register a boolean property to get/set a single bit in a uint32_t field.
5506 *
5507 * The same property name can be registered multiple times to make it affect
5508 * multiple bits in the same FeatureWord. In that case, the getter will return
5509 * true only if all bits are set.
5510 */
5511static void x86_cpu_register_bit_prop(X86CPU *cpu,
5512 const char *prop_name,
a7b0ffac 5513 FeatureWord w,
38e5c119
EH		 5514 int bitnr)
5515{
5516 BitProperty *fp;
5517 ObjectProperty *op;
5518 uint32_t mask = (1UL << bitnr);
5519
5520 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5521 if (op) {
5522 fp = op->opaque;
a7b0ffac 5523 assert(fp->w == w);
38e5c119
EH		 5524 fp->mask |= mask;
5525 } else {
5526 fp = g_new0(BitProperty, 1);
a7b0ffac 5527 fp->w = w;
38e5c119
EH		 5528 fp->mask = mask;
5529 object_property_add(OBJECT(cpu), prop_name, "bool",
5530 x86_cpu_get_bit_prop,
5531 x86_cpu_set_bit_prop,
5532 x86_cpu_release_bit_prop, fp, &error_abort);
5533 }
5534}
5535
5536static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5537 FeatureWord w,
5538 int bitnr)
5539{
38e5c119 5540 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5541 const char *name = fi->feat_names[bitnr];
38e5c119 5542
16d2fcaa 5543 if (!name) {
38e5c119
EH		 5544 return;
5545 }
5546
fc7dfd20
EH		 5547 /* Property names should use "-" instead of "_".
5548 * Old names containing underscores are registered as aliases
5549 * using object_property_add_alias()
5550 */
16d2fcaa
EH		 5551 assert(!strchr(name, '_'));
5552 /* aliases don't use "|" delimiters anymore, they are registered
5553 * manually using object_property_add_alias() */
5554 assert(!strchr(name, '|'));
a7b0ffac 5555 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5556}
5557
d187e08d
AN		 5558static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5559{
5560 X86CPU *cpu = X86_CPU(cs);
5561 CPUX86State *env = &cpu->env;
5562 GuestPanicInformation *panic_info = NULL;
5563
5e953812 5564 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5565 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5566
e8ed97a6 5567 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5568
5e953812 5569 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5570 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5571 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5572 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5573 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5574 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5575 }
5576
5577 return panic_info;
5578}
5579static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5580 const char *name, void *opaque,
5581 Error **errp)
5582{
5583 CPUState *cs = CPU(obj);
5584 GuestPanicInformation *panic_info;
5585
5586 if (!cs->crash_occurred) {
5587 error_setg(errp, "No crash occured");
5588 return;
5589 }
5590
5591 panic_info = x86_cpu_get_crash_info(cs);
5592 if (panic_info == NULL) {
5593 error_setg(errp, "No crash information");
5594 return;
5595 }
5596
5597 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5598 errp);
5599 qapi_free_GuestPanicInformation(panic_info);
5600}
5601
de024815
AF		 5602static void x86_cpu_initfn(Object *obj)
5603{
5604 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5605 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5606 CPUX86State *env = &cpu->env;
38e5c119 5607 FeatureWord w;
de024815 5608
7506ed90 5609 cpu_set_cpustate_pointers(cpu);
71ad61d3
AF		 5610
5611 object_property_add(obj, "family", "int",
95b8519d 5612 x86_cpuid_version_get_family,
71ad61d3 5613 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5614 object_property_add(obj, "model", "int",
67e30c83 5615 x86_cpuid_version_get_model,
c5291a4f 5616 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5617 object_property_add(obj, "stepping", "int",
35112e41 5618 x86_cpuid_version_get_stepping,
036e2222 5619 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5620 object_property_add_str(obj, "vendor",
5621 x86_cpuid_get_vendor,
5622 x86_cpuid_set_vendor, NULL);
938d4c25 5623 object_property_add_str(obj, "model-id",
63e886eb 5624 x86_cpuid_get_model_id,
938d4c25 5625 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5626 object_property_add(obj, "tsc-frequency", "int",
5627 x86_cpuid_get_tsc_freq,
5628 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5629 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5630 x86_cpu_get_feature_words,
7e5292b5
EH		 5631 NULL, NULL, (void *)env->features, NULL);
5632 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5633 x86_cpu_get_feature_words,
5634 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5635
d187e08d
AN		 5636 object_property_add(obj, "crash-information", "GuestPanicInformation",
5637 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5638
92067bf4 5639 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5640
38e5c119
EH		 5641 for (w = 0; w < FEATURE_WORDS; w++) {
5642 int bitnr;
5643
5644 for (bitnr = 0; bitnr < 32; bitnr++) {
5645 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5646 }
5647 }
5648
16d2fcaa
EH		 5649 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5650 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5651 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5652 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5653 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5654 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5655 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5656
54b8dc7c
EH		 5657 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5658 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5659 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5660 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5661 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5662 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5663 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5664 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5665 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5666 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5667 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5668 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5669 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5670 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5671 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5672 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5673 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5674 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5675 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5676 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5677 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5678
0bacd8b3
EH		 5679 if (xcc->cpu_def) {
5680 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5681 }
de024815
AF		 5682}
5683
997395d3
IM		 5684static int64_t x86_cpu_get_arch_id(CPUState *cs)
5685{
5686 X86CPU *cpu = X86_CPU(cs);
997395d3 5687
7e72a45c 5688 return cpu->apic_id;
997395d3
IM		 5689}
5690
444d5590
AF		 5691static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5692{
5693 X86CPU *cpu = X86_CPU(cs);
5694
5695 return cpu->env.cr[0] & CR0_PG_MASK;
5696}
5697
f45748f1
AF		 5698static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5699{
5700 X86CPU *cpu = X86_CPU(cs);
5701
5702 cpu->env.eip = value;
5703}
5704
bdf7ae5b
AF		 5705static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5706{
5707 X86CPU *cpu = X86_CPU(cs);
5708
5709 cpu->env.eip = tb->pc - tb->cs_base;
5710}
5711
92d5f1a4 5712int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5713{
5714 X86CPU *cpu = X86_CPU(cs);
5715 CPUX86State *env = &cpu->env;
5716
92d5f1a4
PB		 5717#if !defined(CONFIG_USER_ONLY)
5718 if (interrupt_request & CPU_INTERRUPT_POLL) {
5719 return CPU_INTERRUPT_POLL;
5720 }
5721#endif
5722 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5723 return CPU_INTERRUPT_SIPI;
5724 }
5725
5726 if (env->hflags2 & HF2_GIF_MASK) {
5727 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5728 !(env->hflags & HF_SMM_MASK)) {
5729 return CPU_INTERRUPT_SMI;
5730 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5731 !(env->hflags2 & HF2_NMI_MASK)) {
5732 return CPU_INTERRUPT_NMI;
5733 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5734 return CPU_INTERRUPT_MCE;
5735 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5736 (((env->hflags2 & HF2_VINTR_MASK) &&
5737 (env->hflags2 & HF2_HIF_MASK)) ||
5738 (!(env->hflags2 & HF2_VINTR_MASK) &&
5739 (env->eflags & IF_MASK &&
5740 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5741 return CPU_INTERRUPT_HARD;
5742#if !defined(CONFIG_USER_ONLY)
5743 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5744 (env->eflags & IF_MASK) &&
5745 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5746 return CPU_INTERRUPT_VIRQ;
5747#endif
5748 }
5749 }
5750
5751 return 0;
5752}
5753
5754static bool x86_cpu_has_work(CPUState *cs)
5755{
5756 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5757}
5758
f50f3dd5
RH		 5759static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5760{
5761 X86CPU *cpu = X86_CPU(cs);
5762 CPUX86State *env = &cpu->env;
5763
5764 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5765 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5766 : bfd_mach_i386_i8086);
5767 info->print_insn = print_insn_i386;
b666d2a4
RH		 5768
5769 info->cap_arch = CS_ARCH_X86;
5770 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5771 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5772 : CS_MODE_16);
15fa1a0a
RH		 5773 info->cap_insn_unit = 1;
5774 info->cap_insn_split = 8;
f50f3dd5
RH		 5775}
5776
35b1b927
TW		 5777void x86_update_hflags(CPUX86State *env)
5778{
5779 uint32_t hflags;
5780#define HFLAG_COPY_MASK \
5781 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5782 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5783 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5784 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5785
5786 hflags = env->hflags & HFLAG_COPY_MASK;
5787 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5788 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5789 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5790 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5791 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5792
5793 if (env->cr[4] & CR4_OSFXSR_MASK) {
5794 hflags |= HF_OSFXSR_MASK;
5795 }
5796
5797 if (env->efer & MSR_EFER_LMA) {
5798 hflags |= HF_LMA_MASK;
5799 }
5800
5801 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5802 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5803 } else {
5804 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5805 (DESC_B_SHIFT - HF_CS32_SHIFT);
5806 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5807 (DESC_B_SHIFT - HF_SS32_SHIFT);
5808 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5809 !(hflags & HF_CS32_MASK)) {
5810 hflags |= HF_ADDSEG_MASK;
5811 } else {
5812 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5813 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5814 }
5815 }
5816 env->hflags = hflags;
5817}
5818
9337e3b6 5819static Property x86_cpu_properties[] = {
2da00e31
IM		 5820#ifdef CONFIG_USER_ONLY
5821 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5822 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5823 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5824 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5825 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5826#else
5827 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5828 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5829 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5830 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5831#endif
15f8b142 5832 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5833 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5834 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5835 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5836 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5837 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5838 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5839 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5840 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5841 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5842 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5843 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5844 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5845 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5846 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
e204ac61 5847 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
6b7a9830 5848 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5849 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5850 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5851 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5852 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5853 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 5854 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 5855 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5856 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5857 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5858 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5859 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5860 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5861 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5862 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5863 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5864 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5865 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5866 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5867 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5868 false),
0b564e6f 5869 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5870 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5871 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5872 true),
ab8f992e 5873 /*
a9f27ea9
EH		 5874 * lecacy_cache defaults to true unless the CPU model provides its
5875 * own cache information (see x86_cpu_load_def()).
ab8f992e 5876 */
a9f27ea9 5877 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5878
5879 /*
5880 * From "Requirements for Implementing the Microsoft
5881 * Hypervisor Interface":
5882 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5883 *
5884 * "Starting with Windows Server 2012 and Windows 8, if
5885 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5886 * the hypervisor imposes no specific limit to the number of VPs.
5887 * In this case, Windows Server 2012 guest VMs may use more than
5888 * 64 VPs, up to the maximum supported number of processors applicable
5889 * to the specific Windows version being used."
5890 */
5891 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5892 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5893 false),
f24c3a79
LK		 5894 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5895 true),
9337e3b6
EH		 5896 DEFINE_PROP_END_OF_LIST()
5897};
5898
5fd2087a
AF		 5899static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5900{
5901 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5902 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5903 DeviceClass *dc = DEVICE_CLASS(oc);
5904
bf853881
PMD		 5905 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5906 &xcc->parent_realize);
5907 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5908 &xcc->parent_unrealize);
9337e3b6 5909 dc->props = x86_cpu_properties;
5fd2087a
AF		 5910
5911 xcc->parent_reset = cc->reset;
5912 cc->reset = x86_cpu_reset;
91b1df8c 5913 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5914
500050d1 5915 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5916 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5917 cc->has_work = x86_cpu_has_work;
79c664f6 5918#ifdef CONFIG_TCG
97a8ea5a 5919 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5920 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5921#endif
878096ee 5922 cc->dump_state = x86_cpu_dump_state;
c86f106b 5923 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5924 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5925 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5926 cc->gdb_read_register = x86_cpu_gdb_read_register;
5927 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5928 cc->get_arch_id = x86_cpu_get_arch_id;
5929 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5d004421 5930#ifndef CONFIG_USER_ONLY
f8c45c65 5931 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5932 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5933 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5934 cc->write_elf64_note = x86_cpu_write_elf64_note;
5935 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5936 cc->write_elf32_note = x86_cpu_write_elf32_note;
5937 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5938 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5939#endif
00fcd100
AB		 5940 cc->gdb_arch_name = x86_gdb_arch_name;
5941#ifdef TARGET_X86_64
b8158192 5942 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 5943 cc->gdb_num_core_regs = 66;
00fcd100 5944#else
b8158192 5945 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 5946 cc->gdb_num_core_regs = 50;
00fcd100 5947#endif
79c664f6 5948#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5949 cc->debug_excp_handler = breakpoint_handler;
5950#endif
374e0cd4
RH		 5951 cc->cpu_exec_enter = x86_cpu_exec_enter;
5952 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5953#ifdef CONFIG_TCG
55c3ceef 5954 cc->tcg_initialize = tcg_x86_init;
5d004421 5955 cc->tlb_fill = x86_cpu_tlb_fill;
74d7fc7f 5956#endif
f50f3dd5 5957 cc->disas_set_info = x86_disas_set_info;
4c315c27 5958
e90f2a8c 5959 dc->user_creatable = true;
5fd2087a
AF		 5960}
5961
5962static const TypeInfo x86_cpu_type_info = {
5963 .name = TYPE_X86_CPU,
5964 .parent = TYPE_CPU,
5965 .instance_size = sizeof(X86CPU),
de024815 5966 .instance_init = x86_cpu_initfn,
d940ee9b 5967 .abstract = true,
5fd2087a
AF		 5968 .class_size = sizeof(X86CPUClass),
5969 .class_init = x86_cpu_common_class_init,
5970};
5971
5adbed30
EH		 5972
5973/* "base" CPU model, used by query-cpu-model-expansion */
5974static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5975{
5976 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5977
5978 xcc->static_model = true;
5979 xcc->migration_safe = true;
5980 xcc->model_description = "base CPU model type with no features enabled";
5981 xcc->ordering = 8;
5982}
5983
5984static const TypeInfo x86_base_cpu_type_info = {
5985 .name = X86_CPU_TYPE_NAME("base"),
5986 .parent = TYPE_X86_CPU,
5987 .class_init = x86_cpu_base_class_init,
5988};
5989
5fd2087a
AF		 5990static void x86_cpu_register_types(void)
5991{
d940ee9b
EH		 5992 int i;
5993
5fd2087a 5994 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5995 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5996 x86_register_cpudef_type(&builtin_x86_defs[i]);
5997 }
c62f2630 5998 type_register_static(&max_x86_cpu_type_info);
5adbed30 5999 type_register_static(&x86_base_cpu_type_info);
d6dcc558 6000#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 6001 type_register_static(&host_x86_cpu_type_info);
6002#endif
5fd2087a
AF		 6003}
6004
6005type_init(x86_cpu_register_types)
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