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Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
0442428a 24#include "qemu/qemu-print.h"
c6dc6f63
AP		 25
26#include "cpu.h"
63c91552 27#include "exec/exec-all.h"
9c17d615 28#include "sysemu/kvm.h"
d6dcc558 29#include "sysemu/hvf.h"
8932cfdf 30#include "sysemu/cpus.h"
50a2c6e5 31#include "kvm_i386.h"
6cb8f2a6 32#include "sev_i386.h"
c6dc6f63 33
d49b6836 34#include "qemu/error-report.h"
1de7afc9
PB		 35#include "qemu/option.h"
36#include "qemu/config-file.h"
e688df6b 37#include "qapi/error.h"
112ed241
MA		 38#include "qapi/qapi-visit-misc.h"
39#include "qapi/qapi-visit-run-state.h"
452fcdbc 40#include "qapi/qmp/qdict.h"
7b1b5d19 41#include "qapi/qmp/qerror.h"
7b1b5d19 42#include "qapi/visitor.h"
f99fd7ca 43#include "qom/qom-qobject.h"
9c17d615 44#include "sysemu/arch_init.h"
96f75b59 45#include "qapi/qapi-commands-target.h"
71ad61d3 46
1814eab6 47#include "standard-headers/asm-x86/kvm_para.h"
65dee380 48
9c17d615 49#include "sysemu/sysemu.h"
53a89e26 50#include "hw/qdev-properties.h"
5232d00a 51#include "hw/i386/topology.h"
bdeec802 52#ifndef CONFIG_USER_ONLY
2001d0cd 53#include "exec/address-spaces.h"
741da0d3 54#include "hw/hw.h"
0d09e41a 55#include "hw/xen/xen.h"
0d09e41a 56#include "hw/i386/apic_internal.h"
bdeec802
IM		 57#endif
58
b666d2a4
RH		 59#include "disas/capstone.h"
60
7e3482f8
EH		 61/* Helpers for building CPUID[2] descriptors: */
62
63struct CPUID2CacheDescriptorInfo {
64 enum CacheType type;
65 int level;
66 int size;
67 int line_size;
68 int associativity;
69};
5e891bf8 70
7e3482f8
EH		 71/*
72 * Known CPUID 2 cache descriptors.
73 * From Intel SDM Volume 2A, CPUID instruction
74 */
75struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 76 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 32, },
5f00335a 78 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 79 .associativity = 4, .line_size = 32, },
5f00335a 80 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 81 .associativity = 4, .line_size = 64, },
5f00335a 82 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 83 .associativity = 2, .line_size = 32, },
5f00335a 84 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 85 .associativity = 4, .line_size = 32, },
5f00335a 86 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 87 .associativity = 4, .line_size = 64, },
5f00335a 88 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 89 .associativity = 6, .line_size = 64, },
5f00335a 90 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 91 .associativity = 2, .line_size = 64, },
5f00335a 92 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 93 .associativity = 8, .line_size = 64, },
94 /* lines per sector is not supported cpuid2_cache_descriptor(),
95 * so descriptors 0x22, 0x23 are not included
96 */
5f00335a 97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 98 .associativity = 16, .line_size = 64, },
99 /* lines per sector is not supported cpuid2_cache_descriptor(),
100 * so descriptors 0x25, 0x20 are not included
101 */
5f00335a 102 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 103 .associativity = 8, .line_size = 64, },
5f00335a 104 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 105 .associativity = 8, .line_size = 64, },
5f00335a 106 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 107 .associativity = 4, .line_size = 32, },
5f00335a 108 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 109 .associativity = 4, .line_size = 32, },
5f00335a 110 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 111 .associativity = 4, .line_size = 32, },
5f00335a 112 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 113 .associativity = 4, .line_size = 32, },
5f00335a 114 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 115 .associativity = 4, .line_size = 32, },
5f00335a 116 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 117 .associativity = 4, .line_size = 64, },
5f00335a 118 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 119 .associativity = 8, .line_size = 64, },
5f00335a 120 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 121 .associativity = 12, .line_size = 64, },
122 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 123 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 124 .associativity = 12, .line_size = 64, },
5f00335a 125 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 126 .associativity = 16, .line_size = 64, },
5f00335a 127 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 128 .associativity = 12, .line_size = 64, },
5f00335a 129 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 130 .associativity = 16, .line_size = 64, },
5f00335a 131 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 132 .associativity = 24, .line_size = 64, },
5f00335a 133 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 134 .associativity = 8, .line_size = 64, },
5f00335a 135 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 136 .associativity = 4, .line_size = 64, },
5f00335a 137 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 138 .associativity = 4, .line_size = 64, },
5f00335a 139 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 140 .associativity = 4, .line_size = 64, },
5f00335a 141 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 142 .associativity = 4, .line_size = 64, },
143 /* lines per sector is not supported cpuid2_cache_descriptor(),
144 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
145 */
5f00335a 146 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 147 .associativity = 8, .line_size = 64, },
5f00335a 148 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 149 .associativity = 2, .line_size = 64, },
5f00335a 150 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 8, .line_size = 64, },
5f00335a 152 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 153 .associativity = 8, .line_size = 32, },
5f00335a 154 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 155 .associativity = 8, .line_size = 32, },
5f00335a 156 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 32, },
5f00335a 158 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 8, .line_size = 32, },
5f00335a 160 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 161 .associativity = 4, .line_size = 64, },
5f00335a 162 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 163 .associativity = 8, .line_size = 64, },
5f00335a 164 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 165 .associativity = 4, .line_size = 64, },
5f00335a 166 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 167 .associativity = 4, .line_size = 64, },
5f00335a 168 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 169 .associativity = 4, .line_size = 64, },
5f00335a 170 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 171 .associativity = 8, .line_size = 64, },
5f00335a 172 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 173 .associativity = 8, .line_size = 64, },
5f00335a 174 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 175 .associativity = 8, .line_size = 64, },
5f00335a 176 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 177 .associativity = 12, .line_size = 64, },
5f00335a 178 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 179 .associativity = 12, .line_size = 64, },
5f00335a 180 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 181 .associativity = 12, .line_size = 64, },
5f00335a 182 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 183 .associativity = 16, .line_size = 64, },
5f00335a 184 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 185 .associativity = 16, .line_size = 64, },
5f00335a 186 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 187 .associativity = 16, .line_size = 64, },
5f00335a 188 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 189 .associativity = 24, .line_size = 64, },
5f00335a 190 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 191 .associativity = 24, .line_size = 64, },
5f00335a 192 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 193 .associativity = 24, .line_size = 64, },
194};
195
196/*
197 * "CPUID leaf 2 does not report cache descriptor information,
198 * use CPUID leaf 4 to query cache parameters"
199 */
200#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 201
7e3482f8
EH		 202/*
203 * Return a CPUID 2 cache descriptor for a given cache.
204 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
205 */
206static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
207{
208 int i;
209
210 assert(cache->size > 0);
211 assert(cache->level > 0);
212 assert(cache->line_size > 0);
213 assert(cache->associativity > 0);
214 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
215 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
216 if (d->level == cache->level && d->type == cache->type &&
217 d->size == cache->size && d->line_size == cache->line_size &&
218 d->associativity == cache->associativity) {
219 return i;
220 }
221 }
5e891bf8 222
7e3482f8
EH		 223 return CACHE_DESCRIPTOR_UNAVAILABLE;
224}
5e891bf8
EH		 225
226/* CPUID Leaf 4 constants: */
227
228/* EAX: */
7e3482f8
EH		 229#define CACHE_TYPE_D 1
230#define CACHE_TYPE_I 2
231#define CACHE_TYPE_UNIFIED 3
5e891bf8 232
7e3482f8 233#define CACHE_LEVEL(l) (l << 5)
5e891bf8 234
7e3482f8 235#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 236
237/* EDX: */
7e3482f8
EH		 238#define CACHE_NO_INVD_SHARING (1 << 0)
239#define CACHE_INCLUSIVE (1 << 1)
240#define CACHE_COMPLEX_IDX (1 << 2)
241
242/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 243#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
244 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
245 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
246 0 /* Invalid value */)
7e3482f8
EH		 247
248
249/* Encode cache info for CPUID[4] */
250static void encode_cache_cpuid4(CPUCacheInfo *cache,
251 int num_apic_ids, int num_cores,
252 uint32_t *eax, uint32_t *ebx,
253 uint32_t *ecx, uint32_t *edx)
254{
255 assert(cache->size == cache->line_size * cache->associativity *
256 cache->partitions * cache->sets);
257
258 assert(num_apic_ids > 0);
259 *eax = CACHE_TYPE(cache->type) |
260 CACHE_LEVEL(cache->level) |
261 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
262 ((num_cores - 1) << 26) |
263 ((num_apic_ids - 1) << 14);
264
265 assert(cache->line_size > 0);
266 assert(cache->partitions > 0);
267 assert(cache->associativity > 0);
268 /* We don't implement fully-associative caches */
269 assert(cache->associativity < cache->sets);
270 *ebx = (cache->line_size - 1) |
271 ((cache->partitions - 1) << 12) |
272 ((cache->associativity - 1) << 22);
273
274 assert(cache->sets > 0);
275 *ecx = cache->sets - 1;
276
277 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
278 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
279 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
280}
281
282/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
283static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
284{
285 assert(cache->size % 1024 == 0);
286 assert(cache->lines_per_tag > 0);
287 assert(cache->associativity > 0);
288 assert(cache->line_size > 0);
289 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
290 (cache->lines_per_tag << 8) | (cache->line_size);
291}
5e891bf8
EH		 292
293#define ASSOC_FULL 0xFF
294
295/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
296#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
297 a == 2 ? 0x2 : \
298 a == 4 ? 0x4 : \
299 a == 8 ? 0x6 : \
300 a == 16 ? 0x8 : \
301 a == 32 ? 0xA : \
302 a == 48 ? 0xB : \
303 a == 64 ? 0xC : \
304 a == 96 ? 0xD : \
305 a == 128 ? 0xE : \
306 a == ASSOC_FULL ? 0xF : \
307 0 /* invalid value */)
308
7e3482f8
EH		 309/*
310 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
311 * @l3 can be NULL.
312 */
313static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
314 CPUCacheInfo *l3,
315 uint32_t *ecx, uint32_t *edx)
316{
317 assert(l2->size % 1024 == 0);
318 assert(l2->associativity > 0);
319 assert(l2->lines_per_tag > 0);
320 assert(l2->line_size > 0);
321 *ecx = ((l2->size / 1024) << 16) |
322 (AMD_ENC_ASSOC(l2->associativity) << 12) |
323 (l2->lines_per_tag << 8) | (l2->line_size);
324
325 if (l3) {
326 assert(l3->size % (512 * 1024) == 0);
327 assert(l3->associativity > 0);
328 assert(l3->lines_per_tag > 0);
329 assert(l3->line_size > 0);
330 *edx = ((l3->size / (512 * 1024)) << 18) |
331 (AMD_ENC_ASSOC(l3->associativity) << 12) |
332 (l3->lines_per_tag << 8) | (l3->line_size);
333 } else {
334 *edx = 0;
335 }
336}
5e891bf8 337
8f4202fb
BM		 338/*
339 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
340 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
341 * Define the constants to build the cpu topology. Right now, TOPOEXT
342 * feature is enabled only on EPYC. So, these constants are based on
343 * EPYC supported configurations. We may need to handle the cases if
344 * these values change in future.
345 */
346/* Maximum core complexes in a node */
347#define MAX_CCX 2
348/* Maximum cores in a core complex */
349#define MAX_CORES_IN_CCX 4
350/* Maximum cores in a node */
351#define MAX_CORES_IN_NODE 8
352/* Maximum nodes in a socket */
353#define MAX_NODES_PER_SOCKET 4
354
355/*
356 * Figure out the number of nodes required to build this config.
357 * Max cores in a node is 8
358 */
359static int nodes_in_socket(int nr_cores)
360{
361 int nodes;
362
363 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
364
365 /* Hardware does not support config with 3 nodes, return 4 in that case */
366 return (nodes == 3) ? 4 : nodes;
367}
368
369/*
370 * Decide the number of cores in a core complex with the given nr_cores using
371 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
372 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
373 * L3 cache is shared across all cores in a core complex. So, this will also
374 * tell us how many cores are sharing the L3 cache.
375 */
376static int cores_in_core_complex(int nr_cores)
377{
378 int nodes;
379
380 /* Check if we can fit all the cores in one core complex */
381 if (nr_cores <= MAX_CORES_IN_CCX) {
382 return nr_cores;
383 }
384 /* Get the number of nodes required to build this config */
385 nodes = nodes_in_socket(nr_cores);
386
387 /*
388 * Divide the cores accros all the core complexes
389 * Return rounded up value
390 */
391 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
392}
393
394/* Encode cache info for CPUID[8000001D] */
395static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
396 uint32_t *eax, uint32_t *ebx,
397 uint32_t *ecx, uint32_t *edx)
398{
399 uint32_t l3_cores;
400 assert(cache->size == cache->line_size * cache->associativity *
401 cache->partitions * cache->sets);
402
403 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
404 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
405
406 /* L3 is shared among multiple cores */
407 if (cache->level == 3) {
408 l3_cores = cores_in_core_complex(cs->nr_cores);
409 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
410 } else {
411 *eax |= ((cs->nr_threads - 1) << 14);
412 }
413
414 assert(cache->line_size > 0);
415 assert(cache->partitions > 0);
416 assert(cache->associativity > 0);
417 /* We don't implement fully-associative caches */
418 assert(cache->associativity < cache->sets);
419 *ebx = (cache->line_size - 1) |
420 ((cache->partitions - 1) << 12) |
421 ((cache->associativity - 1) << 22);
422
423 assert(cache->sets > 0);
424 *ecx = cache->sets - 1;
425
426 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
427 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
428 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
429}
430
ed78467a
BM		 431/* Data structure to hold the configuration info for a given core index */
432struct core_topology {
433 /* core complex id of the current core index */
434 int ccx_id;
435 /*
436 * Adjusted core index for this core in the topology
437 * This can be 0,1,2,3 with max 4 cores in a core complex
438 */
439 int core_id;
440 /* Node id for this core index */
441 int node_id;
442 /* Number of nodes in this config */
443 int num_nodes;
444};
445
446/*
447 * Build the configuration closely match the EPYC hardware. Using the EPYC
448 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
449 * right now. This could change in future.
450 * nr_cores : Total number of cores in the config
451 * core_id : Core index of the current CPU
452 * topo : Data structure to hold all the config info for this core index
453 */
454static void build_core_topology(int nr_cores, int core_id,
455 struct core_topology *topo)
456{
457 int nodes, cores_in_ccx;
458
459 /* First get the number of nodes required */
460 nodes = nodes_in_socket(nr_cores);
461
462 cores_in_ccx = cores_in_core_complex(nr_cores);
463
464 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
465 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
466 topo->core_id = core_id % cores_in_ccx;
467 topo->num_nodes = nodes;
468}
469
470/* Encode cache info for CPUID[8000001E] */
471static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
472 uint32_t *eax, uint32_t *ebx,
473 uint32_t *ecx, uint32_t *edx)
474{
475 struct core_topology topo = {0};
631be321
BM		 476 unsigned long nodes;
477 int shift;
ed78467a
BM		 478
479 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
480 *eax = cpu->apic_id;
481 /*
482 * CPUID_Fn8000001E_EBX
483 * 31:16 Reserved
484 * 15:8 Threads per core (The number of threads per core is
485 * Threads per core + 1)
486 * 7:0 Core id (see bit decoding below)
487 * SMT:
488 * 4:3 node id
489 * 2 Core complex id
490 * 1:0 Core id
491 * Non SMT:
492 * 5:4 node id
493 * 3 Core complex id
494 * 1:0 Core id
495 */
496 if (cs->nr_threads - 1) {
497 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
498 (topo.ccx_id << 2) | topo.core_id;
499 } else {
500 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
501 }
502 /*
503 * CPUID_Fn8000001E_ECX
504 * 31:11 Reserved
505 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
506 * 7:0 Node id (see bit decoding below)
507 * 2 Socket id
508 * 1:0 Node id
509 */
631be321
BM		 510 if (topo.num_nodes <= 4) {
511 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
512 topo.node_id;
513 } else {
514 /*
515 * Node id fix up. Actual hardware supports up to 4 nodes. But with
516 * more than 32 cores, we may end up with more than 4 nodes.
517 * Node id is a combination of socket id and node id. Only requirement
518 * here is that this number should be unique accross the system.
519 * Shift the socket id to accommodate more nodes. We dont expect both
520 * socket id and node id to be big number at the same time. This is not
521 * an ideal config but we need to to support it. Max nodes we can have
522 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
523 * 5 bits for nodes. Find the left most set bit to represent the total
524 * number of nodes. find_last_bit returns last set bit(0 based). Left
525 * shift(+1) the socket id to represent all the nodes.
526 */
527 nodes = topo.num_nodes - 1;
528 shift = find_last_bit(&nodes, 8);
529 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
530 topo.node_id;
531 }
ed78467a
BM		 532 *edx = 0;
533}
534
ab8f992e
BM		 535/*
536 * Definitions of the hardcoded cache entries we expose:
537 * These are legacy cache values. If there is a need to change any
538 * of these values please use builtin_x86_defs
539 */
5e891bf8
EH		 540
541/* L1 data cache: */
ab8f992e 542static CPUCacheInfo legacy_l1d_cache = {
5f00335a 543 .type = DATA_CACHE,
7e3482f8
EH		 544 .level = 1,
545 .size = 32 * KiB,
546 .self_init = 1,
547 .line_size = 64,
548 .associativity = 8,
549 .sets = 64,
550 .partitions = 1,
551 .no_invd_sharing = true,
552};
553
5e891bf8 554/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 555static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 556 .type = DATA_CACHE,
7e3482f8
EH		 557 .level = 1,
558 .size = 64 * KiB,
559 .self_init = 1,
560 .line_size = 64,
561 .associativity = 2,
562 .sets = 512,
563 .partitions = 1,
564 .lines_per_tag = 1,
565 .no_invd_sharing = true,
566};
5e891bf8
EH		 567
568/* L1 instruction cache: */
ab8f992e 569static CPUCacheInfo legacy_l1i_cache = {
5f00335a 570 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 571 .level = 1,
572 .size = 32 * KiB,
573 .self_init = 1,
574 .line_size = 64,
575 .associativity = 8,
576 .sets = 64,
577 .partitions = 1,
578 .no_invd_sharing = true,
579};
580
5e891bf8 581/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 582static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 583 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 584 .level = 1,
585 .size = 64 * KiB,
586 .self_init = 1,
587 .line_size = 64,
588 .associativity = 2,
589 .sets = 512,
590 .partitions = 1,
591 .lines_per_tag = 1,
592 .no_invd_sharing = true,
593};
5e891bf8
EH		 594
595/* Level 2 unified cache: */
ab8f992e 596static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 597 .type = UNIFIED_CACHE,
598 .level = 2,
599 .size = 4 * MiB,
600 .self_init = 1,
601 .line_size = 64,
602 .associativity = 16,
603 .sets = 4096,
604 .partitions = 1,
605 .no_invd_sharing = true,
606};
607
5e891bf8 608/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 609static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 610 .type = UNIFIED_CACHE,
611 .level = 2,
612 .size = 2 * MiB,
613 .line_size = 64,
614 .associativity = 8,
615};
616
617
5e891bf8 618/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 619static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 620 .type = UNIFIED_CACHE,
621 .level = 2,
622 .size = 512 * KiB,
623 .line_size = 64,
624 .lines_per_tag = 1,
625 .associativity = 16,
626 .sets = 512,
627 .partitions = 1,
628};
5e891bf8 629
14c985cf 630/* Level 3 unified cache: */
ab8f992e 631static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 632 .type = UNIFIED_CACHE,
633 .level = 3,
634 .size = 16 * MiB,
635 .line_size = 64,
636 .associativity = 16,
637 .sets = 16384,
638 .partitions = 1,
639 .lines_per_tag = 1,
640 .self_init = true,
641 .inclusive = true,
642 .complex_indexing = true,
643};
5e891bf8
EH		 644
645/* TLB definitions: */
646
647#define L1_DTLB_2M_ASSOC 1
648#define L1_DTLB_2M_ENTRIES 255
649#define L1_DTLB_4K_ASSOC 1
650#define L1_DTLB_4K_ENTRIES 255
651
652#define L1_ITLB_2M_ASSOC 1
653#define L1_ITLB_2M_ENTRIES 255
654#define L1_ITLB_4K_ASSOC 1
655#define L1_ITLB_4K_ENTRIES 255
656
657#define L2_DTLB_2M_ASSOC 0 /* disabled */
658#define L2_DTLB_2M_ENTRIES 0 /* disabled */
659#define L2_DTLB_4K_ASSOC 4
660#define L2_DTLB_4K_ENTRIES 512
661
662#define L2_ITLB_2M_ASSOC 0 /* disabled */
663#define L2_ITLB_2M_ENTRIES 0 /* disabled */
664#define L2_ITLB_4K_ASSOC 4
665#define L2_ITLB_4K_ENTRIES 512
666
e37a5c7f
CP		 667/* CPUID Leaf 0x14 constants: */
668#define INTEL_PT_MAX_SUBLEAF 0x1
669/*
670 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
671 * MSR can be accessed;
672 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
673 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
674 * of Intel PT MSRs across warm reset;
675 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
676 */
677#define INTEL_PT_MINIMAL_EBX 0xf
678/*
679 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
680 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
681 * accessed;
682 * bit[01]: ToPA tables can hold any number of output entries, up to the
683 * maximum allowed by the MaskOrTableOffset field of
684 * IA32_RTIT_OUTPUT_MASK_PTRS;
685 * bit[02]: Support Single-Range Output scheme;
686 */
687#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 688/* generated packets which contain IP payloads have LIP values */
689#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 690#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
691#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
692#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
693#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
694#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 695
99b88a17
IM		 696static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
697 uint32_t vendor2, uint32_t vendor3)
698{
699 int i;
700 for (i = 0; i < 4; i++) {
701 dst[i] = vendor1 >> (8 * i);
702 dst[i + 4] = vendor2 >> (8 * i);
703 dst[i + 8] = vendor3 >> (8 * i);
704 }
705 dst[CPUID_VENDOR_SZ] = '\0';
706}
707
621626ce
EH		 708#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
709#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
710 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
711#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
712 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
713 CPUID_PSE36 | CPUID_FXSR)
714#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
715#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
716 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
717 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
718 CPUID_PAE | CPUID_SEP | CPUID_APIC)
719
720#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
721 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
722 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
723 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 724 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 725 /* partly implemented:
726 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
727 /* missing:
728 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
729#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
730 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
731 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 732 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
621626ce
EH		 733 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
734 /* missing:
735 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
736 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
737 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db
RH		 738 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
739 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
621626ce
EH		 740
741#ifdef TARGET_X86_64
742#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
743#else
744#define TCG_EXT2_X86_64_FEATURES 0
745#endif
746
747#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
748 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
749 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
750 TCG_EXT2_X86_64_FEATURES)
751#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
752 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
753#define TCG_EXT4_FEATURES 0
fe441054 754#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 755#define TCG_KVM_FEATURES 0
756#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 757 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
758 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 759 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
760 CPUID_7_0_EBX_ERMS)
621626ce 761 /* missing:
07929f2a 762 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 763 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 764 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 765#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
766 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 767 CPUID_7_0_ECX_LA57)
95ea69fb 768#define TCG_7_0_EDX_FEATURES 0
303752a9 769#define TCG_APM_FEATURES 0
28b8e4d0 770#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 771#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
772 /* missing:
773 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 774
07585923
RH		 775typedef enum FeatureWordType {
776 CPUID_FEATURE_WORD,
777 MSR_FEATURE_WORD,
778} FeatureWordType;
779
5ef57876 780typedef struct FeatureWordInfo {
07585923 781 FeatureWordType type;
2d5312da
EH		 782 /* feature flags names are taken from "Intel Processor Identification and
783 * the CPUID Instruction" and AMD's "CPUID Specification".
784 * In cases of disagreement between feature naming conventions,
785 * aliases may be added.
786 */
787 const char *feat_names[32];
07585923
RH		 788 union {
789 /* If type==CPUID_FEATURE_WORD */
790 struct {
791 uint32_t eax; /* Input EAX for CPUID */
792 bool needs_ecx; /* CPUID instruction uses ECX as input */
793 uint32_t ecx; /* Input ECX value for CPUID */
794 int reg; /* output register (R_* constant) */
795 } cpuid;
796 /* If type==MSR_FEATURE_WORD */
797 struct {
798 uint32_t index;
799 struct { /*CPUID that enumerate this MSR*/
800 FeatureWord cpuid_class;
801 uint32_t cpuid_flag;
802 } cpuid_dep;
803 } msr;
804 };
37ce3522 805 uint32_t tcg_features; /* Feature flags supported by TCG */
84f1b92f 806 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
6fb2fff7 807 uint32_t migratable_flags; /* Feature flags known to be migratable */
0d914f39
EH		 808 /* Features that shouldn't be auto-enabled by "-cpu host" */
809 uint32_t no_autoenable_flags;
5ef57876
EH		 810} FeatureWordInfo;
811
812static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 813 [FEAT_1_EDX] = {
07585923 814 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 815 .feat_names = {
816 "fpu", "vme", "de", "pse",
817 "tsc", "msr", "pae", "mce",
818 "cx8", "apic", NULL, "sep",
819 "mtrr", "pge", "mca", "cmov",
820 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
821 NULL, "ds" /* Intel dts */, "acpi", "mmx",
822 "fxsr", "sse", "sse2", "ss",
823 "ht" /* Intel htt */, "tm", "ia64", "pbe",
824 },
07585923 825 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 826 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 827 },
828 [FEAT_1_ECX] = {
07585923 829 .type = CPUID_FEATURE_WORD,
2d5312da 830 .feat_names = {
16d2fcaa 831 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 832 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 833 "tm2", "ssse3", "cid", NULL,
834 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 835 NULL, "pcid", "dca", "sse4.1",
836 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 837 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 838 "avx", "f16c", "rdrand", "hypervisor",
839 },
07585923 840 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 841 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 842 },
2d5312da
EH		 843 /* Feature names that are already defined on feature_name[] but
844 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
845 * names on feat_names below. They are copied automatically
846 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
847 */
bffd67b0 848 [FEAT_8000_0001_EDX] = {
07585923 849 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 850 .feat_names = {
851 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
852 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
853 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
854 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
855 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 856 "nx", NULL, "mmxext", NULL /* mmx */,
857 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
858 NULL, "lm", "3dnowext", "3dnow",
2d5312da 859 },
07585923 860 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 861 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 862 },
863 [FEAT_8000_0001_ECX] = {
07585923 864 .type = CPUID_FEATURE_WORD,
2d5312da 865 .feat_names = {
fc7dfd20 866 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 867 "cr8legacy", "abm", "sse4a", "misalignsse",
868 "3dnowprefetch", "osvw", "ibs", "xop",
869 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 870 "fma4", "tce", NULL, "nodeid-msr",
871 NULL, "tbm", "topoext", "perfctr-core",
872 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 873 NULL, NULL, NULL, NULL,
874 },
07585923 875 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 876 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 877 /*
878 * TOPOEXT is always allowed but can't be enabled blindly by
879 * "-cpu host", as it requires consistent cache topology info
880 * to be provided so it doesn't confuse guests.
881 */
882 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 883 },
89e49c8b 884 [FEAT_C000_0001_EDX] = {
07585923 885 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 886 .feat_names = {
887 NULL, NULL, "xstore", "xstore-en",
888 NULL, NULL, "xcrypt", "xcrypt-en",
889 "ace2", "ace2-en", "phe", "phe-en",
890 "pmm", "pmm-en", NULL, NULL,
891 NULL, NULL, NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 },
07585923 896 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 897 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 898 },
bffd67b0 899 [FEAT_KVM] = {
07585923 900 .type = CPUID_FEATURE_WORD,
2d5312da 901 .feat_names = {
fc7dfd20
EH		 902 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
903 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 904 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
2d5312da
EH		 905 NULL, NULL, NULL, NULL,
906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 "kvmclock-stable-bit", NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 },
07585923 911 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 912 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 913 },
be777326 914 [FEAT_KVM_HINTS] = {
07585923 915 .type = CPUID_FEATURE_WORD,
be777326
WL		 916 .feat_names = {
917 "kvm-hint-dedicated", NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 },
07585923 926 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 927 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 928 /*
929 * KVM hints aren't auto-enabled by -cpu host, they need to be
930 * explicitly enabled in the command-line.
931 */
932 .no_autoenable_flags = ~0U,
be777326 933 },
abd5fc4c
VK		 934 /*
935 * .feat_names are commented out for Hyper-V enlightenments because we
936 * don't want to have two different ways for enabling them on QEMU command
937 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
938 * enabling several feature bits simultaneously, exposing these bits
939 * individually may just confuse guests.
940 */
c35bd19a 941 [FEAT_HYPERV_EAX] = {
07585923 942 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 943 .feat_names = {
944 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
945 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
946 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
947 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
948 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
949 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 950 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
951 NULL, NULL,
2d5312da
EH		 952 NULL, NULL, NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 },
07585923 957 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 958 },
959 [FEAT_HYPERV_EBX] = {
07585923 960 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 961 .feat_names = {
962 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
963 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
964 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
965 NULL /* hv_create_port */, NULL /* hv_connect_port */,
966 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
967 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
968 NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 },
07585923 974 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 975 },
976 [FEAT_HYPERV_EDX] = {
07585923 977 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 978 .feat_names = {
979 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
980 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
981 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
982 NULL, NULL,
983 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 },
07585923 990 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 991 },
a2b107db
VK		 992 [FEAT_HV_RECOMM_EAX] = {
993 .type = CPUID_FEATURE_WORD,
994 .feat_names = {
995 NULL /* hv_recommend_pv_as_switch */,
996 NULL /* hv_recommend_pv_tlbflush_local */,
997 NULL /* hv_recommend_pv_tlbflush_remote */,
998 NULL /* hv_recommend_msr_apic_access */,
999 NULL /* hv_recommend_msr_reset */,
1000 NULL /* hv_recommend_relaxed_timing */,
1001 NULL /* hv_recommend_dma_remapping */,
1002 NULL /* hv_recommend_int_remapping */,
1003 NULL /* hv_recommend_x2apic_msrs */,
1004 NULL /* hv_recommend_autoeoi_deprecation */,
1005 NULL /* hv_recommend_pv_ipi */,
1006 NULL /* hv_recommend_ex_hypercalls */,
1007 NULL /* hv_hypervisor_is_nested */,
1008 NULL /* hv_recommend_int_mbec */,
1009 NULL /* hv_recommend_evmcs */,
1010 NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 },
1016 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1017 },
1018 [FEAT_HV_NESTED_EAX] = {
1019 .type = CPUID_FEATURE_WORD,
1020 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1021 },
bffd67b0 1022 [FEAT_SVM] = {
07585923 1023 .type = CPUID_FEATURE_WORD,
2d5312da 1024 .feat_names = {
fc7dfd20
EH		 1025 "npt", "lbrv", "svm-lock", "nrip-save",
1026 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1027 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 1028 "pfthreshold", NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 },
07585923 1034 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 1035 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 1036 },
1037 [FEAT_7_0_EBX] = {
07585923 1038 .type = CPUID_FEATURE_WORD,
2d5312da 1039 .feat_names = {
fc7dfd20 1040 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 1041 "hle", "avx2", NULL, "smep",
1042 "bmi2", "erms", "invpcid", "rtm",
1043 NULL, NULL, "mpx", NULL,
1044 "avx512f", "avx512dq", "rdseed", "adx",
1045 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 1046 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 1047 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 1048 },
07585923
RH		 1049 .cpuid = {
1050 .eax = 7,
1051 .needs_ecx = true, .ecx = 0,
1052 .reg = R_EBX,
1053 },
37ce3522 1054 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 1055 },
f74eefe0 1056 [FEAT_7_0_ECX] = {
07585923 1057 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1058 .feat_names = {
1059 NULL, "avx512vbmi", "umip", "pku",
9ccb9784 1060 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
aff9e6e4
YZ		 1061 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1062 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 1063 "la57", NULL, NULL, NULL,
2d5312da 1064 NULL, NULL, "rdpid", NULL,
24261de4 1065 NULL, "cldemote", NULL, "movdiri",
1c65775f 1066 "movdir64b", NULL, NULL, NULL,
2d5312da 1067 },
07585923
RH		 1068 .cpuid = {
1069 .eax = 7,
1070 .needs_ecx = true, .ecx = 0,
1071 .reg = R_ECX,
1072 },
f74eefe0
HH		 1073 .tcg_features = TCG_7_0_ECX_FEATURES,
1074 },
95ea69fb 1075 [FEAT_7_0_EDX] = {
07585923 1076 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 1077 .feat_names = {
1078 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
712f807e 1082 NULL, NULL, NULL, NULL,
95ea69fb 1083 NULL, NULL, NULL, NULL,
0e891658 1084 NULL, NULL, "spec-ctrl", "stibp",
3fc7c731 1085 NULL, "arch-capabilities", NULL, "ssbd",
95ea69fb 1086 },
07585923
RH		 1087 .cpuid = {
1088 .eax = 7,
1089 .needs_ecx = true, .ecx = 0,
1090 .reg = R_EDX,
1091 },
95ea69fb
LK		 1092 .tcg_features = TCG_7_0_EDX_FEATURES,
1093 },
303752a9 1094 [FEAT_8000_0007_EDX] = {
07585923 1095 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1096 .feat_names = {
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 "invtsc", NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 },
07585923 1106 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1107 .tcg_features = TCG_APM_FEATURES,
1108 .unmigratable_flags = CPUID_APM_INVTSC,
1109 },
1b3420e1 1110 [FEAT_8000_0008_EBX] = {
07585923 1111 .type = CPUID_FEATURE_WORD,
1b3420e1
EH		 1112 .feat_names = {
1113 NULL, NULL, NULL, NULL,
1114 NULL, NULL, NULL, NULL,
59a80a19 1115 NULL, "wbnoinvd", NULL, NULL,
1b3420e1
EH		 1116 "ibpb", NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
254790a9 1119 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1120 NULL, NULL, NULL, NULL,
1121 },
07585923 1122 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1123 .tcg_features = 0,
1124 .unmigratable_flags = 0,
1125 },
0bb0b2d2 1126 [FEAT_XSAVE] = {
07585923 1127 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1128 .feat_names = {
1129 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
07585923
RH		 1138 .cpuid = {
1139 .eax = 0xd,
1140 .needs_ecx = true, .ecx = 1,
1141 .reg = R_EAX,
1142 },
c9cfe8f9 1143 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1144 },
28b8e4d0 1145 [FEAT_6_EAX] = {
07585923 1146 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1147 .feat_names = {
1148 NULL, NULL, "arat", NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 },
07585923 1157 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1158 .tcg_features = TCG_6_EAX_FEATURES,
1159 },
96193c22 1160 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1161 .type = CPUID_FEATURE_WORD,
1162 .cpuid = {
1163 .eax = 0xD,
1164 .needs_ecx = true, .ecx = 0,
1165 .reg = R_EAX,
1166 },
96193c22 1167 .tcg_features = ~0U,
6fb2fff7
EH		 1168 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1169 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1170 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1171 XSTATE_PKRU_MASK,
96193c22
EH		 1172 },
1173 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1174 .type = CPUID_FEATURE_WORD,
1175 .cpuid = {
1176 .eax = 0xD,
1177 .needs_ecx = true, .ecx = 0,
1178 .reg = R_EDX,
1179 },
96193c22
EH		 1180 .tcg_features = ~0U,
1181 },
d86f9636
RH		 1182 /*Below are MSR exposed features*/
1183 [FEAT_ARCH_CAPABILITIES] = {
1184 .type = MSR_FEATURE_WORD,
1185 .feat_names = {
1186 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1187 "ssb-no", NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 },
1195 .msr = {
1196 .index = MSR_IA32_ARCH_CAPABILITIES,
1197 .cpuid_dep = {
1198 FEAT_7_0_EDX,
1199 CPUID_7_0_EDX_ARCH_CAPABILITIES
1200 }
1201 },
1202 },
5ef57876
EH		 1203};
1204
8e8aba50
EH		 1205typedef struct X86RegisterInfo32 {
1206 /* Name of register */
1207 const char *name;
1208 /* QAPI enum value register */
1209 X86CPURegister32 qapi_enum;
1210} X86RegisterInfo32;
1211
1212#define REGISTER(reg) \
5d371f41 1213 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1214static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1215 REGISTER(EAX),
1216 REGISTER(ECX),
1217 REGISTER(EDX),
1218 REGISTER(EBX),
1219 REGISTER(ESP),
1220 REGISTER(EBP),
1221 REGISTER(ESI),
1222 REGISTER(EDI),
1223};
1224#undef REGISTER
1225
3f32bd21
RH		 1226typedef struct ExtSaveArea {
1227 uint32_t feature, bits;
1228 uint32_t offset, size;
1229} ExtSaveArea;
1230
1231static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1232 [XSTATE_FP_BIT] = {
1233 /* x87 FP state component is always enabled if XSAVE is supported */
1234 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1235 /* x87 state is in the legacy region of the XSAVE area */
1236 .offset = 0,
1237 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1238 },
1239 [XSTATE_SSE_BIT] = {
1240 /* SSE state component is always enabled if XSAVE is supported */
1241 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1242 /* SSE state is in the legacy region of the XSAVE area */
1243 .offset = 0,
1244 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1245 },
cfc3b074
PB		 1246 [XSTATE_YMM_BIT] =
1247 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1248 .offset = offsetof(X86XSaveArea, avx_state),
1249 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1250 [XSTATE_BNDREGS_BIT] =
1251 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1252 .offset = offsetof(X86XSaveArea, bndreg_state),
1253 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1254 [XSTATE_BNDCSR_BIT] =
1255 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1256 .offset = offsetof(X86XSaveArea, bndcsr_state),
1257 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1258 [XSTATE_OPMASK_BIT] =
1259 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1260 .offset = offsetof(X86XSaveArea, opmask_state),
1261 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1262 [XSTATE_ZMM_Hi256_BIT] =
1263 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1264 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1265 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1266 [XSTATE_Hi16_ZMM_BIT] =
1267 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1268 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1269 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1270 [XSTATE_PKRU_BIT] =
1271 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1272 .offset = offsetof(X86XSaveArea, pkru_state),
1273 .size = sizeof(XSavePKRU) },
2560f19f 1274};
8e8aba50 1275
1fda6198
EH		 1276static uint32_t xsave_area_size(uint64_t mask)
1277{
1278 int i;
e3c9022b 1279 uint64_t ret = 0;
1fda6198 1280
e3c9022b 1281 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1282 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1283 if ((mask >> i) & 1) {
1284 ret = MAX(ret, esa->offset + esa->size);
1285 }
1286 }
1287 return ret;
1288}
1289
d6dcc558
SAGDR		 1290static inline bool accel_uses_host_cpuid(void)
1291{
1292 return kvm_enabled() || hvf_enabled();
1293}
1294
96193c22
EH		 1295static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1296{
1297 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1298 cpu->env.features[FEAT_XSAVE_COMP_LO];
1299}
1300
8b4beddc
EH		 1301const char *get_register_name_32(unsigned int reg)
1302{
31ccdde2 1303 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1304 return NULL;
1305 }
8e8aba50 1306 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1307}
1308
84f1b92f
EH		 1309/*
1310 * Returns the set of feature flags that are supported and migratable by
1311 * QEMU, for a given FeatureWord.
1312 */
1313static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1314{
1315 FeatureWordInfo *wi = &feature_word_info[w];
1316 uint32_t r = 0;
1317 int i;
1318
1319 for (i = 0; i < 32; i++) {
1320 uint32_t f = 1U << i;
6fb2fff7
EH		 1321
1322 /* If the feature name is known, it is implicitly considered migratable,
1323 * unless it is explicitly set in unmigratable_flags */
1324 if ((wi->migratable_flags & f) ||
1325 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1326 r |= f;
84f1b92f 1327 }
84f1b92f
EH		 1328 }
1329 return r;
1330}
1331
bb44e0d1
JK		 1332void host_cpuid(uint32_t function, uint32_t count,
1333 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1334{
a1fd24af
AL		 1335 uint32_t vec[4];
1336
1337#ifdef __x86_64__
1338 asm volatile("cpuid"
1339 : "=a"(vec[0]), "=b"(vec[1]),
1340 "=c"(vec[2]), "=d"(vec[3])
1341 : "0"(function), "c"(count) : "cc");
c1f41226 1342#elif defined(__i386__)
a1fd24af
AL		 1343 asm volatile("pusha \n\t"
1344 "cpuid \n\t"
1345 "mov %%eax, 0(%2) \n\t"
1346 "mov %%ebx, 4(%2) \n\t"
1347 "mov %%ecx, 8(%2) \n\t"
1348 "mov %%edx, 12(%2) \n\t"
1349 "popa"
1350 : : "a"(function), "c"(count), "S"(vec)
1351 : "memory", "cc");
c1f41226
EH		 1352#else
1353 abort();
a1fd24af
AL		 1354#endif
1355
bdde476a 1356 if (eax)
a1fd24af 1357 *eax = vec[0];
bdde476a 1358 if (ebx)
a1fd24af 1359 *ebx = vec[1];
bdde476a 1360 if (ecx)
a1fd24af 1361 *ecx = vec[2];
bdde476a 1362 if (edx)
a1fd24af 1363 *edx = vec[3];
bdde476a 1364}
c6dc6f63 1365
20271d48
EH		 1366void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1367{
1368 uint32_t eax, ebx, ecx, edx;
1369
1370 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1371 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1372
1373 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1374 if (family) {
1375 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1376 }
1377 if (model) {
1378 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1379 }
1380 if (stepping) {
1381 *stepping = eax & 0x0F;
1382 }
1383}
1384
d940ee9b
EH		 1385/* CPU class name definitions: */
1386
d940ee9b
EH		 1387/* Return type name for a given CPU model name
1388 * Caller is responsible for freeing the returned string.
1389 */
1390static char *x86_cpu_type_name(const char *model_name)
1391{
1392 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1393}
1394
500050d1
AF		 1395static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1396{
d940ee9b 1397 ObjectClass *oc;
99193d8f 1398 char *typename = x86_cpu_type_name(cpu_model);
d940ee9b
EH		 1399 oc = object_class_by_name(typename);
1400 g_free(typename);
1401 return oc;
500050d1
AF		 1402}
1403
104494ea
IM		 1404static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1405{
1406 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1407 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1408 return g_strndup(class_name,
1409 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1410}
1411
d940ee9b 1412struct X86CPUDefinition {
c6dc6f63
AP		 1413 const char *name;
1414 uint32_t level;
90e4b0c3 1415 uint32_t xlevel;
99b88a17
IM		 1416 /* vendor is zero-terminated, 12 character ASCII string */
1417 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1418 int family;
1419 int model;
1420 int stepping;
0514ef2f 1421 FeatureWordArray features;
807e9869 1422 const char *model_id;
6aaeb054 1423 CPUCaches *cache_info;
d940ee9b 1424};
c6dc6f63 1425
fe52acd2 1426static CPUCaches epyc_cache_info = {
a9f27ea9 1427 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1428 .type = DATA_CACHE,
fe52acd2
BM		 1429 .level = 1,
1430 .size = 32 * KiB,
1431 .line_size = 64,
1432 .associativity = 8,
1433 .partitions = 1,
1434 .sets = 64,
1435 .lines_per_tag = 1,
1436 .self_init = 1,
1437 .no_invd_sharing = true,
1438 },
a9f27ea9 1439 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1440 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1441 .level = 1,
1442 .size = 64 * KiB,
1443 .line_size = 64,
1444 .associativity = 4,
1445 .partitions = 1,
1446 .sets = 256,
1447 .lines_per_tag = 1,
1448 .self_init = 1,
1449 .no_invd_sharing = true,
1450 },
a9f27ea9 1451 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1452 .type = UNIFIED_CACHE,
1453 .level = 2,
1454 .size = 512 * KiB,
1455 .line_size = 64,
1456 .associativity = 8,
1457 .partitions = 1,
1458 .sets = 1024,
1459 .lines_per_tag = 1,
1460 },
a9f27ea9 1461 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1462 .type = UNIFIED_CACHE,
1463 .level = 3,
1464 .size = 8 * MiB,
1465 .line_size = 64,
1466 .associativity = 16,
1467 .partitions = 1,
1468 .sets = 8192,
1469 .lines_per_tag = 1,
1470 .self_init = true,
1471 .inclusive = true,
1472 .complex_indexing = true,
1473 },
1474};
1475
9576de75 1476static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1477 {
1478 .name = "qemu64",
3046bb5d 1479 .level = 0xd,
99b88a17 1480 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1481 .family = 6,
f8e6a11a 1482 .model = 6,
c6dc6f63 1483 .stepping = 3,
0514ef2f 1484 .features[FEAT_1_EDX] =
27861ecc 1485 PPRO_FEATURES |
c6dc6f63 1486 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1487 CPUID_PSE36,
0514ef2f 1488 .features[FEAT_1_ECX] =
6aa91e4a 1489 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1490 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1491 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1492 .features[FEAT_8000_0001_ECX] =
71195672 1493 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1494 .xlevel = 0x8000000A,
9cf2cc3d 1495 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1496 },
1497 {
1498 .name = "phenom",
1499 .level = 5,
99b88a17 1500 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1501 .family = 16,
1502 .model = 2,
1503 .stepping = 3,
b9fc20bc 1504 /* Missing: CPUID_HT */
0514ef2f 1505 .features[FEAT_1_EDX] =
27861ecc 1506 PPRO_FEATURES |
c6dc6f63 1507 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1508 CPUID_PSE36 | CPUID_VME,
0514ef2f 1509 .features[FEAT_1_ECX] =
27861ecc 1510 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1511 CPUID_EXT_POPCNT,
0514ef2f 1512 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1513 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1514 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1515 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1516 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1517 CPUID_EXT3_CR8LEG,
1518 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1519 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1520 .features[FEAT_8000_0001_ECX] =
27861ecc 1521 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1522 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1523 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1524 .features[FEAT_SVM] =
b9fc20bc 1525 CPUID_SVM_NPT,
c6dc6f63
AP		 1526 .xlevel = 0x8000001A,
1527 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1528 },
1529 {
1530 .name = "core2duo",
1531 .level = 10,
99b88a17 1532 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1533 .family = 6,
1534 .model = 15,
1535 .stepping = 11,
b9fc20bc 1536 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1537 .features[FEAT_1_EDX] =
27861ecc 1538 PPRO_FEATURES |
c6dc6f63 1539 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1540 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1541 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1542 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1543 .features[FEAT_1_ECX] =
27861ecc 1544 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1545 CPUID_EXT_CX16,
0514ef2f 1546 .features[FEAT_8000_0001_EDX] =
27861ecc 1547 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1548 .features[FEAT_8000_0001_ECX] =
27861ecc 1549 CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 1550 .xlevel = 0x80000008,
1551 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1552 },
1553 {
1554 .name = "kvm64",
3046bb5d 1555 .level = 0xd,
99b88a17 1556 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1557 .family = 15,
1558 .model = 6,
1559 .stepping = 1,
b3a4f0b1 1560 /* Missing: CPUID_HT */
0514ef2f 1561 .features[FEAT_1_EDX] =
b3a4f0b1 1562 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1563 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1564 CPUID_PSE36,
1565 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1566 .features[FEAT_1_ECX] =
27861ecc 1567 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1568 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1569 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1570 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1571 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1572 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1573 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1574 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1575 .features[FEAT_8000_0001_ECX] =
27861ecc 1576 0,
c6dc6f63
AP		 1577 .xlevel = 0x80000008,
1578 .model_id = "Common KVM processor"
1579 },
c6dc6f63
AP		 1580 {
1581 .name = "qemu32",
1582 .level = 4,
99b88a17 1583 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1584 .family = 6,
f8e6a11a 1585 .model = 6,
c6dc6f63 1586 .stepping = 3,
0514ef2f 1587 .features[FEAT_1_EDX] =
27861ecc 1588 PPRO_FEATURES,
0514ef2f 1589 .features[FEAT_1_ECX] =
6aa91e4a 1590 CPUID_EXT_SSE3,
58012d66 1591 .xlevel = 0x80000004,
9cf2cc3d 1592 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1593 },
eafaf1e5
AP		 1594 {
1595 .name = "kvm32",
1596 .level = 5,
99b88a17 1597 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1598 .family = 15,
1599 .model = 6,
1600 .stepping = 1,
0514ef2f 1601 .features[FEAT_1_EDX] =
b3a4f0b1 1602 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1603 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1604 .features[FEAT_1_ECX] =
27861ecc 1605 CPUID_EXT_SSE3,
0514ef2f 1606 .features[FEAT_8000_0001_ECX] =
27861ecc 1607 0,
eafaf1e5
AP		 1608 .xlevel = 0x80000008,
1609 .model_id = "Common 32-bit KVM processor"
1610 },
c6dc6f63
AP		 1611 {
1612 .name = "coreduo",
1613 .level = 10,
99b88a17 1614 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1615 .family = 6,
1616 .model = 14,
1617 .stepping = 8,
b9fc20bc 1618 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1619 .features[FEAT_1_EDX] =
27861ecc 1620 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1621 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1622 CPUID_SS,
1623 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1624 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1625 .features[FEAT_1_ECX] =
e93abc14 1626 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1627 .features[FEAT_8000_0001_EDX] =
27861ecc 1628 CPUID_EXT2_NX,
c6dc6f63
AP		 1629 .xlevel = 0x80000008,
1630 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1631 },
1632 {
1633 .name = "486",
58012d66 1634 .level = 1,
99b88a17 1635 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1636 .family = 4,
b2a856d9 1637 .model = 8,
c6dc6f63 1638 .stepping = 0,
0514ef2f 1639 .features[FEAT_1_EDX] =
27861ecc 1640 I486_FEATURES,
c6dc6f63 1641 .xlevel = 0,
807e9869 1642 .model_id = "",
c6dc6f63
AP		 1643 },
1644 {
1645 .name = "pentium",
1646 .level = 1,
99b88a17 1647 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1648 .family = 5,
1649 .model = 4,
1650 .stepping = 3,
0514ef2f 1651 .features[FEAT_1_EDX] =
27861ecc 1652 PENTIUM_FEATURES,
c6dc6f63 1653 .xlevel = 0,
807e9869 1654 .model_id = "",
c6dc6f63
AP		 1655 },
1656 {
1657 .name = "pentium2",
1658 .level = 2,
99b88a17 1659 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1660 .family = 6,
1661 .model = 5,
1662 .stepping = 2,
0514ef2f 1663 .features[FEAT_1_EDX] =
27861ecc 1664 PENTIUM2_FEATURES,
c6dc6f63 1665 .xlevel = 0,
807e9869 1666 .model_id = "",
c6dc6f63
AP		 1667 },
1668 {
1669 .name = "pentium3",
3046bb5d 1670 .level = 3,
99b88a17 1671 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1672 .family = 6,
1673 .model = 7,
1674 .stepping = 3,
0514ef2f 1675 .features[FEAT_1_EDX] =
27861ecc 1676 PENTIUM3_FEATURES,
c6dc6f63 1677 .xlevel = 0,
807e9869 1678 .model_id = "",
c6dc6f63
AP		 1679 },
1680 {
1681 .name = "athlon",
1682 .level = 2,
99b88a17 1683 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1684 .family = 6,
1685 .model = 2,
1686 .stepping = 3,
0514ef2f 1687 .features[FEAT_1_EDX] =
27861ecc 1688 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 1689 CPUID_MCA,
0514ef2f 1690 .features[FEAT_8000_0001_EDX] =
60032ac0 1691 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 1692 .xlevel = 0x80000008,
9cf2cc3d 1693 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1694 },
1695 {
1696 .name = "n270",
3046bb5d 1697 .level = 10,
99b88a17 1698 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1699 .family = 6,
1700 .model = 28,
1701 .stepping = 2,
b9fc20bc 1702 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1703 .features[FEAT_1_EDX] =
27861ecc 1704 PPRO_FEATURES |
b9fc20bc
EH		 1705 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1706 CPUID_ACPI | CPUID_SS,
c6dc6f63 1707 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 1708 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1709 * CPUID_EXT_XTPR */
0514ef2f 1710 .features[FEAT_1_ECX] =
27861ecc 1711 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 1712 CPUID_EXT_MOVBE,
0514ef2f 1713 .features[FEAT_8000_0001_EDX] =
60032ac0 1714 CPUID_EXT2_NX,
0514ef2f 1715 .features[FEAT_8000_0001_ECX] =
27861ecc 1716 CPUID_EXT3_LAHF_LM,
3046bb5d 1717 .xlevel = 0x80000008,
c6dc6f63
AP		 1718 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1719 },
3eca4642
EH		 1720 {
1721 .name = "Conroe",
3046bb5d 1722 .level = 10,
99b88a17 1723 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1724 .family = 6,
ffce9ebb 1725 .model = 15,
3eca4642 1726 .stepping = 3,
0514ef2f 1727 .features[FEAT_1_EDX] =
b3a4f0b1 1728 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1729 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1730 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1731 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1732 CPUID_DE | CPUID_FP87,
0514ef2f 1733 .features[FEAT_1_ECX] =
27861ecc 1734 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1735 .features[FEAT_8000_0001_EDX] =
27861ecc 1736 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1737 .features[FEAT_8000_0001_ECX] =
27861ecc 1738 CPUID_EXT3_LAHF_LM,
3046bb5d 1739 .xlevel = 0x80000008,
3eca4642
EH		 1740 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1741 },
1742 {
1743 .name = "Penryn",
3046bb5d 1744 .level = 10,
99b88a17 1745 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1746 .family = 6,
ffce9ebb 1747 .model = 23,
3eca4642 1748 .stepping = 3,
0514ef2f 1749 .features[FEAT_1_EDX] =
b3a4f0b1 1750 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1751 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1752 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1753 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1754 CPUID_DE | CPUID_FP87,
0514ef2f 1755 .features[FEAT_1_ECX] =
27861ecc 1756 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 1757 CPUID_EXT_SSE3,
0514ef2f 1758 .features[FEAT_8000_0001_EDX] =
27861ecc 1759 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 1760 .features[FEAT_8000_0001_ECX] =
27861ecc 1761 CPUID_EXT3_LAHF_LM,
3046bb5d 1762 .xlevel = 0x80000008,
3eca4642
EH		 1763 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1764 },
1765 {
1766 .name = "Nehalem",
3046bb5d 1767 .level = 11,
99b88a17 1768 .vendor = CPUID_VENDOR_INTEL,
3eca4642 1769 .family = 6,
ffce9ebb 1770 .model = 26,
3eca4642 1771 .stepping = 3,
0514ef2f 1772 .features[FEAT_1_EDX] =
b3a4f0b1 1773 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1777 CPUID_DE | CPUID_FP87,
0514ef2f 1778 .features[FEAT_1_ECX] =
27861ecc 1779 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 1780 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 1781 .features[FEAT_8000_0001_EDX] =
27861ecc 1782 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1783 .features[FEAT_8000_0001_ECX] =
27861ecc 1784 CPUID_EXT3_LAHF_LM,
3046bb5d 1785 .xlevel = 0x80000008,
3eca4642
EH		 1786 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1787 },
ac96c413
EH		 1788 {
1789 .name = "Nehalem-IBRS",
1790 .level = 11,
1791 .vendor = CPUID_VENDOR_INTEL,
1792 .family = 6,
1793 .model = 26,
1794 .stepping = 3,
1795 .features[FEAT_1_EDX] =
1796 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1797 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1798 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1799 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1800 CPUID_DE | CPUID_FP87,
1801 .features[FEAT_1_ECX] =
1802 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1803 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1804 .features[FEAT_7_0_EDX] =
1805 CPUID_7_0_EDX_SPEC_CTRL,
1806 .features[FEAT_8000_0001_EDX] =
1807 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1808 .features[FEAT_8000_0001_ECX] =
1809 CPUID_EXT3_LAHF_LM,
1810 .xlevel = 0x80000008,
1811 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1812 },
3eca4642
EH		 1813 {
1814 .name = "Westmere",
1815 .level = 11,
99b88a17 1816 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1817 .family = 6,
1818 .model = 44,
1819 .stepping = 1,
0514ef2f 1820 .features[FEAT_1_EDX] =
b3a4f0b1 1821 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1822 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1823 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1824 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1825 CPUID_DE | CPUID_FP87,
0514ef2f 1826 .features[FEAT_1_ECX] =
27861ecc 1827 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 1828 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1829 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 1830 .features[FEAT_8000_0001_EDX] =
27861ecc 1831 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1832 .features[FEAT_8000_0001_ECX] =
27861ecc 1833 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 1834 .features[FEAT_6_EAX] =
1835 CPUID_6_EAX_ARAT,
3046bb5d 1836 .xlevel = 0x80000008,
3eca4642
EH		 1837 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1838 },
ac96c413
EH		 1839 {
1840 .name = "Westmere-IBRS",
1841 .level = 11,
1842 .vendor = CPUID_VENDOR_INTEL,
1843 .family = 6,
1844 .model = 44,
1845 .stepping = 1,
1846 .features[FEAT_1_EDX] =
1847 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1848 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1849 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1850 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1851 CPUID_DE | CPUID_FP87,
1852 .features[FEAT_1_ECX] =
1853 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1854 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1855 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1856 .features[FEAT_8000_0001_EDX] =
1857 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1858 .features[FEAT_8000_0001_ECX] =
1859 CPUID_EXT3_LAHF_LM,
1860 .features[FEAT_7_0_EDX] =
1861 CPUID_7_0_EDX_SPEC_CTRL,
1862 .features[FEAT_6_EAX] =
1863 CPUID_6_EAX_ARAT,
1864 .xlevel = 0x80000008,
1865 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1866 },
3eca4642
EH		 1867 {
1868 .name = "SandyBridge",
1869 .level = 0xd,
99b88a17 1870 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 1871 .family = 6,
1872 .model = 42,
1873 .stepping = 1,
0514ef2f 1874 .features[FEAT_1_EDX] =
b3a4f0b1 1875 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 1876 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1877 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1878 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1879 CPUID_DE | CPUID_FP87,
0514ef2f 1880 .features[FEAT_1_ECX] =
27861ecc 1881 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 1882 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1883 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1884 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1885 CPUID_EXT_SSE3,
0514ef2f 1886 .features[FEAT_8000_0001_EDX] =
27861ecc 1887 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 1888 CPUID_EXT2_SYSCALL,
0514ef2f 1889 .features[FEAT_8000_0001_ECX] =
27861ecc 1890 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 1891 .features[FEAT_XSAVE] =
1892 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1893 .features[FEAT_6_EAX] =
1894 CPUID_6_EAX_ARAT,
3046bb5d 1895 .xlevel = 0x80000008,
3eca4642
EH		 1896 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1897 },
ac96c413
EH		 1898 {
1899 .name = "SandyBridge-IBRS",
1900 .level = 0xd,
1901 .vendor = CPUID_VENDOR_INTEL,
1902 .family = 6,
1903 .model = 42,
1904 .stepping = 1,
1905 .features[FEAT_1_EDX] =
1906 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1907 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1908 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1909 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1910 CPUID_DE | CPUID_FP87,
1911 .features[FEAT_1_ECX] =
1912 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1913 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1914 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1915 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1916 CPUID_EXT_SSE3,
1917 .features[FEAT_8000_0001_EDX] =
1918 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1919 CPUID_EXT2_SYSCALL,
1920 .features[FEAT_8000_0001_ECX] =
1921 CPUID_EXT3_LAHF_LM,
1922 .features[FEAT_7_0_EDX] =
1923 CPUID_7_0_EDX_SPEC_CTRL,
1924 .features[FEAT_XSAVE] =
1925 CPUID_XSAVE_XSAVEOPT,
1926 .features[FEAT_6_EAX] =
1927 CPUID_6_EAX_ARAT,
1928 .xlevel = 0x80000008,
1929 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1930 },
2f9ac42a
PB		 1931 {
1932 .name = "IvyBridge",
1933 .level = 0xd,
1934 .vendor = CPUID_VENDOR_INTEL,
1935 .family = 6,
1936 .model = 58,
1937 .stepping = 9,
1938 .features[FEAT_1_EDX] =
1939 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1940 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1941 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1942 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1943 CPUID_DE | CPUID_FP87,
1944 .features[FEAT_1_ECX] =
1945 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1946 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1947 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1948 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1949 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1950 .features[FEAT_7_0_EBX] =
1951 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1952 CPUID_7_0_EBX_ERMS,
1953 .features[FEAT_8000_0001_EDX] =
1954 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1955 CPUID_EXT2_SYSCALL,
1956 .features[FEAT_8000_0001_ECX] =
1957 CPUID_EXT3_LAHF_LM,
1958 .features[FEAT_XSAVE] =
1959 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 1960 .features[FEAT_6_EAX] =
1961 CPUID_6_EAX_ARAT,
3046bb5d 1962 .xlevel = 0x80000008,
2f9ac42a
PB		 1963 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1964 },
ac96c413
EH		 1965 {
1966 .name = "IvyBridge-IBRS",
1967 .level = 0xd,
1968 .vendor = CPUID_VENDOR_INTEL,
1969 .family = 6,
1970 .model = 58,
1971 .stepping = 9,
1972 .features[FEAT_1_EDX] =
1973 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1977 CPUID_DE | CPUID_FP87,
1978 .features[FEAT_1_ECX] =
1979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1981 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1983 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1984 .features[FEAT_7_0_EBX] =
1985 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1986 CPUID_7_0_EBX_ERMS,
1987 .features[FEAT_8000_0001_EDX] =
1988 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1989 CPUID_EXT2_SYSCALL,
1990 .features[FEAT_8000_0001_ECX] =
1991 CPUID_EXT3_LAHF_LM,
1992 .features[FEAT_7_0_EDX] =
1993 CPUID_7_0_EDX_SPEC_CTRL,
1994 .features[FEAT_XSAVE] =
1995 CPUID_XSAVE_XSAVEOPT,
1996 .features[FEAT_6_EAX] =
1997 CPUID_6_EAX_ARAT,
1998 .xlevel = 0x80000008,
1999 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2000 },
37507094 2001 {
a356850b
EH		 2002 .name = "Haswell-noTSX",
2003 .level = 0xd,
2004 .vendor = CPUID_VENDOR_INTEL,
2005 .family = 6,
2006 .model = 60,
2007 .stepping = 1,
2008 .features[FEAT_1_EDX] =
2009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2013 CPUID_DE | CPUID_FP87,
2014 .features[FEAT_1_ECX] =
2015 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2016 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2017 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2018 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2019 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2020 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2021 .features[FEAT_8000_0001_EDX] =
2022 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2023 CPUID_EXT2_SYSCALL,
2024 .features[FEAT_8000_0001_ECX] =
becb6667 2025 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
a356850b
EH		 2026 .features[FEAT_7_0_EBX] =
2027 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2028 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2029 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2030 .features[FEAT_XSAVE] =
2031 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2032 .features[FEAT_6_EAX] =
2033 CPUID_6_EAX_ARAT,
3046bb5d 2034 .xlevel = 0x80000008,
a356850b 2035 .model_id = "Intel Core Processor (Haswell, no TSX)",
ac96c413
EH		 2036 },
2037 {
2038 .name = "Haswell-noTSX-IBRS",
2039 .level = 0xd,
2040 .vendor = CPUID_VENDOR_INTEL,
2041 .family = 6,
2042 .model = 60,
2043 .stepping = 1,
2044 .features[FEAT_1_EDX] =
2045 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2046 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2047 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2048 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2049 CPUID_DE | CPUID_FP87,
2050 .features[FEAT_1_ECX] =
2051 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2052 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2053 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2054 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2056 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2057 .features[FEAT_8000_0001_EDX] =
2058 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2059 CPUID_EXT2_SYSCALL,
2060 .features[FEAT_8000_0001_ECX] =
2061 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2062 .features[FEAT_7_0_EDX] =
2063 CPUID_7_0_EDX_SPEC_CTRL,
2064 .features[FEAT_7_0_EBX] =
2065 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2066 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2067 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2068 .features[FEAT_XSAVE] =
2069 CPUID_XSAVE_XSAVEOPT,
2070 .features[FEAT_6_EAX] =
2071 CPUID_6_EAX_ARAT,
2072 .xlevel = 0x80000008,
2073 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2074 },
2075 {
37507094
EH		 2076 .name = "Haswell",
2077 .level = 0xd,
99b88a17 2078 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2079 .family = 6,
2080 .model = 60,
ec56a4a7 2081 .stepping = 4,
0514ef2f 2082 .features[FEAT_1_EDX] =
b3a4f0b1 2083 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2084 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2085 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2086 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2087 CPUID_DE | CPUID_FP87,
0514ef2f 2088 .features[FEAT_1_ECX] =
27861ecc 2089 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2090 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2091 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2092 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2093 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2094 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2095 .features[FEAT_8000_0001_EDX] =
27861ecc 2096 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2097 CPUID_EXT2_SYSCALL,
0514ef2f 2098 .features[FEAT_8000_0001_ECX] =
becb6667 2099 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2100 .features[FEAT_7_0_EBX] =
27861ecc 2101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2102 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2103 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2104 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2105 .features[FEAT_XSAVE] =
2106 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2107 .features[FEAT_6_EAX] =
2108 CPUID_6_EAX_ARAT,
3046bb5d 2109 .xlevel = 0x80000008,
37507094
EH		 2110 .model_id = "Intel Core Processor (Haswell)",
2111 },
ac96c413
EH		 2112 {
2113 .name = "Haswell-IBRS",
2114 .level = 0xd,
2115 .vendor = CPUID_VENDOR_INTEL,
2116 .family = 6,
2117 .model = 60,
2118 .stepping = 4,
2119 .features[FEAT_1_EDX] =
2120 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2121 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2122 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2123 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2124 CPUID_DE | CPUID_FP87,
2125 .features[FEAT_1_ECX] =
2126 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2127 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2128 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2129 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2130 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2131 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2132 .features[FEAT_8000_0001_EDX] =
2133 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2134 CPUID_EXT2_SYSCALL,
2135 .features[FEAT_8000_0001_ECX] =
2136 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2137 .features[FEAT_7_0_EDX] =
2138 CPUID_7_0_EDX_SPEC_CTRL,
2139 .features[FEAT_7_0_EBX] =
2140 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2141 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2142 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2143 CPUID_7_0_EBX_RTM,
2144 .features[FEAT_XSAVE] =
2145 CPUID_XSAVE_XSAVEOPT,
2146 .features[FEAT_6_EAX] =
2147 CPUID_6_EAX_ARAT,
2148 .xlevel = 0x80000008,
2149 .model_id = "Intel Core Processor (Haswell, IBRS)",
2150 },
a356850b
EH		 2151 {
2152 .name = "Broadwell-noTSX",
2153 .level = 0xd,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 61,
2157 .stepping = 2,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2166 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2167 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2168 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2169 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2170 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2171 .features[FEAT_8000_0001_EDX] =
2172 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2173 CPUID_EXT2_SYSCALL,
2174 .features[FEAT_8000_0001_ECX] =
becb6667 2175 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
a356850b
EH		 2176 .features[FEAT_7_0_EBX] =
2177 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2178 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2179 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2180 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2181 CPUID_7_0_EBX_SMAP,
2182 .features[FEAT_XSAVE] =
2183 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2184 .features[FEAT_6_EAX] =
2185 CPUID_6_EAX_ARAT,
3046bb5d 2186 .xlevel = 0x80000008,
a356850b
EH		 2187 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2188 },
ac96c413
EH		 2189 {
2190 .name = "Broadwell-noTSX-IBRS",
2191 .level = 0xd,
2192 .vendor = CPUID_VENDOR_INTEL,
2193 .family = 6,
2194 .model = 61,
2195 .stepping = 2,
2196 .features[FEAT_1_EDX] =
2197 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2198 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2199 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2200 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2201 CPUID_DE | CPUID_FP87,
2202 .features[FEAT_1_ECX] =
2203 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2204 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2205 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2206 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2207 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2208 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2209 .features[FEAT_8000_0001_EDX] =
2210 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2211 CPUID_EXT2_SYSCALL,
2212 .features[FEAT_8000_0001_ECX] =
2213 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2214 .features[FEAT_7_0_EDX] =
2215 CPUID_7_0_EDX_SPEC_CTRL,
2216 .features[FEAT_7_0_EBX] =
2217 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2218 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2219 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2220 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2221 CPUID_7_0_EBX_SMAP,
2222 .features[FEAT_XSAVE] =
2223 CPUID_XSAVE_XSAVEOPT,
2224 .features[FEAT_6_EAX] =
2225 CPUID_6_EAX_ARAT,
2226 .xlevel = 0x80000008,
2227 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2228 },
ece01354
EH		 2229 {
2230 .name = "Broadwell",
2231 .level = 0xd,
2232 .vendor = CPUID_VENDOR_INTEL,
2233 .family = 6,
2234 .model = 61,
2235 .stepping = 2,
2236 .features[FEAT_1_EDX] =
b3a4f0b1 2237 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2238 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2239 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2240 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2241 CPUID_DE | CPUID_FP87,
2242 .features[FEAT_1_ECX] =
2243 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2244 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2245 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2246 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2247 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2248 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2249 .features[FEAT_8000_0001_EDX] =
2250 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2251 CPUID_EXT2_SYSCALL,
2252 .features[FEAT_8000_0001_ECX] =
becb6667 2253 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2254 .features[FEAT_7_0_EBX] =
2255 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2256 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2257 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2258 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2259 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2260 .features[FEAT_XSAVE] =
2261 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2262 .features[FEAT_6_EAX] =
2263 CPUID_6_EAX_ARAT,
3046bb5d 2264 .xlevel = 0x80000008,
ece01354
EH		 2265 .model_id = "Intel Core Processor (Broadwell)",
2266 },
ac96c413
EH		 2267 {
2268 .name = "Broadwell-IBRS",
2269 .level = 0xd,
2270 .vendor = CPUID_VENDOR_INTEL,
2271 .family = 6,
2272 .model = 61,
2273 .stepping = 2,
2274 .features[FEAT_1_EDX] =
2275 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2276 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2277 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2278 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2279 CPUID_DE | CPUID_FP87,
2280 .features[FEAT_1_ECX] =
2281 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2282 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2283 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2284 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2285 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2286 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2287 .features[FEAT_8000_0001_EDX] =
2288 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2289 CPUID_EXT2_SYSCALL,
2290 .features[FEAT_8000_0001_ECX] =
2291 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2292 .features[FEAT_7_0_EDX] =
2293 CPUID_7_0_EDX_SPEC_CTRL,
2294 .features[FEAT_7_0_EBX] =
2295 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2296 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2297 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2298 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2299 CPUID_7_0_EBX_SMAP,
2300 .features[FEAT_XSAVE] =
2301 CPUID_XSAVE_XSAVEOPT,
2302 .features[FEAT_6_EAX] =
2303 CPUID_6_EAX_ARAT,
2304 .xlevel = 0x80000008,
2305 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2306 },
f6f949e9
EH		 2307 {
2308 .name = "Skylake-Client",
2309 .level = 0xd,
2310 .vendor = CPUID_VENDOR_INTEL,
2311 .family = 6,
2312 .model = 94,
2313 .stepping = 3,
2314 .features[FEAT_1_EDX] =
2315 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2316 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2317 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2318 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2319 CPUID_DE | CPUID_FP87,
2320 .features[FEAT_1_ECX] =
2321 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2322 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2323 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2324 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2325 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2326 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2327 .features[FEAT_8000_0001_EDX] =
2328 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2329 CPUID_EXT2_SYSCALL,
2330 .features[FEAT_8000_0001_ECX] =
2331 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2332 .features[FEAT_7_0_EBX] =
2333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2334 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2335 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2336 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2337 CPUID_7_0_EBX_SMAP,
f6f949e9 2338 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2339 * including v4.1 to v4.12).
f6f949e9
EH		 2340 * KVM doesn't yet expose any XSAVES state save component,
2341 * and the only one defined in Skylake (processor tracing)
2342 * probably will block migration anyway.
2343 */
2344 .features[FEAT_XSAVE] =
2345 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2346 CPUID_XSAVE_XGETBV1,
2347 .features[FEAT_6_EAX] =
2348 CPUID_6_EAX_ARAT,
2349 .xlevel = 0x80000008,
2350 .model_id = "Intel Core Processor (Skylake)",
2351 },
ac96c413
EH		 2352 {
2353 .name = "Skylake-Client-IBRS",
2354 .level = 0xd,
2355 .vendor = CPUID_VENDOR_INTEL,
2356 .family = 6,
2357 .model = 94,
2358 .stepping = 3,
2359 .features[FEAT_1_EDX] =
2360 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2361 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2362 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2363 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2364 CPUID_DE | CPUID_FP87,
2365 .features[FEAT_1_ECX] =
2366 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2367 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2368 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2369 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2370 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2371 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2372 .features[FEAT_8000_0001_EDX] =
2373 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2374 CPUID_EXT2_SYSCALL,
2375 .features[FEAT_8000_0001_ECX] =
2376 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2377 .features[FEAT_7_0_EDX] =
2378 CPUID_7_0_EDX_SPEC_CTRL,
2379 .features[FEAT_7_0_EBX] =
2380 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2381 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2382 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2383 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2384 CPUID_7_0_EBX_SMAP,
ac96c413
EH		 2385 /* Missing: XSAVES (not supported by some Linux versions,
2386 * including v4.1 to v4.12).
2387 * KVM doesn't yet expose any XSAVES state save component,
2388 * and the only one defined in Skylake (processor tracing)
2389 * probably will block migration anyway.
2390 */
2391 .features[FEAT_XSAVE] =
2392 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2393 CPUID_XSAVE_XGETBV1,
2394 .features[FEAT_6_EAX] =
2395 CPUID_6_EAX_ARAT,
2396 .xlevel = 0x80000008,
2397 .model_id = "Intel Core Processor (Skylake, IBRS)",
2398 },
53f9a6f4
BF		 2399 {
2400 .name = "Skylake-Server",
2401 .level = 0xd,
2402 .vendor = CPUID_VENDOR_INTEL,
2403 .family = 6,
2404 .model = 85,
2405 .stepping = 4,
2406 .features[FEAT_1_EDX] =
2407 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2408 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2409 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2410 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2411 CPUID_DE | CPUID_FP87,
2412 .features[FEAT_1_ECX] =
2413 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2414 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2415 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2416 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2417 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2418 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2419 .features[FEAT_8000_0001_EDX] =
2420 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2421 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2422 .features[FEAT_8000_0001_ECX] =
2423 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2424 .features[FEAT_7_0_EBX] =
2425 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2426 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2427 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2428 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2429 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2430 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2431 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2432 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2433 .features[FEAT_7_0_ECX] =
2434 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2435 /* Missing: XSAVES (not supported by some Linux versions,
2436 * including v4.1 to v4.12).
2437 * KVM doesn't yet expose any XSAVES state save component,
2438 * and the only one defined in Skylake (processor tracing)
2439 * probably will block migration anyway.
2440 */
2441 .features[FEAT_XSAVE] =
2442 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2443 CPUID_XSAVE_XGETBV1,
2444 .features[FEAT_6_EAX] =
2445 CPUID_6_EAX_ARAT,
2446 .xlevel = 0x80000008,
2447 .model_id = "Intel Xeon Processor (Skylake)",
2448 },
ac96c413
EH		 2449 {
2450 .name = "Skylake-Server-IBRS",
2451 .level = 0xd,
2452 .vendor = CPUID_VENDOR_INTEL,
2453 .family = 6,
2454 .model = 85,
2455 .stepping = 4,
2456 .features[FEAT_1_EDX] =
2457 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2458 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2459 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2460 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2461 CPUID_DE | CPUID_FP87,
2462 .features[FEAT_1_ECX] =
2463 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2464 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2465 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2466 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2467 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2468 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2469 .features[FEAT_8000_0001_EDX] =
2470 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2471 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2472 .features[FEAT_8000_0001_ECX] =
2473 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2474 .features[FEAT_7_0_EDX] =
2475 CPUID_7_0_EDX_SPEC_CTRL,
2476 .features[FEAT_7_0_EBX] =
2477 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2478 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2479 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2480 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2481 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
ac96c413
EH		 2482 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2483 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2484 CPUID_7_0_EBX_AVX512VL,
09b9ee64
TX		 2485 .features[FEAT_7_0_ECX] =
2486 CPUID_7_0_ECX_PKU,
ac96c413
EH		 2487 /* Missing: XSAVES (not supported by some Linux versions,
2488 * including v4.1 to v4.12).
2489 * KVM doesn't yet expose any XSAVES state save component,
2490 * and the only one defined in Skylake (processor tracing)
2491 * probably will block migration anyway.
2492 */
2493 .features[FEAT_XSAVE] =
2494 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2495 CPUID_XSAVE_XGETBV1,
2496 .features[FEAT_6_EAX] =
2497 CPUID_6_EAX_ARAT,
2498 .xlevel = 0x80000008,
2499 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2500 },
c7a88b52
TX		 2501 {
2502 .name = "Cascadelake-Server",
2503 .level = 0xd,
2504 .vendor = CPUID_VENDOR_INTEL,
2505 .family = 6,
2506 .model = 85,
b0a19803 2507 .stepping = 6,
c7a88b52
TX		 2508 .features[FEAT_1_EDX] =
2509 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2510 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2511 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2512 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2513 CPUID_DE | CPUID_FP87,
2514 .features[FEAT_1_ECX] =
2515 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2516 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2517 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2518 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2519 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2520 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2521 .features[FEAT_8000_0001_EDX] =
2522 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2523 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2524 .features[FEAT_8000_0001_ECX] =
2525 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2526 .features[FEAT_7_0_EBX] =
2527 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2528 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2529 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2530 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2531 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 2532 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2533 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2534 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 2535 .features[FEAT_7_0_ECX] =
bb4928c7 2536 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 2537 CPUID_7_0_ECX_AVX512VNNI,
2538 .features[FEAT_7_0_EDX] =
2539 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2540 /* Missing: XSAVES (not supported by some Linux versions,
2541 * including v4.1 to v4.12).
2542 * KVM doesn't yet expose any XSAVES state save component,
2543 * and the only one defined in Skylake (processor tracing)
2544 * probably will block migration anyway.
2545 */
2546 .features[FEAT_XSAVE] =
2547 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2548 CPUID_XSAVE_XGETBV1,
2549 .features[FEAT_6_EAX] =
2550 CPUID_6_EAX_ARAT,
2551 .xlevel = 0x80000008,
2552 .model_id = "Intel Xeon Processor (Cascadelake)",
2553 },
8a11c62d
RH		 2554 {
2555 .name = "Icelake-Client",
2556 .level = 0xd,
2557 .vendor = CPUID_VENDOR_INTEL,
2558 .family = 6,
2559 .model = 126,
2560 .stepping = 0,
2561 .features[FEAT_1_EDX] =
2562 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2563 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2564 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2565 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2566 CPUID_DE | CPUID_FP87,
2567 .features[FEAT_1_ECX] =
2568 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2569 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2570 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2571 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2572 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2573 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2574 .features[FEAT_8000_0001_EDX] =
2575 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2576 CPUID_EXT2_SYSCALL,
2577 .features[FEAT_8000_0001_ECX] =
2578 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2579 .features[FEAT_8000_0008_EBX] =
2580 CPUID_8000_0008_EBX_WBNOINVD,
2581 .features[FEAT_7_0_EBX] =
2582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 2586 CPUID_7_0_EBX_SMAP,
8a11c62d
RH		 2587 .features[FEAT_7_0_ECX] =
2588 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2589 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2590 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2591 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2592 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2593 .features[FEAT_7_0_EDX] =
2594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2595 /* Missing: XSAVES (not supported by some Linux versions,
2596 * including v4.1 to v4.12).
2597 * KVM doesn't yet expose any XSAVES state save component,
2598 * and the only one defined in Skylake (processor tracing)
2599 * probably will block migration anyway.
2600 */
2601 .features[FEAT_XSAVE] =
2602 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2603 CPUID_XSAVE_XGETBV1,
2604 .features[FEAT_6_EAX] =
2605 CPUID_6_EAX_ARAT,
2606 .xlevel = 0x80000008,
2607 .model_id = "Intel Core Processor (Icelake)",
2608 },
2609 {
2610 .name = "Icelake-Server",
2611 .level = 0xd,
2612 .vendor = CPUID_VENDOR_INTEL,
2613 .family = 6,
2614 .model = 134,
2615 .stepping = 0,
2616 .features[FEAT_1_EDX] =
2617 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2618 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2619 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2620 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2621 CPUID_DE | CPUID_FP87,
2622 .features[FEAT_1_ECX] =
2623 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2624 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2625 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2626 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2627 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2628 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2629 .features[FEAT_8000_0001_EDX] =
2630 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2631 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2632 .features[FEAT_8000_0001_ECX] =
2633 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2634 .features[FEAT_8000_0008_EBX] =
2635 CPUID_8000_0008_EBX_WBNOINVD,
2636 .features[FEAT_7_0_EBX] =
2637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2638 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2639 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2640 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2641 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 2642 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2643 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 2644 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d
RH		 2645 .features[FEAT_7_0_ECX] =
2646 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
bb4928c7 2647 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 2648 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2649 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2650 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2651 .features[FEAT_7_0_EDX] =
76e5a4d5 2652 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 2653 /* Missing: XSAVES (not supported by some Linux versions,
2654 * including v4.1 to v4.12).
2655 * KVM doesn't yet expose any XSAVES state save component,
2656 * and the only one defined in Skylake (processor tracing)
2657 * probably will block migration anyway.
2658 */
2659 .features[FEAT_XSAVE] =
2660 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2661 CPUID_XSAVE_XGETBV1,
2662 .features[FEAT_6_EAX] =
2663 CPUID_6_EAX_ARAT,
2664 .xlevel = 0x80000008,
2665 .model_id = "Intel Xeon Processor (Icelake)",
2666 },
a1849515
BF		 2667 {
2668 .name = "KnightsMill",
2669 .level = 0xd,
2670 .vendor = CPUID_VENDOR_INTEL,
2671 .family = 6,
2672 .model = 133,
2673 .stepping = 0,
2674 .features[FEAT_1_EDX] =
2675 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2676 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2677 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2678 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2679 CPUID_PSE | CPUID_DE | CPUID_FP87,
2680 .features[FEAT_1_ECX] =
2681 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2682 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2683 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2684 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2685 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2686 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2687 .features[FEAT_8000_0001_EDX] =
2688 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2689 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2690 .features[FEAT_8000_0001_ECX] =
2691 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2692 .features[FEAT_7_0_EBX] =
2693 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2694 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2695 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2696 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2697 CPUID_7_0_EBX_AVX512ER,
2698 .features[FEAT_7_0_ECX] =
2699 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2700 .features[FEAT_7_0_EDX] =
2701 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2702 .features[FEAT_XSAVE] =
2703 CPUID_XSAVE_XSAVEOPT,
2704 .features[FEAT_6_EAX] =
2705 CPUID_6_EAX_ARAT,
2706 .xlevel = 0x80000008,
2707 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2708 },
3eca4642
EH		 2709 {
2710 .name = "Opteron_G1",
2711 .level = 5,
99b88a17 2712 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2713 .family = 15,
2714 .model = 6,
2715 .stepping = 1,
0514ef2f 2716 .features[FEAT_1_EDX] =
b3a4f0b1 2717 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2721 CPUID_DE | CPUID_FP87,
0514ef2f 2722 .features[FEAT_1_ECX] =
27861ecc 2723 CPUID_EXT_SSE3,
0514ef2f 2724 .features[FEAT_8000_0001_EDX] =
2a923a29 2725 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 2726 .xlevel = 0x80000008,
2727 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2728 },
2729 {
2730 .name = "Opteron_G2",
2731 .level = 5,
99b88a17 2732 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2733 .family = 15,
2734 .model = 6,
2735 .stepping = 1,
0514ef2f 2736 .features[FEAT_1_EDX] =
b3a4f0b1 2737 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2738 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2739 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2740 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2741 CPUID_DE | CPUID_FP87,
0514ef2f 2742 .features[FEAT_1_ECX] =
27861ecc 2743 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 2744 .features[FEAT_8000_0001_EDX] =
2a923a29 2745 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2746 .features[FEAT_8000_0001_ECX] =
27861ecc 2747 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2748 .xlevel = 0x80000008,
2749 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2750 },
2751 {
2752 .name = "Opteron_G3",
2753 .level = 5,
99b88a17 2754 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 2755 .family = 16,
2756 .model = 2,
2757 .stepping = 3,
0514ef2f 2758 .features[FEAT_1_EDX] =
b3a4f0b1 2759 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2760 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2761 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2762 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2763 CPUID_DE | CPUID_FP87,
0514ef2f 2764 .features[FEAT_1_ECX] =
27861ecc 2765 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 2766 CPUID_EXT_SSE3,
0514ef2f 2767 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 2768 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2769 CPUID_EXT2_RDTSCP,
0514ef2f 2770 .features[FEAT_8000_0001_ECX] =
27861ecc 2771 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 2772 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 2773 .xlevel = 0x80000008,
2774 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2775 },
2776 {
2777 .name = "Opteron_G4",
2778 .level = 0xd,
99b88a17 2779 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 2780 .family = 21,
2781 .model = 1,
2782 .stepping = 2,
0514ef2f 2783 .features[FEAT_1_EDX] =
b3a4f0b1 2784 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2788 CPUID_DE | CPUID_FP87,
0514ef2f 2789 .features[FEAT_1_ECX] =
27861ecc 2790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2791 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2792 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2793 CPUID_EXT_SSE3,
0514ef2f 2794 .features[FEAT_8000_0001_EDX] =
2a923a29 2795 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2796 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2797 .features[FEAT_8000_0001_ECX] =
27861ecc 2798 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2799 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2800 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2801 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2802 .features[FEAT_SVM] =
2803 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2804 /* no xsaveopt! */
3eca4642
EH		 2805 .xlevel = 0x8000001A,
2806 .model_id = "AMD Opteron 62xx class CPU",
2807 },
021941b9
AP		 2808 {
2809 .name = "Opteron_G5",
2810 .level = 0xd,
99b88a17 2811 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 2812 .family = 21,
2813 .model = 2,
2814 .stepping = 0,
0514ef2f 2815 .features[FEAT_1_EDX] =
b3a4f0b1 2816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2820 CPUID_DE | CPUID_FP87,
0514ef2f 2821 .features[FEAT_1_ECX] =
27861ecc 2822 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 2823 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2824 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2825 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2826 .features[FEAT_8000_0001_EDX] =
2a923a29 2827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 2828 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 2829 .features[FEAT_8000_0001_ECX] =
27861ecc 2830 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 2831 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2832 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2833 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 2834 .features[FEAT_SVM] =
2835 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 2836 /* no xsaveopt! */
021941b9
AP		 2837 .xlevel = 0x8000001A,
2838 .model_id = "AMD Opteron 63xx class CPU",
2839 },
2e2efc7d
BS		 2840 {
2841 .name = "EPYC",
2842 .level = 0xd,
2843 .vendor = CPUID_VENDOR_AMD,
2844 .family = 23,
2845 .model = 1,
2846 .stepping = 2,
2847 .features[FEAT_1_EDX] =
2848 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2849 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2850 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2851 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2852 CPUID_VME | CPUID_FP87,
2853 .features[FEAT_1_ECX] =
2854 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2855 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2856 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2857 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2858 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2859 .features[FEAT_8000_0001_EDX] =
2860 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2861 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2862 CPUID_EXT2_SYSCALL,
2863 .features[FEAT_8000_0001_ECX] =
2864 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2865 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2866 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2867 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 2868 .features[FEAT_7_0_EBX] =
2869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2870 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2871 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2872 CPUID_7_0_EBX_SHA_NI,
2873 /* Missing: XSAVES (not supported by some Linux versions,
2874 * including v4.1 to v4.12).
2875 * KVM doesn't yet expose any XSAVES state save component.
2876 */
2877 .features[FEAT_XSAVE] =
2878 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2879 CPUID_XSAVE_XGETBV1,
2880 .features[FEAT_6_EAX] =
2881 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2882 .features[FEAT_SVM] =
2883 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2884 .xlevel = 0x8000001E,
2e2efc7d 2885 .model_id = "AMD EPYC Processor",
fe52acd2 2886 .cache_info = &epyc_cache_info,
2e2efc7d 2887 },
6cfbc54e
EH		 2888 {
2889 .name = "EPYC-IBPB",
2890 .level = 0xd,
2891 .vendor = CPUID_VENDOR_AMD,
2892 .family = 23,
2893 .model = 1,
2894 .stepping = 2,
2895 .features[FEAT_1_EDX] =
2896 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2897 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2898 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2899 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2900 CPUID_VME | CPUID_FP87,
2901 .features[FEAT_1_ECX] =
2902 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2903 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2904 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2905 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2906 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2907 .features[FEAT_8000_0001_EDX] =
2908 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2909 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2910 CPUID_EXT2_SYSCALL,
2911 .features[FEAT_8000_0001_ECX] =
2912 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2913 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 2914 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2915 CPUID_EXT3_TOPOEXT,
6cfbc54e
EH		 2916 .features[FEAT_8000_0008_EBX] =
2917 CPUID_8000_0008_EBX_IBPB,
2918 .features[FEAT_7_0_EBX] =
2919 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2920 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2921 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2922 CPUID_7_0_EBX_SHA_NI,
2923 /* Missing: XSAVES (not supported by some Linux versions,
2924 * including v4.1 to v4.12).
2925 * KVM doesn't yet expose any XSAVES state save component.
2926 */
2927 .features[FEAT_XSAVE] =
2928 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2929 CPUID_XSAVE_XGETBV1,
2930 .features[FEAT_6_EAX] =
2931 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 2932 .features[FEAT_SVM] =
2933 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 2934 .xlevel = 0x8000001E,
6cfbc54e 2935 .model_id = "AMD EPYC Processor (with IBPB)",
fe52acd2 2936 .cache_info = &epyc_cache_info,
6cfbc54e 2937 },
c6dc6f63
AP		 2938};
2939
5114e842
EH		 2940typedef struct PropValue {
2941 const char *prop, *value;
2942} PropValue;
2943
2944/* KVM-specific features that are automatically added/removed
2945 * from all CPU models when KVM is enabled.
2946 */
2947static PropValue kvm_default_props[] = {
2948 { "kvmclock", "on" },
2949 { "kvm-nopiodelay", "on" },
2950 { "kvm-asyncpf", "on" },
2951 { "kvm-steal-time", "on" },
2952 { "kvm-pv-eoi", "on" },
2953 { "kvmclock-stable-bit", "on" },
2954 { "x2apic", "on" },
2955 { "acpi", "off" },
2956 { "monitor", "off" },
2957 { "svm", "off" },
2958 { NULL, NULL },
2959};
2960
04d99c3c
EH		 2961/* TCG-specific defaults that override all CPU models when using TCG
2962 */
2963static PropValue tcg_default_props[] = {
2964 { "vme", "off" },
2965 { NULL, NULL },
2966};
2967
2968
5114e842
EH		 2969void x86_cpu_change_kvm_default(const char *prop, const char *value)
2970{
2971 PropValue *pv;
2972 for (pv = kvm_default_props; pv->prop; pv++) {
2973 if (!strcmp(pv->prop, prop)) {
2974 pv->value = value;
2975 break;
2976 }
2977 }
2978
2979 /* It is valid to call this function only for properties that
2980 * are already present in the kvm_default_props table.
2981 */
2982 assert(pv->prop);
2983}
2984
4d1b279b
EH		 2985static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2986 bool migratable_only);
2987
40bfe48f
HZ		 2988static bool lmce_supported(void)
2989{
c62f2630 2990 uint64_t mce_cap = 0;
40bfe48f 2991
c62f2630 2992#ifdef CONFIG_KVM
40bfe48f
HZ		 2993 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2994 return false;
2995 }
c62f2630 2996#endif
40bfe48f
HZ		 2997
2998 return !!(mce_cap & MCG_LMCE_P);
2999}
3000
7d8050b5
EH		 3001#define CPUID_MODEL_ID_SZ 48
3002
3003/**
3004 * cpu_x86_fill_model_id:
3005 * Get CPUID model ID string from host CPU.
3006 *
3007 * @str should have at least CPUID_MODEL_ID_SZ bytes
3008 *
3009 * The function does NOT add a null terminator to the string
3010 * automatically.
3011 */
c6dc6f63
AP		 3012static int cpu_x86_fill_model_id(char *str)
3013{
3014 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3015 int i;
3016
3017 for (i = 0; i < 3; i++) {
3018 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3019 memcpy(str + i * 16 + 0, &eax, 4);
3020 memcpy(str + i * 16 + 4, &ebx, 4);
3021 memcpy(str + i * 16 + 8, &ecx, 4);
3022 memcpy(str + i * 16 + 12, &edx, 4);
3023 }
3024 return 0;
3025}
3026
c62f2630 3027static Property max_x86_cpu_properties[] = {
120eee7d 3028 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 3029 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 3030 DEFINE_PROP_END_OF_LIST()
3031};
3032
c62f2630 3033static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 3034{
84f1b92f 3035 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 3036 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 3037
f48c8837 3038 xcc->ordering = 9;
6e746f30 3039
ee465a3e 3040 xcc->model_description =
c62f2630 3041 "Enables all features supported by the accelerator in the current host";
d940ee9b 3042
c62f2630 3043 dc->props = max_x86_cpu_properties;
d940ee9b
EH		 3044}
3045
0bacd8b3
EH		 3046static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3047
c62f2630 3048static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 3049{
3050 X86CPU *cpu = X86_CPU(obj);
3051 CPUX86State *env = &cpu->env;
3052 KVMState *s = kvm_state;
d940ee9b 3053
4d1b279b
EH		 3054 /* We can't fill the features array here because we don't know yet if
3055 * "migratable" is true or false.
3056 */
44bd8e53 3057 cpu->max_features = true;
4d1b279b 3058
d6dcc558 3059 if (accel_uses_host_cpuid()) {
bd182022
EH		 3060 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3061 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3062 int family, model, stepping;
d6dcc558
SAGDR		 3063 X86CPUDefinition host_cpudef = { };
3064 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3065
3066 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3067 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
0bacd8b3 3068
bd182022 3069 host_vendor_fms(vendor, &family, &model, &stepping);
0bacd8b3 3070
bd182022 3071 cpu_x86_fill_model_id(model_id);
0bacd8b3 3072
bd182022
EH		 3073 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3074 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3075 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3076 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3077 &error_abort);
3078 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3079 &error_abort);
0bacd8b3 3080
d6dcc558
SAGDR		 3081 if (kvm_enabled()) {
3082 env->cpuid_min_level =
3083 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3084 env->cpuid_min_xlevel =
3085 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3086 env->cpuid_min_xlevel2 =
3087 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3088 } else {
3089 env->cpuid_min_level =
3090 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3091 env->cpuid_min_xlevel =
3092 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3093 env->cpuid_min_xlevel2 =
3094 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3095 }
40bfe48f
HZ		 3096
3097 if (lmce_supported()) {
3098 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3099 }
6900d1cc
EH		 3100 } else {
3101 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3102 "vendor", &error_abort);
3103 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3104 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3105 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3106 object_property_set_str(OBJECT(cpu),
3107 "QEMU TCG CPU version " QEMU_HW_VERSION,
3108 "model-id", &error_abort);
e4356010 3109 }
2a573259 3110
d940ee9b 3111 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 3112}
3113
c62f2630
EH		 3114static const TypeInfo max_x86_cpu_type_info = {
3115 .name = X86_CPU_TYPE_NAME("max"),
3116 .parent = TYPE_X86_CPU,
3117 .instance_init = max_x86_cpu_initfn,
3118 .class_init = max_x86_cpu_class_init,
3119};
3120
d6dcc558 3121#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 3122static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3123{
3124 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3125
d6dcc558 3126 xcc->host_cpuid_required = true;
c62f2630
EH		 3127 xcc->ordering = 8;
3128
02693cc4
GK		 3129#if defined(CONFIG_KVM)
3130 xcc->model_description =
3131 "KVM processor with all supported host features ";
3132#elif defined(CONFIG_HVF)
3133 xcc->model_description =
3134 "HVF processor with all supported host features ";
3135#endif
c62f2630
EH		 3136}
3137
d940ee9b
EH		 3138static const TypeInfo host_x86_cpu_type_info = {
3139 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 3140 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 3141 .class_init = host_x86_cpu_class_init,
3142};
3143
3144#endif
3145
07585923
RH		 3146static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3147{
3148 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3149
3150 switch (f->type) {
3151 case CPUID_FEATURE_WORD:
3152 {
3153 const char *reg = get_register_name_32(f->cpuid.reg);
3154 assert(reg);
3155 return g_strdup_printf("CPUID.%02XH:%s",
3156 f->cpuid.eax, reg);
3157 }
3158 case MSR_FEATURE_WORD:
3159 return g_strdup_printf("MSR(%02XH)",
3160 f->msr.index);
3161 }
3162
3163 return NULL;
3164}
3165
8459e396 3166static void report_unavailable_features(FeatureWord w, uint32_t mask)
c6dc6f63 3167{
8459e396 3168 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63 3169 int i;
07585923 3170 char *feat_word_str;
c6dc6f63 3171
857aee33 3172 for (i = 0; i < 32; ++i) {
72370dc1 3173 if ((1UL << i) & mask) {
07585923
RH		 3174 feat_word_str = feature_word_description(f, i);
3175 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
d6dcc558 3176 accel_uses_host_cpuid() ? "host" : "TCG",
07585923 3177 feat_word_str,
8297be80
AF		 3178 f->feat_names[i] ? "." : "",
3179 f->feat_names[i] ? f->feat_names[i] : "", i);
07585923 3180 g_free(feat_word_str);
c6dc6f63 3181 }
857aee33 3182 }
c6dc6f63
AP		 3183}
3184
d7bce999
EB		 3185static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3186 const char *name, void *opaque,
3187 Error **errp)
95b8519d
AF		 3188{
3189 X86CPU *cpu = X86_CPU(obj);
3190 CPUX86State *env = &cpu->env;
3191 int64_t value;
3192
3193 value = (env->cpuid_version >> 8) & 0xf;
3194 if (value == 0xf) {
3195 value += (env->cpuid_version >> 20) & 0xff;
3196 }
51e72bc1 3197 visit_type_int(v, name, &value, errp);
95b8519d
AF		 3198}
3199
d7bce999
EB		 3200static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3201 const char *name, void *opaque,
3202 Error **errp)
ed5e1ec3 3203{
71ad61d3
AF		 3204 X86CPU *cpu = X86_CPU(obj);
3205 CPUX86State *env = &cpu->env;
3206 const int64_t min = 0;
3207 const int64_t max = 0xff + 0xf;
65cd9064 3208 Error *local_err = NULL;
71ad61d3
AF		 3209 int64_t value;
3210
51e72bc1 3211 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3212 if (local_err) {
3213 error_propagate(errp, local_err);
71ad61d3
AF		 3214 return;
3215 }
3216 if (value < min || value > max) {
c6bd8c70
MA		 3217 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3218 name ? name : "null", value, min, max);
71ad61d3
AF		 3219 return;
3220 }
3221
ed5e1ec3 3222 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 3223 if (value > 0x0f) {
3224 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 3225 } else {
71ad61d3 3226 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 3227 }
3228}
3229
d7bce999
EB		 3230static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3231 const char *name, void *opaque,
3232 Error **errp)
67e30c83
AF		 3233{
3234 X86CPU *cpu = X86_CPU(obj);
3235 CPUX86State *env = &cpu->env;
3236 int64_t value;
3237
3238 value = (env->cpuid_version >> 4) & 0xf;
3239 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 3240 visit_type_int(v, name, &value, errp);
67e30c83
AF		 3241}
3242
d7bce999
EB		 3243static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3244 const char *name, void *opaque,
3245 Error **errp)
b0704cbd 3246{
c5291a4f
AF		 3247 X86CPU *cpu = X86_CPU(obj);
3248 CPUX86State *env = &cpu->env;
3249 const int64_t min = 0;
3250 const int64_t max = 0xff;
65cd9064 3251 Error *local_err = NULL;
c5291a4f
AF		 3252 int64_t value;
3253
51e72bc1 3254 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3255 if (local_err) {
3256 error_propagate(errp, local_err);
c5291a4f
AF		 3257 return;
3258 }
3259 if (value < min || value > max) {
c6bd8c70
MA		 3260 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3261 name ? name : "null", value, min, max);
c5291a4f
AF		 3262 return;
3263 }
3264
b0704cbd 3265 env->cpuid_version &= ~0xf00f0;
c5291a4f 3266 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 3267}
3268
35112e41 3269static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 3270 const char *name, void *opaque,
35112e41
AF		 3271 Error **errp)
3272{
3273 X86CPU *cpu = X86_CPU(obj);
3274 CPUX86State *env = &cpu->env;
3275 int64_t value;
3276
3277 value = env->cpuid_version & 0xf;
51e72bc1 3278 visit_type_int(v, name, &value, errp);
35112e41
AF		 3279}
3280
036e2222 3281static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 3282 const char *name, void *opaque,
036e2222 3283 Error **errp)
38c3dc46 3284{
036e2222
AF		 3285 X86CPU *cpu = X86_CPU(obj);
3286 CPUX86State *env = &cpu->env;
3287 const int64_t min = 0;
3288 const int64_t max = 0xf;
65cd9064 3289 Error *local_err = NULL;
036e2222
AF		 3290 int64_t value;
3291
51e72bc1 3292 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3293 if (local_err) {
3294 error_propagate(errp, local_err);
036e2222
AF		 3295 return;
3296 }
3297 if (value < min || value > max) {
c6bd8c70
MA		 3298 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3299 name ? name : "null", value, min, max);
036e2222
AF		 3300 return;
3301 }
3302
38c3dc46 3303 env->cpuid_version &= ~0xf;
036e2222 3304 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 3305}
3306
d480e1af
AF		 3307static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3308{
3309 X86CPU *cpu = X86_CPU(obj);
3310 CPUX86State *env = &cpu->env;
3311 char *value;
d480e1af 3312
e42a92ae 3313 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 3314 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3315 env->cpuid_vendor3);
d480e1af
AF		 3316 return value;
3317}
3318
3319static void x86_cpuid_set_vendor(Object *obj, const char *value,
3320 Error **errp)
3321{
3322 X86CPU *cpu = X86_CPU(obj);
3323 CPUX86State *env = &cpu->env;
3324 int i;
3325
9df694ee 3326 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 3327 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 3328 return;
3329 }
3330
3331 env->cpuid_vendor1 = 0;
3332 env->cpuid_vendor2 = 0;
3333 env->cpuid_vendor3 = 0;
3334 for (i = 0; i < 4; i++) {
3335 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3336 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3337 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3338 }
d480e1af
AF		 3339}
3340
63e886eb
AF		 3341static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3342{
3343 X86CPU *cpu = X86_CPU(obj);
3344 CPUX86State *env = &cpu->env;
3345 char *value;
3346 int i;
3347
3348 value = g_malloc(48 + 1);
3349 for (i = 0; i < 48; i++) {
3350 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3351 }
3352 value[48] = '\0';
3353 return value;
3354}
3355
938d4c25
AF		 3356static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3357 Error **errp)
dcce6675 3358{
938d4c25
AF		 3359 X86CPU *cpu = X86_CPU(obj);
3360 CPUX86State *env = &cpu->env;
dcce6675
AF		 3361 int c, len, i;
3362
3363 if (model_id == NULL) {
3364 model_id = "";
3365 }
3366 len = strlen(model_id);
d0a6acf4 3367 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 3368 for (i = 0; i < 48; i++) {
3369 if (i >= len) {
3370 c = '\0';
3371 } else {
3372 c = (uint8_t)model_id[i];
3373 }
3374 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3375 }
3376}
3377
d7bce999
EB		 3378static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3379 void *opaque, Error **errp)
89e48965
AF		 3380{
3381 X86CPU *cpu = X86_CPU(obj);
3382 int64_t value;
3383
3384 value = cpu->env.tsc_khz * 1000;
51e72bc1 3385 visit_type_int(v, name, &value, errp);
89e48965
AF		 3386}
3387
d7bce999
EB		 3388static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3389 void *opaque, Error **errp)
89e48965
AF		 3390{
3391 X86CPU *cpu = X86_CPU(obj);
3392 const int64_t min = 0;
2e84849a 3393 const int64_t max = INT64_MAX;
65cd9064 3394 Error *local_err = NULL;
89e48965
AF		 3395 int64_t value;
3396
51e72bc1 3397 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 3398 if (local_err) {
3399 error_propagate(errp, local_err);
89e48965
AF		 3400 return;
3401 }
3402 if (value < min || value > max) {
c6bd8c70
MA		 3403 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3404 name ? name : "null", value, min, max);
89e48965
AF		 3405 return;
3406 }
3407
36f96c4b 3408 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 3409}
3410
7e5292b5 3411/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 3412static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3413 const char *name, void *opaque,
3414 Error **errp)
8e8aba50 3415{
7e5292b5 3416 uint32_t *array = (uint32_t *)opaque;
8e8aba50 3417 FeatureWord w;
8e8aba50
EH		 3418 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3419 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3420 X86CPUFeatureWordInfoList *list = NULL;
3421
3422 for (w = 0; w < FEATURE_WORDS; w++) {
3423 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 3424 /*
3425 * We didn't have MSR features when "feature-words" was
3426 * introduced. Therefore skipped other type entries.
3427 */
3428 if (wi->type != CPUID_FEATURE_WORD) {
3429 continue;
3430 }
8e8aba50 3431 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 3432 qwi->cpuid_input_eax = wi->cpuid.eax;
3433 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3434 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3435 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 3436 qwi->features = array[w];
8e8aba50
EH		 3437
3438 /* List will be in reverse order, but order shouldn't matter */
3439 list_entries[w].next = list;
3440 list_entries[w].value = &word_infos[w];
3441 list = &list_entries[w];
3442 }
3443
6b62d961 3444 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 3445}
3446
d7bce999
EB		 3447static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3448 void *opaque, Error **errp)
c8f0f88e
IM		 3449{
3450 X86CPU *cpu = X86_CPU(obj);
3451 int64_t value = cpu->hyperv_spinlock_attempts;
3452
51e72bc1 3453 visit_type_int(v, name, &value, errp);
c8f0f88e
IM		 3454}
3455
d7bce999
EB		 3456static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3457 void *opaque, Error **errp)
c8f0f88e
IM		 3458{
3459 const int64_t min = 0xFFF;
3460 const int64_t max = UINT_MAX;
3461 X86CPU *cpu = X86_CPU(obj);
3462 Error *err = NULL;
3463 int64_t value;
3464
51e72bc1 3465 visit_type_int(v, name, &value, &err);
c8f0f88e
IM		 3466 if (err) {
3467 error_propagate(errp, err);
3468 return;
3469 }
3470
3471 if (value < min || value > max) {
3472 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
5bb4c35d 3473 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3474 object_get_typename(obj), name ? name : "null",
3475 value, min, max);
c8f0f88e
IM		 3476 return;
3477 }
3478 cpu->hyperv_spinlock_attempts = value;
3479}
3480
1b6b7d10 3481static const PropertyInfo qdev_prop_spinlocks = {
c8f0f88e
IM		 3482 .name = "int",
3483 .get = x86_get_hv_spinlocks,
3484 .set = x86_set_hv_spinlocks,
3485};
3486
72ac2e87
IM		 3487/* Convert all '_' in a feature string option name to '-', to make feature
3488 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3489 */
3490static inline void feat2prop(char *s)
3491{
3492 while ((s = strchr(s, '_'))) {
3493 *s = '-';
3494 }
3495}
3496
b54c9377
EH		 3497/* Return the feature property name for a feature flag bit */
3498static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3499{
3500 /* XSAVE components are automatically enabled by other features,
3501 * so return the original feature name instead
3502 */
3503 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3504 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3505
3506 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3507 x86_ext_save_areas[comp].bits) {
3508 w = x86_ext_save_areas[comp].feature;
3509 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3510 }
3511 }
3512
3513 assert(bitnr < 32);
3514 assert(w < FEATURE_WORDS);
3515 return feature_word_info[w].feat_names[bitnr];
3516}
3517
dc15c051
IM		 3518/* Compatibily hack to maintain legacy +-feat semantic,
3519 * where +-feat overwrites any feature set by
3520 * feat=on|feat even if the later is parsed after +-feat
3521 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3522 */
2fae0d96 3523static GList *plus_features, *minus_features;
dc15c051 3524
83a00f60
EH		 3525static gint compare_string(gconstpointer a, gconstpointer b)
3526{
3527 return g_strcmp0(a, b);
3528}
3529
8f961357
EH		 3530/* Parse "+feature,-feature,feature=foo" CPU feature string
3531 */
62a48a2a 3532static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 3533 Error **errp)
8f961357 3534{
8f961357 3535 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 3536 static bool cpu_globals_initialized;
83a00f60 3537 bool ambiguous = false;
62a48a2a
IM		 3538
3539 if (cpu_globals_initialized) {
3540 return;
3541 }
3542 cpu_globals_initialized = true;
8f961357 3543
f6750e95
EH		 3544 if (!features) {
3545 return;
3546 }
3547
3548 for (featurestr = strtok(features, ",");
685479bd 3549 featurestr;
f6750e95
EH		 3550 featurestr = strtok(NULL, ",")) {
3551 const char *name;
3552 const char *val = NULL;
3553 char *eq = NULL;
cf2887c9 3554 char num[32];
62a48a2a 3555 GlobalProperty *prop;
c6dc6f63 3556
f6750e95 3557 /* Compatibility syntax: */
c6dc6f63 3558 if (featurestr[0] == '+') {
2fae0d96
EH		 3559 plus_features = g_list_append(plus_features,
3560 g_strdup(featurestr + 1));
f6750e95 3561 continue;
c6dc6f63 3562 } else if (featurestr[0] == '-') {
2fae0d96
EH		 3563 minus_features = g_list_append(minus_features,
3564 g_strdup(featurestr + 1));
f6750e95
EH		 3565 continue;
3566 }
3567
3568 eq = strchr(featurestr, '=');
3569 if (eq) {
3570 *eq++ = 0;
3571 val = eq;
c6dc6f63 3572 } else {
f6750e95 3573 val = "on";
a91987c2 3574 }
f6750e95
EH		 3575
3576 feat2prop(featurestr);
3577 name = featurestr;
3578
83a00f60 3579 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 3580 warn_report("Ambiguous CPU model string. "
3581 "Don't mix both \"+%s\" and \"%s=%s\"",
3582 name, name, val);
83a00f60
EH		 3583 ambiguous = true;
3584 }
3585 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 3586 warn_report("Ambiguous CPU model string. "
3587 "Don't mix both \"-%s\" and \"%s=%s\"",
3588 name, name, val);
83a00f60
EH		 3589 ambiguous = true;
3590 }
3591
f6750e95
EH		 3592 /* Special case: */
3593 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 3594 int ret;
f46bfdbf 3595 uint64_t tsc_freq;
f6750e95 3596
f17fd4fd 3597 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 3598 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 3599 error_setg(errp, "bad numerical value %s", val);
3600 return;
3601 }
3602 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3603 val = num;
3604 name = "tsc-frequency";
c6dc6f63 3605 }
f6750e95 3606
62a48a2a
IM		 3607 prop = g_new0(typeof(*prop), 1);
3608 prop->driver = typename;
3609 prop->property = g_strdup(name);
3610 prop->value = g_strdup(val);
62a48a2a 3611 qdev_prop_register_global(prop);
f6750e95
EH		 3612 }
3613
83a00f60 3614 if (ambiguous) {
3dc6f869
AF		 3615 warn_report("Compatibility of ambiguous CPU model "
3616 "strings won't be kept on future QEMU versions");
83a00f60 3617 }
c6dc6f63
AP		 3618}
3619
b8d834a0 3620static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
b54c9377
EH		 3621static int x86_cpu_filter_features(X86CPU *cpu);
3622
3623/* Check for missing features that may prevent the CPU class from
3624 * running using the current machine and accelerator.
3625 */
3626static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3627 strList **missing_feats)
3628{
3629 X86CPU *xc;
3630 FeatureWord w;
3631 Error *err = NULL;
3632 strList **next = missing_feats;
3633
d6dcc558 3634 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 3635 strList *new = g_new0(strList, 1);
3c254ab8 3636 new->value = g_strdup("kvm");
b54c9377
EH		 3637 *missing_feats = new;
3638 return;
3639 }
3640
3641 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3642
b8d834a0 3643 x86_cpu_expand_features(xc, &err);
b54c9377 3644 if (err) {
b8d834a0 3645 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 3646 * but in case it does, just report the model as not
3647 * runnable at all using the "type" property.
3648 */
3649 strList *new = g_new0(strList, 1);
3650 new->value = g_strdup("type");
3651 *next = new;
3652 next = &new->next;
3653 }
3654
3655 x86_cpu_filter_features(xc);
3656
3657 for (w = 0; w < FEATURE_WORDS; w++) {
3658 uint32_t filtered = xc->filtered_features[w];
3659 int i;
3660 for (i = 0; i < 32; i++) {
3661 if (filtered & (1UL << i)) {
3662 strList *new = g_new0(strList, 1);
3663 new->value = g_strdup(x86_cpu_feature_name(w, i));
3664 *next = new;
3665 next = &new->next;
3666 }
3667 }
3668 }
3669
3670 object_unref(OBJECT(xc));
3671}
3672
8c3329e5 3673/* Print all cpuid feature names in featureset
c6dc6f63 3674 */
0442428a 3675static void listflags(GList *features)
0856579c 3676{
cc643b1e
DB		 3677 size_t len = 0;
3678 GList *tmp;
3679
3680 for (tmp = features; tmp; tmp = tmp->next) {
3681 const char *name = tmp->data;
3682 if ((len + strlen(name) + 1) >= 75) {
0442428a 3683 qemu_printf("\n");
cc643b1e 3684 len = 0;
c6dc6f63 3685 }
0442428a 3686 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 3687 len += strlen(name) + 1;
8c3329e5 3688 }
0442428a 3689 qemu_printf("\n");
c6dc6f63
AP		 3690}
3691
f48c8837 3692/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 3693static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3694{
3695 ObjectClass *class_a = (ObjectClass *)a;
3696 ObjectClass *class_b = (ObjectClass *)b;
3697 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3698 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b
DB		 3699 char *name_a, *name_b;
3700 int ret;
ee465a3e 3701
f48c8837 3702 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 3703 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 3704 } else {
c7dbff4b
DB		 3705 name_a = x86_cpu_class_get_model_name(cc_a);
3706 name_b = x86_cpu_class_get_model_name(cc_b);
3707 ret = strcmp(name_a, name_b);
3708 g_free(name_a);
3709 g_free(name_b);
ee465a3e 3710 }
c7dbff4b 3711 return ret;
ee465a3e
EH		 3712}
3713
3714static GSList *get_sorted_cpu_model_list(void)
3715{
3716 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3717 list = g_slist_sort(list, x86_cpu_list_compare);
3718 return list;
3719}
3720
3721static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3722{
3723 ObjectClass *oc = data;
3724 X86CPUClass *cc = X86_CPU_CLASS(oc);
ee465a3e
EH		 3725 char *name = x86_cpu_class_get_model_name(cc);
3726 const char *desc = cc->model_description;
0bacd8b3 3727 if (!desc && cc->cpu_def) {
ee465a3e
EH		 3728 desc = cc->cpu_def->model_id;
3729 }
3730
0442428a 3731 qemu_printf("x86 %-20s %-48s\n", name, desc);
ee465a3e
EH		 3732 g_free(name);
3733}
3734
3735/* list available CPU models and flags */
0442428a 3736void x86_cpu_list(void)
c6dc6f63 3737{
cc643b1e 3738 int i, j;
ee465a3e 3739 GSList *list;
cc643b1e 3740 GList *names = NULL;
c6dc6f63 3741
0442428a 3742 qemu_printf("Available CPUs:\n");
ee465a3e 3743 list = get_sorted_cpu_model_list();
0442428a 3744 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 3745 g_slist_free(list);
21ad7789 3746
cc643b1e 3747 names = NULL;
3af60be2
JK		 3748 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3749 FeatureWordInfo *fw = &feature_word_info[i];
cc643b1e
DB		 3750 for (j = 0; j < 32; j++) {
3751 if (fw->feat_names[j]) {
3752 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3753 }
3754 }
3af60be2 3755 }
cc643b1e
DB		 3756
3757 names = g_list_sort(names, (GCompareFunc)strcmp);
3758
0442428a
MA		 3759 qemu_printf("\nRecognized CPUID flags:\n");
3760 listflags(names);
3761 qemu_printf("\n");
cc643b1e 3762 g_list_free(names);
c6dc6f63
AP		 3763}
3764
ee465a3e
EH		 3765static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3766{
3767 ObjectClass *oc = data;
3768 X86CPUClass *cc = X86_CPU_CLASS(oc);
3769 CpuDefinitionInfoList **cpu_list = user_data;
3770 CpuDefinitionInfoList *entry;
3771 CpuDefinitionInfo *info;
3772
3773 info = g_malloc0(sizeof(*info));
3774 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 3775 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3776 info->has_unavailable_features = true;
8ed877b7 3777 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 3778 info->migration_safe = cc->migration_safe;
3779 info->has_migration_safe = true;
5adbed30 3780 info->q_static = cc->static_model;
ee465a3e
EH		 3781
3782 entry = g_malloc0(sizeof(*entry));
3783 entry->value = info;
3784 entry->next = *cpu_list;
3785 *cpu_list = entry;
3786}
3787
25a9d6ca 3788CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 3789{
3790 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 3791 GSList *list = get_sorted_cpu_model_list();
3792 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3793 g_slist_free(list);
e3966126
AL		 3794 return cpu_list;
3795}
3796
84f1b92f
EH		 3797static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3798 bool migratable_only)
27418adf
EH		 3799{
3800 FeatureWordInfo *wi = &feature_word_info[w];
07585923 3801 uint32_t r = 0;
27418adf 3802
fefb41bf 3803 if (kvm_enabled()) {
07585923
RH		 3804 switch (wi->type) {
3805 case CPUID_FEATURE_WORD:
3806 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3807 wi->cpuid.ecx,
3808 wi->cpuid.reg);
3809 break;
3810 case MSR_FEATURE_WORD:
d86f9636
RH		 3811 r = kvm_arch_get_supported_msr_feature(kvm_state,
3812 wi->msr.index);
07585923
RH		 3813 break;
3814 }
d6dcc558 3815 } else if (hvf_enabled()) {
07585923
RH		 3816 if (wi->type != CPUID_FEATURE_WORD) {
3817 return 0;
3818 }
3819 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3820 wi->cpuid.ecx,
3821 wi->cpuid.reg);
fefb41bf 3822 } else if (tcg_enabled()) {
84f1b92f 3823 r = wi->tcg_features;
fefb41bf
EH		 3824 } else {
3825 return ~0;
3826 }
84f1b92f
EH		 3827 if (migratable_only) {
3828 r &= x86_cpu_get_migratable_flags(w);
3829 }
3830 return r;
27418adf
EH		 3831}
3832
8ca30e86
EH		 3833static void x86_cpu_report_filtered_features(X86CPU *cpu)
3834{
3835 FeatureWord w;
3836
3837 for (w = 0; w < FEATURE_WORDS; w++) {
3838 report_unavailable_features(w, cpu->filtered_features[w]);
3839 }
3840}
3841
5114e842
EH		 3842static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3843{
3844 PropValue *pv;
3845 for (pv = props; pv->prop; pv++) {
3846 if (!pv->value) {
3847 continue;
3848 }
3849 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3850 &error_abort);
3851 }
3852}
3853
f99fd7ca 3854/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 3855 */
d940ee9b 3856static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
c6dc6f63 3857{
61dcd775 3858 CPUX86State *env = &cpu->env;
74f54bc4
EH		 3859 const char *vendor;
3860 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 3861 FeatureWord w;
c6dc6f63 3862
f99fd7ca
EH		 3863 /*NOTE: any property set by this function should be returned by
3864 * x86_cpu_static_props(), so static expansion of
3865 * query-cpu-model-expansion is always complete.
3866 */
3867
c39c0edf 3868 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 3869 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3870 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 3871
2d64255b
AF		 3872 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3873 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3874 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 3875 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 3876 for (w = 0; w < FEATURE_WORDS; w++) {
3877 env->features[w] = def->features[w];
3878 }
82beb536 3879
a9f27ea9
EH		 3880 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3881 cpu->legacy_cache = !def->cache_info;
ab8f992e 3882
9576de75 3883 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 3884 /* TODO: in-kernel irqchip for hvf */
82beb536 3885 if (kvm_enabled()) {
492a4c94
LT		 3886 if (!kvm_irqchip_in_kernel()) {
3887 x86_cpu_change_kvm_default("x2apic", "off");
3888 }
3889
5114e842 3890 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 3891 } else if (tcg_enabled()) {
3892 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 3893 }
5fcca9ff 3894
82beb536 3895 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 3896
3897 /* sysenter isn't supported in compatibility mode on AMD,
3898 * syscall isn't supported in compatibility mode on Intel.
3899 * Normally we advertise the actual CPU vendor, but you can
3900 * override this using the 'vendor' property if you want to use
3901 * KVM's sysenter/syscall emulation in compatibility mode and
3902 * when doing cross vendor migration
3903 */
74f54bc4 3904 vendor = def->vendor;
d6dcc558 3905 if (accel_uses_host_cpuid()) {
7c08db30
EH		 3906 uint32_t ebx = 0, ecx = 0, edx = 0;
3907 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3908 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3909 vendor = host_vendor;
3910 }
3911
3912 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3913
c6dc6f63
AP		 3914}
3915
96f75b59 3916#ifndef CONFIG_USER_ONLY
f99fd7ca
EH		 3917/* Return a QDict containing keys for all properties that can be included
3918 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3919 * must be included in the dictionary.
3920 */
3921static QDict *x86_cpu_static_props(void)
3922{
3923 FeatureWord w;
3924 int i;
3925 static const char *props[] = {
3926 "min-level",
3927 "min-xlevel",
3928 "family",
3929 "model",
3930 "stepping",
3931 "model-id",
3932 "vendor",
3933 "lmce",
3934 NULL,
3935 };
3936 static QDict *d;
3937
3938 if (d) {
3939 return d;
3940 }
3941
3942 d = qdict_new();
3943 for (i = 0; props[i]; i++) {
0f9afc2a 3944 qdict_put_null(d, props[i]);
f99fd7ca
EH		 3945 }
3946
3947 for (w = 0; w < FEATURE_WORDS; w++) {
3948 FeatureWordInfo *fi = &feature_word_info[w];
3949 int bit;
3950 for (bit = 0; bit < 32; bit++) {
3951 if (!fi->feat_names[bit]) {
3952 continue;
3953 }
0f9afc2a 3954 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 3955 }
3956 }
3957
3958 return d;
3959}
3960
3961/* Add an entry to @props dict, with the value for property. */
3962static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3963{
3964 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3965 &error_abort);
3966
3967 qdict_put_obj(props, prop, value);
3968}
3969
3970/* Convert CPU model data from X86CPU object to a property dictionary
3971 * that can recreate exactly the same CPU model.
3972 */
3973static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3974{
3975 QDict *sprops = x86_cpu_static_props();
3976 const QDictEntry *e;
3977
3978 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3979 const char *prop = qdict_entry_key(e);
3980 x86_cpu_expand_prop(cpu, props, prop);
3981 }
3982}
3983
b8097deb
EH		 3984/* Convert CPU model data from X86CPU object to a property dictionary
3985 * that can recreate exactly the same CPU model, including every
3986 * writeable QOM property.
3987 */
3988static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3989{
3990 ObjectPropertyIterator iter;
3991 ObjectProperty *prop;
3992
3993 object_property_iter_init(&iter, OBJECT(cpu));
3994 while ((prop = object_property_iter_next(&iter))) {
3995 /* skip read-only or write-only properties */
3996 if (!prop->get || !prop->set) {
3997 continue;
3998 }
3999
4000 /* "hotplugged" is the only property that is configurable
4001 * on the command-line but will be set differently on CPUs
4002 * created using "-cpu ... -smp ..." and by CPUs created
4003 * on the fly by x86_cpu_from_model() for querying. Skip it.
4004 */
4005 if (!strcmp(prop->name, "hotplugged")) {
4006 continue;
4007 }
4008 x86_cpu_expand_prop(cpu, props, prop->name);
4009 }
4010}
4011
f99fd7ca
EH		 4012static void object_apply_props(Object *obj, QDict *props, Error **errp)
4013{
4014 const QDictEntry *prop;
4015 Error *err = NULL;
4016
4017 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4018 object_property_set_qobject(obj, qdict_entry_value(prop),
4019 qdict_entry_key(prop), &err);
4020 if (err) {
4021 break;
4022 }
4023 }
4024
4025 error_propagate(errp, err);
4026}
4027
4028/* Create X86CPU object according to model+props specification */
4029static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4030{
4031 X86CPU *xc = NULL;
4032 X86CPUClass *xcc;
4033 Error *err = NULL;
4034
4035 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4036 if (xcc == NULL) {
4037 error_setg(&err, "CPU model '%s' not found", model);
4038 goto out;
4039 }
4040
4041 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4042 if (props) {
4043 object_apply_props(OBJECT(xc), props, &err);
4044 if (err) {
4045 goto out;
4046 }
4047 }
4048
4049 x86_cpu_expand_features(xc, &err);
4050 if (err) {
4051 goto out;
4052 }
4053
4054out:
4055 if (err) {
4056 error_propagate(errp, err);
4057 object_unref(OBJECT(xc));
4058 xc = NULL;
4059 }
4060 return xc;
4061}
4062
4063CpuModelExpansionInfo *
96f75b59 4064qmp_query_cpu_model_expansion(CpuModelExpansionType type,
f99fd7ca
EH		 4065 CpuModelInfo *model,
4066 Error **errp)
4067{
4068 X86CPU *xc = NULL;
4069 Error *err = NULL;
4070 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4071 QDict *props = NULL;
4072 const char *base_name;
4073
4074 xc = x86_cpu_from_model(model->name,
4075 model->has_props ?
7dc847eb 4076 qobject_to(QDict, model->props) :
f99fd7ca
EH		 4077 NULL, &err);
4078 if (err) {
4079 goto out;
4080 }
4081
b8097deb 4082 props = qdict_new();
e38bf612
EH		 4083 ret->model = g_new0(CpuModelInfo, 1);
4084 ret->model->props = QOBJECT(props);
4085 ret->model->has_props = true;
f99fd7ca
EH		 4086
4087 switch (type) {
4088 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4089 /* Static expansion will be based on "base" only */
4090 base_name = "base";
b8097deb 4091 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 4092 break;
4093 case CPU_MODEL_EXPANSION_TYPE_FULL:
4094 /* As we don't return every single property, full expansion needs
4095 * to keep the original model name+props, and add extra
4096 * properties on top of that.
4097 */
4098 base_name = model->name;
b8097deb 4099 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 4100 break;
4101 default:
df68a7f3 4102 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 4103 goto out;
4104 }
4105
f99fd7ca
EH		 4106 x86_cpu_to_dict(xc, props);
4107
f99fd7ca 4108 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 4109
4110out:
4111 object_unref(OBJECT(xc));
4112 if (err) {
4113 error_propagate(errp, err);
4114 qapi_free_CpuModelExpansionInfo(ret);
4115 ret = NULL;
4116 }
4117 return ret;
4118}
96f75b59 4119#endif /* !CONFIG_USER_ONLY */
f99fd7ca 4120
00fcd100
AB		 4121static gchar *x86_gdb_arch_name(CPUState *cs)
4122{
4123#ifdef TARGET_X86_64
4124 return g_strdup("i386:x86-64");
4125#else
4126 return g_strdup("i386");
4127#endif
4128}
4129
d940ee9b
EH		 4130static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4131{
4132 X86CPUDefinition *cpudef = data;
4133 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4134
4135 xcc->cpu_def = cpudef;
bd72159d 4136 xcc->migration_safe = true;
d940ee9b
EH		 4137}
4138
4139static void x86_register_cpudef_type(X86CPUDefinition *def)
4140{
4141 char *typename = x86_cpu_type_name(def->name);
4142 TypeInfo ti = {
4143 .name = typename,
4144 .parent = TYPE_X86_CPU,
4145 .class_init = x86_cpu_cpudef_class_init,
4146 .class_data = def,
4147 };
4148
2a923a29
EH		 4149 /* AMD aliases are handled at runtime based on CPUID vendor, so
4150 * they shouldn't be set on the CPU model table.
4151 */
4152 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 4153 /* catch mistakes instead of silently truncating model_id when too long */
4154 assert(def->model_id && strlen(def->model_id) <= 48);
4155
2a923a29 4156
d940ee9b
EH		 4157 type_register(&ti);
4158 g_free(typename);
4159}
4160
c6dc6f63 4161#if !defined(CONFIG_USER_ONLY)
c6dc6f63 4162
0e26b7b8
BS		 4163void cpu_clear_apic_feature(CPUX86State *env)
4164{
0514ef2f 4165 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 4166}
4167
c6dc6f63
AP		 4168#endif /* !CONFIG_USER_ONLY */
4169
c6dc6f63
AP		 4170void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4171 uint32_t *eax, uint32_t *ebx,
4172 uint32_t *ecx, uint32_t *edx)
4173{
a60f24b5
AF		 4174 X86CPU *cpu = x86_env_get_cpu(env);
4175 CPUState *cs = CPU(cpu);
14c985cf 4176 uint32_t pkg_offset;
4ed3d478 4177 uint32_t limit;
1ce36bfe 4178 uint32_t signature[3];
a60f24b5 4179
4ed3d478
DB		 4180 /* Calculate & apply limits for different index ranges */
4181 if (index >= 0xC0000000) {
4182 limit = env->cpuid_xlevel2;
4183 } else if (index >= 0x80000000) {
4184 limit = env->cpuid_xlevel;
1ce36bfe
DB		 4185 } else if (index >= 0x40000000) {
4186 limit = 0x40000001;
c6dc6f63 4187 } else {
4ed3d478
DB		 4188 limit = env->cpuid_level;
4189 }
4190
4191 if (index > limit) {
4192 /* Intel documentation states that invalid EAX input will
4193 * return the same information as EAX=cpuid_level
4194 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4195 */
4196 index = env->cpuid_level;
c6dc6f63
AP		 4197 }
4198
4199 switch(index) {
4200 case 0:
4201 *eax = env->cpuid_level;
5eb2f7a4
EH		 4202 *ebx = env->cpuid_vendor1;
4203 *edx = env->cpuid_vendor2;
4204 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 4205 break;
4206 case 1:
4207 *eax = env->cpuid_version;
7e72a45c
EH		 4208 *ebx = (cpu->apic_id << 24) |
4209 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 4210 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 4211 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4212 *ecx |= CPUID_EXT_OSXSAVE;
4213 }
0514ef2f 4214 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 4215 if (cs->nr_cores * cs->nr_threads > 1) {
4216 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 4217 *edx |= CPUID_HT;
c6dc6f63
AP		 4218 }
4219 break;
4220 case 2:
4221 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 4222 if (cpu->cache_info_passthrough) {
4223 host_cpuid(index, 0, eax, ebx, ecx, edx);
4224 break;
4225 }
5e891bf8 4226 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 4227 *ebx = 0;
14c985cf
LM		 4228 if (!cpu->enable_l3_cache) {
4229 *ecx = 0;
4230 } else {
a9f27ea9 4231 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 4232 }
a9f27ea9
EH		 4233 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4234 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4235 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 4236 break;
4237 case 4:
4238 /* cache info: needed for Core compatibility */
787aaf57
BC		 4239 if (cpu->cache_info_passthrough) {
4240 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 4241 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 4242 *eax &= ~0xFC000000;
7e3482f8
EH		 4243 if ((*eax & 31) && cs->nr_cores > 1) {
4244 *eax |= (cs->nr_cores - 1) << 26;
4245 }
c6dc6f63 4246 } else {
2f7a21c4 4247 *eax = 0;
76c2975a 4248 switch (count) {
c6dc6f63 4249 case 0: /* L1 dcache info */
a9f27ea9
EH		 4250 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4251 1, cs->nr_cores,
7e3482f8 4252 eax, ebx, ecx, edx);
c6dc6f63
AP		 4253 break;
4254 case 1: /* L1 icache info */
a9f27ea9
EH		 4255 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4256 1, cs->nr_cores,
7e3482f8 4257 eax, ebx, ecx, edx);
c6dc6f63
AP		 4258 break;
4259 case 2: /* L2 cache info */
a9f27ea9
EH		 4260 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4261 cs->nr_threads, cs->nr_cores,
7e3482f8 4262 eax, ebx, ecx, edx);
c6dc6f63 4263 break;
14c985cf 4264 case 3: /* L3 cache info */
7e3482f8
EH		 4265 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4266 if (cpu->enable_l3_cache) {
a9f27ea9
EH		 4267 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4268 (1 << pkg_offset), cs->nr_cores,
7e3482f8 4269 eax, ebx, ecx, edx);
14c985cf
LM		 4270 break;
4271 }
7e3482f8 4272 /* fall through */
c6dc6f63 4273 default: /* end of info */
7e3482f8 4274 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 4275 break;
76c2975a
PB		 4276 }
4277 }
c6dc6f63
AP		 4278 break;
4279 case 5:
2266d443
MT		 4280 /* MONITOR/MWAIT Leaf */
4281 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4282 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4283 *ecx = cpu->mwait.ecx; /* flags */
4284 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 4285 break;
4286 case 6:
4287 /* Thermal and Power Leaf */
28b8e4d0 4288 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 4289 *ebx = 0;
4290 *ecx = 0;
4291 *edx = 0;
4292 break;
f7911686 4293 case 7:
13526728
EH		 4294 /* Structured Extended Feature Flags Enumeration Leaf */
4295 if (count == 0) {
4296 *eax = 0; /* Maximum ECX value for sub-leaves */
0514ef2f 4297 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 4298 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 4299 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4300 *ecx |= CPUID_7_0_ECX_OSPKE;
4301 }
95ea69fb 4302 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
f7911686
YW		 4303 } else {
4304 *eax = 0;
4305 *ebx = 0;
4306 *ecx = 0;
4307 *edx = 0;
4308 }
4309 break;
c6dc6f63
AP		 4310 case 9:
4311 /* Direct Cache Access Information Leaf */
4312 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4313 *ebx = 0;
4314 *ecx = 0;
4315 *edx = 0;
4316 break;
4317 case 0xA:
4318 /* Architectural Performance Monitoring Leaf */
9337e3b6 4319 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 4320 KVMState *s = cs->kvm_state;
a0fa8208
GN		 4321
4322 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4323 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4324 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4325 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 4326 } else if (hvf_enabled() && cpu->enable_pmu) {
4327 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4328 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4329 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4330 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 4331 } else {
4332 *eax = 0;
4333 *ebx = 0;
4334 *ecx = 0;
4335 *edx = 0;
4336 }
c6dc6f63 4337 break;
5232d00a
RK		 4338 case 0xB:
4339 /* Extended Topology Enumeration Leaf */
4340 if (!cpu->enable_cpuid_0xb) {
4341 *eax = *ebx = *ecx = *edx = 0;
4342 break;
4343 }
4344
4345 *ecx = count & 0xff;
4346 *edx = cpu->apic_id;
4347
4348 switch (count) {
4349 case 0:
eab60fb9
MAL		 4350 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4351 *ebx = cs->nr_threads;
5232d00a
RK		 4352 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4353 break;
4354 case 1:
eab60fb9
MAL		 4355 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4356 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 4357 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4358 break;
4359 default:
4360 *eax = 0;
4361 *ebx = 0;
4362 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4363 }
4364
4365 assert(!(*eax & ~0x1f));
4366 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4367 break;
2560f19f 4368 case 0xD: {
51e49430 4369 /* Processor Extended State */
2560f19f
PB		 4370 *eax = 0;
4371 *ebx = 0;
4372 *ecx = 0;
4373 *edx = 0;
19dc85db 4374 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 4375 break;
4376 }
4928cd6d 4377
2560f19f 4378 if (count == 0) {
96193c22
EH		 4379 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4380 *eax = env->features[FEAT_XSAVE_COMP_LO];
4381 *edx = env->features[FEAT_XSAVE_COMP_HI];
de2e68c9 4382 *ebx = xsave_area_size(env->xcr0);
2560f19f 4383 } else if (count == 1) {
0bb0b2d2 4384 *eax = env->features[FEAT_XSAVE];
f4f1110e 4385 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 4386 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4387 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 4388 *eax = esa->size;
4389 *ebx = esa->offset;
2560f19f 4390 }
51e49430
SY		 4391 }
4392 break;
2560f19f 4393 }
e37a5c7f
CP		 4394 case 0x14: {
4395 /* Intel Processor Trace Enumeration */
4396 *eax = 0;
4397 *ebx = 0;
4398 *ecx = 0;
4399 *edx = 0;
4400 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4401 !kvm_enabled()) {
4402 break;
4403 }
4404
4405 if (count == 0) {
4406 *eax = INTEL_PT_MAX_SUBLEAF;
4407 *ebx = INTEL_PT_MINIMAL_EBX;
4408 *ecx = INTEL_PT_MINIMAL_ECX;
4409 } else if (count == 1) {
4410 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4411 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4412 }
4413 break;
4414 }
1ce36bfe
DB		 4415 case 0x40000000:
4416 /*
4417 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4418 * set here, but we restrict to TCG none the less.
4419 */
4420 if (tcg_enabled() && cpu->expose_tcg) {
4421 memcpy(signature, "TCGTCGTCGTCG", 12);
4422 *eax = 0x40000001;
4423 *ebx = signature[0];
4424 *ecx = signature[1];
4425 *edx = signature[2];
4426 } else {
4427 *eax = 0;
4428 *ebx = 0;
4429 *ecx = 0;
4430 *edx = 0;
4431 }
4432 break;
4433 case 0x40000001:
4434 *eax = 0;
4435 *ebx = 0;
4436 *ecx = 0;
4437 *edx = 0;
4438 break;
c6dc6f63
AP		 4439 case 0x80000000:
4440 *eax = env->cpuid_xlevel;
4441 *ebx = env->cpuid_vendor1;
4442 *edx = env->cpuid_vendor2;
4443 *ecx = env->cpuid_vendor3;
4444 break;
4445 case 0x80000001:
4446 *eax = env->cpuid_version;
4447 *ebx = 0;
0514ef2f
EH		 4448 *ecx = env->features[FEAT_8000_0001_ECX];
4449 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 4450
4451 /* The Linux kernel checks for the CMPLegacy bit and
4452 * discards multiple thread information if it is set.
cb8d4c8f 4453 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 4454 */
ce3960eb 4455 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 4456 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4457 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4458 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 4459 *ecx |= 1 << 1; /* CmpLegacy bit */
4460 }
4461 }
c6dc6f63
AP		 4462 break;
4463 case 0x80000002:
4464 case 0x80000003:
4465 case 0x80000004:
4466 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4467 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4468 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4469 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4470 break;
4471 case 0x80000005:
4472 /* cache info (L1 cache) */
787aaf57
BC		 4473 if (cpu->cache_info_passthrough) {
4474 host_cpuid(index, 0, eax, ebx, ecx, edx);
4475 break;
4476 }
5e891bf8
EH		 4477 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4478 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4479 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4480 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4481 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4482 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 4483 break;
4484 case 0x80000006:
4485 /* cache info (L2 cache) */
787aaf57
BC		 4486 if (cpu->cache_info_passthrough) {
4487 host_cpuid(index, 0, eax, ebx, ecx, edx);
4488 break;
4489 }
5e891bf8
EH		 4490 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4491 (L2_DTLB_2M_ENTRIES << 16) | \
4492 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4493 (L2_ITLB_2M_ENTRIES);
4494 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4495 (L2_DTLB_4K_ENTRIES << 16) | \
4496 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4497 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 4498 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4499 cpu->enable_l3_cache ?
4500 env->cache_info_amd.l3_cache : NULL,
4501 ecx, edx);
c6dc6f63 4502 break;
303752a9
MT		 4503 case 0x80000007:
4504 *eax = 0;
4505 *ebx = 0;
4506 *ecx = 0;
4507 *edx = env->features[FEAT_8000_0007_EDX];
4508 break;
c6dc6f63
AP		 4509 case 0x80000008:
4510 /* virtual & phys address size in low 2 bytes. */
0514ef2f 4511 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 4512 /* 64 bit processor */
4513 *eax = cpu->phys_bits; /* configurable physical bits */
4514 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4515 *eax |= 0x00003900; /* 57 bits virtual */
4516 } else {
4517 *eax |= 0x00003000; /* 48 bits virtual */
4518 }
c6dc6f63 4519 } else {
af45907a 4520 *eax = cpu->phys_bits;
c6dc6f63 4521 }
1b3420e1 4522 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 4523 *ecx = 0;
4524 *edx = 0;
ce3960eb
AF		 4525 if (cs->nr_cores * cs->nr_threads > 1) {
4526 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 4527 }
4528 break;
4529 case 0x8000000A:
0514ef2f 4530 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 4531 *eax = 0x00000001; /* SVM Revision */
4532 *ebx = 0x00000010; /* nr of ASIDs */
4533 *ecx = 0;
0514ef2f 4534 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 4535 } else {
4536 *eax = 0;
4537 *ebx = 0;
4538 *ecx = 0;
4539 *edx = 0;
4540 }
c6dc6f63 4541 break;
8f4202fb
BM		 4542 case 0x8000001D:
4543 *eax = 0;
4544 switch (count) {
4545 case 0: /* L1 dcache info */
4546 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4547 eax, ebx, ecx, edx);
4548 break;
4549 case 1: /* L1 icache info */
4550 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4551 eax, ebx, ecx, edx);
4552 break;
4553 case 2: /* L2 cache info */
4554 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4555 eax, ebx, ecx, edx);
4556 break;
4557 case 3: /* L3 cache info */
4558 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4559 eax, ebx, ecx, edx);
4560 break;
4561 default: /* end of info */
4562 *eax = *ebx = *ecx = *edx = 0;
4563 break;
4564 }
4565 break;
ed78467a
BM		 4566 case 0x8000001E:
4567 assert(cpu->core_id <= 255);
4568 encode_topo_cpuid8000001e(cs, cpu,
4569 eax, ebx, ecx, edx);
4570 break;
b3baa152
BW		 4571 case 0xC0000000:
4572 *eax = env->cpuid_xlevel2;
4573 *ebx = 0;
4574 *ecx = 0;
4575 *edx = 0;
4576 break;
4577 case 0xC0000001:
4578 /* Support for VIA CPU's CPUID instruction */
4579 *eax = env->cpuid_version;
4580 *ebx = 0;
4581 *ecx = 0;
0514ef2f 4582 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 4583 break;
4584 case 0xC0000002:
4585 case 0xC0000003:
4586 case 0xC0000004:
4587 /* Reserved for the future, and now filled with zero */
4588 *eax = 0;
4589 *ebx = 0;
4590 *ecx = 0;
4591 *edx = 0;
4592 break;
6cb8f2a6
BS		 4593 case 0x8000001F:
4594 *eax = sev_enabled() ? 0x2 : 0;
4595 *ebx = sev_get_cbit_position();
4596 *ebx |= sev_get_reduced_phys_bits() << 6;
4597 *ecx = 0;
4598 *edx = 0;
4599 break;
c6dc6f63
AP		 4600 default:
4601 /* reserved values: zero */
4602 *eax = 0;
4603 *ebx = 0;
4604 *ecx = 0;
4605 *edx = 0;
4606 break;
4607 }
4608}
5fd2087a
AF		 4609
4610/* CPUClass::reset() */
4611static void x86_cpu_reset(CPUState *s)
4612{
4613 X86CPU *cpu = X86_CPU(s);
4614 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4615 CPUX86State *env = &cpu->env;
a114d25d
RH		 4616 target_ulong cr4;
4617 uint64_t xcr0;
c1958aea
AF		 4618 int i;
4619
5fd2087a
AF		 4620 xcc->parent_reset(s);
4621
5e992a8e 4622 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 4623
c1958aea
AF		 4624 env->old_exception = -1;
4625
4626 /* init to reset state */
4627
c1958aea
AF		 4628 env->hflags2 |= HF2_GIF_MASK;
4629
4630 cpu_x86_update_cr0(env, 0x60000010);
4631 env->a20_mask = ~0x0;
4632 env->smbase = 0x30000;
e13713db 4633 env->msr_smi_count = 0;
c1958aea
AF		 4634
4635 env->idt.limit = 0xffff;
4636 env->gdt.limit = 0xffff;
4637 env->ldt.limit = 0xffff;
4638 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4639 env->tr.limit = 0xffff;
4640 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4641
4642 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4643 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4644 DESC_R_MASK | DESC_A_MASK);
4645 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4646 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4647 DESC_A_MASK);
4648 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4649 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4650 DESC_A_MASK);
4651 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4652 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4653 DESC_A_MASK);
4654 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4655 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4656 DESC_A_MASK);
4657 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4658 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4659 DESC_A_MASK);
4660
4661 env->eip = 0xfff0;
4662 env->regs[R_EDX] = env->cpuid_version;
4663
4664 env->eflags = 0x2;
4665
4666 /* FPU init */
4667 for (i = 0; i < 8; i++) {
4668 env->fptags[i] = 1;
4669 }
5bde1407 4670 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 4671
4672 env->mxcsr = 0x1f80;
a114d25d
RH		 4673 /* All units are in INIT state. */
4674 env->xstate_bv = 0;
c1958aea
AF		 4675
4676 env->pat = 0x0007040600070406ULL;
4677 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4678
4679 memset(env->dr, 0, sizeof(env->dr));
4680 env->dr[6] = DR6_FIXED_1;
4681 env->dr[7] = DR7_FIXED_1;
b3310ab3 4682 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 4683 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 4684
a114d25d 4685 cr4 = 0;
cfc3b074 4686 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 4687
4688#ifdef CONFIG_USER_ONLY
4689 /* Enable all the features for user-mode. */
4690 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 4691 xcr0 |= XSTATE_SSE_MASK;
a114d25d 4692 }
0f70ed47
PB		 4693 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4694 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 4695 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 4696 xcr0 |= 1ull << i;
4697 }
a114d25d 4698 }
0f70ed47 4699
a114d25d
RH		 4700 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4701 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4702 }
07929f2a
RH		 4703 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4704 cr4 |= CR4_FSGSBASE_MASK;
4705 }
a114d25d
RH		 4706#endif
4707
4708 env->xcr0 = xcr0;
4709 cpu_x86_update_cr4(env, cr4);
0522604b 4710
9db2efd9
AW		 4711 /*
4712 * SDM 11.11.5 requires:
4713 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4714 * - IA32_MTRR_PHYSMASKn.V = 0
4715 * All other bits are undefined. For simplification, zero it all.
4716 */
4717 env->mtrr_deftype = 0;
4718 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4719 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4720
b7394c83
SAGDR		 4721 env->interrupt_injected = -1;
4722 env->exception_injected = -1;
4723 env->nmi_injected = false;
dd673288
IM		 4724#if !defined(CONFIG_USER_ONLY)
4725 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 4726 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 4727
259186a7 4728 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 4729
4730 if (kvm_enabled()) {
4731 kvm_arch_reset_vcpu(cpu);
4732 }
d6dcc558
SAGDR		 4733 else if (hvf_enabled()) {
4734 hvf_reset_vcpu(s);
4735 }
dd673288 4736#endif
5fd2087a
AF		 4737}
4738
dd673288
IM		 4739#ifndef CONFIG_USER_ONLY
4740bool cpu_is_bsp(X86CPU *cpu)
4741{
02e51483 4742 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 4743}
65dee380
IM		 4744
4745/* TODO: remove me, when reset over QOM tree is implemented */
4746static void x86_cpu_machine_reset_cb(void *opaque)
4747{
4748 X86CPU *cpu = opaque;
4749 cpu_reset(CPU(cpu));
4750}
dd673288
IM		 4751#endif
4752
de024815
AF		 4753static void mce_init(X86CPU *cpu)
4754{
4755 CPUX86State *cenv = &cpu->env;
4756 unsigned int bank;
4757
4758 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 4759 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 4760 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 4761 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4762 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 4763 cenv->mcg_ctl = ~(uint64_t)0;
4764 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4765 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4766 }
4767 }
4768}
4769
bdeec802 4770#ifndef CONFIG_USER_ONLY
2f114315 4771APICCommonClass *apic_get_class(void)
bdeec802 4772{
bdeec802
IM		 4773 const char *apic_type = "apic";
4774
d6dcc558 4775 /* TODO: in-kernel irqchip for hvf */
15eafc2e 4776 if (kvm_apic_in_kernel()) {
bdeec802
IM		 4777 apic_type = "kvm-apic";
4778 } else if (xen_enabled()) {
4779 apic_type = "xen-apic";
4780 }
4781
2f114315
RK		 4782 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4783}
4784
4785static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4786{
4787 APICCommonState *apic;
4788 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4789
4790 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
bdeec802 4791
6816b1b3
IM		 4792 object_property_add_child(OBJECT(cpu), "lapic",
4793 OBJECT(cpu->apic_state), &error_abort);
67e55caa 4794 object_unref(OBJECT(cpu->apic_state));
6816b1b3 4795
33d7a288 4796 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 4797 /* TODO: convert to link<> */
02e51483 4798 apic = APIC_COMMON(cpu->apic_state);
60671e58 4799 apic->cpu = cpu;
8d42d2d3 4800 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 4801}
4802
4803static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4804{
8d42d2d3
CF		 4805 APICCommonState *apic;
4806 static bool apic_mmio_map_once;
4807
02e51483 4808 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 4809 return;
4810 }
6e8e2651
MA		 4811 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4812 errp);
8d42d2d3
CF		 4813
4814 /* Map APIC MMIO area */
4815 apic = APIC_COMMON(cpu->apic_state);
4816 if (!apic_mmio_map_once) {
4817 memory_region_add_subregion_overlap(get_system_memory(),
4818 apic->apicbase &
4819 MSR_IA32_APICBASE_BASE,
4820 &apic->io_memory,
4821 0x1000);
4822 apic_mmio_map_once = true;
4823 }
bdeec802 4824}
f809c605
PB		 4825
4826static void x86_cpu_machine_done(Notifier *n, void *unused)
4827{
4828 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4829 MemoryRegion *smram =
4830 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4831
4832 if (smram) {
4833 cpu->smram = g_new(MemoryRegion, 1);
4834 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4835 smram, 0, 1ull << 32);
f8c45c65 4836 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 4837 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4838 }
4839}
d3c64d6a
IM		 4840#else
4841static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4842{
4843}
bdeec802
IM		 4844#endif
4845
11f6fee5
DDAG		 4846/* Note: Only safe for use on x86(-64) hosts */
4847static uint32_t x86_host_phys_bits(void)
4848{
4849 uint32_t eax;
4850 uint32_t host_phys_bits;
4851
4852 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4853 if (eax >= 0x80000008) {
4854 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4855 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4856 * at 23:16 that can specify a maximum physical address bits for
4857 * the guest that can override this value; but I've not seen
4858 * anything with that set.
4859 */
4860 host_phys_bits = eax & 0xff;
4861 } else {
4862 /* It's an odd 64 bit machine that doesn't have the leaf for
4863 * physical address bits; fall back to 36 that's most older
4864 * Intel.
4865 */
4866 host_phys_bits = 36;
4867 }
4868
4869 return host_phys_bits;
4870}
e48638fd 4871
c39c0edf
EH		 4872static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4873{
4874 if (*min < value) {
4875 *min = value;
4876 }
4877}
4878
4879/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4880static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4881{
4882 CPUX86State *env = &cpu->env;
4883 FeatureWordInfo *fi = &feature_word_info[w];
07585923 4884 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 4885 uint32_t region = eax & 0xF0000000;
4886
07585923 4887 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 4888 if (!env->features[w]) {
4889 return;
4890 }
4891
4892 switch (region) {
4893 case 0x00000000:
4894 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4895 break;
4896 case 0x80000000:
4897 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4898 break;
4899 case 0xC0000000:
4900 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4901 break;
4902 }
4903}
4904
2ca8a8be
EH		 4905/* Calculate XSAVE components based on the configured CPU feature flags */
4906static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4907{
4908 CPUX86State *env = &cpu->env;
4909 int i;
96193c22 4910 uint64_t mask;
2ca8a8be
EH		 4911
4912 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4913 return;
4914 }
4915
e3c9022b
EH		 4916 mask = 0;
4917 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 4918 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4919 if (env->features[esa->feature] & esa->bits) {
96193c22 4920 mask |= (1ULL << i);
2ca8a8be
EH		 4921 }
4922 }
4923
96193c22
EH		 4924 env->features[FEAT_XSAVE_COMP_LO] = mask;
4925 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 4926}
4927
b8d834a0
EH		 4928/***** Steps involved on loading and filtering CPUID data
4929 *
4930 * When initializing and realizing a CPU object, the steps
4931 * involved in setting up CPUID data are:
4932 *
4933 * 1) Loading CPU model definition (X86CPUDefinition). This is
4934 * implemented by x86_cpu_load_def() and should be completely
4935 * transparent, as it is done automatically by instance_init.
4936 * No code should need to look at X86CPUDefinition structs
4937 * outside instance_init.
4938 *
4939 * 2) CPU expansion. This is done by realize before CPUID
4940 * filtering, and will make sure host/accelerator data is
4941 * loaded for CPU models that depend on host capabilities
4942 * (e.g. "host"). Done by x86_cpu_expand_features().
4943 *
4944 * 3) CPUID filtering. This initializes extra data related to
4945 * CPUID, and checks if the host supports all capabilities
4946 * required by the CPU. Runnability of a CPU model is
4947 * determined at this step. Done by x86_cpu_filter_features().
4948 *
4949 * Some operations don't require all steps to be performed.
4950 * More precisely:
4951 *
4952 * - CPU instance creation (instance_init) will run only CPU
4953 * model loading. CPU expansion can't run at instance_init-time
4954 * because host/accelerator data may be not available yet.
4955 * - CPU realization will perform both CPU model expansion and CPUID
4956 * filtering, and return an error in case one of them fails.
4957 * - query-cpu-definitions needs to run all 3 steps. It needs
4958 * to run CPUID filtering, as the 'unavailable-features'
4959 * field is set based on the filtering results.
4960 * - The query-cpu-model-expansion QMP command only needs to run
4961 * CPU model loading and CPU expansion. It should not filter
4962 * any CPUID data based on host capabilities.
4963 */
4964
4965/* Expand CPU configuration data, based on configured features
4966 * and host/accelerator capabilities when appropriate.
4967 */
4968static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 4969{
b34d12d1 4970 CPUX86State *env = &cpu->env;
dc15c051 4971 FeatureWord w;
2fae0d96 4972 GList *l;
41f3d4d6 4973 Error *local_err = NULL;
9886e834 4974
d4a606b3
EH		 4975 /*TODO: Now cpu->max_features doesn't overwrite features
4976 * set using QOM properties, and we can convert
dc15c051
IM		 4977 * plus_features & minus_features to global properties
4978 * inside x86_cpu_parse_featurestr() too.
4979 */
44bd8e53 4980 if (cpu->max_features) {
dc15c051 4981 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 4982 /* Override only features that weren't set explicitly
4983 * by the user.
4984 */
4985 env->features[w] |=
4986 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 4987 ~env->user_features[w] & \
4988 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 4989 }
4990 }
4991
2fae0d96
EH		 4992 for (l = plus_features; l; l = l->next) {
4993 const char *prop = l->data;
4994 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
4995 if (local_err) {
4996 goto out;
4997 }
4998 }
4999
5000 for (l = minus_features; l; l = l->next) {
5001 const char *prop = l->data;
5002 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5003 if (local_err) {
5004 goto out;
5005 }
dc15c051
IM		 5006 }
5007
aec661de
EH		 5008 if (!kvm_enabled() || !cpu->expose_kvm) {
5009 env->features[FEAT_KVM] = 0;
5010 }
5011
2ca8a8be 5012 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 5013
5014 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5015 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5016 if (cpu->full_cpuid_auto_level) {
5017 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5018 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5019 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5020 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5021 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5022 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5023 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 5024 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 5025 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5026 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5027 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 5028
5029 /* Intel Processor Trace requires CPUID[0x14] */
5030 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5031 kvm_enabled() && cpu->intel_pt_auto_level) {
5032 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5033 }
5034
0c3d7c00
EH		 5035 /* SVM requires CPUID[0x8000000A] */
5036 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5037 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5038 }
6cb8f2a6
BS		 5039
5040 /* SEV requires CPUID[0x8000001F] */
5041 if (sev_enabled()) {
5042 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5043 }
c39c0edf
EH		 5044 }
5045
5046 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5047 if (env->cpuid_level == UINT32_MAX) {
5048 env->cpuid_level = env->cpuid_min_level;
5049 }
5050 if (env->cpuid_xlevel == UINT32_MAX) {
5051 env->cpuid_xlevel = env->cpuid_min_xlevel;
5052 }
5053 if (env->cpuid_xlevel2 == UINT32_MAX) {
5054 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 5055 }
7a059953 5056
41f3d4d6
EH		 5057out:
5058 if (local_err != NULL) {
5059 error_propagate(errp, local_err);
5060 }
5061}
5062
b8d834a0
EH		 5063/*
5064 * Finishes initialization of CPUID data, filters CPU feature
5065 * words based on host availability of each feature.
5066 *
5067 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5068 */
5069static int x86_cpu_filter_features(X86CPU *cpu)
5070{
5071 CPUX86State *env = &cpu->env;
5072 FeatureWord w;
5073 int rv = 0;
5074
5075 for (w = 0; w < FEATURE_WORDS; w++) {
5076 uint32_t host_feat =
5077 x86_cpu_get_supported_feature_word(w, false);
5078 uint32_t requested_features = env->features[w];
5079 env->features[w] &= host_feat;
5080 cpu->filtered_features[w] = requested_features & ~env->features[w];
5081 if (cpu->filtered_features[w]) {
5082 rv = 1;
5083 }
5084 }
5085
e37a5c7f
CP		 5086 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5087 kvm_enabled()) {
5088 KVMState *s = CPU(cpu)->kvm_state;
5089 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5090 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5091 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5092 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5093 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5094
5095 if (!eax_0 ||
5096 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5097 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5098 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5099 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5100 INTEL_PT_ADDR_RANGES_NUM) ||
5101 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 5102 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5103 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 5104 /*
5105 * Processor Trace capabilities aren't configurable, so if the
5106 * host can't emulate the capabilities we report on
5107 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5108 */
5109 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5110 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5111 rv = 1;
5112 }
5113 }
5114
b8d834a0
EH		 5115 return rv;
5116}
5117
41f3d4d6
EH		 5118#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5119 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5120 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5121#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5122 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5123 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5124static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5125{
5126 CPUState *cs = CPU(dev);
5127 X86CPU *cpu = X86_CPU(dev);
5128 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5129 CPUX86State *env = &cpu->env;
5130 Error *local_err = NULL;
5131 static bool ht_warned;
5132
2266d443
MT		 5133 if (xcc->host_cpuid_required) {
5134 if (!accel_uses_host_cpuid()) {
5135 char *name = x86_cpu_class_get_model_name(xcc);
5136 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5137 g_free(name);
5138 goto out;
5139 }
5140
5141 if (enable_cpu_pm) {
5142 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5143 &cpu->mwait.ecx, &cpu->mwait.edx);
5144 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5145 }
41f3d4d6
EH		 5146 }
5147
2266d443
MT		 5148 /* mwait extended info: needed for Core compatibility */
5149 /* We always wake on interrupt even if host does not have the capability */
5150 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5151
41f3d4d6
EH		 5152 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5153 error_setg(errp, "apic-id property was not initialized properly");
5154 return;
5155 }
5156
b8d834a0 5157 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 5158 if (local_err) {
5159 goto out;
5160 }
5161
8ca30e86
EH		 5162 if (x86_cpu_filter_features(cpu) &&
5163 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5164 x86_cpu_report_filtered_features(cpu);
5165 if (cpu->enforce_cpuid) {
5166 error_setg(&local_err,
d6dcc558 5167 accel_uses_host_cpuid() ?
8ca30e86
EH		 5168 "Host doesn't support requested features" :
5169 "TCG doesn't support requested features");
5170 goto out;
5171 }
9997cf7b
EH		 5172 }
5173
9b15cd9e
IM		 5174 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5175 * CPUID[1].EDX.
5176 */
e48638fd 5177 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 5178 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5179 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 5180 & CPUID_EXT2_AMD_ALIASES);
5181 }
5182
11f6fee5
DDAG		 5183 /* For 64bit systems think about the number of physical bits to present.
5184 * ideally this should be the same as the host; anything other than matching
5185 * the host can cause incorrect guest behaviour.
5186 * QEMU used to pick the magic value of 40 bits that corresponds to
5187 * consumer AMD devices but nothing else.
5188 */
af45907a 5189 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 5190 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 5191 uint32_t host_phys_bits = x86_host_phys_bits();
5192 static bool warned;
5193
5194 if (cpu->host_phys_bits) {
5195 /* The user asked for us to use the host physical bits */
5196 cpu->phys_bits = host_phys_bits;
258fe08b
EH		 5197 if (cpu->host_phys_bits_limit &&
5198 cpu->phys_bits > cpu->host_phys_bits_limit) {
5199 cpu->phys_bits = cpu->host_phys_bits_limit;
5200 }
11f6fee5
DDAG		 5201 }
5202
5203 /* Print a warning if the user set it to a value that's not the
5204 * host value.
5205 */
5206 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5207 !warned) {
3dc6f869
AF		 5208 warn_report("Host physical bits (%u)"
5209 " does not match phys-bits property (%u)",
5210 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 5211 warned = true;
5212 }
5213
5214 if (cpu->phys_bits &&
5215 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5216 cpu->phys_bits < 32)) {
af45907a
DDAG		 5217 error_setg(errp, "phys-bits should be between 32 and %u "
5218 " (but is %u)",
5219 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5220 return;
5221 }
5222 } else {
11f6fee5 5223 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 5224 error_setg(errp, "TCG only supports phys-bits=%u",
5225 TCG_PHYS_ADDR_BITS);
5226 return;
5227 }
5228 }
11f6fee5
DDAG		 5229 /* 0 means it was not explicitly set by the user (or by machine
5230 * compat_props or by the host code above). In this case, the default
5231 * is the value used by TCG (40).
5232 */
5233 if (cpu->phys_bits == 0) {
5234 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5235 }
af45907a
DDAG		 5236 } else {
5237 /* For 32 bit systems don't use the user set value, but keep
5238 * phys_bits consistent with what we tell the guest.
5239 */
5240 if (cpu->phys_bits != 0) {
5241 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5242 return;
5243 }
fefb41bf 5244
af45907a
DDAG		 5245 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5246 cpu->phys_bits = 36;
5247 } else {
5248 cpu->phys_bits = 32;
5249 }
5250 }
a9f27ea9
EH		 5251
5252 /* Cache information initialization */
5253 if (!cpu->legacy_cache) {
5254 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5255 char *name = x86_cpu_class_get_model_name(xcc);
5256 error_setg(errp,
5257 "CPU model '%s' doesn't support legacy-cache=off", name);
5258 g_free(name);
5259 return;
5260 }
5261 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5262 *xcc->cpu_def->cache_info;
5263 } else {
5264 /* Build legacy cache information */
5265 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5266 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5267 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5268 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5269
5270 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5271 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5272 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5273 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5274
5275 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5276 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5277 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5278 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5279 }
5280
5281
ce5b1bbf
LV		 5282 cpu_exec_realizefn(cs, &local_err);
5283 if (local_err != NULL) {
5284 error_propagate(errp, local_err);
5285 return;
5286 }
42ecabaa 5287
65dee380
IM		 5288#ifndef CONFIG_USER_ONLY
5289 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 5290
0514ef2f 5291 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
d3c64d6a 5292 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 5293 if (local_err != NULL) {
4dc1f449 5294 goto out;
bdeec802
IM		 5295 }
5296 }
65dee380
IM		 5297#endif
5298
7a059953 5299 mce_init(cpu);
2001d0cd
PB		 5300
5301#ifndef CONFIG_USER_ONLY
5302 if (tcg_enabled()) {
f809c605 5303 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 5304 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 5305
5306 /* Outer container... */
5307 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 5308 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 5309
5310 /* ... with two regions inside: normal system memory with low
5311 * priority, and...
5312 */
5313 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5314 get_system_memory(), 0, ~0ull);
5315 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5316 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 5317
5318 cs->num_ases = 2;
80ceb07a
PX		 5319 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5320 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 5321
5322 /* ... SMRAM with higher priority, linked from /machine/smram. */
5323 cpu->machine_done.notify = x86_cpu_machine_done;
5324 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 5325 }
5326#endif
5327
14a10fc3 5328 qemu_init_vcpu(cs);
d3c64d6a 5329
6b2942f9
BM		 5330 /*
5331 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5332 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5333 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 5334 * users a warning.
5335 *
5336 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5337 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5338 */
0765691e
MA		 5339 if (IS_AMD_CPU(env) &&
5340 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5341 cs->nr_threads > 1 && !ht_warned) {
5342 warn_report("This family of AMD CPU doesn't support "
5343 "hyperthreading(%d)",
5344 cs->nr_threads);
5345 error_printf("Please configure -smp options properly"
5346 " or try enabling topoext feature.\n");
5347 ht_warned = true;
e48638fd
WH		 5348 }
5349
d3c64d6a
IM		 5350 x86_cpu_apic_realize(cpu, &local_err);
5351 if (local_err != NULL) {
5352 goto out;
5353 }
14a10fc3 5354 cpu_reset(cs);
2b6f294c 5355
4dc1f449 5356 xcc->parent_realize(dev, &local_err);
2001d0cd 5357
4dc1f449
IM		 5358out:
5359 if (local_err != NULL) {
5360 error_propagate(errp, local_err);
5361 return;
5362 }
7a059953
AF		 5363}
5364
c884776e
IM		 5365static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5366{
5367 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 5368 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5369 Error *local_err = NULL;
c884776e
IM		 5370
5371#ifndef CONFIG_USER_ONLY
5372 cpu_remove_sync(CPU(dev));
5373 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5374#endif
5375
5376 if (cpu->apic_state) {
5377 object_unparent(OBJECT(cpu->apic_state));
5378 cpu->apic_state = NULL;
5379 }
7bbc124e
LV		 5380
5381 xcc->parent_unrealize(dev, &local_err);
5382 if (local_err != NULL) {
5383 error_propagate(errp, local_err);
5384 return;
5385 }
c884776e
IM		 5386}
5387
38e5c119 5388typedef struct BitProperty {
a7b0ffac 5389 FeatureWord w;
38e5c119
EH		 5390 uint32_t mask;
5391} BitProperty;
5392
d7bce999
EB		 5393static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5394 void *opaque, Error **errp)
38e5c119 5395{
a7b0ffac 5396 X86CPU *cpu = X86_CPU(obj);
38e5c119 5397 BitProperty *fp = opaque;
a7b0ffac
EH		 5398 uint32_t f = cpu->env.features[fp->w];
5399 bool value = (f & fp->mask) == fp->mask;
51e72bc1 5400 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 5401}
5402
d7bce999
EB		 5403static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5404 void *opaque, Error **errp)
38e5c119
EH		 5405{
5406 DeviceState *dev = DEVICE(obj);
a7b0ffac 5407 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 5408 BitProperty *fp = opaque;
5409 Error *local_err = NULL;
5410 bool value;
5411
5412 if (dev->realized) {
5413 qdev_prop_set_after_realize(dev, name, errp);
5414 return;
5415 }
5416
51e72bc1 5417 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 5418 if (local_err) {
5419 error_propagate(errp, local_err);
5420 return;
5421 }
5422
5423 if (value) {
a7b0ffac 5424 cpu->env.features[fp->w] |= fp->mask;
38e5c119 5425 } else {
a7b0ffac 5426 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 5427 }
d4a606b3 5428 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 5429}
5430
5431static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5432 void *opaque)
5433{
5434 BitProperty *prop = opaque;
5435 g_free(prop);
5436}
5437
5438/* Register a boolean property to get/set a single bit in a uint32_t field.
5439 *
5440 * The same property name can be registered multiple times to make it affect
5441 * multiple bits in the same FeatureWord. In that case, the getter will return
5442 * true only if all bits are set.
5443 */
5444static void x86_cpu_register_bit_prop(X86CPU *cpu,
5445 const char *prop_name,
a7b0ffac 5446 FeatureWord w,
38e5c119
EH		 5447 int bitnr)
5448{
5449 BitProperty *fp;
5450 ObjectProperty *op;
5451 uint32_t mask = (1UL << bitnr);
5452
5453 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5454 if (op) {
5455 fp = op->opaque;
a7b0ffac 5456 assert(fp->w == w);
38e5c119
EH		 5457 fp->mask |= mask;
5458 } else {
5459 fp = g_new0(BitProperty, 1);
a7b0ffac 5460 fp->w = w;
38e5c119
EH		 5461 fp->mask = mask;
5462 object_property_add(OBJECT(cpu), prop_name, "bool",
5463 x86_cpu_get_bit_prop,
5464 x86_cpu_set_bit_prop,
5465 x86_cpu_release_bit_prop, fp, &error_abort);
5466 }
5467}
5468
5469static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5470 FeatureWord w,
5471 int bitnr)
5472{
38e5c119 5473 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 5474 const char *name = fi->feat_names[bitnr];
38e5c119 5475
16d2fcaa 5476 if (!name) {
38e5c119
EH		 5477 return;
5478 }
5479
fc7dfd20
EH		 5480 /* Property names should use "-" instead of "_".
5481 * Old names containing underscores are registered as aliases
5482 * using object_property_add_alias()
5483 */
16d2fcaa
EH		 5484 assert(!strchr(name, '_'));
5485 /* aliases don't use "|" delimiters anymore, they are registered
5486 * manually using object_property_add_alias() */
5487 assert(!strchr(name, '|'));
a7b0ffac 5488 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 5489}
5490
d187e08d
AN		 5491static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5492{
5493 X86CPU *cpu = X86_CPU(cs);
5494 CPUX86State *env = &cpu->env;
5495 GuestPanicInformation *panic_info = NULL;
5496
5e953812 5497 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 5498 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5499
e8ed97a6 5500 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 5501
5e953812 5502 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 5503 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5504 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5505 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5506 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5507 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 5508 }
5509
5510 return panic_info;
5511}
5512static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5513 const char *name, void *opaque,
5514 Error **errp)
5515{
5516 CPUState *cs = CPU(obj);
5517 GuestPanicInformation *panic_info;
5518
5519 if (!cs->crash_occurred) {
5520 error_setg(errp, "No crash occured");
5521 return;
5522 }
5523
5524 panic_info = x86_cpu_get_crash_info(cs);
5525 if (panic_info == NULL) {
5526 error_setg(errp, "No crash information");
5527 return;
5528 }
5529
5530 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5531 errp);
5532 qapi_free_GuestPanicInformation(panic_info);
5533}
5534
de024815
AF		 5535static void x86_cpu_initfn(Object *obj)
5536{
55e5c285 5537 CPUState *cs = CPU(obj);
de024815 5538 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5539 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 5540 CPUX86State *env = &cpu->env;
38e5c119 5541 FeatureWord w;
de024815 5542
c05efcb1 5543 cs->env_ptr = env;
71ad61d3
AF		 5544
5545 object_property_add(obj, "family", "int",
95b8519d 5546 x86_cpuid_version_get_family,
71ad61d3 5547 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 5548 object_property_add(obj, "model", "int",
67e30c83 5549 x86_cpuid_version_get_model,
c5291a4f 5550 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 5551 object_property_add(obj, "stepping", "int",
35112e41 5552 x86_cpuid_version_get_stepping,
036e2222 5553 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 5554 object_property_add_str(obj, "vendor",
5555 x86_cpuid_get_vendor,
5556 x86_cpuid_set_vendor, NULL);
938d4c25 5557 object_property_add_str(obj, "model-id",
63e886eb 5558 x86_cpuid_get_model_id,
938d4c25 5559 x86_cpuid_set_model_id, NULL);
89e48965
AF		 5560 object_property_add(obj, "tsc-frequency", "int",
5561 x86_cpuid_get_tsc_freq,
5562 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 5563 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5564 x86_cpu_get_feature_words,
7e5292b5
EH		 5565 NULL, NULL, (void *)env->features, NULL);
5566 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5567 x86_cpu_get_feature_words,
5568 NULL, NULL, (void *)cpu->filtered_features, NULL);
71ad61d3 5569
d187e08d
AN		 5570 object_property_add(obj, "crash-information", "GuestPanicInformation",
5571 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5572
92067bf4 5573 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
d65e9815 5574
38e5c119
EH		 5575 for (w = 0; w < FEATURE_WORDS; w++) {
5576 int bitnr;
5577
5578 for (bitnr = 0; bitnr < 32; bitnr++) {
5579 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5580 }
5581 }
5582
16d2fcaa
EH		 5583 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5584 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5585 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5586 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5587 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5588 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5589 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5590
54b8dc7c
EH		 5591 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5592 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5593 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5594 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5595 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5596 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5597 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5598 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5599 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5600 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5601 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5602 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5603 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5604 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5605 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5606 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5607 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5608 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5609 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5610 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5611 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5612
0bacd8b3
EH		 5613 if (xcc->cpu_def) {
5614 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5615 }
de024815
AF		 5616}
5617
997395d3
IM		 5618static int64_t x86_cpu_get_arch_id(CPUState *cs)
5619{
5620 X86CPU *cpu = X86_CPU(cs);
997395d3 5621
7e72a45c 5622 return cpu->apic_id;
997395d3
IM		 5623}
5624
444d5590
AF		 5625static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5626{
5627 X86CPU *cpu = X86_CPU(cs);
5628
5629 return cpu->env.cr[0] & CR0_PG_MASK;
5630}
5631
f45748f1
AF		 5632static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5633{
5634 X86CPU *cpu = X86_CPU(cs);
5635
5636 cpu->env.eip = value;
5637}
5638
bdf7ae5b
AF		 5639static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5640{
5641 X86CPU *cpu = X86_CPU(cs);
5642
5643 cpu->env.eip = tb->pc - tb->cs_base;
5644}
5645
92d5f1a4 5646int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 5647{
5648 X86CPU *cpu = X86_CPU(cs);
5649 CPUX86State *env = &cpu->env;
5650
92d5f1a4
PB		 5651#if !defined(CONFIG_USER_ONLY)
5652 if (interrupt_request & CPU_INTERRUPT_POLL) {
5653 return CPU_INTERRUPT_POLL;
5654 }
5655#endif
5656 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5657 return CPU_INTERRUPT_SIPI;
5658 }
5659
5660 if (env->hflags2 & HF2_GIF_MASK) {
5661 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5662 !(env->hflags & HF_SMM_MASK)) {
5663 return CPU_INTERRUPT_SMI;
5664 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5665 !(env->hflags2 & HF2_NMI_MASK)) {
5666 return CPU_INTERRUPT_NMI;
5667 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5668 return CPU_INTERRUPT_MCE;
5669 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5670 (((env->hflags2 & HF2_VINTR_MASK) &&
5671 (env->hflags2 & HF2_HIF_MASK)) ||
5672 (!(env->hflags2 & HF2_VINTR_MASK) &&
5673 (env->eflags & IF_MASK &&
5674 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5675 return CPU_INTERRUPT_HARD;
5676#if !defined(CONFIG_USER_ONLY)
5677 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5678 (env->eflags & IF_MASK) &&
5679 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5680 return CPU_INTERRUPT_VIRQ;
5681#endif
5682 }
5683 }
5684
5685 return 0;
5686}
5687
5688static bool x86_cpu_has_work(CPUState *cs)
5689{
5690 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 5691}
5692
f50f3dd5
RH		 5693static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5694{
5695 X86CPU *cpu = X86_CPU(cs);
5696 CPUX86State *env = &cpu->env;
5697
5698 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5699 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5700 : bfd_mach_i386_i8086);
5701 info->print_insn = print_insn_i386;
b666d2a4
RH		 5702
5703 info->cap_arch = CS_ARCH_X86;
5704 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5705 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5706 : CS_MODE_16);
15fa1a0a
RH		 5707 info->cap_insn_unit = 1;
5708 info->cap_insn_split = 8;
f50f3dd5
RH		 5709}
5710
35b1b927
TW		 5711void x86_update_hflags(CPUX86State *env)
5712{
5713 uint32_t hflags;
5714#define HFLAG_COPY_MASK \
5715 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5716 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5717 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5718 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5719
5720 hflags = env->hflags & HFLAG_COPY_MASK;
5721 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5722 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5723 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5724 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5725 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5726
5727 if (env->cr[4] & CR4_OSFXSR_MASK) {
5728 hflags |= HF_OSFXSR_MASK;
5729 }
5730
5731 if (env->efer & MSR_EFER_LMA) {
5732 hflags |= HF_LMA_MASK;
5733 }
5734
5735 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5736 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5737 } else {
5738 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5739 (DESC_B_SHIFT - HF_CS32_SHIFT);
5740 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5741 (DESC_B_SHIFT - HF_SS32_SHIFT);
5742 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5743 !(hflags & HF_CS32_MASK)) {
5744 hflags |= HF_ADDSEG_MASK;
5745 } else {
5746 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5747 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5748 }
5749 }
5750 env->hflags = hflags;
5751}
5752
9337e3b6 5753static Property x86_cpu_properties[] = {
2da00e31
IM		 5754#ifdef CONFIG_USER_ONLY
5755 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5756 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 5757 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5758 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5759 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 5760#else
5761 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 5762 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5763 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5764 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 5765#endif
15f8b142 5766 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 5767 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
c8f0f88e 5768 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
89314504 5769 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
0f46685d 5770 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
48a5f3bc 5771 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
f2a53c9e 5772 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
744b8a94 5773 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
8c145d7c 5774 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
46eb8f98 5775 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
866eea9a 5776 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
ff99aa64 5777 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
9445597b 5778 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
ba6a4fd9 5779 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
47512009 5780 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
e204ac61 5781 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
6b7a9830 5782 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
15e41345 5783 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 5784 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
f522d2ac 5785 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 5786 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 5787 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 5788 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 5789 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
c39c0edf
EH		 5790 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5791 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5792 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5793 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5794 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5795 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5796 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 5797 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 5798 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 5799 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 5800 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 5801 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5802 false),
0b564e6f 5803 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 5804 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 5805 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5806 true),
ab8f992e 5807 /*
a9f27ea9
EH		 5808 * lecacy_cache defaults to true unless the CPU model provides its
5809 * own cache information (see x86_cpu_load_def()).
ab8f992e 5810 */
a9f27ea9 5811 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 5812
5813 /*
5814 * From "Requirements for Implementing the Microsoft
5815 * Hypervisor Interface":
5816 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5817 *
5818 * "Starting with Windows Server 2012 and Windows 8, if
5819 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5820 * the hypervisor imposes no specific limit to the number of VPs.
5821 * In this case, Windows Server 2012 guest VMs may use more than
5822 * 64 VPs, up to the maximum supported number of processors applicable
5823 * to the specific Windows version being used."
5824 */
5825 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 5826 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5827 false),
f24c3a79
LK		 5828 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5829 true),
9337e3b6
EH		 5830 DEFINE_PROP_END_OF_LIST()
5831};
5832
5fd2087a
AF		 5833static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5834{
5835 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5836 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 5837 DeviceClass *dc = DEVICE_CLASS(oc);
5838
bf853881
PMD		 5839 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5840 &xcc->parent_realize);
5841 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5842 &xcc->parent_unrealize);
9337e3b6 5843 dc->props = x86_cpu_properties;
5fd2087a
AF		 5844
5845 xcc->parent_reset = cc->reset;
5846 cc->reset = x86_cpu_reset;
91b1df8c 5847 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 5848
500050d1 5849 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 5850 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 5851 cc->has_work = x86_cpu_has_work;
79c664f6 5852#ifdef CONFIG_TCG
97a8ea5a 5853 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 5854 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 5855#endif
878096ee 5856 cc->dump_state = x86_cpu_dump_state;
c86f106b 5857 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 5858 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 5859 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 5860 cc->gdb_read_register = x86_cpu_gdb_read_register;
5861 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 5862 cc->get_arch_id = x86_cpu_get_arch_id;
5863 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7510454e
AF		 5864#ifdef CONFIG_USER_ONLY
5865 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
5866#else
f8c45c65 5867 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 5868 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
00b941e5 5869 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
c72bf468
JF		 5870 cc->write_elf64_note = x86_cpu_write_elf64_note;
5871 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5872 cc->write_elf32_note = x86_cpu_write_elf32_note;
5873 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 5874 cc->vmsd = &vmstate_x86_cpu;
c72bf468 5875#endif
00fcd100
AB		 5876 cc->gdb_arch_name = x86_gdb_arch_name;
5877#ifdef TARGET_X86_64
b8158192 5878 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 5879 cc->gdb_num_core_regs = 66;
00fcd100 5880#else
b8158192 5881 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 5882 cc->gdb_num_core_regs = 50;
00fcd100 5883#endif
79c664f6 5884#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 5885 cc->debug_excp_handler = breakpoint_handler;
5886#endif
374e0cd4
RH		 5887 cc->cpu_exec_enter = x86_cpu_exec_enter;
5888 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 5889#ifdef CONFIG_TCG
55c3ceef 5890 cc->tcg_initialize = tcg_x86_init;
74d7fc7f 5891#endif
f50f3dd5 5892 cc->disas_set_info = x86_disas_set_info;
4c315c27 5893
e90f2a8c 5894 dc->user_creatable = true;
5fd2087a
AF		 5895}
5896
5897static const TypeInfo x86_cpu_type_info = {
5898 .name = TYPE_X86_CPU,
5899 .parent = TYPE_CPU,
5900 .instance_size = sizeof(X86CPU),
de024815 5901 .instance_init = x86_cpu_initfn,
d940ee9b 5902 .abstract = true,
5fd2087a
AF		 5903 .class_size = sizeof(X86CPUClass),
5904 .class_init = x86_cpu_common_class_init,
5905};
5906
5adbed30
EH		 5907
5908/* "base" CPU model, used by query-cpu-model-expansion */
5909static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5910{
5911 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5912
5913 xcc->static_model = true;
5914 xcc->migration_safe = true;
5915 xcc->model_description = "base CPU model type with no features enabled";
5916 xcc->ordering = 8;
5917}
5918
5919static const TypeInfo x86_base_cpu_type_info = {
5920 .name = X86_CPU_TYPE_NAME("base"),
5921 .parent = TYPE_X86_CPU,
5922 .class_init = x86_cpu_base_class_init,
5923};
5924
5fd2087a
AF		 5925static void x86_cpu_register_types(void)
5926{
d940ee9b
EH		 5927 int i;
5928
5fd2087a 5929 type_register_static(&x86_cpu_type_info);
d940ee9b
EH		 5930 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5931 x86_register_cpudef_type(&builtin_x86_defs[i]);
5932 }
c62f2630 5933 type_register_static(&max_x86_cpu_type_info);
5adbed30 5934 type_register_static(&x86_base_cpu_type_info);
d6dcc558 5935#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 5936 type_register_static(&host_x86_cpu_type_info);
5937#endif
5fd2087a
AF		 5938}
5939
5940type_init(x86_cpu_register_types)
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