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target/i386/cpu: Remove "x86" prefix from the CPU list
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
15e09912 24#include "qemu/hw-version.h"
c6dc6f63 25#include "cpu.h"
ed69e831 26#include "tcg/helper-tcg.h"
d6dcc558 27#include "sysemu/hvf.h"
044431cf 28#include "hvf/hvf-i386.h"
a9dc68d9 29#include "kvm/kvm_i386.h"
93777de3 30#include "sev.h"
f83aeeae 31#include "qapi/error.h"
cc37d98b 32#include "qemu/error-report.h"
8ac25c84 33#include "qapi/qapi-visit-machine.h"
7b1b5d19 34#include "qapi/qmp/qerror.h"
1814eab6 35#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 36#include "hw/qdev-properties.h"
5232d00a 37#include "hw/i386/topology.h"
bdeec802 38#ifndef CONFIG_USER_ONLY
c0f6cd9f 39#include "sysemu/reset.h"
390dbc6e 40#include "qapi/qapi-commands-machine-target.h"
2001d0cd 41#include "exec/address-spaces.h"
0e11fc69 42#include "hw/boards.h"
1dec2e1f 43#include "hw/i386/sgx-epc.h"
bdeec802
IM		 44#endif
45
b666d2a4 46#include "disas/capstone.h"
79f1a68a 47#include "cpu-internal.h"
b666d2a4 48
123fa102
TH		 49static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
50
7e3482f8
EH		 51/* Helpers for building CPUID[2] descriptors: */
52
53struct CPUID2CacheDescriptorInfo {
54 enum CacheType type;
55 int level;
56 int size;
57 int line_size;
58 int associativity;
59};
5e891bf8 60
7e3482f8
EH		 61/*
62 * Known CPUID 2 cache descriptors.
63 * From Intel SDM Volume 2A, CPUID instruction
64 */
65struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 67 .associativity = 4, .line_size = 32, },
5f00335a 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 69 .associativity = 4, .line_size = 32, },
5f00335a 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 71 .associativity = 4, .line_size = 64, },
5f00335a 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 73 .associativity = 2, .line_size = 32, },
5f00335a 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 64, },
5f00335a 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 79 .associativity = 6, .line_size = 64, },
5f00335a 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 64, },
5f00335a 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 83 .associativity = 8, .line_size = 64, },
84 /* lines per sector is not supported cpuid2_cache_descriptor(),
85 * so descriptors 0x22, 0x23 are not included
86 */
5f00335a 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 88 .associativity = 16, .line_size = 64, },
89 /* lines per sector is not supported cpuid2_cache_descriptor(),
90 * so descriptors 0x25, 0x20 are not included
91 */
5f00335a 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 93 .associativity = 8, .line_size = 64, },
5f00335a 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 95 .associativity = 8, .line_size = 64, },
5f00335a 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 97 .associativity = 4, .line_size = 32, },
5f00335a 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 99 .associativity = 4, .line_size = 32, },
5f00335a 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 101 .associativity = 4, .line_size = 32, },
5f00335a 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 103 .associativity = 4, .line_size = 32, },
5f00335a 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 107 .associativity = 4, .line_size = 64, },
5f00335a 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 109 .associativity = 8, .line_size = 64, },
5f00335a 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 111 .associativity = 12, .line_size = 64, },
112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 114 .associativity = 12, .line_size = 64, },
5f00335a 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 116 .associativity = 16, .line_size = 64, },
5f00335a 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 118 .associativity = 12, .line_size = 64, },
5f00335a 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 120 .associativity = 16, .line_size = 64, },
5f00335a 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 24, .line_size = 64, },
5f00335a 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 124 .associativity = 8, .line_size = 64, },
5f00335a 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 126 .associativity = 4, .line_size = 64, },
5f00335a 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 128 .associativity = 4, .line_size = 64, },
5f00335a 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 130 .associativity = 4, .line_size = 64, },
5f00335a 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 132 .associativity = 4, .line_size = 64, },
133 /* lines per sector is not supported cpuid2_cache_descriptor(),
134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
135 */
5f00335a 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 139 .associativity = 2, .line_size = 64, },
5f00335a 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 141 .associativity = 8, .line_size = 64, },
5f00335a 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 143 .associativity = 8, .line_size = 32, },
5f00335a 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 145 .associativity = 8, .line_size = 32, },
5f00335a 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 147 .associativity = 8, .line_size = 32, },
5f00335a 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 149 .associativity = 8, .line_size = 32, },
5f00335a 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 4, .line_size = 64, },
5f00335a 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 153 .associativity = 8, .line_size = 64, },
5f00335a 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 155 .associativity = 4, .line_size = 64, },
5f00335a 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 4, .line_size = 64, },
5f00335a 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 163 .associativity = 8, .line_size = 64, },
5f00335a 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 165 .associativity = 8, .line_size = 64, },
5f00335a 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 167 .associativity = 12, .line_size = 64, },
5f00335a 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 169 .associativity = 12, .line_size = 64, },
5f00335a 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 171 .associativity = 12, .line_size = 64, },
5f00335a 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 173 .associativity = 16, .line_size = 64, },
5f00335a 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 175 .associativity = 16, .line_size = 64, },
5f00335a 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 177 .associativity = 16, .line_size = 64, },
5f00335a 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 179 .associativity = 24, .line_size = 64, },
5f00335a 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 181 .associativity = 24, .line_size = 64, },
5f00335a 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 183 .associativity = 24, .line_size = 64, },
184};
185
186/*
187 * "CPUID leaf 2 does not report cache descriptor information,
188 * use CPUID leaf 4 to query cache parameters"
189 */
190#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 191
7e3482f8
EH		 192/*
193 * Return a CPUID 2 cache descriptor for a given cache.
194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
195 */
196static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
197{
198 int i;
199
200 assert(cache->size > 0);
201 assert(cache->level > 0);
202 assert(cache->line_size > 0);
203 assert(cache->associativity > 0);
204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
206 if (d->level == cache->level && d->type == cache->type &&
207 d->size == cache->size && d->line_size == cache->line_size &&
208 d->associativity == cache->associativity) {
209 return i;
210 }
211 }
5e891bf8 212
7e3482f8
EH		 213 return CACHE_DESCRIPTOR_UNAVAILABLE;
214}
5e891bf8
EH		 215
216/* CPUID Leaf 4 constants: */
217
218/* EAX: */
7e3482f8
EH		 219#define CACHE_TYPE_D 1
220#define CACHE_TYPE_I 2
221#define CACHE_TYPE_UNIFIED 3
5e891bf8 222
7e3482f8 223#define CACHE_LEVEL(l) (l << 5)
5e891bf8 224
7e3482f8 225#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 226
227/* EDX: */
7e3482f8
EH		 228#define CACHE_NO_INVD_SHARING (1 << 0)
229#define CACHE_INCLUSIVE (1 << 1)
230#define CACHE_COMPLEX_IDX (1 << 2)
231
232/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 233#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
236 0 /* Invalid value */)
7e3482f8
EH		 237
238
239/* Encode cache info for CPUID[4] */
240static void encode_cache_cpuid4(CPUCacheInfo *cache,
241 int num_apic_ids, int num_cores,
242 uint32_t *eax, uint32_t *ebx,
243 uint32_t *ecx, uint32_t *edx)
244{
245 assert(cache->size == cache->line_size * cache->associativity *
246 cache->partitions * cache->sets);
247
248 assert(num_apic_ids > 0);
249 *eax = CACHE_TYPE(cache->type) |
250 CACHE_LEVEL(cache->level) |
251 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
252 ((num_cores - 1) << 26) |
253 ((num_apic_ids - 1) << 14);
254
255 assert(cache->line_size > 0);
256 assert(cache->partitions > 0);
257 assert(cache->associativity > 0);
258 /* We don't implement fully-associative caches */
259 assert(cache->associativity < cache->sets);
260 *ebx = (cache->line_size - 1) |
261 ((cache->partitions - 1) << 12) |
262 ((cache->associativity - 1) << 22);
263
264 assert(cache->sets > 0);
265 *ecx = cache->sets - 1;
266
267 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
268 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
269 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
270}
271
272/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
273static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
274{
275 assert(cache->size % 1024 == 0);
276 assert(cache->lines_per_tag > 0);
277 assert(cache->associativity > 0);
278 assert(cache->line_size > 0);
279 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
280 (cache->lines_per_tag << 8) | (cache->line_size);
281}
5e891bf8
EH		 282
283#define ASSOC_FULL 0xFF
284
285/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
286#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
287 a == 2 ? 0x2 : \
288 a == 4 ? 0x4 : \
289 a == 8 ? 0x6 : \
290 a == 16 ? 0x8 : \
291 a == 32 ? 0xA : \
292 a == 48 ? 0xB : \
293 a == 64 ? 0xC : \
294 a == 96 ? 0xD : \
295 a == 128 ? 0xE : \
296 a == ASSOC_FULL ? 0xF : \
297 0 /* invalid value */)
298
7e3482f8
EH		 299/*
300 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
301 * @l3 can be NULL.
302 */
303static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
304 CPUCacheInfo *l3,
305 uint32_t *ecx, uint32_t *edx)
306{
307 assert(l2->size % 1024 == 0);
308 assert(l2->associativity > 0);
309 assert(l2->lines_per_tag > 0);
310 assert(l2->line_size > 0);
311 *ecx = ((l2->size / 1024) << 16) |
312 (AMD_ENC_ASSOC(l2->associativity) << 12) |
313 (l2->lines_per_tag << 8) | (l2->line_size);
314
315 if (l3) {
316 assert(l3->size % (512 * 1024) == 0);
317 assert(l3->associativity > 0);
318 assert(l3->lines_per_tag > 0);
319 assert(l3->line_size > 0);
320 *edx = ((l3->size / (512 * 1024)) << 18) |
321 (AMD_ENC_ASSOC(l3->associativity) << 12) |
322 (l3->lines_per_tag << 8) | (l3->line_size);
323 } else {
324 *edx = 0;
325 }
326}
5e891bf8 327
8f4202fb 328/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 329static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
330 X86CPUTopoInfo *topo_info,
331 uint32_t *eax, uint32_t *ebx,
332 uint32_t *ecx, uint32_t *edx)
8f4202fb 333{
2f084d1e 334 uint32_t l3_threads;
8f4202fb
BM		 335 assert(cache->size == cache->line_size * cache->associativity *
336 cache->partitions * cache->sets);
337
338 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
339 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
340
341 /* L3 is shared among multiple cores */
342 if (cache->level == 3) {
2f084d1e
BM		 343 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
344 *eax |= (l3_threads - 1) << 14;
8f4202fb 345 } else {
2f084d1e 346 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 347 }
348
349 assert(cache->line_size > 0);
350 assert(cache->partitions > 0);
351 assert(cache->associativity > 0);
352 /* We don't implement fully-associative caches */
353 assert(cache->associativity < cache->sets);
354 *ebx = (cache->line_size - 1) |
355 ((cache->partitions - 1) << 12) |
356 ((cache->associativity - 1) << 22);
357
358 assert(cache->sets > 0);
359 *ecx = cache->sets - 1;
360
361 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
362 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
363 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
364}
365
ed78467a 366/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 367static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
368 uint32_t *eax, uint32_t *ebx,
369 uint32_t *ecx, uint32_t *edx)
ed78467a 370{
31ada106
BM		 371 X86CPUTopoIDs topo_ids;
372
373 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 374
ed78467a 375 *eax = cpu->apic_id;
31ada106 376
ed78467a 377 /*
31ada106
BM		 378 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
379 * Read-only. Reset: 0000_XXXXh.
380 * See Core::X86::Cpuid::ExtApicId.
381 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
382 * Bits Description
383 * 31:16 Reserved.
384 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
385 * The number of threads per core is ThreadsPerCore+1.
386 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
387 *
388 * NOTE: CoreId is already part of apic_id. Just use it. We can
389 * use all the 8 bits to represent the core_id here.
ed78467a 390 */
31ada106
BM		 391 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
392
ed78467a 393 /*
31ada106
BM		 394 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
395 * Read-only. Reset: 0000_0XXXh.
396 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
397 * Bits Description
398 * 31:11 Reserved.
399 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
400 * ValidValues:
401 * Value Description
402 * 000b 1 node per processor.
403 * 001b 2 nodes per processor.
404 * 010b Reserved.
405 * 011b 4 nodes per processor.
406 * 111b-100b Reserved.
407 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
408 *
409 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
410 * But users can create more nodes than the actual hardware can
411 * support. To genaralize we can use all the upper 8 bits for nodes.
412 * NodeId is combination of node and socket_id which is already decoded
413 * in apic_id. Just use it by shifting.
ed78467a 414 */
31ada106
BM		 415 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
416 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
417
ed78467a
BM		 418 *edx = 0;
419}
420
ab8f992e
BM		 421/*
422 * Definitions of the hardcoded cache entries we expose:
423 * These are legacy cache values. If there is a need to change any
424 * of these values please use builtin_x86_defs
425 */
5e891bf8
EH		 426
427/* L1 data cache: */
ab8f992e 428static CPUCacheInfo legacy_l1d_cache = {
5f00335a 429 .type = DATA_CACHE,
7e3482f8
EH		 430 .level = 1,
431 .size = 32 * KiB,
432 .self_init = 1,
433 .line_size = 64,
434 .associativity = 8,
435 .sets = 64,
436 .partitions = 1,
437 .no_invd_sharing = true,
438};
439
5e891bf8 440/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 441static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 442 .type = DATA_CACHE,
7e3482f8
EH		 443 .level = 1,
444 .size = 64 * KiB,
445 .self_init = 1,
446 .line_size = 64,
447 .associativity = 2,
448 .sets = 512,
449 .partitions = 1,
450 .lines_per_tag = 1,
451 .no_invd_sharing = true,
452};
5e891bf8
EH		 453
454/* L1 instruction cache: */
ab8f992e 455static CPUCacheInfo legacy_l1i_cache = {
5f00335a 456 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 457 .level = 1,
458 .size = 32 * KiB,
459 .self_init = 1,
460 .line_size = 64,
461 .associativity = 8,
462 .sets = 64,
463 .partitions = 1,
464 .no_invd_sharing = true,
465};
466
5e891bf8 467/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 468static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 469 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 470 .level = 1,
471 .size = 64 * KiB,
472 .self_init = 1,
473 .line_size = 64,
474 .associativity = 2,
475 .sets = 512,
476 .partitions = 1,
477 .lines_per_tag = 1,
478 .no_invd_sharing = true,
479};
5e891bf8
EH		 480
481/* Level 2 unified cache: */
ab8f992e 482static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 483 .type = UNIFIED_CACHE,
484 .level = 2,
485 .size = 4 * MiB,
486 .self_init = 1,
487 .line_size = 64,
488 .associativity = 16,
489 .sets = 4096,
490 .partitions = 1,
491 .no_invd_sharing = true,
492};
493
5e891bf8 494/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 495static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 496 .type = UNIFIED_CACHE,
497 .level = 2,
498 .size = 2 * MiB,
499 .line_size = 64,
500 .associativity = 8,
501};
502
503
5e891bf8 504/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 505static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 506 .type = UNIFIED_CACHE,
507 .level = 2,
508 .size = 512 * KiB,
509 .line_size = 64,
510 .lines_per_tag = 1,
511 .associativity = 16,
512 .sets = 512,
513 .partitions = 1,
514};
5e891bf8 515
14c985cf 516/* Level 3 unified cache: */
ab8f992e 517static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 518 .type = UNIFIED_CACHE,
519 .level = 3,
520 .size = 16 * MiB,
521 .line_size = 64,
522 .associativity = 16,
523 .sets = 16384,
524 .partitions = 1,
525 .lines_per_tag = 1,
526 .self_init = true,
527 .inclusive = true,
528 .complex_indexing = true,
529};
5e891bf8
EH		 530
531/* TLB definitions: */
532
533#define L1_DTLB_2M_ASSOC 1
534#define L1_DTLB_2M_ENTRIES 255
535#define L1_DTLB_4K_ASSOC 1
536#define L1_DTLB_4K_ENTRIES 255
537
538#define L1_ITLB_2M_ASSOC 1
539#define L1_ITLB_2M_ENTRIES 255
540#define L1_ITLB_4K_ASSOC 1
541#define L1_ITLB_4K_ENTRIES 255
542
543#define L2_DTLB_2M_ASSOC 0 /* disabled */
544#define L2_DTLB_2M_ENTRIES 0 /* disabled */
545#define L2_DTLB_4K_ASSOC 4
546#define L2_DTLB_4K_ENTRIES 512
547
548#define L2_ITLB_2M_ASSOC 0 /* disabled */
549#define L2_ITLB_2M_ENTRIES 0 /* disabled */
550#define L2_ITLB_4K_ASSOC 4
551#define L2_ITLB_4K_ENTRIES 512
552
e37a5c7f
CP		 553/* CPUID Leaf 0x14 constants: */
554#define INTEL_PT_MAX_SUBLEAF 0x1
555/*
556 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
557 * MSR can be accessed;
558 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
559 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
560 * of Intel PT MSRs across warm reset;
561 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
562 */
563#define INTEL_PT_MINIMAL_EBX 0xf
564/*
565 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
566 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
567 * accessed;
568 * bit[01]: ToPA tables can hold any number of output entries, up to the
569 * maximum allowed by the MaskOrTableOffset field of
570 * IA32_RTIT_OUTPUT_MASK_PTRS;
571 * bit[02]: Support Single-Range Output scheme;
572 */
573#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 574/* generated packets which contain IP payloads have LIP values */
575#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 576#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
577#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
578#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
579#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
580#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 581
f21a4817
JL		 582/* CPUID Leaf 0x1D constants: */
583#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
584#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
585#define INTEL_AMX_BYTES_PER_TILE 0x400
586#define INTEL_AMX_BYTES_PER_ROW 0x40
587#define INTEL_AMX_TILE_MAX_NAMES 0x8
588#define INTEL_AMX_TILE_MAX_ROWS 0x10
589
590/* CPUID Leaf 0x1E constants: */
591#define INTEL_AMX_TMUL_MAX_K 0x10
592#define INTEL_AMX_TMUL_MAX_N 0x40
593
f5cc5a5c
CF		 594void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
595 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 596{
597 int i;
598 for (i = 0; i < 4; i++) {
599 dst[i] = vendor1 >> (8 * i);
600 dst[i + 4] = vendor2 >> (8 * i);
601 dst[i + 8] = vendor3 >> (8 * i);
602 }
603 dst[CPUID_VENDOR_SZ] = '\0';
604}
605
621626ce
EH		 606#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
607#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
608 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
609#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
610 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
611 CPUID_PSE36 | CPUID_FXSR)
612#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
613#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
614 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
615 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
616 CPUID_PAE | CPUID_SEP | CPUID_APIC)
617
618#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
619 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
620 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
621 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 622 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 623 /* partly implemented:
624 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
625 /* missing:
626 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
d903259d
PB		 627
628/*
629 * Kernel-only features that can be shown to usermode programs even if
630 * they aren't actually supported by TCG, because qemu-user only runs
631 * in CPL=3; remove them if they are ever implemented for system emulation.
632 */
633#if defined CONFIG_USER_ONLY
774204cf
BQM		 634#define CPUID_EXT_KERNEL_FEATURES \
635 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER)
d903259d
PB		 636#else
637#define CPUID_EXT_KERNEL_FEATURES 0
638#endif
621626ce
EH		 639#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
2872b0f3 644 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
774204cf 645 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES)
621626ce
EH		 646 /* missing:
647 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
2872b0f3 648 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
621626ce 649 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
774204cf
BQM		 650 CPUID_EXT_TSC_DEADLINE_TIMER
651 */
621626ce
EH		 652
653#ifdef TARGET_X86_64
63fd8ef0 654#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
621626ce
EH		 655#else
656#define TCG_EXT2_X86_64_FEATURES 0
657#endif
658
d903259d
PB		 659/*
660 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable
661 * in usermode or by 32-bit programs. Those are added to supported
662 * TCG features unconditionally in user-mode emulation mode. This may
663 * indeed seem strange or incorrect, but it works because code running
664 * under usermode emulation cannot access them.
665 *
666 * Even for long mode, qemu-i386 is not running "a userspace program on a
667 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
668 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit
669 * but again the difference is only visible in kernel mode.
670 */
40a205da
PB		 671#if defined CONFIG_LINUX_USER
672#define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR)
673#elif defined CONFIG_USER_ONLY
674/* FIXME: Long mode not yet supported for i386 bsd-user */
d903259d
PB		 675#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
676#else
677#define CPUID_EXT2_KERNEL_FEATURES 0
678#endif
679
621626ce
EH		 680#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
681 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
682 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
d903259d
PB		 683 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \
684 CPUID_EXT2_KERNEL_FEATURES)
685
686#if defined CONFIG_USER_ONLY
687#define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW
688#else
689#define CPUID_EXT3_KERNEL_FEATURES 0
690#endif
691
621626ce 692#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
8afce497 693 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
d903259d
PB		 694 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES)
695
621626ce 696#define TCG_EXT4_FEATURES 0
d903259d
PB		 697
698#if defined CONFIG_USER_ONLY
699#define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI)
700#else
701#define CPUID_SVM_KERNEL_FEATURES 0
702#endif
900eeca5 703#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
d903259d
PB		 704 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES)
705
621626ce 706#define TCG_KVM_FEATURES 0
d903259d
PB		 707
708#if defined CONFIG_USER_ONLY
709#define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID
710#else
711#define CPUID_7_0_EBX_KERNEL_FEATURES 0
712#endif
621626ce 713#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 714 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
715 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386 716 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
d903259d 717 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \
e582b629 718 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES)
621626ce 719 /* missing:
2f8a21d8 720 CPUID_7_0_EBX_HLE
691925e5 721 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
6750485b 722
1da389c5 723#if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX
6750485b
PB		 724#define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
725#else
726#define TCG_7_0_ECX_RDPID 0
727#endif
637f1ee3 728#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
9ccb9784 729 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6750485b
PB		 730 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
731 TCG_7_0_ECX_RDPID)
732
d903259d
PB		 733#if defined CONFIG_USER_ONLY
734#define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \
735 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD)
736#else
737#define CPUID_7_0_EDX_KERNEL_FEATURES 0
738#endif
739#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES)
740
58794f64 741#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
405c7c07 742 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD)
eaaa197d 743#define TCG_7_1_EDX_FEATURES 0
9dd8b710 744#define TCG_7_2_EDX_FEATURES 0
303752a9 745#define TCG_APM_FEATURES 0
28b8e4d0 746#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 747#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
748 /* missing:
749 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 750#define TCG_14_0_ECX_FEATURES 0
4b841a79 751#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 752#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 753#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 754
d903259d
PB		 755#if defined CONFIG_USER_ONLY
756#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
757 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \
758 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \
759 CPUID_8000_0008_EBX_AMD_PSFD)
760#else
761#define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
762#endif
763
431c51e9 764#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
d903259d 765 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES)
1420dd6a 766
79f1a68a 767FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 768 [FEAT_1_EDX] = {
07585923 769 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 770 .feat_names = {
771 "fpu", "vme", "de", "pse",
772 "tsc", "msr", "pae", "mce",
773 "cx8", "apic", NULL, "sep",
774 "mtrr", "pge", "mca", "cmov",
775 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
776 NULL, "ds" /* Intel dts */, "acpi", "mmx",
777 "fxsr", "sse", "sse2", "ss",
778 "ht" /* Intel htt */, "tm", "ia64", "pbe",
779 },
07585923 780 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 781 .tcg_features = TCG_FEATURES,
83629b14 782 .no_autoenable_flags = CPUID_HT,
bffd67b0
EH		 783 },
784 [FEAT_1_ECX] = {
07585923 785 .type = CPUID_FEATURE_WORD,
2d5312da 786 .feat_names = {
16d2fcaa 787 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 788 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 789 "tm2", "ssse3", "cid", NULL,
790 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 791 NULL, "pcid", "dca", "sse4.1",
792 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 793 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 794 "avx", "f16c", "rdrand", "hypervisor",
795 },
07585923 796 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 797 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 798 },
2d5312da
EH		 799 /* Feature names that are already defined on feature_name[] but
800 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
801 * names on feat_names below. They are copied automatically
802 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
803 */
bffd67b0 804 [FEAT_8000_0001_EDX] = {
07585923 805 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 806 .feat_names = {
807 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
808 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
809 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
810 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
811 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 812 "nx", NULL, "mmxext", NULL /* mmx */,
813 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
814 NULL, "lm", "3dnowext", "3dnow",
2d5312da 815 },
07585923 816 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 817 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 818 },
819 [FEAT_8000_0001_ECX] = {
07585923 820 .type = CPUID_FEATURE_WORD,
2d5312da 821 .feat_names = {
fc7dfd20 822 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 823 "cr8legacy", "abm", "sse4a", "misalignsse",
824 "3dnowprefetch", "osvw", "ibs", "xop",
825 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 826 "fma4", "tce", NULL, "nodeid-msr",
827 NULL, "tbm", "topoext", "perfctr-core",
828 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 829 NULL, NULL, NULL, NULL,
830 },
07585923 831 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 832 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 833 /*
834 * TOPOEXT is always allowed but can't be enabled blindly by
835 * "-cpu host", as it requires consistent cache topology info
836 * to be provided so it doesn't confuse guests.
837 */
838 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 839 },
89e49c8b 840 [FEAT_C000_0001_EDX] = {
07585923 841 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 842 .feat_names = {
843 NULL, NULL, "xstore", "xstore-en",
844 NULL, NULL, "xcrypt", "xcrypt-en",
845 "ace2", "ace2-en", "phe", "phe-en",
846 "pmm", "pmm-en", NULL, NULL,
847 NULL, NULL, NULL, NULL,
848 NULL, NULL, NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 },
07585923 852 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 853 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 854 },
bffd67b0 855 [FEAT_KVM] = {
07585923 856 .type = CPUID_FEATURE_WORD,
2d5312da 857 .feat_names = {
fc7dfd20
EH		 858 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
859 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
eba97806 860 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
c1bb5418 861 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 "kvmclock-stable-bit", NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 },
07585923 867 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 868 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 869 },
be777326 870 [FEAT_KVM_HINTS] = {
07585923 871 .type = CPUID_FEATURE_WORD,
be777326
WL		 872 .feat_names = {
873 "kvm-hint-dedicated", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 NULL, NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
07585923 882 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 883 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 884 /*
885 * KVM hints aren't auto-enabled by -cpu host, they need to be
886 * explicitly enabled in the command-line.
887 */
888 .no_autoenable_flags = ~0U,
be777326 889 },
bffd67b0 890 [FEAT_SVM] = {
07585923 891 .type = CPUID_FEATURE_WORD,
2d5312da 892 .feat_names = {
fc7dfd20
EH		 893 "npt", "lbrv", "svm-lock", "nrip-save",
894 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
895 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 896 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
897 "vgif", NULL, NULL, NULL,
2d5312da 898 NULL, NULL, NULL, NULL,
62a798d4 899 NULL, "vnmi", NULL, NULL,
5447089c 900 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 901 },
07585923 902 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 903 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 904 },
905 [FEAT_7_0_EBX] = {
07585923 906 .type = CPUID_FEATURE_WORD,
2d5312da 907 .feat_names = {
5c76b651 908 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 909 "hle", "avx2", NULL, "smep",
910 "bmi2", "erms", "invpcid", "rtm",
911 NULL, NULL, "mpx", NULL,
912 "avx512f", "avx512dq", "rdseed", "adx",
913 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 914 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 915 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 916 },
07585923
RH		 917 .cpuid = {
918 .eax = 7,
919 .needs_ecx = true, .ecx = 0,
920 .reg = R_EBX,
921 },
37ce3522 922 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 923 },
f74eefe0 924 [FEAT_7_0_ECX] = {
07585923 925 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 926 .feat_names = {
927 NULL, "avx512vbmi", "umip", "pku",
67192a29 928 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 929 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
930 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 931 "la57", NULL, NULL, NULL,
2d5312da 932 NULL, NULL, "rdpid", NULL,
06e878b4 933 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 934 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 935 },
07585923
RH		 936 .cpuid = {
937 .eax = 7,
938 .needs_ecx = true, .ecx = 0,
939 .reg = R_ECX,
940 },
f74eefe0
HH		 941 .tcg_features = TCG_7_0_ECX_FEATURES,
942 },
95ea69fb 943 [FEAT_7_0_EDX] = {
07585923 944 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 945 .feat_names = {
946 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 947 "fsrm", NULL, NULL, NULL,
353f98c9 948 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 949 NULL, NULL, "serialize", NULL,
c3c67679 950 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
f21a4817
JL		 951 NULL, NULL, "amx-bf16", "avx512-fp16",
952 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
0e7e3bf1 953 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
95ea69fb 954 },
07585923
RH		 955 .cpuid = {
956 .eax = 7,
957 .needs_ecx = true, .ecx = 0,
958 .reg = R_EDX,
959 },
95ea69fb
LK		 960 .tcg_features = TCG_7_0_EDX_FEATURES,
961 },
80db491d
JL		 962 [FEAT_7_1_EAX] = {
963 .type = CPUID_FEATURE_WORD,
964 .feat_names = {
965 NULL, NULL, NULL, NULL,
a9ce107f 966 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
58794f64
PB		 967 NULL, NULL, "fzrm", "fsrs",
968 "fsrc", NULL, NULL, NULL,
80db491d 969 NULL, NULL, NULL, NULL,
a957a884 970 NULL, "amx-fp16", NULL, "avx-ifma",
80db491d
JL		 971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 },
974 .cpuid = {
975 .eax = 7,
976 .needs_ecx = true, .ecx = 1,
977 .reg = R_EAX,
978 },
979 .tcg_features = TCG_7_1_EAX_FEATURES,
980 },
eaaa197d
JC		 981 [FEAT_7_1_EDX] = {
982 .type = CPUID_FEATURE_WORD,
983 .feat_names = {
984 NULL, NULL, NULL, NULL,
ecd2e6ca 985 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
3e76bafb 986 "amx-complex", NULL, NULL, NULL,
d1a11115 987 NULL, NULL, "prefetchiti", NULL,
eaaa197d
JC		 988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
993 .cpuid = {
994 .eax = 7,
995 .needs_ecx = true, .ecx = 1,
996 .reg = R_EDX,
997 },
998 .tcg_features = TCG_7_1_EDX_FEATURES,
999 },
9dd8b710
TS		 1000 [FEAT_7_2_EDX] = {
1001 .type = CPUID_FEATURE_WORD,
1002 .feat_names = {
1003 NULL, NULL, NULL, NULL,
1004 NULL, "mcdt-no", NULL, NULL,
1005 NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 },
1012 .cpuid = {
1013 .eax = 7,
1014 .needs_ecx = true, .ecx = 2,
1015 .reg = R_EDX,
1016 },
1017 .tcg_features = TCG_7_2_EDX_FEATURES,
1018 },
303752a9 1019 [FEAT_8000_0007_EDX] = {
07585923 1020 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1021 .feat_names = {
1022 NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL,
1024 "invtsc", NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 NULL, NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 },
07585923 1031 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1032 .tcg_features = TCG_APM_FEATURES,
1033 .unmigratable_flags = CPUID_APM_INVTSC,
1034 },
1b3420e1 1035 [FEAT_8000_0008_EBX] = {
07585923 1036 .type = CPUID_FEATURE_WORD,
1b3420e1 1037 .feat_names = {
e900135d 1038 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 1039 NULL, NULL, NULL, NULL,
59a80a19 1040 NULL, "wbnoinvd", NULL, NULL,
623972ce 1041 "ibpb", NULL, "ibrs", "amd-stibp",
bb039a23 1042 NULL, "stibp-always-on", NULL, NULL,
1b3420e1 1043 NULL, NULL, NULL, NULL,
254790a9 1044 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
bb039a23 1045 "amd-psfd", NULL, NULL, NULL,
1b3420e1 1046 },
07585923 1047 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1420dd6a 1048 .tcg_features = TCG_8000_0008_EBX,
1b3420e1
EH		 1049 .unmigratable_flags = 0,
1050 },
b70eec31
BM		 1051 [FEAT_8000_0021_EAX] = {
1052 .type = CPUID_FEATURE_WORD,
1053 .feat_names = {
1054 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
1055 NULL, NULL, "null-sel-clr-base", NULL,
62a798d4 1056 "auto-ibrs", NULL, NULL, NULL,
b70eec31
BM		 1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL,
1062 },
1063 .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
1064 .tcg_features = 0,
1065 .unmigratable_flags = 0,
1066 },
0bb0b2d2 1067 [FEAT_XSAVE] = {
07585923 1068 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1069 .feat_names = {
1070 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
f21a4817 1071 "xfd", NULL, NULL, NULL,
2d5312da
EH		 1072 NULL, NULL, NULL, NULL,
1073 NULL, NULL, NULL, NULL,
1074 NULL, NULL, NULL, NULL,
1075 NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL,
1078 },
07585923
RH		 1079 .cpuid = {
1080 .eax = 0xd,
1081 .needs_ecx = true, .ecx = 1,
1082 .reg = R_EAX,
1083 },
c9cfe8f9 1084 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1085 },
301e9067
YW		 1086 [FEAT_XSAVE_XSS_LO] = {
1087 .type = CPUID_FEATURE_WORD,
1088 .feat_names = {
1089 NULL, NULL, NULL, NULL,
1090 NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, NULL,
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 },
1098 .cpuid = {
1099 .eax = 0xD,
1100 .needs_ecx = true,
1101 .ecx = 1,
1102 .reg = R_ECX,
1103 },
1104 },
1105 [FEAT_XSAVE_XSS_HI] = {
1106 .type = CPUID_FEATURE_WORD,
1107 .cpuid = {
1108 .eax = 0xD,
1109 .needs_ecx = true,
1110 .ecx = 1,
1111 .reg = R_EDX
1112 },
1113 },
28b8e4d0 1114 [FEAT_6_EAX] = {
07585923 1115 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1116 .feat_names = {
1117 NULL, NULL, "arat", NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
07585923 1126 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1127 .tcg_features = TCG_6_EAX_FEATURES,
1128 },
301e9067 1129 [FEAT_XSAVE_XCR0_LO] = {
07585923
RH		 1130 .type = CPUID_FEATURE_WORD,
1131 .cpuid = {
1132 .eax = 0xD,
1133 .needs_ecx = true, .ecx = 0,
1134 .reg = R_EAX,
1135 },
96193c22 1136 .tcg_features = ~0U,
6fb2fff7
EH		 1137 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1138 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1139 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1140 XSTATE_PKRU_MASK,
96193c22 1141 },
301e9067 1142 [FEAT_XSAVE_XCR0_HI] = {
07585923
RH		 1143 .type = CPUID_FEATURE_WORD,
1144 .cpuid = {
1145 .eax = 0xD,
1146 .needs_ecx = true, .ecx = 0,
1147 .reg = R_EDX,
1148 },
96193c22
EH		 1149 .tcg_features = ~0U,
1150 },
d86f9636
RH		 1151 /*Below are MSR exposed features*/
1152 [FEAT_ARCH_CAPABILITIES] = {
1153 .type = MSR_FEATURE_WORD,
1154 .feat_names = {
1155 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1156 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1157 "taa-no", NULL, NULL, NULL,
5bef742c 1158 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
22e1094c 1159 NULL, "fb-clear", NULL, NULL,
d86f9636 1160 NULL, NULL, NULL, NULL,
41bdd981
PG		 1161 "pbrsb-no", NULL, "gds-no", "rfds-no",
1162 "rfds-clear", NULL, NULL, NULL,
d86f9636
RH		 1163 },
1164 .msr = {
1165 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636 1166 },
9fb4f5f5
PB		 1167 /*
1168 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1169 * cannot be read from user mode. Therefore, it has no impact
1170 > on any user-mode operation, and warnings about unsupported
1171 * features do not matter.
1172 */
1173 .tcg_features = ~0U,
d86f9636 1174 },
597360c0
XL		 1175 [FEAT_CORE_CAPABILITY] = {
1176 .type = MSR_FEATURE_WORD,
1177 .feat_names = {
1178 NULL, NULL, NULL, NULL,
1179 NULL, "split-lock-detect", NULL, NULL,
1180 NULL, NULL, NULL, NULL,
1181 NULL, NULL, NULL, NULL,
1182 NULL, NULL, NULL, NULL,
1183 NULL, NULL, NULL, NULL,
1184 NULL, NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 },
1187 .msr = {
1188 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1189 },
1190 },
ea39f9b6
LX		 1191 [FEAT_PERF_CAPABILITIES] = {
1192 .type = MSR_FEATURE_WORD,
1193 .feat_names = {
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 NULL, "full-width-write", NULL, NULL,
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 NULL, NULL, NULL, NULL,
1202 },
1203 .msr = {
1204 .index = MSR_IA32_PERF_CAPABILITIES,
1205 },
1206 },
20a78b02
PB		 1207
1208 [FEAT_VMX_PROCBASED_CTLS] = {
1209 .type = MSR_FEATURE_WORD,
1210 .feat_names = {
1211 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1212 NULL, NULL, NULL, "vmx-hlt-exit",
1213 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1214 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1215 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1216 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1217 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1218 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1219 },
1220 .msr = {
1221 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1222 }
1223 },
1224
1225 [FEAT_VMX_SECONDARY_CTLS] = {
1226 .type = MSR_FEATURE_WORD,
1227 .feat_names = {
1228 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1229 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1230 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1231 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1232 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1233 "vmx-xsaves", NULL, NULL, NULL,
33cc8826 1234 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
20a78b02
PB		 1235 NULL, NULL, NULL, NULL,
1236 },
1237 .msr = {
1238 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1239 }
1240 },
1241
1242 [FEAT_VMX_PINBASED_CTLS] = {
1243 .type = MSR_FEATURE_WORD,
1244 .feat_names = {
1245 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1246 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1247 NULL, NULL, NULL, NULL,
1248 NULL, NULL, NULL, NULL,
1249 NULL, NULL, NULL, NULL,
1250 NULL, NULL, NULL, NULL,
1251 NULL, NULL, NULL, NULL,
1252 NULL, NULL, NULL, NULL,
1253 },
1254 .msr = {
1255 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1256 }
1257 },
1258
1259 [FEAT_VMX_EXIT_CTLS] = {
1260 .type = MSR_FEATURE_WORD,
1261 /*
1262 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1263 * the LM CPUID bit.
1264 */
1265 .feat_names = {
1266 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1267 NULL, NULL, NULL, NULL,
1268 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1269 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1270 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1271 "vmx-exit-save-efer", "vmx-exit-load-efer",
1272 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1273 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1274 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1275 },
1276 .msr = {
1277 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1278 }
1279 },
1280
1281 [FEAT_VMX_ENTRY_CTLS] = {
1282 .type = MSR_FEATURE_WORD,
1283 .feat_names = {
1284 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1285 NULL, NULL, NULL, NULL,
1286 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1287 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1288 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1289 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1290 NULL, NULL, NULL, NULL,
1291 NULL, NULL, NULL, NULL,
1292 },
1293 .msr = {
1294 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1295 }
1296 },
1297
1298 [FEAT_VMX_MISC] = {
1299 .type = MSR_FEATURE_WORD,
1300 .feat_names = {
1301 NULL, NULL, NULL, NULL,
1302 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1303 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1304 NULL, NULL, NULL, NULL,
1305 NULL, NULL, NULL, NULL,
1306 NULL, NULL, NULL, NULL,
1307 NULL, NULL, NULL, NULL,
1308 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1309 },
1310 .msr = {
1311 .index = MSR_IA32_VMX_MISC,
1312 }
1313 },
1314
1315 [FEAT_VMX_EPT_VPID_CAPS] = {
1316 .type = MSR_FEATURE_WORD,
1317 .feat_names = {
1318 "vmx-ept-execonly", NULL, NULL, NULL,
1319 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1320 NULL, NULL, NULL, NULL,
1321 NULL, NULL, NULL, NULL,
1322 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1323 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1324 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1325 NULL, NULL, NULL, NULL,
1326 "vmx-invvpid", NULL, NULL, NULL,
1327 NULL, NULL, NULL, NULL,
1328 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1329 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1330 NULL, NULL, NULL, NULL,
1331 NULL, NULL, NULL, NULL,
1332 NULL, NULL, NULL, NULL,
1333 NULL, NULL, NULL, NULL,
1334 NULL, NULL, NULL, NULL,
1335 },
1336 .msr = {
1337 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1338 }
1339 },
1340
1341 [FEAT_VMX_BASIC] = {
1342 .type = MSR_FEATURE_WORD,
1343 .feat_names = {
1344 [54] = "vmx-ins-outs",
1345 [55] = "vmx-true-ctls",
0c49c918 1346 [56] = "vmx-any-errcode",
20a78b02
PB		 1347 },
1348 .msr = {
1349 .index = MSR_IA32_VMX_BASIC,
1350 },
1351 /* Just to be safe - we don't support setting the MSEG version field. */
1352 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1353 },
1354
1355 [FEAT_VMX_VMFUNC] = {
1356 .type = MSR_FEATURE_WORD,
1357 .feat_names = {
1358 [0] = "vmx-eptp-switching",
1359 },
1360 .msr = {
1361 .index = MSR_IA32_VMX_VMFUNC,
1362 }
1363 },
1364
d1615ea5
LK		 1365 [FEAT_14_0_ECX] = {
1366 .type = CPUID_FEATURE_WORD,
1367 .feat_names = {
1368 NULL, NULL, NULL, NULL,
1369 NULL, NULL, NULL, NULL,
1370 NULL, NULL, NULL, NULL,
1371 NULL, NULL, NULL, NULL,
1372 NULL, NULL, NULL, NULL,
1373 NULL, NULL, NULL, NULL,
1374 NULL, NULL, NULL, NULL,
1375 NULL, NULL, NULL, "intel-pt-lip",
1376 },
1377 .cpuid = {
1378 .eax = 0x14,
1379 .needs_ecx = true, .ecx = 0,
1380 .reg = R_ECX,
1381 },
1382 .tcg_features = TCG_14_0_ECX_FEATURES,
1383 },
1384
4b841a79
SC		 1385 [FEAT_SGX_12_0_EAX] = {
1386 .type = CPUID_FEATURE_WORD,
1387 .feat_names = {
1388 "sgx1", "sgx2", NULL, NULL,
1389 NULL, NULL, NULL, NULL,
d45f24fe 1390 NULL, NULL, NULL, "sgx-edeccssa",
4b841a79
SC		 1391 NULL, NULL, NULL, NULL,
1392 NULL, NULL, NULL, NULL,
1393 NULL, NULL, NULL, NULL,
1394 NULL, NULL, NULL, NULL,
1395 NULL, NULL, NULL, NULL,
1396 },
1397 .cpuid = {
1398 .eax = 0x12,
1399 .needs_ecx = true, .ecx = 0,
1400 .reg = R_EAX,
1401 },
1402 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1403 },
120ca112
SC		 1404
1405 [FEAT_SGX_12_0_EBX] = {
1406 .type = CPUID_FEATURE_WORD,
1407 .feat_names = {
1408 "sgx-exinfo" , NULL, NULL, NULL,
1409 NULL, NULL, NULL, NULL,
1410 NULL, NULL, NULL, NULL,
1411 NULL, NULL, NULL, NULL,
1412 NULL, NULL, NULL, NULL,
1413 NULL, NULL, NULL, NULL,
1414 NULL, NULL, NULL, NULL,
1415 NULL, NULL, NULL, NULL,
1416 },
1417 .cpuid = {
1418 .eax = 0x12,
1419 .needs_ecx = true, .ecx = 0,
1420 .reg = R_EBX,
1421 },
1422 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1423 },
165981a5
SC		 1424
1425 [FEAT_SGX_12_1_EAX] = {
1426 .type = CPUID_FEATURE_WORD,
1427 .feat_names = {
1428 NULL, "sgx-debug", "sgx-mode64", NULL,
1429 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
d45f24fe 1430 NULL, NULL, "sgx-aex-notify", NULL,
165981a5
SC		 1431 NULL, NULL, NULL, NULL,
1432 NULL, NULL, NULL, NULL,
1433 NULL, NULL, NULL, NULL,
1434 NULL, NULL, NULL, NULL,
1435 NULL, NULL, NULL, NULL,
1436 },
1437 .cpuid = {
1438 .eax = 0x12,
1439 .needs_ecx = true, .ecx = 1,
1440 .reg = R_EAX,
1441 },
1442 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1443 },
5ef57876
EH		 1444};
1445
99e24dbd
PB		 1446typedef struct FeatureMask {
1447 FeatureWord index;
ede146c2 1448 uint64_t mask;
99e24dbd
PB		 1449} FeatureMask;
1450
1451typedef struct FeatureDep {
1452 FeatureMask from, to;
1453} FeatureDep;
1454
1455static FeatureDep feature_dependencies[] = {
1456 {
1457 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1458 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1459 },
1460 {
1461 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1462 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1463 },
ea39f9b6
LX		 1464 {
1465 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1466 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1467 },
20a78b02
PB		 1468 {
1469 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1470 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1471 },
1472 {
1473 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1474 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1475 },
1476 {
1477 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1478 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1479 },
1480 {
1481 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1482 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1483 },
1484 {
1485 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1486 .to = { FEAT_VMX_MISC, ~0ull },
1487 },
1488 {
1489 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1490 .to = { FEAT_VMX_BASIC, ~0ull },
1491 },
1492 {
1493 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1494 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1495 },
1496 {
1497 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1498 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1499 },
1500 {
1501 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1502 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1503 },
1504 {
1505 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1506 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1507 },
1508 {
1509 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1510 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1511 },
267b5e7e
MS		 1512 {
1513 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1514 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS },
1515 },
1516 {
1517 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1518 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS },
1519 },
20a78b02
PB		 1520 {
1521 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1522 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1523 },
d1615ea5
LK		 1524 {
1525 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1526 .to = { FEAT_14_0_ECX, ~0ull },
1527 },
20a78b02
PB		 1528 {
1529 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1530 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1531 },
1532 {
1533 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1534 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1535 },
1536 {
1537 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1538 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1539 },
1540 {
1541 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1542 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1543 },
1544 {
1545 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1546 .to = { FEAT_VMX_VMFUNC, ~0ull },
1547 },
730319ae
EH		 1548 {
1549 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1550 .to = { FEAT_SVM, ~0ull },
1551 },
33cc8826
AK		 1552 {
1553 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
1554 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
1555 },
99e24dbd
PB		 1556};
1557
8e8aba50
EH		 1558typedef struct X86RegisterInfo32 {
1559 /* Name of register */
1560 const char *name;
1561 /* QAPI enum value register */
1562 X86CPURegister32 qapi_enum;
1563} X86RegisterInfo32;
1564
1565#define REGISTER(reg) \
5d371f41 1566 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1567static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1568 REGISTER(EAX),
1569 REGISTER(ECX),
1570 REGISTER(EDX),
1571 REGISTER(EBX),
1572 REGISTER(ESP),
1573 REGISTER(EBP),
1574 REGISTER(ESI),
1575 REGISTER(EDI),
1576};
1577#undef REGISTER
1578
301e9067 1579/* CPUID feature bits available in XSS */
10f0abcb 1580#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
301e9067 1581
fea45008 1582ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1583 [XSTATE_FP_BIT] = {
1584 /* x87 FP state component is always enabled if XSAVE is supported */
1585 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1586 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1587 },
1588 [XSTATE_SSE_BIT] = {
1589 /* SSE state component is always enabled if XSAVE is supported */
1590 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1591 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1592 },
cfc3b074
PB		 1593 [XSTATE_YMM_BIT] =
1594 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1595 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1596 [XSTATE_BNDREGS_BIT] =
1597 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1598 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1599 [XSTATE_BNDCSR_BIT] =
1600 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1601 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1602 [XSTATE_OPMASK_BIT] =
1603 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1604 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1605 [XSTATE_ZMM_Hi256_BIT] =
1606 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1607 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1608 [XSTATE_Hi16_ZMM_BIT] =
1609 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1610 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1611 [XSTATE_PKRU_BIT] =
1612 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1613 .size = sizeof(XSavePKRU) },
10f0abcb
YW		 1614 [XSTATE_ARCH_LBR_BIT] = {
1615 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
1616 .offset = 0 /*supervisor mode component, offset = 0 */,
1617 .size = sizeof(XSavesArchLBR) },
1f16764f
JL		 1618 [XSTATE_XTILE_CFG_BIT] = {
1619 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1620 .size = sizeof(XSaveXTILECFG),
1621 },
1622 [XSTATE_XTILE_DATA_BIT] = {
1623 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1624 .size = sizeof(XSaveXTILEDATA)
1625 },
2560f19f 1626};
8e8aba50 1627
5d245678 1628uint32_t xsave_area_size(uint64_t mask, bool compacted)
1fda6198 1629{
301e9067
YW		 1630 uint64_t ret = x86_ext_save_areas[0].size;
1631 const ExtSaveArea *esa;
1632 uint32_t offset = 0;
1fda6198 1633 int i;
1fda6198 1634
301e9067
YW		 1635 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1636 esa = &x86_ext_save_areas[i];
1fda6198 1637 if ((mask >> i) & 1) {
301e9067
YW		 1638 offset = compacted ? ret : esa->offset;
1639 ret = MAX(ret, offset + esa->size);
1fda6198
EH		 1640 }
1641 }
1642 return ret;
1643}
1644
d6dcc558
SAGDR		 1645static inline bool accel_uses_host_cpuid(void)
1646{
1647 return kvm_enabled() || hvf_enabled();
1648}
1649
301e9067 1650static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu)
96193c22 1651{
301e9067
YW		 1652 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 |
1653 cpu->env.features[FEAT_XSAVE_XCR0_LO];
96193c22
EH		 1654}
1655
ed69e831
CF		 1656/* Return name of 32-bit register, from a R_* constant */
1657static const char *get_register_name_32(unsigned int reg)
8b4beddc 1658{
31ccdde2 1659 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1660 return NULL;
1661 }
8e8aba50 1662 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1663}
1664
301e9067
YW		 1665static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu)
1666{
1667 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 |
1668 cpu->env.features[FEAT_XSAVE_XSS_LO];
1669}
1670
84f1b92f
EH		 1671/*
1672 * Returns the set of feature flags that are supported and migratable by
1673 * QEMU, for a given FeatureWord.
1674 */
ede146c2 1675static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1676{
1677 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1678 uint64_t r = 0;
84f1b92f
EH		 1679 int i;
1680
ede146c2
PB		 1681 for (i = 0; i < 64; i++) {
1682 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1683
1684 /* If the feature name is known, it is implicitly considered migratable,
1685 * unless it is explicitly set in unmigratable_flags */
1686 if ((wi->migratable_flags & f) ||
1687 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1688 r |= f;
84f1b92f 1689 }
84f1b92f
EH		 1690 }
1691 return r;
1692}
1693
bb44e0d1
JK		 1694void host_cpuid(uint32_t function, uint32_t count,
1695 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1696{
a1fd24af
AL		 1697 uint32_t vec[4];
1698
1699#ifdef __x86_64__
1700 asm volatile("cpuid"
1701 : "=a"(vec[0]), "=b"(vec[1]),
1702 "=c"(vec[2]), "=d"(vec[3])
1703 : "0"(function), "c"(count) : "cc");
c1f41226 1704#elif defined(__i386__)
a1fd24af
AL		 1705 asm volatile("pusha \n\t"
1706 "cpuid \n\t"
1707 "mov %%eax, 0(%2) \n\t"
1708 "mov %%ebx, 4(%2) \n\t"
1709 "mov %%ecx, 8(%2) \n\t"
1710 "mov %%edx, 12(%2) \n\t"
1711 "popa"
1712 : : "a"(function), "c"(count), "S"(vec)
1713 : "memory", "cc");
c1f41226
EH		 1714#else
1715 abort();
a1fd24af
AL		 1716#endif
1717
bdde476a 1718 if (eax)
a1fd24af 1719 *eax = vec[0];
bdde476a 1720 if (ebx)
a1fd24af 1721 *ebx = vec[1];
bdde476a 1722 if (ecx)
a1fd24af 1723 *ecx = vec[2];
bdde476a 1724 if (edx)
a1fd24af 1725 *edx = vec[3];
bdde476a 1726}
c6dc6f63 1727
d940ee9b
EH		 1728/* CPU class name definitions: */
1729
d940ee9b
EH		 1730/* Return type name for a given CPU model name
1731 * Caller is responsible for freeing the returned string.
1732 */
1733static char *x86_cpu_type_name(const char *model_name)
1734{
1735 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1736}
1737
500050d1
AF		 1738static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1739{
88703ce2
EH		 1740 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1741 return object_class_by_name(typename);
500050d1
AF		 1742}
1743
104494ea
IM		 1744static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1745{
1746 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1747 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
4b26aa9f 1748 return cpu_model_from_type(class_name);
104494ea
IM		 1749}
1750
dcafd1ef
EH		 1751typedef struct X86CPUVersionDefinition {
1752 X86CPUVersion version;
53db89d9 1753 const char *alias;
c63938df 1754 const char *note;
dcafd1ef 1755 PropValue *props;
cca0a000 1756 const CPUCaches *const cache_info;
dcafd1ef
EH		 1757} X86CPUVersionDefinition;
1758
1759/* Base definition for a CPU model */
1760typedef struct X86CPUDefinition {
c6dc6f63
AP		 1761 const char *name;
1762 uint32_t level;
90e4b0c3 1763 uint32_t xlevel;
99b88a17
IM		 1764 /* vendor is zero-terminated, 12 character ASCII string */
1765 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1766 int family;
1767 int model;
1768 int stepping;
0514ef2f 1769 FeatureWordArray features;
807e9869 1770 const char *model_id;
e845de38 1771 const CPUCaches *const cache_info;
dcafd1ef
EH		 1772 /*
1773 * Definitions for alternative versions of CPU model.
1774 * List is terminated by item with version == 0.
1775 * If NULL, version 1 will be registered automatically.
1776 */
1777 const X86CPUVersionDefinition *versions;
61ad65d0 1778 const char *deprecation_note;
dcafd1ef
EH		 1779} X86CPUDefinition;
1780
1781/* Reference to a specific CPU model version */
1782struct X86CPUModel {
1783 /* Base CPU definition */
e11fd689 1784 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1785 /* CPU model version */
1786 X86CPUVersion version;
c63938df 1787 const char *note;
0788a56b
EH		 1788 /*
1789 * If true, this is an alias CPU model.
1790 * This matters only for "-cpu help" and query-cpu-definitions
1791 */
1792 bool is_alias;
d940ee9b 1793};
c6dc6f63 1794
dcafd1ef 1795/* Get full model name for CPU version */
e11fd689 1796static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1797 X86CPUVersion version)
1798{
1799 assert(version > 0);
1800 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1801}
1802
e11fd689
PMD		 1803static const X86CPUVersionDefinition *
1804x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1805{
1806 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1807 static const X86CPUVersionDefinition default_version_list[] = {
1808 { 1 },
1809 { /* end of list */ }
1810 };
1811
1812 return def->versions ?: default_version_list;
1813}
1814
e845de38 1815static const CPUCaches epyc_cache_info = {
a9f27ea9 1816 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1817 .type = DATA_CACHE,
fe52acd2
BM		 1818 .level = 1,
1819 .size = 32 * KiB,
1820 .line_size = 64,
1821 .associativity = 8,
1822 .partitions = 1,
1823 .sets = 64,
1824 .lines_per_tag = 1,
1825 .self_init = 1,
1826 .no_invd_sharing = true,
1827 },
a9f27ea9 1828 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1829 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1830 .level = 1,
1831 .size = 64 * KiB,
1832 .line_size = 64,
1833 .associativity = 4,
1834 .partitions = 1,
1835 .sets = 256,
1836 .lines_per_tag = 1,
1837 .self_init = 1,
1838 .no_invd_sharing = true,
1839 },
a9f27ea9 1840 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1841 .type = UNIFIED_CACHE,
1842 .level = 2,
1843 .size = 512 * KiB,
1844 .line_size = 64,
1845 .associativity = 8,
1846 .partitions = 1,
1847 .sets = 1024,
1848 .lines_per_tag = 1,
1849 },
a9f27ea9 1850 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1851 .type = UNIFIED_CACHE,
1852 .level = 3,
1853 .size = 8 * MiB,
1854 .line_size = 64,
1855 .associativity = 16,
1856 .partitions = 1,
1857 .sets = 8192,
1858 .lines_per_tag = 1,
1859 .self_init = true,
1860 .inclusive = true,
1861 .complex_indexing = true,
1862 },
1863};
1864
d7c72735
MR		 1865static CPUCaches epyc_v4_cache_info = {
1866 .l1d_cache = &(CPUCacheInfo) {
1867 .type = DATA_CACHE,
1868 .level = 1,
1869 .size = 32 * KiB,
1870 .line_size = 64,
1871 .associativity = 8,
1872 .partitions = 1,
1873 .sets = 64,
1874 .lines_per_tag = 1,
1875 .self_init = 1,
1876 .no_invd_sharing = true,
1877 },
1878 .l1i_cache = &(CPUCacheInfo) {
1879 .type = INSTRUCTION_CACHE,
1880 .level = 1,
1881 .size = 64 * KiB,
1882 .line_size = 64,
1883 .associativity = 4,
1884 .partitions = 1,
1885 .sets = 256,
1886 .lines_per_tag = 1,
1887 .self_init = 1,
1888 .no_invd_sharing = true,
1889 },
1890 .l2_cache = &(CPUCacheInfo) {
1891 .type = UNIFIED_CACHE,
1892 .level = 2,
1893 .size = 512 * KiB,
1894 .line_size = 64,
1895 .associativity = 8,
1896 .partitions = 1,
1897 .sets = 1024,
1898 .lines_per_tag = 1,
1899 },
1900 .l3_cache = &(CPUCacheInfo) {
1901 .type = UNIFIED_CACHE,
1902 .level = 3,
1903 .size = 8 * MiB,
1904 .line_size = 64,
1905 .associativity = 16,
1906 .partitions = 1,
1907 .sets = 8192,
1908 .lines_per_tag = 1,
1909 .self_init = true,
1910 .inclusive = true,
1911 .complex_indexing = false,
1912 },
1913};
1914
e845de38 1915static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1916 .l1d_cache = &(CPUCacheInfo) {
1917 .type = DATA_CACHE,
1918 .level = 1,
1919 .size = 32 * KiB,
1920 .line_size = 64,
1921 .associativity = 8,
1922 .partitions = 1,
1923 .sets = 64,
1924 .lines_per_tag = 1,
1925 .self_init = 1,
1926 .no_invd_sharing = true,
1927 },
1928 .l1i_cache = &(CPUCacheInfo) {
1929 .type = INSTRUCTION_CACHE,
1930 .level = 1,
1931 .size = 32 * KiB,
1932 .line_size = 64,
1933 .associativity = 8,
1934 .partitions = 1,
1935 .sets = 64,
1936 .lines_per_tag = 1,
1937 .self_init = 1,
1938 .no_invd_sharing = true,
1939 },
1940 .l2_cache = &(CPUCacheInfo) {
1941 .type = UNIFIED_CACHE,
1942 .level = 2,
1943 .size = 512 * KiB,
1944 .line_size = 64,
1945 .associativity = 8,
1946 .partitions = 1,
1947 .sets = 1024,
1948 .lines_per_tag = 1,
1949 },
1950 .l3_cache = &(CPUCacheInfo) {
1951 .type = UNIFIED_CACHE,
1952 .level = 3,
1953 .size = 16 * MiB,
1954 .line_size = 64,
1955 .associativity = 16,
1956 .partitions = 1,
1957 .sets = 16384,
1958 .lines_per_tag = 1,
1959 .self_init = true,
1960 .inclusive = true,
1961 .complex_indexing = true,
1962 },
1963};
1964
d7c72735
MR		 1965static const CPUCaches epyc_rome_v3_cache_info = {
1966 .l1d_cache = &(CPUCacheInfo) {
1967 .type = DATA_CACHE,
1968 .level = 1,
1969 .size = 32 * KiB,
1970 .line_size = 64,
1971 .associativity = 8,
1972 .partitions = 1,
1973 .sets = 64,
1974 .lines_per_tag = 1,
1975 .self_init = 1,
1976 .no_invd_sharing = true,
1977 },
1978 .l1i_cache = &(CPUCacheInfo) {
1979 .type = INSTRUCTION_CACHE,
1980 .level = 1,
1981 .size = 32 * KiB,
1982 .line_size = 64,
1983 .associativity = 8,
1984 .partitions = 1,
1985 .sets = 64,
1986 .lines_per_tag = 1,
1987 .self_init = 1,
1988 .no_invd_sharing = true,
1989 },
1990 .l2_cache = &(CPUCacheInfo) {
1991 .type = UNIFIED_CACHE,
1992 .level = 2,
1993 .size = 512 * KiB,
1994 .line_size = 64,
1995 .associativity = 8,
1996 .partitions = 1,
1997 .sets = 1024,
1998 .lines_per_tag = 1,
1999 },
2000 .l3_cache = &(CPUCacheInfo) {
2001 .type = UNIFIED_CACHE,
2002 .level = 3,
2003 .size = 16 * MiB,
2004 .line_size = 64,
2005 .associativity = 16,
2006 .partitions = 1,
2007 .sets = 16384,
2008 .lines_per_tag = 1,
2009 .self_init = true,
2010 .inclusive = true,
2011 .complex_indexing = false,
2012 },
2013};
2014
e845de38 2015static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 2016 .l1d_cache = &(CPUCacheInfo) {
2017 .type = DATA_CACHE,
2018 .level = 1,
2019 .size = 32 * KiB,
2020 .line_size = 64,
2021 .associativity = 8,
2022 .partitions = 1,
2023 .sets = 64,
2024 .lines_per_tag = 1,
2025 .self_init = 1,
2026 .no_invd_sharing = true,
2027 },
2028 .l1i_cache = &(CPUCacheInfo) {
2029 .type = INSTRUCTION_CACHE,
2030 .level = 1,
2031 .size = 32 * KiB,
2032 .line_size = 64,
2033 .associativity = 8,
2034 .partitions = 1,
2035 .sets = 64,
2036 .lines_per_tag = 1,
2037 .self_init = 1,
2038 .no_invd_sharing = true,
2039 },
2040 .l2_cache = &(CPUCacheInfo) {
2041 .type = UNIFIED_CACHE,
2042 .level = 2,
2043 .size = 512 * KiB,
2044 .line_size = 64,
2045 .associativity = 8,
2046 .partitions = 1,
2047 .sets = 1024,
2048 .lines_per_tag = 1,
2049 },
2050 .l3_cache = &(CPUCacheInfo) {
2051 .type = UNIFIED_CACHE,
2052 .level = 3,
2053 .size = 32 * MiB,
2054 .line_size = 64,
2055 .associativity = 16,
2056 .partitions = 1,
2057 .sets = 32768,
2058 .lines_per_tag = 1,
2059 .self_init = true,
2060 .inclusive = true,
2061 .complex_indexing = true,
2062 },
2063};
2064
27f03be6
BM		 2065static const CPUCaches epyc_milan_v2_cache_info = {
2066 .l1d_cache = &(CPUCacheInfo) {
2067 .type = DATA_CACHE,
2068 .level = 1,
2069 .size = 32 * KiB,
2070 .line_size = 64,
2071 .associativity = 8,
2072 .partitions = 1,
2073 .sets = 64,
2074 .lines_per_tag = 1,
2075 .self_init = 1,
2076 .no_invd_sharing = true,
2077 },
2078 .l1i_cache = &(CPUCacheInfo) {
2079 .type = INSTRUCTION_CACHE,
2080 .level = 1,
2081 .size = 32 * KiB,
2082 .line_size = 64,
2083 .associativity = 8,
2084 .partitions = 1,
2085 .sets = 64,
2086 .lines_per_tag = 1,
2087 .self_init = 1,
2088 .no_invd_sharing = true,
2089 },
2090 .l2_cache = &(CPUCacheInfo) {
2091 .type = UNIFIED_CACHE,
2092 .level = 2,
2093 .size = 512 * KiB,
2094 .line_size = 64,
2095 .associativity = 8,
2096 .partitions = 1,
2097 .sets = 1024,
2098 .lines_per_tag = 1,
2099 },
2100 .l3_cache = &(CPUCacheInfo) {
2101 .type = UNIFIED_CACHE,
2102 .level = 3,
2103 .size = 32 * MiB,
2104 .line_size = 64,
2105 .associativity = 16,
2106 .partitions = 1,
2107 .sets = 32768,
2108 .lines_per_tag = 1,
2109 .self_init = true,
2110 .inclusive = true,
2111 .complex_indexing = false,
2112 },
2113};
2114
166b1741
BM		 2115static const CPUCaches epyc_genoa_cache_info = {
2116 .l1d_cache = &(CPUCacheInfo) {
2117 .type = DATA_CACHE,
2118 .level = 1,
2119 .size = 32 * KiB,
2120 .line_size = 64,
2121 .associativity = 8,
2122 .partitions = 1,
2123 .sets = 64,
2124 .lines_per_tag = 1,
2125 .self_init = 1,
2126 .no_invd_sharing = true,
2127 },
2128 .l1i_cache = &(CPUCacheInfo) {
2129 .type = INSTRUCTION_CACHE,
2130 .level = 1,
2131 .size = 32 * KiB,
2132 .line_size = 64,
2133 .associativity = 8,
2134 .partitions = 1,
2135 .sets = 64,
2136 .lines_per_tag = 1,
2137 .self_init = 1,
2138 .no_invd_sharing = true,
2139 },
2140 .l2_cache = &(CPUCacheInfo) {
2141 .type = UNIFIED_CACHE,
2142 .level = 2,
2143 .size = 1 * MiB,
2144 .line_size = 64,
2145 .associativity = 8,
2146 .partitions = 1,
2147 .sets = 2048,
2148 .lines_per_tag = 1,
2149 },
2150 .l3_cache = &(CPUCacheInfo) {
2151 .type = UNIFIED_CACHE,
2152 .level = 3,
2153 .size = 32 * MiB,
2154 .line_size = 64,
2155 .associativity = 16,
2156 .partitions = 1,
2157 .sets = 32768,
2158 .lines_per_tag = 1,
2159 .self_init = true,
2160 .inclusive = true,
2161 .complex_indexing = false,
2162 },
2163};
2164
0723cc8a
PB		 2165/* The following VMX features are not supported by KVM and are left out in the
2166 * CPU definitions:
2167 *
2168 * Dual-monitor support (all processors)
2169 * Entry to SMM
2170 * Deactivate dual-monitor treatment
2171 * Number of CR3-target values
2172 * Shutdown activity state
2173 * Wait-for-SIPI activity state
2174 * PAUSE-loop exiting (Westmere and newer)
2175 * EPT-violation #VE (Broadwell and newer)
2176 * Inject event with insn length=0 (Skylake and newer)
2177 * Conceal non-root operation from PT
2178 * Conceal VM exits from PT
2179 * Conceal VM entries from PT
2180 * Enable ENCLS exiting
2181 * Mode-based execute control (XS/XU)
f70c1c06 2182 * TSC scaling (Skylake Server and newer)
0723cc8a
PB		 2183 * GPA translation for PT (IceLake and newer)
2184 * User wait and pause
2185 * ENCLV exiting
2186 * Load IA32_RTIT_CTL
2187 * Clear IA32_RTIT_CTL
2188 * Advanced VM-exit information for EPT violations
2189 * Sub-page write permissions
2190 * PT in VMX operation
2191 */
2192
e11fd689 2193static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 2194 {
2195 .name = "qemu64",
3046bb5d 2196 .level = 0xd,
99b88a17 2197 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 2198 .family = 15,
2199 .model = 107,
2200 .stepping = 1,
0514ef2f 2201 .features[FEAT_1_EDX] =
27861ecc 2202 PPRO_FEATURES |
c6dc6f63 2203 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 2204 CPUID_PSE36,
0514ef2f 2205 .features[FEAT_1_ECX] =
6aa91e4a 2206 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 2207 .features[FEAT_8000_0001_EDX] =
c6dc6f63 2208 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2209 .features[FEAT_8000_0001_ECX] =
71195672 2210 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 2211 .xlevel = 0x8000000A,
9cf2cc3d 2212 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2213 },
2214 {
2215 .name = "phenom",
2216 .level = 5,
99b88a17 2217 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2218 .family = 16,
2219 .model = 2,
2220 .stepping = 3,
b9fc20bc 2221 /* Missing: CPUID_HT */
0514ef2f 2222 .features[FEAT_1_EDX] =
27861ecc 2223 PPRO_FEATURES |
c6dc6f63 2224 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 2225 CPUID_PSE36 | CPUID_VME,
0514ef2f 2226 .features[FEAT_1_ECX] =
27861ecc 2227 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 2228 CPUID_EXT_POPCNT,
0514ef2f 2229 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2230 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
2231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 2232 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 2233 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2234 CPUID_EXT3_CR8LEG,
2235 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2236 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 2237 .features[FEAT_8000_0001_ECX] =
27861ecc 2238 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 2239 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 2240 /* Missing: CPUID_SVM_LBRV */
0514ef2f 2241 .features[FEAT_SVM] =
b9fc20bc 2242 CPUID_SVM_NPT,
c6dc6f63
AP		 2243 .xlevel = 0x8000001A,
2244 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
2245 },
2246 {
2247 .name = "core2duo",
2248 .level = 10,
99b88a17 2249 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2250 .family = 6,
2251 .model = 15,
2252 .stepping = 11,
b9fc20bc 2253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2254 .features[FEAT_1_EDX] =
27861ecc 2255 PPRO_FEATURES |
c6dc6f63 2256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 2257 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
2258 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 2259 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2260 .features[FEAT_1_ECX] =
27861ecc 2261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 2262 CPUID_EXT_CX16,
0514ef2f 2263 .features[FEAT_8000_0001_EDX] =
27861ecc 2264 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2265 .features[FEAT_8000_0001_ECX] =
27861ecc 2266 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2269 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2271 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2272 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2273 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2274 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2275 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2276 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2277 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2278 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2279 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2280 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2281 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2282 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2283 .features[FEAT_VMX_SECONDARY_CTLS] =
2284 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 2285 .xlevel = 0x80000008,
2286 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
2287 },
2288 {
2289 .name = "kvm64",
3046bb5d 2290 .level = 0xd,
99b88a17 2291 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2292 .family = 15,
2293 .model = 6,
2294 .stepping = 1,
b3a4f0b1 2295 /* Missing: CPUID_HT */
0514ef2f 2296 .features[FEAT_1_EDX] =
b3a4f0b1 2297 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 2298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
2299 CPUID_PSE36,
2300 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 2301 .features[FEAT_1_ECX] =
27861ecc 2302 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 2303 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 2304 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2306 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2307 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2308 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2309 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 2310 .features[FEAT_8000_0001_ECX] =
27861ecc 2311 0,
0723cc8a
PB		 2312 /* VMX features from Cedar Mill/Prescott */
2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2314 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2315 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2316 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2317 VMX_PIN_BASED_NMI_EXITING,
2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 2326 .xlevel = 0x80000008,
2327 .model_id = "Common KVM processor"
2328 },
c6dc6f63
AP		 2329 {
2330 .name = "qemu32",
2331 .level = 4,
99b88a17 2332 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2333 .family = 6,
f8e6a11a 2334 .model = 6,
c6dc6f63 2335 .stepping = 3,
0514ef2f 2336 .features[FEAT_1_EDX] =
27861ecc 2337 PPRO_FEATURES,
0514ef2f 2338 .features[FEAT_1_ECX] =
6aa91e4a 2339 CPUID_EXT_SSE3,
58012d66 2340 .xlevel = 0x80000004,
9cf2cc3d 2341 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 2342 },
eafaf1e5
AP		 2343 {
2344 .name = "kvm32",
2345 .level = 5,
99b88a17 2346 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 2347 .family = 15,
2348 .model = 6,
2349 .stepping = 1,
0514ef2f 2350 .features[FEAT_1_EDX] =
b3a4f0b1 2351 PPRO_FEATURES | CPUID_VME |
eafaf1e5 2352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 2353 .features[FEAT_1_ECX] =
27861ecc 2354 CPUID_EXT_SSE3,
0514ef2f 2355 .features[FEAT_8000_0001_ECX] =
27861ecc 2356 0,
0723cc8a
PB		 2357 /* VMX features from Yonah */
2358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2359 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2360 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2361 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2362 VMX_PIN_BASED_NMI_EXITING,
2363 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2364 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2365 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2366 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2367 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2368 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2369 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 2370 .xlevel = 0x80000008,
2371 .model_id = "Common 32-bit KVM processor"
2372 },
c6dc6f63
AP		 2373 {
2374 .name = "coreduo",
2375 .level = 10,
99b88a17 2376 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2377 .family = 6,
2378 .model = 14,
2379 .stepping = 8,
b9fc20bc 2380 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2381 .features[FEAT_1_EDX] =
27861ecc 2382 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 2383 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2384 CPUID_SS,
2385 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 2386 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2387 .features[FEAT_1_ECX] =
e93abc14 2388 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 2389 .features[FEAT_8000_0001_EDX] =
27861ecc 2390 CPUID_EXT2_NX,
0723cc8a
PB		 2391 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2392 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2393 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2394 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2395 VMX_PIN_BASED_NMI_EXITING,
2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2402 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2403 .xlevel = 0x80000008,
2404 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2405 },
2406 {
2407 .name = "486",
58012d66 2408 .level = 1,
99b88a17 2409 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2410 .family = 4,
b2a856d9 2411 .model = 8,
c6dc6f63 2412 .stepping = 0,
0514ef2f 2413 .features[FEAT_1_EDX] =
27861ecc 2414 I486_FEATURES,
c6dc6f63 2415 .xlevel = 0,
807e9869 2416 .model_id = "",
c6dc6f63
AP		 2417 },
2418 {
2419 .name = "pentium",
2420 .level = 1,
99b88a17 2421 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2422 .family = 5,
2423 .model = 4,
2424 .stepping = 3,
0514ef2f 2425 .features[FEAT_1_EDX] =
27861ecc 2426 PENTIUM_FEATURES,
c6dc6f63 2427 .xlevel = 0,
807e9869 2428 .model_id = "",
c6dc6f63
AP		 2429 },
2430 {
2431 .name = "pentium2",
2432 .level = 2,
99b88a17 2433 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2434 .family = 6,
2435 .model = 5,
2436 .stepping = 2,
0514ef2f 2437 .features[FEAT_1_EDX] =
27861ecc 2438 PENTIUM2_FEATURES,
c6dc6f63 2439 .xlevel = 0,
807e9869 2440 .model_id = "",
c6dc6f63
AP		 2441 },
2442 {
2443 .name = "pentium3",
3046bb5d 2444 .level = 3,
99b88a17 2445 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2446 .family = 6,
2447 .model = 7,
2448 .stepping = 3,
0514ef2f 2449 .features[FEAT_1_EDX] =
27861ecc 2450 PENTIUM3_FEATURES,
c6dc6f63 2451 .xlevel = 0,
807e9869 2452 .model_id = "",
c6dc6f63
AP		 2453 },
2454 {
2455 .name = "athlon",
2456 .level = 2,
99b88a17 2457 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2458 .family = 6,
2459 .model = 2,
2460 .stepping = 3,
0514ef2f 2461 .features[FEAT_1_EDX] =
27861ecc 2462 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2463 CPUID_MCA,
0514ef2f 2464 .features[FEAT_8000_0001_EDX] =
60032ac0 2465 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2466 .xlevel = 0x80000008,
9cf2cc3d 2467 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2468 },
2469 {
2470 .name = "n270",
3046bb5d 2471 .level = 10,
99b88a17 2472 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2473 .family = 6,
2474 .model = 28,
2475 .stepping = 2,
b9fc20bc 2476 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2477 .features[FEAT_1_EDX] =
27861ecc 2478 PPRO_FEATURES |
b9fc20bc
EH		 2479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2480 CPUID_ACPI | CPUID_SS,
c6dc6f63 2481 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2482 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2483 * CPUID_EXT_XTPR */
0514ef2f 2484 .features[FEAT_1_ECX] =
27861ecc 2485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2486 CPUID_EXT_MOVBE,
0514ef2f 2487 .features[FEAT_8000_0001_EDX] =
60032ac0 2488 CPUID_EXT2_NX,
0514ef2f 2489 .features[FEAT_8000_0001_ECX] =
27861ecc 2490 CPUID_EXT3_LAHF_LM,
3046bb5d 2491 .xlevel = 0x80000008,
c6dc6f63
AP		 2492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2493 },
3eca4642
EH		 2494 {
2495 .name = "Conroe",
3046bb5d 2496 .level = 10,
99b88a17 2497 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2498 .family = 6,
ffce9ebb 2499 .model = 15,
3eca4642 2500 .stepping = 3,
0514ef2f 2501 .features[FEAT_1_EDX] =
b3a4f0b1 2502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2506 CPUID_DE | CPUID_FP87,
0514ef2f 2507 .features[FEAT_1_ECX] =
27861ecc 2508 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2509 .features[FEAT_8000_0001_EDX] =
27861ecc 2510 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2511 .features[FEAT_8000_0001_ECX] =
27861ecc 2512 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2513 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2514 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2515 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2529 .features[FEAT_VMX_SECONDARY_CTLS] =
2530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2531 .xlevel = 0x80000008,
3eca4642
EH		 2532 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2533 },
2534 {
2535 .name = "Penryn",
3046bb5d 2536 .level = 10,
99b88a17 2537 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2538 .family = 6,
ffce9ebb 2539 .model = 23,
3eca4642 2540 .stepping = 3,
0514ef2f 2541 .features[FEAT_1_EDX] =
b3a4f0b1 2542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2546 CPUID_DE | CPUID_FP87,
0514ef2f 2547 .features[FEAT_1_ECX] =
27861ecc 2548 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2549 CPUID_EXT_SSE3,
0514ef2f 2550 .features[FEAT_8000_0001_EDX] =
27861ecc 2551 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2552 .features[FEAT_8000_0001_ECX] =
27861ecc 2553 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2555 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2556 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2572 .features[FEAT_VMX_SECONDARY_CTLS] =
2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2574 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2575 .xlevel = 0x80000008,
3eca4642
EH		 2576 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2577 },
2578 {
2579 .name = "Nehalem",
3046bb5d 2580 .level = 11,
99b88a17 2581 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2582 .family = 6,
ffce9ebb 2583 .model = 26,
3eca4642 2584 .stepping = 3,
0514ef2f 2585 .features[FEAT_1_EDX] =
b3a4f0b1 2586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2590 CPUID_DE | CPUID_FP87,
0514ef2f 2591 .features[FEAT_1_ECX] =
27861ecc 2592 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2594 .features[FEAT_8000_0001_EDX] =
27861ecc 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2596 .features[FEAT_8000_0001_ECX] =
27861ecc 2597 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2599 MSR_VMX_BASIC_TRUE_CTLS,
2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2610 .features[FEAT_VMX_EXIT_CTLS] =
2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2617 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2618 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2619 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2620 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2621 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2622 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2623 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2624 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2625 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2626 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2627 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2628 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2629 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2630 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2631 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2632 .features[FEAT_VMX_SECONDARY_CTLS] =
2633 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2634 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2635 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2636 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2637 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2638 .xlevel = 0x80000008,
3eca4642 2639 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2640 .versions = (X86CPUVersionDefinition[]) {
2641 { .version = 1 },
2642 {
2643 .version = 2,
53db89d9 2644 .alias = "Nehalem-IBRS",
d86a7088
EH		 2645 .props = (PropValue[]) {
2646 { "spec-ctrl", "on" },
2647 { "model-id",
2648 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2649 { /* end of list */ }
2650 }
2651 },
2652 { /* end of list */ }
2653 }
3eca4642
EH		 2654 },
2655 {
2656 .name = "Westmere",
2657 .level = 11,
99b88a17 2658 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2659 .family = 6,
2660 .model = 44,
2661 .stepping = 1,
0514ef2f 2662 .features[FEAT_1_EDX] =
b3a4f0b1 2663 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2664 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2665 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2666 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2667 CPUID_DE | CPUID_FP87,
0514ef2f 2668 .features[FEAT_1_ECX] =
27861ecc 2669 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2670 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2671 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2672 .features[FEAT_8000_0001_EDX] =
27861ecc 2673 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2674 .features[FEAT_8000_0001_ECX] =
27861ecc 2675 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2676 .features[FEAT_6_EAX] =
2677 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2678 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2679 MSR_VMX_BASIC_TRUE_CTLS,
2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2682 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2683 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2684 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2685 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2686 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2687 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2690 .features[FEAT_VMX_EXIT_CTLS] =
2691 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2692 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2693 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2694 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2695 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2696 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2697 MSR_VMX_MISC_STORE_LMA,
2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2699 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2700 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2701 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2705 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2706 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2707 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2708 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2709 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2711 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2713 .features[FEAT_VMX_SECONDARY_CTLS] =
2714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2715 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2716 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2719 .xlevel = 0x80000008,
3eca4642 2720 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2721 .versions = (X86CPUVersionDefinition[]) {
2722 { .version = 1 },
2723 {
2724 .version = 2,
53db89d9 2725 .alias = "Westmere-IBRS",
d86a7088
EH		 2726 .props = (PropValue[]) {
2727 { "spec-ctrl", "on" },
2728 { "model-id",
2729 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2730 { /* end of list */ }
2731 }
2732 },
2733 { /* end of list */ }
2734 }
3eca4642
EH		 2735 },
2736 {
2737 .name = "SandyBridge",
2738 .level = 0xd,
99b88a17 2739 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2740 .family = 6,
2741 .model = 42,
2742 .stepping = 1,
0514ef2f 2743 .features[FEAT_1_EDX] =
b3a4f0b1 2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2748 CPUID_DE | CPUID_FP87,
0514ef2f 2749 .features[FEAT_1_ECX] =
27861ecc 2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2751 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2752 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2753 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2754 CPUID_EXT_SSE3,
0514ef2f 2755 .features[FEAT_8000_0001_EDX] =
27861ecc 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2757 CPUID_EXT2_SYSCALL,
0514ef2f 2758 .features[FEAT_8000_0001_ECX] =
27861ecc 2759 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2760 .features[FEAT_XSAVE] =
2761 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2762 .features[FEAT_6_EAX] =
2763 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2764 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2765 MSR_VMX_BASIC_TRUE_CTLS,
2766 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2769 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2771 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2773 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2776 .features[FEAT_VMX_EXIT_CTLS] =
2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2779 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2780 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2782 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2783 MSR_VMX_MISC_STORE_LMA,
2784 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2785 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2787 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2788 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2789 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2790 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2791 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2792 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2793 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2794 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2796 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2799 .features[FEAT_VMX_SECONDARY_CTLS] =
2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2801 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2802 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2804 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2805 .xlevel = 0x80000008,
3eca4642 2806 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2807 .versions = (X86CPUVersionDefinition[]) {
2808 { .version = 1 },
2809 {
2810 .version = 2,
53db89d9 2811 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2812 .props = (PropValue[]) {
2813 { "spec-ctrl", "on" },
2814 { "model-id",
2815 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2816 { /* end of list */ }
2817 }
2818 },
2819 { /* end of list */ }
2820 }
3eca4642 2821 },
2f9ac42a
PB		 2822 {
2823 .name = "IvyBridge",
2824 .level = 0xd,
2825 .vendor = CPUID_VENDOR_INTEL,
2826 .family = 6,
2827 .model = 58,
2828 .stepping = 9,
2829 .features[FEAT_1_EDX] =
2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2834 CPUID_DE | CPUID_FP87,
2835 .features[FEAT_1_ECX] =
2836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2838 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2839 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2840 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2841 .features[FEAT_7_0_EBX] =
2842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2843 CPUID_7_0_EBX_ERMS,
2844 .features[FEAT_8000_0001_EDX] =
2845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2846 CPUID_EXT2_SYSCALL,
2847 .features[FEAT_8000_0001_ECX] =
2848 CPUID_EXT3_LAHF_LM,
2849 .features[FEAT_XSAVE] =
2850 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2851 .features[FEAT_6_EAX] =
2852 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2853 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2854 MSR_VMX_BASIC_TRUE_CTLS,
2855 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2856 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2857 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2858 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2859 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2860 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2861 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2862 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2863 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2865 .features[FEAT_VMX_EXIT_CTLS] =
2866 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2867 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2868 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2869 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2870 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2872 MSR_VMX_MISC_STORE_LMA,
2873 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2874 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2875 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2885 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2886 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2887 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2888 .features[FEAT_VMX_SECONDARY_CTLS] =
2889 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2890 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2891 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2892 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2893 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2894 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2895 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2896 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2897 .xlevel = 0x80000008,
2f9ac42a 2898 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2899 .versions = (X86CPUVersionDefinition[]) {
2900 { .version = 1 },
2901 {
2902 .version = 2,
53db89d9 2903 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2904 .props = (PropValue[]) {
2905 { "spec-ctrl", "on" },
2906 { "model-id",
2907 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2908 { /* end of list */ }
2909 }
2910 },
2911 { /* end of list */ }
2912 }
2f9ac42a 2913 },
ac96c413 2914 {
37507094
EH		 2915 .name = "Haswell",
2916 .level = 0xd,
99b88a17 2917 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2918 .family = 6,
2919 .model = 60,
ec56a4a7 2920 .stepping = 4,
0514ef2f 2921 .features[FEAT_1_EDX] =
b3a4f0b1 2922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2926 CPUID_DE | CPUID_FP87,
0514ef2f 2927 .features[FEAT_1_ECX] =
27861ecc 2928 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2929 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2932 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2933 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2934 .features[FEAT_8000_0001_EDX] =
27861ecc 2935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2936 CPUID_EXT2_SYSCALL,
0514ef2f 2937 .features[FEAT_8000_0001_ECX] =
becb6667 2938 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2939 .features[FEAT_7_0_EBX] =
27861ecc 2940 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2941 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2942 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2943 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2944 .features[FEAT_XSAVE] =
2945 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2946 .features[FEAT_6_EAX] =
2947 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2948 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2949 MSR_VMX_BASIC_TRUE_CTLS,
2950 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2952 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2953 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2954 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2955 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2956 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2957 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2960 .features[FEAT_VMX_EXIT_CTLS] =
2961 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2962 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2963 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2964 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2965 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2967 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2969 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2970 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2975 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2976 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2977 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2978 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2979 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2981 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2982 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2983 .features[FEAT_VMX_SECONDARY_CTLS] =
2984 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2985 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2986 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2987 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2988 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2989 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2990 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2991 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2992 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2993 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2994 .xlevel = 0x80000008,
37507094 2995 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2996 .versions = (X86CPUVersionDefinition[]) {
2997 { .version = 1 },
2998 {
2999 .version = 2,
53db89d9 3000 .alias = "Haswell-noTSX",
d86a7088
EH		 3001 .props = (PropValue[]) {
3002 { "hle", "off" },
3003 { "rtm", "off" },
3004 { "stepping", "1" },
3005 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
3006 { /* end of list */ }
3007 },
3008 },
3009 {
3010 .version = 3,
53db89d9 3011 .alias = "Haswell-IBRS",
d86a7088
EH		 3012 .props = (PropValue[]) {
3013 /* Restore TSX features removed by -v2 above */
3014 { "hle", "on" },
3015 { "rtm", "on" },
3016 /*
3017 * Haswell and Haswell-IBRS had stepping=4 in
3018 * QEMU 4.0 and older
3019 */
3020 { "stepping", "4" },
3021 { "spec-ctrl", "on" },
3022 { "model-id",
3023 "Intel Core Processor (Haswell, IBRS)" },
3024 { /* end of list */ }
3025 }
3026 },
3027 {
3028 .version = 4,
53db89d9 3029 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 3030 .props = (PropValue[]) {
3031 { "hle", "off" },
3032 { "rtm", "off" },
3033 /* spec-ctrl was already enabled by -v3 above */
3034 { "stepping", "1" },
3035 { "model-id",
3036 "Intel Core Processor (Haswell, no TSX, IBRS)" },
3037 { /* end of list */ }
3038 }
3039 },
3040 { /* end of list */ }
3041 }
37507094 3042 },
ece01354
EH		 3043 {
3044 .name = "Broadwell",
3045 .level = 0xd,
3046 .vendor = CPUID_VENDOR_INTEL,
3047 .family = 6,
3048 .model = 61,
3049 .stepping = 2,
3050 .features[FEAT_1_EDX] =
b3a4f0b1 3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3055 CPUID_DE | CPUID_FP87,
3056 .features[FEAT_1_ECX] =
3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 3063 .features[FEAT_8000_0001_EDX] =
3064 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3065 CPUID_EXT2_SYSCALL,
3066 .features[FEAT_8000_0001_ECX] =
becb6667 3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 3068 .features[FEAT_7_0_EBX] =
3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 3073 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 3074 .features[FEAT_XSAVE] =
3075 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 3076 .features[FEAT_6_EAX] =
3077 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3079 MSR_VMX_BASIC_TRUE_CTLS,
3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3090 .features[FEAT_VMX_EXIT_CTLS] =
3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3097 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3113 .features[FEAT_VMX_SECONDARY_CTLS] =
3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3119 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3120 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3121 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3122 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3123 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3124 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 3125 .xlevel = 0x80000008,
ece01354 3126 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 3127 .versions = (X86CPUVersionDefinition[]) {
3128 { .version = 1 },
3129 {
3130 .version = 2,
53db89d9 3131 .alias = "Broadwell-noTSX",
d86a7088
EH		 3132 .props = (PropValue[]) {
3133 { "hle", "off" },
3134 { "rtm", "off" },
3135 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3136 { /* end of list */ }
3137 },
3138 },
3139 {
3140 .version = 3,
53db89d9 3141 .alias = "Broadwell-IBRS",
d86a7088
EH		 3142 .props = (PropValue[]) {
3143 /* Restore TSX features removed by -v2 above */
3144 { "hle", "on" },
3145 { "rtm", "on" },
3146 { "spec-ctrl", "on" },
3147 { "model-id",
3148 "Intel Core Processor (Broadwell, IBRS)" },
3149 { /* end of list */ }
3150 }
3151 },
3152 {
3153 .version = 4,
53db89d9 3154 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 3155 .props = (PropValue[]) {
3156 { "hle", "off" },
3157 { "rtm", "off" },
3158 /* spec-ctrl was already enabled by -v3 above */
3159 { "model-id",
3160 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
3161 { /* end of list */ }
3162 }
3163 },
3164 { /* end of list */ }
3165 }
ece01354 3166 },
f6f949e9
EH		 3167 {
3168 .name = "Skylake-Client",
3169 .level = 0xd,
3170 .vendor = CPUID_VENDOR_INTEL,
3171 .family = 6,
3172 .model = 94,
3173 .stepping = 3,
3174 .features[FEAT_1_EDX] =
3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3179 CPUID_DE | CPUID_FP87,
3180 .features[FEAT_1_ECX] =
3181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3187 .features[FEAT_8000_0001_EDX] =
3188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3189 CPUID_EXT2_SYSCALL,
3190 .features[FEAT_8000_0001_ECX] =
3191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3192 .features[FEAT_7_0_EBX] =
3193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3196 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3197 CPUID_7_0_EBX_SMAP,
7bde6b18 3198 /* XSAVES is added in version 4 */
f6f949e9
EH		 3199 .features[FEAT_XSAVE] =
3200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3201 CPUID_XSAVE_XGETBV1,
3202 .features[FEAT_6_EAX] =
3203 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3204 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3206 MSR_VMX_BASIC_TRUE_CTLS,
3207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3217 .features[FEAT_VMX_EXIT_CTLS] =
3218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3224 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3238 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3240 .features[FEAT_VMX_SECONDARY_CTLS] =
3241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3244 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3245 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3248 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 3249 .xlevel = 0x80000008,
3250 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 3251 .versions = (X86CPUVersionDefinition[]) {
3252 { .version = 1 },
3253 {
3254 .version = 2,
53db89d9 3255 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 3256 .props = (PropValue[]) {
3257 { "spec-ctrl", "on" },
3258 { "model-id",
3259 "Intel Core Processor (Skylake, IBRS)" },
3260 { /* end of list */ }
3261 }
3262 },
9ab2237f
EH		 3263 {
3264 .version = 3,
02fa60d1 3265 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 3266 .props = (PropValue[]) {
3267 { "hle", "off" },
3268 { "rtm", "off" },
673b0add
KC		 3269 { "model-id",
3270 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3271 { /* end of list */ }
3272 }
3273 },
7bde6b18
VK		 3274 {
3275 .version = 4,
3276 .note = "IBRS, XSAVES, no TSX",
3277 .props = (PropValue[]) {
3278 { "xsaves", "on" },
3279 { "vmx-xsaves", "on" },
3280 { /* end of list */ }
3281 }
3282 },
d86a7088
EH		 3283 { /* end of list */ }
3284 }
f6f949e9 3285 },
53f9a6f4
BF		 3286 {
3287 .name = "Skylake-Server",
3288 .level = 0xd,
3289 .vendor = CPUID_VENDOR_INTEL,
3290 .family = 6,
3291 .model = 85,
3292 .stepping = 4,
3293 .features[FEAT_1_EDX] =
3294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3298 CPUID_DE | CPUID_FP87,
3299 .features[FEAT_1_ECX] =
3300 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3301 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3302 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3303 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3304 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3305 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3306 .features[FEAT_8000_0001_EDX] =
3307 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3308 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3309 .features[FEAT_8000_0001_ECX] =
3310 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3311 .features[FEAT_7_0_EBX] =
3312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3313 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3314 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3315 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3316 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 3317 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 3319 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 3320 .features[FEAT_7_0_ECX] =
3321 CPUID_7_0_ECX_PKU,
7bde6b18 3322 /* XSAVES is added in version 5 */
53f9a6f4
BF		 3323 .features[FEAT_XSAVE] =
3324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3325 CPUID_XSAVE_XGETBV1,
3326 .features[FEAT_6_EAX] =
3327 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3330 MSR_VMX_BASIC_TRUE_CTLS,
3331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3341 .features[FEAT_VMX_EXIT_CTLS] =
3342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3362 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3364 .features[FEAT_VMX_SECONDARY_CTLS] =
3365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3374 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 3375 .xlevel = 0x80000008,
3376 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 3377 .versions = (X86CPUVersionDefinition[]) {
3378 { .version = 1 },
3379 {
3380 .version = 2,
53db89d9 3381 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 3382 .props = (PropValue[]) {
3383 /* clflushopt was not added to Skylake-Server-IBRS */
3384 /* TODO: add -v3 including clflushopt */
3385 { "clflushopt", "off" },
3386 { "spec-ctrl", "on" },
3387 { "model-id",
3388 "Intel Xeon Processor (Skylake, IBRS)" },
3389 { /* end of list */ }
3390 }
3391 },
9ab2237f
EH		 3392 {
3393 .version = 3,
02fa60d1 3394 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3395 .props = (PropValue[]) {
3396 { "hle", "off" },
3397 { "rtm", "off" },
673b0add
KC		 3398 { "model-id",
3399 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3400 { /* end of list */ }
3401 }
3402 },
644e3c5d
CQ		 3403 {
3404 .version = 4,
3405 .props = (PropValue[]) {
3406 { "vmx-eptp-switching", "on" },
3407 { /* end of list */ }
3408 }
3409 },
7bde6b18
VK		 3410 {
3411 .version = 5,
3412 .note = "IBRS, XSAVES, EPT switching, no TSX",
3413 .props = (PropValue[]) {
3414 { "xsaves", "on" },
3415 { "vmx-xsaves", "on" },
3416 { /* end of list */ }
3417 }
3418 },
d86a7088
EH		 3419 { /* end of list */ }
3420 }
53f9a6f4 3421 },
c7a88b52
TX		 3422 {
3423 .name = "Cascadelake-Server",
3424 .level = 0xd,
3425 .vendor = CPUID_VENDOR_INTEL,
3426 .family = 6,
3427 .model = 85,
b0a19803 3428 .stepping = 6,
c7a88b52
TX		 3429 .features[FEAT_1_EDX] =
3430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3434 CPUID_DE | CPUID_FP87,
3435 .features[FEAT_1_ECX] =
3436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3442 .features[FEAT_8000_0001_EDX] =
3443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3445 .features[FEAT_8000_0001_ECX] =
3446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3447 .features[FEAT_7_0_EBX] =
3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3456 .features[FEAT_7_0_ECX] =
bb4928c7 3457 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3458 CPUID_7_0_ECX_AVX512VNNI,
3459 .features[FEAT_7_0_EDX] =
3460 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3461 /* XSAVES is added in version 5 */
c7a88b52
TX		 3462 .features[FEAT_XSAVE] =
3463 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3464 CPUID_XSAVE_XGETBV1,
3465 .features[FEAT_6_EAX] =
3466 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3467 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3469 MSR_VMX_BASIC_TRUE_CTLS,
3470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3480 .features[FEAT_VMX_EXIT_CTLS] =
3481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3501 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3503 .features[FEAT_VMX_SECONDARY_CTLS] =
3504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3513 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3514 .xlevel = 0x80000008,
3515 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3516 .versions = (X86CPUVersionDefinition[]) {
3517 { .version = 1 },
3518 { .version = 2,
47f0d11d 3519 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3520 .props = (PropValue[]) {
3521 { "arch-capabilities", "on" },
3522 { "rdctl-no", "on" },
3523 { "ibrs-all", "on" },
3524 { "skip-l1dfl-vmentry", "on" },
3525 { "mds-no", "on" },
3526 { /* end of list */ }
3527 },
3528 },
9ab2237f 3529 { .version = 3,
02fa60d1 3530 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3531 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3532 .props = (PropValue[]) {
3533 { "hle", "off" },
3534 { "rtm", "off" },
3535 { /* end of list */ }
3536 },
3537 },
644e3c5d
CQ		 3538 { .version = 4,
3539 .note = "ARCH_CAPABILITIES, no TSX",
3540 .props = (PropValue[]) {
3541 { "vmx-eptp-switching", "on" },
3542 { /* end of list */ }
3543 },
3544 },
7bde6b18
VK		 3545 { .version = 5,
3546 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3547 .props = (PropValue[]) {
3548 { "xsaves", "on" },
3549 { "vmx-xsaves", "on" },
3550 { /* end of list */ }
3551 },
3552 },
fd63c6d1
EH		 3553 { /* end of list */ }
3554 }
c7a88b52 3555 },
22a866b6
CZ		 3556 {
3557 .name = "Cooperlake",
3558 .level = 0xd,
3559 .vendor = CPUID_VENDOR_INTEL,
3560 .family = 6,
3561 .model = 85,
3562 .stepping = 10,
3563 .features[FEAT_1_EDX] =
3564 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3568 CPUID_DE | CPUID_FP87,
3569 .features[FEAT_1_ECX] =
3570 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3571 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3572 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3573 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3574 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3575 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3576 .features[FEAT_8000_0001_EDX] =
3577 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3578 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3579 .features[FEAT_8000_0001_ECX] =
3580 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3581 .features[FEAT_7_0_EBX] =
3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3590 .features[FEAT_7_0_ECX] =
3591 CPUID_7_0_ECX_PKU |
3592 CPUID_7_0_ECX_AVX512VNNI,
3593 .features[FEAT_7_0_EDX] =
3594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3595 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3596 .features[FEAT_ARCH_CAPABILITIES] =
3597 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3598 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3599 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3600 .features[FEAT_7_1_EAX] =
f429dbf8 3601 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3602 /* XSAVES is added in version 2 */
22a866b6
CZ		 3603 .features[FEAT_XSAVE] =
3604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3605 CPUID_XSAVE_XGETBV1,
3606 .features[FEAT_6_EAX] =
3607 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3608 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3610 MSR_VMX_BASIC_TRUE_CTLS,
3611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3621 .features[FEAT_VMX_EXIT_CTLS] =
3622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3642 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3644 .features[FEAT_VMX_SECONDARY_CTLS] =
3645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3656 .xlevel = 0x80000008,
3657 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3658 .versions = (X86CPUVersionDefinition[]) {
3659 { .version = 1 },
3660 { .version = 2,
3661 .note = "XSAVES",
3662 .props = (PropValue[]) {
3663 { "xsaves", "on" },
3664 { "vmx-xsaves", "on" },
3665 { /* end of list */ }
3666 },
3667 },
3668 { /* end of list */ }
3669 }
22a866b6 3670 },
8a11c62d
RH		 3671 {
3672 .name = "Icelake-Server",
3673 .level = 0xd,
3674 .vendor = CPUID_VENDOR_INTEL,
3675 .family = 6,
3676 .model = 134,
3677 .stepping = 0,
3678 .features[FEAT_1_EDX] =
3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3683 CPUID_DE | CPUID_FP87,
3684 .features[FEAT_1_ECX] =
3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3691 .features[FEAT_8000_0001_EDX] =
3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3694 .features[FEAT_8000_0001_ECX] =
3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3696 .features[FEAT_8000_0008_EBX] =
3697 CPUID_8000_0008_EBX_WBNOINVD,
3698 .features[FEAT_7_0_EBX] =
3699 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3700 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3701 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3702 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3703 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3704 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3705 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3706 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3707 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3708 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3709 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3710 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3711 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3712 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3713 .features[FEAT_7_0_EDX] =
76e5a4d5 3714 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3715 /* XSAVES is added in version 5 */
8a11c62d
RH		 3716 .features[FEAT_XSAVE] =
3717 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3718 CPUID_XSAVE_XGETBV1,
3719 .features[FEAT_6_EAX] =
3720 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3721 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3723 MSR_VMX_BASIC_TRUE_CTLS,
3724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3734 .features[FEAT_VMX_EXIT_CTLS] =
3735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3755 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3757 .features[FEAT_VMX_SECONDARY_CTLS] =
3758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3767 .xlevel = 0x80000008,
3768 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3769 .versions = (X86CPUVersionDefinition[]) {
3770 { .version = 1 },
3771 {
3772 .version = 2,
47f0d11d 3773 .note = "no TSX",
02fa60d1 3774 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3775 .props = (PropValue[]) {
3776 { "hle", "off" },
3777 { "rtm", "off" },
3778 { /* end of list */ }
3779 },
3780 },
d965dc35
XL		 3781 {
3782 .version = 3,
3783 .props = (PropValue[]) {
3784 { "arch-capabilities", "on" },
3785 { "rdctl-no", "on" },
3786 { "ibrs-all", "on" },
3787 { "skip-l1dfl-vmentry", "on" },
3788 { "mds-no", "on" },
3789 { "pschange-mc-no", "on" },
3790 { "taa-no", "on" },
3791 { /* end of list */ }
3792 },
3793 },
e0013791
CQ		 3794 {
3795 .version = 4,
3796 .props = (PropValue[]) {
3797 { "sha-ni", "on" },
3798 { "avx512ifma", "on" },
3799 { "rdpid", "on" },
3800 { "fsrm", "on" },
3801 { "vmx-rdseed-exit", "on" },
3802 { "vmx-pml", "on" },
3803 { "vmx-eptp-switching", "on" },
3804 { "model", "106" },
3805 { /* end of list */ }
3806 },
3807 },
7bde6b18
VK		 3808 {
3809 .version = 5,
3810 .note = "XSAVES",
3811 .props = (PropValue[]) {
3812 { "xsaves", "on" },
3813 { "vmx-xsaves", "on" },
3814 { /* end of list */ }
3815 },
3816 },
12cab535
VK		 3817 {
3818 .version = 6,
3819 .note = "5-level EPT",
3820 .props = (PropValue[]) {
3821 { "vmx-page-walk-5", "on" },
3822 { /* end of list */ }
3823 },
3824 },
c895fa54
ZD		 3825 {
3826 .version = 7,
3827 .note = "TSX, taa-no",
3828 .props = (PropValue[]) {
3829 /* Restore TSX features removed by -v2 above */
3830 { "hle", "on" },
3831 { "rtm", "on" },
3832 { /* end of list */ }
3833 },
3834 },
9ab2237f
EH		 3835 { /* end of list */ }
3836 }
8a11c62d 3837 },
7eb061b0
WL		 3838 {
3839 .name = "SapphireRapids",
3840 .level = 0x20,
3841 .vendor = CPUID_VENDOR_INTEL,
3842 .family = 6,
3843 .model = 143,
3844 .stepping = 4,
3845 /*
3846 * please keep the ascending order so that we can have a clear view of
3847 * bit position of each feature.
3848 */
3849 .features[FEAT_1_EDX] =
3850 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3851 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3852 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3853 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3854 CPUID_SSE | CPUID_SSE2,
3855 .features[FEAT_1_ECX] =
3856 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
3857 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
3858 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3859 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
3860 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3861 .features[FEAT_8000_0001_EDX] =
3862 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3863 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3864 .features[FEAT_8000_0001_ECX] =
3865 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
3866 .features[FEAT_8000_0008_EBX] =
3867 CPUID_8000_0008_EBX_WBNOINVD,
3868 .features[FEAT_7_0_EBX] =
3869 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
3870 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
3871 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
3872 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3873 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
3874 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
3875 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
3876 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
3877 .features[FEAT_7_0_ECX] =
3878 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3879 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3880 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3881 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3882 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
3883 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
3884 .features[FEAT_7_0_EDX] =
3885 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
3886 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
3887 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
3888 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
3889 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3890 .features[FEAT_ARCH_CAPABILITIES] =
3891 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3892 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3893 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3894 .features[FEAT_XSAVE] =
3895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3896 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
3897 .features[FEAT_6_EAX] =
3898 CPUID_6_EAX_ARAT,
3899 .features[FEAT_7_1_EAX] =
3900 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
3901 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
3902 .features[FEAT_VMX_BASIC] =
3903 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
3904 .features[FEAT_VMX_ENTRY_CTLS] =
3905 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
3906 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
3907 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
3908 .features[FEAT_VMX_EPT_VPID_CAPS] =
3909 MSR_VMX_EPT_EXECONLY |
3910 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
3911 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
3912 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
3913 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3914 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3915 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
3916 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3917 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
3918 .features[FEAT_VMX_EXIT_CTLS] =
3919 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3920 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3921 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
3922 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3923 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3924 .features[FEAT_VMX_MISC] =
3925 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
3926 MSR_VMX_MISC_VMWRITE_VMEXIT,
3927 .features[FEAT_VMX_PINBASED_CTLS] =
3928 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
3929 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
3930 VMX_PIN_BASED_POSTED_INTR,
3931 .features[FEAT_VMX_PROCBASED_CTLS] =
3932 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3936 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3937 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3938 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
3939 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
3940 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3941 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
3942 VMX_CPU_BASED_PAUSE_EXITING |
3943 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3944 .features[FEAT_VMX_SECONDARY_CTLS] =
3945 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3946 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
3947 VMX_SECONDARY_EXEC_RDTSCP |
3948 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3949 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
3950 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3951 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3952 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3953 VMX_SECONDARY_EXEC_RDRAND_EXITING |
3954 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3955 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3956 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
3957 VMX_SECONDARY_EXEC_XSAVES,
3958 .features[FEAT_VMX_VMFUNC] =
3959 MSR_VMX_VMFUNC_EPT_SWITCHING,
3960 .xlevel = 0x80000008,
3961 .model_id = "Intel Xeon Processor (SapphireRapids)",
3962 .versions = (X86CPUVersionDefinition[]) {
3963 { .version = 1 },
3baf7ae6
LW		 3964 {
3965 .version = 2,
3966 .props = (PropValue[]) {
3967 { "sbdr-ssdp-no", "on" },
3968 { "fbsdp-no", "on" },
3969 { "psdp-no", "on" },
3970 { /* end of list */ }
3971 }
3972 },
3973 { /* end of list */ }
3974 }
7eb061b0 3975 },
6d5e9694
TS		 3976 {
3977 .name = "GraniteRapids",
3978 .level = 0x20,
3979 .vendor = CPUID_VENDOR_INTEL,
3980 .family = 6,
3981 .model = 173,
3982 .stepping = 0,
3983 /*
3984 * please keep the ascending order so that we can have a clear view of
3985 * bit position of each feature.
3986 */
3987 .features[FEAT_1_EDX] =
3988 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3989 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3990 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3991 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3992 CPUID_SSE | CPUID_SSE2,
3993 .features[FEAT_1_ECX] =
3994 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
3995 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
3996 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3997 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
3998 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3999 .features[FEAT_8000_0001_EDX] =
4000 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
4001 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
4002 .features[FEAT_8000_0001_ECX] =
4003 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
4004 .features[FEAT_8000_0008_EBX] =
4005 CPUID_8000_0008_EBX_WBNOINVD,
4006 .features[FEAT_7_0_EBX] =
4007 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
4008 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
4009 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
4010 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
4011 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
4012 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
4013 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
4014 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
4015 .features[FEAT_7_0_ECX] =
4016 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
4017 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
4018 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
4019 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
4020 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
4021 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
4022 .features[FEAT_7_0_EDX] =
4023 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
4024 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
4025 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
4026 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
4027 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
4028 .features[FEAT_ARCH_CAPABILITIES] =
4029 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
4030 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
4031 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
4032 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
4033 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
4034 .features[FEAT_XSAVE] =
4035 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4036 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
4037 .features[FEAT_6_EAX] =
4038 CPUID_6_EAX_ARAT,
4039 .features[FEAT_7_1_EAX] =
4040 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
4041 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
4042 CPUID_7_1_EAX_AMX_FP16,
4043 .features[FEAT_7_1_EDX] =
4044 CPUID_7_1_EDX_PREFETCHITI,
4045 .features[FEAT_7_2_EDX] =
4046 CPUID_7_2_EDX_MCDT_NO,
4047 .features[FEAT_VMX_BASIC] =
4048 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
4049 .features[FEAT_VMX_ENTRY_CTLS] =
4050 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
4051 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
4052 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
4053 .features[FEAT_VMX_EPT_VPID_CAPS] =
4054 MSR_VMX_EPT_EXECONLY |
4055 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
4056 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
4057 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
4058 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4059 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4060 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
4061 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4063 .features[FEAT_VMX_EXIT_CTLS] =
4064 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4065 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4066 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
4067 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4068 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4069 .features[FEAT_VMX_MISC] =
4070 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
4071 MSR_VMX_MISC_VMWRITE_VMEXIT,
4072 .features[FEAT_VMX_PINBASED_CTLS] =
4073 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
4074 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
4075 VMX_PIN_BASED_POSTED_INTR,
4076 .features[FEAT_VMX_PROCBASED_CTLS] =
4077 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4078 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4079 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4080 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4081 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4082 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4083 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
4084 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
4085 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4086 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
4087 VMX_CPU_BASED_PAUSE_EXITING |
4088 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4089 .features[FEAT_VMX_SECONDARY_CTLS] =
4090 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4091 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
4092 VMX_SECONDARY_EXEC_RDTSCP |
4093 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4094 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
4095 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4096 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4097 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4098 VMX_SECONDARY_EXEC_RDRAND_EXITING |
4099 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4100 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4101 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
4102 VMX_SECONDARY_EXEC_XSAVES,
4103 .features[FEAT_VMX_VMFUNC] =
4104 MSR_VMX_VMFUNC_EPT_SWITCHING,
4105 .xlevel = 0x80000008,
4106 .model_id = "Intel Xeon Processor (GraniteRapids)",
4107 .versions = (X86CPUVersionDefinition[]) {
4108 { .version = 1 },
4109 { /* end of list */ },
4110 },
4111 },
6e82d3b6
TS		 4112 {
4113 .name = "SierraForest",
4114 .level = 0x23,
4115 .vendor = CPUID_VENDOR_INTEL,
4116 .family = 6,
4117 .model = 175,
4118 .stepping = 0,
4119 /*
4120 * please keep the ascending order so that we can have a clear view of
4121 * bit position of each feature.
4122 */
4123 .features[FEAT_1_EDX] =
4124 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
4125 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
4126 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
4127 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
4128 CPUID_SSE | CPUID_SSE2,
4129 .features[FEAT_1_ECX] =
4130 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
4131 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
4132 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
4133 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
4134 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
4135 .features[FEAT_8000_0001_EDX] =
4136 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
4137 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
4138 .features[FEAT_8000_0001_ECX] =
4139 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
4140 .features[FEAT_8000_0008_EBX] =
4141 CPUID_8000_0008_EBX_WBNOINVD,
4142 .features[FEAT_7_0_EBX] =
4143 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4144 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4145 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4146 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
4147 CPUID_7_0_EBX_SHA_NI,
4148 .features[FEAT_7_0_ECX] =
4149 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI |
4150 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
4151 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
4152 .features[FEAT_7_0_EDX] =
4153 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
4154 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
4155 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
4156 .features[FEAT_ARCH_CAPABILITIES] =
4157 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
4158 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
4159 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO |
4160 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO |
4161 MSR_ARCH_CAP_PBRSB_NO,
4162 .features[FEAT_XSAVE] =
4163 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4164 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4165 .features[FEAT_6_EAX] =
4166 CPUID_6_EAX_ARAT,
4167 .features[FEAT_7_1_EAX] =
4168 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD |
4169 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA,
4170 .features[FEAT_7_1_EDX] =
4171 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT,
4172 .features[FEAT_7_2_EDX] =
4173 CPUID_7_2_EDX_MCDT_NO,
4174 .features[FEAT_VMX_BASIC] =
4175 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
4176 .features[FEAT_VMX_ENTRY_CTLS] =
4177 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
4178 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
4179 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
4180 .features[FEAT_VMX_EPT_VPID_CAPS] =
4181 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 |
4182 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
4183 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
4184 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4185 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4186 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
4187 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4189 .features[FEAT_VMX_EXIT_CTLS] =
4190 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4191 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4192 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
4193 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4194 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4195 .features[FEAT_VMX_MISC] =
4196 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
4197 MSR_VMX_MISC_VMWRITE_VMEXIT,
4198 .features[FEAT_VMX_PINBASED_CTLS] =
4199 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
4200 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
4201 VMX_PIN_BASED_POSTED_INTR,
4202 .features[FEAT_VMX_PROCBASED_CTLS] =
4203 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4204 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4205 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4206 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4207 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4208 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4209 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
4210 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
4211 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4212 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
4213 VMX_CPU_BASED_PAUSE_EXITING |
4214 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4215 .features[FEAT_VMX_SECONDARY_CTLS] =
4216 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4217 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
4218 VMX_SECONDARY_EXEC_RDTSCP |
4219 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4220 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
4221 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4222 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4223 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4224 VMX_SECONDARY_EXEC_RDRAND_EXITING |
4225 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4226 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4227 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
4228 VMX_SECONDARY_EXEC_XSAVES,
4229 .features[FEAT_VMX_VMFUNC] =
4230 MSR_VMX_VMFUNC_EPT_SWITCHING,
4231 .xlevel = 0x80000008,
4232 .model_id = "Intel Xeon Processor (SierraForest)",
4233 .versions = (X86CPUVersionDefinition[]) {
4234 { .version = 1 },
4235 { /* end of list */ },
4236 },
4237 },
8b44d860
TX		 4238 {
4239 .name = "Denverton",
4240 .level = 21,
4241 .vendor = CPUID_VENDOR_INTEL,
4242 .family = 6,
4243 .model = 95,
4244 .stepping = 1,
4245 .features[FEAT_1_EDX] =
4246 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
4247 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
4248 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
4249 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
4250 CPUID_SSE | CPUID_SSE2,
4251 .features[FEAT_1_ECX] =
4252 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
4253 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
4254 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
4255 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
4256 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
4257 .features[FEAT_8000_0001_EDX] =
4258 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
4259 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
4260 .features[FEAT_8000_0001_ECX] =
4261 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
4262 .features[FEAT_7_0_EBX] =
4263 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
4264 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
4265 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
4266 .features[FEAT_7_0_EDX] =
4267 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
4268 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 4269 /* XSAVES is added in version 3 */
8b44d860
TX		 4270 .features[FEAT_XSAVE] =
4271 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
4272 .features[FEAT_6_EAX] =
4273 CPUID_6_EAX_ARAT,
4274 .features[FEAT_ARCH_CAPABILITIES] =
4275 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 4276 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4277 MSR_VMX_BASIC_TRUE_CTLS,
4278 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4279 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4280 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4281 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4282 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4283 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4284 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4285 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4286 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4287 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4288 .features[FEAT_VMX_EXIT_CTLS] =
4289 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4290 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4291 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4292 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4293 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4294 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4295 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4296 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4297 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4298 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4299 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4300 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4301 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4302 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4303 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4304 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4305 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4306 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4307 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4308 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4309 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4310 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4311 .features[FEAT_VMX_SECONDARY_CTLS] =
4312 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4313 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4314 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4315 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4316 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4317 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4318 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4319 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4320 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4321 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4322 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 4323 .xlevel = 0x80000008,
4324 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 4325 .versions = (X86CPUVersionDefinition[]) {
4326 { .version = 1 },
4327 {
4328 .version = 2,
47f0d11d 4329 .note = "no MPX, no MONITOR",
ab0c942c
TX		 4330 .props = (PropValue[]) {
4331 { "monitor", "off" },
4332 { "mpx", "off" },
4333 { /* end of list */ },
4334 },
4335 },
7bde6b18
VK		 4336 {
4337 .version = 3,
4338 .note = "XSAVES, no MPX, no MONITOR",
4339 .props = (PropValue[]) {
4340 { "xsaves", "on" },
4341 { "vmx-xsaves", "on" },
4342 { /* end of list */ },
4343 },
4344 },
ab0c942c
TX		 4345 { /* end of list */ },
4346 },
8b44d860 4347 },
0b18874b 4348 {
ff656fcd 4349 .name = "Snowridge",
0b18874b
PL		 4350 .level = 27,
4351 .vendor = CPUID_VENDOR_INTEL,
4352 .family = 6,
4353 .model = 134,
4354 .stepping = 1,
4355 .features[FEAT_1_EDX] =
4356 /* missing: CPUID_PN CPUID_IA64 */
4357 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
4358 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
4359 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
4360 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
4361 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
4362 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
4363 CPUID_MMX |
4364 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
4365 .features[FEAT_1_ECX] =
4366 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 4367 CPUID_EXT_SSSE3 |
4368 CPUID_EXT_CX16 |
4369 CPUID_EXT_SSE41 |
4370 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
4371 CPUID_EXT_POPCNT |
4372 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
4373 CPUID_EXT_RDRAND,
4374 .features[FEAT_8000_0001_EDX] =
4375 CPUID_EXT2_SYSCALL |
4376 CPUID_EXT2_NX |
4377 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
4378 CPUID_EXT2_LM,
4379 .features[FEAT_8000_0001_ECX] =
4380 CPUID_EXT3_LAHF_LM |
4381 CPUID_EXT3_3DNOWPREFETCH,
4382 .features[FEAT_7_0_EBX] =
4383 CPUID_7_0_EBX_FSGSBASE |
4384 CPUID_7_0_EBX_SMEP |
4385 CPUID_7_0_EBX_ERMS |
4386 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
4387 CPUID_7_0_EBX_RDSEED |
4388 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4389 CPUID_7_0_EBX_CLWB |
4390 CPUID_7_0_EBX_SHA_NI,
4391 .features[FEAT_7_0_ECX] =
4392 CPUID_7_0_ECX_UMIP |
4393 /* missing bit 5 */
4394 CPUID_7_0_ECX_GFNI |
4395 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
4396 CPUID_7_0_ECX_MOVDIR64B,
4397 .features[FEAT_7_0_EDX] =
4398 CPUID_7_0_EDX_SPEC_CTRL |
4399 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
4400 CPUID_7_0_EDX_CORE_CAPABILITY,
4401 .features[FEAT_CORE_CAPABILITY] =
4402 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7a21bee2 4403 /* XSAVES is added in version 3 */
0b18874b
PL		 4404 .features[FEAT_XSAVE] =
4405 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4406 CPUID_XSAVE_XGETBV1,
4407 .features[FEAT_6_EAX] =
4408 CPUID_6_EAX_ARAT,
0723cc8a
PB		 4409 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4410 MSR_VMX_BASIC_TRUE_CTLS,
4411 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4412 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4413 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4414 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4415 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4416 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4417 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4418 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4419 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4420 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4421 .features[FEAT_VMX_EXIT_CTLS] =
4422 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4423 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4424 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4425 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4426 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4427 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4428 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4429 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4430 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4431 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4432 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4433 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4434 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4435 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4436 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4437 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4438 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4439 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4440 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4441 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4442 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4443 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4444 .features[FEAT_VMX_SECONDARY_CTLS] =
4445 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4446 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4447 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4448 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4449 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4450 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4451 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4452 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4453 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4454 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4455 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 4456 .xlevel = 0x80000008,
4457 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 4458 .versions = (X86CPUVersionDefinition[]) {
4459 { .version = 1 },
4460 {
4461 .version = 2,
4462 .props = (PropValue[]) {
4463 { "mpx", "off" },
4464 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4465 { /* end of list */ },
4466 },
4467 },
7bde6b18
VK		 4468 {
4469 .version = 3,
4470 .note = "XSAVES, no MPX",
4471 .props = (PropValue[]) {
4472 { "xsaves", "on" },
4473 { "vmx-xsaves", "on" },
4474 { /* end of list */ },
4475 },
4476 },
56bb24e5
CQ		 4477 {
4478 .version = 4,
07db29f2 4479 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 4480 .props = (PropValue[]) {
4481 { "split-lock-detect", "off" },
07db29f2 4482 { "core-capability", "off" },
56bb24e5
CQ		 4483 { /* end of list */ },
4484 },
4485 },
69edb0f3
XL		 4486 { /* end of list */ },
4487 },
0b18874b 4488 },
a1849515
BF		 4489 {
4490 .name = "KnightsMill",
4491 .level = 0xd,
4492 .vendor = CPUID_VENDOR_INTEL,
4493 .family = 6,
4494 .model = 133,
4495 .stepping = 0,
4496 .features[FEAT_1_EDX] =
4497 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
4498 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
4499 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
4500 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
4501 CPUID_PSE | CPUID_DE | CPUID_FP87,
4502 .features[FEAT_1_ECX] =
4503 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
4504 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
4505 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
4506 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4507 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
4508 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
4509 .features[FEAT_8000_0001_EDX] =
4510 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
4511 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
4512 .features[FEAT_8000_0001_ECX] =
4513 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
4514 .features[FEAT_7_0_EBX] =
4515 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4516 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4517 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
4518 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
4519 CPUID_7_0_EBX_AVX512ER,
4520 .features[FEAT_7_0_ECX] =
4521 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
4522 .features[FEAT_7_0_EDX] =
4523 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
4524 .features[FEAT_XSAVE] =
4525 CPUID_XSAVE_XSAVEOPT,
4526 .features[FEAT_6_EAX] =
4527 CPUID_6_EAX_ARAT,
4528 .xlevel = 0x80000008,
4529 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
4530 },
3eca4642
EH		 4531 {
4532 .name = "Opteron_G1",
4533 .level = 5,
99b88a17 4534 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4535 .family = 15,
4536 .model = 6,
4537 .stepping = 1,
0514ef2f 4538 .features[FEAT_1_EDX] =
b3a4f0b1 4539 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4540 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4541 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4542 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4543 CPUID_DE | CPUID_FP87,
0514ef2f 4544 .features[FEAT_1_ECX] =
27861ecc 4545 CPUID_EXT_SSE3,
0514ef2f 4546 .features[FEAT_8000_0001_EDX] =
2a923a29 4547 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 4548 .xlevel = 0x80000008,
4549 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
4550 },
4551 {
4552 .name = "Opteron_G2",
4553 .level = 5,
99b88a17 4554 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4555 .family = 15,
4556 .model = 6,
4557 .stepping = 1,
0514ef2f 4558 .features[FEAT_1_EDX] =
b3a4f0b1 4559 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4560 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4561 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4562 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4563 CPUID_DE | CPUID_FP87,
0514ef2f 4564 .features[FEAT_1_ECX] =
27861ecc 4565 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 4566 .features[FEAT_8000_0001_EDX] =
2a923a29 4567 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 4568 .features[FEAT_8000_0001_ECX] =
27861ecc 4569 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4570 .xlevel = 0x80000008,
4571 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
4572 },
4573 {
4574 .name = "Opteron_G3",
4575 .level = 5,
99b88a17 4576 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 4577 .family = 16,
4578 .model = 2,
4579 .stepping = 3,
0514ef2f 4580 .features[FEAT_1_EDX] =
b3a4f0b1 4581 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4582 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4583 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4584 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4585 CPUID_DE | CPUID_FP87,
0514ef2f 4586 .features[FEAT_1_ECX] =
27861ecc 4587 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 4588 CPUID_EXT_SSE3,
0514ef2f 4589 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 4590 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
4591 CPUID_EXT2_RDTSCP,
0514ef2f 4592 .features[FEAT_8000_0001_ECX] =
27861ecc 4593 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 4594 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4595 .xlevel = 0x80000008,
4596 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
4597 },
4598 {
4599 .name = "Opteron_G4",
4600 .level = 0xd,
99b88a17 4601 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4602 .family = 21,
4603 .model = 1,
4604 .stepping = 2,
0514ef2f 4605 .features[FEAT_1_EDX] =
b3a4f0b1 4606 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4610 CPUID_DE | CPUID_FP87,
0514ef2f 4611 .features[FEAT_1_ECX] =
27861ecc 4612 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 4613 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4614 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
4615 CPUID_EXT_SSE3,
0514ef2f 4616 .features[FEAT_8000_0001_EDX] =
2a923a29 4617 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4618 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4619 .features[FEAT_8000_0001_ECX] =
27861ecc 4620 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4621 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4622 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4623 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4624 .features[FEAT_SVM] =
4625 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4626 /* no xsaveopt! */
3eca4642
EH		 4627 .xlevel = 0x8000001A,
4628 .model_id = "AMD Opteron 62xx class CPU",
4629 },
021941b9
AP		 4630 {
4631 .name = "Opteron_G5",
4632 .level = 0xd,
99b88a17 4633 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 4634 .family = 21,
4635 .model = 2,
4636 .stepping = 0,
0514ef2f 4637 .features[FEAT_1_EDX] =
b3a4f0b1 4638 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4639 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4640 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4641 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4642 CPUID_DE | CPUID_FP87,
0514ef2f 4643 .features[FEAT_1_ECX] =
27861ecc 4644 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 4645 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
4646 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4647 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 4648 .features[FEAT_8000_0001_EDX] =
2a923a29 4649 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4650 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4651 .features[FEAT_8000_0001_ECX] =
27861ecc 4652 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4653 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4654 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4655 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4656 .features[FEAT_SVM] =
4657 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4658 /* no xsaveopt! */
021941b9
AP		 4659 .xlevel = 0x8000001A,
4660 .model_id = "AMD Opteron 63xx class CPU",
4661 },
2e2efc7d
BS		 4662 {
4663 .name = "EPYC",
4664 .level = 0xd,
4665 .vendor = CPUID_VENDOR_AMD,
4666 .family = 23,
4667 .model = 1,
4668 .stepping = 2,
4669 .features[FEAT_1_EDX] =
4670 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4671 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4672 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4673 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4674 CPUID_VME | CPUID_FP87,
4675 .features[FEAT_1_ECX] =
4676 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4677 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4678 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4679 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4680 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4681 .features[FEAT_8000_0001_EDX] =
4682 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4683 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4684 CPUID_EXT2_SYSCALL,
4685 .features[FEAT_8000_0001_ECX] =
4686 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4687 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 4688 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4689 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 4690 .features[FEAT_7_0_EBX] =
4691 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4692 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4693 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4694 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 4695 .features[FEAT_XSAVE] =
4696 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4697 CPUID_XSAVE_XGETBV1,
4698 .features[FEAT_6_EAX] =
4699 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 4700 .features[FEAT_SVM] =
4701 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 4702 .xlevel = 0x8000001E,
2e2efc7d 4703 .model_id = "AMD EPYC Processor",
fe52acd2 4704 .cache_info = &epyc_cache_info,
d86a7088
EH		 4705 .versions = (X86CPUVersionDefinition[]) {
4706 { .version = 1 },
4707 {
4708 .version = 2,
53db89d9 4709 .alias = "EPYC-IBPB",
d86a7088
EH		 4710 .props = (PropValue[]) {
4711 { "ibpb", "on" },
4712 { "model-id",
4713 "AMD EPYC Processor (with IBPB)" },
4714 { /* end of list */ }
4715 }
4716 },
a16e8dbc
MB		 4717 {
4718 .version = 3,
4719 .props = (PropValue[]) {
4720 { "ibpb", "on" },
4721 { "perfctr-core", "on" },
4722 { "clzero", "on" },
4723 { "xsaveerptr", "on" },
4724 { "xsaves", "on" },
4725 { "model-id",
4726 "AMD EPYC Processor" },
4727 { /* end of list */ }
4728 }
4729 },
d7c72735
MR		 4730 {
4731 .version = 4,
4732 .props = (PropValue[]) {
4733 { "model-id",
4734 "AMD EPYC-v4 Processor" },
4735 { /* end of list */ }
4736 },
4737 .cache_info = &epyc_v4_cache_info
4738 },
d86a7088
EH		 4739 { /* end of list */ }
4740 }
2e2efc7d 4741 },
8d031cec
PW		 4742 {
4743 .name = "Dhyana",
4744 .level = 0xd,
4745 .vendor = CPUID_VENDOR_HYGON,
4746 .family = 24,
4747 .model = 0,
4748 .stepping = 1,
4749 .features[FEAT_1_EDX] =
4750 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4751 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4752 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4753 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4754 CPUID_VME | CPUID_FP87,
4755 .features[FEAT_1_ECX] =
4756 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4757 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4758 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4759 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4760 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4761 .features[FEAT_8000_0001_EDX] =
4762 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4763 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4764 CPUID_EXT2_SYSCALL,
4765 .features[FEAT_8000_0001_ECX] =
4766 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4767 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4768 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4769 CPUID_EXT3_TOPOEXT,
4770 .features[FEAT_8000_0008_EBX] =
4771 CPUID_8000_0008_EBX_IBPB,
4772 .features[FEAT_7_0_EBX] =
4773 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4774 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4775 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 4776 /* XSAVES is added in version 2 */
8d031cec
PW		 4777 .features[FEAT_XSAVE] =
4778 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4779 CPUID_XSAVE_XGETBV1,
4780 .features[FEAT_6_EAX] =
4781 CPUID_6_EAX_ARAT,
4782 .features[FEAT_SVM] =
4783 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4784 .xlevel = 0x8000001E,
4785 .model_id = "Hygon Dhyana Processor",
4786 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4787 .versions = (X86CPUVersionDefinition[]) {
4788 { .version = 1 },
4789 { .version = 2,
4790 .note = "XSAVES",
4791 .props = (PropValue[]) {
4792 { "xsaves", "on" },
4793 { /* end of list */ }
4794 },
4795 },
4796 { /* end of list */ }
4797 }
8d031cec 4798 },
143c30d4
MB		 4799 {
4800 .name = "EPYC-Rome",
4801 .level = 0xd,
4802 .vendor = CPUID_VENDOR_AMD,
4803 .family = 23,
4804 .model = 49,
4805 .stepping = 0,
4806 .features[FEAT_1_EDX] =
4807 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4808 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4809 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4810 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4811 CPUID_VME | CPUID_FP87,
4812 .features[FEAT_1_ECX] =
4813 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4814 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4815 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4816 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4817 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4818 .features[FEAT_8000_0001_EDX] =
4819 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4820 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4821 CPUID_EXT2_SYSCALL,
4822 .features[FEAT_8000_0001_ECX] =
4823 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4824 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4825 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4826 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4827 .features[FEAT_8000_0008_EBX] =
4828 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4829 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4830 CPUID_8000_0008_EBX_STIBP,
4831 .features[FEAT_7_0_EBX] =
4832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4833 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4834 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4835 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4836 .features[FEAT_7_0_ECX] =
4837 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4838 .features[FEAT_XSAVE] =
4839 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4840 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4841 .features[FEAT_6_EAX] =
4842 CPUID_6_EAX_ARAT,
4843 .features[FEAT_SVM] =
4844 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4845 .xlevel = 0x8000001E,
4846 .model_id = "AMD EPYC-Rome Processor",
4847 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4848 .versions = (X86CPUVersionDefinition[]) {
4849 { .version = 1 },
4850 {
4851 .version = 2,
4852 .props = (PropValue[]) {
4853 { "ibrs", "on" },
4854 { "amd-ssbd", "on" },
4855 { /* end of list */ }
4856 }
4857 },
d7c72735
MR		 4858 {
4859 .version = 3,
4860 .props = (PropValue[]) {
4861 { "model-id",
4862 "AMD EPYC-Rome-v3 Processor" },
4863 { /* end of list */ }
4864 },
4865 .cache_info = &epyc_rome_v3_cache_info
4866 },
fb00aa61
MD		 4867 {
4868 .version = 4,
4869 .props = (PropValue[]) {
4870 /* Erratum 1386 */
4871 { "model-id",
4872 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
4873 { "xsaves", "off" },
4874 { /* end of list */ }
4875 },
4876 },
cdeaed27
BM		 4877 { /* end of list */ }
4878 }
143c30d4 4879 },
623972ce
BM		 4880 {
4881 .name = "EPYC-Milan",
4882 .level = 0xd,
4883 .vendor = CPUID_VENDOR_AMD,
4884 .family = 25,
4885 .model = 1,
4886 .stepping = 1,
4887 .features[FEAT_1_EDX] =
4888 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4889 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4890 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4891 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4892 CPUID_VME | CPUID_FP87,
4893 .features[FEAT_1_ECX] =
4894 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4895 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4896 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4897 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4898 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4899 CPUID_EXT_PCID,
4900 .features[FEAT_8000_0001_EDX] =
4901 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4902 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4903 CPUID_EXT2_SYSCALL,
4904 .features[FEAT_8000_0001_ECX] =
4905 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4906 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4907 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4908 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4909 .features[FEAT_8000_0008_EBX] =
4910 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4911 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4912 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4913 CPUID_8000_0008_EBX_AMD_SSBD,
4914 .features[FEAT_7_0_EBX] =
4915 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4916 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4917 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4918 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4919 CPUID_7_0_EBX_INVPCID,
4920 .features[FEAT_7_0_ECX] =
4921 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4922 .features[FEAT_7_0_EDX] =
4923 CPUID_7_0_EDX_FSRM,
4924 .features[FEAT_XSAVE] =
4925 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4926 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4927 .features[FEAT_6_EAX] =
4928 CPUID_6_EAX_ARAT,
4929 .features[FEAT_SVM] =
4930 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4931 .xlevel = 0x8000001E,
4932 .model_id = "AMD EPYC-Milan Processor",
4933 .cache_info = &epyc_milan_cache_info,
27f03be6
BM		 4934 .versions = (X86CPUVersionDefinition[]) {
4935 { .version = 1 },
4936 {
4937 .version = 2,
4938 .props = (PropValue[]) {
4939 { "model-id",
4940 "AMD EPYC-Milan-v2 Processor" },
4941 { "vaes", "on" },
4942 { "vpclmulqdq", "on" },
4943 { "stibp-always-on", "on" },
4944 { "amd-psfd", "on" },
4945 { "no-nested-data-bp", "on" },
4946 { "lfence-always-serializing", "on" },
4947 { "null-sel-clr-base", "on" },
4948 { /* end of list */ }
4949 },
4950 .cache_info = &epyc_milan_v2_cache_info
4951 },
4952 { /* end of list */ }
4953 }
623972ce 4954 },
166b1741
BM		 4955 {
4956 .name = "EPYC-Genoa",
4957 .level = 0xd,
4958 .vendor = CPUID_VENDOR_AMD,
4959 .family = 25,
4960 .model = 17,
4961 .stepping = 0,
4962 .features[FEAT_1_EDX] =
4963 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4964 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4965 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4966 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4967 CPUID_VME | CPUID_FP87,
4968 .features[FEAT_1_ECX] =
4969 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4970 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4971 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4972 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4973 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ |
4974 CPUID_EXT_SSE3,
4975 .features[FEAT_8000_0001_EDX] =
4976 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4977 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4978 CPUID_EXT2_SYSCALL,
4979 .features[FEAT_8000_0001_ECX] =
4980 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4981 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4982 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4983 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4984 .features[FEAT_8000_0008_EBX] =
4985 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4986 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4987 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4988 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON |
4989 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD,
4990 .features[FEAT_8000_0021_EAX] =
4991 CPUID_8000_0021_EAX_No_NESTED_DATA_BP |
4992 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING |
4993 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE |
4994 CPUID_8000_0021_EAX_AUTO_IBRS,
4995 .features[FEAT_7_0_EBX] =
4996 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4997 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4998 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F |
4999 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
5000 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
5001 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
5002 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
5003 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
5004 .features[FEAT_7_0_ECX] =
5005 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
5006 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
5007 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
5008 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
5009 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
5010 CPUID_7_0_ECX_RDPID,
5011 .features[FEAT_7_0_EDX] =
5012 CPUID_7_0_EDX_FSRM,
5013 .features[FEAT_7_1_EAX] =
5014 CPUID_7_1_EAX_AVX512_BF16,
5015 .features[FEAT_XSAVE] =
5016 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
5017 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
5018 .features[FEAT_6_EAX] =
5019 CPUID_6_EAX_ARAT,
5020 .features[FEAT_SVM] =
5021 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI |
5022 CPUID_SVM_SVME_ADDR_CHK,
5023 .xlevel = 0x80000022,
5024 .model_id = "AMD EPYC-Genoa Processor",
5025 .cache_info = &epyc_genoa_cache_info,
5026 },
c6dc6f63
AP		 5027};
5028
ad183928
EH		 5029/*
5030 * We resolve CPU model aliases using -v1 when using "-machine
5031 * none", but this is just for compatibility while libvirt isn't
5032 * adapted to resolve CPU model versions before creating VMs.
32048d72 5033 * See "Runnability guarantee of CPU models" at
a476b216 5034 * docs/about/deprecated.rst.
ad183928
EH		 5035 */
5036X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 5037
5038void x86_cpu_set_default_version(X86CPUVersion version)
5039{
5040 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
5041 assert(version != CPU_VERSION_AUTO);
5042 default_cpu_version = version;
5043}
5044
dcafd1ef
EH		 5045static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
5046{
5047 int v = 0;
5048 const X86CPUVersionDefinition *vdef =
5049 x86_cpu_def_get_versions(model->cpudef);
5050 while (vdef->version) {
5051 v = vdef->version;
5052 vdef++;
5053 }
5054 return v;
5055}
5056
5057/* Return the actual version being used for a specific CPU model */
5058static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
5059{
5060 X86CPUVersion v = model->version;
0788a56b
EH		 5061 if (v == CPU_VERSION_AUTO) {
5062 v = default_cpu_version;
5063 }
dcafd1ef
EH		 5064 if (v == CPU_VERSION_LATEST) {
5065 return x86_cpu_model_last_version(model);
5066 }
5067 return v;
5068}
5069
c62f2630 5070static Property max_x86_cpu_properties[] = {
120eee7d 5071 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 5072 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 5073 DEFINE_PROP_END_OF_LIST()
5074};
5075
123fa102
TH		 5076static void max_x86_cpu_realize(DeviceState *dev, Error **errp)
5077{
5078 Object *obj = OBJECT(dev);
5079
5080 if (!object_property_get_int(obj, "family", &error_abort)) {
5081 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5082 object_property_set_int(obj, "family", 15, &error_abort);
5083 object_property_set_int(obj, "model", 107, &error_abort);
5084 object_property_set_int(obj, "stepping", 1, &error_abort);
5085 } else {
5086 object_property_set_int(obj, "family", 6, &error_abort);
5087 object_property_set_int(obj, "model", 6, &error_abort);
5088 object_property_set_int(obj, "stepping", 3, &error_abort);
5089 }
5090 }
5091
5092 x86_cpu_realizefn(dev, errp);
5093}
5094
c62f2630 5095static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 5096{
84f1b92f 5097 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 5098 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 5099
f48c8837 5100 xcc->ordering = 9;
6e746f30 5101
ee465a3e 5102 xcc->model_description =
c62f2630 5103 "Enables all features supported by the accelerator in the current host";
d940ee9b 5104
4f67d30b 5105 device_class_set_props(dc, max_x86_cpu_properties);
123fa102 5106 dc->realize = max_x86_cpu_realize;
d940ee9b
EH		 5107}
5108
c62f2630 5109static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 5110{
5111 X86CPU *cpu = X86_CPU(obj);
d940ee9b 5112
4d1b279b
EH		 5113 /* We can't fill the features array here because we don't know yet if
5114 * "migratable" is true or false.
5115 */
44bd8e53 5116 cpu->max_features = true;
5325cc34 5117 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 5118
5119 /*
5120 * these defaults are used for TCG and all other accelerators
5121 * besides KVM and HVF, which overwrite these values
5122 */
5123 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
5124 &error_abort);
f5cc5a5c
CF		 5125 object_property_set_str(OBJECT(cpu), "model-id",
5126 "QEMU TCG CPU version " QEMU_HW_VERSION,
5127 &error_abort);
c6dc6f63
AP		 5128}
5129
c62f2630
EH		 5130static const TypeInfo max_x86_cpu_type_info = {
5131 .name = X86_CPU_TYPE_NAME("max"),
5132 .parent = TYPE_X86_CPU,
5133 .instance_init = max_x86_cpu_initfn,
5134 .class_init = max_x86_cpu_class_init,
5135};
5136
07585923
RH		 5137static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
5138{
5139 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
5140
5141 switch (f->type) {
5142 case CPUID_FEATURE_WORD:
5143 {
5144 const char *reg = get_register_name_32(f->cpuid.reg);
5145 assert(reg);
5146 return g_strdup_printf("CPUID.%02XH:%s",
5147 f->cpuid.eax, reg);
5148 }
5149 case MSR_FEATURE_WORD:
5150 return g_strdup_printf("MSR(%02XH)",
5151 f->msr.index);
5152 }
5153
5154 return NULL;
5155}
5156
245edd0c 5157static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 5158{
245edd0c
PB		 5159 FeatureWord w;
5160
5161 for (w = 0; w < FEATURE_WORDS; w++) {
5162 if (cpu->filtered_features[w]) {
5163 return true;
5164 }
5165 }
5166
5167 return false;
5168}
5169
ede146c2 5170static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 5171 const char *verbose_prefix)
5172{
5173 CPUX86State *env = &cpu->env;
8459e396 5174 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 5175 int i;
5176
245edd0c
PB		 5177 if (!cpu->force_features) {
5178 env->features[w] &= ~mask;
5179 }
5180 cpu->filtered_features[w] |= mask;
5181
5182 if (!verbose_prefix) {
5183 return;
5184 }
5185
ede146c2
PB		 5186 for (i = 0; i < 64; ++i) {
5187 if ((1ULL << i) & mask) {
88703ce2 5188 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 5189 warn_report("%s: %s%s%s [bit %d]",
5190 verbose_prefix,
07585923 5191 feat_word_str,
8297be80
AF		 5192 f->feat_names[i] ? "." : "",
5193 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 5194 }
857aee33 5195 }
c6dc6f63
AP		 5196}
5197
d7bce999
EB		 5198static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
5199 const char *name, void *opaque,
5200 Error **errp)
95b8519d
AF		 5201{
5202 X86CPU *cpu = X86_CPU(obj);
5203 CPUX86State *env = &cpu->env;
5204 int64_t value;
5205
5206 value = (env->cpuid_version >> 8) & 0xf;
5207 if (value == 0xf) {
5208 value += (env->cpuid_version >> 20) & 0xff;
5209 }
51e72bc1 5210 visit_type_int(v, name, &value, errp);
95b8519d
AF		 5211}
5212
d7bce999
EB		 5213static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
5214 const char *name, void *opaque,
5215 Error **errp)
ed5e1ec3 5216{
71ad61d3
AF		 5217 X86CPU *cpu = X86_CPU(obj);
5218 CPUX86State *env = &cpu->env;
5219 const int64_t min = 0;
5220 const int64_t max = 0xff + 0xf;
5221 int64_t value;
5222
668f62ec 5223 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 5224 return;
5225 }
5226 if (value < min || value > max) {
c6bd8c70
MA		 5227 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5228 name ? name : "null", value, min, max);
71ad61d3
AF		 5229 return;
5230 }
5231
ed5e1ec3 5232 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 5233 if (value > 0x0f) {
5234 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 5235 } else {
71ad61d3 5236 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 5237 }
5238}
5239
d7bce999
EB		 5240static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
5241 const char *name, void *opaque,
5242 Error **errp)
67e30c83
AF		 5243{
5244 X86CPU *cpu = X86_CPU(obj);
5245 CPUX86State *env = &cpu->env;
5246 int64_t value;
5247
5248 value = (env->cpuid_version >> 4) & 0xf;
5249 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 5250 visit_type_int(v, name, &value, errp);
67e30c83
AF		 5251}
5252
d7bce999
EB		 5253static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
5254 const char *name, void *opaque,
5255 Error **errp)
b0704cbd 5256{
c5291a4f
AF		 5257 X86CPU *cpu = X86_CPU(obj);
5258 CPUX86State *env = &cpu->env;
5259 const int64_t min = 0;
5260 const int64_t max = 0xff;
5261 int64_t value;
5262
668f62ec 5263 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 5264 return;
5265 }
5266 if (value < min || value > max) {
c6bd8c70
MA		 5267 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5268 name ? name : "null", value, min, max);
c5291a4f
AF		 5269 return;
5270 }
5271
b0704cbd 5272 env->cpuid_version &= ~0xf00f0;
c5291a4f 5273 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 5274}
5275
35112e41 5276static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 5277 const char *name, void *opaque,
35112e41
AF		 5278 Error **errp)
5279{
5280 X86CPU *cpu = X86_CPU(obj);
5281 CPUX86State *env = &cpu->env;
5282 int64_t value;
5283
5284 value = env->cpuid_version & 0xf;
51e72bc1 5285 visit_type_int(v, name, &value, errp);
35112e41
AF		 5286}
5287
036e2222 5288static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 5289 const char *name, void *opaque,
036e2222 5290 Error **errp)
38c3dc46 5291{
036e2222
AF		 5292 X86CPU *cpu = X86_CPU(obj);
5293 CPUX86State *env = &cpu->env;
5294 const int64_t min = 0;
5295 const int64_t max = 0xf;
5296 int64_t value;
5297
668f62ec 5298 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 5299 return;
5300 }
5301 if (value < min || value > max) {
c6bd8c70
MA		 5302 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5303 name ? name : "null", value, min, max);
036e2222
AF		 5304 return;
5305 }
5306
38c3dc46 5307 env->cpuid_version &= ~0xf;
036e2222 5308 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 5309}
5310
d480e1af
AF		 5311static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
5312{
5313 X86CPU *cpu = X86_CPU(obj);
5314 CPUX86State *env = &cpu->env;
5315 char *value;
d480e1af 5316
e42a92ae 5317 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 5318 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
5319 env->cpuid_vendor3);
d480e1af
AF		 5320 return value;
5321}
5322
5323static void x86_cpuid_set_vendor(Object *obj, const char *value,
5324 Error **errp)
5325{
5326 X86CPU *cpu = X86_CPU(obj);
5327 CPUX86State *env = &cpu->env;
5328 int i;
5329
9df694ee 5330 if (strlen(value) != CPUID_VENDOR_SZ) {
298d8b12
MA		 5331 error_setg(errp, "value of property 'vendor' must consist of"
5332 " exactly " stringify(CPUID_VENDOR_SZ) " characters");
d480e1af
AF		 5333 return;
5334 }
5335
5336 env->cpuid_vendor1 = 0;
5337 env->cpuid_vendor2 = 0;
5338 env->cpuid_vendor3 = 0;
5339 for (i = 0; i < 4; i++) {
5340 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
5341 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
5342 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
5343 }
d480e1af
AF		 5344}
5345
63e886eb
AF		 5346static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
5347{
5348 X86CPU *cpu = X86_CPU(obj);
5349 CPUX86State *env = &cpu->env;
5350 char *value;
5351 int i;
5352
5353 value = g_malloc(48 + 1);
5354 for (i = 0; i < 48; i++) {
5355 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
5356 }
5357 value[48] = '\0';
5358 return value;
5359}
5360
938d4c25
AF		 5361static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
5362 Error **errp)
dcce6675 5363{
938d4c25
AF		 5364 X86CPU *cpu = X86_CPU(obj);
5365 CPUX86State *env = &cpu->env;
dcce6675
AF		 5366 int c, len, i;
5367
5368 if (model_id == NULL) {
5369 model_id = "";
5370 }
5371 len = strlen(model_id);
d0a6acf4 5372 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 5373 for (i = 0; i < 48; i++) {
5374 if (i >= len) {
5375 c = '\0';
5376 } else {
5377 c = (uint8_t)model_id[i];
5378 }
5379 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
5380 }
5381}
5382
d7bce999
EB		 5383static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
5384 void *opaque, Error **errp)
89e48965
AF		 5385{
5386 X86CPU *cpu = X86_CPU(obj);
5387 int64_t value;
5388
5389 value = cpu->env.tsc_khz * 1000;
51e72bc1 5390 visit_type_int(v, name, &value, errp);
89e48965
AF		 5391}
5392
d7bce999
EB		 5393static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
5394 void *opaque, Error **errp)
89e48965
AF		 5395{
5396 X86CPU *cpu = X86_CPU(obj);
5397 const int64_t min = 0;
2e84849a 5398 const int64_t max = INT64_MAX;
89e48965
AF		 5399 int64_t value;
5400
668f62ec 5401 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 5402 return;
5403 }
5404 if (value < min || value > max) {
c6bd8c70
MA		 5405 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5406 name ? name : "null", value, min, max);
89e48965
AF		 5407 return;
5408 }
5409
36f96c4b 5410 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 5411}
5412
7e5292b5 5413/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 5414static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
5415 const char *name, void *opaque,
5416 Error **errp)
8e8aba50 5417{
ede146c2 5418 uint64_t *array = (uint64_t *)opaque;
8e8aba50 5419 FeatureWord w;
8e8aba50
EH		 5420 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
5421 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
5422 X86CPUFeatureWordInfoList *list = NULL;
5423
5424 for (w = 0; w < FEATURE_WORDS; w++) {
5425 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 5426 /*
5427 * We didn't have MSR features when "feature-words" was
5428 * introduced. Therefore skipped other type entries.
5429 */
5430 if (wi->type != CPUID_FEATURE_WORD) {
5431 continue;
5432 }
8e8aba50 5433 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 5434 qwi->cpuid_input_eax = wi->cpuid.eax;
5435 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
5436 qwi->cpuid_input_ecx = wi->cpuid.ecx;
5437 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 5438 qwi->features = array[w];
8e8aba50
EH		 5439
5440 /* List will be in reverse order, but order shouldn't matter */
5441 list_entries[w].next = list;
5442 list_entries[w].value = &word_infos[w];
5443 list = &list_entries[w];
5444 }
5445
6b62d961 5446 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 5447}
5448
72ac2e87
IM		 5449/* Convert all '_' in a feature string option name to '-', to make feature
5450 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5451 */
5452static inline void feat2prop(char *s)
5453{
5454 while ((s = strchr(s, '_'))) {
5455 *s = '-';
5456 }
5457}
5458
b54c9377
EH		 5459/* Return the feature property name for a feature flag bit */
5460static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
5461{
ede146c2 5462 const char *name;
b54c9377
EH		 5463 /* XSAVE components are automatically enabled by other features,
5464 * so return the original feature name instead
5465 */
301e9067
YW		 5466 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) {
5467 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr;
b54c9377
EH		 5468
5469 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
5470 x86_ext_save_areas[comp].bits) {
5471 w = x86_ext_save_areas[comp].feature;
5472 bitnr = ctz32(x86_ext_save_areas[comp].bits);
5473 }
5474 }
5475
ede146c2 5476 assert(bitnr < 64);
b54c9377 5477 assert(w < FEATURE_WORDS);
ede146c2
PB		 5478 name = feature_word_info[w].feat_names[bitnr];
5479 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
5480 return name;
b54c9377
EH		 5481}
5482
bad5cfcd 5483/* Compatibility hack to maintain legacy +-feat semantic,
dc15c051
IM		 5484 * where +-feat overwrites any feature set by
5485 * feat=on|feat even if the later is parsed after +-feat
5486 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5487 */
2fae0d96 5488static GList *plus_features, *minus_features;
dc15c051 5489
83a00f60
EH		 5490static gint compare_string(gconstpointer a, gconstpointer b)
5491{
5492 return g_strcmp0(a, b);
5493}
5494
8f961357
EH		 5495/* Parse "+feature,-feature,feature=foo" CPU feature string
5496 */
62a48a2a 5497static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 5498 Error **errp)
8f961357 5499{
8f961357 5500 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 5501 static bool cpu_globals_initialized;
83a00f60 5502 bool ambiguous = false;
62a48a2a
IM		 5503
5504 if (cpu_globals_initialized) {
5505 return;
5506 }
5507 cpu_globals_initialized = true;
8f961357 5508
f6750e95
EH		 5509 if (!features) {
5510 return;
5511 }
5512
5513 for (featurestr = strtok(features, ",");
685479bd 5514 featurestr;
f6750e95
EH		 5515 featurestr = strtok(NULL, ",")) {
5516 const char *name;
5517 const char *val = NULL;
5518 char *eq = NULL;
cf2887c9 5519 char num[32];
62a48a2a 5520 GlobalProperty *prop;
c6dc6f63 5521
f6750e95 5522 /* Compatibility syntax: */
c6dc6f63 5523 if (featurestr[0] == '+') {
2fae0d96
EH		 5524 plus_features = g_list_append(plus_features,
5525 g_strdup(featurestr + 1));
f6750e95 5526 continue;
c6dc6f63 5527 } else if (featurestr[0] == '-') {
2fae0d96
EH		 5528 minus_features = g_list_append(minus_features,
5529 g_strdup(featurestr + 1));
f6750e95
EH		 5530 continue;
5531 }
5532
5533 eq = strchr(featurestr, '=');
5534 if (eq) {
5535 *eq++ = 0;
5536 val = eq;
c6dc6f63 5537 } else {
f6750e95 5538 val = "on";
a91987c2 5539 }
f6750e95
EH		 5540
5541 feat2prop(featurestr);
5542 name = featurestr;
5543
83a00f60 5544 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 5545 warn_report("Ambiguous CPU model string. "
5546 "Don't mix both \"+%s\" and \"%s=%s\"",
5547 name, name, val);
83a00f60
EH		 5548 ambiguous = true;
5549 }
5550 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 5551 warn_report("Ambiguous CPU model string. "
5552 "Don't mix both \"-%s\" and \"%s=%s\"",
5553 name, name, val);
83a00f60
EH		 5554 ambiguous = true;
5555 }
5556
f6750e95
EH		 5557 /* Special case: */
5558 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 5559 int ret;
f46bfdbf 5560 uint64_t tsc_freq;
f6750e95 5561
f17fd4fd 5562 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 5563 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 5564 error_setg(errp, "bad numerical value %s", val);
5565 return;
5566 }
5567 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
5568 val = num;
5569 name = "tsc-frequency";
c6dc6f63 5570 }
f6750e95 5571
62a48a2a
IM		 5572 prop = g_new0(typeof(*prop), 1);
5573 prop->driver = typename;
5574 prop->property = g_strdup(name);
5575 prop->value = g_strdup(val);
62a48a2a 5576 qdev_prop_register_global(prop);
f6750e95
EH		 5577 }
5578
83a00f60 5579 if (ambiguous) {
3dc6f869
AF		 5580 warn_report("Compatibility of ambiguous CPU model "
5581 "strings won't be kept on future QEMU versions");
83a00f60 5582 }
c6dc6f63
AP		 5583}
5584
245edd0c 5585static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 5586
5a853fc5
EH		 5587/* Build a list with the name of all features on a feature word array */
5588static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 5589 strList **list)
5a853fc5 5590{
c3033fd3 5591 strList **tail = list;
5a853fc5 5592 FeatureWord w;
5a853fc5
EH		 5593
5594 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 5595 uint64_t filtered = features[w];
5a853fc5 5596 int i;
ede146c2
PB		 5597 for (i = 0; i < 64; i++) {
5598 if (filtered & (1ULL << i)) {
c3033fd3 5599 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 5600 }
5601 }
5602 }
5603}
5604
506174bf
EH		 5605static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
5606 const char *name, void *opaque,
5607 Error **errp)
5608{
5609 X86CPU *xc = X86_CPU(obj);
5610 strList *result = NULL;
5611
5612 x86_cpu_list_feature_names(xc->filtered_features, &result);
5613 visit_type_strList(v, "unavailable-features", &result, errp);
5614}
5615
8c3329e5 5616/* Print all cpuid feature names in featureset
c6dc6f63 5617 */
0442428a 5618static void listflags(GList *features)
0856579c 5619{
cc643b1e
DB		 5620 size_t len = 0;
5621 GList *tmp;
5622
5623 for (tmp = features; tmp; tmp = tmp->next) {
5624 const char *name = tmp->data;
5625 if ((len + strlen(name) + 1) >= 75) {
0442428a 5626 qemu_printf("\n");
cc643b1e 5627 len = 0;
c6dc6f63 5628 }
0442428a 5629 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 5630 len += strlen(name) + 1;
8c3329e5 5631 }
0442428a 5632 qemu_printf("\n");
c6dc6f63
AP		 5633}
5634
f48c8837 5635/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 5636static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
5637{
5638 ObjectClass *class_a = (ObjectClass *)a;
5639 ObjectClass *class_b = (ObjectClass *)b;
5640 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
5641 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 5642 int ret;
ee465a3e 5643
f48c8837 5644 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 5645 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 5646 } else {
88703ce2
EH		 5647 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
5648 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 5649 ret = strcmp(name_a, name_b);
ee465a3e 5650 }
c7dbff4b 5651 return ret;
ee465a3e
EH		 5652}
5653
5654static GSList *get_sorted_cpu_model_list(void)
5655{
5656 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
5657 list = g_slist_sort(list, x86_cpu_list_compare);
5658 return list;
5659}
5660
164e779c
EH		 5661static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
5662{
3c75e12e 5663 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 5664 char *r = object_property_get_str(obj, "model-id", &error_abort);
5665 object_unref(obj);
5666 return r;
5667}
5668
0788a56b
EH		 5669static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
5670{
5671 X86CPUVersion version;
5672
5673 if (!cc->model || !cc->model->is_alias) {
5674 return NULL;
5675 }
5676 version = x86_cpu_model_resolve_version(cc->model);
5677 if (version <= 0) {
5678 return NULL;
5679 }
5680 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
5681}
5682
ee465a3e
EH		 5683static void x86_cpu_list_entry(gpointer data, gpointer user_data)
5684{
5685 ObjectClass *oc = data;
5686 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 5687 g_autofree char *name = x86_cpu_class_get_model_name(cc);
5688 g_autofree char *desc = g_strdup(cc->model_description);
5689 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 5690 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 5691
0788a56b
EH		 5692 if (!desc && alias_of) {
5693 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
5694 desc = g_strdup("(alias configured by machine type)");
5695 } else {
5696 desc = g_strdup_printf("(alias of %s)", alias_of);
5697 }
5698 }
c63938df
TX		 5699 if (!desc && cc->model && cc->model->note) {
5700 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
5701 }
164e779c 5702 if (!desc) {
c63938df 5703 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 5704 }
5705
5dfa9e86
DB		 5706 if (cc->model && cc->model->cpudef->deprecation_note) {
5707 g_autofree char *olddesc = desc;
5708 desc = g_strdup_printf("%s (deprecated)", olddesc);
5709 }
5710
49843214 5711 qemu_printf(" %-20s %s\n", name, desc);
ee465a3e
EH		 5712}
5713
5714/* list available CPU models and flags */
0442428a 5715void x86_cpu_list(void)
c6dc6f63 5716{
cc643b1e 5717 int i, j;
ee465a3e 5718 GSList *list;
cc643b1e 5719 GList *names = NULL;
c6dc6f63 5720
0442428a 5721 qemu_printf("Available CPUs:\n");
ee465a3e 5722 list = get_sorted_cpu_model_list();
0442428a 5723 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 5724 g_slist_free(list);
21ad7789 5725
cc643b1e 5726 names = NULL;
3af60be2
JK		 5727 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
5728 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 5729 for (j = 0; j < 64; j++) {
cc643b1e
DB		 5730 if (fw->feat_names[j]) {
5731 names = g_list_append(names, (gpointer)fw->feat_names[j]);
5732 }
5733 }
3af60be2 5734 }
cc643b1e
DB		 5735
5736 names = g_list_sort(names, (GCompareFunc)strcmp);
5737
0442428a
MA		 5738 qemu_printf("\nRecognized CPUID flags:\n");
5739 listflags(names);
5740 qemu_printf("\n");
cc643b1e 5741 g_list_free(names);
c6dc6f63
AP		 5742}
5743
390dbc6e
PMD		 5744#ifndef CONFIG_USER_ONLY
5745
5746/* Check for missing features that may prevent the CPU class from
5747 * running using the current machine and accelerator.
5748 */
5749static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
5750 strList **list)
5751{
5752 strList **tail = list;
5753 X86CPU *xc;
5754 Error *err = NULL;
5755
5756 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
5757 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
5758 return;
5759 }
5760
5761 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5762
5763 x86_cpu_expand_features(xc, &err);
5764 if (err) {
5765 /* Errors at x86_cpu_expand_features should never happen,
5766 * but in case it does, just report the model as not
5767 * runnable at all using the "type" property.
5768 */
5769 QAPI_LIST_APPEND(tail, g_strdup("type"));
5770 error_free(err);
5771 }
5772
5773 x86_cpu_filter_features(xc, false);
5774
5775 x86_cpu_list_feature_names(xc->filtered_features, tail);
5776
5777 object_unref(OBJECT(xc));
5778}
5779
ee465a3e
EH		 5780static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
5781{
5782 ObjectClass *oc = data;
5783 X86CPUClass *cc = X86_CPU_CLASS(oc);
5784 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 5785 CpuDefinitionInfo *info;
5786
5787 info = g_malloc0(sizeof(*info));
5788 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 5789 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
5790 info->has_unavailable_features = true;
8ed877b7 5791 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 5792 info->migration_safe = cc->migration_safe;
5793 info->has_migration_safe = true;
5adbed30 5794 info->q_static = cc->static_model;
61ad65d0
RH		 5795 if (cc->model && cc->model->cpudef->deprecation_note) {
5796 info->deprecated = true;
5797 } else {
5798 info->deprecated = false;
5799 }
0788a56b
EH		 5800 /*
5801 * Old machine types won't report aliases, so that alias translation
5802 * doesn't break compatibility with previous QEMU versions.
5803 */
5804 if (default_cpu_version != CPU_VERSION_LEGACY) {
5805 info->alias_of = x86_cpu_class_get_alias_of(cc);
0788a56b 5806 }
ee465a3e 5807
54aa3de7 5808 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 5809}
5810
25a9d6ca 5811CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 5812{
5813 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 5814 GSList *list = get_sorted_cpu_model_list();
5815 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5816 g_slist_free(list);
e3966126
AL		 5817 return cpu_list;
5818}
5819
390dbc6e
PMD		 5820#endif /* !CONFIG_USER_ONLY */
5821
58f7db26
PB		 5822uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5823 bool migratable_only)
27418adf
EH		 5824{
5825 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 5826 uint64_t r = 0;
27418adf 5827
fefb41bf 5828 if (kvm_enabled()) {
07585923
RH		 5829 switch (wi->type) {
5830 case CPUID_FEATURE_WORD:
5831 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5832 wi->cpuid.ecx,
5833 wi->cpuid.reg);
5834 break;
5835 case MSR_FEATURE_WORD:
d86f9636
RH		 5836 r = kvm_arch_get_supported_msr_feature(kvm_state,
5837 wi->msr.index);
07585923
RH		 5838 break;
5839 }
d6dcc558 5840 } else if (hvf_enabled()) {
07585923
RH		 5841 if (wi->type != CPUID_FEATURE_WORD) {
5842 return 0;
5843 }
5844 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5845 wi->cpuid.ecx,
5846 wi->cpuid.reg);
fefb41bf 5847 } else if (tcg_enabled()) {
84f1b92f 5848 r = wi->tcg_features;
fefb41bf
EH		 5849 } else {
5850 return ~0;
5851 }
5ea9e9e2
PB		 5852#ifndef TARGET_X86_64
5853 if (w == FEAT_8000_0001_EDX) {
40a205da
PB		 5854 /*
5855 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no
5856 * way for userspace to get out of its 32-bit jail, we can leave
5857 * the LM bit set.
5858 */
5859 uint32_t unavail = tcg_enabled()
5860 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES
5861 : CPUID_EXT2_LM;
5862 r &= ~unavail;
5ea9e9e2
PB		 5863 }
5864#endif
84f1b92f
EH		 5865 if (migratable_only) {
5866 r &= x86_cpu_get_migratable_flags(w);
5867 }
5868 return r;
27418adf
EH		 5869}
5870
d19d6ffa
PB		 5871static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
5872 uint32_t *eax, uint32_t *ebx,
5873 uint32_t *ecx, uint32_t *edx)
5874{
5875 if (kvm_enabled()) {
5876 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX);
5877 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX);
5878 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX);
5879 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX);
5880 } else if (hvf_enabled()) {
5881 *eax = hvf_get_supported_cpuid(func, index, R_EAX);
5882 *ebx = hvf_get_supported_cpuid(func, index, R_EBX);
5883 *ecx = hvf_get_supported_cpuid(func, index, R_ECX);
5884 *edx = hvf_get_supported_cpuid(func, index, R_EDX);
5885 } else {
5886 *eax = 0;
5887 *ebx = 0;
5888 *ecx = 0;
5889 *edx = 0;
5890 }
5891}
5892
798d8ec0
PB		 5893static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index,
5894 uint32_t *eax, uint32_t *ebx,
5895 uint32_t *ecx, uint32_t *edx)
5896{
5897 uint32_t level, unused;
5898
5899 /* Only return valid host leaves. */
5900 switch (func) {
5901 case 2:
5902 case 4:
5903 host_cpuid(0, 0, &level, &unused, &unused, &unused);
5904 break;
5905 case 0x80000005:
5906 case 0x80000006:
5907 case 0x8000001d:
5908 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused);
5909 break;
5910 default:
5911 return;
5912 }
5913
5914 if (func > level) {
5915 *eax = 0;
5916 *ebx = 0;
5917 *ecx = 0;
5918 *edx = 0;
5919 } else {
5920 host_cpuid(func, index, eax, ebx, ecx, edx);
5921 }
5922}
5923
5b8978d8
CF		 5924/*
5925 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5926 */
f5cc5a5c 5927void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5928{
5929 PropValue *pv;
5930 for (pv = props; pv->prop; pv++) {
5931 if (!pv->value) {
5932 continue;
5933 }
5325cc34 5934 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5935 &error_abort);
5936 }
5937}
5938
5b8978d8
CF		 5939/*
5940 * Apply properties for the CPU model version specified in model.
5941 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5942 */
5943
dcafd1ef
EH		 5944static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5945{
5946 const X86CPUVersionDefinition *vdef;
5947 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5948
5949 if (version == CPU_VERSION_LEGACY) {
5950 return;
5951 }
5952
5953 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5954 PropValue *p;
5955
5956 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5957 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5958 &error_abort);
5959 }
5960
5961 if (vdef->version == version) {
5962 break;
5963 }
5964 }
5965
5966 /*
5967 * If we reached the end of the list, version number was invalid
5968 */
5969 assert(vdef->version == version);
5970}
5971
cca0a000
MR		 5972static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
5973 X86CPUModel *model)
5974{
5975 const X86CPUVersionDefinition *vdef;
5976 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5977 const CPUCaches *cache_info = model->cpudef->cache_info;
5978
5979 if (version == CPU_VERSION_LEGACY) {
5980 return cache_info;
5981 }
5982
5983 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5984 if (vdef->cache_info) {
5985 cache_info = vdef->cache_info;
5986 }
5987
5988 if (vdef->version == version) {
5989 break;
5990 }
5991 }
5992
5993 assert(vdef->version == version);
5994 return cache_info;
5995}
5996
5b8978d8
CF		 5997/*
5998 * Load data from X86CPUDefinition into a X86CPU object.
5999 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 6000 */
49e2fa85 6001static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 6002{
e11fd689 6003 const X86CPUDefinition *def = model->cpudef;
61dcd775 6004 CPUX86State *env = &cpu->env;
e1c224b4 6005 FeatureWord w;
c6dc6f63 6006
f99fd7ca
EH		 6007 /*NOTE: any property set by this function should be returned by
6008 * x86_cpu_static_props(), so static expansion of
6009 * query-cpu-model-expansion is always complete.
6010 */
6011
c39c0edf 6012 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 6013 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 6014 &error_abort);
5325cc34 6015 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 6016 &error_abort);
6017
5325cc34
MA		 6018 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
6019 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
6020 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 6021 &error_abort);
5325cc34 6022 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 6023 &error_abort);
e1c224b4
EH		 6024 for (w = 0; w < FEATURE_WORDS; w++) {
6025 env->features[w] = def->features[w];
6026 }
82beb536 6027
a9f27ea9 6028 /* legacy-cache defaults to 'off' if CPU model provides cache info */
cca0a000 6029 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model);
ab8f992e 6030
82beb536 6031 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 6032
6033 /* sysenter isn't supported in compatibility mode on AMD,
6034 * syscall isn't supported in compatibility mode on Intel.
6035 * Normally we advertise the actual CPU vendor, but you can
6036 * override this using the 'vendor' property if you want to use
6037 * KVM's sysenter/syscall emulation in compatibility mode and
6038 * when doing cross vendor migration
6039 */
7c08db30 6040
f5cc5a5c
CF		 6041 /*
6042 * vendor property is set here but then overloaded with the
6043 * host cpu vendor for KVM and HVF.
6044 */
6045 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 6046
dcafd1ef 6047 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 6048
6049 /*
6050 * Properties in versioned CPU model are not user specified features.
6051 * We can simply clear env->user_features here since it will be filled later
6052 * in x86_cpu_expand_features() based on plus_features and minus_features.
6053 */
6054 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 6055}
6056
a6506838 6057static const gchar *x86_gdb_arch_name(CPUState *cs)
00fcd100
AB		 6058{
6059#ifdef TARGET_X86_64
a6506838 6060 return "i386:x86-64";
00fcd100 6061#else
a6506838 6062 return "i386";
00fcd100
AB		 6063#endif
6064}
6065
d940ee9b
EH		 6066static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
6067{
dcafd1ef 6068 X86CPUModel *model = data;
d940ee9b 6069 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 6070 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 6071
dcafd1ef 6072 xcc->model = model;
bd72159d 6073 xcc->migration_safe = true;
61ad65d0 6074 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 6075}
6076
dcafd1ef 6077static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 6078{
88703ce2 6079 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 6080 TypeInfo ti = {
6081 .name = typename,
6082 .parent = TYPE_X86_CPU,
6083 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 6084 .class_data = model,
d940ee9b
EH		 6085 };
6086
dcafd1ef 6087 type_register(&ti);
dcafd1ef
EH		 6088}
6089
5b8978d8
CF		 6090
6091/*
6092 * register builtin_x86_defs;
6093 * "max", "base" and subclasses ("host") are not registered here.
6094 * See x86_cpu_register_types for all model registrations.
6095 */
e11fd689 6096static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 6097{
6098 X86CPUModel *m;
6099 const X86CPUVersionDefinition *vdef;
dcafd1ef 6100
2a923a29
EH		 6101 /* AMD aliases are handled at runtime based on CPUID vendor, so
6102 * they shouldn't be set on the CPU model table.
6103 */
6104 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 6105 /* catch mistakes instead of silently truncating model_id when too long */
6106 assert(def->model_id && strlen(def->model_id) <= 48);
6107
dcafd1ef
EH		 6108 /* Unversioned model: */
6109 m = g_new0(X86CPUModel, 1);
6110 m->cpudef = def;
0788a56b
EH		 6111 m->version = CPU_VERSION_AUTO;
6112 m->is_alias = true;
dcafd1ef
EH		 6113 x86_register_cpu_model_type(def->name, m);
6114
6115 /* Versioned models: */
6116
6117 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
88703ce2
EH		 6118 g_autofree char *name =
6119 x86_cpu_versioned_model_name(def, vdef->version);
637123a2
PB		 6120
6121 m = g_new0(X86CPUModel, 1);
dcafd1ef
EH		 6122 m->cpudef = def;
6123 m->version = vdef->version;
c63938df 6124 m->note = vdef->note;
dcafd1ef 6125 x86_register_cpu_model_type(name, m);
53db89d9
EH		 6126
6127 if (vdef->alias) {
6128 X86CPUModel *am = g_new0(X86CPUModel, 1);
6129 am->cpudef = def;
6130 am->version = vdef->version;
0788a56b 6131 am->is_alias = true;
53db89d9
EH		 6132 x86_register_cpu_model_type(vdef->alias, am);
6133 }
dcafd1ef 6134 }
2a923a29 6135
d940ee9b
EH		 6136}
6137
97afb47e
LL		 6138uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
6139{
6140 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
6141 return 57; /* 57 bits virtual */
6142 } else {
6143 return 48; /* 48 bits virtual */
6144 }
6145}
6146
c6dc6f63
AP		 6147void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
6148 uint32_t *eax, uint32_t *ebx,
6149 uint32_t *ecx, uint32_t *edx)
6150{
6aa9e42f
RH		 6151 X86CPU *cpu = env_archcpu(env);
6152 CPUState *cs = env_cpu(env);
d65af288 6153 uint32_t die_offset;
4ed3d478 6154 uint32_t limit;
1ce36bfe 6155 uint32_t signature[3];
f20dec0b
BM		 6156 X86CPUTopoInfo topo_info;
6157
6158 topo_info.dies_per_pkg = env->nr_dies;
958ac3c4 6159 topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
f20dec0b 6160 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 6161
4ed3d478
DB		 6162 /* Calculate & apply limits for different index ranges */
6163 if (index >= 0xC0000000) {
6164 limit = env->cpuid_xlevel2;
6165 } else if (index >= 0x80000000) {
6166 limit = env->cpuid_xlevel;
1ce36bfe
DB		 6167 } else if (index >= 0x40000000) {
6168 limit = 0x40000001;
c6dc6f63 6169 } else {
4ed3d478
DB		 6170 limit = env->cpuid_level;
6171 }
6172
6173 if (index > limit) {
6174 /* Intel documentation states that invalid EAX input will
6175 * return the same information as EAX=cpuid_level
6176 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
6177 */
6178 index = env->cpuid_level;
c6dc6f63
AP		 6179 }
6180
6181 switch(index) {
6182 case 0:
6183 *eax = env->cpuid_level;
5eb2f7a4
EH		 6184 *ebx = env->cpuid_vendor1;
6185 *edx = env->cpuid_vendor2;
6186 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 6187 break;
6188 case 1:
6189 *eax = env->cpuid_version;
7e72a45c
EH		 6190 *ebx = (cpu->apic_id << 24) |
6191 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 6192 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 6193 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
6194 *ecx |= CPUID_EXT_OSXSAVE;
6195 }
0514ef2f 6196 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 6197 if (cs->nr_cores * cs->nr_threads > 1) {
6198 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 6199 *edx |= CPUID_HT;
c6dc6f63 6200 }
ea39f9b6
LX		 6201 if (!cpu->enable_pmu) {
6202 *ecx &= ~CPUID_EXT_PDCM;
6203 }
c6dc6f63
AP		 6204 break;
6205 case 2:
6206 /* cache info: needed for Pentium Pro compatibility */
787aaf57 6207 if (cpu->cache_info_passthrough) {
798d8ec0 6208 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57 6209 break;
a7a0da84
MR		 6210 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
6211 *eax = *ebx = *ecx = *edx = 0;
6212 break;
787aaf57 6213 }
5e891bf8 6214 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 6215 *ebx = 0;
14c985cf
LM		 6216 if (!cpu->enable_l3_cache) {
6217 *ecx = 0;
6218 } else {
a9f27ea9 6219 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 6220 }
a9f27ea9
EH		 6221 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
6222 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
6223 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 6224 break;
6225 case 4:
6226 /* cache info: needed for Core compatibility */
787aaf57 6227 if (cpu->cache_info_passthrough) {
798d8ec0 6228 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
d7caf13b
IM		 6229 /*
6230 * QEMU has its own number of cores/logical cpus,
6231 * set 24..14, 31..26 bit to configured values
6232 */
6233 if (*eax & 31) {
6234 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
958ac3c4 6235 int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
d7caf13b
IM		 6236 if (cs->nr_cores > 1) {
6237 *eax &= ~0xFC000000;
6238 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
6239 }
6240 if (host_vcpus_per_cache > vcpus_per_socket) {
6241 *eax &= ~0x3FFC000;
6242 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
6243 }
7e3482f8 6244 }
a7a0da84
MR		 6245 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
6246 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 6247 } else {
2f7a21c4 6248 *eax = 0;
76c2975a 6249 switch (count) {
c6dc6f63 6250 case 0: /* L1 dcache info */
a9f27ea9
EH		 6251 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
6252 1, cs->nr_cores,
7e3482f8 6253 eax, ebx, ecx, edx);
c6dc6f63
AP		 6254 break;
6255 case 1: /* L1 icache info */
a9f27ea9
EH		 6256 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
6257 1, cs->nr_cores,
7e3482f8 6258 eax, ebx, ecx, edx);
c6dc6f63
AP		 6259 break;
6260 case 2: /* L2 cache info */
a9f27ea9
EH		 6261 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
6262 cs->nr_threads, cs->nr_cores,
7e3482f8 6263 eax, ebx, ecx, edx);
c6dc6f63 6264 break;
14c985cf 6265 case 3: /* L3 cache info */
f20dec0b 6266 die_offset = apicid_die_offset(&topo_info);
7e3482f8 6267 if (cpu->enable_l3_cache) {
a9f27ea9 6268 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 6269 (1 << die_offset), cs->nr_cores,
7e3482f8 6270 eax, ebx, ecx, edx);
14c985cf
LM		 6271 break;
6272 }
7e3482f8 6273 /* fall through */
c6dc6f63 6274 default: /* end of info */
7e3482f8 6275 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 6276 break;
76c2975a
PB		 6277 }
6278 }
c6dc6f63
AP		 6279 break;
6280 case 5:
2266d443
MT		 6281 /* MONITOR/MWAIT Leaf */
6282 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
6283 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
6284 *ecx = cpu->mwait.ecx; /* flags */
6285 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 6286 break;
6287 case 6:
6288 /* Thermal and Power Leaf */
28b8e4d0 6289 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 6290 *ebx = 0;
6291 *ecx = 0;
6292 *edx = 0;
6293 break;
f7911686 6294 case 7:
13526728
EH		 6295 /* Structured Extended Feature Flags Enumeration Leaf */
6296 if (count == 0) {
d0474024
PMD		 6297 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused;
6298
80db491d
JL		 6299 /* Maximum ECX value for sub-leaves */
6300 *eax = env->cpuid_level_func7;
0514ef2f 6301 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 6302 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 6303 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
6304 *ecx |= CPUID_7_0_ECX_OSPKE;
6305 }
95ea69fb 6306 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 6307
6308 /*
6309 * SGX cannot be emulated in software. If hardware does not
6310 * support enabling SGX and/or SGX flexible launch control,
6311 * then we need to update the VM's CPUID values accordingly.
6312 */
d0474024
PMD		 6313 x86_cpu_get_supported_cpuid(0x7, 0,
6314 &eax_0_unused, &ebx_0,
6315 &ecx_0, &edx_0_unused);
6316 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) {
1dec2e1f
SC		 6317 *ebx &= ~CPUID_7_0_EBX_SGX;
6318 }
6319
d0474024
PMD		 6320 if ((*ecx & CPUID_7_0_ECX_SGX_LC)
6321 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) {
1dec2e1f
SC		 6322 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
6323 }
80db491d
JL		 6324 } else if (count == 1) {
6325 *eax = env->features[FEAT_7_1_EAX];
eaaa197d 6326 *edx = env->features[FEAT_7_1_EDX];
80db491d
JL		 6327 *ebx = 0;
6328 *ecx = 0;
9dd8b710
TS		 6329 } else if (count == 2) {
6330 *edx = env->features[FEAT_7_2_EDX];
6331 *eax = 0;
6332 *ebx = 0;
6333 *ecx = 0;
f7911686
YW		 6334 } else {
6335 *eax = 0;
6336 *ebx = 0;
6337 *ecx = 0;
6338 *edx = 0;
6339 }
6340 break;
c6dc6f63
AP		 6341 case 9:
6342 /* Direct Cache Access Information Leaf */
6343 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
6344 *ebx = 0;
6345 *ecx = 0;
6346 *edx = 0;
6347 break;
6348 case 0xA:
6349 /* Architectural Performance Monitoring Leaf */
da472f94 6350 if (cpu->enable_pmu) {
d19d6ffa 6351 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx);
a0fa8208
GN		 6352 } else {
6353 *eax = 0;
6354 *ebx = 0;
6355 *ecx = 0;
6356 *edx = 0;
6357 }
c6dc6f63 6358 break;
5232d00a
RK		 6359 case 0xB:
6360 /* Extended Topology Enumeration Leaf */
6361 if (!cpu->enable_cpuid_0xb) {
6362 *eax = *ebx = *ecx = *edx = 0;
6363 break;
6364 }
6365
6366 *ecx = count & 0xff;
6367 *edx = cpu->apic_id;
6368
6369 switch (count) {
6370 case 0:
f20dec0b 6371 *eax = apicid_core_offset(&topo_info);
eab60fb9 6372 *ebx = cs->nr_threads;
5232d00a
RK		 6373 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
6374 break;
6375 case 1:
fb49865d 6376 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 6377 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 6378 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
6379 break;
6380 default:
6381 *eax = 0;
6382 *ebx = 0;
6383 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
6384 }
6385
a94e1428
LX		 6386 assert(!(*eax & ~0x1f));
6387 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
6388 break;
c3c67679 6389 case 0x1C:
da472f94 6390 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
c3c67679
YW		 6391 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
6392 *edx = 0;
6393 }
6394 break;
a94e1428
LX		 6395 case 0x1F:
6396 /* V2 Extended Topology Enumeration Leaf */
6397 if (env->nr_dies < 2) {
6398 *eax = *ebx = *ecx = *edx = 0;
6399 break;
6400 }
6401
6402 *ecx = count & 0xff;
6403 *edx = cpu->apic_id;
6404 switch (count) {
6405 case 0:
f20dec0b 6406 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 6407 *ebx = cs->nr_threads;
6408 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
6409 break;
6410 case 1:
f20dec0b 6411 *eax = apicid_die_offset(&topo_info);
958ac3c4 6412 *ebx = topo_info.cores_per_die * topo_info.threads_per_core;
a94e1428
LX		 6413 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
6414 break;
6415 case 2:
fb49865d 6416 *eax = apicid_pkg_offset(&topo_info);
958ac3c4 6417 *ebx = cs->nr_cores * cs->nr_threads;
a94e1428
LX		 6418 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
6419 break;
6420 default:
6421 *eax = 0;
6422 *ebx = 0;
6423 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
6424 }
5232d00a
RK		 6425 assert(!(*eax & ~0x1f));
6426 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
6427 break;
2560f19f 6428 case 0xD: {
51e49430 6429 /* Processor Extended State */
2560f19f
PB		 6430 *eax = 0;
6431 *ebx = 0;
6432 *ecx = 0;
6433 *edx = 0;
19dc85db 6434 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 6435 break;
6436 }
4928cd6d 6437
2560f19f 6438 if (count == 0) {
301e9067
YW		 6439 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false);
6440 *eax = env->features[FEAT_XSAVE_XCR0_LO];
6441 *edx = env->features[FEAT_XSAVE_XCR0_HI];
76ecd7a5
BS		 6442 /*
6443 * The initial value of xcr0 and ebx == 0, On host without kvm
6444 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
6445 * even through guest update xcr0, this will crash some legacy guest
bad5cfcd 6446 * (e.g., CentOS 6), So set ebx == ecx to workaround it.
76ecd7a5 6447 */
301e9067 6448 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false);
2560f19f 6449 } else if (count == 1) {
301e9067
YW		 6450 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) |
6451 x86_cpu_xsave_xss_components(cpu);
6452
0bb0b2d2 6453 *eax = env->features[FEAT_XSAVE];
301e9067
YW		 6454 *ebx = xsave_area_size(xstate, true);
6455 *ecx = env->features[FEAT_XSAVE_XSS_LO];
6456 *edx = env->features[FEAT_XSAVE_XSS_HI];
c3c67679
YW		 6457 if (kvm_enabled() && cpu->enable_pmu &&
6458 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
6459 (*eax & CPUID_XSAVE_XSAVES)) {
6460 *ecx |= XSTATE_ARCH_LBR_MASK;
6461 } else {
6462 *ecx &= ~XSTATE_ARCH_LBR_MASK;
6463 }
da472f94
PMD		 6464 } else if (count == 0xf && cpu->enable_pmu
6465 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
c3c67679 6466 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
f4f1110e 6467 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
301e9067
YW		 6468 const ExtSaveArea *esa = &x86_ext_save_areas[count];
6469
6470 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) {
33f373d7
LJ		 6471 *eax = esa->size;
6472 *ebx = esa->offset;
0f17f6b3
JL		 6473 *ecx = esa->ecx &
6474 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
301e9067
YW		 6475 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) {
6476 *eax = esa->size;
6477 *ebx = 0;
6478 *ecx = 1;
2560f19f 6479 }
51e49430
SY		 6480 }
6481 break;
2560f19f 6482 }
1dec2e1f
SC		 6483 case 0x12:
6484#ifndef CONFIG_USER_ONLY
6485 if (!kvm_enabled() ||
6486 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
6487 *eax = *ebx = *ecx = *edx = 0;
6488 break;
6489 }
6490
6491 /*
6492 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
6493 * the EPC properties, e.g. confidentiality and integrity, from the
6494 * host's first EPC section, i.e. assume there is one EPC section or
6495 * that all EPC sections have the same security properties.
6496 */
6497 if (count > 1) {
6498 uint64_t epc_addr, epc_size;
6499
6500 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
6501 *eax = *ebx = *ecx = *edx = 0;
6502 break;
6503 }
6504 host_cpuid(index, 2, eax, ebx, ecx, edx);
6505 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
6506 *ebx = (uint32_t)(epc_addr >> 32);
6507 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
6508 *edx = (uint32_t)(epc_size >> 32);
6509 break;
6510 }
6511
6512 /*
6513 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
6514 * and KVM, i.e. QEMU cannot emulate features to override what KVM
6515 * supports. Features can be further restricted by userspace, but not
6516 * made more permissive.
6517 */
b0f3184e 6518 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx);
1dec2e1f
SC		 6519
6520 if (count == 0) {
6521 *eax &= env->features[FEAT_SGX_12_0_EAX];
6522 *ebx &= env->features[FEAT_SGX_12_0_EBX];
6523 } else {
6524 *eax &= env->features[FEAT_SGX_12_1_EAX];
6525 *ebx &= 0; /* ebx reserve */
72497cff
YZ		 6526 *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
6527 *edx &= env->features[FEAT_XSAVE_XCR0_HI];
1dec2e1f
SC		 6528
6529 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
6530 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
6531
6532 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 6533 if ((*eax & (1U << 4)) &&
6534 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
6535 *eax &= ~(1U << 4);
6536 }
1dec2e1f
SC		 6537 }
6538#endif
6539 break;
e37a5c7f
CP		 6540 case 0x14: {
6541 /* Intel Processor Trace Enumeration */
6542 *eax = 0;
6543 *ebx = 0;
6544 *ecx = 0;
6545 *edx = 0;
6546 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
6547 !kvm_enabled()) {
6548 break;
6549 }
6550
028ade14
PB		 6551 /*
6552 * If these are changed, they should stay in sync with
6553 * x86_cpu_filter_features().
6554 */
e37a5c7f
CP		 6555 if (count == 0) {
6556 *eax = INTEL_PT_MAX_SUBLEAF;
6557 *ebx = INTEL_PT_MINIMAL_EBX;
6558 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 6559 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
6560 *ecx |= CPUID_14_0_ECX_LIP;
6561 }
e37a5c7f
CP		 6562 } else if (count == 1) {
6563 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
6564 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
6565 }
6566 break;
6567 }
f21a4817 6568 case 0x1D: {
7eb061b0 6569 /* AMX TILE, for now hardcoded for Sapphire Rapids*/
f21a4817
JL		 6570 *eax = 0;
6571 *ebx = 0;
6572 *ecx = 0;
6573 *edx = 0;
6574 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6575 break;
6576 }
6577
6578 if (count == 0) {
6579 /* Highest numbered palette subleaf */
6580 *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
6581 } else if (count == 1) {
6582 *eax = INTEL_AMX_TOTAL_TILE_BYTES |
6583 (INTEL_AMX_BYTES_PER_TILE << 16);
6584 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
6585 *ecx = INTEL_AMX_TILE_MAX_ROWS;
6586 }
6587 break;
6588 }
6589 case 0x1E: {
7eb061b0 6590 /* AMX TMUL, for now hardcoded for Sapphire Rapids */
f21a4817
JL		 6591 *eax = 0;
6592 *ebx = 0;
6593 *ecx = 0;
6594 *edx = 0;
6595 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6596 break;
6597 }
6598
6599 if (count == 0) {
6600 /* Highest numbered palette subleaf */
6601 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
6602 }
6603 break;
6604 }
1ce36bfe
DB		 6605 case 0x40000000:
6606 /*
6607 * CPUID code in kvm_arch_init_vcpu() ignores stuff
6608 * set here, but we restrict to TCG none the less.
6609 */
6610 if (tcg_enabled() && cpu->expose_tcg) {
6611 memcpy(signature, "TCGTCGTCGTCG", 12);
6612 *eax = 0x40000001;
6613 *ebx = signature[0];
6614 *ecx = signature[1];
6615 *edx = signature[2];
6616 } else {
6617 *eax = 0;
6618 *ebx = 0;
6619 *ecx = 0;
6620 *edx = 0;
6621 }
6622 break;
6623 case 0x40000001:
6624 *eax = 0;
6625 *ebx = 0;
6626 *ecx = 0;
6627 *edx = 0;
6628 break;
c6dc6f63
AP		 6629 case 0x80000000:
6630 *eax = env->cpuid_xlevel;
6631 *ebx = env->cpuid_vendor1;
6632 *edx = env->cpuid_vendor2;
6633 *ecx = env->cpuid_vendor3;
6634 break;
6635 case 0x80000001:
6636 *eax = env->cpuid_version;
6637 *ebx = 0;
0514ef2f
EH		 6638 *ecx = env->features[FEAT_8000_0001_ECX];
6639 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 6640
6641 /* The Linux kernel checks for the CMPLegacy bit and
6642 * discards multiple thread information if it is set.
cb8d4c8f 6643 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 6644 */
ce3960eb 6645 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 6646 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
6647 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
6648 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 6649 *ecx |= 1 << 1; /* CmpLegacy bit */
6650 }
6651 }
fd5dcb1c
PB		 6652 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 &&
6653 !(env->hflags & HF_LMA_MASK)) {
6654 *edx &= ~CPUID_EXT2_SYSCALL;
6655 }
c6dc6f63
AP		 6656 break;
6657 case 0x80000002:
6658 case 0x80000003:
6659 case 0x80000004:
6660 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
6661 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
6662 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
6663 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
6664 break;
6665 case 0x80000005:
6666 /* cache info (L1 cache) */
787aaf57 6667 if (cpu->cache_info_passthrough) {
798d8ec0 6668 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6669 break;
6670 }
78ee6bd0 6671 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 6672 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 6673 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 6674 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6675 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
6676 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 6677 break;
6678 case 0x80000006:
6679 /* cache info (L2 cache) */
787aaf57 6680 if (cpu->cache_info_passthrough) {
798d8ec0 6681 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6682 break;
6683 }
78ee6bd0
PMD		 6684 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
6685 (L2_DTLB_2M_ENTRIES << 16) |
6686 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 6687 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 6688 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
6689 (L2_DTLB_4K_ENTRIES << 16) |
6690 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 6691 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6692 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
6693 cpu->enable_l3_cache ?
6694 env->cache_info_amd.l3_cache : NULL,
6695 ecx, edx);
c6dc6f63 6696 break;
303752a9
MT		 6697 case 0x80000007:
6698 *eax = 0;
6699 *ebx = 0;
6700 *ecx = 0;
6701 *edx = env->features[FEAT_8000_0007_EDX];
6702 break;
c6dc6f63
AP		 6703 case 0x80000008:
6704 /* virtual & phys address size in low 2 bytes. */
97afb47e 6705 *eax = cpu->phys_bits;
0514ef2f 6706 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 6707 /* 64 bit processor */
97afb47e 6708 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
513ba32d 6709 *eax |= (cpu->guest_phys_bits << 16);
c6dc6f63 6710 }
1b3420e1 6711 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 6712 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 6713 /*
6714 * Bits 15:12 is "The number of bits in the initial
6715 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 6716 * thread ID within a package".
cac9edfc
BM		 6717 * Bits 7:0 is "The number of threads in the package is NC+1"
6718 */
fb49865d 6719 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 6720 ((cs->nr_cores * cs->nr_threads) - 1);
6721 } else {
6722 *ecx = 0;
c6dc6f63 6723 }
cac9edfc 6724 *edx = 0;
c6dc6f63
AP		 6725 break;
6726 case 0x8000000A:
0514ef2f 6727 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 6728 *eax = 0x00000001; /* SVM Revision */
6729 *ebx = 0x00000010; /* nr of ASIDs */
6730 *ecx = 0;
0514ef2f 6731 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 6732 } else {
6733 *eax = 0;
6734 *ebx = 0;
6735 *ecx = 0;
6736 *edx = 0;
6737 }
c6dc6f63 6738 break;
8f4202fb
BM		 6739 case 0x8000001D:
6740 *eax = 0;
a4e0b436 6741 if (cpu->cache_info_passthrough) {
798d8ec0 6742 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
a4e0b436
SL		 6743 break;
6744 }
8f4202fb
BM		 6745 switch (count) {
6746 case 0: /* L1 dcache info */
2f084d1e
BM		 6747 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
6748 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6749 break;
6750 case 1: /* L1 icache info */
2f084d1e
BM		 6751 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
6752 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6753 break;
6754 case 2: /* L2 cache info */
2f084d1e
BM		 6755 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
6756 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6757 break;
6758 case 3: /* L3 cache info */
2f084d1e
BM		 6759 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
6760 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6761 break;
6762 default: /* end of info */
6763 *eax = *ebx = *ecx = *edx = 0;
6764 break;
6765 }
6766 break;
ed78467a 6767 case 0x8000001E:
35ac5dfb
BM		 6768 if (cpu->core_id <= 255) {
6769 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
6770 } else {
6771 *eax = 0;
6772 *ebx = 0;
6773 *ecx = 0;
6774 *edx = 0;
6775 }
ed78467a 6776 break;
b3baa152
BW		 6777 case 0xC0000000:
6778 *eax = env->cpuid_xlevel2;
6779 *ebx = 0;
6780 *ecx = 0;
6781 *edx = 0;
6782 break;
6783 case 0xC0000001:
6784 /* Support for VIA CPU's CPUID instruction */
6785 *eax = env->cpuid_version;
6786 *ebx = 0;
6787 *ecx = 0;
0514ef2f 6788 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 6789 break;
6790 case 0xC0000002:
6791 case 0xC0000003:
6792 case 0xC0000004:
6793 /* Reserved for the future, and now filled with zero */
6794 *eax = 0;
6795 *ebx = 0;
6796 *ecx = 0;
6797 *edx = 0;
6798 break;
6cb8f2a6 6799 case 0x8000001F:
02eacf31
PMD		 6800 *eax = *ebx = *ecx = *edx = 0;
6801 if (sev_enabled()) {
6802 *eax = 0x2;
6803 *eax |= sev_es_enabled() ? 0x8 : 0;
fb6bbafc
TL		 6804 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
6805 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
02eacf31 6806 }
6cb8f2a6 6807 break;
b70eec31
BM		 6808 case 0x80000021:
6809 *eax = env->features[FEAT_8000_0021_EAX];
6810 *ebx = *ecx = *edx = 0;
6811 break;
c6dc6f63
AP		 6812 default:
6813 /* reserved values: zero */
6814 *eax = 0;
6815 *ebx = 0;
6816 *ecx = 0;
6817 *edx = 0;
6818 break;
6819 }
6820}
5fd2087a 6821
db888065
SC		 6822static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
6823{
6824#ifndef CONFIG_USER_ONLY
6825 /* Those default values are defined in Skylake HW */
6826 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
6827 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
6828 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
6829 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
6830#endif
6831}
6832
ad80e367 6833static void x86_cpu_reset_hold(Object *obj, ResetType type)
5fd2087a 6834{
348802b5
PMD		 6835 CPUState *cs = CPU(obj);
6836 X86CPU *cpu = X86_CPU(cs);
6837 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
5fd2087a 6838 CPUX86State *env = &cpu->env;
a114d25d
RH		 6839 target_ulong cr4;
6840 uint64_t xcr0;
c1958aea
AF		 6841 int i;
6842
e86787d3 6843 if (xcc->parent_phases.hold) {
ad80e367 6844 xcc->parent_phases.hold(obj, type);
e86787d3 6845 }
5fd2087a 6846
5e992a8e 6847 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 6848
c1958aea
AF		 6849 env->old_exception = -1;
6850
6851 /* init to reset state */
e3126a5c 6852 env->int_ctl = 0;
c1958aea 6853 env->hflags2 |= HF2_GIF_MASK;
b67e2796 6854 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 6855 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 6856
6857 cpu_x86_update_cr0(env, 0x60000010);
6858 env->a20_mask = ~0x0;
6859 env->smbase = 0x30000;
e13713db 6860 env->msr_smi_count = 0;
c1958aea
AF		 6861
6862 env->idt.limit = 0xffff;
6863 env->gdt.limit = 0xffff;
6864 env->ldt.limit = 0xffff;
6865 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
6866 env->tr.limit = 0xffff;
6867 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
6868
6869 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
6870 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
6871 DESC_R_MASK | DESC_A_MASK);
6872 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
6873 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6874 DESC_A_MASK);
6875 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
6876 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6877 DESC_A_MASK);
6878 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6879 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6880 DESC_A_MASK);
6881 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6882 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6883 DESC_A_MASK);
6884 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6885 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6886 DESC_A_MASK);
6887
6888 env->eip = 0xfff0;
6889 env->regs[R_EDX] = env->cpuid_version;
6890
6891 env->eflags = 0x2;
6892
6893 /* FPU init */
6894 for (i = 0; i < 8; i++) {
6895 env->fptags[i] = 1;
6896 }
5bde1407 6897 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 6898
6899 env->mxcsr = 0x1f80;
a114d25d
RH		 6900 /* All units are in INIT state. */
6901 env->xstate_bv = 0;
c1958aea
AF		 6902
6903 env->pat = 0x0007040600070406ULL;
5286c366
PB		 6904
6905 if (kvm_enabled()) {
6906 /*
6907 * KVM handles TSC = 0 specially and thinks we are hot-plugging
6908 * a new CPU, use 1 instead to force a reset.
6909 */
6910 if (env->tsc != 0) {
6911 env->tsc = 1;
6912 }
6913 } else {
6914 env->tsc = 0;
6915 }
6916
c1958aea 6917 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 6918 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6919 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6920 }
c1958aea
AF		 6921
6922 memset(env->dr, 0, sizeof(env->dr));
6923 env->dr[6] = DR6_FIXED_1;
6924 env->dr[7] = DR7_FIXED_1;
348802b5
PMD		 6925 cpu_breakpoint_remove_all(cs, BP_CPU);
6926 cpu_watchpoint_remove_all(cs, BP_CPU);
dd673288 6927
a114d25d 6928 cr4 = 0;
cfc3b074 6929 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 6930
6931#ifdef CONFIG_USER_ONLY
6932 /* Enable all the features for user-mode. */
6933 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 6934 xcr0 |= XSTATE_SSE_MASK;
a114d25d 6935 }
0f70ed47
PB		 6936 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6937 const ExtSaveArea *esa = &x86_ext_save_areas[i];
301e9067
YW		 6938 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
6939 continue;
6940 }
9646f492 6941 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 6942 xcr0 |= 1ull << i;
6943 }
a114d25d 6944 }
0f70ed47 6945
a114d25d
RH		 6946 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6947 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6948 }
07929f2a
RH		 6949 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6950 cr4 |= CR4_FSGSBASE_MASK;
6951 }
a114d25d
RH		 6952#endif
6953
6954 env->xcr0 = xcr0;
6955 cpu_x86_update_cr4(env, cr4);
0522604b 6956
9db2efd9
AW		 6957 /*
6958 * SDM 11.11.5 requires:
6959 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6960 * - IA32_MTRR_PHYSMASKn.V = 0
6961 * All other bits are undefined. For simplification, zero it all.
6962 */
6963 env->mtrr_deftype = 0;
6964 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6965 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6966
b7394c83 6967 env->interrupt_injected = -1;
fd13f23b
LA		 6968 env->exception_nr = -1;
6969 env->exception_pending = 0;
6970 env->exception_injected = 0;
6971 env->exception_has_payload = false;
6972 env->exception_payload = 0;
b7394c83 6973 env->nmi_injected = false;
12f89a39 6974 env->triple_fault_pending = false;
dd673288
IM		 6975#if !defined(CONFIG_USER_ONLY)
6976 /* We hard-wire the BSP to the first CPU. */
348802b5 6977 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0);
dd673288 6978
348802b5 6979 cs->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 6980
6981 if (kvm_enabled()) {
6982 kvm_arch_reset_vcpu(cpu);
6983 }
db888065
SC		 6984
6985 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862 6986
3e4546d5 6987 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
cabf9862 6988
dd673288 6989#endif
5fd2087a
AF		 6990}
6991
ec19444a
MS		 6992void x86_cpu_after_reset(X86CPU *cpu)
6993{
6994#ifndef CONFIG_USER_ONLY
6995 if (kvm_enabled()) {
6996 kvm_arch_after_reset_vcpu(cpu);
6997 }
6998
6999 if (cpu->apic_state) {
08c4f4db 7000 device_cold_reset(cpu->apic_state);
ec19444a
MS		 7001 }
7002#endif
7003}
7004
de024815
AF		 7005static void mce_init(X86CPU *cpu)
7006{
7007 CPUX86State *cenv = &cpu->env;
7008 unsigned int bank;
7009
7010 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 7011 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 7012 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 7013 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
7014 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 7015 cenv->mcg_ctl = ~(uint64_t)0;
7016 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
7017 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
7018 }
7019 }
7020}
7021
c39c0edf
EH		 7022static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
7023{
7024 if (*min < value) {
7025 *min = value;
7026 }
7027}
7028
7029/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
7030static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
7031{
7032 CPUX86State *env = &cpu->env;
7033 FeatureWordInfo *fi = &feature_word_info[w];
07585923 7034 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 7035 uint32_t region = eax & 0xF0000000;
7036
07585923 7037 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 7038 if (!env->features[w]) {
7039 return;
7040 }
7041
7042 switch (region) {
7043 case 0x00000000:
7044 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
7045 break;
7046 case 0x80000000:
7047 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
7048 break;
7049 case 0xC0000000:
7050 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
7051 break;
7052 }
80db491d
JL		 7053
7054 if (eax == 7) {
7055 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
7056 fi->cpuid.ecx);
7057 }
c39c0edf
EH		 7058}
7059
2ca8a8be
EH		 7060/* Calculate XSAVE components based on the configured CPU feature flags */
7061static void x86_cpu_enable_xsave_components(X86CPU *cpu)
7062{
7063 CPUX86State *env = &cpu->env;
7064 int i;
96193c22 7065 uint64_t mask;
19db68ca 7066 static bool request_perm;
2ca8a8be
EH		 7067
7068 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
301e9067
YW		 7069 env->features[FEAT_XSAVE_XCR0_LO] = 0;
7070 env->features[FEAT_XSAVE_XCR0_HI] = 0;
81f5cad3
XL		 7071 env->features[FEAT_XSAVE_XSS_LO] = 0;
7072 env->features[FEAT_XSAVE_XSS_HI] = 0;
2ca8a8be
EH		 7073 return;
7074 }
7075
e3c9022b
EH		 7076 mask = 0;
7077 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 7078 const ExtSaveArea *esa = &x86_ext_save_areas[i];
7079 if (env->features[esa->feature] & esa->bits) {
96193c22 7080 mask |= (1ULL << i);
2ca8a8be
EH		 7081 }
7082 }
7083
19db68ca
YZ		 7084 /* Only request permission for first vcpu */
7085 if (kvm_enabled() && !request_perm) {
7086 kvm_request_xsave_components(cpu, mask);
7087 request_perm = true;
7088 }
7089
301e9067 7090 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK;
a11a3651 7091 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32;
301e9067 7092 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK;
a11a3651 7093 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32;
2ca8a8be
EH		 7094}
7095
b8d834a0
EH		 7096/***** Steps involved on loading and filtering CPUID data
7097 *
7098 * When initializing and realizing a CPU object, the steps
7099 * involved in setting up CPUID data are:
7100 *
7101 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 7102 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 7103 * transparent, as it is done automatically by instance_init.
7104 * No code should need to look at X86CPUDefinition structs
7105 * outside instance_init.
7106 *
7107 * 2) CPU expansion. This is done by realize before CPUID
7108 * filtering, and will make sure host/accelerator data is
7109 * loaded for CPU models that depend on host capabilities
7110 * (e.g. "host"). Done by x86_cpu_expand_features().
7111 *
7112 * 3) CPUID filtering. This initializes extra data related to
7113 * CPUID, and checks if the host supports all capabilities
7114 * required by the CPU. Runnability of a CPU model is
7115 * determined at this step. Done by x86_cpu_filter_features().
7116 *
7117 * Some operations don't require all steps to be performed.
7118 * More precisely:
7119 *
7120 * - CPU instance creation (instance_init) will run only CPU
7121 * model loading. CPU expansion can't run at instance_init-time
7122 * because host/accelerator data may be not available yet.
7123 * - CPU realization will perform both CPU model expansion and CPUID
7124 * filtering, and return an error in case one of them fails.
7125 * - query-cpu-definitions needs to run all 3 steps. It needs
7126 * to run CPUID filtering, as the 'unavailable-features'
7127 * field is set based on the filtering results.
7128 * - The query-cpu-model-expansion QMP command only needs to run
7129 * CPU model loading and CPU expansion. It should not filter
7130 * any CPUID data based on host capabilities.
7131 */
7132
7133/* Expand CPU configuration data, based on configured features
7134 * and host/accelerator capabilities when appropriate.
7135 */
79f1a68a 7136void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 7137{
b34d12d1 7138 CPUX86State *env = &cpu->env;
dc15c051 7139 FeatureWord w;
99e24dbd 7140 int i;
2fae0d96 7141 GList *l;
9886e834 7142
99e24dbd
PB		 7143 for (l = plus_features; l; l = l->next) {
7144 const char *prop = l->data;
992861fb
MA		 7145 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
7146 return;
99e24dbd
PB		 7147 }
7148 }
7149
7150 for (l = minus_features; l; l = l->next) {
7151 const char *prop = l->data;
992861fb
MA		 7152 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
7153 return;
99e24dbd
PB		 7154 }
7155 }
7156
d4a606b3
EH		 7157 /*TODO: Now cpu->max_features doesn't overwrite features
7158 * set using QOM properties, and we can convert
dc15c051
IM		 7159 * plus_features & minus_features to global properties
7160 * inside x86_cpu_parse_featurestr() too.
7161 */
44bd8e53 7162 if (cpu->max_features) {
dc15c051 7163 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 7164 /* Override only features that weren't set explicitly
7165 * by the user.
7166 */
7167 env->features[w] |=
7168 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 7169 ~env->user_features[w] &
0d914f39 7170 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 7171 }
7172 }
7173
99e24dbd
PB		 7174 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
7175 FeatureDep *d = &feature_dependencies[i];
7176 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 7177 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 7178
99e24dbd
PB		 7179 /* Not an error unless the dependent feature was added explicitly. */
7180 mark_unavailable_features(cpu, d->to.index,
7181 unavailable_features & env->user_features[d->to.index],
7182 "This feature depends on other features that were not requested");
7183
99e24dbd 7184 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 7185 }
dc15c051
IM		 7186 }
7187
aec661de
EH		 7188 if (!kvm_enabled() || !cpu->expose_kvm) {
7189 env->features[FEAT_KVM] = 0;
7190 }
7191
2ca8a8be 7192 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 7193
7194 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
7195 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
7196 if (cpu->full_cpuid_auto_level) {
7197 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
7198 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
7199 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
7200 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 7201 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
8731336e 7202 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
9dd8b710 7203 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
c39c0edf
EH		 7204 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
7205 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
7206 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 7207 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 7208 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
7209 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
7210 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 7211
7212 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 7213 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
7214 if (cpu->intel_pt_auto_level) {
7215 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
7216 } else if (cpu->env.cpuid_min_level < 0x14) {
7217 mark_unavailable_features(cpu, FEAT_7_0_EBX,
7218 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 7219 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 7220 }
f24c3a79
LK		 7221 }
7222
760746ac
ZP		 7223 /*
7224 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
7225 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
7226 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
7227 * cpu->vendor_cpuid_only has been unset for compatibility with older
7228 * machine types.
7229 */
7230 if ((env->nr_dies > 1) &&
7231 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 7232 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
7233 }
7234
0c3d7c00
EH		 7235 /* SVM requires CPUID[0x8000000A] */
7236 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
7237 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
7238 }
6cb8f2a6
BS		 7239
7240 /* SEV requires CPUID[0x8000001F] */
7241 if (sev_enabled()) {
7242 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
7243 }
dca6cffc 7244
b70eec31
BM		 7245 if (env->features[FEAT_8000_0021_EAX]) {
7246 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
7247 }
7248
dca6cffc
SC		 7249 /* SGX requires CPUID[0x12] for EPC enumeration */
7250 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
7251 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
7252 }
c39c0edf
EH		 7253 }
7254
7255 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 7256 if (env->cpuid_level_func7 == UINT32_MAX) {
7257 env->cpuid_level_func7 = env->cpuid_min_level_func7;
7258 }
c39c0edf
EH		 7259 if (env->cpuid_level == UINT32_MAX) {
7260 env->cpuid_level = env->cpuid_min_level;
7261 }
7262 if (env->cpuid_xlevel == UINT32_MAX) {
7263 env->cpuid_xlevel = env->cpuid_min_xlevel;
7264 }
7265 if (env->cpuid_xlevel2 == UINT32_MAX) {
7266 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 7267 }
071ce4b0 7268
652a5f22
PMD		 7269 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) {
7270 return;
071ce4b0 7271 }
41f3d4d6
EH		 7272}
7273
b8d834a0
EH		 7274/*
7275 * Finishes initialization of CPUID data, filters CPU feature
7276 * words based on host availability of each feature.
7277 *
7278 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
7279 */
245edd0c 7280static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 7281{
7282 CPUX86State *env = &cpu->env;
7283 FeatureWord w;
245edd0c
PB		 7284 const char *prefix = NULL;
7285
7286 if (verbose) {
7287 prefix = accel_uses_host_cpuid()
7288 ? "host doesn't support requested feature"
7289 : "TCG doesn't support requested feature";
7290 }
b8d834a0
EH		 7291
7292 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 7293 uint64_t host_feat =
b8d834a0 7294 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 7295 uint64_t requested_features = env->features[w];
7296 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 7297 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 7298 }
7299
028ade14
PB		 7300 /*
7301 * Check that KVM actually allows the processor tracing features that
7302 * are advertised by cpu_x86_cpuid(). Keep these two in sync.
7303 */
7304 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
7305 kvm_enabled()) {
d0474024
PMD		 7306 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused;
7307 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused;
7308
7309 x86_cpu_get_supported_cpuid(0x14, 0,
7310 &eax_0, &ebx_0, &ecx_0, &edx_0_unused);
7311 x86_cpu_get_supported_cpuid(0x14, 1,
7312 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused);
e37a5c7f
CP		 7313
7314 if (!eax_0 ||
7315 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
7316 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
7317 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
7318 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
7319 INTEL_PT_ADDR_RANGES_NUM) ||
7320 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 7321 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 7322 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
7323 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 7324 /*
7325 * Processor Trace capabilities aren't configurable, so if the
7326 * host can't emulate the capabilities we report on
7327 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
7328 */
245edd0c 7329 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 7330 }
7331 }
b8d834a0
EH		 7332}
7333
08856771
VK		 7334static void x86_cpu_hyperv_realize(X86CPU *cpu)
7335{
7336 size_t len;
7337
7338 /* Hyper-V vendor id */
7339 if (!cpu->hyperv_vendor) {
4519259a
VK		 7340 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
7341 &error_abort);
7342 }
7343 len = strlen(cpu->hyperv_vendor);
7344 if (len > 12) {
7345 warn_report("hv-vendor-id truncated to 12 characters");
7346 len = 12;
08856771 7347 }
4519259a
VK		 7348 memset(cpu->hyperv_vendor_id, 0, 12);
7349 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 7350
7351 /* 'Hv#1' interface identification*/
7352 cpu->hyperv_interface_id[0] = 0x31237648;
7353 cpu->hyperv_interface_id[1] = 0;
7354 cpu->hyperv_interface_id[2] = 0;
7355 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 7356
23eb5d03
VK		 7357 /* Hypervisor implementation limits */
7358 cpu->hyperv_limits[0] = 64;
7359 cpu->hyperv_limits[1] = 0;
7360 cpu->hyperv_limits[2] = 0;
08856771
VK		 7361}
7362
41f3d4d6
EH		 7363static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7364{
7365 CPUState *cs = CPU(dev);
7366 X86CPU *cpu = X86_CPU(dev);
7367 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
7368 CPUX86State *env = &cpu->env;
7369 Error *local_err = NULL;
f06d8a18 7370 unsigned requested_lbr_fmt;
41f3d4d6 7371
b94b8c60 7372#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
492f8b88 7373 /* Use pc-relative instructions in system-mode */
492f8b88
AJ		 7374 cs->tcg_cflags |= CF_PCREL;
7375#endif
7376
41f3d4d6
EH		 7377 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
7378 error_setg(errp, "apic-id property was not initialized properly");
7379 return;
7380 }
7381
662175b9
CF		 7382 /*
7383 * Process Hyper-V enlightenments.
7384 * Note: this currently has to happen before the expansion of CPU features.
7385 */
7386 x86_cpu_hyperv_realize(cpu);
7387
b8d834a0 7388 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 7389 if (local_err) {
7390 goto out;
7391 }
7392
f06d8a18
YW		 7393 /*
7394 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
7395 * with user-provided setting.
7396 */
7397 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) {
7398 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) {
7399 error_setg(errp, "invalid lbr-fmt");
7400 return;
7401 }
7402 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT;
7403 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt;
7404 }
7405
7406 /*
7407 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
7408 * 3)vPMU LBR format matches that of host setting.
7409 */
7410 requested_lbr_fmt =
7411 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT;
7412 if (requested_lbr_fmt && kvm_enabled()) {
7413 uint64_t host_perf_cap =
7414 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false);
7415 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT;
7416
7417 if (!cpu->enable_pmu) {
7418 error_setg(errp, "vPMU: LBR is unsupported without pmu=on");
7419 return;
7420 }
7421 if (requested_lbr_fmt != host_lbr_fmt) {
7422 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match "
7423 "the host value (0x%x).",
7424 requested_lbr_fmt, host_lbr_fmt);
7425 return;
7426 }
7427 }
7428
245edd0c
PB		 7429 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
7430
7431 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
7432 error_setg(&local_err,
7433 accel_uses_host_cpuid() ?
7434 "Host doesn't support requested features" :
7435 "TCG doesn't support requested features");
7436 goto out;
9997cf7b
EH		 7437 }
7438
9b15cd9e
IM		 7439 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
7440 * CPUID[1].EDX.
7441 */
e48638fd 7442 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 7443 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
7444 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 7445 & CPUID_EXT2_AMD_ALIASES);
7446 }
7447
db888065
SC		 7448 x86_cpu_set_sgxlepubkeyhash(env);
7449
662175b9
CF		 7450 /*
7451 * note: the call to the framework needs to happen after feature expansion,
7452 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
7453 * These may be set by the accel-specific code,
7454 * and the results are subsequently checked / assumed in this function.
7455 */
7456 cpu_exec_realizefn(cs, &local_err);
7457 if (local_err != NULL) {
7458 error_propagate(errp, local_err);
7459 return;
7460 }
7461
7462 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
7463 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
7464 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
7465 goto out;
7466 }
7467
513ba32d
GH		 7468 if (cpu->guest_phys_bits == -1) {
7469 /*
7470 * If it was not set by the user, or by the accelerator via
7471 * cpu_exec_realizefn, clear.
7472 */
7473 cpu->guest_phys_bits = 0;
7474 }
7475
662175b9
CF		 7476 if (cpu->ucode_rev == 0) {
7477 /*
7478 * The default is the same as KVM's. Note that this check
7479 * needs to happen after the evenual setting of ucode_rev in
7480 * accel-specific code in cpu_exec_realizefn.
7481 */
7482 if (IS_AMD_CPU(env)) {
7483 cpu->ucode_rev = 0x01000065;
7484 } else {
7485 cpu->ucode_rev = 0x100000000ULL;
7486 }
7487 }
7488
7489 /*
7490 * mwait extended info: needed for Core compatibility
7491 * We always wake on interrupt even if host does not have the capability.
7492 *
7493 * requires the accel-specific code in cpu_exec_realizefn to
7494 * have already acquired the CPUID data into cpu->mwait.
7495 */
7496 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
7497
11f6fee5
DDAG		 7498 /* For 64bit systems think about the number of physical bits to present.
7499 * ideally this should be the same as the host; anything other than matching
7500 * the host can cause incorrect guest behaviour.
7501 * QEMU used to pick the magic value of 40 bits that corresponds to
7502 * consumer AMD devices but nothing else.
662175b9
CF		 7503 *
7504 * Note that this code assumes features expansion has already been done
7505 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
7506 * phys_bits adjustments to match the host have been already done in
7507 * accel-specific code in cpu_exec_realizefn.
11f6fee5 7508 */
af45907a 7509 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 7510 if (cpu->phys_bits &&
7511 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
7512 cpu->phys_bits < 32)) {
7513 error_setg(errp, "phys-bits should be between 32 and %u "
7514 " (but is %u)",
7515 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
7516 return;
af45907a 7517 }
f5cc5a5c
CF		 7518 /*
7519 * 0 means it was not explicitly set by the user (or by machine
7520 * compat_props or by the host code in host-cpu.c).
7521 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 7522 */
7523 if (cpu->phys_bits == 0) {
7524 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
7525 }
513ba32d
GH		 7526 if (cpu->guest_phys_bits &&
7527 (cpu->guest_phys_bits > cpu->phys_bits ||
7528 cpu->guest_phys_bits < 32)) {
7529 error_setg(errp, "guest-phys-bits should be between 32 and %u "
7530 " (but is %u)",
7531 cpu->phys_bits, cpu->guest_phys_bits);
7532 return;
7533 }
af45907a
DDAG		 7534 } else {
7535 /* For 32 bit systems don't use the user set value, but keep
7536 * phys_bits consistent with what we tell the guest.
7537 */
7538 if (cpu->phys_bits != 0) {
7539 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
7540 return;
7541 }
513ba32d
GH		 7542 if (cpu->guest_phys_bits != 0) {
7543 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit");
7544 return;
7545 }
fefb41bf 7546
d8300542 7547 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) {
af45907a
DDAG		 7548 cpu->phys_bits = 36;
7549 } else {
7550 cpu->phys_bits = 32;
7551 }
7552 }
a9f27ea9
EH		 7553
7554 /* Cache information initialization */
7555 if (!cpu->legacy_cache) {
cca0a000
MR		 7556 const CPUCaches *cache_info =
7557 x86_cpu_get_versioned_cache_info(cpu, xcc->model);
7558
7559 if (!xcc->model || !cache_info) {
88703ce2 7560 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 7561 error_setg(errp,
7562 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 7563 return;
7564 }
7565 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
cca0a000 7566 *cache_info;
a9f27ea9
EH		 7567 } else {
7568 /* Build legacy cache information */
7569 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
7570 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
7571 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
7572 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
7573
7574 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
7575 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
7576 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
7577 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
7578
7579 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
7580 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
7581 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
7582 env->cache_info_amd.l3_cache = &legacy_l3_cache;
7583 }
7584
65dee380 7585#ifndef CONFIG_USER_ONLY
0e11fc69 7586 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 7587 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 7588
0e11fc69 7589 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 7590 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 7591 if (local_err != NULL) {
4dc1f449 7592 goto out;
bdeec802
IM		 7593 }
7594 }
65dee380
IM		 7595#endif
7596
7a059953 7597 mce_init(cpu);
2001d0cd 7598
14a10fc3 7599 qemu_init_vcpu(cs);
d3c64d6a 7600
6b2942f9
BM		 7601 /*
7602 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
7603 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
7604 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 7605 * users a warning.
7606 *
7607 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
7608 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
7609 */
0765691e
MA		 7610 if (IS_AMD_CPU(env) &&
7611 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
8e3991eb
ZL		 7612 cs->nr_threads > 1) {
7613 warn_report_once("This family of AMD CPU doesn't support "
aec202cb
ZL		 7614 "hyperthreading(%d). Please configure -smp "
7615 "options properly or try enabling topoext "
7616 "feature.", cs->nr_threads);
e48638fd
WH		 7617 }
7618
79f1a68a 7619#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 7620 x86_cpu_apic_realize(cpu, &local_err);
7621 if (local_err != NULL) {
7622 goto out;
7623 }
79f1a68a 7624#endif /* !CONFIG_USER_ONLY */
14a10fc3 7625 cpu_reset(cs);
2b6f294c 7626
4dc1f449 7627 xcc->parent_realize(dev, &local_err);
2001d0cd 7628
4dc1f449
IM		 7629out:
7630 if (local_err != NULL) {
7631 error_propagate(errp, local_err);
7632 return;
7633 }
7a059953
AF		 7634}
7635
b69c3c21 7636static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 7637{
7638 X86CPU *cpu = X86_CPU(dev);
7bbc124e 7639 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 7640
7641#ifndef CONFIG_USER_ONLY
7642 cpu_remove_sync(CPU(dev));
7643 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
7644#endif
7645
7646 if (cpu->apic_state) {
7647 object_unparent(OBJECT(cpu->apic_state));
7648 cpu->apic_state = NULL;
7649 }
7bbc124e 7650
b69c3c21 7651 xcc->parent_unrealize(dev);
c884776e
IM		 7652}
7653
38e5c119 7654typedef struct BitProperty {
a7b0ffac 7655 FeatureWord w;
ede146c2 7656 uint64_t mask;
38e5c119
EH		 7657} BitProperty;
7658
d7bce999
EB		 7659static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
7660 void *opaque, Error **errp)
38e5c119 7661{
a7b0ffac 7662 X86CPU *cpu = X86_CPU(obj);
38e5c119 7663 BitProperty *fp = opaque;
ede146c2 7664 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 7665 bool value = (f & fp->mask) == fp->mask;
51e72bc1 7666 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 7667}
7668
d7bce999
EB		 7669static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
7670 void *opaque, Error **errp)
38e5c119
EH		 7671{
7672 DeviceState *dev = DEVICE(obj);
a7b0ffac 7673 X86CPU *cpu = X86_CPU(obj);
38e5c119 7674 BitProperty *fp = opaque;
38e5c119
EH		 7675 bool value;
7676
7677 if (dev->realized) {
7678 qdev_prop_set_after_realize(dev, name, errp);
7679 return;
7680 }
7681
668f62ec 7682 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 7683 return;
7684 }
7685
7686 if (value) {
a7b0ffac 7687 cpu->env.features[fp->w] |= fp->mask;
38e5c119 7688 } else {
a7b0ffac 7689 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 7690 }
d4a606b3 7691 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 7692}
7693
38e5c119
EH		 7694/* Register a boolean property to get/set a single bit in a uint32_t field.
7695 *
7696 * The same property name can be registered multiple times to make it affect
7697 * multiple bits in the same FeatureWord. In that case, the getter will return
7698 * true only if all bits are set.
7699 */
f5730c69 7700static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 7701 const char *prop_name,
a7b0ffac 7702 FeatureWord w,
38e5c119
EH		 7703 int bitnr)
7704{
f5730c69 7705 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 7706 BitProperty *fp;
7707 ObjectProperty *op;
ede146c2 7708 uint64_t mask = (1ULL << bitnr);
38e5c119 7709
f5730c69 7710 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 7711 if (op) {
7712 fp = op->opaque;
a7b0ffac 7713 assert(fp->w == w);
38e5c119
EH		 7714 fp->mask |= mask;
7715 } else {
7716 fp = g_new0(BitProperty, 1);
a7b0ffac 7717 fp->w = w;
38e5c119 7718 fp->mask = mask;
f5730c69
EH		 7719 object_class_property_add(oc, prop_name, "bool",
7720 x86_cpu_get_bit_prop,
7721 x86_cpu_set_bit_prop,
7722 NULL, fp);
38e5c119
EH		 7723 }
7724}
7725
f5730c69 7726static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 7727 FeatureWord w,
7728 int bitnr)
7729{
38e5c119 7730 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 7731 const char *name = fi->feat_names[bitnr];
38e5c119 7732
16d2fcaa 7733 if (!name) {
38e5c119
EH		 7734 return;
7735 }
7736
fc7dfd20
EH		 7737 /* Property names should use "-" instead of "_".
7738 * Old names containing underscores are registered as aliases
7739 * using object_property_add_alias()
7740 */
16d2fcaa
EH		 7741 assert(!strchr(name, '_'));
7742 /* aliases don't use "|" delimiters anymore, they are registered
7743 * manually using object_property_add_alias() */
7744 assert(!strchr(name, '|'));
f5730c69 7745 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 7746}
7747
4db4385a
CF		 7748static void x86_cpu_post_initfn(Object *obj)
7749{
7750 accel_cpu_instance_init(CPU(obj));
7751}
7752
de024815
AF		 7753static void x86_cpu_initfn(Object *obj)
7754{
7755 X86CPU *cpu = X86_CPU(obj);
d940ee9b 7756 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 7757 CPUX86State *env = &cpu->env;
7758
c26ae610 7759 env->nr_dies = 1;
71ad61d3 7760
8e8aba50
EH		 7761 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
7762 x86_cpu_get_feature_words,
d2623129 7763 NULL, NULL, (void *)env->features);
7e5292b5
EH		 7764 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
7765 x86_cpu_get_feature_words,
d2623129 7766 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 7767
d2623129
MA		 7768 object_property_add_alias(obj, "sse3", obj, "pni");
7769 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
7770 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
7771 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
7772 object_property_add_alias(obj, "xd", obj, "nx");
7773 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
7774 object_property_add_alias(obj, "i64", obj, "lm");
7775
7776 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
7777 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
7778 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
7779 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
7780 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
7781 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
7782 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
7783 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
7784 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
7785 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
7786 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 7787 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 7788 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
7789 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
7790 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
7791 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
7792 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
7793 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
7794 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
7795 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
7796 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7797 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7798 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 7799
e1f9a8e8 7800 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
f06d8a18
YW		 7801 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;
7802 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt");
e1f9a8e8 7803
dcafd1ef 7804 if (xcc->model) {
49e2fa85 7805 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 7806 }
de024815
AF		 7807}
7808
997395d3
IM		 7809static int64_t x86_cpu_get_arch_id(CPUState *cs)
7810{
7811 X86CPU *cpu = X86_CPU(cs);
997395d3 7812
7e72a45c 7813 return cpu->apic_id;
997395d3
IM		 7814}
7815
6bc0d6a0 7816#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 7817static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7818{
7819 X86CPU *cpu = X86_CPU(cs);
7820
7821 return cpu->env.cr[0] & CR0_PG_MASK;
7822}
6bc0d6a0 7823#endif /* !CONFIG_USER_ONLY */
444d5590 7824
f45748f1
AF		 7825static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7826{
7827 X86CPU *cpu = X86_CPU(cs);
7828
7829 cpu->env.eip = value;
7830}
7831
e4fdf9df
RH		 7832static vaddr x86_cpu_get_pc(CPUState *cs)
7833{
7834 X86CPU *cpu = X86_CPU(cs);
7835
7836 /* Match cpu_get_tb_cpu_state. */
7837 return cpu->env.eip + cpu->env.segs[R_CS].base;
7838}
7839
92d5f1a4 7840int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 7841{
7842 X86CPU *cpu = X86_CPU(cs);
7843 CPUX86State *env = &cpu->env;
7844
92d5f1a4
PB		 7845#if !defined(CONFIG_USER_ONLY)
7846 if (interrupt_request & CPU_INTERRUPT_POLL) {
7847 return CPU_INTERRUPT_POLL;
7848 }
7849#endif
7850 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7851 return CPU_INTERRUPT_SIPI;
7852 }
7853
7854 if (env->hflags2 & HF2_GIF_MASK) {
7855 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7856 !(env->hflags & HF_SMM_MASK)) {
7857 return CPU_INTERRUPT_SMI;
7858 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7859 !(env->hflags2 & HF2_NMI_MASK)) {
7860 return CPU_INTERRUPT_NMI;
7861 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7862 return CPU_INTERRUPT_MCE;
7863 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7864 (((env->hflags2 & HF2_VINTR_MASK) &&
7865 (env->hflags2 & HF2_HIF_MASK)) ||
7866 (!(env->hflags2 & HF2_VINTR_MASK) &&
7867 (env->eflags & IF_MASK &&
7868 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7869 return CPU_INTERRUPT_HARD;
7870#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 7871 } else if (env->hflags2 & HF2_VGIF_MASK) {
7872 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 7873 (env->eflags & IF_MASK) &&
7874 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 7875 return CPU_INTERRUPT_VIRQ;
7876 }
92d5f1a4
PB		 7877#endif
7878 }
7879 }
7880
7881 return 0;
7882}
7883
7884static bool x86_cpu_has_work(CPUState *cs)
7885{
7886 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 7887}
7888
a120d320 7889static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
ace0c5fe
RH		 7890{
7891 CPUX86State *env = cpu_env(cs);
2cc68629 7892 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1;
90f64153
PB		 7893 int mmu_index_base =
7894 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX :
7895 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
7896 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
ace0c5fe 7897
90f64153 7898 return mmu_index_base + mmu_index_32;
ace0c5fe
RH		 7899}
7900
f50f3dd5
RH		 7901static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7902{
7903 X86CPU *cpu = X86_CPU(cs);
7904 CPUX86State *env = &cpu->env;
7905
7906 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7907 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7908 : bfd_mach_i386_i8086);
b666d2a4
RH		 7909
7910 info->cap_arch = CS_ARCH_X86;
7911 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7912 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7913 : CS_MODE_16);
15fa1a0a
RH		 7914 info->cap_insn_unit = 1;
7915 info->cap_insn_split = 8;
f50f3dd5
RH		 7916}
7917
35b1b927
TW		 7918void x86_update_hflags(CPUX86State *env)
7919{
7920 uint32_t hflags;
7921#define HFLAG_COPY_MASK \
7922 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7923 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7924 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7925 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7926
7927 hflags = env->hflags & HFLAG_COPY_MASK;
7928 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7929 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7930 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7931 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7932 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7933
7934 if (env->cr[4] & CR4_OSFXSR_MASK) {
7935 hflags |= HF_OSFXSR_MASK;
7936 }
7937
7938 if (env->efer & MSR_EFER_LMA) {
7939 hflags |= HF_LMA_MASK;
7940 }
7941
7942 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7943 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7944 } else {
7945 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7946 (DESC_B_SHIFT - HF_CS32_SHIFT);
7947 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7948 (DESC_B_SHIFT - HF_SS32_SHIFT);
7949 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7950 !(hflags & HF_CS32_MASK)) {
7951 hflags |= HF_ADDSEG_MASK;
7952 } else {
7953 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7954 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7955 }
7956 }
7957 env->hflags = hflags;
7958}
7959
9337e3b6 7960static Property x86_cpu_properties[] = {
2da00e31
IM		 7961#ifdef CONFIG_USER_ONLY
7962 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7963 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 7964 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7965 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 7966 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 7967 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 7968#else
7969 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 7970 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7971 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 7972 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 7973 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 7974#endif
15f8b142 7975 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 7976 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
f06d8a18 7977 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
2d384d7c 7978
915aee93 7979 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 7980 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 7981 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7982 HYPERV_FEAT_RELAXED, 0),
7983 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7984 HYPERV_FEAT_VAPIC, 0),
7985 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7986 HYPERV_FEAT_TIME, 0),
7987 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7988 HYPERV_FEAT_CRASH, 0),
7989 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7990 HYPERV_FEAT_RESET, 0),
7991 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7992 HYPERV_FEAT_VPINDEX, 0),
7993 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7994 HYPERV_FEAT_RUNTIME, 0),
7995 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7996 HYPERV_FEAT_SYNIC, 0),
7997 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7998 HYPERV_FEAT_STIMER, 0),
7999 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
8000 HYPERV_FEAT_FREQUENCIES, 0),
8001 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
8002 HYPERV_FEAT_REENLIGHTENMENT, 0),
8003 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
8004 HYPERV_FEAT_TLBFLUSH, 0),
8005 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
8006 HYPERV_FEAT_EVMCS, 0),
8007 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
8008 HYPERV_FEAT_IPI, 0),
128531d9
VK		 8009 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
8010 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 8011 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
8012 HYPERV_FEAT_AVIC, 0),
869840d2
VK		 8013 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
8014 HYPERV_FEAT_MSR_BITMAP, 0),
9411e8b6
VK		 8015 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
8016 HYPERV_FEAT_XMM_INPUT, 0),
aa6bb5fa
VK		 8017 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
8018 HYPERV_FEAT_TLBFLUSH_EXT, 0),
3aae0854
VK		 8019 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
8020 HYPERV_FEAT_TLBFLUSH_DIRECT, 0),
30d6ff66
VK		 8021 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
8022 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
73d24074
JD		 8023 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
8024 HYPERV_FEAT_SYNDBG, 0),
e48ddcc6 8025 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 8026 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 8027
af7228b8
VK		 8028 /* WS2008R2 identify by default */
8029 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 8030 0x3839),
af7228b8 8031 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 8032 0x000A),
af7228b8 8033 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 8034 0x0000),
af7228b8
VK		 8035 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
8036 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
8037 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
8038
15e41345 8039 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 8040 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 8041 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 8042 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 8043 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
513ba32d 8044 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1),
11f6fee5 8045 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 8046 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 8047 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 8048 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
8049 UINT32_MAX),
c39c0edf
EH		 8050 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
8051 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
8052 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
8053 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
8054 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
8055 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 8056 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 8057 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 8058 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 8059 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 8060 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 8061 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 8062 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 8063 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
8064 false),
988f7b8b
VK		 8065 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
8066 false),
0b564e6f 8067 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 8068 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 8069 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
8070 true),
ab8f992e 8071 /*
a9f27ea9
EH		 8072 * lecacy_cache defaults to true unless the CPU model provides its
8073 * own cache information (see x86_cpu_load_def()).
ab8f992e 8074 */
a9f27ea9 8075 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
f66b8a83 8076 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
6c69dfb6
GA		 8077
8078 /*
8079 * From "Requirements for Implementing the Microsoft
8080 * Hypervisor Interface":
8081 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
8082 *
8083 * "Starting with Windows Server 2012 and Windows 8, if
8084 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
8085 * the hypervisor imposes no specific limit to the number of VPs.
8086 * In this case, Windows Server 2012 guest VMs may use more than
8087 * 64 VPs, up to the maximum supported number of processors applicable
8088 * to the specific Windows version being used."
8089 */
8090 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 8091 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
8092 false),
f24c3a79
LK		 8093 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
8094 true),
9337e3b6
EH		 8095 DEFINE_PROP_END_OF_LIST()
8096};
8097
8b80bd28
PMD		 8098#ifndef CONFIG_USER_ONLY
8099#include "hw/core/sysemu-cpu-ops.h"
8100
8101static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 8102 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 8103 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 8104 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 8105 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 8106 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 8107 .write_elf32_note = x86_cpu_write_elf32_note,
8108 .write_elf64_note = x86_cpu_write_elf64_note,
8109 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
8110 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 8111 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 8112};
8113#endif
8114
5fd2087a
AF		 8115static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
8116{
8117 X86CPUClass *xcc = X86_CPU_CLASS(oc);
8118 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 8119 DeviceClass *dc = DEVICE_CLASS(oc);
e86787d3 8120 ResettableClass *rc = RESETTABLE_CLASS(oc);
f5730c69 8121 FeatureWord w;
2b6f294c 8122
bf853881
PMD		 8123 device_class_set_parent_realize(dc, x86_cpu_realizefn,
8124 &xcc->parent_realize);
8125 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
8126 &xcc->parent_unrealize);
4f67d30b 8127 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 8128
e86787d3
PM		 8129 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL,
8130 &xcc->parent_phases);
91b1df8c 8131 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 8132
500050d1 8133 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 8134 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 8135 cc->has_work = x86_cpu_has_work;
ace0c5fe 8136 cc->mmu_index = x86_cpu_mmu_index;
878096ee 8137 cc->dump_state = x86_cpu_dump_state;
f45748f1 8138 cc->set_pc = x86_cpu_set_pc;
e4fdf9df 8139 cc->get_pc = x86_cpu_get_pc;
5b50e790
AF		 8140 cc->gdb_read_register = x86_cpu_gdb_read_register;
8141 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 8142 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 8143
5d004421 8144#ifndef CONFIG_USER_ONLY
8b80bd28 8145 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 8146#endif /* !CONFIG_USER_ONLY */
8147
00fcd100
AB		 8148 cc->gdb_arch_name = x86_gdb_arch_name;
8149#ifdef TARGET_X86_64
b8158192 8150 cc->gdb_core_xml_file = "i386-64bit.xml";
00fcd100 8151#else
b8158192 8152 cc->gdb_core_xml_file = "i386-32bit.xml";
74d7fc7f 8153#endif
f50f3dd5 8154 cc->disas_set_info = x86_disas_set_info;
4c315c27 8155
e90f2a8c 8156 dc->user_creatable = true;
3e0dceaf
EH		 8157
8158 object_class_property_add(oc, "family", "int",
8159 x86_cpuid_version_get_family,
8160 x86_cpuid_version_set_family, NULL, NULL);
8161 object_class_property_add(oc, "model", "int",
8162 x86_cpuid_version_get_model,
8163 x86_cpuid_version_set_model, NULL, NULL);
8164 object_class_property_add(oc, "stepping", "int",
8165 x86_cpuid_version_get_stepping,
8166 x86_cpuid_version_set_stepping, NULL, NULL);
8167 object_class_property_add_str(oc, "vendor",
8168 x86_cpuid_get_vendor,
8169 x86_cpuid_set_vendor);
8170 object_class_property_add_str(oc, "model-id",
8171 x86_cpuid_get_model_id,
8172 x86_cpuid_set_model_id);
8173 object_class_property_add(oc, "tsc-frequency", "int",
8174 x86_cpuid_get_tsc_freq,
8175 x86_cpuid_set_tsc_freq, NULL, NULL);
8176 /*
8177 * The "unavailable-features" property has the same semantics as
8178 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
8179 * QMP command: they list the features that would have prevented the
8180 * CPU from running if the "enforce" flag was set.
8181 */
8182 object_class_property_add(oc, "unavailable-features", "strList",
8183 x86_cpu_get_unavailable_features,
8184 NULL, NULL, NULL);
8185
8186#if !defined(CONFIG_USER_ONLY)
8187 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
8188 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
8189#endif
8190
f5730c69
EH		 8191 for (w = 0; w < FEATURE_WORDS; w++) {
8192 int bitnr;
8193 for (bitnr = 0; bitnr < 64; bitnr++) {
8194 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
8195 }
8196 }
5fd2087a
AF		 8197}
8198
8199static const TypeInfo x86_cpu_type_info = {
8200 .name = TYPE_X86_CPU,
8201 .parent = TYPE_CPU,
8202 .instance_size = sizeof(X86CPU),
f669c992 8203 .instance_align = __alignof(X86CPU),
de024815 8204 .instance_init = x86_cpu_initfn,
4db4385a
CF		 8205 .instance_post_init = x86_cpu_post_initfn,
8206
d940ee9b 8207 .abstract = true,
5fd2087a
AF		 8208 .class_size = sizeof(X86CPUClass),
8209 .class_init = x86_cpu_common_class_init,
8210};
8211
5adbed30
EH		 8212/* "base" CPU model, used by query-cpu-model-expansion */
8213static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
8214{
8215 X86CPUClass *xcc = X86_CPU_CLASS(oc);
8216
8217 xcc->static_model = true;
8218 xcc->migration_safe = true;
8219 xcc->model_description = "base CPU model type with no features enabled";
8220 xcc->ordering = 8;
8221}
8222
8223static const TypeInfo x86_base_cpu_type_info = {
8224 .name = X86_CPU_TYPE_NAME("base"),
8225 .parent = TYPE_X86_CPU,
8226 .class_init = x86_cpu_base_class_init,
8227};
8228
5fd2087a
AF		 8229static void x86_cpu_register_types(void)
8230{
d940ee9b
EH		 8231 int i;
8232
5fd2087a 8233 type_register_static(&x86_cpu_type_info);
d940ee9b 8234 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 8235 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 8236 }
c62f2630 8237 type_register_static(&max_x86_cpu_type_info);
5adbed30 8238 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 8239}
8240
8241type_init(x86_cpu_register_types)
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