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target/i386: Export MSR_ARCH_CAPABILITIES bits to guests
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
15e09912 24#include "qemu/hw-version.h"
c6dc6f63 25#include "cpu.h"
ed69e831 26#include "tcg/helper-tcg.h"
71e8a915 27#include "sysemu/reset.h"
d6dcc558 28#include "sysemu/hvf.h"
a9dc68d9 29#include "kvm/kvm_i386.h"
93777de3 30#include "sev.h"
f83aeeae 31#include "qapi/error.h"
cc37d98b 32#include "qemu/error-report.h"
8ac25c84 33#include "qapi/qapi-visit-machine.h"
7b1b5d19 34#include "qapi/qmp/qerror.h"
1814eab6 35#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 36#include "hw/qdev-properties.h"
5232d00a 37#include "hw/i386/topology.h"
bdeec802 38#ifndef CONFIG_USER_ONLY
390dbc6e 39#include "qapi/qapi-commands-machine-target.h"
2001d0cd 40#include "exec/address-spaces.h"
0e11fc69 41#include "hw/boards.h"
1dec2e1f 42#include "hw/i386/sgx-epc.h"
bdeec802
IM		 43#endif
44
b666d2a4 45#include "disas/capstone.h"
79f1a68a 46#include "cpu-internal.h"
b666d2a4 47
123fa102
TH		 48static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
49
7e3482f8
EH		 50/* Helpers for building CPUID[2] descriptors: */
51
52struct CPUID2CacheDescriptorInfo {
53 enum CacheType type;
54 int level;
55 int size;
56 int line_size;
57 int associativity;
58};
5e891bf8 59
7e3482f8
EH		 60/*
61 * Known CPUID 2 cache descriptors.
62 * From Intel SDM Volume 2A, CPUID instruction
63 */
64struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 66 .associativity = 4, .line_size = 32, },
5f00335a 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 68 .associativity = 4, .line_size = 32, },
5f00335a 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 70 .associativity = 4, .line_size = 64, },
5f00335a 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 72 .associativity = 2, .line_size = 32, },
5f00335a 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 74 .associativity = 4, .line_size = 32, },
5f00335a 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 76 .associativity = 4, .line_size = 64, },
5f00335a 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 78 .associativity = 6, .line_size = 64, },
5f00335a 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 80 .associativity = 2, .line_size = 64, },
5f00335a 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 82 .associativity = 8, .line_size = 64, },
83 /* lines per sector is not supported cpuid2_cache_descriptor(),
84 * so descriptors 0x22, 0x23 are not included
85 */
5f00335a 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 87 .associativity = 16, .line_size = 64, },
88 /* lines per sector is not supported cpuid2_cache_descriptor(),
89 * so descriptors 0x25, 0x20 are not included
90 */
5f00335a 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 92 .associativity = 8, .line_size = 64, },
5f00335a 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 94 .associativity = 8, .line_size = 64, },
5f00335a 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 96 .associativity = 4, .line_size = 32, },
5f00335a 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 98 .associativity = 4, .line_size = 32, },
5f00335a 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 100 .associativity = 4, .line_size = 32, },
5f00335a 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 102 .associativity = 4, .line_size = 32, },
5f00335a 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 104 .associativity = 4, .line_size = 32, },
5f00335a 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 106 .associativity = 4, .line_size = 64, },
5f00335a 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 108 .associativity = 8, .line_size = 64, },
5f00335a 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 110 .associativity = 12, .line_size = 64, },
111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 113 .associativity = 12, .line_size = 64, },
5f00335a 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 115 .associativity = 16, .line_size = 64, },
5f00335a 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 117 .associativity = 12, .line_size = 64, },
5f00335a 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 119 .associativity = 16, .line_size = 64, },
5f00335a 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 121 .associativity = 24, .line_size = 64, },
5f00335a 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 123 .associativity = 8, .line_size = 64, },
5f00335a 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 125 .associativity = 4, .line_size = 64, },
5f00335a 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 127 .associativity = 4, .line_size = 64, },
5f00335a 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 129 .associativity = 4, .line_size = 64, },
5f00335a 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 131 .associativity = 4, .line_size = 64, },
132 /* lines per sector is not supported cpuid2_cache_descriptor(),
133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
134 */
5f00335a 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 136 .associativity = 8, .line_size = 64, },
5f00335a 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 138 .associativity = 2, .line_size = 64, },
5f00335a 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 140 .associativity = 8, .line_size = 64, },
5f00335a 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 142 .associativity = 8, .line_size = 32, },
5f00335a 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 144 .associativity = 8, .line_size = 32, },
5f00335a 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 146 .associativity = 8, .line_size = 32, },
5f00335a 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 148 .associativity = 8, .line_size = 32, },
5f00335a 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 150 .associativity = 4, .line_size = 64, },
5f00335a 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 152 .associativity = 8, .line_size = 64, },
5f00335a 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 154 .associativity = 4, .line_size = 64, },
5f00335a 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 156 .associativity = 4, .line_size = 64, },
5f00335a 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 158 .associativity = 4, .line_size = 64, },
5f00335a 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 160 .associativity = 8, .line_size = 64, },
5f00335a 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 162 .associativity = 8, .line_size = 64, },
5f00335a 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 164 .associativity = 8, .line_size = 64, },
5f00335a 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 166 .associativity = 12, .line_size = 64, },
5f00335a 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 168 .associativity = 12, .line_size = 64, },
5f00335a 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 170 .associativity = 12, .line_size = 64, },
5f00335a 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 172 .associativity = 16, .line_size = 64, },
5f00335a 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 174 .associativity = 16, .line_size = 64, },
5f00335a 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 176 .associativity = 16, .line_size = 64, },
5f00335a 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 178 .associativity = 24, .line_size = 64, },
5f00335a 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 180 .associativity = 24, .line_size = 64, },
5f00335a 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 182 .associativity = 24, .line_size = 64, },
183};
184
185/*
186 * "CPUID leaf 2 does not report cache descriptor information,
187 * use CPUID leaf 4 to query cache parameters"
188 */
189#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 190
7e3482f8
EH		 191/*
192 * Return a CPUID 2 cache descriptor for a given cache.
193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
194 */
195static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
196{
197 int i;
198
199 assert(cache->size > 0);
200 assert(cache->level > 0);
201 assert(cache->line_size > 0);
202 assert(cache->associativity > 0);
203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
205 if (d->level == cache->level && d->type == cache->type &&
206 d->size == cache->size && d->line_size == cache->line_size &&
207 d->associativity == cache->associativity) {
208 return i;
209 }
210 }
5e891bf8 211
7e3482f8
EH		 212 return CACHE_DESCRIPTOR_UNAVAILABLE;
213}
5e891bf8
EH		 214
215/* CPUID Leaf 4 constants: */
216
217/* EAX: */
7e3482f8
EH		 218#define CACHE_TYPE_D 1
219#define CACHE_TYPE_I 2
220#define CACHE_TYPE_UNIFIED 3
5e891bf8 221
7e3482f8 222#define CACHE_LEVEL(l) (l << 5)
5e891bf8 223
7e3482f8 224#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 225
226/* EDX: */
7e3482f8
EH		 227#define CACHE_NO_INVD_SHARING (1 << 0)
228#define CACHE_INCLUSIVE (1 << 1)
229#define CACHE_COMPLEX_IDX (1 << 2)
230
231/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 232#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
235 0 /* Invalid value */)
7e3482f8
EH		 236
237
238/* Encode cache info for CPUID[4] */
239static void encode_cache_cpuid4(CPUCacheInfo *cache,
240 int num_apic_ids, int num_cores,
241 uint32_t *eax, uint32_t *ebx,
242 uint32_t *ecx, uint32_t *edx)
243{
244 assert(cache->size == cache->line_size * cache->associativity *
245 cache->partitions * cache->sets);
246
247 assert(num_apic_ids > 0);
248 *eax = CACHE_TYPE(cache->type) |
249 CACHE_LEVEL(cache->level) |
250 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
251 ((num_cores - 1) << 26) |
252 ((num_apic_ids - 1) << 14);
253
254 assert(cache->line_size > 0);
255 assert(cache->partitions > 0);
256 assert(cache->associativity > 0);
257 /* We don't implement fully-associative caches */
258 assert(cache->associativity < cache->sets);
259 *ebx = (cache->line_size - 1) |
260 ((cache->partitions - 1) << 12) |
261 ((cache->associativity - 1) << 22);
262
263 assert(cache->sets > 0);
264 *ecx = cache->sets - 1;
265
266 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
267 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
268 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
269}
270
271/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
272static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
273{
274 assert(cache->size % 1024 == 0);
275 assert(cache->lines_per_tag > 0);
276 assert(cache->associativity > 0);
277 assert(cache->line_size > 0);
278 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
279 (cache->lines_per_tag << 8) | (cache->line_size);
280}
5e891bf8
EH		 281
282#define ASSOC_FULL 0xFF
283
284/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
285#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
286 a == 2 ? 0x2 : \
287 a == 4 ? 0x4 : \
288 a == 8 ? 0x6 : \
289 a == 16 ? 0x8 : \
290 a == 32 ? 0xA : \
291 a == 48 ? 0xB : \
292 a == 64 ? 0xC : \
293 a == 96 ? 0xD : \
294 a == 128 ? 0xE : \
295 a == ASSOC_FULL ? 0xF : \
296 0 /* invalid value */)
297
7e3482f8
EH		 298/*
299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
300 * @l3 can be NULL.
301 */
302static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
303 CPUCacheInfo *l3,
304 uint32_t *ecx, uint32_t *edx)
305{
306 assert(l2->size % 1024 == 0);
307 assert(l2->associativity > 0);
308 assert(l2->lines_per_tag > 0);
309 assert(l2->line_size > 0);
310 *ecx = ((l2->size / 1024) << 16) |
311 (AMD_ENC_ASSOC(l2->associativity) << 12) |
312 (l2->lines_per_tag << 8) | (l2->line_size);
313
314 if (l3) {
315 assert(l3->size % (512 * 1024) == 0);
316 assert(l3->associativity > 0);
317 assert(l3->lines_per_tag > 0);
318 assert(l3->line_size > 0);
319 *edx = ((l3->size / (512 * 1024)) << 18) |
320 (AMD_ENC_ASSOC(l3->associativity) << 12) |
321 (l3->lines_per_tag << 8) | (l3->line_size);
322 } else {
323 *edx = 0;
324 }
325}
5e891bf8 326
8f4202fb 327/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 328static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
329 X86CPUTopoInfo *topo_info,
330 uint32_t *eax, uint32_t *ebx,
331 uint32_t *ecx, uint32_t *edx)
8f4202fb 332{
2f084d1e 333 uint32_t l3_threads;
8f4202fb
BM		 334 assert(cache->size == cache->line_size * cache->associativity *
335 cache->partitions * cache->sets);
336
337 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
338 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
339
340 /* L3 is shared among multiple cores */
341 if (cache->level == 3) {
2f084d1e
BM		 342 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
343 *eax |= (l3_threads - 1) << 14;
8f4202fb 344 } else {
2f084d1e 345 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 346 }
347
348 assert(cache->line_size > 0);
349 assert(cache->partitions > 0);
350 assert(cache->associativity > 0);
351 /* We don't implement fully-associative caches */
352 assert(cache->associativity < cache->sets);
353 *ebx = (cache->line_size - 1) |
354 ((cache->partitions - 1) << 12) |
355 ((cache->associativity - 1) << 22);
356
357 assert(cache->sets > 0);
358 *ecx = cache->sets - 1;
359
360 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
361 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
362 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
363}
364
ed78467a 365/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 366static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
367 uint32_t *eax, uint32_t *ebx,
368 uint32_t *ecx, uint32_t *edx)
ed78467a 369{
31ada106
BM		 370 X86CPUTopoIDs topo_ids;
371
372 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 373
ed78467a 374 *eax = cpu->apic_id;
31ada106 375
ed78467a 376 /*
31ada106
BM		 377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
378 * Read-only. Reset: 0000_XXXXh.
379 * See Core::X86::Cpuid::ExtApicId.
380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
381 * Bits Description
382 * 31:16 Reserved.
383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
384 * The number of threads per core is ThreadsPerCore+1.
385 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
386 *
387 * NOTE: CoreId is already part of apic_id. Just use it. We can
388 * use all the 8 bits to represent the core_id here.
ed78467a 389 */
31ada106
BM		 390 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
391
ed78467a 392 /*
31ada106
BM		 393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
394 * Read-only. Reset: 0000_0XXXh.
395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
396 * Bits Description
397 * 31:11 Reserved.
398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
399 * ValidValues:
400 * Value Description
401 * 000b 1 node per processor.
402 * 001b 2 nodes per processor.
403 * 010b Reserved.
404 * 011b 4 nodes per processor.
405 * 111b-100b Reserved.
406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
407 *
408 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
409 * But users can create more nodes than the actual hardware can
410 * support. To genaralize we can use all the upper 8 bits for nodes.
411 * NodeId is combination of node and socket_id which is already decoded
412 * in apic_id. Just use it by shifting.
ed78467a 413 */
31ada106
BM		 414 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
415 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
416
ed78467a
BM		 417 *edx = 0;
418}
419
ab8f992e
BM		 420/*
421 * Definitions of the hardcoded cache entries we expose:
422 * These are legacy cache values. If there is a need to change any
423 * of these values please use builtin_x86_defs
424 */
5e891bf8
EH		 425
426/* L1 data cache: */
ab8f992e 427static CPUCacheInfo legacy_l1d_cache = {
5f00335a 428 .type = DATA_CACHE,
7e3482f8
EH		 429 .level = 1,
430 .size = 32 * KiB,
431 .self_init = 1,
432 .line_size = 64,
433 .associativity = 8,
434 .sets = 64,
435 .partitions = 1,
436 .no_invd_sharing = true,
437};
438
5e891bf8 439/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 440static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 441 .type = DATA_CACHE,
7e3482f8
EH		 442 .level = 1,
443 .size = 64 * KiB,
444 .self_init = 1,
445 .line_size = 64,
446 .associativity = 2,
447 .sets = 512,
448 .partitions = 1,
449 .lines_per_tag = 1,
450 .no_invd_sharing = true,
451};
5e891bf8
EH		 452
453/* L1 instruction cache: */
ab8f992e 454static CPUCacheInfo legacy_l1i_cache = {
5f00335a 455 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 456 .level = 1,
457 .size = 32 * KiB,
458 .self_init = 1,
459 .line_size = 64,
460 .associativity = 8,
461 .sets = 64,
462 .partitions = 1,
463 .no_invd_sharing = true,
464};
465
5e891bf8 466/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 467static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 468 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 469 .level = 1,
470 .size = 64 * KiB,
471 .self_init = 1,
472 .line_size = 64,
473 .associativity = 2,
474 .sets = 512,
475 .partitions = 1,
476 .lines_per_tag = 1,
477 .no_invd_sharing = true,
478};
5e891bf8
EH		 479
480/* Level 2 unified cache: */
ab8f992e 481static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 482 .type = UNIFIED_CACHE,
483 .level = 2,
484 .size = 4 * MiB,
485 .self_init = 1,
486 .line_size = 64,
487 .associativity = 16,
488 .sets = 4096,
489 .partitions = 1,
490 .no_invd_sharing = true,
491};
492
5e891bf8 493/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 494static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 495 .type = UNIFIED_CACHE,
496 .level = 2,
497 .size = 2 * MiB,
498 .line_size = 64,
499 .associativity = 8,
500};
501
502
5e891bf8 503/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 504static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 505 .type = UNIFIED_CACHE,
506 .level = 2,
507 .size = 512 * KiB,
508 .line_size = 64,
509 .lines_per_tag = 1,
510 .associativity = 16,
511 .sets = 512,
512 .partitions = 1,
513};
5e891bf8 514
14c985cf 515/* Level 3 unified cache: */
ab8f992e 516static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 517 .type = UNIFIED_CACHE,
518 .level = 3,
519 .size = 16 * MiB,
520 .line_size = 64,
521 .associativity = 16,
522 .sets = 16384,
523 .partitions = 1,
524 .lines_per_tag = 1,
525 .self_init = true,
526 .inclusive = true,
527 .complex_indexing = true,
528};
5e891bf8
EH		 529
530/* TLB definitions: */
531
532#define L1_DTLB_2M_ASSOC 1
533#define L1_DTLB_2M_ENTRIES 255
534#define L1_DTLB_4K_ASSOC 1
535#define L1_DTLB_4K_ENTRIES 255
536
537#define L1_ITLB_2M_ASSOC 1
538#define L1_ITLB_2M_ENTRIES 255
539#define L1_ITLB_4K_ASSOC 1
540#define L1_ITLB_4K_ENTRIES 255
541
542#define L2_DTLB_2M_ASSOC 0 /* disabled */
543#define L2_DTLB_2M_ENTRIES 0 /* disabled */
544#define L2_DTLB_4K_ASSOC 4
545#define L2_DTLB_4K_ENTRIES 512
546
547#define L2_ITLB_2M_ASSOC 0 /* disabled */
548#define L2_ITLB_2M_ENTRIES 0 /* disabled */
549#define L2_ITLB_4K_ASSOC 4
550#define L2_ITLB_4K_ENTRIES 512
551
e37a5c7f
CP		 552/* CPUID Leaf 0x14 constants: */
553#define INTEL_PT_MAX_SUBLEAF 0x1
554/*
555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
556 * MSR can be accessed;
557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
559 * of Intel PT MSRs across warm reset;
560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
561 */
562#define INTEL_PT_MINIMAL_EBX 0xf
563/*
564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
566 * accessed;
567 * bit[01]: ToPA tables can hold any number of output entries, up to the
568 * maximum allowed by the MaskOrTableOffset field of
569 * IA32_RTIT_OUTPUT_MASK_PTRS;
570 * bit[02]: Support Single-Range Output scheme;
571 */
572#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 573/* generated packets which contain IP payloads have LIP values */
574#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 575#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
576#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
577#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
578#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
579#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 580
f21a4817
JL		 581/* CPUID Leaf 0x1D constants: */
582#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
583#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
584#define INTEL_AMX_BYTES_PER_TILE 0x400
585#define INTEL_AMX_BYTES_PER_ROW 0x40
586#define INTEL_AMX_TILE_MAX_NAMES 0x8
587#define INTEL_AMX_TILE_MAX_ROWS 0x10
588
589/* CPUID Leaf 0x1E constants: */
590#define INTEL_AMX_TMUL_MAX_K 0x10
591#define INTEL_AMX_TMUL_MAX_N 0x40
592
f5cc5a5c
CF		 593void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
594 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 595{
596 int i;
597 for (i = 0; i < 4; i++) {
598 dst[i] = vendor1 >> (8 * i);
599 dst[i + 4] = vendor2 >> (8 * i);
600 dst[i + 8] = vendor3 >> (8 * i);
601 }
602 dst[CPUID_VENDOR_SZ] = '\0';
603}
604
621626ce
EH		 605#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
606#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
608#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
610 CPUID_PSE36 | CPUID_FXSR)
611#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
612#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
615 CPUID_PAE | CPUID_SEP | CPUID_APIC)
616
617#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 622 /* partly implemented:
623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
624 /* missing:
625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
626#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
627 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
628 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 629 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca 630 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
2872b0f3
PB		 631 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
632 CPUID_EXT_FMA)
621626ce
EH		 633 /* missing:
634 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
2872b0f3 635 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
621626ce 636 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
cf5ec664 637 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
621626ce
EH		 638
639#ifdef TARGET_X86_64
63fd8ef0 640#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
621626ce
EH		 641#else
642#define TCG_EXT2_X86_64_FEATURES 0
643#endif
644
645#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
646 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
63fd8ef0 648 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
621626ce 649#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
8afce497
PB		 650 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
651 CPUID_EXT3_3DNOWPREFETCH)
621626ce 652#define TCG_EXT4_FEATURES 0
900eeca5
LL		 653#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
654 CPUID_SVM_SVME_ADDR_CHK)
621626ce
EH		 655#define TCG_KVM_FEATURES 0
656#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386 659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
691925e5 660 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
621626ce 661 /* missing:
2f8a21d8 662 CPUID_7_0_EBX_HLE
691925e5 663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
6750485b
PB		 664
665#if defined CONFIG_SOFTMMU || defined CONFIG_LINUX
666#define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
667#else
668#define TCG_7_0_ECX_RDPID 0
669#endif
637f1ee3 670#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
9ccb9784 671 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6750485b
PB		 672 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
673 TCG_7_0_ECX_RDPID)
674
c0728d4e 675#define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
58794f64
PB		 676#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
677 CPUID_7_1_EAX_FSRC)
eaaa197d 678#define TCG_7_1_EDX_FEATURES 0
303752a9 679#define TCG_APM_FEATURES 0
28b8e4d0 680#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 681#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
682 /* missing:
683 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 684#define TCG_14_0_ECX_FEATURES 0
4b841a79 685#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 686#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 687#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 688
431c51e9
PB		 689#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
690 CPUID_8000_0008_EBX_WBNOINVD)
1420dd6a 691
79f1a68a 692FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 693 [FEAT_1_EDX] = {
07585923 694 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 695 .feat_names = {
696 "fpu", "vme", "de", "pse",
697 "tsc", "msr", "pae", "mce",
698 "cx8", "apic", NULL, "sep",
699 "mtrr", "pge", "mca", "cmov",
700 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
701 NULL, "ds" /* Intel dts */, "acpi", "mmx",
702 "fxsr", "sse", "sse2", "ss",
703 "ht" /* Intel htt */, "tm", "ia64", "pbe",
704 },
07585923 705 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 706 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 707 },
708 [FEAT_1_ECX] = {
07585923 709 .type = CPUID_FEATURE_WORD,
2d5312da 710 .feat_names = {
16d2fcaa 711 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 712 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 713 "tm2", "ssse3", "cid", NULL,
714 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 715 NULL, "pcid", "dca", "sse4.1",
716 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 717 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 718 "avx", "f16c", "rdrand", "hypervisor",
719 },
07585923 720 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 721 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 722 },
2d5312da
EH		 723 /* Feature names that are already defined on feature_name[] but
724 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
725 * names on feat_names below. They are copied automatically
726 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
727 */
bffd67b0 728 [FEAT_8000_0001_EDX] = {
07585923 729 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 730 .feat_names = {
731 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
732 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
733 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
734 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
735 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 736 "nx", NULL, "mmxext", NULL /* mmx */,
737 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
738 NULL, "lm", "3dnowext", "3dnow",
2d5312da 739 },
07585923 740 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 741 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 742 },
743 [FEAT_8000_0001_ECX] = {
07585923 744 .type = CPUID_FEATURE_WORD,
2d5312da 745 .feat_names = {
fc7dfd20 746 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 747 "cr8legacy", "abm", "sse4a", "misalignsse",
748 "3dnowprefetch", "osvw", "ibs", "xop",
749 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 750 "fma4", "tce", NULL, "nodeid-msr",
751 NULL, "tbm", "topoext", "perfctr-core",
752 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 753 NULL, NULL, NULL, NULL,
754 },
07585923 755 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 756 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 757 /*
758 * TOPOEXT is always allowed but can't be enabled blindly by
759 * "-cpu host", as it requires consistent cache topology info
760 * to be provided so it doesn't confuse guests.
761 */
762 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 763 },
89e49c8b 764 [FEAT_C000_0001_EDX] = {
07585923 765 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 766 .feat_names = {
767 NULL, NULL, "xstore", "xstore-en",
768 NULL, NULL, "xcrypt", "xcrypt-en",
769 "ace2", "ace2-en", "phe", "phe-en",
770 "pmm", "pmm-en", NULL, NULL,
771 NULL, NULL, NULL, NULL,
772 NULL, NULL, NULL, NULL,
773 NULL, NULL, NULL, NULL,
774 NULL, NULL, NULL, NULL,
775 },
07585923 776 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 777 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 778 },
bffd67b0 779 [FEAT_KVM] = {
07585923 780 .type = CPUID_FEATURE_WORD,
2d5312da 781 .feat_names = {
fc7dfd20
EH		 782 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
783 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 784 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 785 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 786 NULL, NULL, NULL, NULL,
787 NULL, NULL, NULL, NULL,
788 "kvmclock-stable-bit", NULL, NULL, NULL,
789 NULL, NULL, NULL, NULL,
790 },
07585923 791 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 792 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 793 },
be777326 794 [FEAT_KVM_HINTS] = {
07585923 795 .type = CPUID_FEATURE_WORD,
be777326
WL		 796 .feat_names = {
797 "kvm-hint-dedicated", NULL, NULL, NULL,
798 NULL, NULL, NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
803 NULL, NULL, NULL, NULL,
804 NULL, NULL, NULL, NULL,
805 },
07585923 806 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 807 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 808 /*
809 * KVM hints aren't auto-enabled by -cpu host, they need to be
810 * explicitly enabled in the command-line.
811 */
812 .no_autoenable_flags = ~0U,
be777326 813 },
bffd67b0 814 [FEAT_SVM] = {
07585923 815 .type = CPUID_FEATURE_WORD,
2d5312da 816 .feat_names = {
fc7dfd20
EH		 817 "npt", "lbrv", "svm-lock", "nrip-save",
818 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
819 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 820 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
821 "vgif", NULL, NULL, NULL,
2d5312da 822 NULL, NULL, NULL, NULL,
62a798d4 823 NULL, "vnmi", NULL, NULL,
5447089c 824 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 825 },
07585923 826 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 827 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 828 },
829 [FEAT_7_0_EBX] = {
07585923 830 .type = CPUID_FEATURE_WORD,
2d5312da 831 .feat_names = {
5c76b651 832 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 833 "hle", "avx2", NULL, "smep",
834 "bmi2", "erms", "invpcid", "rtm",
835 NULL, NULL, "mpx", NULL,
836 "avx512f", "avx512dq", "rdseed", "adx",
837 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 838 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 839 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 840 },
07585923
RH		 841 .cpuid = {
842 .eax = 7,
843 .needs_ecx = true, .ecx = 0,
844 .reg = R_EBX,
845 },
37ce3522 846 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 847 },
f74eefe0 848 [FEAT_7_0_ECX] = {
07585923 849 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 850 .feat_names = {
851 NULL, "avx512vbmi", "umip", "pku",
67192a29 852 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 853 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
854 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 855 "la57", NULL, NULL, NULL,
2d5312da 856 NULL, NULL, "rdpid", NULL,
06e878b4 857 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 858 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 859 },
07585923
RH		 860 .cpuid = {
861 .eax = 7,
862 .needs_ecx = true, .ecx = 0,
863 .reg = R_ECX,
864 },
f74eefe0
HH		 865 .tcg_features = TCG_7_0_ECX_FEATURES,
866 },
95ea69fb 867 [FEAT_7_0_EDX] = {
07585923 868 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 869 .feat_names = {
870 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 871 "fsrm", NULL, NULL, NULL,
353f98c9 872 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 873 NULL, NULL, "serialize", NULL,
c3c67679 874 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
f21a4817
JL		 875 NULL, NULL, "amx-bf16", "avx512-fp16",
876 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
0e7e3bf1 877 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
95ea69fb 878 },
07585923
RH		 879 .cpuid = {
880 .eax = 7,
881 .needs_ecx = true, .ecx = 0,
882 .reg = R_EDX,
883 },
95ea69fb
LK		 884 .tcg_features = TCG_7_0_EDX_FEATURES,
885 },
80db491d
JL		 886 [FEAT_7_1_EAX] = {
887 .type = CPUID_FEATURE_WORD,
888 .feat_names = {
889 NULL, NULL, NULL, NULL,
a9ce107f 890 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
58794f64
PB		 891 NULL, NULL, "fzrm", "fsrs",
892 "fsrc", NULL, NULL, NULL,
80db491d 893 NULL, NULL, NULL, NULL,
a957a884 894 NULL, "amx-fp16", NULL, "avx-ifma",
80db491d
JL		 895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 },
898 .cpuid = {
899 .eax = 7,
900 .needs_ecx = true, .ecx = 1,
901 .reg = R_EAX,
902 },
903 .tcg_features = TCG_7_1_EAX_FEATURES,
904 },
eaaa197d
JC		 905 [FEAT_7_1_EDX] = {
906 .type = CPUID_FEATURE_WORD,
907 .feat_names = {
908 NULL, NULL, NULL, NULL,
ecd2e6ca 909 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
eaaa197d 910 NULL, NULL, NULL, NULL,
d1a11115 911 NULL, NULL, "prefetchiti", NULL,
eaaa197d
JC		 912 NULL, NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
914 NULL, NULL, NULL, NULL,
915 NULL, NULL, NULL, NULL,
916 },
917 .cpuid = {
918 .eax = 7,
919 .needs_ecx = true, .ecx = 1,
920 .reg = R_EDX,
921 },
922 .tcg_features = TCG_7_1_EDX_FEATURES,
923 },
303752a9 924 [FEAT_8000_0007_EDX] = {
07585923 925 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 926 .feat_names = {
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 "invtsc", NULL, NULL, NULL,
930 NULL, NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 NULL, NULL, NULL, NULL,
933 NULL, NULL, NULL, NULL,
934 NULL, NULL, NULL, NULL,
935 },
07585923 936 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 937 .tcg_features = TCG_APM_FEATURES,
938 .unmigratable_flags = CPUID_APM_INVTSC,
939 },
1b3420e1 940 [FEAT_8000_0008_EBX] = {
07585923 941 .type = CPUID_FEATURE_WORD,
1b3420e1 942 .feat_names = {
e900135d 943 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 944 NULL, NULL, NULL, NULL,
59a80a19 945 NULL, "wbnoinvd", NULL, NULL,
623972ce 946 "ibpb", NULL, "ibrs", "amd-stibp",
bb039a23 947 NULL, "stibp-always-on", NULL, NULL,
1b3420e1 948 NULL, NULL, NULL, NULL,
254790a9 949 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
bb039a23 950 "amd-psfd", NULL, NULL, NULL,
1b3420e1 951 },
07585923 952 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1420dd6a 953 .tcg_features = TCG_8000_0008_EBX,
1b3420e1
EH		 954 .unmigratable_flags = 0,
955 },
b70eec31
BM		 956 [FEAT_8000_0021_EAX] = {
957 .type = CPUID_FEATURE_WORD,
958 .feat_names = {
959 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
960 NULL, NULL, "null-sel-clr-base", NULL,
62a798d4 961 "auto-ibrs", NULL, NULL, NULL,
b70eec31
BM		 962 NULL, NULL, NULL, NULL,
963 NULL, NULL, NULL, NULL,
964 NULL, NULL, NULL, NULL,
965 NULL, NULL, NULL, NULL,
966 NULL, NULL, NULL, NULL,
967 },
968 .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
969 .tcg_features = 0,
970 .unmigratable_flags = 0,
971 },
0bb0b2d2 972 [FEAT_XSAVE] = {
07585923 973 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 974 .feat_names = {
975 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
f21a4817 976 "xfd", NULL, NULL, NULL,
2d5312da
EH		 977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 NULL, NULL, NULL, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, NULL, NULL,
982 NULL, NULL, NULL, NULL,
983 },
07585923
RH		 984 .cpuid = {
985 .eax = 0xd,
986 .needs_ecx = true, .ecx = 1,
987 .reg = R_EAX,
988 },
c9cfe8f9 989 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 990 },
301e9067
YW		 991 [FEAT_XSAVE_XSS_LO] = {
992 .type = CPUID_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, NULL, NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .cpuid = {
1004 .eax = 0xD,
1005 .needs_ecx = true,
1006 .ecx = 1,
1007 .reg = R_ECX,
1008 },
1009 },
1010 [FEAT_XSAVE_XSS_HI] = {
1011 .type = CPUID_FEATURE_WORD,
1012 .cpuid = {
1013 .eax = 0xD,
1014 .needs_ecx = true,
1015 .ecx = 1,
1016 .reg = R_EDX
1017 },
1018 },
28b8e4d0 1019 [FEAT_6_EAX] = {
07585923 1020 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1021 .feat_names = {
1022 NULL, NULL, "arat", NULL,
1023 NULL, NULL, NULL, NULL,
1024 NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 NULL, NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 },
07585923 1031 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1032 .tcg_features = TCG_6_EAX_FEATURES,
1033 },
301e9067 1034 [FEAT_XSAVE_XCR0_LO] = {
07585923
RH		 1035 .type = CPUID_FEATURE_WORD,
1036 .cpuid = {
1037 .eax = 0xD,
1038 .needs_ecx = true, .ecx = 0,
1039 .reg = R_EAX,
1040 },
96193c22 1041 .tcg_features = ~0U,
6fb2fff7
EH		 1042 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1043 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1044 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1045 XSTATE_PKRU_MASK,
96193c22 1046 },
301e9067 1047 [FEAT_XSAVE_XCR0_HI] = {
07585923
RH		 1048 .type = CPUID_FEATURE_WORD,
1049 .cpuid = {
1050 .eax = 0xD,
1051 .needs_ecx = true, .ecx = 0,
1052 .reg = R_EDX,
1053 },
96193c22
EH		 1054 .tcg_features = ~0U,
1055 },
d86f9636
RH		 1056 /*Below are MSR exposed features*/
1057 [FEAT_ARCH_CAPABILITIES] = {
1058 .type = MSR_FEATURE_WORD,
1059 .feat_names = {
1060 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1061 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1062 "taa-no", NULL, NULL, NULL,
5bef742c 1063 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
22e1094c 1064 NULL, "fb-clear", NULL, NULL,
d86f9636 1065 NULL, NULL, NULL, NULL,
5bef742c 1066 "pbrsb-no", NULL, NULL, NULL,
d86f9636
RH		 1067 NULL, NULL, NULL, NULL,
1068 },
1069 .msr = {
1070 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 1071 },
1072 },
597360c0
XL		 1073 [FEAT_CORE_CAPABILITY] = {
1074 .type = MSR_FEATURE_WORD,
1075 .feat_names = {
1076 NULL, NULL, NULL, NULL,
1077 NULL, "split-lock-detect", NULL, NULL,
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL,
1084 },
1085 .msr = {
1086 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1087 },
1088 },
ea39f9b6
LX		 1089 [FEAT_PERF_CAPABILITIES] = {
1090 .type = MSR_FEATURE_WORD,
1091 .feat_names = {
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, "full-width-write", NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL,
1100 },
1101 .msr = {
1102 .index = MSR_IA32_PERF_CAPABILITIES,
1103 },
1104 },
20a78b02
PB		 1105
1106 [FEAT_VMX_PROCBASED_CTLS] = {
1107 .type = MSR_FEATURE_WORD,
1108 .feat_names = {
1109 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1110 NULL, NULL, NULL, "vmx-hlt-exit",
1111 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1112 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1113 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1114 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1115 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1116 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1117 },
1118 .msr = {
1119 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1120 }
1121 },
1122
1123 [FEAT_VMX_SECONDARY_CTLS] = {
1124 .type = MSR_FEATURE_WORD,
1125 .feat_names = {
1126 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1127 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1128 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1129 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1130 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1131 "vmx-xsaves", NULL, NULL, NULL,
9ce8af4d 1132 NULL, "vmx-tsc-scaling", NULL, NULL,
20a78b02
PB		 1133 NULL, NULL, NULL, NULL,
1134 },
1135 .msr = {
1136 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1137 }
1138 },
1139
1140 [FEAT_VMX_PINBASED_CTLS] = {
1141 .type = MSR_FEATURE_WORD,
1142 .feat_names = {
1143 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1144 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1145 NULL, NULL, NULL, NULL,
1146 NULL, NULL, NULL, NULL,
1147 NULL, NULL, NULL, NULL,
1148 NULL, NULL, NULL, NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 },
1152 .msr = {
1153 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1154 }
1155 },
1156
1157 [FEAT_VMX_EXIT_CTLS] = {
1158 .type = MSR_FEATURE_WORD,
1159 /*
1160 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1161 * the LM CPUID bit.
1162 */
1163 .feat_names = {
1164 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1165 NULL, NULL, NULL, NULL,
1166 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1167 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1168 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1169 "vmx-exit-save-efer", "vmx-exit-load-efer",
1170 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1171 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1172 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1173 },
1174 .msr = {
1175 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1176 }
1177 },
1178
1179 [FEAT_VMX_ENTRY_CTLS] = {
1180 .type = MSR_FEATURE_WORD,
1181 .feat_names = {
1182 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1183 NULL, NULL, NULL, NULL,
1184 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1185 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1186 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1187 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 },
1191 .msr = {
1192 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1193 }
1194 },
1195
1196 [FEAT_VMX_MISC] = {
1197 .type = MSR_FEATURE_WORD,
1198 .feat_names = {
1199 NULL, NULL, NULL, NULL,
1200 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1201 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1202 NULL, NULL, NULL, NULL,
1203 NULL, NULL, NULL, NULL,
1204 NULL, NULL, NULL, NULL,
1205 NULL, NULL, NULL, NULL,
1206 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1207 },
1208 .msr = {
1209 .index = MSR_IA32_VMX_MISC,
1210 }
1211 },
1212
1213 [FEAT_VMX_EPT_VPID_CAPS] = {
1214 .type = MSR_FEATURE_WORD,
1215 .feat_names = {
1216 "vmx-ept-execonly", NULL, NULL, NULL,
1217 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL,
1220 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1221 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1222 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1223 NULL, NULL, NULL, NULL,
1224 "vmx-invvpid", NULL, NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1227 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1228 NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL,
1230 NULL, NULL, NULL, NULL,
1231 NULL, NULL, NULL, NULL,
1232 NULL, NULL, NULL, NULL,
1233 },
1234 .msr = {
1235 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1236 }
1237 },
1238
1239 [FEAT_VMX_BASIC] = {
1240 .type = MSR_FEATURE_WORD,
1241 .feat_names = {
1242 [54] = "vmx-ins-outs",
1243 [55] = "vmx-true-ctls",
1244 },
1245 .msr = {
1246 .index = MSR_IA32_VMX_BASIC,
1247 },
1248 /* Just to be safe - we don't support setting the MSEG version field. */
1249 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1250 },
1251
1252 [FEAT_VMX_VMFUNC] = {
1253 .type = MSR_FEATURE_WORD,
1254 .feat_names = {
1255 [0] = "vmx-eptp-switching",
1256 },
1257 .msr = {
1258 .index = MSR_IA32_VMX_VMFUNC,
1259 }
1260 },
1261
d1615ea5
LK		 1262 [FEAT_14_0_ECX] = {
1263 .type = CPUID_FEATURE_WORD,
1264 .feat_names = {
1265 NULL, NULL, NULL, NULL,
1266 NULL, NULL, NULL, NULL,
1267 NULL, NULL, NULL, NULL,
1268 NULL, NULL, NULL, NULL,
1269 NULL, NULL, NULL, NULL,
1270 NULL, NULL, NULL, NULL,
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, "intel-pt-lip",
1273 },
1274 .cpuid = {
1275 .eax = 0x14,
1276 .needs_ecx = true, .ecx = 0,
1277 .reg = R_ECX,
1278 },
1279 .tcg_features = TCG_14_0_ECX_FEATURES,
1280 },
1281
4b841a79
SC		 1282 [FEAT_SGX_12_0_EAX] = {
1283 .type = CPUID_FEATURE_WORD,
1284 .feat_names = {
1285 "sgx1", "sgx2", NULL, NULL,
1286 NULL, NULL, NULL, NULL,
d45f24fe 1287 NULL, NULL, NULL, "sgx-edeccssa",
4b841a79
SC		 1288 NULL, NULL, NULL, NULL,
1289 NULL, NULL, NULL, NULL,
1290 NULL, NULL, NULL, NULL,
1291 NULL, NULL, NULL, NULL,
1292 NULL, NULL, NULL, NULL,
1293 },
1294 .cpuid = {
1295 .eax = 0x12,
1296 .needs_ecx = true, .ecx = 0,
1297 .reg = R_EAX,
1298 },
1299 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1300 },
120ca112
SC		 1301
1302 [FEAT_SGX_12_0_EBX] = {
1303 .type = CPUID_FEATURE_WORD,
1304 .feat_names = {
1305 "sgx-exinfo" , NULL, NULL, NULL,
1306 NULL, NULL, NULL, NULL,
1307 NULL, NULL, NULL, NULL,
1308 NULL, NULL, NULL, NULL,
1309 NULL, NULL, NULL, NULL,
1310 NULL, NULL, NULL, NULL,
1311 NULL, NULL, NULL, NULL,
1312 NULL, NULL, NULL, NULL,
1313 },
1314 .cpuid = {
1315 .eax = 0x12,
1316 .needs_ecx = true, .ecx = 0,
1317 .reg = R_EBX,
1318 },
1319 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1320 },
165981a5
SC		 1321
1322 [FEAT_SGX_12_1_EAX] = {
1323 .type = CPUID_FEATURE_WORD,
1324 .feat_names = {
1325 NULL, "sgx-debug", "sgx-mode64", NULL,
1326 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
d45f24fe 1327 NULL, NULL, "sgx-aex-notify", NULL,
165981a5
SC		 1328 NULL, NULL, NULL, NULL,
1329 NULL, NULL, NULL, NULL,
1330 NULL, NULL, NULL, NULL,
1331 NULL, NULL, NULL, NULL,
1332 NULL, NULL, NULL, NULL,
1333 },
1334 .cpuid = {
1335 .eax = 0x12,
1336 .needs_ecx = true, .ecx = 1,
1337 .reg = R_EAX,
1338 },
1339 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1340 },
5ef57876
EH		 1341};
1342
99e24dbd
PB		 1343typedef struct FeatureMask {
1344 FeatureWord index;
ede146c2 1345 uint64_t mask;
99e24dbd
PB		 1346} FeatureMask;
1347
1348typedef struct FeatureDep {
1349 FeatureMask from, to;
1350} FeatureDep;
1351
1352static FeatureDep feature_dependencies[] = {
1353 {
1354 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1355 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1356 },
1357 {
1358 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1359 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1360 },
ea39f9b6
LX		 1361 {
1362 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1363 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1364 },
20a78b02
PB		 1365 {
1366 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1367 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1368 },
1369 {
1370 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1371 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1372 },
1373 {
1374 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1375 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1376 },
1377 {
1378 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1379 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1380 },
1381 {
1382 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1383 .to = { FEAT_VMX_MISC, ~0ull },
1384 },
1385 {
1386 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1387 .to = { FEAT_VMX_BASIC, ~0ull },
1388 },
1389 {
1390 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1391 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1392 },
1393 {
1394 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1395 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1396 },
1397 {
1398 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1399 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1400 },
1401 {
1402 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1403 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1404 },
1405 {
1406 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1407 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1408 },
267b5e7e
MS		 1409 {
1410 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1411 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS },
1412 },
1413 {
1414 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1415 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS },
1416 },
20a78b02
PB		 1417 {
1418 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1419 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1420 },
d1615ea5
LK		 1421 {
1422 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1423 .to = { FEAT_14_0_ECX, ~0ull },
1424 },
20a78b02
PB		 1425 {
1426 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1427 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1428 },
1429 {
1430 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1431 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1432 },
1433 {
1434 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1435 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1436 },
1437 {
1438 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1439 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1440 },
1441 {
1442 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1443 .to = { FEAT_VMX_VMFUNC, ~0ull },
1444 },
730319ae
EH		 1445 {
1446 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1447 .to = { FEAT_SVM, ~0ull },
1448 },
99e24dbd
PB		 1449};
1450
8e8aba50
EH		 1451typedef struct X86RegisterInfo32 {
1452 /* Name of register */
1453 const char *name;
1454 /* QAPI enum value register */
1455 X86CPURegister32 qapi_enum;
1456} X86RegisterInfo32;
1457
1458#define REGISTER(reg) \
5d371f41 1459 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1460static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1461 REGISTER(EAX),
1462 REGISTER(ECX),
1463 REGISTER(EDX),
1464 REGISTER(EBX),
1465 REGISTER(ESP),
1466 REGISTER(EBP),
1467 REGISTER(ESI),
1468 REGISTER(EDI),
1469};
1470#undef REGISTER
1471
301e9067 1472/* CPUID feature bits available in XSS */
10f0abcb 1473#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
301e9067 1474
fea45008 1475ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1476 [XSTATE_FP_BIT] = {
1477 /* x87 FP state component is always enabled if XSAVE is supported */
1478 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1479 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1480 },
1481 [XSTATE_SSE_BIT] = {
1482 /* SSE state component is always enabled if XSAVE is supported */
1483 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1484 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1485 },
cfc3b074
PB		 1486 [XSTATE_YMM_BIT] =
1487 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1488 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1489 [XSTATE_BNDREGS_BIT] =
1490 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1491 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1492 [XSTATE_BNDCSR_BIT] =
1493 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1494 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1495 [XSTATE_OPMASK_BIT] =
1496 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1497 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1498 [XSTATE_ZMM_Hi256_BIT] =
1499 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1500 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1501 [XSTATE_Hi16_ZMM_BIT] =
1502 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1503 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1504 [XSTATE_PKRU_BIT] =
1505 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1506 .size = sizeof(XSavePKRU) },
10f0abcb
YW		 1507 [XSTATE_ARCH_LBR_BIT] = {
1508 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
1509 .offset = 0 /*supervisor mode component, offset = 0 */,
1510 .size = sizeof(XSavesArchLBR) },
1f16764f
JL		 1511 [XSTATE_XTILE_CFG_BIT] = {
1512 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1513 .size = sizeof(XSaveXTILECFG),
1514 },
1515 [XSTATE_XTILE_DATA_BIT] = {
1516 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1517 .size = sizeof(XSaveXTILEDATA)
1518 },
2560f19f 1519};
8e8aba50 1520
5d245678 1521uint32_t xsave_area_size(uint64_t mask, bool compacted)
1fda6198 1522{
301e9067
YW		 1523 uint64_t ret = x86_ext_save_areas[0].size;
1524 const ExtSaveArea *esa;
1525 uint32_t offset = 0;
1fda6198 1526 int i;
1fda6198 1527
301e9067
YW		 1528 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1529 esa = &x86_ext_save_areas[i];
1fda6198 1530 if ((mask >> i) & 1) {
301e9067
YW		 1531 offset = compacted ? ret : esa->offset;
1532 ret = MAX(ret, offset + esa->size);
1fda6198
EH		 1533 }
1534 }
1535 return ret;
1536}
1537
d6dcc558
SAGDR		 1538static inline bool accel_uses_host_cpuid(void)
1539{
1540 return kvm_enabled() || hvf_enabled();
1541}
1542
301e9067 1543static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu)
96193c22 1544{
301e9067
YW		 1545 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 |
1546 cpu->env.features[FEAT_XSAVE_XCR0_LO];
96193c22
EH		 1547}
1548
ed69e831
CF		 1549/* Return name of 32-bit register, from a R_* constant */
1550static const char *get_register_name_32(unsigned int reg)
8b4beddc 1551{
31ccdde2 1552 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1553 return NULL;
1554 }
8e8aba50 1555 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1556}
1557
301e9067
YW		 1558static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu)
1559{
1560 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 |
1561 cpu->env.features[FEAT_XSAVE_XSS_LO];
1562}
1563
84f1b92f
EH		 1564/*
1565 * Returns the set of feature flags that are supported and migratable by
1566 * QEMU, for a given FeatureWord.
1567 */
ede146c2 1568static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1569{
1570 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1571 uint64_t r = 0;
84f1b92f
EH		 1572 int i;
1573
ede146c2
PB		 1574 for (i = 0; i < 64; i++) {
1575 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1576
1577 /* If the feature name is known, it is implicitly considered migratable,
1578 * unless it is explicitly set in unmigratable_flags */
1579 if ((wi->migratable_flags & f) ||
1580 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1581 r |= f;
84f1b92f 1582 }
84f1b92f
EH		 1583 }
1584 return r;
1585}
1586
bb44e0d1
JK		 1587void host_cpuid(uint32_t function, uint32_t count,
1588 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1589{
a1fd24af
AL		 1590 uint32_t vec[4];
1591
1592#ifdef __x86_64__
1593 asm volatile("cpuid"
1594 : "=a"(vec[0]), "=b"(vec[1]),
1595 "=c"(vec[2]), "=d"(vec[3])
1596 : "0"(function), "c"(count) : "cc");
c1f41226 1597#elif defined(__i386__)
a1fd24af
AL		 1598 asm volatile("pusha \n\t"
1599 "cpuid \n\t"
1600 "mov %%eax, 0(%2) \n\t"
1601 "mov %%ebx, 4(%2) \n\t"
1602 "mov %%ecx, 8(%2) \n\t"
1603 "mov %%edx, 12(%2) \n\t"
1604 "popa"
1605 : : "a"(function), "c"(count), "S"(vec)
1606 : "memory", "cc");
c1f41226
EH		 1607#else
1608 abort();
a1fd24af
AL		 1609#endif
1610
bdde476a 1611 if (eax)
a1fd24af 1612 *eax = vec[0];
bdde476a 1613 if (ebx)
a1fd24af 1614 *ebx = vec[1];
bdde476a 1615 if (ecx)
a1fd24af 1616 *ecx = vec[2];
bdde476a 1617 if (edx)
a1fd24af 1618 *edx = vec[3];
bdde476a 1619}
c6dc6f63 1620
d940ee9b
EH		 1621/* CPU class name definitions: */
1622
d940ee9b
EH		 1623/* Return type name for a given CPU model name
1624 * Caller is responsible for freeing the returned string.
1625 */
1626static char *x86_cpu_type_name(const char *model_name)
1627{
1628 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1629}
1630
500050d1
AF		 1631static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1632{
88703ce2
EH		 1633 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1634 return object_class_by_name(typename);
500050d1
AF		 1635}
1636
104494ea
IM		 1637static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1638{
1639 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1640 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1641 return g_strndup(class_name,
1642 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1643}
1644
dcafd1ef
EH		 1645typedef struct X86CPUVersionDefinition {
1646 X86CPUVersion version;
53db89d9 1647 const char *alias;
c63938df 1648 const char *note;
dcafd1ef 1649 PropValue *props;
cca0a000 1650 const CPUCaches *const cache_info;
dcafd1ef
EH		 1651} X86CPUVersionDefinition;
1652
1653/* Base definition for a CPU model */
1654typedef struct X86CPUDefinition {
c6dc6f63
AP		 1655 const char *name;
1656 uint32_t level;
90e4b0c3 1657 uint32_t xlevel;
99b88a17
IM		 1658 /* vendor is zero-terminated, 12 character ASCII string */
1659 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1660 int family;
1661 int model;
1662 int stepping;
0514ef2f 1663 FeatureWordArray features;
807e9869 1664 const char *model_id;
e845de38 1665 const CPUCaches *const cache_info;
dcafd1ef
EH		 1666 /*
1667 * Definitions for alternative versions of CPU model.
1668 * List is terminated by item with version == 0.
1669 * If NULL, version 1 will be registered automatically.
1670 */
1671 const X86CPUVersionDefinition *versions;
61ad65d0 1672 const char *deprecation_note;
dcafd1ef
EH		 1673} X86CPUDefinition;
1674
1675/* Reference to a specific CPU model version */
1676struct X86CPUModel {
1677 /* Base CPU definition */
e11fd689 1678 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1679 /* CPU model version */
1680 X86CPUVersion version;
c63938df 1681 const char *note;
0788a56b
EH		 1682 /*
1683 * If true, this is an alias CPU model.
1684 * This matters only for "-cpu help" and query-cpu-definitions
1685 */
1686 bool is_alias;
d940ee9b 1687};
c6dc6f63 1688
dcafd1ef 1689/* Get full model name for CPU version */
e11fd689 1690static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1691 X86CPUVersion version)
1692{
1693 assert(version > 0);
1694 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1695}
1696
e11fd689
PMD		 1697static const X86CPUVersionDefinition *
1698x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1699{
1700 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1701 static const X86CPUVersionDefinition default_version_list[] = {
1702 { 1 },
1703 { /* end of list */ }
1704 };
1705
1706 return def->versions ?: default_version_list;
1707}
1708
e845de38 1709static const CPUCaches epyc_cache_info = {
a9f27ea9 1710 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1711 .type = DATA_CACHE,
fe52acd2
BM		 1712 .level = 1,
1713 .size = 32 * KiB,
1714 .line_size = 64,
1715 .associativity = 8,
1716 .partitions = 1,
1717 .sets = 64,
1718 .lines_per_tag = 1,
1719 .self_init = 1,
1720 .no_invd_sharing = true,
1721 },
a9f27ea9 1722 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1723 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1724 .level = 1,
1725 .size = 64 * KiB,
1726 .line_size = 64,
1727 .associativity = 4,
1728 .partitions = 1,
1729 .sets = 256,
1730 .lines_per_tag = 1,
1731 .self_init = 1,
1732 .no_invd_sharing = true,
1733 },
a9f27ea9 1734 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1735 .type = UNIFIED_CACHE,
1736 .level = 2,
1737 .size = 512 * KiB,
1738 .line_size = 64,
1739 .associativity = 8,
1740 .partitions = 1,
1741 .sets = 1024,
1742 .lines_per_tag = 1,
1743 },
a9f27ea9 1744 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1745 .type = UNIFIED_CACHE,
1746 .level = 3,
1747 .size = 8 * MiB,
1748 .line_size = 64,
1749 .associativity = 16,
1750 .partitions = 1,
1751 .sets = 8192,
1752 .lines_per_tag = 1,
1753 .self_init = true,
1754 .inclusive = true,
1755 .complex_indexing = true,
1756 },
1757};
1758
d7c72735
MR		 1759static CPUCaches epyc_v4_cache_info = {
1760 .l1d_cache = &(CPUCacheInfo) {
1761 .type = DATA_CACHE,
1762 .level = 1,
1763 .size = 32 * KiB,
1764 .line_size = 64,
1765 .associativity = 8,
1766 .partitions = 1,
1767 .sets = 64,
1768 .lines_per_tag = 1,
1769 .self_init = 1,
1770 .no_invd_sharing = true,
1771 },
1772 .l1i_cache = &(CPUCacheInfo) {
1773 .type = INSTRUCTION_CACHE,
1774 .level = 1,
1775 .size = 64 * KiB,
1776 .line_size = 64,
1777 .associativity = 4,
1778 .partitions = 1,
1779 .sets = 256,
1780 .lines_per_tag = 1,
1781 .self_init = 1,
1782 .no_invd_sharing = true,
1783 },
1784 .l2_cache = &(CPUCacheInfo) {
1785 .type = UNIFIED_CACHE,
1786 .level = 2,
1787 .size = 512 * KiB,
1788 .line_size = 64,
1789 .associativity = 8,
1790 .partitions = 1,
1791 .sets = 1024,
1792 .lines_per_tag = 1,
1793 },
1794 .l3_cache = &(CPUCacheInfo) {
1795 .type = UNIFIED_CACHE,
1796 .level = 3,
1797 .size = 8 * MiB,
1798 .line_size = 64,
1799 .associativity = 16,
1800 .partitions = 1,
1801 .sets = 8192,
1802 .lines_per_tag = 1,
1803 .self_init = true,
1804 .inclusive = true,
1805 .complex_indexing = false,
1806 },
1807};
1808
e845de38 1809static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1810 .l1d_cache = &(CPUCacheInfo) {
1811 .type = DATA_CACHE,
1812 .level = 1,
1813 .size = 32 * KiB,
1814 .line_size = 64,
1815 .associativity = 8,
1816 .partitions = 1,
1817 .sets = 64,
1818 .lines_per_tag = 1,
1819 .self_init = 1,
1820 .no_invd_sharing = true,
1821 },
1822 .l1i_cache = &(CPUCacheInfo) {
1823 .type = INSTRUCTION_CACHE,
1824 .level = 1,
1825 .size = 32 * KiB,
1826 .line_size = 64,
1827 .associativity = 8,
1828 .partitions = 1,
1829 .sets = 64,
1830 .lines_per_tag = 1,
1831 .self_init = 1,
1832 .no_invd_sharing = true,
1833 },
1834 .l2_cache = &(CPUCacheInfo) {
1835 .type = UNIFIED_CACHE,
1836 .level = 2,
1837 .size = 512 * KiB,
1838 .line_size = 64,
1839 .associativity = 8,
1840 .partitions = 1,
1841 .sets = 1024,
1842 .lines_per_tag = 1,
1843 },
1844 .l3_cache = &(CPUCacheInfo) {
1845 .type = UNIFIED_CACHE,
1846 .level = 3,
1847 .size = 16 * MiB,
1848 .line_size = 64,
1849 .associativity = 16,
1850 .partitions = 1,
1851 .sets = 16384,
1852 .lines_per_tag = 1,
1853 .self_init = true,
1854 .inclusive = true,
1855 .complex_indexing = true,
1856 },
1857};
1858
d7c72735
MR		 1859static const CPUCaches epyc_rome_v3_cache_info = {
1860 .l1d_cache = &(CPUCacheInfo) {
1861 .type = DATA_CACHE,
1862 .level = 1,
1863 .size = 32 * KiB,
1864 .line_size = 64,
1865 .associativity = 8,
1866 .partitions = 1,
1867 .sets = 64,
1868 .lines_per_tag = 1,
1869 .self_init = 1,
1870 .no_invd_sharing = true,
1871 },
1872 .l1i_cache = &(CPUCacheInfo) {
1873 .type = INSTRUCTION_CACHE,
1874 .level = 1,
1875 .size = 32 * KiB,
1876 .line_size = 64,
1877 .associativity = 8,
1878 .partitions = 1,
1879 .sets = 64,
1880 .lines_per_tag = 1,
1881 .self_init = 1,
1882 .no_invd_sharing = true,
1883 },
1884 .l2_cache = &(CPUCacheInfo) {
1885 .type = UNIFIED_CACHE,
1886 .level = 2,
1887 .size = 512 * KiB,
1888 .line_size = 64,
1889 .associativity = 8,
1890 .partitions = 1,
1891 .sets = 1024,
1892 .lines_per_tag = 1,
1893 },
1894 .l3_cache = &(CPUCacheInfo) {
1895 .type = UNIFIED_CACHE,
1896 .level = 3,
1897 .size = 16 * MiB,
1898 .line_size = 64,
1899 .associativity = 16,
1900 .partitions = 1,
1901 .sets = 16384,
1902 .lines_per_tag = 1,
1903 .self_init = true,
1904 .inclusive = true,
1905 .complex_indexing = false,
1906 },
1907};
1908
e845de38 1909static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 1910 .l1d_cache = &(CPUCacheInfo) {
1911 .type = DATA_CACHE,
1912 .level = 1,
1913 .size = 32 * KiB,
1914 .line_size = 64,
1915 .associativity = 8,
1916 .partitions = 1,
1917 .sets = 64,
1918 .lines_per_tag = 1,
1919 .self_init = 1,
1920 .no_invd_sharing = true,
1921 },
1922 .l1i_cache = &(CPUCacheInfo) {
1923 .type = INSTRUCTION_CACHE,
1924 .level = 1,
1925 .size = 32 * KiB,
1926 .line_size = 64,
1927 .associativity = 8,
1928 .partitions = 1,
1929 .sets = 64,
1930 .lines_per_tag = 1,
1931 .self_init = 1,
1932 .no_invd_sharing = true,
1933 },
1934 .l2_cache = &(CPUCacheInfo) {
1935 .type = UNIFIED_CACHE,
1936 .level = 2,
1937 .size = 512 * KiB,
1938 .line_size = 64,
1939 .associativity = 8,
1940 .partitions = 1,
1941 .sets = 1024,
1942 .lines_per_tag = 1,
1943 },
1944 .l3_cache = &(CPUCacheInfo) {
1945 .type = UNIFIED_CACHE,
1946 .level = 3,
1947 .size = 32 * MiB,
1948 .line_size = 64,
1949 .associativity = 16,
1950 .partitions = 1,
1951 .sets = 32768,
1952 .lines_per_tag = 1,
1953 .self_init = true,
1954 .inclusive = true,
1955 .complex_indexing = true,
1956 },
1957};
1958
27f03be6
BM		 1959static const CPUCaches epyc_milan_v2_cache_info = {
1960 .l1d_cache = &(CPUCacheInfo) {
1961 .type = DATA_CACHE,
1962 .level = 1,
1963 .size = 32 * KiB,
1964 .line_size = 64,
1965 .associativity = 8,
1966 .partitions = 1,
1967 .sets = 64,
1968 .lines_per_tag = 1,
1969 .self_init = 1,
1970 .no_invd_sharing = true,
1971 },
1972 .l1i_cache = &(CPUCacheInfo) {
1973 .type = INSTRUCTION_CACHE,
1974 .level = 1,
1975 .size = 32 * KiB,
1976 .line_size = 64,
1977 .associativity = 8,
1978 .partitions = 1,
1979 .sets = 64,
1980 .lines_per_tag = 1,
1981 .self_init = 1,
1982 .no_invd_sharing = true,
1983 },
1984 .l2_cache = &(CPUCacheInfo) {
1985 .type = UNIFIED_CACHE,
1986 .level = 2,
1987 .size = 512 * KiB,
1988 .line_size = 64,
1989 .associativity = 8,
1990 .partitions = 1,
1991 .sets = 1024,
1992 .lines_per_tag = 1,
1993 },
1994 .l3_cache = &(CPUCacheInfo) {
1995 .type = UNIFIED_CACHE,
1996 .level = 3,
1997 .size = 32 * MiB,
1998 .line_size = 64,
1999 .associativity = 16,
2000 .partitions = 1,
2001 .sets = 32768,
2002 .lines_per_tag = 1,
2003 .self_init = true,
2004 .inclusive = true,
2005 .complex_indexing = false,
2006 },
2007};
2008
166b1741
BM		 2009static const CPUCaches epyc_genoa_cache_info = {
2010 .l1d_cache = &(CPUCacheInfo) {
2011 .type = DATA_CACHE,
2012 .level = 1,
2013 .size = 32 * KiB,
2014 .line_size = 64,
2015 .associativity = 8,
2016 .partitions = 1,
2017 .sets = 64,
2018 .lines_per_tag = 1,
2019 .self_init = 1,
2020 .no_invd_sharing = true,
2021 },
2022 .l1i_cache = &(CPUCacheInfo) {
2023 .type = INSTRUCTION_CACHE,
2024 .level = 1,
2025 .size = 32 * KiB,
2026 .line_size = 64,
2027 .associativity = 8,
2028 .partitions = 1,
2029 .sets = 64,
2030 .lines_per_tag = 1,
2031 .self_init = 1,
2032 .no_invd_sharing = true,
2033 },
2034 .l2_cache = &(CPUCacheInfo) {
2035 .type = UNIFIED_CACHE,
2036 .level = 2,
2037 .size = 1 * MiB,
2038 .line_size = 64,
2039 .associativity = 8,
2040 .partitions = 1,
2041 .sets = 2048,
2042 .lines_per_tag = 1,
2043 },
2044 .l3_cache = &(CPUCacheInfo) {
2045 .type = UNIFIED_CACHE,
2046 .level = 3,
2047 .size = 32 * MiB,
2048 .line_size = 64,
2049 .associativity = 16,
2050 .partitions = 1,
2051 .sets = 32768,
2052 .lines_per_tag = 1,
2053 .self_init = true,
2054 .inclusive = true,
2055 .complex_indexing = false,
2056 },
2057};
2058
0723cc8a
PB		 2059/* The following VMX features are not supported by KVM and are left out in the
2060 * CPU definitions:
2061 *
2062 * Dual-monitor support (all processors)
2063 * Entry to SMM
2064 * Deactivate dual-monitor treatment
2065 * Number of CR3-target values
2066 * Shutdown activity state
2067 * Wait-for-SIPI activity state
2068 * PAUSE-loop exiting (Westmere and newer)
2069 * EPT-violation #VE (Broadwell and newer)
2070 * Inject event with insn length=0 (Skylake and newer)
2071 * Conceal non-root operation from PT
2072 * Conceal VM exits from PT
2073 * Conceal VM entries from PT
2074 * Enable ENCLS exiting
2075 * Mode-based execute control (XS/XU)
2076 s TSC scaling (Skylake Server and newer)
2077 * GPA translation for PT (IceLake and newer)
2078 * User wait and pause
2079 * ENCLV exiting
2080 * Load IA32_RTIT_CTL
2081 * Clear IA32_RTIT_CTL
2082 * Advanced VM-exit information for EPT violations
2083 * Sub-page write permissions
2084 * PT in VMX operation
2085 */
2086
e11fd689 2087static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 2088 {
2089 .name = "qemu64",
3046bb5d 2090 .level = 0xd,
99b88a17 2091 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 2092 .family = 15,
2093 .model = 107,
2094 .stepping = 1,
0514ef2f 2095 .features[FEAT_1_EDX] =
27861ecc 2096 PPRO_FEATURES |
c6dc6f63 2097 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 2098 CPUID_PSE36,
0514ef2f 2099 .features[FEAT_1_ECX] =
6aa91e4a 2100 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 2101 .features[FEAT_8000_0001_EDX] =
c6dc6f63 2102 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2103 .features[FEAT_8000_0001_ECX] =
71195672 2104 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 2105 .xlevel = 0x8000000A,
9cf2cc3d 2106 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2107 },
2108 {
2109 .name = "phenom",
2110 .level = 5,
99b88a17 2111 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2112 .family = 16,
2113 .model = 2,
2114 .stepping = 3,
b9fc20bc 2115 /* Missing: CPUID_HT */
0514ef2f 2116 .features[FEAT_1_EDX] =
27861ecc 2117 PPRO_FEATURES |
c6dc6f63 2118 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 2119 CPUID_PSE36 | CPUID_VME,
0514ef2f 2120 .features[FEAT_1_ECX] =
27861ecc 2121 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 2122 CPUID_EXT_POPCNT,
0514ef2f 2123 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2124 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
2125 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 2126 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 2127 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2128 CPUID_EXT3_CR8LEG,
2129 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2130 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 2131 .features[FEAT_8000_0001_ECX] =
27861ecc 2132 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 2133 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 2134 /* Missing: CPUID_SVM_LBRV */
0514ef2f 2135 .features[FEAT_SVM] =
b9fc20bc 2136 CPUID_SVM_NPT,
c6dc6f63
AP		 2137 .xlevel = 0x8000001A,
2138 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
2139 },
2140 {
2141 .name = "core2duo",
2142 .level = 10,
99b88a17 2143 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2144 .family = 6,
2145 .model = 15,
2146 .stepping = 11,
b9fc20bc 2147 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2148 .features[FEAT_1_EDX] =
27861ecc 2149 PPRO_FEATURES |
c6dc6f63 2150 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 2151 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
2152 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 2153 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2154 .features[FEAT_1_ECX] =
27861ecc 2155 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 2156 CPUID_EXT_CX16,
0514ef2f 2157 .features[FEAT_8000_0001_EDX] =
27861ecc 2158 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2159 .features[FEAT_8000_0001_ECX] =
27861ecc 2160 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2161 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2162 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2163 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2164 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2165 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2166 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2167 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2168 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2169 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2170 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2171 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2172 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2173 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2174 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2175 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2176 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2177 .features[FEAT_VMX_SECONDARY_CTLS] =
2178 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 2179 .xlevel = 0x80000008,
2180 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
2181 },
2182 {
2183 .name = "kvm64",
3046bb5d 2184 .level = 0xd,
99b88a17 2185 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2186 .family = 15,
2187 .model = 6,
2188 .stepping = 1,
b3a4f0b1 2189 /* Missing: CPUID_HT */
0514ef2f 2190 .features[FEAT_1_EDX] =
b3a4f0b1 2191 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 2192 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
2193 CPUID_PSE36,
2194 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 2195 .features[FEAT_1_ECX] =
27861ecc 2196 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 2197 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 2198 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2199 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2200 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2201 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2202 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2203 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 2204 .features[FEAT_8000_0001_ECX] =
27861ecc 2205 0,
0723cc8a
PB		 2206 /* VMX features from Cedar Mill/Prescott */
2207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2208 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2209 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2210 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2211 VMX_PIN_BASED_NMI_EXITING,
2212 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2213 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2214 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2215 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2216 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2217 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2218 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2219 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 2220 .xlevel = 0x80000008,
2221 .model_id = "Common KVM processor"
2222 },
c6dc6f63
AP		 2223 {
2224 .name = "qemu32",
2225 .level = 4,
99b88a17 2226 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2227 .family = 6,
f8e6a11a 2228 .model = 6,
c6dc6f63 2229 .stepping = 3,
0514ef2f 2230 .features[FEAT_1_EDX] =
27861ecc 2231 PPRO_FEATURES,
0514ef2f 2232 .features[FEAT_1_ECX] =
6aa91e4a 2233 CPUID_EXT_SSE3,
58012d66 2234 .xlevel = 0x80000004,
9cf2cc3d 2235 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 2236 },
eafaf1e5
AP		 2237 {
2238 .name = "kvm32",
2239 .level = 5,
99b88a17 2240 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 2241 .family = 15,
2242 .model = 6,
2243 .stepping = 1,
0514ef2f 2244 .features[FEAT_1_EDX] =
b3a4f0b1 2245 PPRO_FEATURES | CPUID_VME |
eafaf1e5 2246 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 2247 .features[FEAT_1_ECX] =
27861ecc 2248 CPUID_EXT_SSE3,
0514ef2f 2249 .features[FEAT_8000_0001_ECX] =
27861ecc 2250 0,
0723cc8a
PB		 2251 /* VMX features from Yonah */
2252 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2253 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2254 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2255 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2256 VMX_PIN_BASED_NMI_EXITING,
2257 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2258 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2259 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2260 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2261 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2262 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2263 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 2264 .xlevel = 0x80000008,
2265 .model_id = "Common 32-bit KVM processor"
2266 },
c6dc6f63
AP		 2267 {
2268 .name = "coreduo",
2269 .level = 10,
99b88a17 2270 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2271 .family = 6,
2272 .model = 14,
2273 .stepping = 8,
b9fc20bc 2274 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2275 .features[FEAT_1_EDX] =
27861ecc 2276 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 2277 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2278 CPUID_SS,
2279 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 2280 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2281 .features[FEAT_1_ECX] =
e93abc14 2282 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 2283 .features[FEAT_8000_0001_EDX] =
27861ecc 2284 CPUID_EXT2_NX,
0723cc8a
PB		 2285 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2286 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2287 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2288 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2289 VMX_PIN_BASED_NMI_EXITING,
2290 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2291 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2292 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2293 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2294 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2295 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2296 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2297 .xlevel = 0x80000008,
2298 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2299 },
2300 {
2301 .name = "486",
58012d66 2302 .level = 1,
99b88a17 2303 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2304 .family = 4,
b2a856d9 2305 .model = 8,
c6dc6f63 2306 .stepping = 0,
0514ef2f 2307 .features[FEAT_1_EDX] =
27861ecc 2308 I486_FEATURES,
c6dc6f63 2309 .xlevel = 0,
807e9869 2310 .model_id = "",
c6dc6f63
AP		 2311 },
2312 {
2313 .name = "pentium",
2314 .level = 1,
99b88a17 2315 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2316 .family = 5,
2317 .model = 4,
2318 .stepping = 3,
0514ef2f 2319 .features[FEAT_1_EDX] =
27861ecc 2320 PENTIUM_FEATURES,
c6dc6f63 2321 .xlevel = 0,
807e9869 2322 .model_id = "",
c6dc6f63
AP		 2323 },
2324 {
2325 .name = "pentium2",
2326 .level = 2,
99b88a17 2327 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2328 .family = 6,
2329 .model = 5,
2330 .stepping = 2,
0514ef2f 2331 .features[FEAT_1_EDX] =
27861ecc 2332 PENTIUM2_FEATURES,
c6dc6f63 2333 .xlevel = 0,
807e9869 2334 .model_id = "",
c6dc6f63
AP		 2335 },
2336 {
2337 .name = "pentium3",
3046bb5d 2338 .level = 3,
99b88a17 2339 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2340 .family = 6,
2341 .model = 7,
2342 .stepping = 3,
0514ef2f 2343 .features[FEAT_1_EDX] =
27861ecc 2344 PENTIUM3_FEATURES,
c6dc6f63 2345 .xlevel = 0,
807e9869 2346 .model_id = "",
c6dc6f63
AP		 2347 },
2348 {
2349 .name = "athlon",
2350 .level = 2,
99b88a17 2351 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2352 .family = 6,
2353 .model = 2,
2354 .stepping = 3,
0514ef2f 2355 .features[FEAT_1_EDX] =
27861ecc 2356 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2357 CPUID_MCA,
0514ef2f 2358 .features[FEAT_8000_0001_EDX] =
60032ac0 2359 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2360 .xlevel = 0x80000008,
9cf2cc3d 2361 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2362 },
2363 {
2364 .name = "n270",
3046bb5d 2365 .level = 10,
99b88a17 2366 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2367 .family = 6,
2368 .model = 28,
2369 .stepping = 2,
b9fc20bc 2370 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2371 .features[FEAT_1_EDX] =
27861ecc 2372 PPRO_FEATURES |
b9fc20bc
EH		 2373 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2374 CPUID_ACPI | CPUID_SS,
c6dc6f63 2375 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2376 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2377 * CPUID_EXT_XTPR */
0514ef2f 2378 .features[FEAT_1_ECX] =
27861ecc 2379 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2380 CPUID_EXT_MOVBE,
0514ef2f 2381 .features[FEAT_8000_0001_EDX] =
60032ac0 2382 CPUID_EXT2_NX,
0514ef2f 2383 .features[FEAT_8000_0001_ECX] =
27861ecc 2384 CPUID_EXT3_LAHF_LM,
3046bb5d 2385 .xlevel = 0x80000008,
c6dc6f63
AP		 2386 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2387 },
3eca4642
EH		 2388 {
2389 .name = "Conroe",
3046bb5d 2390 .level = 10,
99b88a17 2391 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2392 .family = 6,
ffce9ebb 2393 .model = 15,
3eca4642 2394 .stepping = 3,
0514ef2f 2395 .features[FEAT_1_EDX] =
b3a4f0b1 2396 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2397 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2398 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2399 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2400 CPUID_DE | CPUID_FP87,
0514ef2f 2401 .features[FEAT_1_ECX] =
27861ecc 2402 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2403 .features[FEAT_8000_0001_EDX] =
27861ecc 2404 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2405 .features[FEAT_8000_0001_ECX] =
27861ecc 2406 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2407 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2408 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2409 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2410 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2411 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2412 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2413 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2414 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2415 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2416 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2417 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2418 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2419 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2420 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2421 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2422 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2423 .features[FEAT_VMX_SECONDARY_CTLS] =
2424 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2425 .xlevel = 0x80000008,
3eca4642
EH		 2426 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2427 },
2428 {
2429 .name = "Penryn",
3046bb5d 2430 .level = 10,
99b88a17 2431 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2432 .family = 6,
ffce9ebb 2433 .model = 23,
3eca4642 2434 .stepping = 3,
0514ef2f 2435 .features[FEAT_1_EDX] =
b3a4f0b1 2436 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2437 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2438 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2439 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2440 CPUID_DE | CPUID_FP87,
0514ef2f 2441 .features[FEAT_1_ECX] =
27861ecc 2442 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2443 CPUID_EXT_SSE3,
0514ef2f 2444 .features[FEAT_8000_0001_EDX] =
27861ecc 2445 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2446 .features[FEAT_8000_0001_ECX] =
27861ecc 2447 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2448 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2449 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2450 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2451 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2452 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2453 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2454 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2455 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2456 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2457 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2458 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2459 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2460 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2461 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2462 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2463 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2464 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2465 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2466 .features[FEAT_VMX_SECONDARY_CTLS] =
2467 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2468 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2469 .xlevel = 0x80000008,
3eca4642
EH		 2470 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2471 },
2472 {
2473 .name = "Nehalem",
3046bb5d 2474 .level = 11,
99b88a17 2475 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2476 .family = 6,
ffce9ebb 2477 .model = 26,
3eca4642 2478 .stepping = 3,
0514ef2f 2479 .features[FEAT_1_EDX] =
b3a4f0b1 2480 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2481 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2482 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2483 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2484 CPUID_DE | CPUID_FP87,
0514ef2f 2485 .features[FEAT_1_ECX] =
27861ecc 2486 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2487 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2488 .features[FEAT_8000_0001_EDX] =
27861ecc 2489 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2490 .features[FEAT_8000_0001_ECX] =
27861ecc 2491 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2492 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2493 MSR_VMX_BASIC_TRUE_CTLS,
2494 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2497 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2498 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2499 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2500 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2501 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2502 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2504 .features[FEAT_VMX_EXIT_CTLS] =
2505 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2507 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2508 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2509 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2510 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2511 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2512 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2513 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2514 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2515 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2516 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2517 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2518 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2519 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2520 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2521 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2522 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2523 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2524 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2525 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2526 .features[FEAT_VMX_SECONDARY_CTLS] =
2527 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2528 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2529 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2530 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2531 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2532 .xlevel = 0x80000008,
3eca4642 2533 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2534 .versions = (X86CPUVersionDefinition[]) {
2535 { .version = 1 },
2536 {
2537 .version = 2,
53db89d9 2538 .alias = "Nehalem-IBRS",
d86a7088
EH		 2539 .props = (PropValue[]) {
2540 { "spec-ctrl", "on" },
2541 { "model-id",
2542 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2543 { /* end of list */ }
2544 }
2545 },
2546 { /* end of list */ }
2547 }
3eca4642
EH		 2548 },
2549 {
2550 .name = "Westmere",
2551 .level = 11,
99b88a17 2552 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2553 .family = 6,
2554 .model = 44,
2555 .stepping = 1,
0514ef2f 2556 .features[FEAT_1_EDX] =
b3a4f0b1 2557 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2558 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2559 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2560 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2561 CPUID_DE | CPUID_FP87,
0514ef2f 2562 .features[FEAT_1_ECX] =
27861ecc 2563 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2564 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2565 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2566 .features[FEAT_8000_0001_EDX] =
27861ecc 2567 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2568 .features[FEAT_8000_0001_ECX] =
27861ecc 2569 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2570 .features[FEAT_6_EAX] =
2571 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2572 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2573 MSR_VMX_BASIC_TRUE_CTLS,
2574 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2575 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2576 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2577 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2578 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2579 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2580 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2581 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2582 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2583 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2584 .features[FEAT_VMX_EXIT_CTLS] =
2585 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2586 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2587 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2588 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2589 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2590 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2591 MSR_VMX_MISC_STORE_LMA,
2592 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2593 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2594 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2595 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2596 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2597 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2598 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2599 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2600 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2601 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2602 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2603 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2604 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2605 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2606 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2607 .features[FEAT_VMX_SECONDARY_CTLS] =
2608 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2609 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2610 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2611 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2612 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2613 .xlevel = 0x80000008,
3eca4642 2614 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2615 .versions = (X86CPUVersionDefinition[]) {
2616 { .version = 1 },
2617 {
2618 .version = 2,
53db89d9 2619 .alias = "Westmere-IBRS",
d86a7088
EH		 2620 .props = (PropValue[]) {
2621 { "spec-ctrl", "on" },
2622 { "model-id",
2623 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2624 { /* end of list */ }
2625 }
2626 },
2627 { /* end of list */ }
2628 }
3eca4642
EH		 2629 },
2630 {
2631 .name = "SandyBridge",
2632 .level = 0xd,
99b88a17 2633 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2634 .family = 6,
2635 .model = 42,
2636 .stepping = 1,
0514ef2f 2637 .features[FEAT_1_EDX] =
b3a4f0b1 2638 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2639 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2640 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2641 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2642 CPUID_DE | CPUID_FP87,
0514ef2f 2643 .features[FEAT_1_ECX] =
27861ecc 2644 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2645 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2646 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2647 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2648 CPUID_EXT_SSE3,
0514ef2f 2649 .features[FEAT_8000_0001_EDX] =
27861ecc 2650 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2651 CPUID_EXT2_SYSCALL,
0514ef2f 2652 .features[FEAT_8000_0001_ECX] =
27861ecc 2653 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2654 .features[FEAT_XSAVE] =
2655 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2656 .features[FEAT_6_EAX] =
2657 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2658 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2659 MSR_VMX_BASIC_TRUE_CTLS,
2660 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2661 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2662 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2663 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2664 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2665 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2666 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2667 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2668 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2669 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2670 .features[FEAT_VMX_EXIT_CTLS] =
2671 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2672 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2673 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2674 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2675 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2676 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2677 MSR_VMX_MISC_STORE_LMA,
2678 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2679 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2680 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2681 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2682 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2683 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2684 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2685 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2686 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2687 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2688 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2689 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2690 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2691 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2692 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2693 .features[FEAT_VMX_SECONDARY_CTLS] =
2694 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2695 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2696 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2697 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2698 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2699 .xlevel = 0x80000008,
3eca4642 2700 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2701 .versions = (X86CPUVersionDefinition[]) {
2702 { .version = 1 },
2703 {
2704 .version = 2,
53db89d9 2705 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2706 .props = (PropValue[]) {
2707 { "spec-ctrl", "on" },
2708 { "model-id",
2709 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2710 { /* end of list */ }
2711 }
2712 },
2713 { /* end of list */ }
2714 }
3eca4642 2715 },
2f9ac42a
PB		 2716 {
2717 .name = "IvyBridge",
2718 .level = 0xd,
2719 .vendor = CPUID_VENDOR_INTEL,
2720 .family = 6,
2721 .model = 58,
2722 .stepping = 9,
2723 .features[FEAT_1_EDX] =
2724 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2725 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2726 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2727 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2728 CPUID_DE | CPUID_FP87,
2729 .features[FEAT_1_ECX] =
2730 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2731 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2732 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2733 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2734 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2735 .features[FEAT_7_0_EBX] =
2736 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2737 CPUID_7_0_EBX_ERMS,
2738 .features[FEAT_8000_0001_EDX] =
2739 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2740 CPUID_EXT2_SYSCALL,
2741 .features[FEAT_8000_0001_ECX] =
2742 CPUID_EXT3_LAHF_LM,
2743 .features[FEAT_XSAVE] =
2744 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2745 .features[FEAT_6_EAX] =
2746 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2747 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2748 MSR_VMX_BASIC_TRUE_CTLS,
2749 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2750 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2751 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2752 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2753 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2754 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2755 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2756 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2757 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2758 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2759 .features[FEAT_VMX_EXIT_CTLS] =
2760 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2761 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2762 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2763 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2764 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2765 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2766 MSR_VMX_MISC_STORE_LMA,
2767 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2768 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2769 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2770 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2771 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2772 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2773 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2774 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2775 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2776 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2777 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2778 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2779 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2780 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2781 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2782 .features[FEAT_VMX_SECONDARY_CTLS] =
2783 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2784 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2785 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2786 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2787 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2788 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2789 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2790 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2791 .xlevel = 0x80000008,
2f9ac42a 2792 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2793 .versions = (X86CPUVersionDefinition[]) {
2794 { .version = 1 },
2795 {
2796 .version = 2,
53db89d9 2797 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2798 .props = (PropValue[]) {
2799 { "spec-ctrl", "on" },
2800 { "model-id",
2801 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2802 { /* end of list */ }
2803 }
2804 },
2805 { /* end of list */ }
2806 }
2f9ac42a 2807 },
ac96c413 2808 {
37507094
EH		 2809 .name = "Haswell",
2810 .level = 0xd,
99b88a17 2811 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2812 .family = 6,
2813 .model = 60,
ec56a4a7 2814 .stepping = 4,
0514ef2f 2815 .features[FEAT_1_EDX] =
b3a4f0b1 2816 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2817 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2818 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2819 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2820 CPUID_DE | CPUID_FP87,
0514ef2f 2821 .features[FEAT_1_ECX] =
27861ecc 2822 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2823 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2824 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2825 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2826 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2827 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2828 .features[FEAT_8000_0001_EDX] =
27861ecc 2829 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2830 CPUID_EXT2_SYSCALL,
0514ef2f 2831 .features[FEAT_8000_0001_ECX] =
becb6667 2832 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2833 .features[FEAT_7_0_EBX] =
27861ecc 2834 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2835 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2836 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2837 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2838 .features[FEAT_XSAVE] =
2839 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2840 .features[FEAT_6_EAX] =
2841 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2842 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2843 MSR_VMX_BASIC_TRUE_CTLS,
2844 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2845 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2846 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2847 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2848 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2849 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2850 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2851 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2852 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2853 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2854 .features[FEAT_VMX_EXIT_CTLS] =
2855 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2856 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2857 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2858 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2859 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2860 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2861 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2862 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2863 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2864 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2865 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2866 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2867 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2868 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2869 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2870 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2871 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2872 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2873 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2874 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2875 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2876 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2877 .features[FEAT_VMX_SECONDARY_CTLS] =
2878 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2879 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2880 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2881 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2882 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2883 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2884 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2885 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2886 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2887 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2888 .xlevel = 0x80000008,
37507094 2889 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2890 .versions = (X86CPUVersionDefinition[]) {
2891 { .version = 1 },
2892 {
2893 .version = 2,
53db89d9 2894 .alias = "Haswell-noTSX",
d86a7088
EH		 2895 .props = (PropValue[]) {
2896 { "hle", "off" },
2897 { "rtm", "off" },
2898 { "stepping", "1" },
2899 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2900 { /* end of list */ }
2901 },
2902 },
2903 {
2904 .version = 3,
53db89d9 2905 .alias = "Haswell-IBRS",
d86a7088
EH		 2906 .props = (PropValue[]) {
2907 /* Restore TSX features removed by -v2 above */
2908 { "hle", "on" },
2909 { "rtm", "on" },
2910 /*
2911 * Haswell and Haswell-IBRS had stepping=4 in
2912 * QEMU 4.0 and older
2913 */
2914 { "stepping", "4" },
2915 { "spec-ctrl", "on" },
2916 { "model-id",
2917 "Intel Core Processor (Haswell, IBRS)" },
2918 { /* end of list */ }
2919 }
2920 },
2921 {
2922 .version = 4,
53db89d9 2923 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2924 .props = (PropValue[]) {
2925 { "hle", "off" },
2926 { "rtm", "off" },
2927 /* spec-ctrl was already enabled by -v3 above */
2928 { "stepping", "1" },
2929 { "model-id",
2930 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2931 { /* end of list */ }
2932 }
2933 },
2934 { /* end of list */ }
2935 }
37507094 2936 },
ece01354
EH		 2937 {
2938 .name = "Broadwell",
2939 .level = 0xd,
2940 .vendor = CPUID_VENDOR_INTEL,
2941 .family = 6,
2942 .model = 61,
2943 .stepping = 2,
2944 .features[FEAT_1_EDX] =
b3a4f0b1 2945 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2946 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2947 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2948 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2949 CPUID_DE | CPUID_FP87,
2950 .features[FEAT_1_ECX] =
2951 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2952 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2953 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2954 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2955 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2956 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2957 .features[FEAT_8000_0001_EDX] =
2958 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2959 CPUID_EXT2_SYSCALL,
2960 .features[FEAT_8000_0001_ECX] =
becb6667 2961 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2962 .features[FEAT_7_0_EBX] =
2963 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2964 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2965 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2966 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2967 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2968 .features[FEAT_XSAVE] =
2969 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2970 .features[FEAT_6_EAX] =
2971 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2972 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2973 MSR_VMX_BASIC_TRUE_CTLS,
2974 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2975 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2976 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2977 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2978 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2979 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2980 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2981 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2984 .features[FEAT_VMX_EXIT_CTLS] =
2985 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2986 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2987 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2988 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2989 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2990 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2991 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2992 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2993 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2994 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2995 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2996 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2997 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2998 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2999 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3000 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3001 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3002 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3003 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3004 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3005 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3006 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3007 .features[FEAT_VMX_SECONDARY_CTLS] =
3008 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3009 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3010 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3011 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3012 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3013 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3014 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3015 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3016 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3017 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3018 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 3019 .xlevel = 0x80000008,
ece01354 3020 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 3021 .versions = (X86CPUVersionDefinition[]) {
3022 { .version = 1 },
3023 {
3024 .version = 2,
53db89d9 3025 .alias = "Broadwell-noTSX",
d86a7088
EH		 3026 .props = (PropValue[]) {
3027 { "hle", "off" },
3028 { "rtm", "off" },
3029 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3030 { /* end of list */ }
3031 },
3032 },
3033 {
3034 .version = 3,
53db89d9 3035 .alias = "Broadwell-IBRS",
d86a7088
EH		 3036 .props = (PropValue[]) {
3037 /* Restore TSX features removed by -v2 above */
3038 { "hle", "on" },
3039 { "rtm", "on" },
3040 { "spec-ctrl", "on" },
3041 { "model-id",
3042 "Intel Core Processor (Broadwell, IBRS)" },
3043 { /* end of list */ }
3044 }
3045 },
3046 {
3047 .version = 4,
53db89d9 3048 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 3049 .props = (PropValue[]) {
3050 { "hle", "off" },
3051 { "rtm", "off" },
3052 /* spec-ctrl was already enabled by -v3 above */
3053 { "model-id",
3054 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
3055 { /* end of list */ }
3056 }
3057 },
3058 { /* end of list */ }
3059 }
ece01354 3060 },
f6f949e9
EH		 3061 {
3062 .name = "Skylake-Client",
3063 .level = 0xd,
3064 .vendor = CPUID_VENDOR_INTEL,
3065 .family = 6,
3066 .model = 94,
3067 .stepping = 3,
3068 .features[FEAT_1_EDX] =
3069 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3070 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3071 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3072 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3073 CPUID_DE | CPUID_FP87,
3074 .features[FEAT_1_ECX] =
3075 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3076 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3077 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3078 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3079 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3080 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3081 .features[FEAT_8000_0001_EDX] =
3082 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3083 CPUID_EXT2_SYSCALL,
3084 .features[FEAT_8000_0001_ECX] =
3085 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3086 .features[FEAT_7_0_EBX] =
3087 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3088 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3089 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3090 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3091 CPUID_7_0_EBX_SMAP,
7bde6b18 3092 /* XSAVES is added in version 4 */
f6f949e9
EH		 3093 .features[FEAT_XSAVE] =
3094 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3095 CPUID_XSAVE_XGETBV1,
3096 .features[FEAT_6_EAX] =
3097 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3098 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3099 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3100 MSR_VMX_BASIC_TRUE_CTLS,
3101 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3102 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3103 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3104 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3105 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3106 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3107 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3108 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3109 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3110 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3111 .features[FEAT_VMX_EXIT_CTLS] =
3112 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3113 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3114 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3115 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3116 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3117 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3118 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3119 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3120 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3121 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3122 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3123 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3124 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3125 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3126 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3127 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3128 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3129 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3130 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3131 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3132 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3133 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3134 .features[FEAT_VMX_SECONDARY_CTLS] =
3135 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3136 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3137 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3138 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3139 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3140 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3141 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3142 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 3143 .xlevel = 0x80000008,
3144 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 3145 .versions = (X86CPUVersionDefinition[]) {
3146 { .version = 1 },
3147 {
3148 .version = 2,
53db89d9 3149 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 3150 .props = (PropValue[]) {
3151 { "spec-ctrl", "on" },
3152 { "model-id",
3153 "Intel Core Processor (Skylake, IBRS)" },
3154 { /* end of list */ }
3155 }
3156 },
9ab2237f
EH		 3157 {
3158 .version = 3,
02fa60d1 3159 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 3160 .props = (PropValue[]) {
3161 { "hle", "off" },
3162 { "rtm", "off" },
673b0add
KC		 3163 { "model-id",
3164 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3165 { /* end of list */ }
3166 }
3167 },
7bde6b18
VK		 3168 {
3169 .version = 4,
3170 .note = "IBRS, XSAVES, no TSX",
3171 .props = (PropValue[]) {
3172 { "xsaves", "on" },
3173 { "vmx-xsaves", "on" },
3174 { /* end of list */ }
3175 }
3176 },
d86a7088
EH		 3177 { /* end of list */ }
3178 }
f6f949e9 3179 },
53f9a6f4
BF		 3180 {
3181 .name = "Skylake-Server",
3182 .level = 0xd,
3183 .vendor = CPUID_VENDOR_INTEL,
3184 .family = 6,
3185 .model = 85,
3186 .stepping = 4,
3187 .features[FEAT_1_EDX] =
3188 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3189 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3190 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3191 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3192 CPUID_DE | CPUID_FP87,
3193 .features[FEAT_1_ECX] =
3194 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3195 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3196 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3197 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3198 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3199 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3200 .features[FEAT_8000_0001_EDX] =
3201 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3202 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3203 .features[FEAT_8000_0001_ECX] =
3204 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3205 .features[FEAT_7_0_EBX] =
3206 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3207 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3208 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3209 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3210 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 3211 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3212 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 3213 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 3214 .features[FEAT_7_0_ECX] =
3215 CPUID_7_0_ECX_PKU,
7bde6b18 3216 /* XSAVES is added in version 5 */
53f9a6f4
BF		 3217 .features[FEAT_XSAVE] =
3218 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3219 CPUID_XSAVE_XGETBV1,
3220 .features[FEAT_6_EAX] =
3221 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3222 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3223 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3224 MSR_VMX_BASIC_TRUE_CTLS,
3225 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3227 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3228 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3229 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3230 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3231 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3232 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3233 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3235 .features[FEAT_VMX_EXIT_CTLS] =
3236 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3237 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3238 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3239 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3240 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3241 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3242 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3243 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3244 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3245 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3252 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3253 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3255 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3256 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3258 .features[FEAT_VMX_SECONDARY_CTLS] =
3259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3260 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3261 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3262 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3263 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3264 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3265 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3266 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3267 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3268 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 3269 .xlevel = 0x80000008,
3270 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 3271 .versions = (X86CPUVersionDefinition[]) {
3272 { .version = 1 },
3273 {
3274 .version = 2,
53db89d9 3275 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 3276 .props = (PropValue[]) {
3277 /* clflushopt was not added to Skylake-Server-IBRS */
3278 /* TODO: add -v3 including clflushopt */
3279 { "clflushopt", "off" },
3280 { "spec-ctrl", "on" },
3281 { "model-id",
3282 "Intel Xeon Processor (Skylake, IBRS)" },
3283 { /* end of list */ }
3284 }
3285 },
9ab2237f
EH		 3286 {
3287 .version = 3,
02fa60d1 3288 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3289 .props = (PropValue[]) {
3290 { "hle", "off" },
3291 { "rtm", "off" },
673b0add
KC		 3292 { "model-id",
3293 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3294 { /* end of list */ }
3295 }
3296 },
644e3c5d
CQ		 3297 {
3298 .version = 4,
3299 .props = (PropValue[]) {
3300 { "vmx-eptp-switching", "on" },
3301 { /* end of list */ }
3302 }
3303 },
7bde6b18
VK		 3304 {
3305 .version = 5,
3306 .note = "IBRS, XSAVES, EPT switching, no TSX",
3307 .props = (PropValue[]) {
3308 { "xsaves", "on" },
3309 { "vmx-xsaves", "on" },
3310 { /* end of list */ }
3311 }
3312 },
d86a7088
EH		 3313 { /* end of list */ }
3314 }
53f9a6f4 3315 },
c7a88b52
TX		 3316 {
3317 .name = "Cascadelake-Server",
3318 .level = 0xd,
3319 .vendor = CPUID_VENDOR_INTEL,
3320 .family = 6,
3321 .model = 85,
b0a19803 3322 .stepping = 6,
c7a88b52
TX		 3323 .features[FEAT_1_EDX] =
3324 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3325 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3326 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3327 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3328 CPUID_DE | CPUID_FP87,
3329 .features[FEAT_1_ECX] =
3330 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3331 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3332 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3333 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3334 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3335 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3336 .features[FEAT_8000_0001_EDX] =
3337 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3338 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3339 .features[FEAT_8000_0001_ECX] =
3340 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3341 .features[FEAT_7_0_EBX] =
3342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3343 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3344 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3345 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3346 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3347 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3348 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3349 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3350 .features[FEAT_7_0_ECX] =
bb4928c7 3351 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3352 CPUID_7_0_ECX_AVX512VNNI,
3353 .features[FEAT_7_0_EDX] =
3354 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3355 /* XSAVES is added in version 5 */
c7a88b52
TX		 3356 .features[FEAT_XSAVE] =
3357 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3358 CPUID_XSAVE_XGETBV1,
3359 .features[FEAT_6_EAX] =
3360 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3361 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3362 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3363 MSR_VMX_BASIC_TRUE_CTLS,
3364 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3365 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3366 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3367 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3368 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3369 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3370 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3371 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3372 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3373 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3374 .features[FEAT_VMX_EXIT_CTLS] =
3375 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3376 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3377 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3378 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3379 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3380 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3381 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3382 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3383 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3384 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3385 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3386 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3387 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3388 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3389 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3390 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3391 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3392 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3393 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3394 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3395 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3396 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3397 .features[FEAT_VMX_SECONDARY_CTLS] =
3398 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3399 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3400 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3401 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3402 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3403 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3404 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3405 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3406 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3407 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3408 .xlevel = 0x80000008,
3409 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3410 .versions = (X86CPUVersionDefinition[]) {
3411 { .version = 1 },
3412 { .version = 2,
47f0d11d 3413 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3414 .props = (PropValue[]) {
3415 { "arch-capabilities", "on" },
3416 { "rdctl-no", "on" },
3417 { "ibrs-all", "on" },
3418 { "skip-l1dfl-vmentry", "on" },
3419 { "mds-no", "on" },
3420 { /* end of list */ }
3421 },
3422 },
9ab2237f 3423 { .version = 3,
02fa60d1 3424 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3425 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3426 .props = (PropValue[]) {
3427 { "hle", "off" },
3428 { "rtm", "off" },
3429 { /* end of list */ }
3430 },
3431 },
644e3c5d
CQ		 3432 { .version = 4,
3433 .note = "ARCH_CAPABILITIES, no TSX",
3434 .props = (PropValue[]) {
3435 { "vmx-eptp-switching", "on" },
3436 { /* end of list */ }
3437 },
3438 },
7bde6b18
VK		 3439 { .version = 5,
3440 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3441 .props = (PropValue[]) {
3442 { "xsaves", "on" },
3443 { "vmx-xsaves", "on" },
3444 { /* end of list */ }
3445 },
3446 },
fd63c6d1
EH		 3447 { /* end of list */ }
3448 }
c7a88b52 3449 },
22a866b6
CZ		 3450 {
3451 .name = "Cooperlake",
3452 .level = 0xd,
3453 .vendor = CPUID_VENDOR_INTEL,
3454 .family = 6,
3455 .model = 85,
3456 .stepping = 10,
3457 .features[FEAT_1_EDX] =
3458 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3459 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3460 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3461 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3462 CPUID_DE | CPUID_FP87,
3463 .features[FEAT_1_ECX] =
3464 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3465 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3466 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3467 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3468 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3469 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3470 .features[FEAT_8000_0001_EDX] =
3471 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3472 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3473 .features[FEAT_8000_0001_ECX] =
3474 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3475 .features[FEAT_7_0_EBX] =
3476 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3477 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3478 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3479 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3480 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3481 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3482 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3483 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3484 .features[FEAT_7_0_ECX] =
3485 CPUID_7_0_ECX_PKU |
3486 CPUID_7_0_ECX_AVX512VNNI,
3487 .features[FEAT_7_0_EDX] =
3488 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3489 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3490 .features[FEAT_ARCH_CAPABILITIES] =
3491 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3492 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3493 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3494 .features[FEAT_7_1_EAX] =
f429dbf8 3495 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3496 /* XSAVES is added in version 2 */
22a866b6
CZ		 3497 .features[FEAT_XSAVE] =
3498 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3499 CPUID_XSAVE_XGETBV1,
3500 .features[FEAT_6_EAX] =
3501 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3502 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3503 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3504 MSR_VMX_BASIC_TRUE_CTLS,
3505 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3506 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3507 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3508 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3509 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3510 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3511 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3512 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3513 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3514 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3515 .features[FEAT_VMX_EXIT_CTLS] =
3516 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3517 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3518 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3519 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3520 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3521 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3522 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3523 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3524 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3525 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3526 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3527 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3528 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3529 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3530 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3531 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3532 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3533 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3534 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3535 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3536 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3537 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3538 .features[FEAT_VMX_SECONDARY_CTLS] =
3539 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3540 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3541 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3542 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3543 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3544 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3545 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3546 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3547 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3548 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3549 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3550 .xlevel = 0x80000008,
3551 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3552 .versions = (X86CPUVersionDefinition[]) {
3553 { .version = 1 },
3554 { .version = 2,
3555 .note = "XSAVES",
3556 .props = (PropValue[]) {
3557 { "xsaves", "on" },
3558 { "vmx-xsaves", "on" },
3559 { /* end of list */ }
3560 },
3561 },
3562 { /* end of list */ }
3563 }
22a866b6 3564 },
8a11c62d
RH		 3565 {
3566 .name = "Icelake-Server",
3567 .level = 0xd,
3568 .vendor = CPUID_VENDOR_INTEL,
3569 .family = 6,
3570 .model = 134,
3571 .stepping = 0,
3572 .features[FEAT_1_EDX] =
3573 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3574 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3575 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3576 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3577 CPUID_DE | CPUID_FP87,
3578 .features[FEAT_1_ECX] =
3579 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3580 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3581 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3582 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3583 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3584 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3585 .features[FEAT_8000_0001_EDX] =
3586 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3587 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3588 .features[FEAT_8000_0001_ECX] =
3589 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3590 .features[FEAT_8000_0008_EBX] =
3591 CPUID_8000_0008_EBX_WBNOINVD,
3592 .features[FEAT_7_0_EBX] =
3593 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3594 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3595 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3596 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3597 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3598 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3599 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3600 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3601 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3602 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3603 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3604 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3605 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3606 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3607 .features[FEAT_7_0_EDX] =
76e5a4d5 3608 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3609 /* XSAVES is added in version 5 */
8a11c62d
RH		 3610 .features[FEAT_XSAVE] =
3611 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3612 CPUID_XSAVE_XGETBV1,
3613 .features[FEAT_6_EAX] =
3614 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3615 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3616 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3617 MSR_VMX_BASIC_TRUE_CTLS,
3618 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3619 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3620 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3621 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3622 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3623 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3624 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3625 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3626 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3627 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3628 .features[FEAT_VMX_EXIT_CTLS] =
3629 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3630 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3631 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3632 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3633 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3634 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3635 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3636 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3637 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3638 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3639 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3640 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3641 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3642 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3643 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3644 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3645 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3646 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3647 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3648 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3649 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3650 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3651 .features[FEAT_VMX_SECONDARY_CTLS] =
3652 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3653 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3654 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3655 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3656 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3657 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3658 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3659 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3660 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3661 .xlevel = 0x80000008,
3662 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3663 .versions = (X86CPUVersionDefinition[]) {
3664 { .version = 1 },
3665 {
3666 .version = 2,
47f0d11d 3667 .note = "no TSX",
02fa60d1 3668 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3669 .props = (PropValue[]) {
3670 { "hle", "off" },
3671 { "rtm", "off" },
3672 { /* end of list */ }
3673 },
3674 },
d965dc35
XL		 3675 {
3676 .version = 3,
3677 .props = (PropValue[]) {
3678 { "arch-capabilities", "on" },
3679 { "rdctl-no", "on" },
3680 { "ibrs-all", "on" },
3681 { "skip-l1dfl-vmentry", "on" },
3682 { "mds-no", "on" },
3683 { "pschange-mc-no", "on" },
3684 { "taa-no", "on" },
3685 { /* end of list */ }
3686 },
3687 },
e0013791
CQ		 3688 {
3689 .version = 4,
3690 .props = (PropValue[]) {
3691 { "sha-ni", "on" },
3692 { "avx512ifma", "on" },
3693 { "rdpid", "on" },
3694 { "fsrm", "on" },
3695 { "vmx-rdseed-exit", "on" },
3696 { "vmx-pml", "on" },
3697 { "vmx-eptp-switching", "on" },
3698 { "model", "106" },
3699 { /* end of list */ }
3700 },
3701 },
7bde6b18
VK		 3702 {
3703 .version = 5,
3704 .note = "XSAVES",
3705 .props = (PropValue[]) {
3706 { "xsaves", "on" },
3707 { "vmx-xsaves", "on" },
3708 { /* end of list */ }
3709 },
3710 },
12cab535
VK		 3711 {
3712 .version = 6,
3713 .note = "5-level EPT",
3714 .props = (PropValue[]) {
3715 { "vmx-page-walk-5", "on" },
3716 { /* end of list */ }
3717 },
3718 },
9ab2237f
EH		 3719 { /* end of list */ }
3720 }
8a11c62d 3721 },
7eb061b0
WL		 3722 {
3723 .name = "SapphireRapids",
3724 .level = 0x20,
3725 .vendor = CPUID_VENDOR_INTEL,
3726 .family = 6,
3727 .model = 143,
3728 .stepping = 4,
3729 /*
3730 * please keep the ascending order so that we can have a clear view of
3731 * bit position of each feature.
3732 */
3733 .features[FEAT_1_EDX] =
3734 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3735 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3736 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3737 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3738 CPUID_SSE | CPUID_SSE2,
3739 .features[FEAT_1_ECX] =
3740 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
3741 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
3742 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3743 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
3744 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3745 .features[FEAT_8000_0001_EDX] =
3746 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3747 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3748 .features[FEAT_8000_0001_ECX] =
3749 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
3750 .features[FEAT_8000_0008_EBX] =
3751 CPUID_8000_0008_EBX_WBNOINVD,
3752 .features[FEAT_7_0_EBX] =
3753 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
3754 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
3755 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
3756 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3757 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
3758 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
3759 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
3760 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
3761 .features[FEAT_7_0_ECX] =
3762 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3763 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3764 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3765 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3766 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
3767 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
3768 .features[FEAT_7_0_EDX] =
3769 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
3770 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
3771 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
3772 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
3773 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3774 .features[FEAT_ARCH_CAPABILITIES] =
3775 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3776 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3777 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3778 .features[FEAT_XSAVE] =
3779 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3780 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
3781 .features[FEAT_6_EAX] =
3782 CPUID_6_EAX_ARAT,
3783 .features[FEAT_7_1_EAX] =
3784 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
3785 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
3786 .features[FEAT_VMX_BASIC] =
3787 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
3788 .features[FEAT_VMX_ENTRY_CTLS] =
3789 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
3790 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
3791 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
3792 .features[FEAT_VMX_EPT_VPID_CAPS] =
3793 MSR_VMX_EPT_EXECONLY |
3794 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
3795 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
3796 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
3797 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3798 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3799 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
3800 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3801 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
3802 .features[FEAT_VMX_EXIT_CTLS] =
3803 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3804 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3805 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
3806 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3807 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3808 .features[FEAT_VMX_MISC] =
3809 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
3810 MSR_VMX_MISC_VMWRITE_VMEXIT,
3811 .features[FEAT_VMX_PINBASED_CTLS] =
3812 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
3813 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
3814 VMX_PIN_BASED_POSTED_INTR,
3815 .features[FEAT_VMX_PROCBASED_CTLS] =
3816 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3817 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3818 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3819 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3820 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3821 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3822 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
3823 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
3824 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3825 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
3826 VMX_CPU_BASED_PAUSE_EXITING |
3827 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3828 .features[FEAT_VMX_SECONDARY_CTLS] =
3829 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3830 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
3831 VMX_SECONDARY_EXEC_RDTSCP |
3832 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3833 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
3834 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3835 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3836 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3837 VMX_SECONDARY_EXEC_RDRAND_EXITING |
3838 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3839 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3840 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
3841 VMX_SECONDARY_EXEC_XSAVES,
3842 .features[FEAT_VMX_VMFUNC] =
3843 MSR_VMX_VMFUNC_EPT_SWITCHING,
3844 .xlevel = 0x80000008,
3845 .model_id = "Intel Xeon Processor (SapphireRapids)",
3846 .versions = (X86CPUVersionDefinition[]) {
3847 { .version = 1 },
3848 { /* end of list */ },
3849 },
3850 },
8b44d860
TX		 3851 {
3852 .name = "Denverton",
3853 .level = 21,
3854 .vendor = CPUID_VENDOR_INTEL,
3855 .family = 6,
3856 .model = 95,
3857 .stepping = 1,
3858 .features[FEAT_1_EDX] =
3859 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3860 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3861 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3862 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3863 CPUID_SSE | CPUID_SSE2,
3864 .features[FEAT_1_ECX] =
3865 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3866 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3867 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3868 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3869 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3870 .features[FEAT_8000_0001_EDX] =
3871 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3872 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3873 .features[FEAT_8000_0001_ECX] =
3874 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3875 .features[FEAT_7_0_EBX] =
3876 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3877 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3878 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3879 .features[FEAT_7_0_EDX] =
3880 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3881 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3882 /* XSAVES is added in version 3 */
8b44d860
TX		 3883 .features[FEAT_XSAVE] =
3884 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3885 .features[FEAT_6_EAX] =
3886 CPUID_6_EAX_ARAT,
3887 .features[FEAT_ARCH_CAPABILITIES] =
3888 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3889 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3890 MSR_VMX_BASIC_TRUE_CTLS,
3891 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3892 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3893 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3894 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3895 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3896 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3897 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3898 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3899 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3900 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3901 .features[FEAT_VMX_EXIT_CTLS] =
3902 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3903 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3904 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3905 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3906 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3907 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3908 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3909 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3910 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3911 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3912 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3913 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3914 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3915 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3916 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3917 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3918 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3919 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3920 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3921 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3922 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3923 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3924 .features[FEAT_VMX_SECONDARY_CTLS] =
3925 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3926 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3927 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3928 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3929 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3930 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3931 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3932 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3933 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3934 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3935 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3936 .xlevel = 0x80000008,
3937 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3938 .versions = (X86CPUVersionDefinition[]) {
3939 { .version = 1 },
3940 {
3941 .version = 2,
47f0d11d 3942 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3943 .props = (PropValue[]) {
3944 { "monitor", "off" },
3945 { "mpx", "off" },
3946 { /* end of list */ },
3947 },
3948 },
7bde6b18
VK		 3949 {
3950 .version = 3,
3951 .note = "XSAVES, no MPX, no MONITOR",
3952 .props = (PropValue[]) {
3953 { "xsaves", "on" },
3954 { "vmx-xsaves", "on" },
3955 { /* end of list */ },
3956 },
3957 },
ab0c942c
TX		 3958 { /* end of list */ },
3959 },
8b44d860 3960 },
0b18874b 3961 {
ff656fcd 3962 .name = "Snowridge",
0b18874b
PL		 3963 .level = 27,
3964 .vendor = CPUID_VENDOR_INTEL,
3965 .family = 6,
3966 .model = 134,
3967 .stepping = 1,
3968 .features[FEAT_1_EDX] =
3969 /* missing: CPUID_PN CPUID_IA64 */
3970 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3971 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3972 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3973 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3974 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3975 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3976 CPUID_MMX |
3977 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3978 .features[FEAT_1_ECX] =
3979 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3980 CPUID_EXT_SSSE3 |
3981 CPUID_EXT_CX16 |
3982 CPUID_EXT_SSE41 |
3983 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3984 CPUID_EXT_POPCNT |
3985 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3986 CPUID_EXT_RDRAND,
3987 .features[FEAT_8000_0001_EDX] =
3988 CPUID_EXT2_SYSCALL |
3989 CPUID_EXT2_NX |
3990 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3991 CPUID_EXT2_LM,
3992 .features[FEAT_8000_0001_ECX] =
3993 CPUID_EXT3_LAHF_LM |
3994 CPUID_EXT3_3DNOWPREFETCH,
3995 .features[FEAT_7_0_EBX] =
3996 CPUID_7_0_EBX_FSGSBASE |
3997 CPUID_7_0_EBX_SMEP |
3998 CPUID_7_0_EBX_ERMS |
3999 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
4000 CPUID_7_0_EBX_RDSEED |
4001 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4002 CPUID_7_0_EBX_CLWB |
4003 CPUID_7_0_EBX_SHA_NI,
4004 .features[FEAT_7_0_ECX] =
4005 CPUID_7_0_ECX_UMIP |
4006 /* missing bit 5 */
4007 CPUID_7_0_ECX_GFNI |
4008 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
4009 CPUID_7_0_ECX_MOVDIR64B,
4010 .features[FEAT_7_0_EDX] =
4011 CPUID_7_0_EDX_SPEC_CTRL |
4012 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
4013 CPUID_7_0_EDX_CORE_CAPABILITY,
4014 .features[FEAT_CORE_CAPABILITY] =
4015 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7a21bee2 4016 /* XSAVES is added in version 3 */
0b18874b
PL		 4017 .features[FEAT_XSAVE] =
4018 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4019 CPUID_XSAVE_XGETBV1,
4020 .features[FEAT_6_EAX] =
4021 CPUID_6_EAX_ARAT,
0723cc8a
PB		 4022 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4023 MSR_VMX_BASIC_TRUE_CTLS,
4024 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4025 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4026 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4027 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4028 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4029 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4030 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4031 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4032 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4033 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4034 .features[FEAT_VMX_EXIT_CTLS] =
4035 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4036 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4037 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4038 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4039 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4040 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4041 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4042 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4043 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4044 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4045 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4046 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4047 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4048 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4049 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4050 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4051 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4052 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4053 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4054 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4055 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4056 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4057 .features[FEAT_VMX_SECONDARY_CTLS] =
4058 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4059 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4060 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4061 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4062 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4063 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4064 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4065 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4066 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4067 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4068 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 4069 .xlevel = 0x80000008,
4070 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 4071 .versions = (X86CPUVersionDefinition[]) {
4072 { .version = 1 },
4073 {
4074 .version = 2,
4075 .props = (PropValue[]) {
4076 { "mpx", "off" },
4077 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4078 { /* end of list */ },
4079 },
4080 },
7bde6b18
VK		 4081 {
4082 .version = 3,
4083 .note = "XSAVES, no MPX",
4084 .props = (PropValue[]) {
4085 { "xsaves", "on" },
4086 { "vmx-xsaves", "on" },
4087 { /* end of list */ },
4088 },
4089 },
56bb24e5
CQ		 4090 {
4091 .version = 4,
07db29f2 4092 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 4093 .props = (PropValue[]) {
4094 { "split-lock-detect", "off" },
07db29f2 4095 { "core-capability", "off" },
56bb24e5
CQ		 4096 { /* end of list */ },
4097 },
4098 },
69edb0f3
XL		 4099 { /* end of list */ },
4100 },
0b18874b 4101 },
a1849515
BF		 4102 {
4103 .name = "KnightsMill",
4104 .level = 0xd,
4105 .vendor = CPUID_VENDOR_INTEL,
4106 .family = 6,
4107 .model = 133,
4108 .stepping = 0,
4109 .features[FEAT_1_EDX] =
4110 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
4111 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
4112 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
4113 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
4114 CPUID_PSE | CPUID_DE | CPUID_FP87,
4115 .features[FEAT_1_ECX] =
4116 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
4117 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
4118 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
4119 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4120 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
4121 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
4122 .features[FEAT_8000_0001_EDX] =
4123 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
4124 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
4125 .features[FEAT_8000_0001_ECX] =
4126 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
4127 .features[FEAT_7_0_EBX] =
4128 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4129 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4130 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
4131 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
4132 CPUID_7_0_EBX_AVX512ER,
4133 .features[FEAT_7_0_ECX] =
4134 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
4135 .features[FEAT_7_0_EDX] =
4136 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
4137 .features[FEAT_XSAVE] =
4138 CPUID_XSAVE_XSAVEOPT,
4139 .features[FEAT_6_EAX] =
4140 CPUID_6_EAX_ARAT,
4141 .xlevel = 0x80000008,
4142 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
4143 },
3eca4642
EH		 4144 {
4145 .name = "Opteron_G1",
4146 .level = 5,
99b88a17 4147 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4148 .family = 15,
4149 .model = 6,
4150 .stepping = 1,
0514ef2f 4151 .features[FEAT_1_EDX] =
b3a4f0b1 4152 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4153 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4154 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4155 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4156 CPUID_DE | CPUID_FP87,
0514ef2f 4157 .features[FEAT_1_ECX] =
27861ecc 4158 CPUID_EXT_SSE3,
0514ef2f 4159 .features[FEAT_8000_0001_EDX] =
2a923a29 4160 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 4161 .xlevel = 0x80000008,
4162 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
4163 },
4164 {
4165 .name = "Opteron_G2",
4166 .level = 5,
99b88a17 4167 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4168 .family = 15,
4169 .model = 6,
4170 .stepping = 1,
0514ef2f 4171 .features[FEAT_1_EDX] =
b3a4f0b1 4172 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4173 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4174 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4175 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4176 CPUID_DE | CPUID_FP87,
0514ef2f 4177 .features[FEAT_1_ECX] =
27861ecc 4178 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 4179 .features[FEAT_8000_0001_EDX] =
2a923a29 4180 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 4181 .features[FEAT_8000_0001_ECX] =
27861ecc 4182 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4183 .xlevel = 0x80000008,
4184 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
4185 },
4186 {
4187 .name = "Opteron_G3",
4188 .level = 5,
99b88a17 4189 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 4190 .family = 16,
4191 .model = 2,
4192 .stepping = 3,
0514ef2f 4193 .features[FEAT_1_EDX] =
b3a4f0b1 4194 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4195 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4196 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4197 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4198 CPUID_DE | CPUID_FP87,
0514ef2f 4199 .features[FEAT_1_ECX] =
27861ecc 4200 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 4201 CPUID_EXT_SSE3,
0514ef2f 4202 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 4203 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
4204 CPUID_EXT2_RDTSCP,
0514ef2f 4205 .features[FEAT_8000_0001_ECX] =
27861ecc 4206 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 4207 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4208 .xlevel = 0x80000008,
4209 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
4210 },
4211 {
4212 .name = "Opteron_G4",
4213 .level = 0xd,
99b88a17 4214 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4215 .family = 21,
4216 .model = 1,
4217 .stepping = 2,
0514ef2f 4218 .features[FEAT_1_EDX] =
b3a4f0b1 4219 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4220 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4221 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4222 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4223 CPUID_DE | CPUID_FP87,
0514ef2f 4224 .features[FEAT_1_ECX] =
27861ecc 4225 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 4226 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4227 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
4228 CPUID_EXT_SSE3,
0514ef2f 4229 .features[FEAT_8000_0001_EDX] =
2a923a29 4230 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4231 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4232 .features[FEAT_8000_0001_ECX] =
27861ecc 4233 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4234 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4235 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4236 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4237 .features[FEAT_SVM] =
4238 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4239 /* no xsaveopt! */
3eca4642
EH		 4240 .xlevel = 0x8000001A,
4241 .model_id = "AMD Opteron 62xx class CPU",
4242 },
021941b9
AP		 4243 {
4244 .name = "Opteron_G5",
4245 .level = 0xd,
99b88a17 4246 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 4247 .family = 21,
4248 .model = 2,
4249 .stepping = 0,
0514ef2f 4250 .features[FEAT_1_EDX] =
b3a4f0b1 4251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4255 CPUID_DE | CPUID_FP87,
0514ef2f 4256 .features[FEAT_1_ECX] =
27861ecc 4257 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 4258 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
4259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4260 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 4261 .features[FEAT_8000_0001_EDX] =
2a923a29 4262 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4263 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4264 .features[FEAT_8000_0001_ECX] =
27861ecc 4265 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4266 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4267 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4268 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4269 .features[FEAT_SVM] =
4270 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4271 /* no xsaveopt! */
021941b9
AP		 4272 .xlevel = 0x8000001A,
4273 .model_id = "AMD Opteron 63xx class CPU",
4274 },
2e2efc7d
BS		 4275 {
4276 .name = "EPYC",
4277 .level = 0xd,
4278 .vendor = CPUID_VENDOR_AMD,
4279 .family = 23,
4280 .model = 1,
4281 .stepping = 2,
4282 .features[FEAT_1_EDX] =
4283 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4284 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4285 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4286 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4287 CPUID_VME | CPUID_FP87,
4288 .features[FEAT_1_ECX] =
4289 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4290 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4291 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4292 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4293 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4294 .features[FEAT_8000_0001_EDX] =
4295 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4296 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4297 CPUID_EXT2_SYSCALL,
4298 .features[FEAT_8000_0001_ECX] =
4299 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4300 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 4301 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4302 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 4303 .features[FEAT_7_0_EBX] =
4304 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4305 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4306 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4307 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 4308 .features[FEAT_XSAVE] =
4309 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4310 CPUID_XSAVE_XGETBV1,
4311 .features[FEAT_6_EAX] =
4312 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 4313 .features[FEAT_SVM] =
4314 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 4315 .xlevel = 0x8000001E,
2e2efc7d 4316 .model_id = "AMD EPYC Processor",
fe52acd2 4317 .cache_info = &epyc_cache_info,
d86a7088
EH		 4318 .versions = (X86CPUVersionDefinition[]) {
4319 { .version = 1 },
4320 {
4321 .version = 2,
53db89d9 4322 .alias = "EPYC-IBPB",
d86a7088
EH		 4323 .props = (PropValue[]) {
4324 { "ibpb", "on" },
4325 { "model-id",
4326 "AMD EPYC Processor (with IBPB)" },
4327 { /* end of list */ }
4328 }
4329 },
a16e8dbc
MB		 4330 {
4331 .version = 3,
4332 .props = (PropValue[]) {
4333 { "ibpb", "on" },
4334 { "perfctr-core", "on" },
4335 { "clzero", "on" },
4336 { "xsaveerptr", "on" },
4337 { "xsaves", "on" },
4338 { "model-id",
4339 "AMD EPYC Processor" },
4340 { /* end of list */ }
4341 }
4342 },
d7c72735
MR		 4343 {
4344 .version = 4,
4345 .props = (PropValue[]) {
4346 { "model-id",
4347 "AMD EPYC-v4 Processor" },
4348 { /* end of list */ }
4349 },
4350 .cache_info = &epyc_v4_cache_info
4351 },
d86a7088
EH		 4352 { /* end of list */ }
4353 }
2e2efc7d 4354 },
8d031cec
PW		 4355 {
4356 .name = "Dhyana",
4357 .level = 0xd,
4358 .vendor = CPUID_VENDOR_HYGON,
4359 .family = 24,
4360 .model = 0,
4361 .stepping = 1,
4362 .features[FEAT_1_EDX] =
4363 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4364 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4365 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4366 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4367 CPUID_VME | CPUID_FP87,
4368 .features[FEAT_1_ECX] =
4369 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4370 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4371 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4372 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4373 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4374 .features[FEAT_8000_0001_EDX] =
4375 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4376 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4377 CPUID_EXT2_SYSCALL,
4378 .features[FEAT_8000_0001_ECX] =
4379 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4380 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4381 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4382 CPUID_EXT3_TOPOEXT,
4383 .features[FEAT_8000_0008_EBX] =
4384 CPUID_8000_0008_EBX_IBPB,
4385 .features[FEAT_7_0_EBX] =
4386 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4387 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4388 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 4389 /* XSAVES is added in version 2 */
8d031cec
PW		 4390 .features[FEAT_XSAVE] =
4391 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4392 CPUID_XSAVE_XGETBV1,
4393 .features[FEAT_6_EAX] =
4394 CPUID_6_EAX_ARAT,
4395 .features[FEAT_SVM] =
4396 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4397 .xlevel = 0x8000001E,
4398 .model_id = "Hygon Dhyana Processor",
4399 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4400 .versions = (X86CPUVersionDefinition[]) {
4401 { .version = 1 },
4402 { .version = 2,
4403 .note = "XSAVES",
4404 .props = (PropValue[]) {
4405 { "xsaves", "on" },
4406 { /* end of list */ }
4407 },
4408 },
4409 { /* end of list */ }
4410 }
8d031cec 4411 },
143c30d4
MB		 4412 {
4413 .name = "EPYC-Rome",
4414 .level = 0xd,
4415 .vendor = CPUID_VENDOR_AMD,
4416 .family = 23,
4417 .model = 49,
4418 .stepping = 0,
4419 .features[FEAT_1_EDX] =
4420 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4421 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4422 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4423 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4424 CPUID_VME | CPUID_FP87,
4425 .features[FEAT_1_ECX] =
4426 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4427 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4428 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4429 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4430 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4431 .features[FEAT_8000_0001_EDX] =
4432 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4433 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4434 CPUID_EXT2_SYSCALL,
4435 .features[FEAT_8000_0001_ECX] =
4436 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4437 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4438 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4439 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4440 .features[FEAT_8000_0008_EBX] =
4441 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4442 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4443 CPUID_8000_0008_EBX_STIBP,
4444 .features[FEAT_7_0_EBX] =
4445 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4446 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4447 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4448 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4449 .features[FEAT_7_0_ECX] =
4450 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4451 .features[FEAT_XSAVE] =
4452 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4453 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4454 .features[FEAT_6_EAX] =
4455 CPUID_6_EAX_ARAT,
4456 .features[FEAT_SVM] =
4457 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4458 .xlevel = 0x8000001E,
4459 .model_id = "AMD EPYC-Rome Processor",
4460 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4461 .versions = (X86CPUVersionDefinition[]) {
4462 { .version = 1 },
4463 {
4464 .version = 2,
4465 .props = (PropValue[]) {
4466 { "ibrs", "on" },
4467 { "amd-ssbd", "on" },
4468 { /* end of list */ }
4469 }
4470 },
d7c72735
MR		 4471 {
4472 .version = 3,
4473 .props = (PropValue[]) {
4474 { "model-id",
4475 "AMD EPYC-Rome-v3 Processor" },
4476 { /* end of list */ }
4477 },
4478 .cache_info = &epyc_rome_v3_cache_info
4479 },
fb00aa61
MD		 4480 {
4481 .version = 4,
4482 .props = (PropValue[]) {
4483 /* Erratum 1386 */
4484 { "model-id",
4485 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
4486 { "xsaves", "off" },
4487 { /* end of list */ }
4488 },
4489 },
cdeaed27
BM		 4490 { /* end of list */ }
4491 }
143c30d4 4492 },
623972ce
BM		 4493 {
4494 .name = "EPYC-Milan",
4495 .level = 0xd,
4496 .vendor = CPUID_VENDOR_AMD,
4497 .family = 25,
4498 .model = 1,
4499 .stepping = 1,
4500 .features[FEAT_1_EDX] =
4501 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4502 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4503 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4504 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4505 CPUID_VME | CPUID_FP87,
4506 .features[FEAT_1_ECX] =
4507 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4508 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4509 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4510 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4511 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4512 CPUID_EXT_PCID,
4513 .features[FEAT_8000_0001_EDX] =
4514 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4515 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4516 CPUID_EXT2_SYSCALL,
4517 .features[FEAT_8000_0001_ECX] =
4518 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4519 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4520 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4521 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4522 .features[FEAT_8000_0008_EBX] =
4523 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4524 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4525 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4526 CPUID_8000_0008_EBX_AMD_SSBD,
4527 .features[FEAT_7_0_EBX] =
4528 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4529 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4530 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4531 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4532 CPUID_7_0_EBX_INVPCID,
4533 .features[FEAT_7_0_ECX] =
4534 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4535 .features[FEAT_7_0_EDX] =
4536 CPUID_7_0_EDX_FSRM,
4537 .features[FEAT_XSAVE] =
4538 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4539 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4540 .features[FEAT_6_EAX] =
4541 CPUID_6_EAX_ARAT,
4542 .features[FEAT_SVM] =
4543 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4544 .xlevel = 0x8000001E,
4545 .model_id = "AMD EPYC-Milan Processor",
4546 .cache_info = &epyc_milan_cache_info,
27f03be6
BM		 4547 .versions = (X86CPUVersionDefinition[]) {
4548 { .version = 1 },
4549 {
4550 .version = 2,
4551 .props = (PropValue[]) {
4552 { "model-id",
4553 "AMD EPYC-Milan-v2 Processor" },
4554 { "vaes", "on" },
4555 { "vpclmulqdq", "on" },
4556 { "stibp-always-on", "on" },
4557 { "amd-psfd", "on" },
4558 { "no-nested-data-bp", "on" },
4559 { "lfence-always-serializing", "on" },
4560 { "null-sel-clr-base", "on" },
4561 { /* end of list */ }
4562 },
4563 .cache_info = &epyc_milan_v2_cache_info
4564 },
4565 { /* end of list */ }
4566 }
623972ce 4567 },
166b1741
BM		 4568 {
4569 .name = "EPYC-Genoa",
4570 .level = 0xd,
4571 .vendor = CPUID_VENDOR_AMD,
4572 .family = 25,
4573 .model = 17,
4574 .stepping = 0,
4575 .features[FEAT_1_EDX] =
4576 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4577 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4578 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4579 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4580 CPUID_VME | CPUID_FP87,
4581 .features[FEAT_1_ECX] =
4582 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4583 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4584 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4585 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4586 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ |
4587 CPUID_EXT_SSE3,
4588 .features[FEAT_8000_0001_EDX] =
4589 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4590 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4591 CPUID_EXT2_SYSCALL,
4592 .features[FEAT_8000_0001_ECX] =
4593 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4594 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4595 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4596 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4597 .features[FEAT_8000_0008_EBX] =
4598 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4599 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4600 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4601 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON |
4602 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD,
4603 .features[FEAT_8000_0021_EAX] =
4604 CPUID_8000_0021_EAX_No_NESTED_DATA_BP |
4605 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING |
4606 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE |
4607 CPUID_8000_0021_EAX_AUTO_IBRS,
4608 .features[FEAT_7_0_EBX] =
4609 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4610 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4611 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F |
4612 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4613 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
4614 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
4615 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
4616 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
4617 .features[FEAT_7_0_ECX] =
4618 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
4619 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
4620 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
4621 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
4622 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
4623 CPUID_7_0_ECX_RDPID,
4624 .features[FEAT_7_0_EDX] =
4625 CPUID_7_0_EDX_FSRM,
4626 .features[FEAT_7_1_EAX] =
4627 CPUID_7_1_EAX_AVX512_BF16,
4628 .features[FEAT_XSAVE] =
4629 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4630 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4631 .features[FEAT_6_EAX] =
4632 CPUID_6_EAX_ARAT,
4633 .features[FEAT_SVM] =
4634 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI |
4635 CPUID_SVM_SVME_ADDR_CHK,
4636 .xlevel = 0x80000022,
4637 .model_id = "AMD EPYC-Genoa Processor",
4638 .cache_info = &epyc_genoa_cache_info,
4639 },
c6dc6f63
AP		 4640};
4641
ad183928
EH		 4642/*
4643 * We resolve CPU model aliases using -v1 when using "-machine
4644 * none", but this is just for compatibility while libvirt isn't
4645 * adapted to resolve CPU model versions before creating VMs.
32048d72 4646 * See "Runnability guarantee of CPU models" at
a476b216 4647 * docs/about/deprecated.rst.
ad183928
EH		 4648 */
4649X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4650
4651void x86_cpu_set_default_version(X86CPUVersion version)
4652{
4653 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4654 assert(version != CPU_VERSION_AUTO);
4655 default_cpu_version = version;
4656}
4657
dcafd1ef
EH		 4658static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4659{
4660 int v = 0;
4661 const X86CPUVersionDefinition *vdef =
4662 x86_cpu_def_get_versions(model->cpudef);
4663 while (vdef->version) {
4664 v = vdef->version;
4665 vdef++;
4666 }
4667 return v;
4668}
4669
4670/* Return the actual version being used for a specific CPU model */
4671static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4672{
4673 X86CPUVersion v = model->version;
0788a56b
EH		 4674 if (v == CPU_VERSION_AUTO) {
4675 v = default_cpu_version;
4676 }
dcafd1ef
EH		 4677 if (v == CPU_VERSION_LATEST) {
4678 return x86_cpu_model_last_version(model);
4679 }
4680 return v;
4681}
4682
c62f2630 4683static Property max_x86_cpu_properties[] = {
120eee7d 4684 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4685 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4686 DEFINE_PROP_END_OF_LIST()
4687};
4688
123fa102
TH		 4689static void max_x86_cpu_realize(DeviceState *dev, Error **errp)
4690{
4691 Object *obj = OBJECT(dev);
4692
4693 if (!object_property_get_int(obj, "family", &error_abort)) {
4694 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4695 object_property_set_int(obj, "family", 15, &error_abort);
4696 object_property_set_int(obj, "model", 107, &error_abort);
4697 object_property_set_int(obj, "stepping", 1, &error_abort);
4698 } else {
4699 object_property_set_int(obj, "family", 6, &error_abort);
4700 object_property_set_int(obj, "model", 6, &error_abort);
4701 object_property_set_int(obj, "stepping", 3, &error_abort);
4702 }
4703 }
4704
4705 x86_cpu_realizefn(dev, errp);
4706}
4707
c62f2630 4708static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4709{
84f1b92f 4710 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4711 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4712
f48c8837 4713 xcc->ordering = 9;
6e746f30 4714
ee465a3e 4715 xcc->model_description =
c62f2630 4716 "Enables all features supported by the accelerator in the current host";
d940ee9b 4717
4f67d30b 4718 device_class_set_props(dc, max_x86_cpu_properties);
123fa102 4719 dc->realize = max_x86_cpu_realize;
d940ee9b
EH		 4720}
4721
c62f2630 4722static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4723{
4724 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4725
4d1b279b
EH		 4726 /* We can't fill the features array here because we don't know yet if
4727 * "migratable" is true or false.
4728 */
44bd8e53 4729 cpu->max_features = true;
5325cc34 4730 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4731
4732 /*
4733 * these defaults are used for TCG and all other accelerators
4734 * besides KVM and HVF, which overwrite these values
4735 */
4736 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4737 &error_abort);
f5cc5a5c
CF		 4738 object_property_set_str(OBJECT(cpu), "model-id",
4739 "QEMU TCG CPU version " QEMU_HW_VERSION,
4740 &error_abort);
c6dc6f63
AP		 4741}
4742
c62f2630
EH		 4743static const TypeInfo max_x86_cpu_type_info = {
4744 .name = X86_CPU_TYPE_NAME("max"),
4745 .parent = TYPE_X86_CPU,
4746 .instance_init = max_x86_cpu_initfn,
4747 .class_init = max_x86_cpu_class_init,
4748};
4749
07585923
RH		 4750static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4751{
4752 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4753
4754 switch (f->type) {
4755 case CPUID_FEATURE_WORD:
4756 {
4757 const char *reg = get_register_name_32(f->cpuid.reg);
4758 assert(reg);
4759 return g_strdup_printf("CPUID.%02XH:%s",
4760 f->cpuid.eax, reg);
4761 }
4762 case MSR_FEATURE_WORD:
4763 return g_strdup_printf("MSR(%02XH)",
4764 f->msr.index);
4765 }
4766
4767 return NULL;
4768}
4769
245edd0c 4770static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4771{
245edd0c
PB		 4772 FeatureWord w;
4773
4774 for (w = 0; w < FEATURE_WORDS; w++) {
4775 if (cpu->filtered_features[w]) {
4776 return true;
4777 }
4778 }
4779
4780 return false;
4781}
4782
ede146c2 4783static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4784 const char *verbose_prefix)
4785{
4786 CPUX86State *env = &cpu->env;
8459e396 4787 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4788 int i;
4789
245edd0c
PB		 4790 if (!cpu->force_features) {
4791 env->features[w] &= ~mask;
4792 }
4793 cpu->filtered_features[w] |= mask;
4794
4795 if (!verbose_prefix) {
4796 return;
4797 }
4798
ede146c2
PB		 4799 for (i = 0; i < 64; ++i) {
4800 if ((1ULL << i) & mask) {
88703ce2 4801 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4802 warn_report("%s: %s%s%s [bit %d]",
4803 verbose_prefix,
07585923 4804 feat_word_str,
8297be80
AF		 4805 f->feat_names[i] ? "." : "",
4806 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4807 }
857aee33 4808 }
c6dc6f63
AP		 4809}
4810
d7bce999
EB		 4811static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4812 const char *name, void *opaque,
4813 Error **errp)
95b8519d
AF		 4814{
4815 X86CPU *cpu = X86_CPU(obj);
4816 CPUX86State *env = &cpu->env;
4817 int64_t value;
4818
4819 value = (env->cpuid_version >> 8) & 0xf;
4820 if (value == 0xf) {
4821 value += (env->cpuid_version >> 20) & 0xff;
4822 }
51e72bc1 4823 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4824}
4825
d7bce999
EB		 4826static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4827 const char *name, void *opaque,
4828 Error **errp)
ed5e1ec3 4829{
71ad61d3
AF		 4830 X86CPU *cpu = X86_CPU(obj);
4831 CPUX86State *env = &cpu->env;
4832 const int64_t min = 0;
4833 const int64_t max = 0xff + 0xf;
4834 int64_t value;
4835
668f62ec 4836 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4837 return;
4838 }
4839 if (value < min || value > max) {
c6bd8c70
MA		 4840 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4841 name ? name : "null", value, min, max);
71ad61d3
AF		 4842 return;
4843 }
4844
ed5e1ec3 4845 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4846 if (value > 0x0f) {
4847 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4848 } else {
71ad61d3 4849 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4850 }
4851}
4852
d7bce999
EB		 4853static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4854 const char *name, void *opaque,
4855 Error **errp)
67e30c83
AF		 4856{
4857 X86CPU *cpu = X86_CPU(obj);
4858 CPUX86State *env = &cpu->env;
4859 int64_t value;
4860
4861 value = (env->cpuid_version >> 4) & 0xf;
4862 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4863 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4864}
4865
d7bce999
EB		 4866static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4867 const char *name, void *opaque,
4868 Error **errp)
b0704cbd 4869{
c5291a4f
AF		 4870 X86CPU *cpu = X86_CPU(obj);
4871 CPUX86State *env = &cpu->env;
4872 const int64_t min = 0;
4873 const int64_t max = 0xff;
4874 int64_t value;
4875
668f62ec 4876 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4877 return;
4878 }
4879 if (value < min || value > max) {
c6bd8c70
MA		 4880 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4881 name ? name : "null", value, min, max);
c5291a4f
AF		 4882 return;
4883 }
4884
b0704cbd 4885 env->cpuid_version &= ~0xf00f0;
c5291a4f 4886 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4887}
4888
35112e41 4889static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4890 const char *name, void *opaque,
35112e41
AF		 4891 Error **errp)
4892{
4893 X86CPU *cpu = X86_CPU(obj);
4894 CPUX86State *env = &cpu->env;
4895 int64_t value;
4896
4897 value = env->cpuid_version & 0xf;
51e72bc1 4898 visit_type_int(v, name, &value, errp);
35112e41
AF		 4899}
4900
036e2222 4901static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4902 const char *name, void *opaque,
036e2222 4903 Error **errp)
38c3dc46 4904{
036e2222
AF		 4905 X86CPU *cpu = X86_CPU(obj);
4906 CPUX86State *env = &cpu->env;
4907 const int64_t min = 0;
4908 const int64_t max = 0xf;
4909 int64_t value;
4910
668f62ec 4911 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4912 return;
4913 }
4914 if (value < min || value > max) {
c6bd8c70
MA		 4915 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4916 name ? name : "null", value, min, max);
036e2222
AF		 4917 return;
4918 }
4919
38c3dc46 4920 env->cpuid_version &= ~0xf;
036e2222 4921 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4922}
4923
d480e1af
AF		 4924static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4925{
4926 X86CPU *cpu = X86_CPU(obj);
4927 CPUX86State *env = &cpu->env;
4928 char *value;
d480e1af 4929
e42a92ae 4930 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4931 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4932 env->cpuid_vendor3);
d480e1af
AF		 4933 return value;
4934}
4935
4936static void x86_cpuid_set_vendor(Object *obj, const char *value,
4937 Error **errp)
4938{
4939 X86CPU *cpu = X86_CPU(obj);
4940 CPUX86State *env = &cpu->env;
4941 int i;
4942
9df694ee 4943 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4944 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4945 return;
4946 }
4947
4948 env->cpuid_vendor1 = 0;
4949 env->cpuid_vendor2 = 0;
4950 env->cpuid_vendor3 = 0;
4951 for (i = 0; i < 4; i++) {
4952 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4953 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4954 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4955 }
d480e1af
AF		 4956}
4957
63e886eb
AF		 4958static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4959{
4960 X86CPU *cpu = X86_CPU(obj);
4961 CPUX86State *env = &cpu->env;
4962 char *value;
4963 int i;
4964
4965 value = g_malloc(48 + 1);
4966 for (i = 0; i < 48; i++) {
4967 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4968 }
4969 value[48] = '\0';
4970 return value;
4971}
4972
938d4c25
AF		 4973static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4974 Error **errp)
dcce6675 4975{
938d4c25
AF		 4976 X86CPU *cpu = X86_CPU(obj);
4977 CPUX86State *env = &cpu->env;
dcce6675
AF		 4978 int c, len, i;
4979
4980 if (model_id == NULL) {
4981 model_id = "";
4982 }
4983 len = strlen(model_id);
d0a6acf4 4984 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4985 for (i = 0; i < 48; i++) {
4986 if (i >= len) {
4987 c = '\0';
4988 } else {
4989 c = (uint8_t)model_id[i];
4990 }
4991 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4992 }
4993}
4994
d7bce999
EB		 4995static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4996 void *opaque, Error **errp)
89e48965
AF		 4997{
4998 X86CPU *cpu = X86_CPU(obj);
4999 int64_t value;
5000
5001 value = cpu->env.tsc_khz * 1000;
51e72bc1 5002 visit_type_int(v, name, &value, errp);
89e48965
AF		 5003}
5004
d7bce999
EB		 5005static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
5006 void *opaque, Error **errp)
89e48965
AF		 5007{
5008 X86CPU *cpu = X86_CPU(obj);
5009 const int64_t min = 0;
2e84849a 5010 const int64_t max = INT64_MAX;
89e48965
AF		 5011 int64_t value;
5012
668f62ec 5013 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 5014 return;
5015 }
5016 if (value < min || value > max) {
c6bd8c70
MA		 5017 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5018 name ? name : "null", value, min, max);
89e48965
AF		 5019 return;
5020 }
5021
36f96c4b 5022 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 5023}
5024
7e5292b5 5025/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 5026static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
5027 const char *name, void *opaque,
5028 Error **errp)
8e8aba50 5029{
ede146c2 5030 uint64_t *array = (uint64_t *)opaque;
8e8aba50 5031 FeatureWord w;
8e8aba50
EH		 5032 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
5033 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
5034 X86CPUFeatureWordInfoList *list = NULL;
5035
5036 for (w = 0; w < FEATURE_WORDS; w++) {
5037 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 5038 /*
5039 * We didn't have MSR features when "feature-words" was
5040 * introduced. Therefore skipped other type entries.
5041 */
5042 if (wi->type != CPUID_FEATURE_WORD) {
5043 continue;
5044 }
8e8aba50 5045 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 5046 qwi->cpuid_input_eax = wi->cpuid.eax;
5047 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
5048 qwi->cpuid_input_ecx = wi->cpuid.ecx;
5049 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 5050 qwi->features = array[w];
8e8aba50
EH		 5051
5052 /* List will be in reverse order, but order shouldn't matter */
5053 list_entries[w].next = list;
5054 list_entries[w].value = &word_infos[w];
5055 list = &list_entries[w];
5056 }
5057
6b62d961 5058 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 5059}
5060
72ac2e87
IM		 5061/* Convert all '_' in a feature string option name to '-', to make feature
5062 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5063 */
5064static inline void feat2prop(char *s)
5065{
5066 while ((s = strchr(s, '_'))) {
5067 *s = '-';
5068 }
5069}
5070
b54c9377
EH		 5071/* Return the feature property name for a feature flag bit */
5072static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
5073{
ede146c2 5074 const char *name;
b54c9377
EH		 5075 /* XSAVE components are automatically enabled by other features,
5076 * so return the original feature name instead
5077 */
301e9067
YW		 5078 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) {
5079 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr;
b54c9377
EH		 5080
5081 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
5082 x86_ext_save_areas[comp].bits) {
5083 w = x86_ext_save_areas[comp].feature;
5084 bitnr = ctz32(x86_ext_save_areas[comp].bits);
5085 }
5086 }
5087
ede146c2 5088 assert(bitnr < 64);
b54c9377 5089 assert(w < FEATURE_WORDS);
ede146c2
PB		 5090 name = feature_word_info[w].feat_names[bitnr];
5091 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
5092 return name;
b54c9377
EH		 5093}
5094
dc15c051
IM		 5095/* Compatibily hack to maintain legacy +-feat semantic,
5096 * where +-feat overwrites any feature set by
5097 * feat=on|feat even if the later is parsed after +-feat
5098 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5099 */
2fae0d96 5100static GList *plus_features, *minus_features;
dc15c051 5101
83a00f60
EH		 5102static gint compare_string(gconstpointer a, gconstpointer b)
5103{
5104 return g_strcmp0(a, b);
5105}
5106
8f961357
EH		 5107/* Parse "+feature,-feature,feature=foo" CPU feature string
5108 */
62a48a2a 5109static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 5110 Error **errp)
8f961357 5111{
8f961357 5112 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 5113 static bool cpu_globals_initialized;
83a00f60 5114 bool ambiguous = false;
62a48a2a
IM		 5115
5116 if (cpu_globals_initialized) {
5117 return;
5118 }
5119 cpu_globals_initialized = true;
8f961357 5120
f6750e95
EH		 5121 if (!features) {
5122 return;
5123 }
5124
5125 for (featurestr = strtok(features, ",");
685479bd 5126 featurestr;
f6750e95
EH		 5127 featurestr = strtok(NULL, ",")) {
5128 const char *name;
5129 const char *val = NULL;
5130 char *eq = NULL;
cf2887c9 5131 char num[32];
62a48a2a 5132 GlobalProperty *prop;
c6dc6f63 5133
f6750e95 5134 /* Compatibility syntax: */
c6dc6f63 5135 if (featurestr[0] == '+') {
2fae0d96
EH		 5136 plus_features = g_list_append(plus_features,
5137 g_strdup(featurestr + 1));
f6750e95 5138 continue;
c6dc6f63 5139 } else if (featurestr[0] == '-') {
2fae0d96
EH		 5140 minus_features = g_list_append(minus_features,
5141 g_strdup(featurestr + 1));
f6750e95
EH		 5142 continue;
5143 }
5144
5145 eq = strchr(featurestr, '=');
5146 if (eq) {
5147 *eq++ = 0;
5148 val = eq;
c6dc6f63 5149 } else {
f6750e95 5150 val = "on";
a91987c2 5151 }
f6750e95
EH		 5152
5153 feat2prop(featurestr);
5154 name = featurestr;
5155
83a00f60 5156 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 5157 warn_report("Ambiguous CPU model string. "
5158 "Don't mix both \"+%s\" and \"%s=%s\"",
5159 name, name, val);
83a00f60
EH		 5160 ambiguous = true;
5161 }
5162 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 5163 warn_report("Ambiguous CPU model string. "
5164 "Don't mix both \"-%s\" and \"%s=%s\"",
5165 name, name, val);
83a00f60
EH		 5166 ambiguous = true;
5167 }
5168
f6750e95
EH		 5169 /* Special case: */
5170 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 5171 int ret;
f46bfdbf 5172 uint64_t tsc_freq;
f6750e95 5173
f17fd4fd 5174 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 5175 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 5176 error_setg(errp, "bad numerical value %s", val);
5177 return;
5178 }
5179 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
5180 val = num;
5181 name = "tsc-frequency";
c6dc6f63 5182 }
f6750e95 5183
62a48a2a
IM		 5184 prop = g_new0(typeof(*prop), 1);
5185 prop->driver = typename;
5186 prop->property = g_strdup(name);
5187 prop->value = g_strdup(val);
62a48a2a 5188 qdev_prop_register_global(prop);
f6750e95
EH		 5189 }
5190
83a00f60 5191 if (ambiguous) {
3dc6f869
AF		 5192 warn_report("Compatibility of ambiguous CPU model "
5193 "strings won't be kept on future QEMU versions");
83a00f60 5194 }
c6dc6f63
AP		 5195}
5196
245edd0c 5197static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 5198
5a853fc5
EH		 5199/* Build a list with the name of all features on a feature word array */
5200static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 5201 strList **list)
5a853fc5 5202{
c3033fd3 5203 strList **tail = list;
5a853fc5 5204 FeatureWord w;
5a853fc5
EH		 5205
5206 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 5207 uint64_t filtered = features[w];
5a853fc5 5208 int i;
ede146c2
PB		 5209 for (i = 0; i < 64; i++) {
5210 if (filtered & (1ULL << i)) {
c3033fd3 5211 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 5212 }
5213 }
5214 }
5215}
5216
506174bf
EH		 5217static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
5218 const char *name, void *opaque,
5219 Error **errp)
5220{
5221 X86CPU *xc = X86_CPU(obj);
5222 strList *result = NULL;
5223
5224 x86_cpu_list_feature_names(xc->filtered_features, &result);
5225 visit_type_strList(v, "unavailable-features", &result, errp);
5226}
5227
8c3329e5 5228/* Print all cpuid feature names in featureset
c6dc6f63 5229 */
0442428a 5230static void listflags(GList *features)
0856579c 5231{
cc643b1e
DB		 5232 size_t len = 0;
5233 GList *tmp;
5234
5235 for (tmp = features; tmp; tmp = tmp->next) {
5236 const char *name = tmp->data;
5237 if ((len + strlen(name) + 1) >= 75) {
0442428a 5238 qemu_printf("\n");
cc643b1e 5239 len = 0;
c6dc6f63 5240 }
0442428a 5241 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 5242 len += strlen(name) + 1;
8c3329e5 5243 }
0442428a 5244 qemu_printf("\n");
c6dc6f63
AP		 5245}
5246
f48c8837 5247/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 5248static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
5249{
5250 ObjectClass *class_a = (ObjectClass *)a;
5251 ObjectClass *class_b = (ObjectClass *)b;
5252 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
5253 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 5254 int ret;
ee465a3e 5255
f48c8837 5256 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 5257 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 5258 } else {
88703ce2
EH		 5259 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
5260 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 5261 ret = strcmp(name_a, name_b);
ee465a3e 5262 }
c7dbff4b 5263 return ret;
ee465a3e
EH		 5264}
5265
5266static GSList *get_sorted_cpu_model_list(void)
5267{
5268 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
5269 list = g_slist_sort(list, x86_cpu_list_compare);
5270 return list;
5271}
5272
164e779c
EH		 5273static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
5274{
3c75e12e 5275 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 5276 char *r = object_property_get_str(obj, "model-id", &error_abort);
5277 object_unref(obj);
5278 return r;
5279}
5280
0788a56b
EH		 5281static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
5282{
5283 X86CPUVersion version;
5284
5285 if (!cc->model || !cc->model->is_alias) {
5286 return NULL;
5287 }
5288 version = x86_cpu_model_resolve_version(cc->model);
5289 if (version <= 0) {
5290 return NULL;
5291 }
5292 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
5293}
5294
ee465a3e
EH		 5295static void x86_cpu_list_entry(gpointer data, gpointer user_data)
5296{
5297 ObjectClass *oc = data;
5298 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 5299 g_autofree char *name = x86_cpu_class_get_model_name(cc);
5300 g_autofree char *desc = g_strdup(cc->model_description);
5301 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 5302 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 5303
0788a56b
EH		 5304 if (!desc && alias_of) {
5305 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
5306 desc = g_strdup("(alias configured by machine type)");
5307 } else {
5308 desc = g_strdup_printf("(alias of %s)", alias_of);
5309 }
5310 }
c63938df
TX		 5311 if (!desc && cc->model && cc->model->note) {
5312 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
5313 }
164e779c 5314 if (!desc) {
c63938df 5315 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 5316 }
5317
5dfa9e86
DB		 5318 if (cc->model && cc->model->cpudef->deprecation_note) {
5319 g_autofree char *olddesc = desc;
5320 desc = g_strdup_printf("%s (deprecated)", olddesc);
5321 }
5322
61848717 5323 qemu_printf("x86 %-20s %s\n", name, desc);
ee465a3e
EH		 5324}
5325
5326/* list available CPU models and flags */
0442428a 5327void x86_cpu_list(void)
c6dc6f63 5328{
cc643b1e 5329 int i, j;
ee465a3e 5330 GSList *list;
cc643b1e 5331 GList *names = NULL;
c6dc6f63 5332
0442428a 5333 qemu_printf("Available CPUs:\n");
ee465a3e 5334 list = get_sorted_cpu_model_list();
0442428a 5335 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 5336 g_slist_free(list);
21ad7789 5337
cc643b1e 5338 names = NULL;
3af60be2
JK		 5339 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
5340 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 5341 for (j = 0; j < 64; j++) {
cc643b1e
DB		 5342 if (fw->feat_names[j]) {
5343 names = g_list_append(names, (gpointer)fw->feat_names[j]);
5344 }
5345 }
3af60be2 5346 }
cc643b1e
DB		 5347
5348 names = g_list_sort(names, (GCompareFunc)strcmp);
5349
0442428a
MA		 5350 qemu_printf("\nRecognized CPUID flags:\n");
5351 listflags(names);
5352 qemu_printf("\n");
cc643b1e 5353 g_list_free(names);
c6dc6f63
AP		 5354}
5355
390dbc6e
PMD		 5356#ifndef CONFIG_USER_ONLY
5357
5358/* Check for missing features that may prevent the CPU class from
5359 * running using the current machine and accelerator.
5360 */
5361static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
5362 strList **list)
5363{
5364 strList **tail = list;
5365 X86CPU *xc;
5366 Error *err = NULL;
5367
5368 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
5369 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
5370 return;
5371 }
5372
5373 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5374
5375 x86_cpu_expand_features(xc, &err);
5376 if (err) {
5377 /* Errors at x86_cpu_expand_features should never happen,
5378 * but in case it does, just report the model as not
5379 * runnable at all using the "type" property.
5380 */
5381 QAPI_LIST_APPEND(tail, g_strdup("type"));
5382 error_free(err);
5383 }
5384
5385 x86_cpu_filter_features(xc, false);
5386
5387 x86_cpu_list_feature_names(xc->filtered_features, tail);
5388
5389 object_unref(OBJECT(xc));
5390}
5391
ee465a3e
EH		 5392static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
5393{
5394 ObjectClass *oc = data;
5395 X86CPUClass *cc = X86_CPU_CLASS(oc);
5396 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 5397 CpuDefinitionInfo *info;
5398
5399 info = g_malloc0(sizeof(*info));
5400 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 5401 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
5402 info->has_unavailable_features = true;
8ed877b7 5403 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 5404 info->migration_safe = cc->migration_safe;
5405 info->has_migration_safe = true;
5adbed30 5406 info->q_static = cc->static_model;
61ad65d0
RH		 5407 if (cc->model && cc->model->cpudef->deprecation_note) {
5408 info->deprecated = true;
5409 } else {
5410 info->deprecated = false;
5411 }
0788a56b
EH		 5412 /*
5413 * Old machine types won't report aliases, so that alias translation
5414 * doesn't break compatibility with previous QEMU versions.
5415 */
5416 if (default_cpu_version != CPU_VERSION_LEGACY) {
5417 info->alias_of = x86_cpu_class_get_alias_of(cc);
0788a56b 5418 }
ee465a3e 5419
54aa3de7 5420 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 5421}
5422
25a9d6ca 5423CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 5424{
5425 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 5426 GSList *list = get_sorted_cpu_model_list();
5427 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5428 g_slist_free(list);
e3966126
AL		 5429 return cpu_list;
5430}
5431
390dbc6e
PMD		 5432#endif /* !CONFIG_USER_ONLY */
5433
58f7db26
PB		 5434uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5435 bool migratable_only)
27418adf
EH		 5436{
5437 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 5438 uint64_t r = 0;
27418adf 5439
fefb41bf 5440 if (kvm_enabled()) {
07585923
RH		 5441 switch (wi->type) {
5442 case CPUID_FEATURE_WORD:
5443 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5444 wi->cpuid.ecx,
5445 wi->cpuid.reg);
5446 break;
5447 case MSR_FEATURE_WORD:
d86f9636
RH		 5448 r = kvm_arch_get_supported_msr_feature(kvm_state,
5449 wi->msr.index);
07585923
RH		 5450 break;
5451 }
d6dcc558 5452 } else if (hvf_enabled()) {
07585923
RH		 5453 if (wi->type != CPUID_FEATURE_WORD) {
5454 return 0;
5455 }
5456 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5457 wi->cpuid.ecx,
5458 wi->cpuid.reg);
fefb41bf 5459 } else if (tcg_enabled()) {
84f1b92f 5460 r = wi->tcg_features;
fefb41bf
EH		 5461 } else {
5462 return ~0;
5463 }
5ea9e9e2
PB		 5464#ifndef TARGET_X86_64
5465 if (w == FEAT_8000_0001_EDX) {
5466 r &= ~CPUID_EXT2_LM;
5467 }
5468#endif
84f1b92f
EH		 5469 if (migratable_only) {
5470 r &= x86_cpu_get_migratable_flags(w);
5471 }
5472 return r;
27418adf
EH		 5473}
5474
d19d6ffa
PB		 5475static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
5476 uint32_t *eax, uint32_t *ebx,
5477 uint32_t *ecx, uint32_t *edx)
5478{
5479 if (kvm_enabled()) {
5480 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX);
5481 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX);
5482 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX);
5483 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX);
5484 } else if (hvf_enabled()) {
5485 *eax = hvf_get_supported_cpuid(func, index, R_EAX);
5486 *ebx = hvf_get_supported_cpuid(func, index, R_EBX);
5487 *ecx = hvf_get_supported_cpuid(func, index, R_ECX);
5488 *edx = hvf_get_supported_cpuid(func, index, R_EDX);
5489 } else {
5490 *eax = 0;
5491 *ebx = 0;
5492 *ecx = 0;
5493 *edx = 0;
5494 }
5495}
5496
798d8ec0
PB		 5497static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index,
5498 uint32_t *eax, uint32_t *ebx,
5499 uint32_t *ecx, uint32_t *edx)
5500{
5501 uint32_t level, unused;
5502
5503 /* Only return valid host leaves. */
5504 switch (func) {
5505 case 2:
5506 case 4:
5507 host_cpuid(0, 0, &level, &unused, &unused, &unused);
5508 break;
5509 case 0x80000005:
5510 case 0x80000006:
5511 case 0x8000001d:
5512 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused);
5513 break;
5514 default:
5515 return;
5516 }
5517
5518 if (func > level) {
5519 *eax = 0;
5520 *ebx = 0;
5521 *ecx = 0;
5522 *edx = 0;
5523 } else {
5524 host_cpuid(func, index, eax, ebx, ecx, edx);
5525 }
5526}
5527
5b8978d8
CF		 5528/*
5529 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5530 */
f5cc5a5c 5531void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5532{
5533 PropValue *pv;
5534 for (pv = props; pv->prop; pv++) {
5535 if (!pv->value) {
5536 continue;
5537 }
5325cc34 5538 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5539 &error_abort);
5540 }
5541}
5542
5b8978d8
CF		 5543/*
5544 * Apply properties for the CPU model version specified in model.
5545 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5546 */
5547
dcafd1ef
EH		 5548static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5549{
5550 const X86CPUVersionDefinition *vdef;
5551 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5552
5553 if (version == CPU_VERSION_LEGACY) {
5554 return;
5555 }
5556
5557 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5558 PropValue *p;
5559
5560 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5561 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5562 &error_abort);
5563 }
5564
5565 if (vdef->version == version) {
5566 break;
5567 }
5568 }
5569
5570 /*
5571 * If we reached the end of the list, version number was invalid
5572 */
5573 assert(vdef->version == version);
5574}
5575
cca0a000
MR		 5576static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
5577 X86CPUModel *model)
5578{
5579 const X86CPUVersionDefinition *vdef;
5580 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5581 const CPUCaches *cache_info = model->cpudef->cache_info;
5582
5583 if (version == CPU_VERSION_LEGACY) {
5584 return cache_info;
5585 }
5586
5587 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5588 if (vdef->cache_info) {
5589 cache_info = vdef->cache_info;
5590 }
5591
5592 if (vdef->version == version) {
5593 break;
5594 }
5595 }
5596
5597 assert(vdef->version == version);
5598 return cache_info;
5599}
5600
5b8978d8
CF		 5601/*
5602 * Load data from X86CPUDefinition into a X86CPU object.
5603 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 5604 */
49e2fa85 5605static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5606{
e11fd689 5607 const X86CPUDefinition *def = model->cpudef;
61dcd775 5608 CPUX86State *env = &cpu->env;
e1c224b4 5609 FeatureWord w;
c6dc6f63 5610
f99fd7ca
EH		 5611 /*NOTE: any property set by this function should be returned by
5612 * x86_cpu_static_props(), so static expansion of
5613 * query-cpu-model-expansion is always complete.
5614 */
5615
c39c0edf 5616 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5617 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5618 &error_abort);
5325cc34 5619 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5620 &error_abort);
5621
5325cc34
MA		 5622 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5623 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5624 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5625 &error_abort);
5325cc34 5626 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5627 &error_abort);
e1c224b4
EH		 5628 for (w = 0; w < FEATURE_WORDS; w++) {
5629 env->features[w] = def->features[w];
5630 }
82beb536 5631
a9f27ea9 5632 /* legacy-cache defaults to 'off' if CPU model provides cache info */
cca0a000 5633 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model);
ab8f992e 5634
82beb536 5635 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5636
5637 /* sysenter isn't supported in compatibility mode on AMD,
5638 * syscall isn't supported in compatibility mode on Intel.
5639 * Normally we advertise the actual CPU vendor, but you can
5640 * override this using the 'vendor' property if you want to use
5641 * KVM's sysenter/syscall emulation in compatibility mode and
5642 * when doing cross vendor migration
5643 */
7c08db30 5644
f5cc5a5c
CF		 5645 /*
5646 * vendor property is set here but then overloaded with the
5647 * host cpu vendor for KVM and HVF.
5648 */
5649 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5650
dcafd1ef 5651 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5652
5653 /*
5654 * Properties in versioned CPU model are not user specified features.
5655 * We can simply clear env->user_features here since it will be filled later
5656 * in x86_cpu_expand_features() based on plus_features and minus_features.
5657 */
5658 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5659}
5660
00fcd100
AB		 5661static gchar *x86_gdb_arch_name(CPUState *cs)
5662{
5663#ifdef TARGET_X86_64
5664 return g_strdup("i386:x86-64");
5665#else
5666 return g_strdup("i386");
5667#endif
5668}
5669
d940ee9b
EH		 5670static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5671{
dcafd1ef 5672 X86CPUModel *model = data;
d940ee9b 5673 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5674 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5675
dcafd1ef 5676 xcc->model = model;
bd72159d 5677 xcc->migration_safe = true;
61ad65d0 5678 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5679}
5680
dcafd1ef 5681static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5682{
88703ce2 5683 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5684 TypeInfo ti = {
5685 .name = typename,
5686 .parent = TYPE_X86_CPU,
5687 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5688 .class_data = model,
d940ee9b
EH		 5689 };
5690
dcafd1ef 5691 type_register(&ti);
dcafd1ef
EH		 5692}
5693
5b8978d8
CF		 5694
5695/*
5696 * register builtin_x86_defs;
5697 * "max", "base" and subclasses ("host") are not registered here.
5698 * See x86_cpu_register_types for all model registrations.
5699 */
e11fd689 5700static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5701{
5702 X86CPUModel *m;
5703 const X86CPUVersionDefinition *vdef;
dcafd1ef 5704
2a923a29
EH		 5705 /* AMD aliases are handled at runtime based on CPUID vendor, so
5706 * they shouldn't be set on the CPU model table.
5707 */
5708 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5709 /* catch mistakes instead of silently truncating model_id when too long */
5710 assert(def->model_id && strlen(def->model_id) <= 48);
5711
dcafd1ef
EH		 5712 /* Unversioned model: */
5713 m = g_new0(X86CPUModel, 1);
5714 m->cpudef = def;
0788a56b
EH		 5715 m->version = CPU_VERSION_AUTO;
5716 m->is_alias = true;
dcafd1ef
EH		 5717 x86_register_cpu_model_type(def->name, m);
5718
5719 /* Versioned models: */
5720
5721 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5722 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5723 g_autofree char *name =
5724 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5725 m->cpudef = def;
5726 m->version = vdef->version;
c63938df 5727 m->note = vdef->note;
dcafd1ef 5728 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5729
5730 if (vdef->alias) {
5731 X86CPUModel *am = g_new0(X86CPUModel, 1);
5732 am->cpudef = def;
5733 am->version = vdef->version;
0788a56b 5734 am->is_alias = true;
53db89d9
EH		 5735 x86_register_cpu_model_type(vdef->alias, am);
5736 }
dcafd1ef 5737 }
2a923a29 5738
d940ee9b
EH		 5739}
5740
97afb47e
LL		 5741uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
5742{
5743 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5744 return 57; /* 57 bits virtual */
5745 } else {
5746 return 48; /* 48 bits virtual */
5747 }
5748}
5749
c6dc6f63
AP		 5750void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5751 uint32_t *eax, uint32_t *ebx,
5752 uint32_t *ecx, uint32_t *edx)
5753{
6aa9e42f
RH		 5754 X86CPU *cpu = env_archcpu(env);
5755 CPUState *cs = env_cpu(env);
d65af288 5756 uint32_t die_offset;
4ed3d478 5757 uint32_t limit;
1ce36bfe 5758 uint32_t signature[3];
f20dec0b
BM		 5759 X86CPUTopoInfo topo_info;
5760
5761 topo_info.dies_per_pkg = env->nr_dies;
5762 topo_info.cores_per_die = cs->nr_cores;
5763 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5764
4ed3d478
DB		 5765 /* Calculate & apply limits for different index ranges */
5766 if (index >= 0xC0000000) {
5767 limit = env->cpuid_xlevel2;
5768 } else if (index >= 0x80000000) {
5769 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5770 } else if (index >= 0x40000000) {
5771 limit = 0x40000001;
c6dc6f63 5772 } else {
4ed3d478
DB		 5773 limit = env->cpuid_level;
5774 }
5775
5776 if (index > limit) {
5777 /* Intel documentation states that invalid EAX input will
5778 * return the same information as EAX=cpuid_level
5779 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5780 */
5781 index = env->cpuid_level;
c6dc6f63
AP		 5782 }
5783
5784 switch(index) {
5785 case 0:
5786 *eax = env->cpuid_level;
5eb2f7a4
EH		 5787 *ebx = env->cpuid_vendor1;
5788 *edx = env->cpuid_vendor2;
5789 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5790 break;
5791 case 1:
5792 *eax = env->cpuid_version;
7e72a45c
EH		 5793 *ebx = (cpu->apic_id << 24) |
5794 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5795 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5796 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5797 *ecx |= CPUID_EXT_OSXSAVE;
5798 }
0514ef2f 5799 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5800 if (cs->nr_cores * cs->nr_threads > 1) {
5801 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5802 *edx |= CPUID_HT;
c6dc6f63 5803 }
ea39f9b6
LX		 5804 if (!cpu->enable_pmu) {
5805 *ecx &= ~CPUID_EXT_PDCM;
5806 }
c6dc6f63
AP		 5807 break;
5808 case 2:
5809 /* cache info: needed for Pentium Pro compatibility */
787aaf57 5810 if (cpu->cache_info_passthrough) {
798d8ec0 5811 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57 5812 break;
a7a0da84
MR		 5813 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5814 *eax = *ebx = *ecx = *edx = 0;
5815 break;
787aaf57 5816 }
5e891bf8 5817 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5818 *ebx = 0;
14c985cf
LM		 5819 if (!cpu->enable_l3_cache) {
5820 *ecx = 0;
5821 } else {
a9f27ea9 5822 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5823 }
a9f27ea9
EH		 5824 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5825 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5826 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5827 break;
5828 case 4:
5829 /* cache info: needed for Core compatibility */
787aaf57 5830 if (cpu->cache_info_passthrough) {
798d8ec0 5831 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
d7caf13b
IM		 5832 /*
5833 * QEMU has its own number of cores/logical cpus,
5834 * set 24..14, 31..26 bit to configured values
5835 */
5836 if (*eax & 31) {
5837 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
5838 int vcpus_per_socket = env->nr_dies * cs->nr_cores *
5839 cs->nr_threads;
5840 if (cs->nr_cores > 1) {
5841 *eax &= ~0xFC000000;
5842 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
5843 }
5844 if (host_vcpus_per_cache > vcpus_per_socket) {
5845 *eax &= ~0x3FFC000;
5846 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
5847 }
7e3482f8 5848 }
a7a0da84
MR		 5849 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5850 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5851 } else {
2f7a21c4 5852 *eax = 0;
76c2975a 5853 switch (count) {
c6dc6f63 5854 case 0: /* L1 dcache info */
a9f27ea9
EH		 5855 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5856 1, cs->nr_cores,
7e3482f8 5857 eax, ebx, ecx, edx);
c6dc6f63
AP		 5858 break;
5859 case 1: /* L1 icache info */
a9f27ea9
EH		 5860 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5861 1, cs->nr_cores,
7e3482f8 5862 eax, ebx, ecx, edx);
c6dc6f63
AP		 5863 break;
5864 case 2: /* L2 cache info */
a9f27ea9
EH		 5865 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5866 cs->nr_threads, cs->nr_cores,
7e3482f8 5867 eax, ebx, ecx, edx);
c6dc6f63 5868 break;
14c985cf 5869 case 3: /* L3 cache info */
f20dec0b 5870 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5871 if (cpu->enable_l3_cache) {
a9f27ea9 5872 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5873 (1 << die_offset), cs->nr_cores,
7e3482f8 5874 eax, ebx, ecx, edx);
14c985cf
LM		 5875 break;
5876 }
7e3482f8 5877 /* fall through */
c6dc6f63 5878 default: /* end of info */
7e3482f8 5879 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5880 break;
76c2975a
PB		 5881 }
5882 }
c6dc6f63
AP		 5883 break;
5884 case 5:
2266d443
MT		 5885 /* MONITOR/MWAIT Leaf */
5886 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5887 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5888 *ecx = cpu->mwait.ecx; /* flags */
5889 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5890 break;
5891 case 6:
5892 /* Thermal and Power Leaf */
28b8e4d0 5893 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5894 *ebx = 0;
5895 *ecx = 0;
5896 *edx = 0;
5897 break;
f7911686 5898 case 7:
13526728
EH		 5899 /* Structured Extended Feature Flags Enumeration Leaf */
5900 if (count == 0) {
80db491d
JL		 5901 /* Maximum ECX value for sub-leaves */
5902 *eax = env->cpuid_level_func7;
0514ef2f 5903 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5904 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5905 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5906 *ecx |= CPUID_7_0_ECX_OSPKE;
5907 }
95ea69fb 5908 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 5909
5910 /*
5911 * SGX cannot be emulated in software. If hardware does not
5912 * support enabling SGX and/or SGX flexible launch control,
5913 * then we need to update the VM's CPUID values accordingly.
5914 */
5915 if ((*ebx & CPUID_7_0_EBX_SGX) &&
5916 (!kvm_enabled() ||
5917 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) &
5918 CPUID_7_0_EBX_SGX))) {
5919 *ebx &= ~CPUID_7_0_EBX_SGX;
5920 }
5921
5922 if ((*ecx & CPUID_7_0_ECX_SGX_LC) &&
5923 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() ||
5924 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) &
5925 CPUID_7_0_ECX_SGX_LC))) {
5926 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
5927 }
80db491d
JL		 5928 } else if (count == 1) {
5929 *eax = env->features[FEAT_7_1_EAX];
eaaa197d 5930 *edx = env->features[FEAT_7_1_EDX];
80db491d
JL		 5931 *ebx = 0;
5932 *ecx = 0;
f7911686
YW		 5933 } else {
5934 *eax = 0;
5935 *ebx = 0;
5936 *ecx = 0;
5937 *edx = 0;
5938 }
5939 break;
c6dc6f63
AP		 5940 case 9:
5941 /* Direct Cache Access Information Leaf */
5942 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5943 *ebx = 0;
5944 *ecx = 0;
5945 *edx = 0;
5946 break;
5947 case 0xA:
5948 /* Architectural Performance Monitoring Leaf */
d19d6ffa
PB		 5949 if (accel_uses_host_cpuid() && cpu->enable_pmu) {
5950 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx);
a0fa8208
GN		 5951 } else {
5952 *eax = 0;
5953 *ebx = 0;
5954 *ecx = 0;
5955 *edx = 0;
5956 }
c6dc6f63 5957 break;
5232d00a
RK		 5958 case 0xB:
5959 /* Extended Topology Enumeration Leaf */
5960 if (!cpu->enable_cpuid_0xb) {
5961 *eax = *ebx = *ecx = *edx = 0;
5962 break;
5963 }
5964
5965 *ecx = count & 0xff;
5966 *edx = cpu->apic_id;
5967
5968 switch (count) {
5969 case 0:
f20dec0b 5970 *eax = apicid_core_offset(&topo_info);
eab60fb9 5971 *ebx = cs->nr_threads;
5232d00a
RK		 5972 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5973 break;
5974 case 1:
fb49865d 5975 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5976 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5977 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5978 break;
5979 default:
5980 *eax = 0;
5981 *ebx = 0;
5982 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5983 }
5984
a94e1428
LX		 5985 assert(!(*eax & ~0x1f));
5986 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5987 break;
c3c67679
YW		 5988 case 0x1C:
5989 if (accel_uses_host_cpuid() && cpu->enable_pmu &&
5990 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
5991 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
5992 *edx = 0;
5993 }
5994 break;
a94e1428
LX		 5995 case 0x1F:
5996 /* V2 Extended Topology Enumeration Leaf */
5997 if (env->nr_dies < 2) {
5998 *eax = *ebx = *ecx = *edx = 0;
5999 break;
6000 }
6001
6002 *ecx = count & 0xff;
6003 *edx = cpu->apic_id;
6004 switch (count) {
6005 case 0:
f20dec0b 6006 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 6007 *ebx = cs->nr_threads;
6008 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
6009 break;
6010 case 1:
f20dec0b 6011 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 6012 *ebx = cs->nr_cores * cs->nr_threads;
6013 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
6014 break;
6015 case 2:
fb49865d 6016 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 6017 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
6018 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
6019 break;
6020 default:
6021 *eax = 0;
6022 *ebx = 0;
6023 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
6024 }
5232d00a
RK		 6025 assert(!(*eax & ~0x1f));
6026 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
6027 break;
2560f19f 6028 case 0xD: {
51e49430 6029 /* Processor Extended State */
2560f19f
PB		 6030 *eax = 0;
6031 *ebx = 0;
6032 *ecx = 0;
6033 *edx = 0;
19dc85db 6034 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 6035 break;
6036 }
4928cd6d 6037
2560f19f 6038 if (count == 0) {
301e9067
YW		 6039 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false);
6040 *eax = env->features[FEAT_XSAVE_XCR0_LO];
6041 *edx = env->features[FEAT_XSAVE_XCR0_HI];
76ecd7a5
BS		 6042 /*
6043 * The initial value of xcr0 and ebx == 0, On host without kvm
6044 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
6045 * even through guest update xcr0, this will crash some legacy guest
6046 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
6047 */
301e9067 6048 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false);
2560f19f 6049 } else if (count == 1) {
301e9067
YW		 6050 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) |
6051 x86_cpu_xsave_xss_components(cpu);
6052
0bb0b2d2 6053 *eax = env->features[FEAT_XSAVE];
301e9067
YW		 6054 *ebx = xsave_area_size(xstate, true);
6055 *ecx = env->features[FEAT_XSAVE_XSS_LO];
6056 *edx = env->features[FEAT_XSAVE_XSS_HI];
c3c67679
YW		 6057 if (kvm_enabled() && cpu->enable_pmu &&
6058 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
6059 (*eax & CPUID_XSAVE_XSAVES)) {
6060 *ecx |= XSTATE_ARCH_LBR_MASK;
6061 } else {
6062 *ecx &= ~XSTATE_ARCH_LBR_MASK;
6063 }
6064 } else if (count == 0xf &&
6065 accel_uses_host_cpuid() && cpu->enable_pmu &&
6066 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
6067 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
f4f1110e 6068 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
301e9067
YW		 6069 const ExtSaveArea *esa = &x86_ext_save_areas[count];
6070
6071 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) {
33f373d7
LJ		 6072 *eax = esa->size;
6073 *ebx = esa->offset;
0f17f6b3
JL		 6074 *ecx = esa->ecx &
6075 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
301e9067
YW		 6076 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) {
6077 *eax = esa->size;
6078 *ebx = 0;
6079 *ecx = 1;
2560f19f 6080 }
51e49430
SY		 6081 }
6082 break;
2560f19f 6083 }
1dec2e1f
SC		 6084 case 0x12:
6085#ifndef CONFIG_USER_ONLY
6086 if (!kvm_enabled() ||
6087 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
6088 *eax = *ebx = *ecx = *edx = 0;
6089 break;
6090 }
6091
6092 /*
6093 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
6094 * the EPC properties, e.g. confidentiality and integrity, from the
6095 * host's first EPC section, i.e. assume there is one EPC section or
6096 * that all EPC sections have the same security properties.
6097 */
6098 if (count > 1) {
6099 uint64_t epc_addr, epc_size;
6100
6101 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
6102 *eax = *ebx = *ecx = *edx = 0;
6103 break;
6104 }
6105 host_cpuid(index, 2, eax, ebx, ecx, edx);
6106 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
6107 *ebx = (uint32_t)(epc_addr >> 32);
6108 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
6109 *edx = (uint32_t)(epc_size >> 32);
6110 break;
6111 }
6112
6113 /*
6114 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
6115 * and KVM, i.e. QEMU cannot emulate features to override what KVM
6116 * supports. Features can be further restricted by userspace, but not
6117 * made more permissive.
6118 */
b0f3184e 6119 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx);
1dec2e1f
SC		 6120
6121 if (count == 0) {
6122 *eax &= env->features[FEAT_SGX_12_0_EAX];
6123 *ebx &= env->features[FEAT_SGX_12_0_EBX];
6124 } else {
6125 *eax &= env->features[FEAT_SGX_12_1_EAX];
6126 *ebx &= 0; /* ebx reserve */
72497cff
YZ		 6127 *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
6128 *edx &= env->features[FEAT_XSAVE_XCR0_HI];
1dec2e1f
SC		 6129
6130 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
6131 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
6132
6133 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 6134 if ((*eax & (1U << 4)) &&
6135 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
6136 *eax &= ~(1U << 4);
6137 }
1dec2e1f
SC		 6138 }
6139#endif
6140 break;
e37a5c7f
CP		 6141 case 0x14: {
6142 /* Intel Processor Trace Enumeration */
6143 *eax = 0;
6144 *ebx = 0;
6145 *ecx = 0;
6146 *edx = 0;
6147 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
6148 !kvm_enabled()) {
6149 break;
6150 }
6151
6152 if (count == 0) {
6153 *eax = INTEL_PT_MAX_SUBLEAF;
6154 *ebx = INTEL_PT_MINIMAL_EBX;
6155 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 6156 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
6157 *ecx |= CPUID_14_0_ECX_LIP;
6158 }
e37a5c7f
CP		 6159 } else if (count == 1) {
6160 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
6161 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
6162 }
6163 break;
6164 }
f21a4817 6165 case 0x1D: {
7eb061b0 6166 /* AMX TILE, for now hardcoded for Sapphire Rapids*/
f21a4817
JL		 6167 *eax = 0;
6168 *ebx = 0;
6169 *ecx = 0;
6170 *edx = 0;
6171 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6172 break;
6173 }
6174
6175 if (count == 0) {
6176 /* Highest numbered palette subleaf */
6177 *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
6178 } else if (count == 1) {
6179 *eax = INTEL_AMX_TOTAL_TILE_BYTES |
6180 (INTEL_AMX_BYTES_PER_TILE << 16);
6181 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
6182 *ecx = INTEL_AMX_TILE_MAX_ROWS;
6183 }
6184 break;
6185 }
6186 case 0x1E: {
7eb061b0 6187 /* AMX TMUL, for now hardcoded for Sapphire Rapids */
f21a4817
JL		 6188 *eax = 0;
6189 *ebx = 0;
6190 *ecx = 0;
6191 *edx = 0;
6192 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6193 break;
6194 }
6195
6196 if (count == 0) {
6197 /* Highest numbered palette subleaf */
6198 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
6199 }
6200 break;
6201 }
1ce36bfe
DB		 6202 case 0x40000000:
6203 /*
6204 * CPUID code in kvm_arch_init_vcpu() ignores stuff
6205 * set here, but we restrict to TCG none the less.
6206 */
6207 if (tcg_enabled() && cpu->expose_tcg) {
6208 memcpy(signature, "TCGTCGTCGTCG", 12);
6209 *eax = 0x40000001;
6210 *ebx = signature[0];
6211 *ecx = signature[1];
6212 *edx = signature[2];
6213 } else {
6214 *eax = 0;
6215 *ebx = 0;
6216 *ecx = 0;
6217 *edx = 0;
6218 }
6219 break;
6220 case 0x40000001:
6221 *eax = 0;
6222 *ebx = 0;
6223 *ecx = 0;
6224 *edx = 0;
6225 break;
c6dc6f63
AP		 6226 case 0x80000000:
6227 *eax = env->cpuid_xlevel;
6228 *ebx = env->cpuid_vendor1;
6229 *edx = env->cpuid_vendor2;
6230 *ecx = env->cpuid_vendor3;
6231 break;
6232 case 0x80000001:
6233 *eax = env->cpuid_version;
6234 *ebx = 0;
0514ef2f
EH		 6235 *ecx = env->features[FEAT_8000_0001_ECX];
6236 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 6237
6238 /* The Linux kernel checks for the CMPLegacy bit and
6239 * discards multiple thread information if it is set.
cb8d4c8f 6240 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 6241 */
ce3960eb 6242 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 6243 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
6244 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
6245 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 6246 *ecx |= 1 << 1; /* CmpLegacy bit */
6247 }
6248 }
fd5dcb1c
PB		 6249 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 &&
6250 !(env->hflags & HF_LMA_MASK)) {
6251 *edx &= ~CPUID_EXT2_SYSCALL;
6252 }
c6dc6f63
AP		 6253 break;
6254 case 0x80000002:
6255 case 0x80000003:
6256 case 0x80000004:
6257 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
6258 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
6259 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
6260 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
6261 break;
6262 case 0x80000005:
6263 /* cache info (L1 cache) */
787aaf57 6264 if (cpu->cache_info_passthrough) {
798d8ec0 6265 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6266 break;
6267 }
78ee6bd0 6268 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 6269 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 6270 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 6271 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6272 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
6273 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 6274 break;
6275 case 0x80000006:
6276 /* cache info (L2 cache) */
787aaf57 6277 if (cpu->cache_info_passthrough) {
798d8ec0 6278 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6279 break;
6280 }
78ee6bd0
PMD		 6281 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
6282 (L2_DTLB_2M_ENTRIES << 16) |
6283 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 6284 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 6285 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
6286 (L2_DTLB_4K_ENTRIES << 16) |
6287 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 6288 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6289 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
6290 cpu->enable_l3_cache ?
6291 env->cache_info_amd.l3_cache : NULL,
6292 ecx, edx);
c6dc6f63 6293 break;
303752a9
MT		 6294 case 0x80000007:
6295 *eax = 0;
6296 *ebx = 0;
6297 *ecx = 0;
6298 *edx = env->features[FEAT_8000_0007_EDX];
6299 break;
c6dc6f63
AP		 6300 case 0x80000008:
6301 /* virtual & phys address size in low 2 bytes. */
97afb47e 6302 *eax = cpu->phys_bits;
0514ef2f 6303 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 6304 /* 64 bit processor */
97afb47e 6305 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
c6dc6f63 6306 }
1b3420e1 6307 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 6308 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 6309 /*
6310 * Bits 15:12 is "The number of bits in the initial
6311 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 6312 * thread ID within a package".
cac9edfc
BM		 6313 * Bits 7:0 is "The number of threads in the package is NC+1"
6314 */
fb49865d 6315 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 6316 ((cs->nr_cores * cs->nr_threads) - 1);
6317 } else {
6318 *ecx = 0;
c6dc6f63 6319 }
cac9edfc 6320 *edx = 0;
c6dc6f63
AP		 6321 break;
6322 case 0x8000000A:
0514ef2f 6323 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 6324 *eax = 0x00000001; /* SVM Revision */
6325 *ebx = 0x00000010; /* nr of ASIDs */
6326 *ecx = 0;
0514ef2f 6327 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 6328 } else {
6329 *eax = 0;
6330 *ebx = 0;
6331 *ecx = 0;
6332 *edx = 0;
6333 }
c6dc6f63 6334 break;
8f4202fb
BM		 6335 case 0x8000001D:
6336 *eax = 0;
a4e0b436 6337 if (cpu->cache_info_passthrough) {
798d8ec0 6338 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
a4e0b436
SL		 6339 break;
6340 }
8f4202fb
BM		 6341 switch (count) {
6342 case 0: /* L1 dcache info */
2f084d1e
BM		 6343 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
6344 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6345 break;
6346 case 1: /* L1 icache info */
2f084d1e
BM		 6347 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
6348 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6349 break;
6350 case 2: /* L2 cache info */
2f084d1e
BM		 6351 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
6352 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6353 break;
6354 case 3: /* L3 cache info */
2f084d1e
BM		 6355 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
6356 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6357 break;
6358 default: /* end of info */
6359 *eax = *ebx = *ecx = *edx = 0;
6360 break;
6361 }
6362 break;
ed78467a 6363 case 0x8000001E:
35ac5dfb
BM		 6364 if (cpu->core_id <= 255) {
6365 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
6366 } else {
6367 *eax = 0;
6368 *ebx = 0;
6369 *ecx = 0;
6370 *edx = 0;
6371 }
ed78467a 6372 break;
b3baa152
BW		 6373 case 0xC0000000:
6374 *eax = env->cpuid_xlevel2;
6375 *ebx = 0;
6376 *ecx = 0;
6377 *edx = 0;
6378 break;
6379 case 0xC0000001:
6380 /* Support for VIA CPU's CPUID instruction */
6381 *eax = env->cpuid_version;
6382 *ebx = 0;
6383 *ecx = 0;
0514ef2f 6384 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 6385 break;
6386 case 0xC0000002:
6387 case 0xC0000003:
6388 case 0xC0000004:
6389 /* Reserved for the future, and now filled with zero */
6390 *eax = 0;
6391 *ebx = 0;
6392 *ecx = 0;
6393 *edx = 0;
6394 break;
6cb8f2a6 6395 case 0x8000001F:
02eacf31
PMD		 6396 *eax = *ebx = *ecx = *edx = 0;
6397 if (sev_enabled()) {
6398 *eax = 0x2;
6399 *eax |= sev_es_enabled() ? 0x8 : 0;
fb6bbafc
TL		 6400 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
6401 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
02eacf31 6402 }
6cb8f2a6 6403 break;
b70eec31
BM		 6404 case 0x80000021:
6405 *eax = env->features[FEAT_8000_0021_EAX];
6406 *ebx = *ecx = *edx = 0;
6407 break;
c6dc6f63
AP		 6408 default:
6409 /* reserved values: zero */
6410 *eax = 0;
6411 *ebx = 0;
6412 *ecx = 0;
6413 *edx = 0;
6414 break;
6415 }
6416}
5fd2087a 6417
db888065
SC		 6418static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
6419{
6420#ifndef CONFIG_USER_ONLY
6421 /* Those default values are defined in Skylake HW */
6422 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
6423 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
6424 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
6425 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
6426#endif
6427}
6428
e86787d3 6429static void x86_cpu_reset_hold(Object *obj)
5fd2087a 6430{
e86787d3 6431 CPUState *s = CPU(obj);
5fd2087a
AF		 6432 X86CPU *cpu = X86_CPU(s);
6433 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
6434 CPUX86State *env = &cpu->env;
a114d25d
RH		 6435 target_ulong cr4;
6436 uint64_t xcr0;
c1958aea
AF		 6437 int i;
6438
e86787d3
PM		 6439 if (xcc->parent_phases.hold) {
6440 xcc->parent_phases.hold(obj);
6441 }
5fd2087a 6442
5e992a8e 6443 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 6444
c1958aea
AF		 6445 env->old_exception = -1;
6446
6447 /* init to reset state */
e3126a5c 6448 env->int_ctl = 0;
c1958aea 6449 env->hflags2 |= HF2_GIF_MASK;
b67e2796 6450 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 6451 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 6452
6453 cpu_x86_update_cr0(env, 0x60000010);
6454 env->a20_mask = ~0x0;
6455 env->smbase = 0x30000;
e13713db 6456 env->msr_smi_count = 0;
c1958aea
AF		 6457
6458 env->idt.limit = 0xffff;
6459 env->gdt.limit = 0xffff;
6460 env->ldt.limit = 0xffff;
6461 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
6462 env->tr.limit = 0xffff;
6463 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
6464
6465 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
6466 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
6467 DESC_R_MASK | DESC_A_MASK);
6468 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
6469 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6470 DESC_A_MASK);
6471 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
6472 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6473 DESC_A_MASK);
6474 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6475 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6476 DESC_A_MASK);
6477 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6478 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6479 DESC_A_MASK);
6480 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6481 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6482 DESC_A_MASK);
6483
6484 env->eip = 0xfff0;
6485 env->regs[R_EDX] = env->cpuid_version;
6486
6487 env->eflags = 0x2;
6488
6489 /* FPU init */
6490 for (i = 0; i < 8; i++) {
6491 env->fptags[i] = 1;
6492 }
5bde1407 6493 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 6494
6495 env->mxcsr = 0x1f80;
a114d25d
RH		 6496 /* All units are in INIT state. */
6497 env->xstate_bv = 0;
c1958aea
AF		 6498
6499 env->pat = 0x0007040600070406ULL;
5286c366
PB		 6500
6501 if (kvm_enabled()) {
6502 /*
6503 * KVM handles TSC = 0 specially and thinks we are hot-plugging
6504 * a new CPU, use 1 instead to force a reset.
6505 */
6506 if (env->tsc != 0) {
6507 env->tsc = 1;
6508 }
6509 } else {
6510 env->tsc = 0;
6511 }
6512
c1958aea 6513 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 6514 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6515 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6516 }
c1958aea
AF		 6517
6518 memset(env->dr, 0, sizeof(env->dr));
6519 env->dr[6] = DR6_FIXED_1;
6520 env->dr[7] = DR7_FIXED_1;
b3310ab3 6521 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 6522 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 6523
a114d25d 6524 cr4 = 0;
cfc3b074 6525 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 6526
6527#ifdef CONFIG_USER_ONLY
6528 /* Enable all the features for user-mode. */
6529 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 6530 xcr0 |= XSTATE_SSE_MASK;
a114d25d 6531 }
0f70ed47
PB		 6532 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6533 const ExtSaveArea *esa = &x86_ext_save_areas[i];
301e9067
YW		 6534 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
6535 continue;
6536 }
9646f492 6537 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 6538 xcr0 |= 1ull << i;
6539 }
a114d25d 6540 }
0f70ed47 6541
a114d25d
RH		 6542 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6543 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6544 }
07929f2a
RH		 6545 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6546 cr4 |= CR4_FSGSBASE_MASK;
6547 }
a114d25d
RH		 6548#endif
6549
6550 env->xcr0 = xcr0;
6551 cpu_x86_update_cr4(env, cr4);
0522604b 6552
9db2efd9
AW		 6553 /*
6554 * SDM 11.11.5 requires:
6555 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6556 * - IA32_MTRR_PHYSMASKn.V = 0
6557 * All other bits are undefined. For simplification, zero it all.
6558 */
6559 env->mtrr_deftype = 0;
6560 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6561 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6562
b7394c83 6563 env->interrupt_injected = -1;
fd13f23b
LA		 6564 env->exception_nr = -1;
6565 env->exception_pending = 0;
6566 env->exception_injected = 0;
6567 env->exception_has_payload = false;
6568 env->exception_payload = 0;
b7394c83 6569 env->nmi_injected = false;
12f89a39 6570 env->triple_fault_pending = false;
dd673288
IM		 6571#if !defined(CONFIG_USER_ONLY)
6572 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 6573 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 6574
259186a7 6575 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 6576
6577 if (kvm_enabled()) {
6578 kvm_arch_reset_vcpu(cpu);
6579 }
db888065
SC		 6580
6581 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862 6582
3e4546d5 6583 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
cabf9862 6584
dd673288 6585#endif
5fd2087a
AF		 6586}
6587
ec19444a
MS		 6588void x86_cpu_after_reset(X86CPU *cpu)
6589{
6590#ifndef CONFIG_USER_ONLY
6591 if (kvm_enabled()) {
6592 kvm_arch_after_reset_vcpu(cpu);
6593 }
6594
6595 if (cpu->apic_state) {
08c4f4db 6596 device_cold_reset(cpu->apic_state);
ec19444a
MS		 6597 }
6598#endif
6599}
6600
de024815
AF		 6601static void mce_init(X86CPU *cpu)
6602{
6603 CPUX86State *cenv = &cpu->env;
6604 unsigned int bank;
6605
6606 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 6607 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 6608 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 6609 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6610 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 6611 cenv->mcg_ctl = ~(uint64_t)0;
6612 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6613 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6614 }
6615 }
6616}
6617
c39c0edf
EH		 6618static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6619{
6620 if (*min < value) {
6621 *min = value;
6622 }
6623}
6624
6625/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6626static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6627{
6628 CPUX86State *env = &cpu->env;
6629 FeatureWordInfo *fi = &feature_word_info[w];
07585923 6630 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 6631 uint32_t region = eax & 0xF0000000;
6632
07585923 6633 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 6634 if (!env->features[w]) {
6635 return;
6636 }
6637
6638 switch (region) {
6639 case 0x00000000:
6640 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6641 break;
6642 case 0x80000000:
6643 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6644 break;
6645 case 0xC0000000:
6646 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6647 break;
6648 }
80db491d
JL		 6649
6650 if (eax == 7) {
6651 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6652 fi->cpuid.ecx);
6653 }
c39c0edf
EH		 6654}
6655
2ca8a8be
EH		 6656/* Calculate XSAVE components based on the configured CPU feature flags */
6657static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6658{
6659 CPUX86State *env = &cpu->env;
6660 int i;
96193c22 6661 uint64_t mask;
19db68ca 6662 static bool request_perm;
2ca8a8be
EH		 6663
6664 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
301e9067
YW		 6665 env->features[FEAT_XSAVE_XCR0_LO] = 0;
6666 env->features[FEAT_XSAVE_XCR0_HI] = 0;
2ca8a8be
EH		 6667 return;
6668 }
6669
e3c9022b
EH		 6670 mask = 0;
6671 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6672 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6673 if (env->features[esa->feature] & esa->bits) {
96193c22 6674 mask |= (1ULL << i);
2ca8a8be
EH		 6675 }
6676 }
6677
19db68ca
YZ		 6678 /* Only request permission for first vcpu */
6679 if (kvm_enabled() && !request_perm) {
6680 kvm_request_xsave_components(cpu, mask);
6681 request_perm = true;
6682 }
6683
301e9067
YW		 6684 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK;
6685 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32;
6686 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK;
6687 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32;
2ca8a8be
EH		 6688}
6689
b8d834a0
EH		 6690/***** Steps involved on loading and filtering CPUID data
6691 *
6692 * When initializing and realizing a CPU object, the steps
6693 * involved in setting up CPUID data are:
6694 *
6695 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6696 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6697 * transparent, as it is done automatically by instance_init.
6698 * No code should need to look at X86CPUDefinition structs
6699 * outside instance_init.
6700 *
6701 * 2) CPU expansion. This is done by realize before CPUID
6702 * filtering, and will make sure host/accelerator data is
6703 * loaded for CPU models that depend on host capabilities
6704 * (e.g. "host"). Done by x86_cpu_expand_features().
6705 *
6706 * 3) CPUID filtering. This initializes extra data related to
6707 * CPUID, and checks if the host supports all capabilities
6708 * required by the CPU. Runnability of a CPU model is
6709 * determined at this step. Done by x86_cpu_filter_features().
6710 *
6711 * Some operations don't require all steps to be performed.
6712 * More precisely:
6713 *
6714 * - CPU instance creation (instance_init) will run only CPU
6715 * model loading. CPU expansion can't run at instance_init-time
6716 * because host/accelerator data may be not available yet.
6717 * - CPU realization will perform both CPU model expansion and CPUID
6718 * filtering, and return an error in case one of them fails.
6719 * - query-cpu-definitions needs to run all 3 steps. It needs
6720 * to run CPUID filtering, as the 'unavailable-features'
6721 * field is set based on the filtering results.
6722 * - The query-cpu-model-expansion QMP command only needs to run
6723 * CPU model loading and CPU expansion. It should not filter
6724 * any CPUID data based on host capabilities.
6725 */
6726
6727/* Expand CPU configuration data, based on configured features
6728 * and host/accelerator capabilities when appropriate.
6729 */
79f1a68a 6730void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6731{
b34d12d1 6732 CPUX86State *env = &cpu->env;
dc15c051 6733 FeatureWord w;
99e24dbd 6734 int i;
2fae0d96 6735 GList *l;
9886e834 6736
99e24dbd
PB		 6737 for (l = plus_features; l; l = l->next) {
6738 const char *prop = l->data;
992861fb
MA		 6739 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6740 return;
99e24dbd
PB		 6741 }
6742 }
6743
6744 for (l = minus_features; l; l = l->next) {
6745 const char *prop = l->data;
992861fb
MA		 6746 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6747 return;
99e24dbd
PB		 6748 }
6749 }
6750
d4a606b3
EH		 6751 /*TODO: Now cpu->max_features doesn't overwrite features
6752 * set using QOM properties, and we can convert
dc15c051
IM		 6753 * plus_features & minus_features to global properties
6754 * inside x86_cpu_parse_featurestr() too.
6755 */
44bd8e53 6756 if (cpu->max_features) {
dc15c051 6757 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6758 /* Override only features that weren't set explicitly
6759 * by the user.
6760 */
6761 env->features[w] |=
6762 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 6763 ~env->user_features[w] &
0d914f39 6764 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6765 }
6766 }
6767
99e24dbd
PB		 6768 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6769 FeatureDep *d = &feature_dependencies[i];
6770 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6771 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6772
99e24dbd
PB		 6773 /* Not an error unless the dependent feature was added explicitly. */
6774 mark_unavailable_features(cpu, d->to.index,
6775 unavailable_features & env->user_features[d->to.index],
6776 "This feature depends on other features that were not requested");
6777
99e24dbd 6778 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6779 }
dc15c051
IM		 6780 }
6781
aec661de
EH		 6782 if (!kvm_enabled() || !cpu->expose_kvm) {
6783 env->features[FEAT_KVM] = 0;
6784 }
6785
2ca8a8be 6786 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6787
6788 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6789 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6790 if (cpu->full_cpuid_auto_level) {
6791 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6792 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6793 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6794 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6795 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6796 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6797 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6798 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6799 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6800 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6801 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6802 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6803
6804 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6805 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6806 if (cpu->intel_pt_auto_level) {
6807 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6808 } else if (cpu->env.cpuid_min_level < 0x14) {
6809 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6810 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 6811 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 6812 }
f24c3a79
LK		 6813 }
6814
760746ac
ZP		 6815 /*
6816 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6817 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6818 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6819 * cpu->vendor_cpuid_only has been unset for compatibility with older
6820 * machine types.
6821 */
6822 if ((env->nr_dies > 1) &&
6823 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 6824 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6825 }
6826
0c3d7c00
EH		 6827 /* SVM requires CPUID[0x8000000A] */
6828 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6829 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6830 }
6cb8f2a6
BS		 6831
6832 /* SEV requires CPUID[0x8000001F] */
6833 if (sev_enabled()) {
6834 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6835 }
dca6cffc 6836
b70eec31
BM		 6837 if (env->features[FEAT_8000_0021_EAX]) {
6838 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
6839 }
6840
dca6cffc
SC		 6841 /* SGX requires CPUID[0x12] for EPC enumeration */
6842 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
6843 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
6844 }
c39c0edf
EH		 6845 }
6846
6847 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6848 if (env->cpuid_level_func7 == UINT32_MAX) {
6849 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6850 }
c39c0edf
EH		 6851 if (env->cpuid_level == UINT32_MAX) {
6852 env->cpuid_level = env->cpuid_min_level;
6853 }
6854 if (env->cpuid_xlevel == UINT32_MAX) {
6855 env->cpuid_xlevel = env->cpuid_min_xlevel;
6856 }
6857 if (env->cpuid_xlevel2 == UINT32_MAX) {
6858 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6859 }
071ce4b0
VK		 6860
6861 if (kvm_enabled()) {
6862 kvm_hyperv_expand_features(cpu, errp);
6863 }
41f3d4d6
EH		 6864}
6865
b8d834a0
EH		 6866/*
6867 * Finishes initialization of CPUID data, filters CPU feature
6868 * words based on host availability of each feature.
6869 *
6870 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6871 */
245edd0c 6872static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6873{
6874 CPUX86State *env = &cpu->env;
6875 FeatureWord w;
245edd0c
PB		 6876 const char *prefix = NULL;
6877
6878 if (verbose) {
6879 prefix = accel_uses_host_cpuid()
6880 ? "host doesn't support requested feature"
6881 : "TCG doesn't support requested feature";
6882 }
b8d834a0
EH		 6883
6884 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6885 uint64_t host_feat =
b8d834a0 6886 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6887 uint64_t requested_features = env->features[w];
6888 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6889 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6890 }
6891
e37a5c7f
CP		 6892 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6893 kvm_enabled()) {
6894 KVMState *s = CPU(cpu)->kvm_state;
6895 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6896 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6897 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6898 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6899 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6900
6901 if (!eax_0 ||
6902 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6903 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6904 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6905 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6906 INTEL_PT_ADDR_RANGES_NUM) ||
6907 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6908 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6909 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6910 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6911 /*
6912 * Processor Trace capabilities aren't configurable, so if the
6913 * host can't emulate the capabilities we report on
6914 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6915 */
245edd0c 6916 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6917 }
6918 }
b8d834a0
EH		 6919}
6920
08856771
VK		 6921static void x86_cpu_hyperv_realize(X86CPU *cpu)
6922{
6923 size_t len;
6924
6925 /* Hyper-V vendor id */
6926 if (!cpu->hyperv_vendor) {
4519259a
VK		 6927 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
6928 &error_abort);
6929 }
6930 len = strlen(cpu->hyperv_vendor);
6931 if (len > 12) {
6932 warn_report("hv-vendor-id truncated to 12 characters");
6933 len = 12;
08856771 6934 }
4519259a
VK		 6935 memset(cpu->hyperv_vendor_id, 0, 12);
6936 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 6937
6938 /* 'Hv#1' interface identification*/
6939 cpu->hyperv_interface_id[0] = 0x31237648;
6940 cpu->hyperv_interface_id[1] = 0;
6941 cpu->hyperv_interface_id[2] = 0;
6942 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 6943
23eb5d03
VK		 6944 /* Hypervisor implementation limits */
6945 cpu->hyperv_limits[0] = 64;
6946 cpu->hyperv_limits[1] = 0;
6947 cpu->hyperv_limits[2] = 0;
08856771
VK		 6948}
6949
41f3d4d6
EH		 6950static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6951{
6952 CPUState *cs = CPU(dev);
6953 X86CPU *cpu = X86_CPU(dev);
6954 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6955 CPUX86State *env = &cpu->env;
6956 Error *local_err = NULL;
6957 static bool ht_warned;
f06d8a18 6958 unsigned requested_lbr_fmt;
41f3d4d6 6959
492f8b88
AJ		 6960 /* Use pc-relative instructions in system-mode */
6961#ifndef CONFIG_USER_ONLY
6962 cs->tcg_cflags |= CF_PCREL;
6963#endif
6964
41f3d4d6
EH		 6965 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6966 error_setg(errp, "apic-id property was not initialized properly");
6967 return;
6968 }
6969
662175b9
CF		 6970 /*
6971 * Process Hyper-V enlightenments.
6972 * Note: this currently has to happen before the expansion of CPU features.
6973 */
6974 x86_cpu_hyperv_realize(cpu);
6975
b8d834a0 6976 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6977 if (local_err) {
6978 goto out;
6979 }
6980
f06d8a18
YW		 6981 /*
6982 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
6983 * with user-provided setting.
6984 */
6985 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) {
6986 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) {
6987 error_setg(errp, "invalid lbr-fmt");
6988 return;
6989 }
6990 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT;
6991 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt;
6992 }
6993
6994 /*
6995 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
6996 * 3)vPMU LBR format matches that of host setting.
6997 */
6998 requested_lbr_fmt =
6999 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT;
7000 if (requested_lbr_fmt && kvm_enabled()) {
7001 uint64_t host_perf_cap =
7002 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false);
7003 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT;
7004
7005 if (!cpu->enable_pmu) {
7006 error_setg(errp, "vPMU: LBR is unsupported without pmu=on");
7007 return;
7008 }
7009 if (requested_lbr_fmt != host_lbr_fmt) {
7010 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match "
7011 "the host value (0x%x).",
7012 requested_lbr_fmt, host_lbr_fmt);
7013 return;
7014 }
7015 }
7016
245edd0c
PB		 7017 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
7018
7019 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
7020 error_setg(&local_err,
7021 accel_uses_host_cpuid() ?
7022 "Host doesn't support requested features" :
7023 "TCG doesn't support requested features");
7024 goto out;
9997cf7b
EH		 7025 }
7026
9b15cd9e
IM		 7027 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
7028 * CPUID[1].EDX.
7029 */
e48638fd 7030 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 7031 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
7032 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 7033 & CPUID_EXT2_AMD_ALIASES);
7034 }
7035
db888065
SC		 7036 x86_cpu_set_sgxlepubkeyhash(env);
7037
662175b9
CF		 7038 /*
7039 * note: the call to the framework needs to happen after feature expansion,
7040 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
7041 * These may be set by the accel-specific code,
7042 * and the results are subsequently checked / assumed in this function.
7043 */
7044 cpu_exec_realizefn(cs, &local_err);
7045 if (local_err != NULL) {
7046 error_propagate(errp, local_err);
7047 return;
7048 }
7049
7050 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
7051 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
7052 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
7053 goto out;
7054 }
7055
7056 if (cpu->ucode_rev == 0) {
7057 /*
7058 * The default is the same as KVM's. Note that this check
7059 * needs to happen after the evenual setting of ucode_rev in
7060 * accel-specific code in cpu_exec_realizefn.
7061 */
7062 if (IS_AMD_CPU(env)) {
7063 cpu->ucode_rev = 0x01000065;
7064 } else {
7065 cpu->ucode_rev = 0x100000000ULL;
7066 }
7067 }
7068
7069 /*
7070 * mwait extended info: needed for Core compatibility
7071 * We always wake on interrupt even if host does not have the capability.
7072 *
7073 * requires the accel-specific code in cpu_exec_realizefn to
7074 * have already acquired the CPUID data into cpu->mwait.
7075 */
7076 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
7077
11f6fee5
DDAG		 7078 /* For 64bit systems think about the number of physical bits to present.
7079 * ideally this should be the same as the host; anything other than matching
7080 * the host can cause incorrect guest behaviour.
7081 * QEMU used to pick the magic value of 40 bits that corresponds to
7082 * consumer AMD devices but nothing else.
662175b9
CF		 7083 *
7084 * Note that this code assumes features expansion has already been done
7085 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
7086 * phys_bits adjustments to match the host have been already done in
7087 * accel-specific code in cpu_exec_realizefn.
11f6fee5 7088 */
af45907a 7089 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 7090 if (cpu->phys_bits &&
7091 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
7092 cpu->phys_bits < 32)) {
7093 error_setg(errp, "phys-bits should be between 32 and %u "
7094 " (but is %u)",
7095 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
7096 return;
af45907a 7097 }
f5cc5a5c
CF		 7098 /*
7099 * 0 means it was not explicitly set by the user (or by machine
7100 * compat_props or by the host code in host-cpu.c).
7101 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 7102 */
7103 if (cpu->phys_bits == 0) {
7104 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
7105 }
af45907a
DDAG		 7106 } else {
7107 /* For 32 bit systems don't use the user set value, but keep
7108 * phys_bits consistent with what we tell the guest.
7109 */
7110 if (cpu->phys_bits != 0) {
7111 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
7112 return;
7113 }
fefb41bf 7114
af45907a
DDAG		 7115 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
7116 cpu->phys_bits = 36;
7117 } else {
7118 cpu->phys_bits = 32;
7119 }
7120 }
a9f27ea9
EH		 7121
7122 /* Cache information initialization */
7123 if (!cpu->legacy_cache) {
cca0a000
MR		 7124 const CPUCaches *cache_info =
7125 x86_cpu_get_versioned_cache_info(cpu, xcc->model);
7126
7127 if (!xcc->model || !cache_info) {
88703ce2 7128 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 7129 error_setg(errp,
7130 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 7131 return;
7132 }
7133 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
cca0a000 7134 *cache_info;
a9f27ea9
EH		 7135 } else {
7136 /* Build legacy cache information */
7137 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
7138 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
7139 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
7140 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
7141
7142 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
7143 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
7144 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
7145 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
7146
7147 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
7148 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
7149 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
7150 env->cache_info_amd.l3_cache = &legacy_l3_cache;
7151 }
7152
65dee380 7153#ifndef CONFIG_USER_ONLY
0e11fc69 7154 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 7155 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 7156
0e11fc69 7157 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 7158 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 7159 if (local_err != NULL) {
4dc1f449 7160 goto out;
bdeec802
IM		 7161 }
7162 }
65dee380
IM		 7163#endif
7164
7a059953 7165 mce_init(cpu);
2001d0cd 7166
14a10fc3 7167 qemu_init_vcpu(cs);
d3c64d6a 7168
6b2942f9
BM		 7169 /*
7170 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
7171 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
7172 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 7173 * users a warning.
7174 *
7175 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
7176 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
7177 */
0765691e
MA		 7178 if (IS_AMD_CPU(env) &&
7179 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
7180 cs->nr_threads > 1 && !ht_warned) {
7181 warn_report("This family of AMD CPU doesn't support "
7182 "hyperthreading(%d)",
7183 cs->nr_threads);
7184 error_printf("Please configure -smp options properly"
7185 " or try enabling topoext feature.\n");
7186 ht_warned = true;
e48638fd
WH		 7187 }
7188
79f1a68a 7189#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 7190 x86_cpu_apic_realize(cpu, &local_err);
7191 if (local_err != NULL) {
7192 goto out;
7193 }
79f1a68a 7194#endif /* !CONFIG_USER_ONLY */
14a10fc3 7195 cpu_reset(cs);
2b6f294c 7196
4dc1f449 7197 xcc->parent_realize(dev, &local_err);
2001d0cd 7198
4dc1f449
IM		 7199out:
7200 if (local_err != NULL) {
7201 error_propagate(errp, local_err);
7202 return;
7203 }
7a059953
AF		 7204}
7205
b69c3c21 7206static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 7207{
7208 X86CPU *cpu = X86_CPU(dev);
7bbc124e 7209 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 7210
7211#ifndef CONFIG_USER_ONLY
7212 cpu_remove_sync(CPU(dev));
7213 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
7214#endif
7215
7216 if (cpu->apic_state) {
7217 object_unparent(OBJECT(cpu->apic_state));
7218 cpu->apic_state = NULL;
7219 }
7bbc124e 7220
b69c3c21 7221 xcc->parent_unrealize(dev);
c884776e
IM		 7222}
7223
38e5c119 7224typedef struct BitProperty {
a7b0ffac 7225 FeatureWord w;
ede146c2 7226 uint64_t mask;
38e5c119
EH		 7227} BitProperty;
7228
d7bce999
EB		 7229static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
7230 void *opaque, Error **errp)
38e5c119 7231{
a7b0ffac 7232 X86CPU *cpu = X86_CPU(obj);
38e5c119 7233 BitProperty *fp = opaque;
ede146c2 7234 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 7235 bool value = (f & fp->mask) == fp->mask;
51e72bc1 7236 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 7237}
7238
d7bce999
EB		 7239static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
7240 void *opaque, Error **errp)
38e5c119
EH		 7241{
7242 DeviceState *dev = DEVICE(obj);
a7b0ffac 7243 X86CPU *cpu = X86_CPU(obj);
38e5c119 7244 BitProperty *fp = opaque;
38e5c119
EH		 7245 bool value;
7246
7247 if (dev->realized) {
7248 qdev_prop_set_after_realize(dev, name, errp);
7249 return;
7250 }
7251
668f62ec 7252 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 7253 return;
7254 }
7255
7256 if (value) {
a7b0ffac 7257 cpu->env.features[fp->w] |= fp->mask;
38e5c119 7258 } else {
a7b0ffac 7259 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 7260 }
d4a606b3 7261 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 7262}
7263
38e5c119
EH		 7264/* Register a boolean property to get/set a single bit in a uint32_t field.
7265 *
7266 * The same property name can be registered multiple times to make it affect
7267 * multiple bits in the same FeatureWord. In that case, the getter will return
7268 * true only if all bits are set.
7269 */
f5730c69 7270static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 7271 const char *prop_name,
a7b0ffac 7272 FeatureWord w,
38e5c119
EH		 7273 int bitnr)
7274{
f5730c69 7275 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 7276 BitProperty *fp;
7277 ObjectProperty *op;
ede146c2 7278 uint64_t mask = (1ULL << bitnr);
38e5c119 7279
f5730c69 7280 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 7281 if (op) {
7282 fp = op->opaque;
a7b0ffac 7283 assert(fp->w == w);
38e5c119
EH		 7284 fp->mask |= mask;
7285 } else {
7286 fp = g_new0(BitProperty, 1);
a7b0ffac 7287 fp->w = w;
38e5c119 7288 fp->mask = mask;
f5730c69
EH		 7289 object_class_property_add(oc, prop_name, "bool",
7290 x86_cpu_get_bit_prop,
7291 x86_cpu_set_bit_prop,
7292 NULL, fp);
38e5c119
EH		 7293 }
7294}
7295
f5730c69 7296static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 7297 FeatureWord w,
7298 int bitnr)
7299{
38e5c119 7300 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 7301 const char *name = fi->feat_names[bitnr];
38e5c119 7302
16d2fcaa 7303 if (!name) {
38e5c119
EH		 7304 return;
7305 }
7306
fc7dfd20
EH		 7307 /* Property names should use "-" instead of "_".
7308 * Old names containing underscores are registered as aliases
7309 * using object_property_add_alias()
7310 */
16d2fcaa
EH		 7311 assert(!strchr(name, '_'));
7312 /* aliases don't use "|" delimiters anymore, they are registered
7313 * manually using object_property_add_alias() */
7314 assert(!strchr(name, '|'));
f5730c69 7315 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 7316}
7317
4db4385a
CF		 7318static void x86_cpu_post_initfn(Object *obj)
7319{
7320 accel_cpu_instance_init(CPU(obj));
7321}
7322
de024815
AF		 7323static void x86_cpu_initfn(Object *obj)
7324{
7325 X86CPU *cpu = X86_CPU(obj);
d940ee9b 7326 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 7327 CPUX86State *env = &cpu->env;
7328
c26ae610 7329 env->nr_dies = 1;
7506ed90 7330 cpu_set_cpustate_pointers(cpu);
71ad61d3 7331
8e8aba50
EH		 7332 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
7333 x86_cpu_get_feature_words,
d2623129 7334 NULL, NULL, (void *)env->features);
7e5292b5
EH		 7335 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
7336 x86_cpu_get_feature_words,
d2623129 7337 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 7338
d2623129
MA		 7339 object_property_add_alias(obj, "sse3", obj, "pni");
7340 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
7341 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
7342 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
7343 object_property_add_alias(obj, "xd", obj, "nx");
7344 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
7345 object_property_add_alias(obj, "i64", obj, "lm");
7346
7347 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
7348 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
7349 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
7350 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
7351 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
7352 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
7353 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
7354 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
7355 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
7356 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
7357 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 7358 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 7359 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
7360 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
7361 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
7362 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
7363 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
7364 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
7365 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
7366 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
7367 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7368 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7369 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 7370
e1f9a8e8 7371 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
f06d8a18
YW		 7372 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;
7373 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt");
e1f9a8e8 7374
dcafd1ef 7375 if (xcc->model) {
49e2fa85 7376 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 7377 }
de024815
AF		 7378}
7379
997395d3
IM		 7380static int64_t x86_cpu_get_arch_id(CPUState *cs)
7381{
7382 X86CPU *cpu = X86_CPU(cs);
997395d3 7383
7e72a45c 7384 return cpu->apic_id;
997395d3
IM		 7385}
7386
6bc0d6a0 7387#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 7388static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7389{
7390 X86CPU *cpu = X86_CPU(cs);
7391
7392 return cpu->env.cr[0] & CR0_PG_MASK;
7393}
6bc0d6a0 7394#endif /* !CONFIG_USER_ONLY */
444d5590 7395
f45748f1
AF		 7396static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7397{
7398 X86CPU *cpu = X86_CPU(cs);
7399
7400 cpu->env.eip = value;
7401}
7402
e4fdf9df
RH		 7403static vaddr x86_cpu_get_pc(CPUState *cs)
7404{
7405 X86CPU *cpu = X86_CPU(cs);
7406
7407 /* Match cpu_get_tb_cpu_state. */
7408 return cpu->env.eip + cpu->env.segs[R_CS].base;
7409}
7410
92d5f1a4 7411int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 7412{
7413 X86CPU *cpu = X86_CPU(cs);
7414 CPUX86State *env = &cpu->env;
7415
92d5f1a4
PB		 7416#if !defined(CONFIG_USER_ONLY)
7417 if (interrupt_request & CPU_INTERRUPT_POLL) {
7418 return CPU_INTERRUPT_POLL;
7419 }
7420#endif
7421 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7422 return CPU_INTERRUPT_SIPI;
7423 }
7424
7425 if (env->hflags2 & HF2_GIF_MASK) {
7426 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7427 !(env->hflags & HF_SMM_MASK)) {
7428 return CPU_INTERRUPT_SMI;
7429 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7430 !(env->hflags2 & HF2_NMI_MASK)) {
7431 return CPU_INTERRUPT_NMI;
7432 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7433 return CPU_INTERRUPT_MCE;
7434 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7435 (((env->hflags2 & HF2_VINTR_MASK) &&
7436 (env->hflags2 & HF2_HIF_MASK)) ||
7437 (!(env->hflags2 & HF2_VINTR_MASK) &&
7438 (env->eflags & IF_MASK &&
7439 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7440 return CPU_INTERRUPT_HARD;
7441#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 7442 } else if (env->hflags2 & HF2_VGIF_MASK) {
7443 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 7444 (env->eflags & IF_MASK) &&
7445 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 7446 return CPU_INTERRUPT_VIRQ;
7447 }
92d5f1a4
PB		 7448#endif
7449 }
7450 }
7451
7452 return 0;
7453}
7454
7455static bool x86_cpu_has_work(CPUState *cs)
7456{
7457 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 7458}
7459
f50f3dd5
RH		 7460static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7461{
7462 X86CPU *cpu = X86_CPU(cs);
7463 CPUX86State *env = &cpu->env;
7464
7465 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7466 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7467 : bfd_mach_i386_i8086);
b666d2a4
RH		 7468
7469 info->cap_arch = CS_ARCH_X86;
7470 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7471 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7472 : CS_MODE_16);
15fa1a0a
RH		 7473 info->cap_insn_unit = 1;
7474 info->cap_insn_split = 8;
f50f3dd5
RH		 7475}
7476
35b1b927
TW		 7477void x86_update_hflags(CPUX86State *env)
7478{
7479 uint32_t hflags;
7480#define HFLAG_COPY_MASK \
7481 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7482 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7483 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7484 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7485
7486 hflags = env->hflags & HFLAG_COPY_MASK;
7487 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7488 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7489 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7490 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7491 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7492
7493 if (env->cr[4] & CR4_OSFXSR_MASK) {
7494 hflags |= HF_OSFXSR_MASK;
7495 }
7496
7497 if (env->efer & MSR_EFER_LMA) {
7498 hflags |= HF_LMA_MASK;
7499 }
7500
7501 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7502 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7503 } else {
7504 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7505 (DESC_B_SHIFT - HF_CS32_SHIFT);
7506 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7507 (DESC_B_SHIFT - HF_SS32_SHIFT);
7508 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7509 !(hflags & HF_CS32_MASK)) {
7510 hflags |= HF_ADDSEG_MASK;
7511 } else {
7512 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7513 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7514 }
7515 }
7516 env->hflags = hflags;
7517}
7518
9337e3b6 7519static Property x86_cpu_properties[] = {
2da00e31
IM		 7520#ifdef CONFIG_USER_ONLY
7521 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7522 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 7523 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7524 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 7525 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 7526 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 7527#else
7528 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 7529 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7530 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 7531 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 7532 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 7533#endif
15f8b142 7534 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 7535 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
f06d8a18 7536 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
2d384d7c 7537
915aee93 7538 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 7539 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 7540 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7541 HYPERV_FEAT_RELAXED, 0),
7542 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7543 HYPERV_FEAT_VAPIC, 0),
7544 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7545 HYPERV_FEAT_TIME, 0),
7546 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7547 HYPERV_FEAT_CRASH, 0),
7548 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7549 HYPERV_FEAT_RESET, 0),
7550 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7551 HYPERV_FEAT_VPINDEX, 0),
7552 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7553 HYPERV_FEAT_RUNTIME, 0),
7554 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7555 HYPERV_FEAT_SYNIC, 0),
7556 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7557 HYPERV_FEAT_STIMER, 0),
7558 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7559 HYPERV_FEAT_FREQUENCIES, 0),
7560 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7561 HYPERV_FEAT_REENLIGHTENMENT, 0),
7562 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7563 HYPERV_FEAT_TLBFLUSH, 0),
7564 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7565 HYPERV_FEAT_EVMCS, 0),
7566 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7567 HYPERV_FEAT_IPI, 0),
128531d9
VK		 7568 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7569 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 7570 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
7571 HYPERV_FEAT_AVIC, 0),
869840d2
VK		 7572 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
7573 HYPERV_FEAT_MSR_BITMAP, 0),
9411e8b6
VK		 7574 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
7575 HYPERV_FEAT_XMM_INPUT, 0),
aa6bb5fa
VK		 7576 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
7577 HYPERV_FEAT_TLBFLUSH_EXT, 0),
3aae0854
VK		 7578 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
7579 HYPERV_FEAT_TLBFLUSH_DIRECT, 0),
30d6ff66
VK		 7580 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7581 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
73d24074
JD		 7582 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
7583 HYPERV_FEAT_SYNDBG, 0),
e48ddcc6 7584 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 7585 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 7586
af7228b8
VK		 7587 /* WS2008R2 identify by default */
7588 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 7589 0x3839),
af7228b8 7590 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 7591 0x000A),
af7228b8 7592 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 7593 0x0000),
af7228b8
VK		 7594 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
7595 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
7596 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
7597
15e41345 7598 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 7599 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 7600 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 7601 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 7602 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 7603 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 7604 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 7605 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 7606 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7607 UINT32_MAX),
c39c0edf
EH		 7608 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7609 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7610 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7611 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7612 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7613 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 7614 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 7615 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 7616 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 7617 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 7618 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 7619 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 7620 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 7621 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7622 false),
988f7b8b
VK		 7623 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
7624 false),
0b564e6f 7625 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 7626 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 7627 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7628 true),
ab8f992e 7629 /*
a9f27ea9
EH		 7630 * lecacy_cache defaults to true unless the CPU model provides its
7631 * own cache information (see x86_cpu_load_def()).
ab8f992e 7632 */
a9f27ea9 7633 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
f66b8a83 7634 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
6c69dfb6
GA		 7635
7636 /*
7637 * From "Requirements for Implementing the Microsoft
7638 * Hypervisor Interface":
7639 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7640 *
7641 * "Starting with Windows Server 2012 and Windows 8, if
7642 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7643 * the hypervisor imposes no specific limit to the number of VPs.
7644 * In this case, Windows Server 2012 guest VMs may use more than
7645 * 64 VPs, up to the maximum supported number of processors applicable
7646 * to the specific Windows version being used."
7647 */
7648 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 7649 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7650 false),
f24c3a79
LK		 7651 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7652 true),
9337e3b6
EH		 7653 DEFINE_PROP_END_OF_LIST()
7654};
7655
8b80bd28
PMD		 7656#ifndef CONFIG_USER_ONLY
7657#include "hw/core/sysemu-cpu-ops.h"
7658
7659static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 7660 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 7661 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 7662 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 7663 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 7664 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 7665 .write_elf32_note = x86_cpu_write_elf32_note,
7666 .write_elf64_note = x86_cpu_write_elf64_note,
7667 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
7668 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 7669 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 7670};
7671#endif
7672
5fd2087a
AF		 7673static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7674{
7675 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7676 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 7677 DeviceClass *dc = DEVICE_CLASS(oc);
e86787d3 7678 ResettableClass *rc = RESETTABLE_CLASS(oc);
f5730c69 7679 FeatureWord w;
2b6f294c 7680
bf853881
PMD		 7681 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7682 &xcc->parent_realize);
7683 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7684 &xcc->parent_unrealize);
4f67d30b 7685 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 7686
e86787d3
PM		 7687 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL,
7688 &xcc->parent_phases);
91b1df8c 7689 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 7690
500050d1 7691 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 7692 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 7693 cc->has_work = x86_cpu_has_work;
878096ee 7694 cc->dump_state = x86_cpu_dump_state;
f45748f1 7695 cc->set_pc = x86_cpu_set_pc;
e4fdf9df 7696 cc->get_pc = x86_cpu_get_pc;
5b50e790
AF		 7697 cc->gdb_read_register = x86_cpu_gdb_read_register;
7698 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 7699 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 7700
5d004421 7701#ifndef CONFIG_USER_ONLY
8b80bd28 7702 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 7703#endif /* !CONFIG_USER_ONLY */
7704
00fcd100
AB		 7705 cc->gdb_arch_name = x86_gdb_arch_name;
7706#ifdef TARGET_X86_64
b8158192 7707 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 7708 cc->gdb_num_core_regs = 66;
00fcd100 7709#else
b8158192 7710 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 7711 cc->gdb_num_core_regs = 50;
74d7fc7f 7712#endif
f50f3dd5 7713 cc->disas_set_info = x86_disas_set_info;
4c315c27 7714
e90f2a8c 7715 dc->user_creatable = true;
3e0dceaf
EH		 7716
7717 object_class_property_add(oc, "family", "int",
7718 x86_cpuid_version_get_family,
7719 x86_cpuid_version_set_family, NULL, NULL);
7720 object_class_property_add(oc, "model", "int",
7721 x86_cpuid_version_get_model,
7722 x86_cpuid_version_set_model, NULL, NULL);
7723 object_class_property_add(oc, "stepping", "int",
7724 x86_cpuid_version_get_stepping,
7725 x86_cpuid_version_set_stepping, NULL, NULL);
7726 object_class_property_add_str(oc, "vendor",
7727 x86_cpuid_get_vendor,
7728 x86_cpuid_set_vendor);
7729 object_class_property_add_str(oc, "model-id",
7730 x86_cpuid_get_model_id,
7731 x86_cpuid_set_model_id);
7732 object_class_property_add(oc, "tsc-frequency", "int",
7733 x86_cpuid_get_tsc_freq,
7734 x86_cpuid_set_tsc_freq, NULL, NULL);
7735 /*
7736 * The "unavailable-features" property has the same semantics as
7737 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7738 * QMP command: they list the features that would have prevented the
7739 * CPU from running if the "enforce" flag was set.
7740 */
7741 object_class_property_add(oc, "unavailable-features", "strList",
7742 x86_cpu_get_unavailable_features,
7743 NULL, NULL, NULL);
7744
7745#if !defined(CONFIG_USER_ONLY)
7746 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7747 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7748#endif
7749
f5730c69
EH		 7750 for (w = 0; w < FEATURE_WORDS; w++) {
7751 int bitnr;
7752 for (bitnr = 0; bitnr < 64; bitnr++) {
7753 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
7754 }
7755 }
5fd2087a
AF		 7756}
7757
7758static const TypeInfo x86_cpu_type_info = {
7759 .name = TYPE_X86_CPU,
7760 .parent = TYPE_CPU,
7761 .instance_size = sizeof(X86CPU),
de024815 7762 .instance_init = x86_cpu_initfn,
4db4385a
CF		 7763 .instance_post_init = x86_cpu_post_initfn,
7764
d940ee9b 7765 .abstract = true,
5fd2087a
AF		 7766 .class_size = sizeof(X86CPUClass),
7767 .class_init = x86_cpu_common_class_init,
7768};
7769
5adbed30
EH		 7770/* "base" CPU model, used by query-cpu-model-expansion */
7771static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7772{
7773 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7774
7775 xcc->static_model = true;
7776 xcc->migration_safe = true;
7777 xcc->model_description = "base CPU model type with no features enabled";
7778 xcc->ordering = 8;
7779}
7780
7781static const TypeInfo x86_base_cpu_type_info = {
7782 .name = X86_CPU_TYPE_NAME("base"),
7783 .parent = TYPE_X86_CPU,
7784 .class_init = x86_cpu_base_class_init,
7785};
7786
5fd2087a
AF		 7787static void x86_cpu_register_types(void)
7788{
d940ee9b
EH		 7789 int i;
7790
5fd2087a 7791 type_register_static(&x86_cpu_type_info);
d940ee9b 7792 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7793 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7794 }
c62f2630 7795 type_register_static(&max_x86_cpu_type_info);
5adbed30 7796 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 7797}
7798
7799type_init(x86_cpu_register_types)
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