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Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into...
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
c6dc6f63 24#include "cpu.h"
ed69e831 25#include "tcg/helper-tcg.h"
71e8a915 26#include "sysemu/reset.h"
d6dcc558 27#include "sysemu/hvf.h"
a9dc68d9 28#include "kvm/kvm_i386.h"
93777de3 29#include "sev.h"
f83aeeae 30#include "qapi/error.h"
8ac25c84 31#include "qapi/qapi-visit-machine.h"
7b1b5d19 32#include "qapi/qmp/qerror.h"
7f7b4e7a 33#include "qapi/qapi-commands-machine-target.h"
1814eab6 34#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 35#include "hw/qdev-properties.h"
5232d00a 36#include "hw/i386/topology.h"
bdeec802 37#ifndef CONFIG_USER_ONLY
2001d0cd 38#include "exec/address-spaces.h"
0e11fc69 39#include "hw/boards.h"
1dec2e1f 40#include "hw/i386/sgx-epc.h"
bdeec802
IM		 41#endif
42
b666d2a4 43#include "disas/capstone.h"
79f1a68a 44#include "cpu-internal.h"
b666d2a4 45
7e3482f8
EH		 46/* Helpers for building CPUID[2] descriptors: */
47
48struct CPUID2CacheDescriptorInfo {
49 enum CacheType type;
50 int level;
51 int size;
52 int line_size;
53 int associativity;
54};
5e891bf8 55
7e3482f8
EH		 56/*
57 * Known CPUID 2 cache descriptors.
58 * From Intel SDM Volume 2A, CPUID instruction
59 */
60struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 61 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 62 .associativity = 4, .line_size = 32, },
5f00335a 63 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 64 .associativity = 4, .line_size = 32, },
5f00335a 65 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 66 .associativity = 4, .line_size = 64, },
5f00335a 67 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 68 .associativity = 2, .line_size = 32, },
5f00335a 69 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 70 .associativity = 4, .line_size = 32, },
5f00335a 71 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 72 .associativity = 4, .line_size = 64, },
5f00335a 73 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 74 .associativity = 6, .line_size = 64, },
5f00335a 75 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 76 .associativity = 2, .line_size = 64, },
5f00335a 77 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 78 .associativity = 8, .line_size = 64, },
79 /* lines per sector is not supported cpuid2_cache_descriptor(),
80 * so descriptors 0x22, 0x23 are not included
81 */
5f00335a 82 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 83 .associativity = 16, .line_size = 64, },
84 /* lines per sector is not supported cpuid2_cache_descriptor(),
85 * so descriptors 0x25, 0x20 are not included
86 */
5f00335a 87 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 88 .associativity = 8, .line_size = 64, },
5f00335a 89 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 90 .associativity = 8, .line_size = 64, },
5f00335a 91 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 92 .associativity = 4, .line_size = 32, },
5f00335a 93 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 94 .associativity = 4, .line_size = 32, },
5f00335a 95 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 96 .associativity = 4, .line_size = 32, },
5f00335a 97 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 98 .associativity = 4, .line_size = 32, },
5f00335a 99 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 100 .associativity = 4, .line_size = 32, },
5f00335a 101 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 102 .associativity = 4, .line_size = 64, },
5f00335a 103 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 104 .associativity = 8, .line_size = 64, },
5f00335a 105 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 106 .associativity = 12, .line_size = 64, },
107 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 108 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 109 .associativity = 12, .line_size = 64, },
5f00335a 110 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 111 .associativity = 16, .line_size = 64, },
5f00335a 112 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 113 .associativity = 12, .line_size = 64, },
5f00335a 114 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 115 .associativity = 16, .line_size = 64, },
5f00335a 116 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 117 .associativity = 24, .line_size = 64, },
5f00335a 118 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 119 .associativity = 8, .line_size = 64, },
5f00335a 120 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 121 .associativity = 4, .line_size = 64, },
5f00335a 122 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 123 .associativity = 4, .line_size = 64, },
5f00335a 124 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 125 .associativity = 4, .line_size = 64, },
5f00335a 126 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 127 .associativity = 4, .line_size = 64, },
128 /* lines per sector is not supported cpuid2_cache_descriptor(),
129 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
130 */
5f00335a 131 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 132 .associativity = 8, .line_size = 64, },
5f00335a 133 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 134 .associativity = 2, .line_size = 64, },
5f00335a 135 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 136 .associativity = 8, .line_size = 64, },
5f00335a 137 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 138 .associativity = 8, .line_size = 32, },
5f00335a 139 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 140 .associativity = 8, .line_size = 32, },
5f00335a 141 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 142 .associativity = 8, .line_size = 32, },
5f00335a 143 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 144 .associativity = 8, .line_size = 32, },
5f00335a 145 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 146 .associativity = 4, .line_size = 64, },
5f00335a 147 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 148 .associativity = 8, .line_size = 64, },
5f00335a 149 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 150 .associativity = 4, .line_size = 64, },
5f00335a 151 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 152 .associativity = 4, .line_size = 64, },
5f00335a 153 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 154 .associativity = 4, .line_size = 64, },
5f00335a 155 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 156 .associativity = 8, .line_size = 64, },
5f00335a 157 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 158 .associativity = 8, .line_size = 64, },
5f00335a 159 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 160 .associativity = 8, .line_size = 64, },
5f00335a 161 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 162 .associativity = 12, .line_size = 64, },
5f00335a 163 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 164 .associativity = 12, .line_size = 64, },
5f00335a 165 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 166 .associativity = 12, .line_size = 64, },
5f00335a 167 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 168 .associativity = 16, .line_size = 64, },
5f00335a 169 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 170 .associativity = 16, .line_size = 64, },
5f00335a 171 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 172 .associativity = 16, .line_size = 64, },
5f00335a 173 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 174 .associativity = 24, .line_size = 64, },
5f00335a 175 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 176 .associativity = 24, .line_size = 64, },
5f00335a 177 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 178 .associativity = 24, .line_size = 64, },
179};
180
181/*
182 * "CPUID leaf 2 does not report cache descriptor information,
183 * use CPUID leaf 4 to query cache parameters"
184 */
185#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 186
7e3482f8
EH		 187/*
188 * Return a CPUID 2 cache descriptor for a given cache.
189 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
190 */
191static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
192{
193 int i;
194
195 assert(cache->size > 0);
196 assert(cache->level > 0);
197 assert(cache->line_size > 0);
198 assert(cache->associativity > 0);
199 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
200 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
201 if (d->level == cache->level && d->type == cache->type &&
202 d->size == cache->size && d->line_size == cache->line_size &&
203 d->associativity == cache->associativity) {
204 return i;
205 }
206 }
5e891bf8 207
7e3482f8
EH		 208 return CACHE_DESCRIPTOR_UNAVAILABLE;
209}
5e891bf8
EH		 210
211/* CPUID Leaf 4 constants: */
212
213/* EAX: */
7e3482f8
EH		 214#define CACHE_TYPE_D 1
215#define CACHE_TYPE_I 2
216#define CACHE_TYPE_UNIFIED 3
5e891bf8 217
7e3482f8 218#define CACHE_LEVEL(l) (l << 5)
5e891bf8 219
7e3482f8 220#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 221
222/* EDX: */
7e3482f8
EH		 223#define CACHE_NO_INVD_SHARING (1 << 0)
224#define CACHE_INCLUSIVE (1 << 1)
225#define CACHE_COMPLEX_IDX (1 << 2)
226
227/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 228#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
229 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
230 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
231 0 /* Invalid value */)
7e3482f8
EH		 232
233
234/* Encode cache info for CPUID[4] */
235static void encode_cache_cpuid4(CPUCacheInfo *cache,
236 int num_apic_ids, int num_cores,
237 uint32_t *eax, uint32_t *ebx,
238 uint32_t *ecx, uint32_t *edx)
239{
240 assert(cache->size == cache->line_size * cache->associativity *
241 cache->partitions * cache->sets);
242
243 assert(num_apic_ids > 0);
244 *eax = CACHE_TYPE(cache->type) |
245 CACHE_LEVEL(cache->level) |
246 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
247 ((num_cores - 1) << 26) |
248 ((num_apic_ids - 1) << 14);
249
250 assert(cache->line_size > 0);
251 assert(cache->partitions > 0);
252 assert(cache->associativity > 0);
253 /* We don't implement fully-associative caches */
254 assert(cache->associativity < cache->sets);
255 *ebx = (cache->line_size - 1) |
256 ((cache->partitions - 1) << 12) |
257 ((cache->associativity - 1) << 22);
258
259 assert(cache->sets > 0);
260 *ecx = cache->sets - 1;
261
262 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
263 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
264 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
265}
266
267/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
268static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
269{
270 assert(cache->size % 1024 == 0);
271 assert(cache->lines_per_tag > 0);
272 assert(cache->associativity > 0);
273 assert(cache->line_size > 0);
274 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
275 (cache->lines_per_tag << 8) | (cache->line_size);
276}
5e891bf8
EH		 277
278#define ASSOC_FULL 0xFF
279
280/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
281#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
282 a == 2 ? 0x2 : \
283 a == 4 ? 0x4 : \
284 a == 8 ? 0x6 : \
285 a == 16 ? 0x8 : \
286 a == 32 ? 0xA : \
287 a == 48 ? 0xB : \
288 a == 64 ? 0xC : \
289 a == 96 ? 0xD : \
290 a == 128 ? 0xE : \
291 a == ASSOC_FULL ? 0xF : \
292 0 /* invalid value */)
293
7e3482f8
EH		 294/*
295 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
296 * @l3 can be NULL.
297 */
298static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
299 CPUCacheInfo *l3,
300 uint32_t *ecx, uint32_t *edx)
301{
302 assert(l2->size % 1024 == 0);
303 assert(l2->associativity > 0);
304 assert(l2->lines_per_tag > 0);
305 assert(l2->line_size > 0);
306 *ecx = ((l2->size / 1024) << 16) |
307 (AMD_ENC_ASSOC(l2->associativity) << 12) |
308 (l2->lines_per_tag << 8) | (l2->line_size);
309
310 if (l3) {
311 assert(l3->size % (512 * 1024) == 0);
312 assert(l3->associativity > 0);
313 assert(l3->lines_per_tag > 0);
314 assert(l3->line_size > 0);
315 *edx = ((l3->size / (512 * 1024)) << 18) |
316 (AMD_ENC_ASSOC(l3->associativity) << 12) |
317 (l3->lines_per_tag << 8) | (l3->line_size);
318 } else {
319 *edx = 0;
320 }
321}
5e891bf8 322
8f4202fb 323/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 324static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
325 X86CPUTopoInfo *topo_info,
326 uint32_t *eax, uint32_t *ebx,
327 uint32_t *ecx, uint32_t *edx)
8f4202fb 328{
2f084d1e 329 uint32_t l3_threads;
8f4202fb
BM		 330 assert(cache->size == cache->line_size * cache->associativity *
331 cache->partitions * cache->sets);
332
333 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
334 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
335
336 /* L3 is shared among multiple cores */
337 if (cache->level == 3) {
2f084d1e
BM		 338 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
339 *eax |= (l3_threads - 1) << 14;
8f4202fb 340 } else {
2f084d1e 341 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 342 }
343
344 assert(cache->line_size > 0);
345 assert(cache->partitions > 0);
346 assert(cache->associativity > 0);
347 /* We don't implement fully-associative caches */
348 assert(cache->associativity < cache->sets);
349 *ebx = (cache->line_size - 1) |
350 ((cache->partitions - 1) << 12) |
351 ((cache->associativity - 1) << 22);
352
353 assert(cache->sets > 0);
354 *ecx = cache->sets - 1;
355
356 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
357 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
358 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
359}
360
ed78467a 361/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 362static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
363 uint32_t *eax, uint32_t *ebx,
364 uint32_t *ecx, uint32_t *edx)
ed78467a 365{
31ada106
BM		 366 X86CPUTopoIDs topo_ids;
367
368 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 369
ed78467a 370 *eax = cpu->apic_id;
31ada106 371
ed78467a 372 /*
31ada106
BM		 373 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
374 * Read-only. Reset: 0000_XXXXh.
375 * See Core::X86::Cpuid::ExtApicId.
376 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
377 * Bits Description
378 * 31:16 Reserved.
379 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
380 * The number of threads per core is ThreadsPerCore+1.
381 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
382 *
383 * NOTE: CoreId is already part of apic_id. Just use it. We can
384 * use all the 8 bits to represent the core_id here.
ed78467a 385 */
31ada106
BM		 386 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
387
ed78467a 388 /*
31ada106
BM		 389 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
390 * Read-only. Reset: 0000_0XXXh.
391 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
392 * Bits Description
393 * 31:11 Reserved.
394 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
395 * ValidValues:
396 * Value Description
397 * 000b 1 node per processor.
398 * 001b 2 nodes per processor.
399 * 010b Reserved.
400 * 011b 4 nodes per processor.
401 * 111b-100b Reserved.
402 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
403 *
404 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
405 * But users can create more nodes than the actual hardware can
406 * support. To genaralize we can use all the upper 8 bits for nodes.
407 * NodeId is combination of node and socket_id which is already decoded
408 * in apic_id. Just use it by shifting.
ed78467a 409 */
31ada106
BM		 410 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
411 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
412
ed78467a
BM		 413 *edx = 0;
414}
415
ab8f992e
BM		 416/*
417 * Definitions of the hardcoded cache entries we expose:
418 * These are legacy cache values. If there is a need to change any
419 * of these values please use builtin_x86_defs
420 */
5e891bf8
EH		 421
422/* L1 data cache: */
ab8f992e 423static CPUCacheInfo legacy_l1d_cache = {
5f00335a 424 .type = DATA_CACHE,
7e3482f8
EH		 425 .level = 1,
426 .size = 32 * KiB,
427 .self_init = 1,
428 .line_size = 64,
429 .associativity = 8,
430 .sets = 64,
431 .partitions = 1,
432 .no_invd_sharing = true,
433};
434
5e891bf8 435/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 436static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 437 .type = DATA_CACHE,
7e3482f8
EH		 438 .level = 1,
439 .size = 64 * KiB,
440 .self_init = 1,
441 .line_size = 64,
442 .associativity = 2,
443 .sets = 512,
444 .partitions = 1,
445 .lines_per_tag = 1,
446 .no_invd_sharing = true,
447};
5e891bf8
EH		 448
449/* L1 instruction cache: */
ab8f992e 450static CPUCacheInfo legacy_l1i_cache = {
5f00335a 451 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 452 .level = 1,
453 .size = 32 * KiB,
454 .self_init = 1,
455 .line_size = 64,
456 .associativity = 8,
457 .sets = 64,
458 .partitions = 1,
459 .no_invd_sharing = true,
460};
461
5e891bf8 462/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 463static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 464 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 465 .level = 1,
466 .size = 64 * KiB,
467 .self_init = 1,
468 .line_size = 64,
469 .associativity = 2,
470 .sets = 512,
471 .partitions = 1,
472 .lines_per_tag = 1,
473 .no_invd_sharing = true,
474};
5e891bf8
EH		 475
476/* Level 2 unified cache: */
ab8f992e 477static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 478 .type = UNIFIED_CACHE,
479 .level = 2,
480 .size = 4 * MiB,
481 .self_init = 1,
482 .line_size = 64,
483 .associativity = 16,
484 .sets = 4096,
485 .partitions = 1,
486 .no_invd_sharing = true,
487};
488
5e891bf8 489/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 490static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 491 .type = UNIFIED_CACHE,
492 .level = 2,
493 .size = 2 * MiB,
494 .line_size = 64,
495 .associativity = 8,
496};
497
498
5e891bf8 499/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 500static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 501 .type = UNIFIED_CACHE,
502 .level = 2,
503 .size = 512 * KiB,
504 .line_size = 64,
505 .lines_per_tag = 1,
506 .associativity = 16,
507 .sets = 512,
508 .partitions = 1,
509};
5e891bf8 510
14c985cf 511/* Level 3 unified cache: */
ab8f992e 512static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 513 .type = UNIFIED_CACHE,
514 .level = 3,
515 .size = 16 * MiB,
516 .line_size = 64,
517 .associativity = 16,
518 .sets = 16384,
519 .partitions = 1,
520 .lines_per_tag = 1,
521 .self_init = true,
522 .inclusive = true,
523 .complex_indexing = true,
524};
5e891bf8
EH		 525
526/* TLB definitions: */
527
528#define L1_DTLB_2M_ASSOC 1
529#define L1_DTLB_2M_ENTRIES 255
530#define L1_DTLB_4K_ASSOC 1
531#define L1_DTLB_4K_ENTRIES 255
532
533#define L1_ITLB_2M_ASSOC 1
534#define L1_ITLB_2M_ENTRIES 255
535#define L1_ITLB_4K_ASSOC 1
536#define L1_ITLB_4K_ENTRIES 255
537
538#define L2_DTLB_2M_ASSOC 0 /* disabled */
539#define L2_DTLB_2M_ENTRIES 0 /* disabled */
540#define L2_DTLB_4K_ASSOC 4
541#define L2_DTLB_4K_ENTRIES 512
542
543#define L2_ITLB_2M_ASSOC 0 /* disabled */
544#define L2_ITLB_2M_ENTRIES 0 /* disabled */
545#define L2_ITLB_4K_ASSOC 4
546#define L2_ITLB_4K_ENTRIES 512
547
e37a5c7f
CP		 548/* CPUID Leaf 0x14 constants: */
549#define INTEL_PT_MAX_SUBLEAF 0x1
550/*
551 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
552 * MSR can be accessed;
553 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
554 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
555 * of Intel PT MSRs across warm reset;
556 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
557 */
558#define INTEL_PT_MINIMAL_EBX 0xf
559/*
560 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
561 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
562 * accessed;
563 * bit[01]: ToPA tables can hold any number of output entries, up to the
564 * maximum allowed by the MaskOrTableOffset field of
565 * IA32_RTIT_OUTPUT_MASK_PTRS;
566 * bit[02]: Support Single-Range Output scheme;
567 */
568#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 569/* generated packets which contain IP payloads have LIP values */
570#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 571#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
572#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
573#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
574#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
575#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 576
f5cc5a5c
CF		 577void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
578 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 579{
580 int i;
581 for (i = 0; i < 4; i++) {
582 dst[i] = vendor1 >> (8 * i);
583 dst[i + 4] = vendor2 >> (8 * i);
584 dst[i + 8] = vendor3 >> (8 * i);
585 }
586 dst[CPUID_VENDOR_SZ] = '\0';
587}
588
621626ce
EH		 589#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
590#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
591 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
592#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
593 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
594 CPUID_PSE36 | CPUID_FXSR)
595#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
596#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
597 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
598 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
599 CPUID_PAE | CPUID_SEP | CPUID_APIC)
600
601#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
602 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
603 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
604 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 605 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 606 /* partly implemented:
607 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
608 /* missing:
609 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
610#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
611 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
612 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 613 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 614 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
615 CPUID_EXT_RDRAND)
621626ce
EH		 616 /* missing:
617 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
618 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
619 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 620 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 621 CPUID_EXT_F16C */
621626ce
EH		 622
623#ifdef TARGET_X86_64
624#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
625#else
626#define TCG_EXT2_X86_64_FEATURES 0
627#endif
628
629#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
630 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
631 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
632 TCG_EXT2_X86_64_FEATURES)
633#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
634 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
635#define TCG_EXT4_FEATURES 0
900eeca5
LL		 636#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
637 CPUID_SVM_SVME_ADDR_CHK)
621626ce
EH		 638#define TCG_KVM_FEATURES 0
639#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 640 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
641 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 642 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
643 CPUID_7_0_EBX_ERMS)
621626ce 644 /* missing:
07929f2a 645 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 646 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 647 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 648#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
649 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
e7e7bdab 650 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
95ea69fb 651#define TCG_7_0_EDX_FEATURES 0
80db491d 652#define TCG_7_1_EAX_FEATURES 0
303752a9 653#define TCG_APM_FEATURES 0
28b8e4d0 654#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 655#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
656 /* missing:
657 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 658#define TCG_14_0_ECX_FEATURES 0
4b841a79 659#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 660#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 661#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 662
79f1a68a 663FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 664 [FEAT_1_EDX] = {
07585923 665 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 666 .feat_names = {
667 "fpu", "vme", "de", "pse",
668 "tsc", "msr", "pae", "mce",
669 "cx8", "apic", NULL, "sep",
670 "mtrr", "pge", "mca", "cmov",
671 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
672 NULL, "ds" /* Intel dts */, "acpi", "mmx",
673 "fxsr", "sse", "sse2", "ss",
674 "ht" /* Intel htt */, "tm", "ia64", "pbe",
675 },
07585923 676 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 677 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 678 },
679 [FEAT_1_ECX] = {
07585923 680 .type = CPUID_FEATURE_WORD,
2d5312da 681 .feat_names = {
16d2fcaa 682 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 683 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 684 "tm2", "ssse3", "cid", NULL,
685 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 686 NULL, "pcid", "dca", "sse4.1",
687 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 688 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 689 "avx", "f16c", "rdrand", "hypervisor",
690 },
07585923 691 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 692 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 693 },
2d5312da
EH		 694 /* Feature names that are already defined on feature_name[] but
695 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
696 * names on feat_names below. They are copied automatically
697 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
698 */
bffd67b0 699 [FEAT_8000_0001_EDX] = {
07585923 700 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 701 .feat_names = {
702 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
703 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
704 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
705 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
706 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 707 "nx", NULL, "mmxext", NULL /* mmx */,
708 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
709 NULL, "lm", "3dnowext", "3dnow",
2d5312da 710 },
07585923 711 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 712 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 713 },
714 [FEAT_8000_0001_ECX] = {
07585923 715 .type = CPUID_FEATURE_WORD,
2d5312da 716 .feat_names = {
fc7dfd20 717 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 718 "cr8legacy", "abm", "sse4a", "misalignsse",
719 "3dnowprefetch", "osvw", "ibs", "xop",
720 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 721 "fma4", "tce", NULL, "nodeid-msr",
722 NULL, "tbm", "topoext", "perfctr-core",
723 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 724 NULL, NULL, NULL, NULL,
725 },
07585923 726 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 727 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 728 /*
729 * TOPOEXT is always allowed but can't be enabled blindly by
730 * "-cpu host", as it requires consistent cache topology info
731 * to be provided so it doesn't confuse guests.
732 */
733 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 734 },
89e49c8b 735 [FEAT_C000_0001_EDX] = {
07585923 736 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 737 .feat_names = {
738 NULL, NULL, "xstore", "xstore-en",
739 NULL, NULL, "xcrypt", "xcrypt-en",
740 "ace2", "ace2-en", "phe", "phe-en",
741 "pmm", "pmm-en", NULL, NULL,
742 NULL, NULL, NULL, NULL,
743 NULL, NULL, NULL, NULL,
744 NULL, NULL, NULL, NULL,
745 NULL, NULL, NULL, NULL,
746 },
07585923 747 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 748 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 749 },
bffd67b0 750 [FEAT_KVM] = {
07585923 751 .type = CPUID_FEATURE_WORD,
2d5312da 752 .feat_names = {
fc7dfd20
EH		 753 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
754 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 755 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 756 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 "kvmclock-stable-bit", NULL, NULL, NULL,
760 NULL, NULL, NULL, NULL,
761 },
07585923 762 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 763 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 764 },
be777326 765 [FEAT_KVM_HINTS] = {
07585923 766 .type = CPUID_FEATURE_WORD,
be777326
WL		 767 .feat_names = {
768 "kvm-hint-dedicated", NULL, NULL, NULL,
769 NULL, NULL, NULL, NULL,
770 NULL, NULL, NULL, NULL,
771 NULL, NULL, NULL, NULL,
772 NULL, NULL, NULL, NULL,
773 NULL, NULL, NULL, NULL,
774 NULL, NULL, NULL, NULL,
775 NULL, NULL, NULL, NULL,
776 },
07585923 777 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 778 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 779 /*
780 * KVM hints aren't auto-enabled by -cpu host, they need to be
781 * explicitly enabled in the command-line.
782 */
783 .no_autoenable_flags = ~0U,
be777326 784 },
bffd67b0 785 [FEAT_SVM] = {
07585923 786 .type = CPUID_FEATURE_WORD,
2d5312da 787 .feat_names = {
fc7dfd20
EH		 788 "npt", "lbrv", "svm-lock", "nrip-save",
789 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
790 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 791 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
792 "vgif", NULL, NULL, NULL,
2d5312da
EH		 793 NULL, NULL, NULL, NULL,
794 NULL, NULL, NULL, NULL,
5447089c 795 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 796 },
07585923 797 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 798 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 799 },
800 [FEAT_7_0_EBX] = {
07585923 801 .type = CPUID_FEATURE_WORD,
2d5312da 802 .feat_names = {
5c76b651 803 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 804 "hle", "avx2", NULL, "smep",
805 "bmi2", "erms", "invpcid", "rtm",
806 NULL, NULL, "mpx", NULL,
807 "avx512f", "avx512dq", "rdseed", "adx",
808 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 809 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 810 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 811 },
07585923
RH		 812 .cpuid = {
813 .eax = 7,
814 .needs_ecx = true, .ecx = 0,
815 .reg = R_EBX,
816 },
37ce3522 817 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 818 },
f74eefe0 819 [FEAT_7_0_ECX] = {
07585923 820 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 821 .feat_names = {
822 NULL, "avx512vbmi", "umip", "pku",
67192a29 823 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 824 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
825 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 826 "la57", NULL, NULL, NULL,
2d5312da 827 NULL, NULL, "rdpid", NULL,
06e878b4 828 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 829 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 830 },
07585923
RH		 831 .cpuid = {
832 .eax = 7,
833 .needs_ecx = true, .ecx = 0,
834 .reg = R_ECX,
835 },
f74eefe0
HH		 836 .tcg_features = TCG_7_0_ECX_FEATURES,
837 },
95ea69fb 838 [FEAT_7_0_EDX] = {
07585923 839 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 840 .feat_names = {
841 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 842 "fsrm", NULL, NULL, NULL,
353f98c9 843 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 844 NULL, NULL, "serialize", NULL,
b3c7344e 845 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
40399ecb 846 NULL, NULL, NULL, "avx512-fp16",
0e891658 847 NULL, NULL, "spec-ctrl", "stibp",
597360c0 848 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 849 },
07585923
RH		 850 .cpuid = {
851 .eax = 7,
852 .needs_ecx = true, .ecx = 0,
853 .reg = R_EDX,
854 },
95ea69fb
LK		 855 .tcg_features = TCG_7_0_EDX_FEATURES,
856 },
80db491d
JL		 857 [FEAT_7_1_EAX] = {
858 .type = CPUID_FEATURE_WORD,
859 .feat_names = {
860 NULL, NULL, NULL, NULL,
c1826ea6 861 "avx-vnni", "avx512-bf16", NULL, NULL,
80db491d
JL		 862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 NULL, NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 },
869 .cpuid = {
870 .eax = 7,
871 .needs_ecx = true, .ecx = 1,
872 .reg = R_EAX,
873 },
874 .tcg_features = TCG_7_1_EAX_FEATURES,
875 },
303752a9 876 [FEAT_8000_0007_EDX] = {
07585923 877 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 878 .feat_names = {
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 "invtsc", NULL, NULL, NULL,
882 NULL, NULL, NULL, NULL,
883 NULL, NULL, NULL, NULL,
884 NULL, NULL, NULL, NULL,
885 NULL, NULL, NULL, NULL,
886 NULL, NULL, NULL, NULL,
887 },
07585923 888 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 889 .tcg_features = TCG_APM_FEATURES,
890 .unmigratable_flags = CPUID_APM_INVTSC,
891 },
1b3420e1 892 [FEAT_8000_0008_EBX] = {
07585923 893 .type = CPUID_FEATURE_WORD,
1b3420e1 894 .feat_names = {
e900135d 895 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 896 NULL, NULL, NULL, NULL,
59a80a19 897 NULL, "wbnoinvd", NULL, NULL,
623972ce 898 "ibpb", NULL, "ibrs", "amd-stibp",
1b3420e1
EH		 899 NULL, NULL, NULL, NULL,
900 NULL, NULL, NULL, NULL,
254790a9 901 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 902 NULL, NULL, NULL, NULL,
903 },
07585923 904 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 905 .tcg_features = 0,
906 .unmigratable_flags = 0,
907 },
0bb0b2d2 908 [FEAT_XSAVE] = {
07585923 909 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 910 .feat_names = {
911 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
912 NULL, NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
914 NULL, NULL, NULL, NULL,
915 NULL, NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 },
07585923
RH		 920 .cpuid = {
921 .eax = 0xd,
922 .needs_ecx = true, .ecx = 1,
923 .reg = R_EAX,
924 },
c9cfe8f9 925 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 926 },
28b8e4d0 927 [FEAT_6_EAX] = {
07585923 928 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 929 .feat_names = {
930 NULL, NULL, "arat", NULL,
931 NULL, NULL, NULL, NULL,
932 NULL, NULL, NULL, NULL,
933 NULL, NULL, NULL, NULL,
934 NULL, NULL, NULL, NULL,
935 NULL, NULL, NULL, NULL,
936 NULL, NULL, NULL, NULL,
937 NULL, NULL, NULL, NULL,
938 },
07585923 939 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 940 .tcg_features = TCG_6_EAX_FEATURES,
941 },
96193c22 942 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 943 .type = CPUID_FEATURE_WORD,
944 .cpuid = {
945 .eax = 0xD,
946 .needs_ecx = true, .ecx = 0,
947 .reg = R_EAX,
948 },
96193c22 949 .tcg_features = ~0U,
6fb2fff7
EH		 950 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
951 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
952 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
953 XSTATE_PKRU_MASK,
96193c22
EH		 954 },
955 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 956 .type = CPUID_FEATURE_WORD,
957 .cpuid = {
958 .eax = 0xD,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EDX,
961 },
96193c22
EH		 962 .tcg_features = ~0U,
963 },
d86f9636
RH		 964 /*Below are MSR exposed features*/
965 [FEAT_ARCH_CAPABILITIES] = {
966 .type = MSR_FEATURE_WORD,
967 .feat_names = {
968 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 969 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 970 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 },
977 .msr = {
978 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 979 },
980 },
597360c0
XL		 981 [FEAT_CORE_CAPABILITY] = {
982 .type = MSR_FEATURE_WORD,
983 .feat_names = {
984 NULL, NULL, NULL, NULL,
985 NULL, "split-lock-detect", NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
993 .msr = {
994 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 995 },
996 },
ea39f9b6
LX		 997 [FEAT_PERF_CAPABILITIES] = {
998 .type = MSR_FEATURE_WORD,
999 .feat_names = {
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 NULL, NULL, NULL, NULL,
1003 NULL, "full-width-write", NULL, NULL,
1004 NULL, NULL, NULL, NULL,
1005 NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 },
1009 .msr = {
1010 .index = MSR_IA32_PERF_CAPABILITIES,
1011 },
1012 },
20a78b02
PB		 1013
1014 [FEAT_VMX_PROCBASED_CTLS] = {
1015 .type = MSR_FEATURE_WORD,
1016 .feat_names = {
1017 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1018 NULL, NULL, NULL, "vmx-hlt-exit",
1019 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1020 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1021 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1022 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1023 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1024 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1025 },
1026 .msr = {
1027 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1028 }
1029 },
1030
1031 [FEAT_VMX_SECONDARY_CTLS] = {
1032 .type = MSR_FEATURE_WORD,
1033 .feat_names = {
1034 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1035 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1036 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1037 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1038 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1039 "vmx-xsaves", NULL, NULL, NULL,
9ce8af4d 1040 NULL, "vmx-tsc-scaling", NULL, NULL,
20a78b02
PB		 1041 NULL, NULL, NULL, NULL,
1042 },
1043 .msr = {
1044 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1045 }
1046 },
1047
1048 [FEAT_VMX_PINBASED_CTLS] = {
1049 .type = MSR_FEATURE_WORD,
1050 .feat_names = {
1051 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1052 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1053 NULL, NULL, NULL, NULL,
1054 NULL, NULL, NULL, NULL,
1055 NULL, NULL, NULL, NULL,
1056 NULL, NULL, NULL, NULL,
1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 },
1060 .msr = {
1061 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1062 }
1063 },
1064
1065 [FEAT_VMX_EXIT_CTLS] = {
1066 .type = MSR_FEATURE_WORD,
1067 /*
1068 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1069 * the LM CPUID bit.
1070 */
1071 .feat_names = {
1072 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1073 NULL, NULL, NULL, NULL,
1074 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1075 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1076 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1077 "vmx-exit-save-efer", "vmx-exit-load-efer",
1078 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1079 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1080 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1081 },
1082 .msr = {
1083 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1084 }
1085 },
1086
1087 [FEAT_VMX_ENTRY_CTLS] = {
1088 .type = MSR_FEATURE_WORD,
1089 .feat_names = {
1090 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1091 NULL, NULL, NULL, NULL,
1092 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1093 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1094 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1095 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 },
1099 .msr = {
1100 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1101 }
1102 },
1103
1104 [FEAT_VMX_MISC] = {
1105 .type = MSR_FEATURE_WORD,
1106 .feat_names = {
1107 NULL, NULL, NULL, NULL,
1108 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1109 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1110 NULL, NULL, NULL, NULL,
1111 NULL, NULL, NULL, NULL,
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
1114 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1115 },
1116 .msr = {
1117 .index = MSR_IA32_VMX_MISC,
1118 }
1119 },
1120
1121 [FEAT_VMX_EPT_VPID_CAPS] = {
1122 .type = MSR_FEATURE_WORD,
1123 .feat_names = {
1124 "vmx-ept-execonly", NULL, NULL, NULL,
1125 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1126 NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL,
1128 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1129 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1130 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1131 NULL, NULL, NULL, NULL,
1132 "vmx-invvpid", NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1135 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .msr = {
1143 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1144 }
1145 },
1146
1147 [FEAT_VMX_BASIC] = {
1148 .type = MSR_FEATURE_WORD,
1149 .feat_names = {
1150 [54] = "vmx-ins-outs",
1151 [55] = "vmx-true-ctls",
1152 },
1153 .msr = {
1154 .index = MSR_IA32_VMX_BASIC,
1155 },
1156 /* Just to be safe - we don't support setting the MSEG version field. */
1157 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1158 },
1159
1160 [FEAT_VMX_VMFUNC] = {
1161 .type = MSR_FEATURE_WORD,
1162 .feat_names = {
1163 [0] = "vmx-eptp-switching",
1164 },
1165 .msr = {
1166 .index = MSR_IA32_VMX_VMFUNC,
1167 }
1168 },
1169
d1615ea5
LK		 1170 [FEAT_14_0_ECX] = {
1171 .type = CPUID_FEATURE_WORD,
1172 .feat_names = {
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 NULL, NULL, NULL, NULL,
1177 NULL, NULL, NULL, NULL,
1178 NULL, NULL, NULL, NULL,
1179 NULL, NULL, NULL, NULL,
1180 NULL, NULL, NULL, "intel-pt-lip",
1181 },
1182 .cpuid = {
1183 .eax = 0x14,
1184 .needs_ecx = true, .ecx = 0,
1185 .reg = R_ECX,
1186 },
1187 .tcg_features = TCG_14_0_ECX_FEATURES,
1188 },
1189
4b841a79
SC		 1190 [FEAT_SGX_12_0_EAX] = {
1191 .type = CPUID_FEATURE_WORD,
1192 .feat_names = {
1193 "sgx1", "sgx2", NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 NULL, NULL, NULL, NULL,
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 },
1202 .cpuid = {
1203 .eax = 0x12,
1204 .needs_ecx = true, .ecx = 0,
1205 .reg = R_EAX,
1206 },
1207 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1208 },
120ca112
SC		 1209
1210 [FEAT_SGX_12_0_EBX] = {
1211 .type = CPUID_FEATURE_WORD,
1212 .feat_names = {
1213 "sgx-exinfo" , NULL, NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 NULL, NULL, NULL, NULL,
1217 NULL, NULL, NULL, NULL,
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, NULL,
1221 },
1222 .cpuid = {
1223 .eax = 0x12,
1224 .needs_ecx = true, .ecx = 0,
1225 .reg = R_EBX,
1226 },
1227 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1228 },
165981a5
SC		 1229
1230 [FEAT_SGX_12_1_EAX] = {
1231 .type = CPUID_FEATURE_WORD,
1232 .feat_names = {
1233 NULL, "sgx-debug", "sgx-mode64", NULL,
1234 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1235 NULL, NULL, NULL, NULL,
1236 NULL, NULL, NULL, NULL,
1237 NULL, NULL, NULL, NULL,
1238 NULL, NULL, NULL, NULL,
1239 NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL,
1241 },
1242 .cpuid = {
1243 .eax = 0x12,
1244 .needs_ecx = true, .ecx = 1,
1245 .reg = R_EAX,
1246 },
1247 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1248 },
5ef57876
EH		 1249};
1250
99e24dbd
PB		 1251typedef struct FeatureMask {
1252 FeatureWord index;
ede146c2 1253 uint64_t mask;
99e24dbd
PB		 1254} FeatureMask;
1255
1256typedef struct FeatureDep {
1257 FeatureMask from, to;
1258} FeatureDep;
1259
1260static FeatureDep feature_dependencies[] = {
1261 {
1262 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1263 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1264 },
1265 {
1266 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1267 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1268 },
ea39f9b6
LX		 1269 {
1270 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1271 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1272 },
20a78b02
PB		 1273 {
1274 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1275 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1276 },
1277 {
1278 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1279 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1280 },
1281 {
1282 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1283 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1284 },
1285 {
1286 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1287 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1288 },
1289 {
1290 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1291 .to = { FEAT_VMX_MISC, ~0ull },
1292 },
1293 {
1294 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1295 .to = { FEAT_VMX_BASIC, ~0ull },
1296 },
1297 {
1298 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1299 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1300 },
1301 {
1302 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1303 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1304 },
1305 {
1306 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1307 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1308 },
1309 {
1310 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1311 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1312 },
1313 {
1314 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1315 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1316 },
1317 {
1318 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1319 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1320 },
d1615ea5
LK		 1321 {
1322 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1323 .to = { FEAT_14_0_ECX, ~0ull },
1324 },
20a78b02
PB		 1325 {
1326 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1327 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1328 },
1329 {
1330 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1331 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1332 },
1333 {
1334 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1335 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1336 },
1337 {
1338 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1339 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1340 },
1341 {
1342 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1343 .to = { FEAT_VMX_VMFUNC, ~0ull },
1344 },
730319ae
EH		 1345 {
1346 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1347 .to = { FEAT_SVM, ~0ull },
1348 },
99e24dbd
PB		 1349};
1350
8e8aba50
EH		 1351typedef struct X86RegisterInfo32 {
1352 /* Name of register */
1353 const char *name;
1354 /* QAPI enum value register */
1355 X86CPURegister32 qapi_enum;
1356} X86RegisterInfo32;
1357
1358#define REGISTER(reg) \
5d371f41 1359 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1360static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1361 REGISTER(EAX),
1362 REGISTER(ECX),
1363 REGISTER(EDX),
1364 REGISTER(EBX),
1365 REGISTER(ESP),
1366 REGISTER(EBP),
1367 REGISTER(ESI),
1368 REGISTER(EDI),
1369};
1370#undef REGISTER
1371
fea45008 1372ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1373 [XSTATE_FP_BIT] = {
1374 /* x87 FP state component is always enabled if XSAVE is supported */
1375 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1376 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1377 },
1378 [XSTATE_SSE_BIT] = {
1379 /* SSE state component is always enabled if XSAVE is supported */
1380 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1381 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1382 },
cfc3b074
PB		 1383 [XSTATE_YMM_BIT] =
1384 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1385 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1386 [XSTATE_BNDREGS_BIT] =
1387 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1388 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1389 [XSTATE_BNDCSR_BIT] =
1390 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1391 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1392 [XSTATE_OPMASK_BIT] =
1393 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1394 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1395 [XSTATE_ZMM_Hi256_BIT] =
1396 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1397 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1398 [XSTATE_Hi16_ZMM_BIT] =
1399 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1400 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1401 [XSTATE_PKRU_BIT] =
1402 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1403 .size = sizeof(XSavePKRU) },
2560f19f 1404};
8e8aba50 1405
1fda6198
EH		 1406static uint32_t xsave_area_size(uint64_t mask)
1407{
1408 int i;
e3c9022b 1409 uint64_t ret = 0;
1fda6198 1410
e3c9022b 1411 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1412 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1413 if ((mask >> i) & 1) {
1414 ret = MAX(ret, esa->offset + esa->size);
1415 }
1416 }
1417 return ret;
1418}
1419
d6dcc558
SAGDR		 1420static inline bool accel_uses_host_cpuid(void)
1421{
1422 return kvm_enabled() || hvf_enabled();
1423}
1424
96193c22
EH		 1425static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1426{
1427 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1428 cpu->env.features[FEAT_XSAVE_COMP_LO];
1429}
1430
ed69e831
CF		 1431/* Return name of 32-bit register, from a R_* constant */
1432static const char *get_register_name_32(unsigned int reg)
8b4beddc 1433{
31ccdde2 1434 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1435 return NULL;
1436 }
8e8aba50 1437 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1438}
1439
84f1b92f
EH		 1440/*
1441 * Returns the set of feature flags that are supported and migratable by
1442 * QEMU, for a given FeatureWord.
1443 */
ede146c2 1444static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1445{
1446 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1447 uint64_t r = 0;
84f1b92f
EH		 1448 int i;
1449
ede146c2
PB		 1450 for (i = 0; i < 64; i++) {
1451 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1452
1453 /* If the feature name is known, it is implicitly considered migratable,
1454 * unless it is explicitly set in unmigratable_flags */
1455 if ((wi->migratable_flags & f) ||
1456 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1457 r |= f;
84f1b92f 1458 }
84f1b92f
EH		 1459 }
1460 return r;
1461}
1462
bb44e0d1
JK		 1463void host_cpuid(uint32_t function, uint32_t count,
1464 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1465{
a1fd24af
AL		 1466 uint32_t vec[4];
1467
1468#ifdef __x86_64__
1469 asm volatile("cpuid"
1470 : "=a"(vec[0]), "=b"(vec[1]),
1471 "=c"(vec[2]), "=d"(vec[3])
1472 : "0"(function), "c"(count) : "cc");
c1f41226 1473#elif defined(__i386__)
a1fd24af
AL		 1474 asm volatile("pusha \n\t"
1475 "cpuid \n\t"
1476 "mov %%eax, 0(%2) \n\t"
1477 "mov %%ebx, 4(%2) \n\t"
1478 "mov %%ecx, 8(%2) \n\t"
1479 "mov %%edx, 12(%2) \n\t"
1480 "popa"
1481 : : "a"(function), "c"(count), "S"(vec)
1482 : "memory", "cc");
c1f41226
EH		 1483#else
1484 abort();
a1fd24af
AL		 1485#endif
1486
bdde476a 1487 if (eax)
a1fd24af 1488 *eax = vec[0];
bdde476a 1489 if (ebx)
a1fd24af 1490 *ebx = vec[1];
bdde476a 1491 if (ecx)
a1fd24af 1492 *ecx = vec[2];
bdde476a 1493 if (edx)
a1fd24af 1494 *edx = vec[3];
bdde476a 1495}
c6dc6f63 1496
d940ee9b
EH		 1497/* CPU class name definitions: */
1498
d940ee9b
EH		 1499/* Return type name for a given CPU model name
1500 * Caller is responsible for freeing the returned string.
1501 */
1502static char *x86_cpu_type_name(const char *model_name)
1503{
1504 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1505}
1506
500050d1
AF		 1507static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1508{
88703ce2
EH		 1509 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1510 return object_class_by_name(typename);
500050d1
AF		 1511}
1512
104494ea
IM		 1513static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1514{
1515 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1516 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1517 return g_strndup(class_name,
1518 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1519}
1520
dcafd1ef
EH		 1521typedef struct X86CPUVersionDefinition {
1522 X86CPUVersion version;
53db89d9 1523 const char *alias;
c63938df 1524 const char *note;
dcafd1ef
EH		 1525 PropValue *props;
1526} X86CPUVersionDefinition;
1527
1528/* Base definition for a CPU model */
1529typedef struct X86CPUDefinition {
c6dc6f63
AP		 1530 const char *name;
1531 uint32_t level;
90e4b0c3 1532 uint32_t xlevel;
99b88a17
IM		 1533 /* vendor is zero-terminated, 12 character ASCII string */
1534 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1535 int family;
1536 int model;
1537 int stepping;
0514ef2f 1538 FeatureWordArray features;
807e9869 1539 const char *model_id;
e845de38 1540 const CPUCaches *const cache_info;
dcafd1ef
EH		 1541 /*
1542 * Definitions for alternative versions of CPU model.
1543 * List is terminated by item with version == 0.
1544 * If NULL, version 1 will be registered automatically.
1545 */
1546 const X86CPUVersionDefinition *versions;
61ad65d0 1547 const char *deprecation_note;
dcafd1ef
EH		 1548} X86CPUDefinition;
1549
1550/* Reference to a specific CPU model version */
1551struct X86CPUModel {
1552 /* Base CPU definition */
e11fd689 1553 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1554 /* CPU model version */
1555 X86CPUVersion version;
c63938df 1556 const char *note;
0788a56b
EH		 1557 /*
1558 * If true, this is an alias CPU model.
1559 * This matters only for "-cpu help" and query-cpu-definitions
1560 */
1561 bool is_alias;
d940ee9b 1562};
c6dc6f63 1563
dcafd1ef 1564/* Get full model name for CPU version */
e11fd689 1565static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1566 X86CPUVersion version)
1567{
1568 assert(version > 0);
1569 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1570}
1571
e11fd689
PMD		 1572static const X86CPUVersionDefinition *
1573x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1574{
1575 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1576 static const X86CPUVersionDefinition default_version_list[] = {
1577 { 1 },
1578 { /* end of list */ }
1579 };
1580
1581 return def->versions ?: default_version_list;
1582}
1583
e845de38 1584static const CPUCaches epyc_cache_info = {
a9f27ea9 1585 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1586 .type = DATA_CACHE,
fe52acd2
BM		 1587 .level = 1,
1588 .size = 32 * KiB,
1589 .line_size = 64,
1590 .associativity = 8,
1591 .partitions = 1,
1592 .sets = 64,
1593 .lines_per_tag = 1,
1594 .self_init = 1,
1595 .no_invd_sharing = true,
1596 },
a9f27ea9 1597 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1598 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1599 .level = 1,
1600 .size = 64 * KiB,
1601 .line_size = 64,
1602 .associativity = 4,
1603 .partitions = 1,
1604 .sets = 256,
1605 .lines_per_tag = 1,
1606 .self_init = 1,
1607 .no_invd_sharing = true,
1608 },
a9f27ea9 1609 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1610 .type = UNIFIED_CACHE,
1611 .level = 2,
1612 .size = 512 * KiB,
1613 .line_size = 64,
1614 .associativity = 8,
1615 .partitions = 1,
1616 .sets = 1024,
1617 .lines_per_tag = 1,
1618 },
a9f27ea9 1619 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1620 .type = UNIFIED_CACHE,
1621 .level = 3,
1622 .size = 8 * MiB,
1623 .line_size = 64,
1624 .associativity = 16,
1625 .partitions = 1,
1626 .sets = 8192,
1627 .lines_per_tag = 1,
1628 .self_init = true,
1629 .inclusive = true,
1630 .complex_indexing = true,
1631 },
1632};
1633
e845de38 1634static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1635 .l1d_cache = &(CPUCacheInfo) {
1636 .type = DATA_CACHE,
1637 .level = 1,
1638 .size = 32 * KiB,
1639 .line_size = 64,
1640 .associativity = 8,
1641 .partitions = 1,
1642 .sets = 64,
1643 .lines_per_tag = 1,
1644 .self_init = 1,
1645 .no_invd_sharing = true,
1646 },
1647 .l1i_cache = &(CPUCacheInfo) {
1648 .type = INSTRUCTION_CACHE,
1649 .level = 1,
1650 .size = 32 * KiB,
1651 .line_size = 64,
1652 .associativity = 8,
1653 .partitions = 1,
1654 .sets = 64,
1655 .lines_per_tag = 1,
1656 .self_init = 1,
1657 .no_invd_sharing = true,
1658 },
1659 .l2_cache = &(CPUCacheInfo) {
1660 .type = UNIFIED_CACHE,
1661 .level = 2,
1662 .size = 512 * KiB,
1663 .line_size = 64,
1664 .associativity = 8,
1665 .partitions = 1,
1666 .sets = 1024,
1667 .lines_per_tag = 1,
1668 },
1669 .l3_cache = &(CPUCacheInfo) {
1670 .type = UNIFIED_CACHE,
1671 .level = 3,
1672 .size = 16 * MiB,
1673 .line_size = 64,
1674 .associativity = 16,
1675 .partitions = 1,
1676 .sets = 16384,
1677 .lines_per_tag = 1,
1678 .self_init = true,
1679 .inclusive = true,
1680 .complex_indexing = true,
1681 },
1682};
1683
e845de38 1684static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 1685 .l1d_cache = &(CPUCacheInfo) {
1686 .type = DATA_CACHE,
1687 .level = 1,
1688 .size = 32 * KiB,
1689 .line_size = 64,
1690 .associativity = 8,
1691 .partitions = 1,
1692 .sets = 64,
1693 .lines_per_tag = 1,
1694 .self_init = 1,
1695 .no_invd_sharing = true,
1696 },
1697 .l1i_cache = &(CPUCacheInfo) {
1698 .type = INSTRUCTION_CACHE,
1699 .level = 1,
1700 .size = 32 * KiB,
1701 .line_size = 64,
1702 .associativity = 8,
1703 .partitions = 1,
1704 .sets = 64,
1705 .lines_per_tag = 1,
1706 .self_init = 1,
1707 .no_invd_sharing = true,
1708 },
1709 .l2_cache = &(CPUCacheInfo) {
1710 .type = UNIFIED_CACHE,
1711 .level = 2,
1712 .size = 512 * KiB,
1713 .line_size = 64,
1714 .associativity = 8,
1715 .partitions = 1,
1716 .sets = 1024,
1717 .lines_per_tag = 1,
1718 },
1719 .l3_cache = &(CPUCacheInfo) {
1720 .type = UNIFIED_CACHE,
1721 .level = 3,
1722 .size = 32 * MiB,
1723 .line_size = 64,
1724 .associativity = 16,
1725 .partitions = 1,
1726 .sets = 32768,
1727 .lines_per_tag = 1,
1728 .self_init = true,
1729 .inclusive = true,
1730 .complex_indexing = true,
1731 },
1732};
1733
0723cc8a
PB		 1734/* The following VMX features are not supported by KVM and are left out in the
1735 * CPU definitions:
1736 *
1737 * Dual-monitor support (all processors)
1738 * Entry to SMM
1739 * Deactivate dual-monitor treatment
1740 * Number of CR3-target values
1741 * Shutdown activity state
1742 * Wait-for-SIPI activity state
1743 * PAUSE-loop exiting (Westmere and newer)
1744 * EPT-violation #VE (Broadwell and newer)
1745 * Inject event with insn length=0 (Skylake and newer)
1746 * Conceal non-root operation from PT
1747 * Conceal VM exits from PT
1748 * Conceal VM entries from PT
1749 * Enable ENCLS exiting
1750 * Mode-based execute control (XS/XU)
1751 s TSC scaling (Skylake Server and newer)
1752 * GPA translation for PT (IceLake and newer)
1753 * User wait and pause
1754 * ENCLV exiting
1755 * Load IA32_RTIT_CTL
1756 * Clear IA32_RTIT_CTL
1757 * Advanced VM-exit information for EPT violations
1758 * Sub-page write permissions
1759 * PT in VMX operation
1760 */
1761
e11fd689 1762static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1763 {
1764 .name = "qemu64",
3046bb5d 1765 .level = 0xd,
99b88a17 1766 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 1767 .family = 15,
1768 .model = 107,
1769 .stepping = 1,
0514ef2f 1770 .features[FEAT_1_EDX] =
27861ecc 1771 PPRO_FEATURES |
c6dc6f63 1772 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1773 CPUID_PSE36,
0514ef2f 1774 .features[FEAT_1_ECX] =
6aa91e4a 1775 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1776 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1777 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1778 .features[FEAT_8000_0001_ECX] =
71195672 1779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1780 .xlevel = 0x8000000A,
9cf2cc3d 1781 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1782 },
1783 {
1784 .name = "phenom",
1785 .level = 5,
99b88a17 1786 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1787 .family = 16,
1788 .model = 2,
1789 .stepping = 3,
b9fc20bc 1790 /* Missing: CPUID_HT */
0514ef2f 1791 .features[FEAT_1_EDX] =
27861ecc 1792 PPRO_FEATURES |
c6dc6f63 1793 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1794 CPUID_PSE36 | CPUID_VME,
0514ef2f 1795 .features[FEAT_1_ECX] =
27861ecc 1796 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1797 CPUID_EXT_POPCNT,
0514ef2f 1798 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1799 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1800 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1801 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1802 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1803 CPUID_EXT3_CR8LEG,
1804 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1805 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1806 .features[FEAT_8000_0001_ECX] =
27861ecc 1807 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1808 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1809 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1810 .features[FEAT_SVM] =
b9fc20bc 1811 CPUID_SVM_NPT,
c6dc6f63
AP		 1812 .xlevel = 0x8000001A,
1813 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1814 },
1815 {
1816 .name = "core2duo",
1817 .level = 10,
99b88a17 1818 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1819 .family = 6,
1820 .model = 15,
1821 .stepping = 11,
b9fc20bc 1822 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1823 .features[FEAT_1_EDX] =
27861ecc 1824 PPRO_FEATURES |
c6dc6f63 1825 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1826 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1827 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1828 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1829 .features[FEAT_1_ECX] =
27861ecc 1830 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1831 CPUID_EXT_CX16,
0514ef2f 1832 .features[FEAT_8000_0001_EDX] =
27861ecc 1833 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1834 .features[FEAT_8000_0001_ECX] =
27861ecc 1835 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1836 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1837 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1838 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1839 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1840 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1841 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1842 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1843 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1844 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1845 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1846 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1847 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1848 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1849 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1850 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1851 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1852 .features[FEAT_VMX_SECONDARY_CTLS] =
1853 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1854 .xlevel = 0x80000008,
1855 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1856 },
1857 {
1858 .name = "kvm64",
3046bb5d 1859 .level = 0xd,
99b88a17 1860 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1861 .family = 15,
1862 .model = 6,
1863 .stepping = 1,
b3a4f0b1 1864 /* Missing: CPUID_HT */
0514ef2f 1865 .features[FEAT_1_EDX] =
b3a4f0b1 1866 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1867 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1868 CPUID_PSE36,
1869 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1870 .features[FEAT_1_ECX] =
27861ecc 1871 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1872 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1873 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1874 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1875 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1876 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1877 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1878 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1879 .features[FEAT_8000_0001_ECX] =
27861ecc 1880 0,
0723cc8a
PB		 1881 /* VMX features from Cedar Mill/Prescott */
1882 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1883 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1884 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1885 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1886 VMX_PIN_BASED_NMI_EXITING,
1887 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1888 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1889 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1890 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1891 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1892 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1893 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1894 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1895 .xlevel = 0x80000008,
1896 .model_id = "Common KVM processor"
1897 },
c6dc6f63
AP		 1898 {
1899 .name = "qemu32",
1900 .level = 4,
99b88a17 1901 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1902 .family = 6,
f8e6a11a 1903 .model = 6,
c6dc6f63 1904 .stepping = 3,
0514ef2f 1905 .features[FEAT_1_EDX] =
27861ecc 1906 PPRO_FEATURES,
0514ef2f 1907 .features[FEAT_1_ECX] =
6aa91e4a 1908 CPUID_EXT_SSE3,
58012d66 1909 .xlevel = 0x80000004,
9cf2cc3d 1910 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1911 },
eafaf1e5
AP		 1912 {
1913 .name = "kvm32",
1914 .level = 5,
99b88a17 1915 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1916 .family = 15,
1917 .model = 6,
1918 .stepping = 1,
0514ef2f 1919 .features[FEAT_1_EDX] =
b3a4f0b1 1920 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1921 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1922 .features[FEAT_1_ECX] =
27861ecc 1923 CPUID_EXT_SSE3,
0514ef2f 1924 .features[FEAT_8000_0001_ECX] =
27861ecc 1925 0,
0723cc8a
PB		 1926 /* VMX features from Yonah */
1927 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1928 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1929 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1930 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1931 VMX_PIN_BASED_NMI_EXITING,
1932 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1936 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1937 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1938 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 1939 .xlevel = 0x80000008,
1940 .model_id = "Common 32-bit KVM processor"
1941 },
c6dc6f63
AP		 1942 {
1943 .name = "coreduo",
1944 .level = 10,
99b88a17 1945 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1946 .family = 6,
1947 .model = 14,
1948 .stepping = 8,
b9fc20bc 1949 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1950 .features[FEAT_1_EDX] =
27861ecc 1951 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1952 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1953 CPUID_SS,
1954 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1955 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1956 .features[FEAT_1_ECX] =
e93abc14 1957 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1958 .features[FEAT_8000_0001_EDX] =
27861ecc 1959 CPUID_EXT2_NX,
0723cc8a
PB		 1960 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1961 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1962 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1963 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1964 VMX_PIN_BASED_NMI_EXITING,
1965 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1966 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1967 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1968 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1969 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1970 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1971 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 1972 .xlevel = 0x80000008,
1973 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1974 },
1975 {
1976 .name = "486",
58012d66 1977 .level = 1,
99b88a17 1978 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1979 .family = 4,
b2a856d9 1980 .model = 8,
c6dc6f63 1981 .stepping = 0,
0514ef2f 1982 .features[FEAT_1_EDX] =
27861ecc 1983 I486_FEATURES,
c6dc6f63 1984 .xlevel = 0,
807e9869 1985 .model_id = "",
c6dc6f63
AP		 1986 },
1987 {
1988 .name = "pentium",
1989 .level = 1,
99b88a17 1990 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1991 .family = 5,
1992 .model = 4,
1993 .stepping = 3,
0514ef2f 1994 .features[FEAT_1_EDX] =
27861ecc 1995 PENTIUM_FEATURES,
c6dc6f63 1996 .xlevel = 0,
807e9869 1997 .model_id = "",
c6dc6f63
AP		 1998 },
1999 {
2000 .name = "pentium2",
2001 .level = 2,
99b88a17 2002 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2003 .family = 6,
2004 .model = 5,
2005 .stepping = 2,
0514ef2f 2006 .features[FEAT_1_EDX] =
27861ecc 2007 PENTIUM2_FEATURES,
c6dc6f63 2008 .xlevel = 0,
807e9869 2009 .model_id = "",
c6dc6f63
AP		 2010 },
2011 {
2012 .name = "pentium3",
3046bb5d 2013 .level = 3,
99b88a17 2014 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2015 .family = 6,
2016 .model = 7,
2017 .stepping = 3,
0514ef2f 2018 .features[FEAT_1_EDX] =
27861ecc 2019 PENTIUM3_FEATURES,
c6dc6f63 2020 .xlevel = 0,
807e9869 2021 .model_id = "",
c6dc6f63
AP		 2022 },
2023 {
2024 .name = "athlon",
2025 .level = 2,
99b88a17 2026 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2027 .family = 6,
2028 .model = 2,
2029 .stepping = 3,
0514ef2f 2030 .features[FEAT_1_EDX] =
27861ecc 2031 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2032 CPUID_MCA,
0514ef2f 2033 .features[FEAT_8000_0001_EDX] =
60032ac0 2034 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2035 .xlevel = 0x80000008,
9cf2cc3d 2036 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2037 },
2038 {
2039 .name = "n270",
3046bb5d 2040 .level = 10,
99b88a17 2041 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2042 .family = 6,
2043 .model = 28,
2044 .stepping = 2,
b9fc20bc 2045 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2046 .features[FEAT_1_EDX] =
27861ecc 2047 PPRO_FEATURES |
b9fc20bc
EH		 2048 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2049 CPUID_ACPI | CPUID_SS,
c6dc6f63 2050 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2051 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2052 * CPUID_EXT_XTPR */
0514ef2f 2053 .features[FEAT_1_ECX] =
27861ecc 2054 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2055 CPUID_EXT_MOVBE,
0514ef2f 2056 .features[FEAT_8000_0001_EDX] =
60032ac0 2057 CPUID_EXT2_NX,
0514ef2f 2058 .features[FEAT_8000_0001_ECX] =
27861ecc 2059 CPUID_EXT3_LAHF_LM,
3046bb5d 2060 .xlevel = 0x80000008,
c6dc6f63
AP		 2061 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2062 },
3eca4642
EH		 2063 {
2064 .name = "Conroe",
3046bb5d 2065 .level = 10,
99b88a17 2066 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2067 .family = 6,
ffce9ebb 2068 .model = 15,
3eca4642 2069 .stepping = 3,
0514ef2f 2070 .features[FEAT_1_EDX] =
b3a4f0b1 2071 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2075 CPUID_DE | CPUID_FP87,
0514ef2f 2076 .features[FEAT_1_ECX] =
27861ecc 2077 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2078 .features[FEAT_8000_0001_EDX] =
27861ecc 2079 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2080 .features[FEAT_8000_0001_ECX] =
27861ecc 2081 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2082 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2083 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2084 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2085 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2086 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2087 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2088 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2089 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2090 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2091 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2092 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2093 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2094 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2095 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2096 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2097 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2098 .features[FEAT_VMX_SECONDARY_CTLS] =
2099 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2100 .xlevel = 0x80000008,
3eca4642
EH		 2101 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2102 },
2103 {
2104 .name = "Penryn",
3046bb5d 2105 .level = 10,
99b88a17 2106 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2107 .family = 6,
ffce9ebb 2108 .model = 23,
3eca4642 2109 .stepping = 3,
0514ef2f 2110 .features[FEAT_1_EDX] =
b3a4f0b1 2111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2115 CPUID_DE | CPUID_FP87,
0514ef2f 2116 .features[FEAT_1_ECX] =
27861ecc 2117 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2118 CPUID_EXT_SSE3,
0514ef2f 2119 .features[FEAT_8000_0001_EDX] =
27861ecc 2120 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2121 .features[FEAT_8000_0001_ECX] =
27861ecc 2122 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2123 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2124 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2125 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2126 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2127 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2128 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2129 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2130 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2131 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2132 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2133 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2134 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2135 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2136 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2137 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2138 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2139 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2140 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2141 .features[FEAT_VMX_SECONDARY_CTLS] =
2142 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2143 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2144 .xlevel = 0x80000008,
3eca4642
EH		 2145 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2146 },
2147 {
2148 .name = "Nehalem",
3046bb5d 2149 .level = 11,
99b88a17 2150 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2151 .family = 6,
ffce9ebb 2152 .model = 26,
3eca4642 2153 .stepping = 3,
0514ef2f 2154 .features[FEAT_1_EDX] =
b3a4f0b1 2155 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2156 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2157 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2158 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2159 CPUID_DE | CPUID_FP87,
0514ef2f 2160 .features[FEAT_1_ECX] =
27861ecc 2161 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2162 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2163 .features[FEAT_8000_0001_EDX] =
27861ecc 2164 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2165 .features[FEAT_8000_0001_ECX] =
27861ecc 2166 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2167 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2168 MSR_VMX_BASIC_TRUE_CTLS,
2169 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2170 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2171 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2172 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2173 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2174 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2175 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2176 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2177 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2178 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2179 .features[FEAT_VMX_EXIT_CTLS] =
2180 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2181 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2182 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2183 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2184 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2185 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2186 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2187 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2188 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2189 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2190 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2191 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2192 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2193 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2194 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2195 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2196 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2197 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2198 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2199 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2200 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2201 .features[FEAT_VMX_SECONDARY_CTLS] =
2202 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2203 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2204 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2205 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2206 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2207 .xlevel = 0x80000008,
3eca4642 2208 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2209 .versions = (X86CPUVersionDefinition[]) {
2210 { .version = 1 },
2211 {
2212 .version = 2,
53db89d9 2213 .alias = "Nehalem-IBRS",
d86a7088
EH		 2214 .props = (PropValue[]) {
2215 { "spec-ctrl", "on" },
2216 { "model-id",
2217 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2218 { /* end of list */ }
2219 }
2220 },
2221 { /* end of list */ }
2222 }
3eca4642
EH		 2223 },
2224 {
2225 .name = "Westmere",
2226 .level = 11,
99b88a17 2227 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2228 .family = 6,
2229 .model = 44,
2230 .stepping = 1,
0514ef2f 2231 .features[FEAT_1_EDX] =
b3a4f0b1 2232 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2233 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2234 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2235 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2236 CPUID_DE | CPUID_FP87,
0514ef2f 2237 .features[FEAT_1_ECX] =
27861ecc 2238 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2239 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2240 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2241 .features[FEAT_8000_0001_EDX] =
27861ecc 2242 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2243 .features[FEAT_8000_0001_ECX] =
27861ecc 2244 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2245 .features[FEAT_6_EAX] =
2246 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2247 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2248 MSR_VMX_BASIC_TRUE_CTLS,
2249 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2250 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2251 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2252 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2253 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2254 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2255 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2256 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2257 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2258 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2259 .features[FEAT_VMX_EXIT_CTLS] =
2260 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2261 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2262 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2263 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2264 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2265 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2266 MSR_VMX_MISC_STORE_LMA,
2267 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2268 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2269 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2270 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2271 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2272 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2273 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2274 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2275 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2276 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2277 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2278 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2279 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2280 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2281 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2282 .features[FEAT_VMX_SECONDARY_CTLS] =
2283 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2284 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2285 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2286 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2287 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2288 .xlevel = 0x80000008,
3eca4642 2289 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2290 .versions = (X86CPUVersionDefinition[]) {
2291 { .version = 1 },
2292 {
2293 .version = 2,
53db89d9 2294 .alias = "Westmere-IBRS",
d86a7088
EH		 2295 .props = (PropValue[]) {
2296 { "spec-ctrl", "on" },
2297 { "model-id",
2298 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2299 { /* end of list */ }
2300 }
2301 },
2302 { /* end of list */ }
2303 }
3eca4642
EH		 2304 },
2305 {
2306 .name = "SandyBridge",
2307 .level = 0xd,
99b88a17 2308 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2309 .family = 6,
2310 .model = 42,
2311 .stepping = 1,
0514ef2f 2312 .features[FEAT_1_EDX] =
b3a4f0b1 2313 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2314 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2315 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2316 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2317 CPUID_DE | CPUID_FP87,
0514ef2f 2318 .features[FEAT_1_ECX] =
27861ecc 2319 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2320 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2321 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2322 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2323 CPUID_EXT_SSE3,
0514ef2f 2324 .features[FEAT_8000_0001_EDX] =
27861ecc 2325 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2326 CPUID_EXT2_SYSCALL,
0514ef2f 2327 .features[FEAT_8000_0001_ECX] =
27861ecc 2328 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2329 .features[FEAT_XSAVE] =
2330 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2331 .features[FEAT_6_EAX] =
2332 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2333 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2334 MSR_VMX_BASIC_TRUE_CTLS,
2335 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2336 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2337 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2338 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2339 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2340 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2341 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2342 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2343 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2344 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2345 .features[FEAT_VMX_EXIT_CTLS] =
2346 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2347 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2348 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2349 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2350 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2351 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2352 MSR_VMX_MISC_STORE_LMA,
2353 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2354 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2355 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2356 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2357 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2358 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2359 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2360 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2361 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2362 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2363 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2364 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2365 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2366 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2367 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2368 .features[FEAT_VMX_SECONDARY_CTLS] =
2369 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2370 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2371 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2372 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2373 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2374 .xlevel = 0x80000008,
3eca4642 2375 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2376 .versions = (X86CPUVersionDefinition[]) {
2377 { .version = 1 },
2378 {
2379 .version = 2,
53db89d9 2380 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2381 .props = (PropValue[]) {
2382 { "spec-ctrl", "on" },
2383 { "model-id",
2384 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2385 { /* end of list */ }
2386 }
2387 },
2388 { /* end of list */ }
2389 }
3eca4642 2390 },
2f9ac42a
PB		 2391 {
2392 .name = "IvyBridge",
2393 .level = 0xd,
2394 .vendor = CPUID_VENDOR_INTEL,
2395 .family = 6,
2396 .model = 58,
2397 .stepping = 9,
2398 .features[FEAT_1_EDX] =
2399 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2400 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2401 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2402 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2403 CPUID_DE | CPUID_FP87,
2404 .features[FEAT_1_ECX] =
2405 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2406 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2407 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2408 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2409 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2410 .features[FEAT_7_0_EBX] =
2411 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2412 CPUID_7_0_EBX_ERMS,
2413 .features[FEAT_8000_0001_EDX] =
2414 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2415 CPUID_EXT2_SYSCALL,
2416 .features[FEAT_8000_0001_ECX] =
2417 CPUID_EXT3_LAHF_LM,
2418 .features[FEAT_XSAVE] =
2419 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2420 .features[FEAT_6_EAX] =
2421 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2422 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2423 MSR_VMX_BASIC_TRUE_CTLS,
2424 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2425 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2426 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2427 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2428 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2429 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2430 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2431 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2432 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2433 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2434 .features[FEAT_VMX_EXIT_CTLS] =
2435 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2436 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2437 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2438 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2439 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2440 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2441 MSR_VMX_MISC_STORE_LMA,
2442 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2443 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2444 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2445 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2446 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2447 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2448 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2449 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2450 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2451 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2452 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2453 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2454 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2455 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2456 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2457 .features[FEAT_VMX_SECONDARY_CTLS] =
2458 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2459 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2460 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2461 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2462 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2463 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2464 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2465 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2466 .xlevel = 0x80000008,
2f9ac42a 2467 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2468 .versions = (X86CPUVersionDefinition[]) {
2469 { .version = 1 },
2470 {
2471 .version = 2,
53db89d9 2472 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2473 .props = (PropValue[]) {
2474 { "spec-ctrl", "on" },
2475 { "model-id",
2476 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2477 { /* end of list */ }
2478 }
2479 },
2480 { /* end of list */ }
2481 }
2f9ac42a 2482 },
ac96c413 2483 {
37507094
EH		 2484 .name = "Haswell",
2485 .level = 0xd,
99b88a17 2486 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2487 .family = 6,
2488 .model = 60,
ec56a4a7 2489 .stepping = 4,
0514ef2f 2490 .features[FEAT_1_EDX] =
b3a4f0b1 2491 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2492 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2493 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2494 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2495 CPUID_DE | CPUID_FP87,
0514ef2f 2496 .features[FEAT_1_ECX] =
27861ecc 2497 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2498 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2499 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2500 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2501 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2502 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2503 .features[FEAT_8000_0001_EDX] =
27861ecc 2504 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2505 CPUID_EXT2_SYSCALL,
0514ef2f 2506 .features[FEAT_8000_0001_ECX] =
becb6667 2507 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2508 .features[FEAT_7_0_EBX] =
27861ecc 2509 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2510 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2511 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2512 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2513 .features[FEAT_XSAVE] =
2514 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2515 .features[FEAT_6_EAX] =
2516 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2517 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2518 MSR_VMX_BASIC_TRUE_CTLS,
2519 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2520 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2521 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2522 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2523 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2524 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2525 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2526 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2528 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2529 .features[FEAT_VMX_EXIT_CTLS] =
2530 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2531 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2532 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2533 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2534 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2535 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2536 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2537 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2538 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2539 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2540 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2541 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2542 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2543 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2544 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2545 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2546 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2547 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2548 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2549 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2550 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2551 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2552 .features[FEAT_VMX_SECONDARY_CTLS] =
2553 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2554 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2555 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2556 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2557 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2558 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2559 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2560 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2561 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2562 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2563 .xlevel = 0x80000008,
37507094 2564 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2565 .versions = (X86CPUVersionDefinition[]) {
2566 { .version = 1 },
2567 {
2568 .version = 2,
53db89d9 2569 .alias = "Haswell-noTSX",
d86a7088
EH		 2570 .props = (PropValue[]) {
2571 { "hle", "off" },
2572 { "rtm", "off" },
2573 { "stepping", "1" },
2574 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2575 { /* end of list */ }
2576 },
2577 },
2578 {
2579 .version = 3,
53db89d9 2580 .alias = "Haswell-IBRS",
d86a7088
EH		 2581 .props = (PropValue[]) {
2582 /* Restore TSX features removed by -v2 above */
2583 { "hle", "on" },
2584 { "rtm", "on" },
2585 /*
2586 * Haswell and Haswell-IBRS had stepping=4 in
2587 * QEMU 4.0 and older
2588 */
2589 { "stepping", "4" },
2590 { "spec-ctrl", "on" },
2591 { "model-id",
2592 "Intel Core Processor (Haswell, IBRS)" },
2593 { /* end of list */ }
2594 }
2595 },
2596 {
2597 .version = 4,
53db89d9 2598 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2599 .props = (PropValue[]) {
2600 { "hle", "off" },
2601 { "rtm", "off" },
2602 /* spec-ctrl was already enabled by -v3 above */
2603 { "stepping", "1" },
2604 { "model-id",
2605 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2606 { /* end of list */ }
2607 }
2608 },
2609 { /* end of list */ }
2610 }
37507094 2611 },
ece01354
EH		 2612 {
2613 .name = "Broadwell",
2614 .level = 0xd,
2615 .vendor = CPUID_VENDOR_INTEL,
2616 .family = 6,
2617 .model = 61,
2618 .stepping = 2,
2619 .features[FEAT_1_EDX] =
b3a4f0b1 2620 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2621 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2622 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2623 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2624 CPUID_DE | CPUID_FP87,
2625 .features[FEAT_1_ECX] =
2626 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2627 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2628 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2629 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2630 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2631 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2632 .features[FEAT_8000_0001_EDX] =
2633 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2634 CPUID_EXT2_SYSCALL,
2635 .features[FEAT_8000_0001_ECX] =
becb6667 2636 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2637 .features[FEAT_7_0_EBX] =
2638 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2639 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2640 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2641 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2642 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2643 .features[FEAT_XSAVE] =
2644 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2645 .features[FEAT_6_EAX] =
2646 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2647 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2648 MSR_VMX_BASIC_TRUE_CTLS,
2649 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2650 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2652 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2653 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2654 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2655 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2656 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2659 .features[FEAT_VMX_EXIT_CTLS] =
2660 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2661 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2662 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2663 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2664 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2665 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2666 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2667 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2668 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2669 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2670 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2671 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2672 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2673 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2674 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2675 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2676 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2677 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2678 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2679 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2680 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2681 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2682 .features[FEAT_VMX_SECONDARY_CTLS] =
2683 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2684 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2685 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2686 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2687 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2688 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2689 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2690 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2691 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2692 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2693 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2694 .xlevel = 0x80000008,
ece01354 2695 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2696 .versions = (X86CPUVersionDefinition[]) {
2697 { .version = 1 },
2698 {
2699 .version = 2,
53db89d9 2700 .alias = "Broadwell-noTSX",
d86a7088
EH		 2701 .props = (PropValue[]) {
2702 { "hle", "off" },
2703 { "rtm", "off" },
2704 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2705 { /* end of list */ }
2706 },
2707 },
2708 {
2709 .version = 3,
53db89d9 2710 .alias = "Broadwell-IBRS",
d86a7088
EH		 2711 .props = (PropValue[]) {
2712 /* Restore TSX features removed by -v2 above */
2713 { "hle", "on" },
2714 { "rtm", "on" },
2715 { "spec-ctrl", "on" },
2716 { "model-id",
2717 "Intel Core Processor (Broadwell, IBRS)" },
2718 { /* end of list */ }
2719 }
2720 },
2721 {
2722 .version = 4,
53db89d9 2723 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2724 .props = (PropValue[]) {
2725 { "hle", "off" },
2726 { "rtm", "off" },
2727 /* spec-ctrl was already enabled by -v3 above */
2728 { "model-id",
2729 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2730 { /* end of list */ }
2731 }
2732 },
2733 { /* end of list */ }
2734 }
ece01354 2735 },
f6f949e9
EH		 2736 {
2737 .name = "Skylake-Client",
2738 .level = 0xd,
2739 .vendor = CPUID_VENDOR_INTEL,
2740 .family = 6,
2741 .model = 94,
2742 .stepping = 3,
2743 .features[FEAT_1_EDX] =
2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2748 CPUID_DE | CPUID_FP87,
2749 .features[FEAT_1_ECX] =
2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2751 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2752 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2753 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2754 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2755 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2756 .features[FEAT_8000_0001_EDX] =
2757 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2758 CPUID_EXT2_SYSCALL,
2759 .features[FEAT_8000_0001_ECX] =
2760 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2761 .features[FEAT_7_0_EBX] =
2762 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2763 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2764 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2765 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2766 CPUID_7_0_EBX_SMAP,
7bde6b18 2767 /* XSAVES is added in version 4 */
f6f949e9
EH		 2768 .features[FEAT_XSAVE] =
2769 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2770 CPUID_XSAVE_XGETBV1,
2771 .features[FEAT_6_EAX] =
2772 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2773 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2774 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2775 MSR_VMX_BASIC_TRUE_CTLS,
2776 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2777 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2778 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2779 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2780 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2781 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2782 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2783 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2785 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2786 .features[FEAT_VMX_EXIT_CTLS] =
2787 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2788 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2789 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2790 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2791 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2792 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2793 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2794 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2795 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2796 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2797 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2798 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2799 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2800 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2801 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2802 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2803 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2804 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2805 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2806 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2807 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2808 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2809 .features[FEAT_VMX_SECONDARY_CTLS] =
2810 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2811 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2812 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2813 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2814 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2815 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2816 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2817 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2818 .xlevel = 0x80000008,
2819 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2820 .versions = (X86CPUVersionDefinition[]) {
2821 { .version = 1 },
2822 {
2823 .version = 2,
53db89d9 2824 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2825 .props = (PropValue[]) {
2826 { "spec-ctrl", "on" },
2827 { "model-id",
2828 "Intel Core Processor (Skylake, IBRS)" },
2829 { /* end of list */ }
2830 }
2831 },
9ab2237f
EH		 2832 {
2833 .version = 3,
02fa60d1 2834 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2835 .props = (PropValue[]) {
2836 { "hle", "off" },
2837 { "rtm", "off" },
673b0add
KC		 2838 { "model-id",
2839 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2840 { /* end of list */ }
2841 }
2842 },
7bde6b18
VK		 2843 {
2844 .version = 4,
2845 .note = "IBRS, XSAVES, no TSX",
2846 .props = (PropValue[]) {
2847 { "xsaves", "on" },
2848 { "vmx-xsaves", "on" },
2849 { /* end of list */ }
2850 }
2851 },
d86a7088
EH		 2852 { /* end of list */ }
2853 }
f6f949e9 2854 },
53f9a6f4
BF		 2855 {
2856 .name = "Skylake-Server",
2857 .level = 0xd,
2858 .vendor = CPUID_VENDOR_INTEL,
2859 .family = 6,
2860 .model = 85,
2861 .stepping = 4,
2862 .features[FEAT_1_EDX] =
2863 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2864 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2865 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2866 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2867 CPUID_DE | CPUID_FP87,
2868 .features[FEAT_1_ECX] =
2869 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2870 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2871 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2872 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2873 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2874 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2875 .features[FEAT_8000_0001_EDX] =
2876 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2877 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2878 .features[FEAT_8000_0001_ECX] =
2879 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2880 .features[FEAT_7_0_EBX] =
2881 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2882 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2883 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2884 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2885 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2886 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2887 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2888 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2889 .features[FEAT_7_0_ECX] =
2890 CPUID_7_0_ECX_PKU,
7bde6b18 2891 /* XSAVES is added in version 5 */
53f9a6f4
BF		 2892 .features[FEAT_XSAVE] =
2893 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2894 CPUID_XSAVE_XGETBV1,
2895 .features[FEAT_6_EAX] =
2896 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2897 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2899 MSR_VMX_BASIC_TRUE_CTLS,
2900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2910 .features[FEAT_VMX_EXIT_CTLS] =
2911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2917 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2931 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2933 .features[FEAT_VMX_SECONDARY_CTLS] =
2934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2939 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2940 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2941 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 2942 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2943 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 2944 .xlevel = 0x80000008,
2945 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 2946 .versions = (X86CPUVersionDefinition[]) {
2947 { .version = 1 },
2948 {
2949 .version = 2,
53db89d9 2950 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 2951 .props = (PropValue[]) {
2952 /* clflushopt was not added to Skylake-Server-IBRS */
2953 /* TODO: add -v3 including clflushopt */
2954 { "clflushopt", "off" },
2955 { "spec-ctrl", "on" },
2956 { "model-id",
2957 "Intel Xeon Processor (Skylake, IBRS)" },
2958 { /* end of list */ }
2959 }
2960 },
9ab2237f
EH		 2961 {
2962 .version = 3,
02fa60d1 2963 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 2964 .props = (PropValue[]) {
2965 { "hle", "off" },
2966 { "rtm", "off" },
673b0add
KC		 2967 { "model-id",
2968 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2969 { /* end of list */ }
2970 }
2971 },
644e3c5d
CQ		 2972 {
2973 .version = 4,
2974 .props = (PropValue[]) {
2975 { "vmx-eptp-switching", "on" },
2976 { /* end of list */ }
2977 }
2978 },
7bde6b18
VK		 2979 {
2980 .version = 5,
2981 .note = "IBRS, XSAVES, EPT switching, no TSX",
2982 .props = (PropValue[]) {
2983 { "xsaves", "on" },
2984 { "vmx-xsaves", "on" },
2985 { /* end of list */ }
2986 }
2987 },
d86a7088
EH		 2988 { /* end of list */ }
2989 }
53f9a6f4 2990 },
c7a88b52
TX		 2991 {
2992 .name = "Cascadelake-Server",
2993 .level = 0xd,
2994 .vendor = CPUID_VENDOR_INTEL,
2995 .family = 6,
2996 .model = 85,
b0a19803 2997 .stepping = 6,
c7a88b52
TX		 2998 .features[FEAT_1_EDX] =
2999 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3003 CPUID_DE | CPUID_FP87,
3004 .features[FEAT_1_ECX] =
3005 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3006 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3007 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3008 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3009 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3010 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3011 .features[FEAT_8000_0001_EDX] =
3012 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3013 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3014 .features[FEAT_8000_0001_ECX] =
3015 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3016 .features[FEAT_7_0_EBX] =
3017 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3018 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3019 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3020 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3021 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3022 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3023 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3024 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3025 .features[FEAT_7_0_ECX] =
bb4928c7 3026 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3027 CPUID_7_0_ECX_AVX512VNNI,
3028 .features[FEAT_7_0_EDX] =
3029 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3030 /* XSAVES is added in version 5 */
c7a88b52
TX		 3031 .features[FEAT_XSAVE] =
3032 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3033 CPUID_XSAVE_XGETBV1,
3034 .features[FEAT_6_EAX] =
3035 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3036 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3037 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3038 MSR_VMX_BASIC_TRUE_CTLS,
3039 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3040 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3041 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3042 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3043 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3044 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3045 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3046 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3047 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3048 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3049 .features[FEAT_VMX_EXIT_CTLS] =
3050 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3051 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3052 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3053 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3054 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3055 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3056 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3057 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3058 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3059 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3060 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3061 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3062 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3063 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3064 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3065 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3066 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3067 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3068 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3069 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3070 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3071 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3072 .features[FEAT_VMX_SECONDARY_CTLS] =
3073 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3074 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3075 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3076 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3077 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3078 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3079 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3080 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3081 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3082 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3083 .xlevel = 0x80000008,
3084 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3085 .versions = (X86CPUVersionDefinition[]) {
3086 { .version = 1 },
3087 { .version = 2,
47f0d11d 3088 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3089 .props = (PropValue[]) {
3090 { "arch-capabilities", "on" },
3091 { "rdctl-no", "on" },
3092 { "ibrs-all", "on" },
3093 { "skip-l1dfl-vmentry", "on" },
3094 { "mds-no", "on" },
3095 { /* end of list */ }
3096 },
3097 },
9ab2237f 3098 { .version = 3,
02fa60d1 3099 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3100 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3101 .props = (PropValue[]) {
3102 { "hle", "off" },
3103 { "rtm", "off" },
3104 { /* end of list */ }
3105 },
3106 },
644e3c5d
CQ		 3107 { .version = 4,
3108 .note = "ARCH_CAPABILITIES, no TSX",
3109 .props = (PropValue[]) {
3110 { "vmx-eptp-switching", "on" },
3111 { /* end of list */ }
3112 },
3113 },
7bde6b18
VK		 3114 { .version = 5,
3115 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3116 .props = (PropValue[]) {
3117 { "xsaves", "on" },
3118 { "vmx-xsaves", "on" },
3119 { /* end of list */ }
3120 },
3121 },
fd63c6d1
EH		 3122 { /* end of list */ }
3123 }
c7a88b52 3124 },
22a866b6
CZ		 3125 {
3126 .name = "Cooperlake",
3127 .level = 0xd,
3128 .vendor = CPUID_VENDOR_INTEL,
3129 .family = 6,
3130 .model = 85,
3131 .stepping = 10,
3132 .features[FEAT_1_EDX] =
3133 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3134 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3135 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3136 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3137 CPUID_DE | CPUID_FP87,
3138 .features[FEAT_1_ECX] =
3139 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3140 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3141 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3142 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3143 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3144 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3145 .features[FEAT_8000_0001_EDX] =
3146 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3147 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3148 .features[FEAT_8000_0001_ECX] =
3149 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3150 .features[FEAT_7_0_EBX] =
3151 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3152 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3153 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3154 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3155 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3156 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3157 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3158 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3159 .features[FEAT_7_0_ECX] =
3160 CPUID_7_0_ECX_PKU |
3161 CPUID_7_0_ECX_AVX512VNNI,
3162 .features[FEAT_7_0_EDX] =
3163 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3164 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3165 .features[FEAT_ARCH_CAPABILITIES] =
3166 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3167 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3168 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3169 .features[FEAT_7_1_EAX] =
f429dbf8 3170 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3171 /* XSAVES is added in version 2 */
22a866b6
CZ		 3172 .features[FEAT_XSAVE] =
3173 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3174 CPUID_XSAVE_XGETBV1,
3175 .features[FEAT_6_EAX] =
3176 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3177 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3178 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3179 MSR_VMX_BASIC_TRUE_CTLS,
3180 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3181 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3182 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3183 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3184 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3185 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3186 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3187 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3189 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3190 .features[FEAT_VMX_EXIT_CTLS] =
3191 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3192 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3193 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3194 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3195 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3196 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3197 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3198 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3199 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3200 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3201 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3202 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3203 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3204 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3205 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3206 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3207 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3208 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3209 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3210 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3211 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3212 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3213 .features[FEAT_VMX_SECONDARY_CTLS] =
3214 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3215 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3216 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3217 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3218 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3219 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3220 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3221 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3222 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3223 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3224 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3225 .xlevel = 0x80000008,
3226 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3227 .versions = (X86CPUVersionDefinition[]) {
3228 { .version = 1 },
3229 { .version = 2,
3230 .note = "XSAVES",
3231 .props = (PropValue[]) {
3232 { "xsaves", "on" },
3233 { "vmx-xsaves", "on" },
3234 { /* end of list */ }
3235 },
3236 },
3237 { /* end of list */ }
3238 }
22a866b6 3239 },
8a11c62d
RH		 3240 {
3241 .name = "Icelake-Client",
3242 .level = 0xd,
3243 .vendor = CPUID_VENDOR_INTEL,
3244 .family = 6,
3245 .model = 126,
3246 .stepping = 0,
3247 .features[FEAT_1_EDX] =
3248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3252 CPUID_DE | CPUID_FP87,
3253 .features[FEAT_1_ECX] =
3254 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3255 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3256 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3257 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3258 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3259 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3260 .features[FEAT_8000_0001_EDX] =
3261 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3262 CPUID_EXT2_SYSCALL,
3263 .features[FEAT_8000_0001_ECX] =
3264 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3265 .features[FEAT_8000_0008_EBX] =
3266 CPUID_8000_0008_EBX_WBNOINVD,
3267 .features[FEAT_7_0_EBX] =
3268 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3269 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3270 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3271 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 3272 CPUID_7_0_EBX_SMAP,
8a11c62d 3273 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3274 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3275 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3276 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3277 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3278 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3279 .features[FEAT_7_0_EDX] =
3280 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3281 /* XSAVES is added in version 3 */
8a11c62d
RH		 3282 .features[FEAT_XSAVE] =
3283 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3284 CPUID_XSAVE_XGETBV1,
3285 .features[FEAT_6_EAX] =
3286 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3287 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3288 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3289 MSR_VMX_BASIC_TRUE_CTLS,
3290 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3291 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3292 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3293 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3294 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3295 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3296 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3297 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3298 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3299 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3300 .features[FEAT_VMX_EXIT_CTLS] =
3301 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3302 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3303 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3304 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3305 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3306 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3307 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3308 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3309 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3310 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3311 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3312 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3313 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3314 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3315 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3316 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3317 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3318 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3319 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3320 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3321 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3322 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3323 .features[FEAT_VMX_SECONDARY_CTLS] =
3324 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3325 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3326 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3327 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3328 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3329 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3330 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3331 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8a11c62d
RH		 3332 .xlevel = 0x80000008,
3333 .model_id = "Intel Core Processor (Icelake)",
9ab2237f 3334 .versions = (X86CPUVersionDefinition[]) {
3e6a015c
RH		 3335 {
3336 .version = 1,
3337 .note = "deprecated"
3338 },
9ab2237f
EH		 3339 {
3340 .version = 2,
3e6a015c 3341 .note = "no TSX, deprecated",
02fa60d1 3342 .alias = "Icelake-Client-noTSX",
9ab2237f
EH		 3343 .props = (PropValue[]) {
3344 { "hle", "off" },
3345 { "rtm", "off" },
3346 { /* end of list */ }
3347 },
3348 },
7bde6b18
VK		 3349 {
3350 .version = 3,
3351 .note = "no TSX, XSAVES, deprecated",
3352 .props = (PropValue[]) {
3353 { "xsaves", "on" },
3354 { "vmx-xsaves", "on" },
3355 { /* end of list */ }
3356 },
3357 },
9ab2237f 3358 { /* end of list */ }
3e6a015c
RH		 3359 },
3360 .deprecation_note = "use Icelake-Server instead"
8a11c62d
RH		 3361 },
3362 {
3363 .name = "Icelake-Server",
3364 .level = 0xd,
3365 .vendor = CPUID_VENDOR_INTEL,
3366 .family = 6,
3367 .model = 134,
3368 .stepping = 0,
3369 .features[FEAT_1_EDX] =
3370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3374 CPUID_DE | CPUID_FP87,
3375 .features[FEAT_1_ECX] =
3376 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3377 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3378 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3379 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3380 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3381 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3382 .features[FEAT_8000_0001_EDX] =
3383 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3384 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3385 .features[FEAT_8000_0001_ECX] =
3386 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3387 .features[FEAT_8000_0008_EBX] =
3388 CPUID_8000_0008_EBX_WBNOINVD,
3389 .features[FEAT_7_0_EBX] =
3390 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3391 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3392 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3393 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3394 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3395 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3396 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3397 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3398 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3399 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3400 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3401 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3402 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3403 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3404 .features[FEAT_7_0_EDX] =
76e5a4d5 3405 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3406 /* XSAVES is added in version 5 */
8a11c62d
RH		 3407 .features[FEAT_XSAVE] =
3408 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3409 CPUID_XSAVE_XGETBV1,
3410 .features[FEAT_6_EAX] =
3411 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3412 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3413 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3414 MSR_VMX_BASIC_TRUE_CTLS,
3415 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3416 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3417 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3418 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3419 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3420 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3421 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3422 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3423 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3424 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3425 .features[FEAT_VMX_EXIT_CTLS] =
3426 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3427 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3428 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3429 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3430 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3431 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3432 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3433 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3434 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3435 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3436 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3437 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3438 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3439 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3440 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3441 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3442 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3443 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3444 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3445 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3446 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3447 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3448 .features[FEAT_VMX_SECONDARY_CTLS] =
3449 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3450 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3451 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3452 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3453 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3454 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3455 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3456 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3457 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3458 .xlevel = 0x80000008,
3459 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3460 .versions = (X86CPUVersionDefinition[]) {
3461 { .version = 1 },
3462 {
3463 .version = 2,
47f0d11d 3464 .note = "no TSX",
02fa60d1 3465 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3466 .props = (PropValue[]) {
3467 { "hle", "off" },
3468 { "rtm", "off" },
3469 { /* end of list */ }
3470 },
3471 },
d965dc35
XL		 3472 {
3473 .version = 3,
3474 .props = (PropValue[]) {
3475 { "arch-capabilities", "on" },
3476 { "rdctl-no", "on" },
3477 { "ibrs-all", "on" },
3478 { "skip-l1dfl-vmentry", "on" },
3479 { "mds-no", "on" },
3480 { "pschange-mc-no", "on" },
3481 { "taa-no", "on" },
3482 { /* end of list */ }
3483 },
3484 },
e0013791
CQ		 3485 {
3486 .version = 4,
3487 .props = (PropValue[]) {
3488 { "sha-ni", "on" },
3489 { "avx512ifma", "on" },
3490 { "rdpid", "on" },
3491 { "fsrm", "on" },
3492 { "vmx-rdseed-exit", "on" },
3493 { "vmx-pml", "on" },
3494 { "vmx-eptp-switching", "on" },
3495 { "model", "106" },
3496 { /* end of list */ }
3497 },
3498 },
7bde6b18
VK		 3499 {
3500 .version = 5,
3501 .note = "XSAVES",
3502 .props = (PropValue[]) {
3503 { "xsaves", "on" },
3504 { "vmx-xsaves", "on" },
3505 { /* end of list */ }
3506 },
3507 },
9ab2237f
EH		 3508 { /* end of list */ }
3509 }
8a11c62d 3510 },
8b44d860
TX		 3511 {
3512 .name = "Denverton",
3513 .level = 21,
3514 .vendor = CPUID_VENDOR_INTEL,
3515 .family = 6,
3516 .model = 95,
3517 .stepping = 1,
3518 .features[FEAT_1_EDX] =
3519 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3520 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3521 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3522 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3523 CPUID_SSE | CPUID_SSE2,
3524 .features[FEAT_1_ECX] =
3525 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3526 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3527 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3528 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3529 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3530 .features[FEAT_8000_0001_EDX] =
3531 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3532 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3533 .features[FEAT_8000_0001_ECX] =
3534 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3535 .features[FEAT_7_0_EBX] =
3536 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3537 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3538 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3539 .features[FEAT_7_0_EDX] =
3540 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3541 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3542 /* XSAVES is added in version 3 */
8b44d860
TX		 3543 .features[FEAT_XSAVE] =
3544 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3545 .features[FEAT_6_EAX] =
3546 CPUID_6_EAX_ARAT,
3547 .features[FEAT_ARCH_CAPABILITIES] =
3548 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3549 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3550 MSR_VMX_BASIC_TRUE_CTLS,
3551 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3552 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3553 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3554 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3555 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3556 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3557 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3558 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3560 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3561 .features[FEAT_VMX_EXIT_CTLS] =
3562 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3563 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3564 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3565 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3566 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3567 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3568 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3569 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3570 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3571 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3572 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3573 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3574 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3575 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3576 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3577 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3578 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3579 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3580 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3581 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3582 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3583 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3584 .features[FEAT_VMX_SECONDARY_CTLS] =
3585 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3586 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3587 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3588 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3589 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3590 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3591 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3592 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3593 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3594 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3595 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3596 .xlevel = 0x80000008,
3597 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3598 .versions = (X86CPUVersionDefinition[]) {
3599 { .version = 1 },
3600 {
3601 .version = 2,
47f0d11d 3602 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3603 .props = (PropValue[]) {
3604 { "monitor", "off" },
3605 { "mpx", "off" },
3606 { /* end of list */ },
3607 },
3608 },
7bde6b18
VK		 3609 {
3610 .version = 3,
3611 .note = "XSAVES, no MPX, no MONITOR",
3612 .props = (PropValue[]) {
3613 { "xsaves", "on" },
3614 { "vmx-xsaves", "on" },
3615 { /* end of list */ },
3616 },
3617 },
ab0c942c
TX		 3618 { /* end of list */ },
3619 },
8b44d860 3620 },
0b18874b 3621 {
ff656fcd 3622 .name = "Snowridge",
0b18874b
PL		 3623 .level = 27,
3624 .vendor = CPUID_VENDOR_INTEL,
3625 .family = 6,
3626 .model = 134,
3627 .stepping = 1,
3628 .features[FEAT_1_EDX] =
3629 /* missing: CPUID_PN CPUID_IA64 */
3630 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3631 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3632 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3633 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3634 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3635 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3636 CPUID_MMX |
3637 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3638 .features[FEAT_1_ECX] =
3639 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3640 CPUID_EXT_SSSE3 |
3641 CPUID_EXT_CX16 |
3642 CPUID_EXT_SSE41 |
3643 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3644 CPUID_EXT_POPCNT |
3645 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3646 CPUID_EXT_RDRAND,
3647 .features[FEAT_8000_0001_EDX] =
3648 CPUID_EXT2_SYSCALL |
3649 CPUID_EXT2_NX |
3650 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3651 CPUID_EXT2_LM,
3652 .features[FEAT_8000_0001_ECX] =
3653 CPUID_EXT3_LAHF_LM |
3654 CPUID_EXT3_3DNOWPREFETCH,
3655 .features[FEAT_7_0_EBX] =
3656 CPUID_7_0_EBX_FSGSBASE |
3657 CPUID_7_0_EBX_SMEP |
3658 CPUID_7_0_EBX_ERMS |
3659 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3660 CPUID_7_0_EBX_RDSEED |
3661 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3662 CPUID_7_0_EBX_CLWB |
3663 CPUID_7_0_EBX_SHA_NI,
3664 .features[FEAT_7_0_ECX] =
3665 CPUID_7_0_ECX_UMIP |
3666 /* missing bit 5 */
3667 CPUID_7_0_ECX_GFNI |
3668 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3669 CPUID_7_0_ECX_MOVDIR64B,
3670 .features[FEAT_7_0_EDX] =
3671 CPUID_7_0_EDX_SPEC_CTRL |
3672 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3673 CPUID_7_0_EDX_CORE_CAPABILITY,
3674 .features[FEAT_CORE_CAPABILITY] =
3675 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7bde6b18 3676 /* XSAVES is is added in version 3 */
0b18874b
PL		 3677 .features[FEAT_XSAVE] =
3678 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3679 CPUID_XSAVE_XGETBV1,
3680 .features[FEAT_6_EAX] =
3681 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3682 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3683 MSR_VMX_BASIC_TRUE_CTLS,
3684 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3685 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3686 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3687 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3688 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3689 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3690 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3691 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3692 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3693 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3694 .features[FEAT_VMX_EXIT_CTLS] =
3695 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3696 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3697 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3698 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3699 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3700 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3701 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3702 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3703 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3704 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3705 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3706 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3707 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3708 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3709 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3710 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3711 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3712 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3713 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3714 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3715 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3716 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3717 .features[FEAT_VMX_SECONDARY_CTLS] =
3718 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3719 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3720 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3721 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3722 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3723 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3724 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3725 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3726 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3727 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3728 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3729 .xlevel = 0x80000008,
3730 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3731 .versions = (X86CPUVersionDefinition[]) {
3732 { .version = 1 },
3733 {
3734 .version = 2,
3735 .props = (PropValue[]) {
3736 { "mpx", "off" },
3737 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3738 { /* end of list */ },
3739 },
3740 },
7bde6b18
VK		 3741 {
3742 .version = 3,
3743 .note = "XSAVES, no MPX",
3744 .props = (PropValue[]) {
3745 { "xsaves", "on" },
3746 { "vmx-xsaves", "on" },
3747 { /* end of list */ },
3748 },
3749 },
56bb24e5
CQ		 3750 {
3751 .version = 4,
07db29f2 3752 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 3753 .props = (PropValue[]) {
3754 { "split-lock-detect", "off" },
07db29f2 3755 { "core-capability", "off" },
56bb24e5
CQ		 3756 { /* end of list */ },
3757 },
3758 },
69edb0f3
XL		 3759 { /* end of list */ },
3760 },
0b18874b 3761 },
a1849515
BF		 3762 {
3763 .name = "KnightsMill",
3764 .level = 0xd,
3765 .vendor = CPUID_VENDOR_INTEL,
3766 .family = 6,
3767 .model = 133,
3768 .stepping = 0,
3769 .features[FEAT_1_EDX] =
3770 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3771 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3772 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3773 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3774 CPUID_PSE | CPUID_DE | CPUID_FP87,
3775 .features[FEAT_1_ECX] =
3776 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3777 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3778 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3779 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3780 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3781 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3782 .features[FEAT_8000_0001_EDX] =
3783 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3784 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3785 .features[FEAT_8000_0001_ECX] =
3786 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3787 .features[FEAT_7_0_EBX] =
3788 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3789 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3790 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3791 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3792 CPUID_7_0_EBX_AVX512ER,
3793 .features[FEAT_7_0_ECX] =
3794 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3795 .features[FEAT_7_0_EDX] =
3796 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3797 .features[FEAT_XSAVE] =
3798 CPUID_XSAVE_XSAVEOPT,
3799 .features[FEAT_6_EAX] =
3800 CPUID_6_EAX_ARAT,
3801 .xlevel = 0x80000008,
3802 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3803 },
3eca4642
EH		 3804 {
3805 .name = "Opteron_G1",
3806 .level = 5,
99b88a17 3807 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3808 .family = 15,
3809 .model = 6,
3810 .stepping = 1,
0514ef2f 3811 .features[FEAT_1_EDX] =
b3a4f0b1 3812 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3813 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3814 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3815 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3816 CPUID_DE | CPUID_FP87,
0514ef2f 3817 .features[FEAT_1_ECX] =
27861ecc 3818 CPUID_EXT_SSE3,
0514ef2f 3819 .features[FEAT_8000_0001_EDX] =
2a923a29 3820 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3821 .xlevel = 0x80000008,
3822 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3823 },
3824 {
3825 .name = "Opteron_G2",
3826 .level = 5,
99b88a17 3827 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3828 .family = 15,
3829 .model = 6,
3830 .stepping = 1,
0514ef2f 3831 .features[FEAT_1_EDX] =
b3a4f0b1 3832 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3833 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3834 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3835 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3836 CPUID_DE | CPUID_FP87,
0514ef2f 3837 .features[FEAT_1_ECX] =
27861ecc 3838 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3839 .features[FEAT_8000_0001_EDX] =
2a923a29 3840 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3841 .features[FEAT_8000_0001_ECX] =
27861ecc 3842 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3843 .xlevel = 0x80000008,
3844 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3845 },
3846 {
3847 .name = "Opteron_G3",
3848 .level = 5,
99b88a17 3849 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3850 .family = 16,
3851 .model = 2,
3852 .stepping = 3,
0514ef2f 3853 .features[FEAT_1_EDX] =
b3a4f0b1 3854 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3855 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3856 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3857 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3858 CPUID_DE | CPUID_FP87,
0514ef2f 3859 .features[FEAT_1_ECX] =
27861ecc 3860 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3861 CPUID_EXT_SSE3,
0514ef2f 3862 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3863 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3864 CPUID_EXT2_RDTSCP,
0514ef2f 3865 .features[FEAT_8000_0001_ECX] =
27861ecc 3866 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3867 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3868 .xlevel = 0x80000008,
3869 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3870 },
3871 {
3872 .name = "Opteron_G4",
3873 .level = 0xd,
99b88a17 3874 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3875 .family = 21,
3876 .model = 1,
3877 .stepping = 2,
0514ef2f 3878 .features[FEAT_1_EDX] =
b3a4f0b1 3879 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3880 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3881 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3882 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3883 CPUID_DE | CPUID_FP87,
0514ef2f 3884 .features[FEAT_1_ECX] =
27861ecc 3885 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3886 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3887 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3888 CPUID_EXT_SSE3,
0514ef2f 3889 .features[FEAT_8000_0001_EDX] =
2a923a29 3890 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3891 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3892 .features[FEAT_8000_0001_ECX] =
27861ecc 3893 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3894 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3895 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3896 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3897 .features[FEAT_SVM] =
3898 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3899 /* no xsaveopt! */
3eca4642
EH		 3900 .xlevel = 0x8000001A,
3901 .model_id = "AMD Opteron 62xx class CPU",
3902 },
021941b9
AP		 3903 {
3904 .name = "Opteron_G5",
3905 .level = 0xd,
99b88a17 3906 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3907 .family = 21,
3908 .model = 2,
3909 .stepping = 0,
0514ef2f 3910 .features[FEAT_1_EDX] =
b3a4f0b1 3911 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3912 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3913 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3914 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3915 CPUID_DE | CPUID_FP87,
0514ef2f 3916 .features[FEAT_1_ECX] =
27861ecc 3917 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3918 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3919 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3920 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3921 .features[FEAT_8000_0001_EDX] =
2a923a29 3922 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3923 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3924 .features[FEAT_8000_0001_ECX] =
27861ecc 3925 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3926 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3927 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3928 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3929 .features[FEAT_SVM] =
3930 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3931 /* no xsaveopt! */
021941b9
AP		 3932 .xlevel = 0x8000001A,
3933 .model_id = "AMD Opteron 63xx class CPU",
3934 },
2e2efc7d
BS		 3935 {
3936 .name = "EPYC",
3937 .level = 0xd,
3938 .vendor = CPUID_VENDOR_AMD,
3939 .family = 23,
3940 .model = 1,
3941 .stepping = 2,
3942 .features[FEAT_1_EDX] =
3943 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3944 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3945 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3946 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3947 CPUID_VME | CPUID_FP87,
3948 .features[FEAT_1_ECX] =
3949 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3950 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3951 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3952 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3953 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3954 .features[FEAT_8000_0001_EDX] =
3955 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3956 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3957 CPUID_EXT2_SYSCALL,
3958 .features[FEAT_8000_0001_ECX] =
3959 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3960 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3961 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3962 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3963 .features[FEAT_7_0_EBX] =
3964 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3965 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3966 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3967 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3968 .features[FEAT_XSAVE] =
3969 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3970 CPUID_XSAVE_XGETBV1,
3971 .features[FEAT_6_EAX] =
3972 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3973 .features[FEAT_SVM] =
3974 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3975 .xlevel = 0x8000001E,
2e2efc7d 3976 .model_id = "AMD EPYC Processor",
fe52acd2 3977 .cache_info = &epyc_cache_info,
d86a7088
EH		 3978 .versions = (X86CPUVersionDefinition[]) {
3979 { .version = 1 },
3980 {
3981 .version = 2,
53db89d9 3982 .alias = "EPYC-IBPB",
d86a7088
EH		 3983 .props = (PropValue[]) {
3984 { "ibpb", "on" },
3985 { "model-id",
3986 "AMD EPYC Processor (with IBPB)" },
3987 { /* end of list */ }
3988 }
3989 },
a16e8dbc
MB		 3990 {
3991 .version = 3,
3992 .props = (PropValue[]) {
3993 { "ibpb", "on" },
3994 { "perfctr-core", "on" },
3995 { "clzero", "on" },
3996 { "xsaveerptr", "on" },
3997 { "xsaves", "on" },
3998 { "model-id",
3999 "AMD EPYC Processor" },
4000 { /* end of list */ }
4001 }
4002 },
d86a7088
EH		 4003 { /* end of list */ }
4004 }
2e2efc7d 4005 },
8d031cec
PW		 4006 {
4007 .name = "Dhyana",
4008 .level = 0xd,
4009 .vendor = CPUID_VENDOR_HYGON,
4010 .family = 24,
4011 .model = 0,
4012 .stepping = 1,
4013 .features[FEAT_1_EDX] =
4014 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4015 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4016 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4017 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4018 CPUID_VME | CPUID_FP87,
4019 .features[FEAT_1_ECX] =
4020 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4021 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4022 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4023 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4024 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4025 .features[FEAT_8000_0001_EDX] =
4026 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4027 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4028 CPUID_EXT2_SYSCALL,
4029 .features[FEAT_8000_0001_ECX] =
4030 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4031 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4032 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4033 CPUID_EXT3_TOPOEXT,
4034 .features[FEAT_8000_0008_EBX] =
4035 CPUID_8000_0008_EBX_IBPB,
4036 .features[FEAT_7_0_EBX] =
4037 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4038 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4039 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 4040 /* XSAVES is added in version 2 */
8d031cec
PW		 4041 .features[FEAT_XSAVE] =
4042 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4043 CPUID_XSAVE_XGETBV1,
4044 .features[FEAT_6_EAX] =
4045 CPUID_6_EAX_ARAT,
4046 .features[FEAT_SVM] =
4047 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4048 .xlevel = 0x8000001E,
4049 .model_id = "Hygon Dhyana Processor",
4050 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4051 .versions = (X86CPUVersionDefinition[]) {
4052 { .version = 1 },
4053 { .version = 2,
4054 .note = "XSAVES",
4055 .props = (PropValue[]) {
4056 { "xsaves", "on" },
4057 { /* end of list */ }
4058 },
4059 },
4060 { /* end of list */ }
4061 }
8d031cec 4062 },
143c30d4
MB		 4063 {
4064 .name = "EPYC-Rome",
4065 .level = 0xd,
4066 .vendor = CPUID_VENDOR_AMD,
4067 .family = 23,
4068 .model = 49,
4069 .stepping = 0,
4070 .features[FEAT_1_EDX] =
4071 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4072 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4073 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4074 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4075 CPUID_VME | CPUID_FP87,
4076 .features[FEAT_1_ECX] =
4077 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4078 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4079 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4080 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4081 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4082 .features[FEAT_8000_0001_EDX] =
4083 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4084 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4085 CPUID_EXT2_SYSCALL,
4086 .features[FEAT_8000_0001_ECX] =
4087 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4088 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4089 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4090 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4091 .features[FEAT_8000_0008_EBX] =
4092 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4093 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4094 CPUID_8000_0008_EBX_STIBP,
4095 .features[FEAT_7_0_EBX] =
4096 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4097 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4098 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4099 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4100 .features[FEAT_7_0_ECX] =
4101 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4102 .features[FEAT_XSAVE] =
4103 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4104 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4105 .features[FEAT_6_EAX] =
4106 CPUID_6_EAX_ARAT,
4107 .features[FEAT_SVM] =
4108 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4109 .xlevel = 0x8000001E,
4110 .model_id = "AMD EPYC-Rome Processor",
4111 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4112 .versions = (X86CPUVersionDefinition[]) {
4113 { .version = 1 },
4114 {
4115 .version = 2,
4116 .props = (PropValue[]) {
4117 { "ibrs", "on" },
4118 { "amd-ssbd", "on" },
4119 { /* end of list */ }
4120 }
4121 },
4122 { /* end of list */ }
4123 }
143c30d4 4124 },
623972ce
BM		 4125 {
4126 .name = "EPYC-Milan",
4127 .level = 0xd,
4128 .vendor = CPUID_VENDOR_AMD,
4129 .family = 25,
4130 .model = 1,
4131 .stepping = 1,
4132 .features[FEAT_1_EDX] =
4133 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4134 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4135 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4136 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4137 CPUID_VME | CPUID_FP87,
4138 .features[FEAT_1_ECX] =
4139 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4140 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4141 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4142 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4143 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4144 CPUID_EXT_PCID,
4145 .features[FEAT_8000_0001_EDX] =
4146 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4147 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4148 CPUID_EXT2_SYSCALL,
4149 .features[FEAT_8000_0001_ECX] =
4150 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4151 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4152 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4153 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4154 .features[FEAT_8000_0008_EBX] =
4155 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4156 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4157 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4158 CPUID_8000_0008_EBX_AMD_SSBD,
4159 .features[FEAT_7_0_EBX] =
4160 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4161 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4162 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4163 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4164 CPUID_7_0_EBX_INVPCID,
4165 .features[FEAT_7_0_ECX] =
4166 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4167 .features[FEAT_7_0_EDX] =
4168 CPUID_7_0_EDX_FSRM,
4169 .features[FEAT_XSAVE] =
4170 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4171 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4172 .features[FEAT_6_EAX] =
4173 CPUID_6_EAX_ARAT,
4174 .features[FEAT_SVM] =
4175 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4176 .xlevel = 0x8000001E,
4177 .model_id = "AMD EPYC-Milan Processor",
4178 .cache_info = &epyc_milan_cache_info,
4179 },
c6dc6f63
AP		 4180};
4181
ad183928
EH		 4182/*
4183 * We resolve CPU model aliases using -v1 when using "-machine
4184 * none", but this is just for compatibility while libvirt isn't
4185 * adapted to resolve CPU model versions before creating VMs.
32048d72 4186 * See "Runnability guarantee of CPU models" at
a476b216 4187 * docs/about/deprecated.rst.
ad183928
EH		 4188 */
4189X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4190
4191void x86_cpu_set_default_version(X86CPUVersion version)
4192{
4193 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4194 assert(version != CPU_VERSION_AUTO);
4195 default_cpu_version = version;
4196}
4197
dcafd1ef
EH		 4198static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4199{
4200 int v = 0;
4201 const X86CPUVersionDefinition *vdef =
4202 x86_cpu_def_get_versions(model->cpudef);
4203 while (vdef->version) {
4204 v = vdef->version;
4205 vdef++;
4206 }
4207 return v;
4208}
4209
4210/* Return the actual version being used for a specific CPU model */
4211static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4212{
4213 X86CPUVersion v = model->version;
0788a56b
EH		 4214 if (v == CPU_VERSION_AUTO) {
4215 v = default_cpu_version;
4216 }
dcafd1ef
EH		 4217 if (v == CPU_VERSION_LATEST) {
4218 return x86_cpu_model_last_version(model);
4219 }
4220 return v;
4221}
4222
c62f2630 4223static Property max_x86_cpu_properties[] = {
120eee7d 4224 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4225 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4226 DEFINE_PROP_END_OF_LIST()
4227};
4228
c62f2630 4229static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4230{
84f1b92f 4231 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4232 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4233
f48c8837 4234 xcc->ordering = 9;
6e746f30 4235
ee465a3e 4236 xcc->model_description =
c62f2630 4237 "Enables all features supported by the accelerator in the current host";
d940ee9b 4238
4f67d30b 4239 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4240}
4241
c62f2630 4242static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4243{
4244 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4245
4d1b279b
EH		 4246 /* We can't fill the features array here because we don't know yet if
4247 * "migratable" is true or false.
4248 */
44bd8e53 4249 cpu->max_features = true;
5325cc34 4250 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4251
4252 /*
4253 * these defaults are used for TCG and all other accelerators
4254 * besides KVM and HVF, which overwrite these values
4255 */
4256 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4257 &error_abort);
40b3cc35
DB		 4258#ifdef TARGET_X86_64
4259 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort);
4260 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort);
4261 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort);
4262#else
f5cc5a5c
CF		 4263 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4264 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4265 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
40b3cc35 4266#endif
f5cc5a5c
CF		 4267 object_property_set_str(OBJECT(cpu), "model-id",
4268 "QEMU TCG CPU version " QEMU_HW_VERSION,
4269 &error_abort);
c6dc6f63
AP		 4270}
4271
c62f2630
EH		 4272static const TypeInfo max_x86_cpu_type_info = {
4273 .name = X86_CPU_TYPE_NAME("max"),
4274 .parent = TYPE_X86_CPU,
4275 .instance_init = max_x86_cpu_initfn,
4276 .class_init = max_x86_cpu_class_init,
4277};
4278
07585923
RH		 4279static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4280{
4281 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4282
4283 switch (f->type) {
4284 case CPUID_FEATURE_WORD:
4285 {
4286 const char *reg = get_register_name_32(f->cpuid.reg);
4287 assert(reg);
4288 return g_strdup_printf("CPUID.%02XH:%s",
4289 f->cpuid.eax, reg);
4290 }
4291 case MSR_FEATURE_WORD:
4292 return g_strdup_printf("MSR(%02XH)",
4293 f->msr.index);
4294 }
4295
4296 return NULL;
4297}
4298
245edd0c 4299static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4300{
245edd0c
PB		 4301 FeatureWord w;
4302
4303 for (w = 0; w < FEATURE_WORDS; w++) {
4304 if (cpu->filtered_features[w]) {
4305 return true;
4306 }
4307 }
4308
4309 return false;
4310}
4311
ede146c2 4312static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4313 const char *verbose_prefix)
4314{
4315 CPUX86State *env = &cpu->env;
8459e396 4316 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4317 int i;
4318
245edd0c
PB		 4319 if (!cpu->force_features) {
4320 env->features[w] &= ~mask;
4321 }
4322 cpu->filtered_features[w] |= mask;
4323
4324 if (!verbose_prefix) {
4325 return;
4326 }
4327
ede146c2
PB		 4328 for (i = 0; i < 64; ++i) {
4329 if ((1ULL << i) & mask) {
88703ce2 4330 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4331 warn_report("%s: %s%s%s [bit %d]",
4332 verbose_prefix,
07585923 4333 feat_word_str,
8297be80
AF		 4334 f->feat_names[i] ? "." : "",
4335 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4336 }
857aee33 4337 }
c6dc6f63
AP		 4338}
4339
d7bce999
EB		 4340static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4341 const char *name, void *opaque,
4342 Error **errp)
95b8519d
AF		 4343{
4344 X86CPU *cpu = X86_CPU(obj);
4345 CPUX86State *env = &cpu->env;
4346 int64_t value;
4347
4348 value = (env->cpuid_version >> 8) & 0xf;
4349 if (value == 0xf) {
4350 value += (env->cpuid_version >> 20) & 0xff;
4351 }
51e72bc1 4352 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4353}
4354
d7bce999
EB		 4355static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4356 const char *name, void *opaque,
4357 Error **errp)
ed5e1ec3 4358{
71ad61d3
AF		 4359 X86CPU *cpu = X86_CPU(obj);
4360 CPUX86State *env = &cpu->env;
4361 const int64_t min = 0;
4362 const int64_t max = 0xff + 0xf;
4363 int64_t value;
4364
668f62ec 4365 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4366 return;
4367 }
4368 if (value < min || value > max) {
c6bd8c70
MA		 4369 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4370 name ? name : "null", value, min, max);
71ad61d3
AF		 4371 return;
4372 }
4373
ed5e1ec3 4374 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4375 if (value > 0x0f) {
4376 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4377 } else {
71ad61d3 4378 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4379 }
4380}
4381
d7bce999
EB		 4382static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4383 const char *name, void *opaque,
4384 Error **errp)
67e30c83
AF		 4385{
4386 X86CPU *cpu = X86_CPU(obj);
4387 CPUX86State *env = &cpu->env;
4388 int64_t value;
4389
4390 value = (env->cpuid_version >> 4) & 0xf;
4391 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4392 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4393}
4394
d7bce999
EB		 4395static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4396 const char *name, void *opaque,
4397 Error **errp)
b0704cbd 4398{
c5291a4f
AF		 4399 X86CPU *cpu = X86_CPU(obj);
4400 CPUX86State *env = &cpu->env;
4401 const int64_t min = 0;
4402 const int64_t max = 0xff;
4403 int64_t value;
4404
668f62ec 4405 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4406 return;
4407 }
4408 if (value < min || value > max) {
c6bd8c70
MA		 4409 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4410 name ? name : "null", value, min, max);
c5291a4f
AF		 4411 return;
4412 }
4413
b0704cbd 4414 env->cpuid_version &= ~0xf00f0;
c5291a4f 4415 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4416}
4417
35112e41 4418static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4419 const char *name, void *opaque,
35112e41
AF		 4420 Error **errp)
4421{
4422 X86CPU *cpu = X86_CPU(obj);
4423 CPUX86State *env = &cpu->env;
4424 int64_t value;
4425
4426 value = env->cpuid_version & 0xf;
51e72bc1 4427 visit_type_int(v, name, &value, errp);
35112e41
AF		 4428}
4429
036e2222 4430static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4431 const char *name, void *opaque,
036e2222 4432 Error **errp)
38c3dc46 4433{
036e2222
AF		 4434 X86CPU *cpu = X86_CPU(obj);
4435 CPUX86State *env = &cpu->env;
4436 const int64_t min = 0;
4437 const int64_t max = 0xf;
4438 int64_t value;
4439
668f62ec 4440 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4441 return;
4442 }
4443 if (value < min || value > max) {
c6bd8c70
MA		 4444 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4445 name ? name : "null", value, min, max);
036e2222
AF		 4446 return;
4447 }
4448
38c3dc46 4449 env->cpuid_version &= ~0xf;
036e2222 4450 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4451}
4452
d480e1af
AF		 4453static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4454{
4455 X86CPU *cpu = X86_CPU(obj);
4456 CPUX86State *env = &cpu->env;
4457 char *value;
d480e1af 4458
e42a92ae 4459 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4460 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4461 env->cpuid_vendor3);
d480e1af
AF		 4462 return value;
4463}
4464
4465static void x86_cpuid_set_vendor(Object *obj, const char *value,
4466 Error **errp)
4467{
4468 X86CPU *cpu = X86_CPU(obj);
4469 CPUX86State *env = &cpu->env;
4470 int i;
4471
9df694ee 4472 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4473 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4474 return;
4475 }
4476
4477 env->cpuid_vendor1 = 0;
4478 env->cpuid_vendor2 = 0;
4479 env->cpuid_vendor3 = 0;
4480 for (i = 0; i < 4; i++) {
4481 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4482 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4483 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4484 }
d480e1af
AF		 4485}
4486
63e886eb
AF		 4487static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4488{
4489 X86CPU *cpu = X86_CPU(obj);
4490 CPUX86State *env = &cpu->env;
4491 char *value;
4492 int i;
4493
4494 value = g_malloc(48 + 1);
4495 for (i = 0; i < 48; i++) {
4496 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4497 }
4498 value[48] = '\0';
4499 return value;
4500}
4501
938d4c25
AF		 4502static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4503 Error **errp)
dcce6675 4504{
938d4c25
AF		 4505 X86CPU *cpu = X86_CPU(obj);
4506 CPUX86State *env = &cpu->env;
dcce6675
AF		 4507 int c, len, i;
4508
4509 if (model_id == NULL) {
4510 model_id = "";
4511 }
4512 len = strlen(model_id);
d0a6acf4 4513 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4514 for (i = 0; i < 48; i++) {
4515 if (i >= len) {
4516 c = '\0';
4517 } else {
4518 c = (uint8_t)model_id[i];
4519 }
4520 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4521 }
4522}
4523
d7bce999
EB		 4524static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4525 void *opaque, Error **errp)
89e48965
AF		 4526{
4527 X86CPU *cpu = X86_CPU(obj);
4528 int64_t value;
4529
4530 value = cpu->env.tsc_khz * 1000;
51e72bc1 4531 visit_type_int(v, name, &value, errp);
89e48965
AF		 4532}
4533
d7bce999
EB		 4534static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4535 void *opaque, Error **errp)
89e48965
AF		 4536{
4537 X86CPU *cpu = X86_CPU(obj);
4538 const int64_t min = 0;
2e84849a 4539 const int64_t max = INT64_MAX;
89e48965
AF		 4540 int64_t value;
4541
668f62ec 4542 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4543 return;
4544 }
4545 if (value < min || value > max) {
c6bd8c70
MA		 4546 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4547 name ? name : "null", value, min, max);
89e48965
AF		 4548 return;
4549 }
4550
36f96c4b 4551 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4552}
4553
7e5292b5 4554/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4555static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4556 const char *name, void *opaque,
4557 Error **errp)
8e8aba50 4558{
ede146c2 4559 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4560 FeatureWord w;
8e8aba50
EH		 4561 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4562 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4563 X86CPUFeatureWordInfoList *list = NULL;
4564
4565 for (w = 0; w < FEATURE_WORDS; w++) {
4566 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4567 /*
4568 * We didn't have MSR features when "feature-words" was
4569 * introduced. Therefore skipped other type entries.
4570 */
4571 if (wi->type != CPUID_FEATURE_WORD) {
4572 continue;
4573 }
8e8aba50 4574 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4575 qwi->cpuid_input_eax = wi->cpuid.eax;
4576 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4577 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4578 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4579 qwi->features = array[w];
8e8aba50
EH		 4580
4581 /* List will be in reverse order, but order shouldn't matter */
4582 list_entries[w].next = list;
4583 list_entries[w].value = &word_infos[w];
4584 list = &list_entries[w];
4585 }
4586
6b62d961 4587 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4588}
4589
72ac2e87
IM		 4590/* Convert all '_' in a feature string option name to '-', to make feature
4591 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4592 */
4593static inline void feat2prop(char *s)
4594{
4595 while ((s = strchr(s, '_'))) {
4596 *s = '-';
4597 }
4598}
4599
b54c9377
EH		 4600/* Return the feature property name for a feature flag bit */
4601static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4602{
ede146c2 4603 const char *name;
b54c9377
EH		 4604 /* XSAVE components are automatically enabled by other features,
4605 * so return the original feature name instead
4606 */
4607 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4608 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4609
4610 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4611 x86_ext_save_areas[comp].bits) {
4612 w = x86_ext_save_areas[comp].feature;
4613 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4614 }
4615 }
4616
ede146c2 4617 assert(bitnr < 64);
b54c9377 4618 assert(w < FEATURE_WORDS);
ede146c2
PB		 4619 name = feature_word_info[w].feat_names[bitnr];
4620 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4621 return name;
b54c9377
EH		 4622}
4623
dc15c051
IM		 4624/* Compatibily hack to maintain legacy +-feat semantic,
4625 * where +-feat overwrites any feature set by
4626 * feat=on|feat even if the later is parsed after +-feat
4627 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4628 */
2fae0d96 4629static GList *plus_features, *minus_features;
dc15c051 4630
83a00f60
EH		 4631static gint compare_string(gconstpointer a, gconstpointer b)
4632{
4633 return g_strcmp0(a, b);
4634}
4635
8f961357
EH		 4636/* Parse "+feature,-feature,feature=foo" CPU feature string
4637 */
62a48a2a 4638static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4639 Error **errp)
8f961357 4640{
8f961357 4641 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4642 static bool cpu_globals_initialized;
83a00f60 4643 bool ambiguous = false;
62a48a2a
IM		 4644
4645 if (cpu_globals_initialized) {
4646 return;
4647 }
4648 cpu_globals_initialized = true;
8f961357 4649
f6750e95
EH		 4650 if (!features) {
4651 return;
4652 }
4653
4654 for (featurestr = strtok(features, ",");
685479bd 4655 featurestr;
f6750e95
EH		 4656 featurestr = strtok(NULL, ",")) {
4657 const char *name;
4658 const char *val = NULL;
4659 char *eq = NULL;
cf2887c9 4660 char num[32];
62a48a2a 4661 GlobalProperty *prop;
c6dc6f63 4662
f6750e95 4663 /* Compatibility syntax: */
c6dc6f63 4664 if (featurestr[0] == '+') {
2fae0d96
EH		 4665 plus_features = g_list_append(plus_features,
4666 g_strdup(featurestr + 1));
f6750e95 4667 continue;
c6dc6f63 4668 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4669 minus_features = g_list_append(minus_features,
4670 g_strdup(featurestr + 1));
f6750e95
EH		 4671 continue;
4672 }
4673
4674 eq = strchr(featurestr, '=');
4675 if (eq) {
4676 *eq++ = 0;
4677 val = eq;
c6dc6f63 4678 } else {
f6750e95 4679 val = "on";
a91987c2 4680 }
f6750e95
EH		 4681
4682 feat2prop(featurestr);
4683 name = featurestr;
4684
83a00f60 4685 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4686 warn_report("Ambiguous CPU model string. "
4687 "Don't mix both \"+%s\" and \"%s=%s\"",
4688 name, name, val);
83a00f60
EH		 4689 ambiguous = true;
4690 }
4691 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4692 warn_report("Ambiguous CPU model string. "
4693 "Don't mix both \"-%s\" and \"%s=%s\"",
4694 name, name, val);
83a00f60
EH		 4695 ambiguous = true;
4696 }
4697
f6750e95
EH		 4698 /* Special case: */
4699 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4700 int ret;
f46bfdbf 4701 uint64_t tsc_freq;
f6750e95 4702
f17fd4fd 4703 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4704 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4705 error_setg(errp, "bad numerical value %s", val);
4706 return;
4707 }
4708 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4709 val = num;
4710 name = "tsc-frequency";
c6dc6f63 4711 }
f6750e95 4712
62a48a2a
IM		 4713 prop = g_new0(typeof(*prop), 1);
4714 prop->driver = typename;
4715 prop->property = g_strdup(name);
4716 prop->value = g_strdup(val);
62a48a2a 4717 qdev_prop_register_global(prop);
f6750e95
EH		 4718 }
4719
83a00f60 4720 if (ambiguous) {
3dc6f869
AF		 4721 warn_report("Compatibility of ambiguous CPU model "
4722 "strings won't be kept on future QEMU versions");
83a00f60 4723 }
c6dc6f63
AP		 4724}
4725
245edd0c 4726static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4727
5a853fc5
EH		 4728/* Build a list with the name of all features on a feature word array */
4729static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 4730 strList **list)
5a853fc5 4731{
c3033fd3 4732 strList **tail = list;
5a853fc5 4733 FeatureWord w;
5a853fc5
EH		 4734
4735 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4736 uint64_t filtered = features[w];
5a853fc5 4737 int i;
ede146c2
PB		 4738 for (i = 0; i < 64; i++) {
4739 if (filtered & (1ULL << i)) {
c3033fd3 4740 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 4741 }
4742 }
4743 }
4744}
4745
506174bf
EH		 4746static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4747 const char *name, void *opaque,
4748 Error **errp)
4749{
4750 X86CPU *xc = X86_CPU(obj);
4751 strList *result = NULL;
4752
4753 x86_cpu_list_feature_names(xc->filtered_features, &result);
4754 visit_type_strList(v, "unavailable-features", &result, errp);
4755}
4756
b54c9377
EH		 4757/* Check for missing features that may prevent the CPU class from
4758 * running using the current machine and accelerator.
4759 */
4760static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
c3033fd3 4761 strList **list)
b54c9377 4762{
c3033fd3 4763 strList **tail = list;
b54c9377 4764 X86CPU *xc;
b54c9377 4765 Error *err = NULL;
b54c9377 4766
d6dcc558 4767 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
c3033fd3 4768 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
b54c9377
EH		 4769 return;
4770 }
4771
3c75e12e 4772 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4773
b8d834a0 4774 x86_cpu_expand_features(xc, &err);
b54c9377 4775 if (err) {
b8d834a0 4776 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4777 * but in case it does, just report the model as not
4778 * runnable at all using the "type" property.
4779 */
c3033fd3 4780 QAPI_LIST_APPEND(tail, g_strdup("type"));
3aa8203e 4781 error_free(err);
b54c9377
EH		 4782 }
4783
245edd0c 4784 x86_cpu_filter_features(xc, false);
b54c9377 4785
c3033fd3 4786 x86_cpu_list_feature_names(xc->filtered_features, tail);
b54c9377
EH		 4787
4788 object_unref(OBJECT(xc));
4789}
4790
8c3329e5 4791/* Print all cpuid feature names in featureset
c6dc6f63 4792 */
0442428a 4793static void listflags(GList *features)
0856579c 4794{
cc643b1e
DB		 4795 size_t len = 0;
4796 GList *tmp;
4797
4798 for (tmp = features; tmp; tmp = tmp->next) {
4799 const char *name = tmp->data;
4800 if ((len + strlen(name) + 1) >= 75) {
0442428a 4801 qemu_printf("\n");
cc643b1e 4802 len = 0;
c6dc6f63 4803 }
0442428a 4804 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4805 len += strlen(name) + 1;
8c3329e5 4806 }
0442428a 4807 qemu_printf("\n");
c6dc6f63
AP		 4808}
4809
f48c8837 4810/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4811static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4812{
4813 ObjectClass *class_a = (ObjectClass *)a;
4814 ObjectClass *class_b = (ObjectClass *)b;
4815 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4816 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4817 int ret;
ee465a3e 4818
f48c8837 4819 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4820 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4821 } else {
88703ce2
EH		 4822 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4823 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4824 ret = strcmp(name_a, name_b);
ee465a3e 4825 }
c7dbff4b 4826 return ret;
ee465a3e
EH		 4827}
4828
4829static GSList *get_sorted_cpu_model_list(void)
4830{
4831 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4832 list = g_slist_sort(list, x86_cpu_list_compare);
4833 return list;
4834}
4835
164e779c
EH		 4836static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4837{
3c75e12e 4838 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4839 char *r = object_property_get_str(obj, "model-id", &error_abort);
4840 object_unref(obj);
4841 return r;
4842}
4843
0788a56b
EH		 4844static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4845{
4846 X86CPUVersion version;
4847
4848 if (!cc->model || !cc->model->is_alias) {
4849 return NULL;
4850 }
4851 version = x86_cpu_model_resolve_version(cc->model);
4852 if (version <= 0) {
4853 return NULL;
4854 }
4855 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4856}
4857
ee465a3e
EH		 4858static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4859{
4860 ObjectClass *oc = data;
4861 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4862 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4863 g_autofree char *desc = g_strdup(cc->model_description);
4864 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4865 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4866
0788a56b
EH		 4867 if (!desc && alias_of) {
4868 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4869 desc = g_strdup("(alias configured by machine type)");
4870 } else {
4871 desc = g_strdup_printf("(alias of %s)", alias_of);
4872 }
4873 }
c63938df
TX		 4874 if (!desc && cc->model && cc->model->note) {
4875 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4876 }
164e779c 4877 if (!desc) {
c63938df 4878 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4879 }
4880
61848717 4881 qemu_printf("x86 %-20s %s\n", name, desc);
ee465a3e
EH		 4882}
4883
4884/* list available CPU models and flags */
0442428a 4885void x86_cpu_list(void)
c6dc6f63 4886{
cc643b1e 4887 int i, j;
ee465a3e 4888 GSList *list;
cc643b1e 4889 GList *names = NULL;
c6dc6f63 4890
0442428a 4891 qemu_printf("Available CPUs:\n");
ee465a3e 4892 list = get_sorted_cpu_model_list();
0442428a 4893 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4894 g_slist_free(list);
21ad7789 4895
cc643b1e 4896 names = NULL;
3af60be2
JK		 4897 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4898 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4899 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4900 if (fw->feat_names[j]) {
4901 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4902 }
4903 }
3af60be2 4904 }
cc643b1e
DB		 4905
4906 names = g_list_sort(names, (GCompareFunc)strcmp);
4907
0442428a
MA		 4908 qemu_printf("\nRecognized CPUID flags:\n");
4909 listflags(names);
4910 qemu_printf("\n");
cc643b1e 4911 g_list_free(names);
c6dc6f63
AP		 4912}
4913
ee465a3e
EH		 4914static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4915{
4916 ObjectClass *oc = data;
4917 X86CPUClass *cc = X86_CPU_CLASS(oc);
4918 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 4919 CpuDefinitionInfo *info;
4920
4921 info = g_malloc0(sizeof(*info));
4922 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4923 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4924 info->has_unavailable_features = true;
8ed877b7 4925 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4926 info->migration_safe = cc->migration_safe;
4927 info->has_migration_safe = true;
5adbed30 4928 info->q_static = cc->static_model;
61ad65d0
RH		 4929 if (cc->model && cc->model->cpudef->deprecation_note) {
4930 info->deprecated = true;
4931 } else {
4932 info->deprecated = false;
4933 }
0788a56b
EH		 4934 /*
4935 * Old machine types won't report aliases, so that alias translation
4936 * doesn't break compatibility with previous QEMU versions.
4937 */
4938 if (default_cpu_version != CPU_VERSION_LEGACY) {
4939 info->alias_of = x86_cpu_class_get_alias_of(cc);
4940 info->has_alias_of = !!info->alias_of;
4941 }
ee465a3e 4942
54aa3de7 4943 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 4944}
4945
25a9d6ca 4946CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4947{
4948 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4949 GSList *list = get_sorted_cpu_model_list();
4950 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4951 g_slist_free(list);
e3966126
AL		 4952 return cpu_list;
4953}
4954
ede146c2 4955static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
84f1b92f 4956 bool migratable_only)
27418adf
EH		 4957{
4958 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4959 uint64_t r = 0;
27418adf 4960
fefb41bf 4961 if (kvm_enabled()) {
07585923
RH		 4962 switch (wi->type) {
4963 case CPUID_FEATURE_WORD:
4964 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4965 wi->cpuid.ecx,
4966 wi->cpuid.reg);
4967 break;
4968 case MSR_FEATURE_WORD:
d86f9636
RH		 4969 r = kvm_arch_get_supported_msr_feature(kvm_state,
4970 wi->msr.index);
07585923
RH		 4971 break;
4972 }
d6dcc558 4973 } else if (hvf_enabled()) {
07585923
RH		 4974 if (wi->type != CPUID_FEATURE_WORD) {
4975 return 0;
4976 }
4977 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4978 wi->cpuid.ecx,
4979 wi->cpuid.reg);
fefb41bf 4980 } else if (tcg_enabled()) {
84f1b92f 4981 r = wi->tcg_features;
fefb41bf
EH		 4982 } else {
4983 return ~0;
4984 }
5ea9e9e2
PB		 4985#ifndef TARGET_X86_64
4986 if (w == FEAT_8000_0001_EDX) {
4987 r &= ~CPUID_EXT2_LM;
4988 }
4989#endif
84f1b92f
EH		 4990 if (migratable_only) {
4991 r &= x86_cpu_get_migratable_flags(w);
4992 }
4993 return r;
27418adf
EH		 4994}
4995
5b8978d8
CF		 4996/*
4997 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
4998 */
f5cc5a5c 4999void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5000{
5001 PropValue *pv;
5002 for (pv = props; pv->prop; pv++) {
5003 if (!pv->value) {
5004 continue;
5005 }
5325cc34 5006 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5007 &error_abort);
5008 }
5009}
5010
5b8978d8
CF		 5011/*
5012 * Apply properties for the CPU model version specified in model.
5013 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5014 */
5015
dcafd1ef
EH		 5016static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5017{
5018 const X86CPUVersionDefinition *vdef;
5019 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5020
5021 if (version == CPU_VERSION_LEGACY) {
5022 return;
5023 }
5024
5025 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5026 PropValue *p;
5027
5028 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5029 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5030 &error_abort);
5031 }
5032
5033 if (vdef->version == version) {
5034 break;
5035 }
5036 }
5037
5038 /*
5039 * If we reached the end of the list, version number was invalid
5040 */
5041 assert(vdef->version == version);
5042}
5043
5b8978d8
CF		 5044/*
5045 * Load data from X86CPUDefinition into a X86CPU object.
5046 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 5047 */
49e2fa85 5048static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5049{
e11fd689 5050 const X86CPUDefinition *def = model->cpudef;
61dcd775 5051 CPUX86State *env = &cpu->env;
e1c224b4 5052 FeatureWord w;
c6dc6f63 5053
f99fd7ca
EH		 5054 /*NOTE: any property set by this function should be returned by
5055 * x86_cpu_static_props(), so static expansion of
5056 * query-cpu-model-expansion is always complete.
5057 */
5058
c39c0edf 5059 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5060 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5061 &error_abort);
5325cc34 5062 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5063 &error_abort);
5064
5325cc34
MA		 5065 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5066 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5067 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5068 &error_abort);
5325cc34 5069 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5070 &error_abort);
e1c224b4
EH		 5071 for (w = 0; w < FEATURE_WORDS; w++) {
5072 env->features[w] = def->features[w];
5073 }
82beb536 5074
a9f27ea9
EH		 5075 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5076 cpu->legacy_cache = !def->cache_info;
ab8f992e 5077
82beb536 5078 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5079
5080 /* sysenter isn't supported in compatibility mode on AMD,
5081 * syscall isn't supported in compatibility mode on Intel.
5082 * Normally we advertise the actual CPU vendor, but you can
5083 * override this using the 'vendor' property if you want to use
5084 * KVM's sysenter/syscall emulation in compatibility mode and
5085 * when doing cross vendor migration
5086 */
7c08db30 5087
f5cc5a5c
CF		 5088 /*
5089 * vendor property is set here but then overloaded with the
5090 * host cpu vendor for KVM and HVF.
5091 */
5092 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5093
dcafd1ef 5094 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5095
5096 /*
5097 * Properties in versioned CPU model are not user specified features.
5098 * We can simply clear env->user_features here since it will be filled later
5099 * in x86_cpu_expand_features() based on plus_features and minus_features.
5100 */
5101 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5102}
5103
00fcd100
AB		 5104static gchar *x86_gdb_arch_name(CPUState *cs)
5105{
5106#ifdef TARGET_X86_64
5107 return g_strdup("i386:x86-64");
5108#else
5109 return g_strdup("i386");
5110#endif
5111}
5112
d940ee9b
EH		 5113static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5114{
dcafd1ef 5115 X86CPUModel *model = data;
d940ee9b 5116 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5117 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5118
dcafd1ef 5119 xcc->model = model;
bd72159d 5120 xcc->migration_safe = true;
61ad65d0 5121 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5122}
5123
dcafd1ef 5124static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5125{
88703ce2 5126 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5127 TypeInfo ti = {
5128 .name = typename,
5129 .parent = TYPE_X86_CPU,
5130 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5131 .class_data = model,
d940ee9b
EH		 5132 };
5133
dcafd1ef 5134 type_register(&ti);
dcafd1ef
EH		 5135}
5136
5b8978d8
CF		 5137
5138/*
5139 * register builtin_x86_defs;
5140 * "max", "base" and subclasses ("host") are not registered here.
5141 * See x86_cpu_register_types for all model registrations.
5142 */
e11fd689 5143static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5144{
5145 X86CPUModel *m;
5146 const X86CPUVersionDefinition *vdef;
dcafd1ef 5147
2a923a29
EH		 5148 /* AMD aliases are handled at runtime based on CPUID vendor, so
5149 * they shouldn't be set on the CPU model table.
5150 */
5151 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5152 /* catch mistakes instead of silently truncating model_id when too long */
5153 assert(def->model_id && strlen(def->model_id) <= 48);
5154
dcafd1ef
EH		 5155 /* Unversioned model: */
5156 m = g_new0(X86CPUModel, 1);
5157 m->cpudef = def;
0788a56b
EH		 5158 m->version = CPU_VERSION_AUTO;
5159 m->is_alias = true;
dcafd1ef
EH		 5160 x86_register_cpu_model_type(def->name, m);
5161
5162 /* Versioned models: */
5163
5164 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5165 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5166 g_autofree char *name =
5167 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5168 m->cpudef = def;
5169 m->version = vdef->version;
c63938df 5170 m->note = vdef->note;
dcafd1ef 5171 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5172
5173 if (vdef->alias) {
5174 X86CPUModel *am = g_new0(X86CPUModel, 1);
5175 am->cpudef = def;
5176 am->version = vdef->version;
0788a56b 5177 am->is_alias = true;
53db89d9
EH		 5178 x86_register_cpu_model_type(vdef->alias, am);
5179 }
dcafd1ef 5180 }
2a923a29 5181
d940ee9b
EH		 5182}
5183
97afb47e
LL		 5184uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
5185{
5186 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5187 return 57; /* 57 bits virtual */
5188 } else {
5189 return 48; /* 48 bits virtual */
5190 }
5191}
5192
c6dc6f63
AP		 5193void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5194 uint32_t *eax, uint32_t *ebx,
5195 uint32_t *ecx, uint32_t *edx)
5196{
6aa9e42f
RH		 5197 X86CPU *cpu = env_archcpu(env);
5198 CPUState *cs = env_cpu(env);
d65af288 5199 uint32_t die_offset;
4ed3d478 5200 uint32_t limit;
1ce36bfe 5201 uint32_t signature[3];
f20dec0b
BM		 5202 X86CPUTopoInfo topo_info;
5203
5204 topo_info.dies_per_pkg = env->nr_dies;
5205 topo_info.cores_per_die = cs->nr_cores;
5206 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5207
4ed3d478
DB		 5208 /* Calculate & apply limits for different index ranges */
5209 if (index >= 0xC0000000) {
5210 limit = env->cpuid_xlevel2;
5211 } else if (index >= 0x80000000) {
5212 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5213 } else if (index >= 0x40000000) {
5214 limit = 0x40000001;
c6dc6f63 5215 } else {
4ed3d478
DB		 5216 limit = env->cpuid_level;
5217 }
5218
5219 if (index > limit) {
5220 /* Intel documentation states that invalid EAX input will
5221 * return the same information as EAX=cpuid_level
5222 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5223 */
5224 index = env->cpuid_level;
c6dc6f63
AP		 5225 }
5226
5227 switch(index) {
5228 case 0:
5229 *eax = env->cpuid_level;
5eb2f7a4
EH		 5230 *ebx = env->cpuid_vendor1;
5231 *edx = env->cpuid_vendor2;
5232 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5233 break;
5234 case 1:
5235 *eax = env->cpuid_version;
7e72a45c
EH		 5236 *ebx = (cpu->apic_id << 24) |
5237 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5238 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5239 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5240 *ecx |= CPUID_EXT_OSXSAVE;
5241 }
0514ef2f 5242 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5243 if (cs->nr_cores * cs->nr_threads > 1) {
5244 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5245 *edx |= CPUID_HT;
c6dc6f63 5246 }
ea39f9b6
LX		 5247 if (!cpu->enable_pmu) {
5248 *ecx &= ~CPUID_EXT_PDCM;
5249 }
c6dc6f63
AP		 5250 break;
5251 case 2:
5252 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 5253 if (cpu->cache_info_passthrough) {
5254 host_cpuid(index, 0, eax, ebx, ecx, edx);
5255 break;
a7a0da84
MR		 5256 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5257 *eax = *ebx = *ecx = *edx = 0;
5258 break;
787aaf57 5259 }
5e891bf8 5260 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5261 *ebx = 0;
14c985cf
LM		 5262 if (!cpu->enable_l3_cache) {
5263 *ecx = 0;
5264 } else {
a9f27ea9 5265 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5266 }
a9f27ea9
EH		 5267 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5268 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5269 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5270 break;
5271 case 4:
5272 /* cache info: needed for Core compatibility */
787aaf57
BC		 5273 if (cpu->cache_info_passthrough) {
5274 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5275 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5276 *eax &= ~0xFC000000;
7e3482f8
EH		 5277 if ((*eax & 31) && cs->nr_cores > 1) {
5278 *eax |= (cs->nr_cores - 1) << 26;
5279 }
a7a0da84
MR		 5280 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5281 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5282 } else {
2f7a21c4 5283 *eax = 0;
76c2975a 5284 switch (count) {
c6dc6f63 5285 case 0: /* L1 dcache info */
a9f27ea9
EH		 5286 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5287 1, cs->nr_cores,
7e3482f8 5288 eax, ebx, ecx, edx);
c6dc6f63
AP		 5289 break;
5290 case 1: /* L1 icache info */
a9f27ea9
EH		 5291 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5292 1, cs->nr_cores,
7e3482f8 5293 eax, ebx, ecx, edx);
c6dc6f63
AP		 5294 break;
5295 case 2: /* L2 cache info */
a9f27ea9
EH		 5296 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5297 cs->nr_threads, cs->nr_cores,
7e3482f8 5298 eax, ebx, ecx, edx);
c6dc6f63 5299 break;
14c985cf 5300 case 3: /* L3 cache info */
f20dec0b 5301 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5302 if (cpu->enable_l3_cache) {
a9f27ea9 5303 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5304 (1 << die_offset), cs->nr_cores,
7e3482f8 5305 eax, ebx, ecx, edx);
14c985cf
LM		 5306 break;
5307 }
7e3482f8 5308 /* fall through */
c6dc6f63 5309 default: /* end of info */
7e3482f8 5310 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5311 break;
76c2975a
PB		 5312 }
5313 }
c6dc6f63
AP		 5314 break;
5315 case 5:
2266d443
MT		 5316 /* MONITOR/MWAIT Leaf */
5317 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5318 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5319 *ecx = cpu->mwait.ecx; /* flags */
5320 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5321 break;
5322 case 6:
5323 /* Thermal and Power Leaf */
28b8e4d0 5324 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5325 *ebx = 0;
5326 *ecx = 0;
5327 *edx = 0;
5328 break;
f7911686 5329 case 7:
13526728
EH		 5330 /* Structured Extended Feature Flags Enumeration Leaf */
5331 if (count == 0) {
80db491d
JL		 5332 /* Maximum ECX value for sub-leaves */
5333 *eax = env->cpuid_level_func7;
0514ef2f 5334 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5335 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5336 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5337 *ecx |= CPUID_7_0_ECX_OSPKE;
5338 }
95ea69fb 5339 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 5340
5341 /*
5342 * SGX cannot be emulated in software. If hardware does not
5343 * support enabling SGX and/or SGX flexible launch control,
5344 * then we need to update the VM's CPUID values accordingly.
5345 */
5346 if ((*ebx & CPUID_7_0_EBX_SGX) &&
5347 (!kvm_enabled() ||
5348 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) &
5349 CPUID_7_0_EBX_SGX))) {
5350 *ebx &= ~CPUID_7_0_EBX_SGX;
5351 }
5352
5353 if ((*ecx & CPUID_7_0_ECX_SGX_LC) &&
5354 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() ||
5355 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) &
5356 CPUID_7_0_ECX_SGX_LC))) {
5357 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
5358 }
80db491d
JL		 5359 } else if (count == 1) {
5360 *eax = env->features[FEAT_7_1_EAX];
5361 *ebx = 0;
5362 *ecx = 0;
5363 *edx = 0;
f7911686
YW		 5364 } else {
5365 *eax = 0;
5366 *ebx = 0;
5367 *ecx = 0;
5368 *edx = 0;
5369 }
5370 break;
c6dc6f63
AP		 5371 case 9:
5372 /* Direct Cache Access Information Leaf */
5373 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5374 *ebx = 0;
5375 *ecx = 0;
5376 *edx = 0;
5377 break;
5378 case 0xA:
5379 /* Architectural Performance Monitoring Leaf */
9337e3b6 5380 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5381 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5382
5383 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5384 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5385 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5386 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5387 } else if (hvf_enabled() && cpu->enable_pmu) {
5388 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5389 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5390 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5391 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5392 } else {
5393 *eax = 0;
5394 *ebx = 0;
5395 *ecx = 0;
5396 *edx = 0;
5397 }
c6dc6f63 5398 break;
5232d00a
RK		 5399 case 0xB:
5400 /* Extended Topology Enumeration Leaf */
5401 if (!cpu->enable_cpuid_0xb) {
5402 *eax = *ebx = *ecx = *edx = 0;
5403 break;
5404 }
5405
5406 *ecx = count & 0xff;
5407 *edx = cpu->apic_id;
5408
5409 switch (count) {
5410 case 0:
f20dec0b 5411 *eax = apicid_core_offset(&topo_info);
eab60fb9 5412 *ebx = cs->nr_threads;
5232d00a
RK		 5413 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5414 break;
5415 case 1:
fb49865d 5416 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5417 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5418 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5419 break;
5420 default:
5421 *eax = 0;
5422 *ebx = 0;
5423 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5424 }
5425
a94e1428
LX		 5426 assert(!(*eax & ~0x1f));
5427 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5428 break;
5429 case 0x1F:
5430 /* V2 Extended Topology Enumeration Leaf */
5431 if (env->nr_dies < 2) {
5432 *eax = *ebx = *ecx = *edx = 0;
5433 break;
5434 }
5435
5436 *ecx = count & 0xff;
5437 *edx = cpu->apic_id;
5438 switch (count) {
5439 case 0:
f20dec0b 5440 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5441 *ebx = cs->nr_threads;
5442 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5443 break;
5444 case 1:
f20dec0b 5445 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5446 *ebx = cs->nr_cores * cs->nr_threads;
5447 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5448 break;
5449 case 2:
fb49865d 5450 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5451 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5452 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5453 break;
5454 default:
5455 *eax = 0;
5456 *ebx = 0;
5457 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5458 }
5232d00a
RK		 5459 assert(!(*eax & ~0x1f));
5460 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5461 break;
2560f19f 5462 case 0xD: {
51e49430 5463 /* Processor Extended State */
2560f19f
PB		 5464 *eax = 0;
5465 *ebx = 0;
5466 *ecx = 0;
5467 *edx = 0;
19dc85db 5468 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5469 break;
5470 }
4928cd6d 5471
2560f19f 5472 if (count == 0) {
96193c22
EH		 5473 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5474 *eax = env->features[FEAT_XSAVE_COMP_LO];
5475 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5476 /*
5477 * The initial value of xcr0 and ebx == 0, On host without kvm
5478 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5479 * even through guest update xcr0, this will crash some legacy guest
5480 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5481 */
5482 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5483 } else if (count == 1) {
0bb0b2d2 5484 *eax = env->features[FEAT_XSAVE];
f4f1110e 5485 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5486 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5487 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5488 *eax = esa->size;
5489 *ebx = esa->offset;
2560f19f 5490 }
51e49430
SY		 5491 }
5492 break;
2560f19f 5493 }
1dec2e1f
SC		 5494 case 0x12:
5495#ifndef CONFIG_USER_ONLY
5496 if (!kvm_enabled() ||
5497 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
5498 *eax = *ebx = *ecx = *edx = 0;
5499 break;
5500 }
5501
5502 /*
5503 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
5504 * the EPC properties, e.g. confidentiality and integrity, from the
5505 * host's first EPC section, i.e. assume there is one EPC section or
5506 * that all EPC sections have the same security properties.
5507 */
5508 if (count > 1) {
5509 uint64_t epc_addr, epc_size;
5510
5511 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
5512 *eax = *ebx = *ecx = *edx = 0;
5513 break;
5514 }
5515 host_cpuid(index, 2, eax, ebx, ecx, edx);
5516 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
5517 *ebx = (uint32_t)(epc_addr >> 32);
5518 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
5519 *edx = (uint32_t)(epc_size >> 32);
5520 break;
5521 }
5522
5523 /*
5524 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
5525 * and KVM, i.e. QEMU cannot emulate features to override what KVM
5526 * supports. Features can be further restricted by userspace, but not
5527 * made more permissive.
5528 */
5529 *eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EAX);
5530 *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EBX);
5531 *ecx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_ECX);
5532 *edx = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x12, count, R_EDX);
5533
5534 if (count == 0) {
5535 *eax &= env->features[FEAT_SGX_12_0_EAX];
5536 *ebx &= env->features[FEAT_SGX_12_0_EBX];
5537 } else {
5538 *eax &= env->features[FEAT_SGX_12_1_EAX];
5539 *ebx &= 0; /* ebx reserve */
5540 *ecx &= env->features[FEAT_XSAVE_COMP_LO];
5541 *edx &= env->features[FEAT_XSAVE_COMP_HI];
5542
5543 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
5544 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
5545
5546 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 5547 if ((*eax & (1U << 4)) &&
5548 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
5549 *eax &= ~(1U << 4);
5550 }
1dec2e1f
SC		 5551 }
5552#endif
5553 break;
e37a5c7f
CP		 5554 case 0x14: {
5555 /* Intel Processor Trace Enumeration */
5556 *eax = 0;
5557 *ebx = 0;
5558 *ecx = 0;
5559 *edx = 0;
5560 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5561 !kvm_enabled()) {
5562 break;
5563 }
5564
5565 if (count == 0) {
5566 *eax = INTEL_PT_MAX_SUBLEAF;
5567 *ebx = INTEL_PT_MINIMAL_EBX;
5568 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 5569 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5570 *ecx |= CPUID_14_0_ECX_LIP;
5571 }
e37a5c7f
CP		 5572 } else if (count == 1) {
5573 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5574 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5575 }
5576 break;
5577 }
1ce36bfe
DB		 5578 case 0x40000000:
5579 /*
5580 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5581 * set here, but we restrict to TCG none the less.
5582 */
5583 if (tcg_enabled() && cpu->expose_tcg) {
5584 memcpy(signature, "TCGTCGTCGTCG", 12);
5585 *eax = 0x40000001;
5586 *ebx = signature[0];
5587 *ecx = signature[1];
5588 *edx = signature[2];
5589 } else {
5590 *eax = 0;
5591 *ebx = 0;
5592 *ecx = 0;
5593 *edx = 0;
5594 }
5595 break;
5596 case 0x40000001:
5597 *eax = 0;
5598 *ebx = 0;
5599 *ecx = 0;
5600 *edx = 0;
5601 break;
c6dc6f63
AP		 5602 case 0x80000000:
5603 *eax = env->cpuid_xlevel;
5604 *ebx = env->cpuid_vendor1;
5605 *edx = env->cpuid_vendor2;
5606 *ecx = env->cpuid_vendor3;
5607 break;
5608 case 0x80000001:
5609 *eax = env->cpuid_version;
5610 *ebx = 0;
0514ef2f
EH		 5611 *ecx = env->features[FEAT_8000_0001_ECX];
5612 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5613
5614 /* The Linux kernel checks for the CMPLegacy bit and
5615 * discards multiple thread information if it is set.
cb8d4c8f 5616 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5617 */
ce3960eb 5618 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5619 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5620 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5621 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5622 *ecx |= 1 << 1; /* CmpLegacy bit */
5623 }
5624 }
c6dc6f63
AP		 5625 break;
5626 case 0x80000002:
5627 case 0x80000003:
5628 case 0x80000004:
5629 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5630 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5631 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5632 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5633 break;
5634 case 0x80000005:
5635 /* cache info (L1 cache) */
787aaf57
BC		 5636 if (cpu->cache_info_passthrough) {
5637 host_cpuid(index, 0, eax, ebx, ecx, edx);
5638 break;
5639 }
78ee6bd0 5640 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5641 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5642 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5643 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5644 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5645 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5646 break;
5647 case 0x80000006:
5648 /* cache info (L2 cache) */
787aaf57
BC		 5649 if (cpu->cache_info_passthrough) {
5650 host_cpuid(index, 0, eax, ebx, ecx, edx);
5651 break;
5652 }
78ee6bd0
PMD		 5653 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5654 (L2_DTLB_2M_ENTRIES << 16) |
5655 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5656 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5657 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5658 (L2_DTLB_4K_ENTRIES << 16) |
5659 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5660 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5661 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5662 cpu->enable_l3_cache ?
5663 env->cache_info_amd.l3_cache : NULL,
5664 ecx, edx);
c6dc6f63 5665 break;
303752a9
MT		 5666 case 0x80000007:
5667 *eax = 0;
5668 *ebx = 0;
5669 *ecx = 0;
5670 *edx = env->features[FEAT_8000_0007_EDX];
5671 break;
c6dc6f63
AP		 5672 case 0x80000008:
5673 /* virtual & phys address size in low 2 bytes. */
97afb47e 5674 *eax = cpu->phys_bits;
0514ef2f 5675 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 5676 /* 64 bit processor */
97afb47e 5677 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
c6dc6f63 5678 }
1b3420e1 5679 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5680 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5681 /*
5682 * Bits 15:12 is "The number of bits in the initial
5683 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 5684 * thread ID within a package".
cac9edfc
BM		 5685 * Bits 7:0 is "The number of threads in the package is NC+1"
5686 */
fb49865d 5687 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 5688 ((cs->nr_cores * cs->nr_threads) - 1);
5689 } else {
5690 *ecx = 0;
c6dc6f63 5691 }
cac9edfc 5692 *edx = 0;
c6dc6f63
AP		 5693 break;
5694 case 0x8000000A:
0514ef2f 5695 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5696 *eax = 0x00000001; /* SVM Revision */
5697 *ebx = 0x00000010; /* nr of ASIDs */
5698 *ecx = 0;
0514ef2f 5699 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5700 } else {
5701 *eax = 0;
5702 *ebx = 0;
5703 *ecx = 0;
5704 *edx = 0;
5705 }
c6dc6f63 5706 break;
8f4202fb
BM		 5707 case 0x8000001D:
5708 *eax = 0;
a4e0b436
SL		 5709 if (cpu->cache_info_passthrough) {
5710 host_cpuid(index, count, eax, ebx, ecx, edx);
5711 break;
5712 }
8f4202fb
BM		 5713 switch (count) {
5714 case 0: /* L1 dcache info */
2f084d1e
BM		 5715 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5716 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5717 break;
5718 case 1: /* L1 icache info */
2f084d1e
BM		 5719 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5720 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5721 break;
5722 case 2: /* L2 cache info */
2f084d1e
BM		 5723 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5724 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5725 break;
5726 case 3: /* L3 cache info */
2f084d1e
BM		 5727 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5728 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5729 break;
5730 default: /* end of info */
5731 *eax = *ebx = *ecx = *edx = 0;
5732 break;
5733 }
5734 break;
ed78467a 5735 case 0x8000001E:
35ac5dfb
BM		 5736 if (cpu->core_id <= 255) {
5737 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5738 } else {
5739 *eax = 0;
5740 *ebx = 0;
5741 *ecx = 0;
5742 *edx = 0;
5743 }
ed78467a 5744 break;
b3baa152
BW		 5745 case 0xC0000000:
5746 *eax = env->cpuid_xlevel2;
5747 *ebx = 0;
5748 *ecx = 0;
5749 *edx = 0;
5750 break;
5751 case 0xC0000001:
5752 /* Support for VIA CPU's CPUID instruction */
5753 *eax = env->cpuid_version;
5754 *ebx = 0;
5755 *ecx = 0;
0514ef2f 5756 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5757 break;
5758 case 0xC0000002:
5759 case 0xC0000003:
5760 case 0xC0000004:
5761 /* Reserved for the future, and now filled with zero */
5762 *eax = 0;
5763 *ebx = 0;
5764 *ecx = 0;
5765 *edx = 0;
5766 break;
6cb8f2a6 5767 case 0x8000001F:
02eacf31
PMD		 5768 *eax = *ebx = *ecx = *edx = 0;
5769 if (sev_enabled()) {
5770 *eax = 0x2;
5771 *eax |= sev_es_enabled() ? 0x8 : 0;
5772 *ebx = sev_get_cbit_position();
5773 *ebx |= sev_get_reduced_phys_bits() << 6;
5774 }
6cb8f2a6 5775 break;
c6dc6f63
AP		 5776 default:
5777 /* reserved values: zero */
5778 *eax = 0;
5779 *ebx = 0;
5780 *ecx = 0;
5781 *edx = 0;
5782 break;
5783 }
5784}
5fd2087a 5785
db888065
SC		 5786static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
5787{
5788#ifndef CONFIG_USER_ONLY
5789 /* Those default values are defined in Skylake HW */
5790 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
5791 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
5792 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
5793 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
5794#endif
5795}
5796
781c67ca 5797static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5798{
781c67ca 5799 CPUState *s = CPU(dev);
5fd2087a
AF		 5800 X86CPU *cpu = X86_CPU(s);
5801 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5802 CPUX86State *env = &cpu->env;
a114d25d
RH		 5803 target_ulong cr4;
5804 uint64_t xcr0;
c1958aea
AF		 5805 int i;
5806
781c67ca 5807 xcc->parent_reset(dev);
5fd2087a 5808
5e992a8e 5809 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5810
c1958aea
AF		 5811 env->old_exception = -1;
5812
5813 /* init to reset state */
e3126a5c 5814 env->int_ctl = 0;
c1958aea 5815 env->hflags2 |= HF2_GIF_MASK;
b67e2796 5816 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 5817 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 5818
5819 cpu_x86_update_cr0(env, 0x60000010);
5820 env->a20_mask = ~0x0;
5821 env->smbase = 0x30000;
e13713db 5822 env->msr_smi_count = 0;
c1958aea
AF		 5823
5824 env->idt.limit = 0xffff;
5825 env->gdt.limit = 0xffff;
5826 env->ldt.limit = 0xffff;
5827 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5828 env->tr.limit = 0xffff;
5829 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5830
5831 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5832 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5833 DESC_R_MASK | DESC_A_MASK);
5834 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5835 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5836 DESC_A_MASK);
5837 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5838 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5839 DESC_A_MASK);
5840 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5841 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5842 DESC_A_MASK);
5843 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5844 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5845 DESC_A_MASK);
5846 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5847 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5848 DESC_A_MASK);
5849
5850 env->eip = 0xfff0;
5851 env->regs[R_EDX] = env->cpuid_version;
5852
5853 env->eflags = 0x2;
5854
5855 /* FPU init */
5856 for (i = 0; i < 8; i++) {
5857 env->fptags[i] = 1;
5858 }
5bde1407 5859 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5860
5861 env->mxcsr = 0x1f80;
a114d25d
RH		 5862 /* All units are in INIT state. */
5863 env->xstate_bv = 0;
c1958aea
AF		 5864
5865 env->pat = 0x0007040600070406ULL;
5866 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5867 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5868 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5869 }
c1958aea
AF		 5870
5871 memset(env->dr, 0, sizeof(env->dr));
5872 env->dr[6] = DR6_FIXED_1;
5873 env->dr[7] = DR7_FIXED_1;
b3310ab3 5874 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5875 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5876
a114d25d 5877 cr4 = 0;
cfc3b074 5878 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5879
5880#ifdef CONFIG_USER_ONLY
5881 /* Enable all the features for user-mode. */
5882 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5883 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5884 }
0f70ed47
PB		 5885 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5886 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 5887 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5888 xcr0 |= 1ull << i;
5889 }
a114d25d 5890 }
0f70ed47 5891
a114d25d
RH		 5892 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5893 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5894 }
07929f2a
RH		 5895 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5896 cr4 |= CR4_FSGSBASE_MASK;
5897 }
a114d25d
RH		 5898#endif
5899
5900 env->xcr0 = xcr0;
5901 cpu_x86_update_cr4(env, cr4);
0522604b 5902
9db2efd9
AW		 5903 /*
5904 * SDM 11.11.5 requires:
5905 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5906 * - IA32_MTRR_PHYSMASKn.V = 0
5907 * All other bits are undefined. For simplification, zero it all.
5908 */
5909 env->mtrr_deftype = 0;
5910 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5911 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5912
b7394c83 5913 env->interrupt_injected = -1;
fd13f23b
LA		 5914 env->exception_nr = -1;
5915 env->exception_pending = 0;
5916 env->exception_injected = 0;
5917 env->exception_has_payload = false;
5918 env->exception_payload = 0;
b7394c83 5919 env->nmi_injected = false;
dd673288
IM		 5920#if !defined(CONFIG_USER_ONLY)
5921 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 5922 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 5923
259186a7 5924 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 5925
5926 if (kvm_enabled()) {
5927 kvm_arch_reset_vcpu(cpu);
5928 }
db888065
SC		 5929
5930 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862
ML		 5931
5932 if (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE) {
5933 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
5934 }
5935
dd673288 5936#endif
5fd2087a
AF		 5937}
5938
de024815
AF		 5939static void mce_init(X86CPU *cpu)
5940{
5941 CPUX86State *cenv = &cpu->env;
5942 unsigned int bank;
5943
5944 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 5945 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 5946 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 5947 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
5948 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 5949 cenv->mcg_ctl = ~(uint64_t)0;
5950 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
5951 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
5952 }
5953 }
5954}
5955
c39c0edf
EH		 5956static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
5957{
5958 if (*min < value) {
5959 *min = value;
5960 }
5961}
5962
5963/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
5964static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
5965{
5966 CPUX86State *env = &cpu->env;
5967 FeatureWordInfo *fi = &feature_word_info[w];
07585923 5968 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 5969 uint32_t region = eax & 0xF0000000;
5970
07585923 5971 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 5972 if (!env->features[w]) {
5973 return;
5974 }
5975
5976 switch (region) {
5977 case 0x00000000:
5978 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
5979 break;
5980 case 0x80000000:
5981 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
5982 break;
5983 case 0xC0000000:
5984 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
5985 break;
5986 }
80db491d
JL		 5987
5988 if (eax == 7) {
5989 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
5990 fi->cpuid.ecx);
5991 }
c39c0edf
EH		 5992}
5993
2ca8a8be
EH		 5994/* Calculate XSAVE components based on the configured CPU feature flags */
5995static void x86_cpu_enable_xsave_components(X86CPU *cpu)
5996{
5997 CPUX86State *env = &cpu->env;
5998 int i;
96193c22 5999 uint64_t mask;
2ca8a8be
EH		 6000
6001 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
19ca8285
XL		 6002 env->features[FEAT_XSAVE_COMP_LO] = 0;
6003 env->features[FEAT_XSAVE_COMP_HI] = 0;
2ca8a8be
EH		 6004 return;
6005 }
6006
e3c9022b
EH		 6007 mask = 0;
6008 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6009 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6010 if (env->features[esa->feature] & esa->bits) {
96193c22 6011 mask |= (1ULL << i);
2ca8a8be
EH		 6012 }
6013 }
6014
96193c22
EH		 6015 env->features[FEAT_XSAVE_COMP_LO] = mask;
6016 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 6017}
6018
b8d834a0
EH		 6019/***** Steps involved on loading and filtering CPUID data
6020 *
6021 * When initializing and realizing a CPU object, the steps
6022 * involved in setting up CPUID data are:
6023 *
6024 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6025 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6026 * transparent, as it is done automatically by instance_init.
6027 * No code should need to look at X86CPUDefinition structs
6028 * outside instance_init.
6029 *
6030 * 2) CPU expansion. This is done by realize before CPUID
6031 * filtering, and will make sure host/accelerator data is
6032 * loaded for CPU models that depend on host capabilities
6033 * (e.g. "host"). Done by x86_cpu_expand_features().
6034 *
6035 * 3) CPUID filtering. This initializes extra data related to
6036 * CPUID, and checks if the host supports all capabilities
6037 * required by the CPU. Runnability of a CPU model is
6038 * determined at this step. Done by x86_cpu_filter_features().
6039 *
6040 * Some operations don't require all steps to be performed.
6041 * More precisely:
6042 *
6043 * - CPU instance creation (instance_init) will run only CPU
6044 * model loading. CPU expansion can't run at instance_init-time
6045 * because host/accelerator data may be not available yet.
6046 * - CPU realization will perform both CPU model expansion and CPUID
6047 * filtering, and return an error in case one of them fails.
6048 * - query-cpu-definitions needs to run all 3 steps. It needs
6049 * to run CPUID filtering, as the 'unavailable-features'
6050 * field is set based on the filtering results.
6051 * - The query-cpu-model-expansion QMP command only needs to run
6052 * CPU model loading and CPU expansion. It should not filter
6053 * any CPUID data based on host capabilities.
6054 */
6055
6056/* Expand CPU configuration data, based on configured features
6057 * and host/accelerator capabilities when appropriate.
6058 */
79f1a68a 6059void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6060{
b34d12d1 6061 CPUX86State *env = &cpu->env;
dc15c051 6062 FeatureWord w;
99e24dbd 6063 int i;
2fae0d96 6064 GList *l;
9886e834 6065
99e24dbd
PB		 6066 for (l = plus_features; l; l = l->next) {
6067 const char *prop = l->data;
992861fb
MA		 6068 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6069 return;
99e24dbd
PB		 6070 }
6071 }
6072
6073 for (l = minus_features; l; l = l->next) {
6074 const char *prop = l->data;
992861fb
MA		 6075 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6076 return;
99e24dbd
PB		 6077 }
6078 }
6079
d4a606b3
EH		 6080 /*TODO: Now cpu->max_features doesn't overwrite features
6081 * set using QOM properties, and we can convert
dc15c051
IM		 6082 * plus_features & minus_features to global properties
6083 * inside x86_cpu_parse_featurestr() too.
6084 */
44bd8e53 6085 if (cpu->max_features) {
dc15c051 6086 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6087 /* Override only features that weren't set explicitly
6088 * by the user.
6089 */
6090 env->features[w] |=
6091 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 6092 ~env->user_features[w] &
0d914f39 6093 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6094 }
6095 }
6096
99e24dbd
PB		 6097 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6098 FeatureDep *d = &feature_dependencies[i];
6099 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6100 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6101
99e24dbd
PB		 6102 /* Not an error unless the dependent feature was added explicitly. */
6103 mark_unavailable_features(cpu, d->to.index,
6104 unavailable_features & env->user_features[d->to.index],
6105 "This feature depends on other features that were not requested");
6106
99e24dbd 6107 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6108 }
dc15c051
IM		 6109 }
6110
aec661de
EH		 6111 if (!kvm_enabled() || !cpu->expose_kvm) {
6112 env->features[FEAT_KVM] = 0;
6113 }
6114
2ca8a8be 6115 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6116
6117 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6118 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6119 if (cpu->full_cpuid_auto_level) {
6120 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6121 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6122 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6123 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6124 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6125 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6126 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6127 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6128 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6129 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6130 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6131 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6132
6133 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6134 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6135 if (cpu->intel_pt_auto_level) {
6136 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6137 } else if (cpu->env.cpuid_min_level < 0x14) {
6138 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6139 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 6140 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 6141 }
f24c3a79
LK		 6142 }
6143
760746ac
ZP		 6144 /*
6145 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6146 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6147 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6148 * cpu->vendor_cpuid_only has been unset for compatibility with older
6149 * machine types.
6150 */
6151 if ((env->nr_dies > 1) &&
6152 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 6153 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6154 }
6155
0c3d7c00
EH		 6156 /* SVM requires CPUID[0x8000000A] */
6157 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6158 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6159 }
6cb8f2a6
BS		 6160
6161 /* SEV requires CPUID[0x8000001F] */
6162 if (sev_enabled()) {
6163 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6164 }
dca6cffc
SC		 6165
6166 /* SGX requires CPUID[0x12] for EPC enumeration */
6167 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
6168 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
6169 }
c39c0edf
EH		 6170 }
6171
6172 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6173 if (env->cpuid_level_func7 == UINT32_MAX) {
6174 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6175 }
c39c0edf
EH		 6176 if (env->cpuid_level == UINT32_MAX) {
6177 env->cpuid_level = env->cpuid_min_level;
6178 }
6179 if (env->cpuid_xlevel == UINT32_MAX) {
6180 env->cpuid_xlevel = env->cpuid_min_xlevel;
6181 }
6182 if (env->cpuid_xlevel2 == UINT32_MAX) {
6183 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6184 }
071ce4b0
VK		 6185
6186 if (kvm_enabled()) {
6187 kvm_hyperv_expand_features(cpu, errp);
6188 }
41f3d4d6
EH		 6189}
6190
b8d834a0
EH		 6191/*
6192 * Finishes initialization of CPUID data, filters CPU feature
6193 * words based on host availability of each feature.
6194 *
6195 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6196 */
245edd0c 6197static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6198{
6199 CPUX86State *env = &cpu->env;
6200 FeatureWord w;
245edd0c
PB		 6201 const char *prefix = NULL;
6202
6203 if (verbose) {
6204 prefix = accel_uses_host_cpuid()
6205 ? "host doesn't support requested feature"
6206 : "TCG doesn't support requested feature";
6207 }
b8d834a0
EH		 6208
6209 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6210 uint64_t host_feat =
b8d834a0 6211 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6212 uint64_t requested_features = env->features[w];
6213 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6214 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6215 }
6216
e37a5c7f
CP		 6217 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6218 kvm_enabled()) {
6219 KVMState *s = CPU(cpu)->kvm_state;
6220 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6221 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6222 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6223 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6224 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6225
6226 if (!eax_0 ||
6227 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6228 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6229 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6230 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6231 INTEL_PT_ADDR_RANGES_NUM) ||
6232 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6233 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6234 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6235 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6236 /*
6237 * Processor Trace capabilities aren't configurable, so if the
6238 * host can't emulate the capabilities we report on
6239 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6240 */
245edd0c 6241 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6242 }
6243 }
b8d834a0
EH		 6244}
6245
08856771
VK		 6246static void x86_cpu_hyperv_realize(X86CPU *cpu)
6247{
6248 size_t len;
6249
6250 /* Hyper-V vendor id */
6251 if (!cpu->hyperv_vendor) {
4519259a
VK		 6252 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
6253 &error_abort);
6254 }
6255 len = strlen(cpu->hyperv_vendor);
6256 if (len > 12) {
6257 warn_report("hv-vendor-id truncated to 12 characters");
6258 len = 12;
08856771 6259 }
4519259a
VK		 6260 memset(cpu->hyperv_vendor_id, 0, 12);
6261 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 6262
6263 /* 'Hv#1' interface identification*/
6264 cpu->hyperv_interface_id[0] = 0x31237648;
6265 cpu->hyperv_interface_id[1] = 0;
6266 cpu->hyperv_interface_id[2] = 0;
6267 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 6268
23eb5d03
VK		 6269 /* Hypervisor implementation limits */
6270 cpu->hyperv_limits[0] = 64;
6271 cpu->hyperv_limits[1] = 0;
6272 cpu->hyperv_limits[2] = 0;
08856771
VK		 6273}
6274
41f3d4d6
EH		 6275static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6276{
6277 CPUState *cs = CPU(dev);
6278 X86CPU *cpu = X86_CPU(dev);
6279 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6280 CPUX86State *env = &cpu->env;
6281 Error *local_err = NULL;
6282 static bool ht_warned;
6283
41f3d4d6
EH		 6284 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6285 error_setg(errp, "apic-id property was not initialized properly");
6286 return;
6287 }
6288
662175b9
CF		 6289 /*
6290 * Process Hyper-V enlightenments.
6291 * Note: this currently has to happen before the expansion of CPU features.
6292 */
6293 x86_cpu_hyperv_realize(cpu);
6294
b8d834a0 6295 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6296 if (local_err) {
6297 goto out;
6298 }
6299
245edd0c
PB		 6300 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6301
6302 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6303 error_setg(&local_err,
6304 accel_uses_host_cpuid() ?
6305 "Host doesn't support requested features" :
6306 "TCG doesn't support requested features");
6307 goto out;
9997cf7b
EH		 6308 }
6309
9b15cd9e
IM		 6310 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6311 * CPUID[1].EDX.
6312 */
e48638fd 6313 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6314 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6315 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6316 & CPUID_EXT2_AMD_ALIASES);
6317 }
6318
db888065
SC		 6319 x86_cpu_set_sgxlepubkeyhash(env);
6320
662175b9
CF		 6321 /*
6322 * note: the call to the framework needs to happen after feature expansion,
6323 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
6324 * These may be set by the accel-specific code,
6325 * and the results are subsequently checked / assumed in this function.
6326 */
6327 cpu_exec_realizefn(cs, &local_err);
6328 if (local_err != NULL) {
6329 error_propagate(errp, local_err);
6330 return;
6331 }
6332
6333 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6334 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6335 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6336 goto out;
6337 }
6338
6339 if (cpu->ucode_rev == 0) {
6340 /*
6341 * The default is the same as KVM's. Note that this check
6342 * needs to happen after the evenual setting of ucode_rev in
6343 * accel-specific code in cpu_exec_realizefn.
6344 */
6345 if (IS_AMD_CPU(env)) {
6346 cpu->ucode_rev = 0x01000065;
6347 } else {
6348 cpu->ucode_rev = 0x100000000ULL;
6349 }
6350 }
6351
6352 /*
6353 * mwait extended info: needed for Core compatibility
6354 * We always wake on interrupt even if host does not have the capability.
6355 *
6356 * requires the accel-specific code in cpu_exec_realizefn to
6357 * have already acquired the CPUID data into cpu->mwait.
6358 */
6359 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6360
11f6fee5
DDAG		 6361 /* For 64bit systems think about the number of physical bits to present.
6362 * ideally this should be the same as the host; anything other than matching
6363 * the host can cause incorrect guest behaviour.
6364 * QEMU used to pick the magic value of 40 bits that corresponds to
6365 * consumer AMD devices but nothing else.
662175b9
CF		 6366 *
6367 * Note that this code assumes features expansion has already been done
6368 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
6369 * phys_bits adjustments to match the host have been already done in
6370 * accel-specific code in cpu_exec_realizefn.
11f6fee5 6371 */
af45907a 6372 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 6373 if (cpu->phys_bits &&
6374 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6375 cpu->phys_bits < 32)) {
6376 error_setg(errp, "phys-bits should be between 32 and %u "
6377 " (but is %u)",
6378 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6379 return;
af45907a 6380 }
f5cc5a5c
CF		 6381 /*
6382 * 0 means it was not explicitly set by the user (or by machine
6383 * compat_props or by the host code in host-cpu.c).
6384 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 6385 */
6386 if (cpu->phys_bits == 0) {
6387 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6388 }
af45907a
DDAG		 6389 } else {
6390 /* For 32 bit systems don't use the user set value, but keep
6391 * phys_bits consistent with what we tell the guest.
6392 */
6393 if (cpu->phys_bits != 0) {
6394 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6395 return;
6396 }
fefb41bf 6397
af45907a
DDAG		 6398 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6399 cpu->phys_bits = 36;
6400 } else {
6401 cpu->phys_bits = 32;
6402 }
6403 }
a9f27ea9
EH		 6404
6405 /* Cache information initialization */
6406 if (!cpu->legacy_cache) {
dcafd1ef 6407 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6408 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6409 error_setg(errp,
6410 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6411 return;
6412 }
6413 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6414 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6415 } else {
6416 /* Build legacy cache information */
6417 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6418 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6419 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6420 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6421
6422 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6423 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6424 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6425 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6426
6427 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6428 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6429 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6430 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6431 }
6432
65dee380 6433#ifndef CONFIG_USER_ONLY
0e11fc69 6434 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6435 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6436
0e11fc69 6437 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6438 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6439 if (local_err != NULL) {
4dc1f449 6440 goto out;
bdeec802
IM		 6441 }
6442 }
65dee380
IM		 6443#endif
6444
7a059953 6445 mce_init(cpu);
2001d0cd 6446
14a10fc3 6447 qemu_init_vcpu(cs);
d3c64d6a 6448
6b2942f9
BM		 6449 /*
6450 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6451 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6452 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6453 * users a warning.
6454 *
6455 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6456 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6457 */
0765691e
MA		 6458 if (IS_AMD_CPU(env) &&
6459 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6460 cs->nr_threads > 1 && !ht_warned) {
6461 warn_report("This family of AMD CPU doesn't support "
6462 "hyperthreading(%d)",
6463 cs->nr_threads);
6464 error_printf("Please configure -smp options properly"
6465 " or try enabling topoext feature.\n");
6466 ht_warned = true;
e48638fd
WH		 6467 }
6468
79f1a68a 6469#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 6470 x86_cpu_apic_realize(cpu, &local_err);
6471 if (local_err != NULL) {
6472 goto out;
6473 }
79f1a68a 6474#endif /* !CONFIG_USER_ONLY */
14a10fc3 6475 cpu_reset(cs);
2b6f294c 6476
4dc1f449 6477 xcc->parent_realize(dev, &local_err);
2001d0cd 6478
4dc1f449
IM		 6479out:
6480 if (local_err != NULL) {
6481 error_propagate(errp, local_err);
6482 return;
6483 }
7a059953
AF		 6484}
6485
b69c3c21 6486static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6487{
6488 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6489 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6490
6491#ifndef CONFIG_USER_ONLY
6492 cpu_remove_sync(CPU(dev));
6493 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6494#endif
6495
6496 if (cpu->apic_state) {
6497 object_unparent(OBJECT(cpu->apic_state));
6498 cpu->apic_state = NULL;
6499 }
7bbc124e 6500
b69c3c21 6501 xcc->parent_unrealize(dev);
c884776e
IM		 6502}
6503
38e5c119 6504typedef struct BitProperty {
a7b0ffac 6505 FeatureWord w;
ede146c2 6506 uint64_t mask;
38e5c119
EH		 6507} BitProperty;
6508
d7bce999
EB		 6509static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6510 void *opaque, Error **errp)
38e5c119 6511{
a7b0ffac 6512 X86CPU *cpu = X86_CPU(obj);
38e5c119 6513 BitProperty *fp = opaque;
ede146c2 6514 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6515 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6516 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6517}
6518
d7bce999
EB		 6519static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6520 void *opaque, Error **errp)
38e5c119
EH		 6521{
6522 DeviceState *dev = DEVICE(obj);
a7b0ffac 6523 X86CPU *cpu = X86_CPU(obj);
38e5c119 6524 BitProperty *fp = opaque;
38e5c119
EH		 6525 bool value;
6526
6527 if (dev->realized) {
6528 qdev_prop_set_after_realize(dev, name, errp);
6529 return;
6530 }
6531
668f62ec 6532 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6533 return;
6534 }
6535
6536 if (value) {
a7b0ffac 6537 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6538 } else {
a7b0ffac 6539 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6540 }
d4a606b3 6541 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6542}
6543
38e5c119
EH		 6544/* Register a boolean property to get/set a single bit in a uint32_t field.
6545 *
6546 * The same property name can be registered multiple times to make it affect
6547 * multiple bits in the same FeatureWord. In that case, the getter will return
6548 * true only if all bits are set.
6549 */
f5730c69 6550static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 6551 const char *prop_name,
a7b0ffac 6552 FeatureWord w,
38e5c119
EH		 6553 int bitnr)
6554{
f5730c69 6555 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 6556 BitProperty *fp;
6557 ObjectProperty *op;
ede146c2 6558 uint64_t mask = (1ULL << bitnr);
38e5c119 6559
f5730c69 6560 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 6561 if (op) {
6562 fp = op->opaque;
a7b0ffac 6563 assert(fp->w == w);
38e5c119
EH		 6564 fp->mask |= mask;
6565 } else {
6566 fp = g_new0(BitProperty, 1);
a7b0ffac 6567 fp->w = w;
38e5c119 6568 fp->mask = mask;
f5730c69
EH		 6569 object_class_property_add(oc, prop_name, "bool",
6570 x86_cpu_get_bit_prop,
6571 x86_cpu_set_bit_prop,
6572 NULL, fp);
38e5c119
EH		 6573 }
6574}
6575
f5730c69 6576static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 6577 FeatureWord w,
6578 int bitnr)
6579{
38e5c119 6580 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6581 const char *name = fi->feat_names[bitnr];
38e5c119 6582
16d2fcaa 6583 if (!name) {
38e5c119
EH		 6584 return;
6585 }
6586
fc7dfd20
EH		 6587 /* Property names should use "-" instead of "_".
6588 * Old names containing underscores are registered as aliases
6589 * using object_property_add_alias()
6590 */
16d2fcaa
EH		 6591 assert(!strchr(name, '_'));
6592 /* aliases don't use "|" delimiters anymore, they are registered
6593 * manually using object_property_add_alias() */
6594 assert(!strchr(name, '|'));
f5730c69 6595 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 6596}
6597
4db4385a
CF		 6598static void x86_cpu_post_initfn(Object *obj)
6599{
6600 accel_cpu_instance_init(CPU(obj));
6601}
6602
de024815
AF		 6603static void x86_cpu_initfn(Object *obj)
6604{
6605 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6606 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 6607 CPUX86State *env = &cpu->env;
6608
c26ae610 6609 env->nr_dies = 1;
7506ed90 6610 cpu_set_cpustate_pointers(cpu);
71ad61d3 6611
8e8aba50
EH		 6612 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6613 x86_cpu_get_feature_words,
d2623129 6614 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6615 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6616 x86_cpu_get_feature_words,
d2623129 6617 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 6618
d2623129
MA		 6619 object_property_add_alias(obj, "sse3", obj, "pni");
6620 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6621 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6622 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6623 object_property_add_alias(obj, "xd", obj, "nx");
6624 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6625 object_property_add_alias(obj, "i64", obj, "lm");
6626
6627 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6628 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6629 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6630 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6631 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6632 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6633 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6634 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6635 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6636 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6637 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 6638 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 6639 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6640 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6641 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6642 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6643 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6644 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6645 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6646 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6647 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6648 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6649 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6650
e1f9a8e8
VK		 6651 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
6652
dcafd1ef 6653 if (xcc->model) {
49e2fa85 6654 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 6655 }
de024815
AF		 6656}
6657
997395d3
IM		 6658static int64_t x86_cpu_get_arch_id(CPUState *cs)
6659{
6660 X86CPU *cpu = X86_CPU(cs);
997395d3 6661
7e72a45c 6662 return cpu->apic_id;
997395d3
IM		 6663}
6664
6bc0d6a0 6665#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 6666static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6667{
6668 X86CPU *cpu = X86_CPU(cs);
6669
6670 return cpu->env.cr[0] & CR0_PG_MASK;
6671}
6bc0d6a0 6672#endif /* !CONFIG_USER_ONLY */
444d5590 6673
f45748f1
AF		 6674static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6675{
6676 X86CPU *cpu = X86_CPU(cs);
6677
6678 cpu->env.eip = value;
6679}
6680
92d5f1a4 6681int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6682{
6683 X86CPU *cpu = X86_CPU(cs);
6684 CPUX86State *env = &cpu->env;
6685
92d5f1a4
PB		 6686#if !defined(CONFIG_USER_ONLY)
6687 if (interrupt_request & CPU_INTERRUPT_POLL) {
6688 return CPU_INTERRUPT_POLL;
6689 }
6690#endif
6691 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6692 return CPU_INTERRUPT_SIPI;
6693 }
6694
6695 if (env->hflags2 & HF2_GIF_MASK) {
6696 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6697 !(env->hflags & HF_SMM_MASK)) {
6698 return CPU_INTERRUPT_SMI;
6699 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6700 !(env->hflags2 & HF2_NMI_MASK)) {
6701 return CPU_INTERRUPT_NMI;
6702 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6703 return CPU_INTERRUPT_MCE;
6704 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6705 (((env->hflags2 & HF2_VINTR_MASK) &&
6706 (env->hflags2 & HF2_HIF_MASK)) ||
6707 (!(env->hflags2 & HF2_VINTR_MASK) &&
6708 (env->eflags & IF_MASK &&
6709 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6710 return CPU_INTERRUPT_HARD;
6711#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 6712 } else if (env->hflags2 & HF2_VGIF_MASK) {
6713 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 6714 (env->eflags & IF_MASK) &&
6715 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 6716 return CPU_INTERRUPT_VIRQ;
6717 }
92d5f1a4
PB		 6718#endif
6719 }
6720 }
6721
6722 return 0;
6723}
6724
6725static bool x86_cpu_has_work(CPUState *cs)
6726{
6727 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 6728}
6729
f50f3dd5
RH		 6730static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6731{
6732 X86CPU *cpu = X86_CPU(cs);
6733 CPUX86State *env = &cpu->env;
6734
6735 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6736 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6737 : bfd_mach_i386_i8086);
6738 info->print_insn = print_insn_i386;
b666d2a4
RH		 6739
6740 info->cap_arch = CS_ARCH_X86;
6741 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6742 : env->hflags & HF_CS32_MASK ? CS_MODE_32
6743 : CS_MODE_16);
15fa1a0a
RH		 6744 info->cap_insn_unit = 1;
6745 info->cap_insn_split = 8;
f50f3dd5
RH		 6746}
6747
35b1b927
TW		 6748void x86_update_hflags(CPUX86State *env)
6749{
6750 uint32_t hflags;
6751#define HFLAG_COPY_MASK \
6752 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6753 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6754 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6755 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6756
6757 hflags = env->hflags & HFLAG_COPY_MASK;
6758 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6759 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6760 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6761 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6762 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6763
6764 if (env->cr[4] & CR4_OSFXSR_MASK) {
6765 hflags |= HF_OSFXSR_MASK;
6766 }
6767
6768 if (env->efer & MSR_EFER_LMA) {
6769 hflags |= HF_LMA_MASK;
6770 }
6771
6772 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6773 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6774 } else {
6775 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6776 (DESC_B_SHIFT - HF_CS32_SHIFT);
6777 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6778 (DESC_B_SHIFT - HF_SS32_SHIFT);
6779 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6780 !(hflags & HF_CS32_MASK)) {
6781 hflags |= HF_ADDSEG_MASK;
6782 } else {
6783 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6784 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6785 }
6786 }
6787 env->hflags = hflags;
6788}
6789
9337e3b6 6790static Property x86_cpu_properties[] = {
2da00e31
IM		 6791#ifdef CONFIG_USER_ONLY
6792 /* apic_id = 0 by default for *-user, see commit 9886e834 */
6793 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 6794 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6795 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 6796 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 6797 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 6798#else
6799 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 6800 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6801 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 6802 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 6803 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 6804#endif
15f8b142 6805 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 6806 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 6807
915aee93 6808 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 6809 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 6810 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
6811 HYPERV_FEAT_RELAXED, 0),
6812 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
6813 HYPERV_FEAT_VAPIC, 0),
6814 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
6815 HYPERV_FEAT_TIME, 0),
6816 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
6817 HYPERV_FEAT_CRASH, 0),
6818 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
6819 HYPERV_FEAT_RESET, 0),
6820 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
6821 HYPERV_FEAT_VPINDEX, 0),
6822 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
6823 HYPERV_FEAT_RUNTIME, 0),
6824 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
6825 HYPERV_FEAT_SYNIC, 0),
6826 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
6827 HYPERV_FEAT_STIMER, 0),
6828 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
6829 HYPERV_FEAT_FREQUENCIES, 0),
6830 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
6831 HYPERV_FEAT_REENLIGHTENMENT, 0),
6832 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
6833 HYPERV_FEAT_TLBFLUSH, 0),
6834 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
6835 HYPERV_FEAT_EVMCS, 0),
6836 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
6837 HYPERV_FEAT_IPI, 0),
128531d9
VK		 6838 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
6839 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 6840 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
6841 HYPERV_FEAT_AVIC, 0),
30d6ff66
VK		 6842 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
6843 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
e48ddcc6 6844 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 6845 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 6846
af7228b8
VK		 6847 /* WS2008R2 identify by default */
6848 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 6849 0x3839),
af7228b8 6850 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 6851 0x000A),
af7228b8 6852 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 6853 0x0000),
af7228b8
VK		 6854 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
6855 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
6856 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
6857
15e41345 6858 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 6859 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 6860 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 6861 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 6862 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 6863 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 6864 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 6865 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 6866 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
6867 UINT32_MAX),
c39c0edf
EH		 6868 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
6869 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
6870 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
6871 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
6872 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
6873 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 6874 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 6875 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 6876 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 6877 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 6878 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 6879 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 6880 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 6881 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
6882 false),
988f7b8b
VK		 6883 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
6884 false),
0b564e6f 6885 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 6886 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 6887 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
6888 true),
ab8f992e 6889 /*
a9f27ea9
EH		 6890 * lecacy_cache defaults to true unless the CPU model provides its
6891 * own cache information (see x86_cpu_load_def()).
ab8f992e 6892 */
a9f27ea9 6893 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 6894
6895 /*
6896 * From "Requirements for Implementing the Microsoft
6897 * Hypervisor Interface":
6898 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
6899 *
6900 * "Starting with Windows Server 2012 and Windows 8, if
6901 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
6902 * the hypervisor imposes no specific limit to the number of VPs.
6903 * In this case, Windows Server 2012 guest VMs may use more than
6904 * 64 VPs, up to the maximum supported number of processors applicable
6905 * to the specific Windows version being used."
6906 */
6907 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 6908 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
6909 false),
f24c3a79
LK		 6910 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
6911 true),
9337e3b6
EH		 6912 DEFINE_PROP_END_OF_LIST()
6913};
6914
8b80bd28
PMD		 6915#ifndef CONFIG_USER_ONLY
6916#include "hw/core/sysemu-cpu-ops.h"
6917
6918static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 6919 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 6920 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 6921 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 6922 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 6923 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 6924 .write_elf32_note = x86_cpu_write_elf32_note,
6925 .write_elf64_note = x86_cpu_write_elf64_note,
6926 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
6927 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 6928 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 6929};
6930#endif
6931
5fd2087a
AF		 6932static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
6933{
6934 X86CPUClass *xcc = X86_CPU_CLASS(oc);
6935 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 6936 DeviceClass *dc = DEVICE_CLASS(oc);
f5730c69 6937 FeatureWord w;
2b6f294c 6938
bf853881
PMD		 6939 device_class_set_parent_realize(dc, x86_cpu_realizefn,
6940 &xcc->parent_realize);
6941 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
6942 &xcc->parent_unrealize);
4f67d30b 6943 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 6944
781c67ca 6945 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 6946 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 6947
500050d1 6948 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 6949 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 6950 cc->has_work = x86_cpu_has_work;
878096ee 6951 cc->dump_state = x86_cpu_dump_state;
f45748f1 6952 cc->set_pc = x86_cpu_set_pc;
5b50e790
AF		 6953 cc->gdb_read_register = x86_cpu_gdb_read_register;
6954 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 6955 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 6956
5d004421 6957#ifndef CONFIG_USER_ONLY
8b80bd28 6958 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 6959#endif /* !CONFIG_USER_ONLY */
6960
00fcd100
AB		 6961 cc->gdb_arch_name = x86_gdb_arch_name;
6962#ifdef TARGET_X86_64
b8158192 6963 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 6964 cc->gdb_num_core_regs = 66;
00fcd100 6965#else
b8158192 6966 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 6967 cc->gdb_num_core_regs = 50;
74d7fc7f 6968#endif
f50f3dd5 6969 cc->disas_set_info = x86_disas_set_info;
4c315c27 6970
e90f2a8c 6971 dc->user_creatable = true;
3e0dceaf
EH		 6972
6973 object_class_property_add(oc, "family", "int",
6974 x86_cpuid_version_get_family,
6975 x86_cpuid_version_set_family, NULL, NULL);
6976 object_class_property_add(oc, "model", "int",
6977 x86_cpuid_version_get_model,
6978 x86_cpuid_version_set_model, NULL, NULL);
6979 object_class_property_add(oc, "stepping", "int",
6980 x86_cpuid_version_get_stepping,
6981 x86_cpuid_version_set_stepping, NULL, NULL);
6982 object_class_property_add_str(oc, "vendor",
6983 x86_cpuid_get_vendor,
6984 x86_cpuid_set_vendor);
6985 object_class_property_add_str(oc, "model-id",
6986 x86_cpuid_get_model_id,
6987 x86_cpuid_set_model_id);
6988 object_class_property_add(oc, "tsc-frequency", "int",
6989 x86_cpuid_get_tsc_freq,
6990 x86_cpuid_set_tsc_freq, NULL, NULL);
6991 /*
6992 * The "unavailable-features" property has the same semantics as
6993 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6994 * QMP command: they list the features that would have prevented the
6995 * CPU from running if the "enforce" flag was set.
6996 */
6997 object_class_property_add(oc, "unavailable-features", "strList",
6998 x86_cpu_get_unavailable_features,
6999 NULL, NULL, NULL);
7000
7001#if !defined(CONFIG_USER_ONLY)
7002 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7003 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7004#endif
7005
f5730c69
EH		 7006 for (w = 0; w < FEATURE_WORDS; w++) {
7007 int bitnr;
7008 for (bitnr = 0; bitnr < 64; bitnr++) {
7009 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
7010 }
7011 }
5fd2087a
AF		 7012}
7013
7014static const TypeInfo x86_cpu_type_info = {
7015 .name = TYPE_X86_CPU,
7016 .parent = TYPE_CPU,
7017 .instance_size = sizeof(X86CPU),
de024815 7018 .instance_init = x86_cpu_initfn,
4db4385a
CF		 7019 .instance_post_init = x86_cpu_post_initfn,
7020
d940ee9b 7021 .abstract = true,
5fd2087a
AF		 7022 .class_size = sizeof(X86CPUClass),
7023 .class_init = x86_cpu_common_class_init,
7024};
7025
5adbed30
EH		 7026/* "base" CPU model, used by query-cpu-model-expansion */
7027static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7028{
7029 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7030
7031 xcc->static_model = true;
7032 xcc->migration_safe = true;
7033 xcc->model_description = "base CPU model type with no features enabled";
7034 xcc->ordering = 8;
7035}
7036
7037static const TypeInfo x86_base_cpu_type_info = {
7038 .name = X86_CPU_TYPE_NAME("base"),
7039 .parent = TYPE_X86_CPU,
7040 .class_init = x86_cpu_base_class_init,
7041};
7042
5fd2087a
AF		 7043static void x86_cpu_register_types(void)
7044{
d940ee9b
EH		 7045 int i;
7046
5fd2087a 7047 type_register_static(&x86_cpu_type_info);
d940ee9b 7048 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7049 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7050 }
c62f2630 7051 type_register_static(&max_x86_cpu_type_info);
5adbed30 7052 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 7053}
7054
7055type_init(x86_cpu_register_types)
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