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target/i386: introduce helper to access supported CPUID
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
15e09912 24#include "qemu/hw-version.h"
c6dc6f63 25#include "cpu.h"
ed69e831 26#include "tcg/helper-tcg.h"
71e8a915 27#include "sysemu/reset.h"
d6dcc558 28#include "sysemu/hvf.h"
a9dc68d9 29#include "kvm/kvm_i386.h"
93777de3 30#include "sev.h"
f83aeeae 31#include "qapi/error.h"
8ac25c84 32#include "qapi/qapi-visit-machine.h"
7b1b5d19 33#include "qapi/qmp/qerror.h"
7f7b4e7a 34#include "qapi/qapi-commands-machine-target.h"
1814eab6 35#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 36#include "hw/qdev-properties.h"
5232d00a 37#include "hw/i386/topology.h"
bdeec802 38#ifndef CONFIG_USER_ONLY
2001d0cd 39#include "exec/address-spaces.h"
0e11fc69 40#include "hw/boards.h"
1dec2e1f 41#include "hw/i386/sgx-epc.h"
bdeec802
IM		 42#endif
43
b666d2a4 44#include "disas/capstone.h"
79f1a68a 45#include "cpu-internal.h"
b666d2a4 46
7e3482f8
EH		 47/* Helpers for building CPUID[2] descriptors: */
48
49struct CPUID2CacheDescriptorInfo {
50 enum CacheType type;
51 int level;
52 int size;
53 int line_size;
54 int associativity;
55};
5e891bf8 56
7e3482f8
EH		 57/*
58 * Known CPUID 2 cache descriptors.
59 * From Intel SDM Volume 2A, CPUID instruction
60 */
61struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 62 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 63 .associativity = 4, .line_size = 32, },
5f00335a 64 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 65 .associativity = 4, .line_size = 32, },
5f00335a 66 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 67 .associativity = 4, .line_size = 64, },
5f00335a 68 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 69 .associativity = 2, .line_size = 32, },
5f00335a 70 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 71 .associativity = 4, .line_size = 32, },
5f00335a 72 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 73 .associativity = 4, .line_size = 64, },
5f00335a 74 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 75 .associativity = 6, .line_size = 64, },
5f00335a 76 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 77 .associativity = 2, .line_size = 64, },
5f00335a 78 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 79 .associativity = 8, .line_size = 64, },
80 /* lines per sector is not supported cpuid2_cache_descriptor(),
81 * so descriptors 0x22, 0x23 are not included
82 */
5f00335a 83 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 84 .associativity = 16, .line_size = 64, },
85 /* lines per sector is not supported cpuid2_cache_descriptor(),
86 * so descriptors 0x25, 0x20 are not included
87 */
5f00335a 88 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 89 .associativity = 8, .line_size = 64, },
5f00335a 90 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 91 .associativity = 8, .line_size = 64, },
5f00335a 92 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 93 .associativity = 4, .line_size = 32, },
5f00335a 94 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 95 .associativity = 4, .line_size = 32, },
5f00335a 96 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 97 .associativity = 4, .line_size = 32, },
5f00335a 98 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 99 .associativity = 4, .line_size = 32, },
5f00335a 100 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 101 .associativity = 4, .line_size = 32, },
5f00335a 102 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 103 .associativity = 4, .line_size = 64, },
5f00335a 104 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 105 .associativity = 8, .line_size = 64, },
5f00335a 106 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 107 .associativity = 12, .line_size = 64, },
108 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 109 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 110 .associativity = 12, .line_size = 64, },
5f00335a 111 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 112 .associativity = 16, .line_size = 64, },
5f00335a 113 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 114 .associativity = 12, .line_size = 64, },
5f00335a 115 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 116 .associativity = 16, .line_size = 64, },
5f00335a 117 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 118 .associativity = 24, .line_size = 64, },
5f00335a 119 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 120 .associativity = 8, .line_size = 64, },
5f00335a 121 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 122 .associativity = 4, .line_size = 64, },
5f00335a 123 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 124 .associativity = 4, .line_size = 64, },
5f00335a 125 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 126 .associativity = 4, .line_size = 64, },
5f00335a 127 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 128 .associativity = 4, .line_size = 64, },
129 /* lines per sector is not supported cpuid2_cache_descriptor(),
130 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
131 */
5f00335a 132 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 133 .associativity = 8, .line_size = 64, },
5f00335a 134 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 135 .associativity = 2, .line_size = 64, },
5f00335a 136 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 139 .associativity = 8, .line_size = 32, },
5f00335a 140 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 141 .associativity = 8, .line_size = 32, },
5f00335a 142 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 143 .associativity = 8, .line_size = 32, },
5f00335a 144 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 145 .associativity = 8, .line_size = 32, },
5f00335a 146 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 147 .associativity = 4, .line_size = 64, },
5f00335a 148 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 149 .associativity = 8, .line_size = 64, },
5f00335a 150 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 4, .line_size = 64, },
5f00335a 152 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 153 .associativity = 4, .line_size = 64, },
5f00335a 154 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 155 .associativity = 4, .line_size = 64, },
5f00335a 156 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 8, .line_size = 64, },
5f00335a 158 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 8, .line_size = 64, },
5f00335a 160 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 163 .associativity = 12, .line_size = 64, },
5f00335a 164 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 165 .associativity = 12, .line_size = 64, },
5f00335a 166 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 167 .associativity = 12, .line_size = 64, },
5f00335a 168 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 169 .associativity = 16, .line_size = 64, },
5f00335a 170 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 171 .associativity = 16, .line_size = 64, },
5f00335a 172 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 173 .associativity = 16, .line_size = 64, },
5f00335a 174 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 175 .associativity = 24, .line_size = 64, },
5f00335a 176 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 177 .associativity = 24, .line_size = 64, },
5f00335a 178 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 179 .associativity = 24, .line_size = 64, },
180};
181
182/*
183 * "CPUID leaf 2 does not report cache descriptor information,
184 * use CPUID leaf 4 to query cache parameters"
185 */
186#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 187
7e3482f8
EH		 188/*
189 * Return a CPUID 2 cache descriptor for a given cache.
190 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
191 */
192static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
193{
194 int i;
195
196 assert(cache->size > 0);
197 assert(cache->level > 0);
198 assert(cache->line_size > 0);
199 assert(cache->associativity > 0);
200 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
201 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
202 if (d->level == cache->level && d->type == cache->type &&
203 d->size == cache->size && d->line_size == cache->line_size &&
204 d->associativity == cache->associativity) {
205 return i;
206 }
207 }
5e891bf8 208
7e3482f8
EH		 209 return CACHE_DESCRIPTOR_UNAVAILABLE;
210}
5e891bf8
EH		 211
212/* CPUID Leaf 4 constants: */
213
214/* EAX: */
7e3482f8
EH		 215#define CACHE_TYPE_D 1
216#define CACHE_TYPE_I 2
217#define CACHE_TYPE_UNIFIED 3
5e891bf8 218
7e3482f8 219#define CACHE_LEVEL(l) (l << 5)
5e891bf8 220
7e3482f8 221#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 222
223/* EDX: */
7e3482f8
EH		 224#define CACHE_NO_INVD_SHARING (1 << 0)
225#define CACHE_INCLUSIVE (1 << 1)
226#define CACHE_COMPLEX_IDX (1 << 2)
227
228/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 229#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
230 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
231 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
232 0 /* Invalid value */)
7e3482f8
EH		 233
234
235/* Encode cache info for CPUID[4] */
236static void encode_cache_cpuid4(CPUCacheInfo *cache,
237 int num_apic_ids, int num_cores,
238 uint32_t *eax, uint32_t *ebx,
239 uint32_t *ecx, uint32_t *edx)
240{
241 assert(cache->size == cache->line_size * cache->associativity *
242 cache->partitions * cache->sets);
243
244 assert(num_apic_ids > 0);
245 *eax = CACHE_TYPE(cache->type) |
246 CACHE_LEVEL(cache->level) |
247 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
248 ((num_cores - 1) << 26) |
249 ((num_apic_ids - 1) << 14);
250
251 assert(cache->line_size > 0);
252 assert(cache->partitions > 0);
253 assert(cache->associativity > 0);
254 /* We don't implement fully-associative caches */
255 assert(cache->associativity < cache->sets);
256 *ebx = (cache->line_size - 1) |
257 ((cache->partitions - 1) << 12) |
258 ((cache->associativity - 1) << 22);
259
260 assert(cache->sets > 0);
261 *ecx = cache->sets - 1;
262
263 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
264 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
265 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
266}
267
268/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
269static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
270{
271 assert(cache->size % 1024 == 0);
272 assert(cache->lines_per_tag > 0);
273 assert(cache->associativity > 0);
274 assert(cache->line_size > 0);
275 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
276 (cache->lines_per_tag << 8) | (cache->line_size);
277}
5e891bf8
EH		 278
279#define ASSOC_FULL 0xFF
280
281/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
282#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
283 a == 2 ? 0x2 : \
284 a == 4 ? 0x4 : \
285 a == 8 ? 0x6 : \
286 a == 16 ? 0x8 : \
287 a == 32 ? 0xA : \
288 a == 48 ? 0xB : \
289 a == 64 ? 0xC : \
290 a == 96 ? 0xD : \
291 a == 128 ? 0xE : \
292 a == ASSOC_FULL ? 0xF : \
293 0 /* invalid value */)
294
7e3482f8
EH		 295/*
296 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
297 * @l3 can be NULL.
298 */
299static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
300 CPUCacheInfo *l3,
301 uint32_t *ecx, uint32_t *edx)
302{
303 assert(l2->size % 1024 == 0);
304 assert(l2->associativity > 0);
305 assert(l2->lines_per_tag > 0);
306 assert(l2->line_size > 0);
307 *ecx = ((l2->size / 1024) << 16) |
308 (AMD_ENC_ASSOC(l2->associativity) << 12) |
309 (l2->lines_per_tag << 8) | (l2->line_size);
310
311 if (l3) {
312 assert(l3->size % (512 * 1024) == 0);
313 assert(l3->associativity > 0);
314 assert(l3->lines_per_tag > 0);
315 assert(l3->line_size > 0);
316 *edx = ((l3->size / (512 * 1024)) << 18) |
317 (AMD_ENC_ASSOC(l3->associativity) << 12) |
318 (l3->lines_per_tag << 8) | (l3->line_size);
319 } else {
320 *edx = 0;
321 }
322}
5e891bf8 323
8f4202fb 324/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 325static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
326 X86CPUTopoInfo *topo_info,
327 uint32_t *eax, uint32_t *ebx,
328 uint32_t *ecx, uint32_t *edx)
8f4202fb 329{
2f084d1e 330 uint32_t l3_threads;
8f4202fb
BM		 331 assert(cache->size == cache->line_size * cache->associativity *
332 cache->partitions * cache->sets);
333
334 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
335 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
336
337 /* L3 is shared among multiple cores */
338 if (cache->level == 3) {
2f084d1e
BM		 339 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
340 *eax |= (l3_threads - 1) << 14;
8f4202fb 341 } else {
2f084d1e 342 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 343 }
344
345 assert(cache->line_size > 0);
346 assert(cache->partitions > 0);
347 assert(cache->associativity > 0);
348 /* We don't implement fully-associative caches */
349 assert(cache->associativity < cache->sets);
350 *ebx = (cache->line_size - 1) |
351 ((cache->partitions - 1) << 12) |
352 ((cache->associativity - 1) << 22);
353
354 assert(cache->sets > 0);
355 *ecx = cache->sets - 1;
356
357 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
358 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
359 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
360}
361
ed78467a 362/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 363static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
364 uint32_t *eax, uint32_t *ebx,
365 uint32_t *ecx, uint32_t *edx)
ed78467a 366{
31ada106
BM		 367 X86CPUTopoIDs topo_ids;
368
369 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 370
ed78467a 371 *eax = cpu->apic_id;
31ada106 372
ed78467a 373 /*
31ada106
BM		 374 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
375 * Read-only. Reset: 0000_XXXXh.
376 * See Core::X86::Cpuid::ExtApicId.
377 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
378 * Bits Description
379 * 31:16 Reserved.
380 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
381 * The number of threads per core is ThreadsPerCore+1.
382 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
383 *
384 * NOTE: CoreId is already part of apic_id. Just use it. We can
385 * use all the 8 bits to represent the core_id here.
ed78467a 386 */
31ada106
BM		 387 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
388
ed78467a 389 /*
31ada106
BM		 390 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
391 * Read-only. Reset: 0000_0XXXh.
392 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
393 * Bits Description
394 * 31:11 Reserved.
395 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
396 * ValidValues:
397 * Value Description
398 * 000b 1 node per processor.
399 * 001b 2 nodes per processor.
400 * 010b Reserved.
401 * 011b 4 nodes per processor.
402 * 111b-100b Reserved.
403 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
404 *
405 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
406 * But users can create more nodes than the actual hardware can
407 * support. To genaralize we can use all the upper 8 bits for nodes.
408 * NodeId is combination of node and socket_id which is already decoded
409 * in apic_id. Just use it by shifting.
ed78467a 410 */
31ada106
BM		 411 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
412 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
413
ed78467a
BM		 414 *edx = 0;
415}
416
ab8f992e
BM		 417/*
418 * Definitions of the hardcoded cache entries we expose:
419 * These are legacy cache values. If there is a need to change any
420 * of these values please use builtin_x86_defs
421 */
5e891bf8
EH		 422
423/* L1 data cache: */
ab8f992e 424static CPUCacheInfo legacy_l1d_cache = {
5f00335a 425 .type = DATA_CACHE,
7e3482f8
EH		 426 .level = 1,
427 .size = 32 * KiB,
428 .self_init = 1,
429 .line_size = 64,
430 .associativity = 8,
431 .sets = 64,
432 .partitions = 1,
433 .no_invd_sharing = true,
434};
435
5e891bf8 436/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 437static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 438 .type = DATA_CACHE,
7e3482f8
EH		 439 .level = 1,
440 .size = 64 * KiB,
441 .self_init = 1,
442 .line_size = 64,
443 .associativity = 2,
444 .sets = 512,
445 .partitions = 1,
446 .lines_per_tag = 1,
447 .no_invd_sharing = true,
448};
5e891bf8
EH		 449
450/* L1 instruction cache: */
ab8f992e 451static CPUCacheInfo legacy_l1i_cache = {
5f00335a 452 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 453 .level = 1,
454 .size = 32 * KiB,
455 .self_init = 1,
456 .line_size = 64,
457 .associativity = 8,
458 .sets = 64,
459 .partitions = 1,
460 .no_invd_sharing = true,
461};
462
5e891bf8 463/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 464static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 465 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 466 .level = 1,
467 .size = 64 * KiB,
468 .self_init = 1,
469 .line_size = 64,
470 .associativity = 2,
471 .sets = 512,
472 .partitions = 1,
473 .lines_per_tag = 1,
474 .no_invd_sharing = true,
475};
5e891bf8
EH		 476
477/* Level 2 unified cache: */
ab8f992e 478static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 479 .type = UNIFIED_CACHE,
480 .level = 2,
481 .size = 4 * MiB,
482 .self_init = 1,
483 .line_size = 64,
484 .associativity = 16,
485 .sets = 4096,
486 .partitions = 1,
487 .no_invd_sharing = true,
488};
489
5e891bf8 490/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 491static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 492 .type = UNIFIED_CACHE,
493 .level = 2,
494 .size = 2 * MiB,
495 .line_size = 64,
496 .associativity = 8,
497};
498
499
5e891bf8 500/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 501static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 502 .type = UNIFIED_CACHE,
503 .level = 2,
504 .size = 512 * KiB,
505 .line_size = 64,
506 .lines_per_tag = 1,
507 .associativity = 16,
508 .sets = 512,
509 .partitions = 1,
510};
5e891bf8 511
14c985cf 512/* Level 3 unified cache: */
ab8f992e 513static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 514 .type = UNIFIED_CACHE,
515 .level = 3,
516 .size = 16 * MiB,
517 .line_size = 64,
518 .associativity = 16,
519 .sets = 16384,
520 .partitions = 1,
521 .lines_per_tag = 1,
522 .self_init = true,
523 .inclusive = true,
524 .complex_indexing = true,
525};
5e891bf8
EH		 526
527/* TLB definitions: */
528
529#define L1_DTLB_2M_ASSOC 1
530#define L1_DTLB_2M_ENTRIES 255
531#define L1_DTLB_4K_ASSOC 1
532#define L1_DTLB_4K_ENTRIES 255
533
534#define L1_ITLB_2M_ASSOC 1
535#define L1_ITLB_2M_ENTRIES 255
536#define L1_ITLB_4K_ASSOC 1
537#define L1_ITLB_4K_ENTRIES 255
538
539#define L2_DTLB_2M_ASSOC 0 /* disabled */
540#define L2_DTLB_2M_ENTRIES 0 /* disabled */
541#define L2_DTLB_4K_ASSOC 4
542#define L2_DTLB_4K_ENTRIES 512
543
544#define L2_ITLB_2M_ASSOC 0 /* disabled */
545#define L2_ITLB_2M_ENTRIES 0 /* disabled */
546#define L2_ITLB_4K_ASSOC 4
547#define L2_ITLB_4K_ENTRIES 512
548
e37a5c7f
CP		 549/* CPUID Leaf 0x14 constants: */
550#define INTEL_PT_MAX_SUBLEAF 0x1
551/*
552 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
553 * MSR can be accessed;
554 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
555 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
556 * of Intel PT MSRs across warm reset;
557 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
558 */
559#define INTEL_PT_MINIMAL_EBX 0xf
560/*
561 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
562 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
563 * accessed;
564 * bit[01]: ToPA tables can hold any number of output entries, up to the
565 * maximum allowed by the MaskOrTableOffset field of
566 * IA32_RTIT_OUTPUT_MASK_PTRS;
567 * bit[02]: Support Single-Range Output scheme;
568 */
569#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 570/* generated packets which contain IP payloads have LIP values */
571#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 572#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
573#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
574#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
575#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
576#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 577
f21a4817
JL		 578/* CPUID Leaf 0x1D constants: */
579#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
580#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
581#define INTEL_AMX_BYTES_PER_TILE 0x400
582#define INTEL_AMX_BYTES_PER_ROW 0x40
583#define INTEL_AMX_TILE_MAX_NAMES 0x8
584#define INTEL_AMX_TILE_MAX_ROWS 0x10
585
586/* CPUID Leaf 0x1E constants: */
587#define INTEL_AMX_TMUL_MAX_K 0x10
588#define INTEL_AMX_TMUL_MAX_N 0x40
589
f5cc5a5c
CF		 590void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
591 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 592{
593 int i;
594 for (i = 0; i < 4; i++) {
595 dst[i] = vendor1 >> (8 * i);
596 dst[i + 4] = vendor2 >> (8 * i);
597 dst[i + 8] = vendor3 >> (8 * i);
598 }
599 dst[CPUID_VENDOR_SZ] = '\0';
600}
601
621626ce
EH		 602#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
603#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
604 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
605#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
606 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
607 CPUID_PSE36 | CPUID_FXSR)
608#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
609#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
610 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
611 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
612 CPUID_PAE | CPUID_SEP | CPUID_APIC)
613
614#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
615 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
616 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
617 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 618 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 619 /* partly implemented:
620 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
621 /* missing:
622 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
623#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
624 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
625 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 626 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 627 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
628 CPUID_EXT_RDRAND)
621626ce
EH		 629 /* missing:
630 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
631 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
632 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 633 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 634 CPUID_EXT_F16C */
621626ce
EH		 635
636#ifdef TARGET_X86_64
637#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
638#else
639#define TCG_EXT2_X86_64_FEATURES 0
640#endif
641
642#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
643 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
644 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
645 TCG_EXT2_X86_64_FEATURES)
646#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
647 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
648#define TCG_EXT4_FEATURES 0
900eeca5
LL		 649#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
650 CPUID_SVM_SVME_ADDR_CHK)
621626ce
EH		 651#define TCG_KVM_FEATURES 0
652#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 653 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
654 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 655 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
656 CPUID_7_0_EBX_ERMS)
621626ce 657 /* missing:
07929f2a 658 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 659 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 660 CPUID_7_0_EBX_RDSEED */
637f1ee3 661#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
9ccb9784 662 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
e7e7bdab 663 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
95ea69fb 664#define TCG_7_0_EDX_FEATURES 0
80db491d 665#define TCG_7_1_EAX_FEATURES 0
303752a9 666#define TCG_APM_FEATURES 0
28b8e4d0 667#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 668#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
669 /* missing:
670 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 671#define TCG_14_0_ECX_FEATURES 0
4b841a79 672#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 673#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 674#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 675
79f1a68a 676FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 677 [FEAT_1_EDX] = {
07585923 678 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 679 .feat_names = {
680 "fpu", "vme", "de", "pse",
681 "tsc", "msr", "pae", "mce",
682 "cx8", "apic", NULL, "sep",
683 "mtrr", "pge", "mca", "cmov",
684 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
685 NULL, "ds" /* Intel dts */, "acpi", "mmx",
686 "fxsr", "sse", "sse2", "ss",
687 "ht" /* Intel htt */, "tm", "ia64", "pbe",
688 },
07585923 689 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 690 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 691 },
692 [FEAT_1_ECX] = {
07585923 693 .type = CPUID_FEATURE_WORD,
2d5312da 694 .feat_names = {
16d2fcaa 695 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 696 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 697 "tm2", "ssse3", "cid", NULL,
698 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 699 NULL, "pcid", "dca", "sse4.1",
700 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 701 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 702 "avx", "f16c", "rdrand", "hypervisor",
703 },
07585923 704 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 705 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 706 },
2d5312da
EH		 707 /* Feature names that are already defined on feature_name[] but
708 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
709 * names on feat_names below. They are copied automatically
710 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
711 */
bffd67b0 712 [FEAT_8000_0001_EDX] = {
07585923 713 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 714 .feat_names = {
715 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
716 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
717 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
718 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
719 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 720 "nx", NULL, "mmxext", NULL /* mmx */,
721 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
722 NULL, "lm", "3dnowext", "3dnow",
2d5312da 723 },
07585923 724 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 725 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 726 },
727 [FEAT_8000_0001_ECX] = {
07585923 728 .type = CPUID_FEATURE_WORD,
2d5312da 729 .feat_names = {
fc7dfd20 730 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 731 "cr8legacy", "abm", "sse4a", "misalignsse",
732 "3dnowprefetch", "osvw", "ibs", "xop",
733 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 734 "fma4", "tce", NULL, "nodeid-msr",
735 NULL, "tbm", "topoext", "perfctr-core",
736 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 737 NULL, NULL, NULL, NULL,
738 },
07585923 739 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 740 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 741 /*
742 * TOPOEXT is always allowed but can't be enabled blindly by
743 * "-cpu host", as it requires consistent cache topology info
744 * to be provided so it doesn't confuse guests.
745 */
746 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 747 },
89e49c8b 748 [FEAT_C000_0001_EDX] = {
07585923 749 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 750 .feat_names = {
751 NULL, NULL, "xstore", "xstore-en",
752 NULL, NULL, "xcrypt", "xcrypt-en",
753 "ace2", "ace2-en", "phe", "phe-en",
754 "pmm", "pmm-en", NULL, NULL,
755 NULL, NULL, NULL, NULL,
756 NULL, NULL, NULL, NULL,
757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 },
07585923 760 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 761 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 762 },
bffd67b0 763 [FEAT_KVM] = {
07585923 764 .type = CPUID_FEATURE_WORD,
2d5312da 765 .feat_names = {
fc7dfd20
EH		 766 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
767 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 768 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
c1bb5418 769 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 770 NULL, NULL, NULL, NULL,
771 NULL, NULL, NULL, NULL,
772 "kvmclock-stable-bit", NULL, NULL, NULL,
773 NULL, NULL, NULL, NULL,
774 },
07585923 775 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 776 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 777 },
be777326 778 [FEAT_KVM_HINTS] = {
07585923 779 .type = CPUID_FEATURE_WORD,
be777326
WL		 780 .feat_names = {
781 "kvm-hint-dedicated", NULL, NULL, NULL,
782 NULL, NULL, NULL, NULL,
783 NULL, NULL, NULL, NULL,
784 NULL, NULL, NULL, NULL,
785 NULL, NULL, NULL, NULL,
786 NULL, NULL, NULL, NULL,
787 NULL, NULL, NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 },
07585923 790 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 791 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 792 /*
793 * KVM hints aren't auto-enabled by -cpu host, they need to be
794 * explicitly enabled in the command-line.
795 */
796 .no_autoenable_flags = ~0U,
be777326 797 },
bffd67b0 798 [FEAT_SVM] = {
07585923 799 .type = CPUID_FEATURE_WORD,
2d5312da 800 .feat_names = {
fc7dfd20
EH		 801 "npt", "lbrv", "svm-lock", "nrip-save",
802 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
803 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 804 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
805 "vgif", NULL, NULL, NULL,
2d5312da
EH		 806 NULL, NULL, NULL, NULL,
807 NULL, NULL, NULL, NULL,
5447089c 808 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 809 },
07585923 810 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 811 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 812 },
813 [FEAT_7_0_EBX] = {
07585923 814 .type = CPUID_FEATURE_WORD,
2d5312da 815 .feat_names = {
5c76b651 816 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 817 "hle", "avx2", NULL, "smep",
818 "bmi2", "erms", "invpcid", "rtm",
819 NULL, NULL, "mpx", NULL,
820 "avx512f", "avx512dq", "rdseed", "adx",
821 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 822 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 823 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 824 },
07585923
RH		 825 .cpuid = {
826 .eax = 7,
827 .needs_ecx = true, .ecx = 0,
828 .reg = R_EBX,
829 },
37ce3522 830 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 831 },
f74eefe0 832 [FEAT_7_0_ECX] = {
07585923 833 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 834 .feat_names = {
835 NULL, "avx512vbmi", "umip", "pku",
67192a29 836 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 837 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
838 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 839 "la57", NULL, NULL, NULL,
2d5312da 840 NULL, NULL, "rdpid", NULL,
06e878b4 841 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 842 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 843 },
07585923
RH		 844 .cpuid = {
845 .eax = 7,
846 .needs_ecx = true, .ecx = 0,
847 .reg = R_ECX,
848 },
f74eefe0
HH		 849 .tcg_features = TCG_7_0_ECX_FEATURES,
850 },
95ea69fb 851 [FEAT_7_0_EDX] = {
07585923 852 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 853 .feat_names = {
854 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 855 "fsrm", NULL, NULL, NULL,
353f98c9 856 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 857 NULL, NULL, "serialize", NULL,
b3c7344e 858 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
f21a4817
JL		 859 NULL, NULL, "amx-bf16", "avx512-fp16",
860 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
597360c0 861 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 862 },
07585923
RH		 863 .cpuid = {
864 .eax = 7,
865 .needs_ecx = true, .ecx = 0,
866 .reg = R_EDX,
867 },
95ea69fb
LK		 868 .tcg_features = TCG_7_0_EDX_FEATURES,
869 },
80db491d
JL		 870 [FEAT_7_1_EAX] = {
871 .type = CPUID_FEATURE_WORD,
872 .feat_names = {
873 NULL, NULL, NULL, NULL,
c1826ea6 874 "avx-vnni", "avx512-bf16", NULL, NULL,
80db491d
JL		 875 NULL, NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
882 .cpuid = {
883 .eax = 7,
884 .needs_ecx = true, .ecx = 1,
885 .reg = R_EAX,
886 },
887 .tcg_features = TCG_7_1_EAX_FEATURES,
888 },
303752a9 889 [FEAT_8000_0007_EDX] = {
07585923 890 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 891 .feat_names = {
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 "invtsc", NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, NULL, NULL, NULL,
898 NULL, NULL, NULL, NULL,
899 NULL, NULL, NULL, NULL,
900 },
07585923 901 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 902 .tcg_features = TCG_APM_FEATURES,
903 .unmigratable_flags = CPUID_APM_INVTSC,
904 },
1b3420e1 905 [FEAT_8000_0008_EBX] = {
07585923 906 .type = CPUID_FEATURE_WORD,
1b3420e1 907 .feat_names = {
e900135d 908 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 909 NULL, NULL, NULL, NULL,
59a80a19 910 NULL, "wbnoinvd", NULL, NULL,
623972ce 911 "ibpb", NULL, "ibrs", "amd-stibp",
1b3420e1
EH		 912 NULL, NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
254790a9 914 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 915 NULL, NULL, NULL, NULL,
916 },
07585923 917 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 918 .tcg_features = 0,
919 .unmigratable_flags = 0,
920 },
0bb0b2d2 921 [FEAT_XSAVE] = {
07585923 922 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 923 .feat_names = {
924 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
f21a4817 925 "xfd", NULL, NULL, NULL,
2d5312da
EH		 926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 NULL, NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 },
07585923
RH		 933 .cpuid = {
934 .eax = 0xd,
935 .needs_ecx = true, .ecx = 1,
936 .reg = R_EAX,
937 },
c9cfe8f9 938 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 939 },
301e9067
YW		 940 [FEAT_XSAVE_XSS_LO] = {
941 .type = CPUID_FEATURE_WORD,
942 .feat_names = {
943 NULL, NULL, NULL, NULL,
944 NULL, NULL, NULL, NULL,
945 NULL, NULL, NULL, NULL,
946 NULL, NULL, NULL, NULL,
947 NULL, NULL, NULL, NULL,
948 NULL, NULL, NULL, NULL,
949 NULL, NULL, NULL, NULL,
950 NULL, NULL, NULL, NULL,
951 },
952 .cpuid = {
953 .eax = 0xD,
954 .needs_ecx = true,
955 .ecx = 1,
956 .reg = R_ECX,
957 },
958 },
959 [FEAT_XSAVE_XSS_HI] = {
960 .type = CPUID_FEATURE_WORD,
961 .cpuid = {
962 .eax = 0xD,
963 .needs_ecx = true,
964 .ecx = 1,
965 .reg = R_EDX
966 },
967 },
28b8e4d0 968 [FEAT_6_EAX] = {
07585923 969 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 970 .feat_names = {
971 NULL, NULL, "arat", NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 NULL, NULL, NULL, NULL,
978 NULL, NULL, NULL, NULL,
979 },
07585923 980 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 981 .tcg_features = TCG_6_EAX_FEATURES,
982 },
301e9067 983 [FEAT_XSAVE_XCR0_LO] = {
07585923
RH		 984 .type = CPUID_FEATURE_WORD,
985 .cpuid = {
986 .eax = 0xD,
987 .needs_ecx = true, .ecx = 0,
988 .reg = R_EAX,
989 },
96193c22 990 .tcg_features = ~0U,
6fb2fff7
EH		 991 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
992 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
993 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
994 XSTATE_PKRU_MASK,
96193c22 995 },
301e9067 996 [FEAT_XSAVE_XCR0_HI] = {
07585923
RH		 997 .type = CPUID_FEATURE_WORD,
998 .cpuid = {
999 .eax = 0xD,
1000 .needs_ecx = true, .ecx = 0,
1001 .reg = R_EDX,
1002 },
96193c22
EH		 1003 .tcg_features = ~0U,
1004 },
d86f9636
RH		 1005 /*Below are MSR exposed features*/
1006 [FEAT_ARCH_CAPABILITIES] = {
1007 .type = MSR_FEATURE_WORD,
1008 .feat_names = {
1009 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1010 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1011 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 },
1018 .msr = {
1019 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 1020 },
1021 },
597360c0
XL		 1022 [FEAT_CORE_CAPABILITY] = {
1023 .type = MSR_FEATURE_WORD,
1024 .feat_names = {
1025 NULL, NULL, NULL, NULL,
1026 NULL, "split-lock-detect", NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 },
1034 .msr = {
1035 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1036 },
1037 },
ea39f9b6
LX		 1038 [FEAT_PERF_CAPABILITIES] = {
1039 .type = MSR_FEATURE_WORD,
1040 .feat_names = {
1041 NULL, NULL, NULL, NULL,
1042 NULL, NULL, NULL, NULL,
1043 NULL, NULL, NULL, NULL,
1044 NULL, "full-width-write", NULL, NULL,
1045 NULL, NULL, NULL, NULL,
1046 NULL, NULL, NULL, NULL,
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 },
1050 .msr = {
1051 .index = MSR_IA32_PERF_CAPABILITIES,
1052 },
1053 },
20a78b02
PB		 1054
1055 [FEAT_VMX_PROCBASED_CTLS] = {
1056 .type = MSR_FEATURE_WORD,
1057 .feat_names = {
1058 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1059 NULL, NULL, NULL, "vmx-hlt-exit",
1060 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1061 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1062 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1063 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1064 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1065 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1066 },
1067 .msr = {
1068 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1069 }
1070 },
1071
1072 [FEAT_VMX_SECONDARY_CTLS] = {
1073 .type = MSR_FEATURE_WORD,
1074 .feat_names = {
1075 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1076 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1077 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1078 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1079 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1080 "vmx-xsaves", NULL, NULL, NULL,
9ce8af4d 1081 NULL, "vmx-tsc-scaling", NULL, NULL,
20a78b02
PB		 1082 NULL, NULL, NULL, NULL,
1083 },
1084 .msr = {
1085 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1086 }
1087 },
1088
1089 [FEAT_VMX_PINBASED_CTLS] = {
1090 .type = MSR_FEATURE_WORD,
1091 .feat_names = {
1092 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1093 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL,
1100 },
1101 .msr = {
1102 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1103 }
1104 },
1105
1106 [FEAT_VMX_EXIT_CTLS] = {
1107 .type = MSR_FEATURE_WORD,
1108 /*
1109 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1110 * the LM CPUID bit.
1111 */
1112 .feat_names = {
1113 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1116 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1117 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1118 "vmx-exit-save-efer", "vmx-exit-load-efer",
1119 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1120 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1121 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1122 },
1123 .msr = {
1124 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1125 }
1126 },
1127
1128 [FEAT_VMX_ENTRY_CTLS] = {
1129 .type = MSR_FEATURE_WORD,
1130 .feat_names = {
1131 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1134 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1135 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1136 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 },
1140 .msr = {
1141 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1142 }
1143 },
1144
1145 [FEAT_VMX_MISC] = {
1146 .type = MSR_FEATURE_WORD,
1147 .feat_names = {
1148 NULL, NULL, NULL, NULL,
1149 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1150 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1156 },
1157 .msr = {
1158 .index = MSR_IA32_VMX_MISC,
1159 }
1160 },
1161
1162 [FEAT_VMX_EPT_VPID_CAPS] = {
1163 .type = MSR_FEATURE_WORD,
1164 .feat_names = {
1165 "vmx-ept-execonly", NULL, NULL, NULL,
1166 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1167 NULL, NULL, NULL, NULL,
1168 NULL, NULL, NULL, NULL,
1169 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1170 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1171 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1172 NULL, NULL, NULL, NULL,
1173 "vmx-invvpid", NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1176 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1177 NULL, NULL, NULL, NULL,
1178 NULL, NULL, NULL, NULL,
1179 NULL, NULL, NULL, NULL,
1180 NULL, NULL, NULL, NULL,
1181 NULL, NULL, NULL, NULL,
1182 },
1183 .msr = {
1184 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1185 }
1186 },
1187
1188 [FEAT_VMX_BASIC] = {
1189 .type = MSR_FEATURE_WORD,
1190 .feat_names = {
1191 [54] = "vmx-ins-outs",
1192 [55] = "vmx-true-ctls",
1193 },
1194 .msr = {
1195 .index = MSR_IA32_VMX_BASIC,
1196 },
1197 /* Just to be safe - we don't support setting the MSEG version field. */
1198 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1199 },
1200
1201 [FEAT_VMX_VMFUNC] = {
1202 .type = MSR_FEATURE_WORD,
1203 .feat_names = {
1204 [0] = "vmx-eptp-switching",
1205 },
1206 .msr = {
1207 .index = MSR_IA32_VMX_VMFUNC,
1208 }
1209 },
1210
d1615ea5
LK		 1211 [FEAT_14_0_ECX] = {
1212 .type = CPUID_FEATURE_WORD,
1213 .feat_names = {
1214 NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 NULL, NULL, NULL, NULL,
1217 NULL, NULL, NULL, NULL,
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, NULL,
1221 NULL, NULL, NULL, "intel-pt-lip",
1222 },
1223 .cpuid = {
1224 .eax = 0x14,
1225 .needs_ecx = true, .ecx = 0,
1226 .reg = R_ECX,
1227 },
1228 .tcg_features = TCG_14_0_ECX_FEATURES,
1229 },
1230
4b841a79
SC		 1231 [FEAT_SGX_12_0_EAX] = {
1232 .type = CPUID_FEATURE_WORD,
1233 .feat_names = {
1234 "sgx1", "sgx2", NULL, NULL,
1235 NULL, NULL, NULL, NULL,
1236 NULL, NULL, NULL, NULL,
1237 NULL, NULL, NULL, NULL,
1238 NULL, NULL, NULL, NULL,
1239 NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL,
1242 },
1243 .cpuid = {
1244 .eax = 0x12,
1245 .needs_ecx = true, .ecx = 0,
1246 .reg = R_EAX,
1247 },
1248 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1249 },
120ca112
SC		 1250
1251 [FEAT_SGX_12_0_EBX] = {
1252 .type = CPUID_FEATURE_WORD,
1253 .feat_names = {
1254 "sgx-exinfo" , NULL, NULL, NULL,
1255 NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL, NULL,
1257 NULL, NULL, NULL, NULL,
1258 NULL, NULL, NULL, NULL,
1259 NULL, NULL, NULL, NULL,
1260 NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL,
1262 },
1263 .cpuid = {
1264 .eax = 0x12,
1265 .needs_ecx = true, .ecx = 0,
1266 .reg = R_EBX,
1267 },
1268 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1269 },
165981a5
SC		 1270
1271 [FEAT_SGX_12_1_EAX] = {
1272 .type = CPUID_FEATURE_WORD,
1273 .feat_names = {
1274 NULL, "sgx-debug", "sgx-mode64", NULL,
1275 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1276 NULL, NULL, NULL, NULL,
1277 NULL, NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 NULL, NULL, NULL, NULL,
1280 NULL, NULL, NULL, NULL,
1281 NULL, NULL, NULL, NULL,
1282 },
1283 .cpuid = {
1284 .eax = 0x12,
1285 .needs_ecx = true, .ecx = 1,
1286 .reg = R_EAX,
1287 },
1288 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1289 },
5ef57876
EH		 1290};
1291
99e24dbd
PB		 1292typedef struct FeatureMask {
1293 FeatureWord index;
ede146c2 1294 uint64_t mask;
99e24dbd
PB		 1295} FeatureMask;
1296
1297typedef struct FeatureDep {
1298 FeatureMask from, to;
1299} FeatureDep;
1300
1301static FeatureDep feature_dependencies[] = {
1302 {
1303 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1304 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1305 },
1306 {
1307 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1308 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1309 },
ea39f9b6
LX		 1310 {
1311 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1312 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1313 },
20a78b02
PB		 1314 {
1315 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1316 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1317 },
1318 {
1319 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1320 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1321 },
1322 {
1323 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1324 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1325 },
1326 {
1327 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1328 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1329 },
1330 {
1331 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1332 .to = { FEAT_VMX_MISC, ~0ull },
1333 },
1334 {
1335 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1336 .to = { FEAT_VMX_BASIC, ~0ull },
1337 },
1338 {
1339 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1340 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1341 },
1342 {
1343 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1344 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1345 },
1346 {
1347 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1348 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1349 },
1350 {
1351 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1352 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1353 },
1354 {
1355 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1356 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1357 },
1358 {
1359 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1360 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1361 },
d1615ea5
LK		 1362 {
1363 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1364 .to = { FEAT_14_0_ECX, ~0ull },
1365 },
20a78b02
PB		 1366 {
1367 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1368 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1369 },
1370 {
1371 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1372 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1373 },
1374 {
1375 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1376 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1377 },
1378 {
1379 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1380 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1381 },
1382 {
1383 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1384 .to = { FEAT_VMX_VMFUNC, ~0ull },
1385 },
730319ae
EH		 1386 {
1387 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1388 .to = { FEAT_SVM, ~0ull },
1389 },
99e24dbd
PB		 1390};
1391
8e8aba50
EH		 1392typedef struct X86RegisterInfo32 {
1393 /* Name of register */
1394 const char *name;
1395 /* QAPI enum value register */
1396 X86CPURegister32 qapi_enum;
1397} X86RegisterInfo32;
1398
1399#define REGISTER(reg) \
5d371f41 1400 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1401static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1402 REGISTER(EAX),
1403 REGISTER(ECX),
1404 REGISTER(EDX),
1405 REGISTER(EBX),
1406 REGISTER(ESP),
1407 REGISTER(EBP),
1408 REGISTER(ESI),
1409 REGISTER(EDI),
1410};
1411#undef REGISTER
1412
301e9067 1413/* CPUID feature bits available in XSS */
10f0abcb 1414#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
301e9067 1415
fea45008 1416ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1417 [XSTATE_FP_BIT] = {
1418 /* x87 FP state component is always enabled if XSAVE is supported */
1419 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1420 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1421 },
1422 [XSTATE_SSE_BIT] = {
1423 /* SSE state component is always enabled if XSAVE is supported */
1424 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1425 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1426 },
cfc3b074
PB		 1427 [XSTATE_YMM_BIT] =
1428 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1429 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1430 [XSTATE_BNDREGS_BIT] =
1431 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1432 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1433 [XSTATE_BNDCSR_BIT] =
1434 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1435 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1436 [XSTATE_OPMASK_BIT] =
1437 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1438 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1439 [XSTATE_ZMM_Hi256_BIT] =
1440 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1441 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1442 [XSTATE_Hi16_ZMM_BIT] =
1443 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1444 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1445 [XSTATE_PKRU_BIT] =
1446 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1447 .size = sizeof(XSavePKRU) },
10f0abcb
YW		 1448 [XSTATE_ARCH_LBR_BIT] = {
1449 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
1450 .offset = 0 /*supervisor mode component, offset = 0 */,
1451 .size = sizeof(XSavesArchLBR) },
1f16764f
JL		 1452 [XSTATE_XTILE_CFG_BIT] = {
1453 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1454 .size = sizeof(XSaveXTILECFG),
1455 },
1456 [XSTATE_XTILE_DATA_BIT] = {
1457 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1458 .size = sizeof(XSaveXTILEDATA)
1459 },
2560f19f 1460};
8e8aba50 1461
301e9067 1462static uint32_t xsave_area_size(uint64_t mask, bool compacted)
1fda6198 1463{
301e9067
YW		 1464 uint64_t ret = x86_ext_save_areas[0].size;
1465 const ExtSaveArea *esa;
1466 uint32_t offset = 0;
1fda6198 1467 int i;
1fda6198 1468
301e9067
YW		 1469 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1470 esa = &x86_ext_save_areas[i];
1fda6198 1471 if ((mask >> i) & 1) {
301e9067
YW		 1472 offset = compacted ? ret : esa->offset;
1473 ret = MAX(ret, offset + esa->size);
1fda6198
EH		 1474 }
1475 }
1476 return ret;
1477}
1478
d6dcc558
SAGDR		 1479static inline bool accel_uses_host_cpuid(void)
1480{
1481 return kvm_enabled() || hvf_enabled();
1482}
1483
301e9067 1484static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu)
96193c22 1485{
301e9067
YW		 1486 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 |
1487 cpu->env.features[FEAT_XSAVE_XCR0_LO];
96193c22
EH		 1488}
1489
ed69e831
CF		 1490/* Return name of 32-bit register, from a R_* constant */
1491static const char *get_register_name_32(unsigned int reg)
8b4beddc 1492{
31ccdde2 1493 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1494 return NULL;
1495 }
8e8aba50 1496 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1497}
1498
301e9067
YW		 1499static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu)
1500{
1501 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 |
1502 cpu->env.features[FEAT_XSAVE_XSS_LO];
1503}
1504
84f1b92f
EH		 1505/*
1506 * Returns the set of feature flags that are supported and migratable by
1507 * QEMU, for a given FeatureWord.
1508 */
ede146c2 1509static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1510{
1511 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1512 uint64_t r = 0;
84f1b92f
EH		 1513 int i;
1514
ede146c2
PB		 1515 for (i = 0; i < 64; i++) {
1516 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1517
1518 /* If the feature name is known, it is implicitly considered migratable,
1519 * unless it is explicitly set in unmigratable_flags */
1520 if ((wi->migratable_flags & f) ||
1521 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1522 r |= f;
84f1b92f 1523 }
84f1b92f
EH		 1524 }
1525 return r;
1526}
1527
bb44e0d1
JK		 1528void host_cpuid(uint32_t function, uint32_t count,
1529 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1530{
a1fd24af
AL		 1531 uint32_t vec[4];
1532
1533#ifdef __x86_64__
1534 asm volatile("cpuid"
1535 : "=a"(vec[0]), "=b"(vec[1]),
1536 "=c"(vec[2]), "=d"(vec[3])
1537 : "0"(function), "c"(count) : "cc");
c1f41226 1538#elif defined(__i386__)
a1fd24af
AL		 1539 asm volatile("pusha \n\t"
1540 "cpuid \n\t"
1541 "mov %%eax, 0(%2) \n\t"
1542 "mov %%ebx, 4(%2) \n\t"
1543 "mov %%ecx, 8(%2) \n\t"
1544 "mov %%edx, 12(%2) \n\t"
1545 "popa"
1546 : : "a"(function), "c"(count), "S"(vec)
1547 : "memory", "cc");
c1f41226
EH		 1548#else
1549 abort();
a1fd24af
AL		 1550#endif
1551
bdde476a 1552 if (eax)
a1fd24af 1553 *eax = vec[0];
bdde476a 1554 if (ebx)
a1fd24af 1555 *ebx = vec[1];
bdde476a 1556 if (ecx)
a1fd24af 1557 *ecx = vec[2];
bdde476a 1558 if (edx)
a1fd24af 1559 *edx = vec[3];
bdde476a 1560}
c6dc6f63 1561
d940ee9b
EH		 1562/* CPU class name definitions: */
1563
d940ee9b
EH		 1564/* Return type name for a given CPU model name
1565 * Caller is responsible for freeing the returned string.
1566 */
1567static char *x86_cpu_type_name(const char *model_name)
1568{
1569 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1570}
1571
500050d1
AF		 1572static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1573{
88703ce2
EH		 1574 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1575 return object_class_by_name(typename);
500050d1
AF		 1576}
1577
104494ea
IM		 1578static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1579{
1580 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1581 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1582 return g_strndup(class_name,
1583 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1584}
1585
dcafd1ef
EH		 1586typedef struct X86CPUVersionDefinition {
1587 X86CPUVersion version;
53db89d9 1588 const char *alias;
c63938df 1589 const char *note;
dcafd1ef
EH		 1590 PropValue *props;
1591} X86CPUVersionDefinition;
1592
1593/* Base definition for a CPU model */
1594typedef struct X86CPUDefinition {
c6dc6f63
AP		 1595 const char *name;
1596 uint32_t level;
90e4b0c3 1597 uint32_t xlevel;
99b88a17
IM		 1598 /* vendor is zero-terminated, 12 character ASCII string */
1599 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1600 int family;
1601 int model;
1602 int stepping;
0514ef2f 1603 FeatureWordArray features;
807e9869 1604 const char *model_id;
e845de38 1605 const CPUCaches *const cache_info;
dcafd1ef
EH		 1606 /*
1607 * Definitions for alternative versions of CPU model.
1608 * List is terminated by item with version == 0.
1609 * If NULL, version 1 will be registered automatically.
1610 */
1611 const X86CPUVersionDefinition *versions;
61ad65d0 1612 const char *deprecation_note;
dcafd1ef
EH		 1613} X86CPUDefinition;
1614
1615/* Reference to a specific CPU model version */
1616struct X86CPUModel {
1617 /* Base CPU definition */
e11fd689 1618 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1619 /* CPU model version */
1620 X86CPUVersion version;
c63938df 1621 const char *note;
0788a56b
EH		 1622 /*
1623 * If true, this is an alias CPU model.
1624 * This matters only for "-cpu help" and query-cpu-definitions
1625 */
1626 bool is_alias;
d940ee9b 1627};
c6dc6f63 1628
dcafd1ef 1629/* Get full model name for CPU version */
e11fd689 1630static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1631 X86CPUVersion version)
1632{
1633 assert(version > 0);
1634 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1635}
1636
e11fd689
PMD		 1637static const X86CPUVersionDefinition *
1638x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1639{
1640 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1641 static const X86CPUVersionDefinition default_version_list[] = {
1642 { 1 },
1643 { /* end of list */ }
1644 };
1645
1646 return def->versions ?: default_version_list;
1647}
1648
e845de38 1649static const CPUCaches epyc_cache_info = {
a9f27ea9 1650 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1651 .type = DATA_CACHE,
fe52acd2
BM		 1652 .level = 1,
1653 .size = 32 * KiB,
1654 .line_size = 64,
1655 .associativity = 8,
1656 .partitions = 1,
1657 .sets = 64,
1658 .lines_per_tag = 1,
1659 .self_init = 1,
1660 .no_invd_sharing = true,
1661 },
a9f27ea9 1662 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1663 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1664 .level = 1,
1665 .size = 64 * KiB,
1666 .line_size = 64,
1667 .associativity = 4,
1668 .partitions = 1,
1669 .sets = 256,
1670 .lines_per_tag = 1,
1671 .self_init = 1,
1672 .no_invd_sharing = true,
1673 },
a9f27ea9 1674 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1675 .type = UNIFIED_CACHE,
1676 .level = 2,
1677 .size = 512 * KiB,
1678 .line_size = 64,
1679 .associativity = 8,
1680 .partitions = 1,
1681 .sets = 1024,
1682 .lines_per_tag = 1,
1683 },
a9f27ea9 1684 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1685 .type = UNIFIED_CACHE,
1686 .level = 3,
1687 .size = 8 * MiB,
1688 .line_size = 64,
1689 .associativity = 16,
1690 .partitions = 1,
1691 .sets = 8192,
1692 .lines_per_tag = 1,
1693 .self_init = true,
1694 .inclusive = true,
1695 .complex_indexing = true,
1696 },
1697};
1698
e845de38 1699static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1700 .l1d_cache = &(CPUCacheInfo) {
1701 .type = DATA_CACHE,
1702 .level = 1,
1703 .size = 32 * KiB,
1704 .line_size = 64,
1705 .associativity = 8,
1706 .partitions = 1,
1707 .sets = 64,
1708 .lines_per_tag = 1,
1709 .self_init = 1,
1710 .no_invd_sharing = true,
1711 },
1712 .l1i_cache = &(CPUCacheInfo) {
1713 .type = INSTRUCTION_CACHE,
1714 .level = 1,
1715 .size = 32 * KiB,
1716 .line_size = 64,
1717 .associativity = 8,
1718 .partitions = 1,
1719 .sets = 64,
1720 .lines_per_tag = 1,
1721 .self_init = 1,
1722 .no_invd_sharing = true,
1723 },
1724 .l2_cache = &(CPUCacheInfo) {
1725 .type = UNIFIED_CACHE,
1726 .level = 2,
1727 .size = 512 * KiB,
1728 .line_size = 64,
1729 .associativity = 8,
1730 .partitions = 1,
1731 .sets = 1024,
1732 .lines_per_tag = 1,
1733 },
1734 .l3_cache = &(CPUCacheInfo) {
1735 .type = UNIFIED_CACHE,
1736 .level = 3,
1737 .size = 16 * MiB,
1738 .line_size = 64,
1739 .associativity = 16,
1740 .partitions = 1,
1741 .sets = 16384,
1742 .lines_per_tag = 1,
1743 .self_init = true,
1744 .inclusive = true,
1745 .complex_indexing = true,
1746 },
1747};
1748
e845de38 1749static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 1750 .l1d_cache = &(CPUCacheInfo) {
1751 .type = DATA_CACHE,
1752 .level = 1,
1753 .size = 32 * KiB,
1754 .line_size = 64,
1755 .associativity = 8,
1756 .partitions = 1,
1757 .sets = 64,
1758 .lines_per_tag = 1,
1759 .self_init = 1,
1760 .no_invd_sharing = true,
1761 },
1762 .l1i_cache = &(CPUCacheInfo) {
1763 .type = INSTRUCTION_CACHE,
1764 .level = 1,
1765 .size = 32 * KiB,
1766 .line_size = 64,
1767 .associativity = 8,
1768 .partitions = 1,
1769 .sets = 64,
1770 .lines_per_tag = 1,
1771 .self_init = 1,
1772 .no_invd_sharing = true,
1773 },
1774 .l2_cache = &(CPUCacheInfo) {
1775 .type = UNIFIED_CACHE,
1776 .level = 2,
1777 .size = 512 * KiB,
1778 .line_size = 64,
1779 .associativity = 8,
1780 .partitions = 1,
1781 .sets = 1024,
1782 .lines_per_tag = 1,
1783 },
1784 .l3_cache = &(CPUCacheInfo) {
1785 .type = UNIFIED_CACHE,
1786 .level = 3,
1787 .size = 32 * MiB,
1788 .line_size = 64,
1789 .associativity = 16,
1790 .partitions = 1,
1791 .sets = 32768,
1792 .lines_per_tag = 1,
1793 .self_init = true,
1794 .inclusive = true,
1795 .complex_indexing = true,
1796 },
1797};
1798
0723cc8a
PB		 1799/* The following VMX features are not supported by KVM and are left out in the
1800 * CPU definitions:
1801 *
1802 * Dual-monitor support (all processors)
1803 * Entry to SMM
1804 * Deactivate dual-monitor treatment
1805 * Number of CR3-target values
1806 * Shutdown activity state
1807 * Wait-for-SIPI activity state
1808 * PAUSE-loop exiting (Westmere and newer)
1809 * EPT-violation #VE (Broadwell and newer)
1810 * Inject event with insn length=0 (Skylake and newer)
1811 * Conceal non-root operation from PT
1812 * Conceal VM exits from PT
1813 * Conceal VM entries from PT
1814 * Enable ENCLS exiting
1815 * Mode-based execute control (XS/XU)
1816 s TSC scaling (Skylake Server and newer)
1817 * GPA translation for PT (IceLake and newer)
1818 * User wait and pause
1819 * ENCLV exiting
1820 * Load IA32_RTIT_CTL
1821 * Clear IA32_RTIT_CTL
1822 * Advanced VM-exit information for EPT violations
1823 * Sub-page write permissions
1824 * PT in VMX operation
1825 */
1826
e11fd689 1827static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1828 {
1829 .name = "qemu64",
3046bb5d 1830 .level = 0xd,
99b88a17 1831 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 1832 .family = 15,
1833 .model = 107,
1834 .stepping = 1,
0514ef2f 1835 .features[FEAT_1_EDX] =
27861ecc 1836 PPRO_FEATURES |
c6dc6f63 1837 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1838 CPUID_PSE36,
0514ef2f 1839 .features[FEAT_1_ECX] =
6aa91e4a 1840 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1841 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1842 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1843 .features[FEAT_8000_0001_ECX] =
71195672 1844 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1845 .xlevel = 0x8000000A,
9cf2cc3d 1846 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1847 },
1848 {
1849 .name = "phenom",
1850 .level = 5,
99b88a17 1851 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1852 .family = 16,
1853 .model = 2,
1854 .stepping = 3,
b9fc20bc 1855 /* Missing: CPUID_HT */
0514ef2f 1856 .features[FEAT_1_EDX] =
27861ecc 1857 PPRO_FEATURES |
c6dc6f63 1858 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1859 CPUID_PSE36 | CPUID_VME,
0514ef2f 1860 .features[FEAT_1_ECX] =
27861ecc 1861 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1862 CPUID_EXT_POPCNT,
0514ef2f 1863 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1864 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1865 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1866 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1867 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1868 CPUID_EXT3_CR8LEG,
1869 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1870 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1871 .features[FEAT_8000_0001_ECX] =
27861ecc 1872 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1873 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1874 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1875 .features[FEAT_SVM] =
b9fc20bc 1876 CPUID_SVM_NPT,
c6dc6f63
AP		 1877 .xlevel = 0x8000001A,
1878 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1879 },
1880 {
1881 .name = "core2duo",
1882 .level = 10,
99b88a17 1883 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1884 .family = 6,
1885 .model = 15,
1886 .stepping = 11,
b9fc20bc 1887 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1888 .features[FEAT_1_EDX] =
27861ecc 1889 PPRO_FEATURES |
c6dc6f63 1890 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1891 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1892 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1893 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1894 .features[FEAT_1_ECX] =
27861ecc 1895 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1896 CPUID_EXT_CX16,
0514ef2f 1897 .features[FEAT_8000_0001_EDX] =
27861ecc 1898 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1899 .features[FEAT_8000_0001_ECX] =
27861ecc 1900 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1901 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1902 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1903 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1904 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1905 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1906 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1907 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1908 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1909 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1910 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1911 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1912 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1913 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1914 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1915 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1916 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1917 .features[FEAT_VMX_SECONDARY_CTLS] =
1918 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1919 .xlevel = 0x80000008,
1920 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1921 },
1922 {
1923 .name = "kvm64",
3046bb5d 1924 .level = 0xd,
99b88a17 1925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1926 .family = 15,
1927 .model = 6,
1928 .stepping = 1,
b3a4f0b1 1929 /* Missing: CPUID_HT */
0514ef2f 1930 .features[FEAT_1_EDX] =
b3a4f0b1 1931 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1932 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1933 CPUID_PSE36,
1934 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1935 .features[FEAT_1_ECX] =
27861ecc 1936 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1937 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1938 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1939 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1940 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1941 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1942 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1943 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1944 .features[FEAT_8000_0001_ECX] =
27861ecc 1945 0,
0723cc8a
PB		 1946 /* VMX features from Cedar Mill/Prescott */
1947 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1948 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1949 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1950 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1951 VMX_PIN_BASED_NMI_EXITING,
1952 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1953 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1954 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1955 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1956 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1957 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1958 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1959 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1960 .xlevel = 0x80000008,
1961 .model_id = "Common KVM processor"
1962 },
c6dc6f63
AP		 1963 {
1964 .name = "qemu32",
1965 .level = 4,
99b88a17 1966 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1967 .family = 6,
f8e6a11a 1968 .model = 6,
c6dc6f63 1969 .stepping = 3,
0514ef2f 1970 .features[FEAT_1_EDX] =
27861ecc 1971 PPRO_FEATURES,
0514ef2f 1972 .features[FEAT_1_ECX] =
6aa91e4a 1973 CPUID_EXT_SSE3,
58012d66 1974 .xlevel = 0x80000004,
9cf2cc3d 1975 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1976 },
eafaf1e5
AP		 1977 {
1978 .name = "kvm32",
1979 .level = 5,
99b88a17 1980 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1981 .family = 15,
1982 .model = 6,
1983 .stepping = 1,
0514ef2f 1984 .features[FEAT_1_EDX] =
b3a4f0b1 1985 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1986 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1987 .features[FEAT_1_ECX] =
27861ecc 1988 CPUID_EXT_SSE3,
0514ef2f 1989 .features[FEAT_8000_0001_ECX] =
27861ecc 1990 0,
0723cc8a
PB		 1991 /* VMX features from Yonah */
1992 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1993 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1994 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1995 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1996 VMX_PIN_BASED_NMI_EXITING,
1997 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1998 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1999 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2000 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2001 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2002 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2003 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 2004 .xlevel = 0x80000008,
2005 .model_id = "Common 32-bit KVM processor"
2006 },
c6dc6f63
AP		 2007 {
2008 .name = "coreduo",
2009 .level = 10,
99b88a17 2010 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2011 .family = 6,
2012 .model = 14,
2013 .stepping = 8,
b9fc20bc 2014 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2015 .features[FEAT_1_EDX] =
27861ecc 2016 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 2017 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2018 CPUID_SS,
2019 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 2020 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2021 .features[FEAT_1_ECX] =
e93abc14 2022 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 2023 .features[FEAT_8000_0001_EDX] =
27861ecc 2024 CPUID_EXT2_NX,
0723cc8a
PB		 2025 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2026 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2027 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2028 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2029 VMX_PIN_BASED_NMI_EXITING,
2030 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2031 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2032 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2033 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2034 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2035 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2036 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2037 .xlevel = 0x80000008,
2038 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2039 },
2040 {
2041 .name = "486",
58012d66 2042 .level = 1,
99b88a17 2043 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2044 .family = 4,
b2a856d9 2045 .model = 8,
c6dc6f63 2046 .stepping = 0,
0514ef2f 2047 .features[FEAT_1_EDX] =
27861ecc 2048 I486_FEATURES,
c6dc6f63 2049 .xlevel = 0,
807e9869 2050 .model_id = "",
c6dc6f63
AP		 2051 },
2052 {
2053 .name = "pentium",
2054 .level = 1,
99b88a17 2055 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2056 .family = 5,
2057 .model = 4,
2058 .stepping = 3,
0514ef2f 2059 .features[FEAT_1_EDX] =
27861ecc 2060 PENTIUM_FEATURES,
c6dc6f63 2061 .xlevel = 0,
807e9869 2062 .model_id = "",
c6dc6f63
AP		 2063 },
2064 {
2065 .name = "pentium2",
2066 .level = 2,
99b88a17 2067 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2068 .family = 6,
2069 .model = 5,
2070 .stepping = 2,
0514ef2f 2071 .features[FEAT_1_EDX] =
27861ecc 2072 PENTIUM2_FEATURES,
c6dc6f63 2073 .xlevel = 0,
807e9869 2074 .model_id = "",
c6dc6f63
AP		 2075 },
2076 {
2077 .name = "pentium3",
3046bb5d 2078 .level = 3,
99b88a17 2079 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2080 .family = 6,
2081 .model = 7,
2082 .stepping = 3,
0514ef2f 2083 .features[FEAT_1_EDX] =
27861ecc 2084 PENTIUM3_FEATURES,
c6dc6f63 2085 .xlevel = 0,
807e9869 2086 .model_id = "",
c6dc6f63
AP		 2087 },
2088 {
2089 .name = "athlon",
2090 .level = 2,
99b88a17 2091 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2092 .family = 6,
2093 .model = 2,
2094 .stepping = 3,
0514ef2f 2095 .features[FEAT_1_EDX] =
27861ecc 2096 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2097 CPUID_MCA,
0514ef2f 2098 .features[FEAT_8000_0001_EDX] =
60032ac0 2099 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2100 .xlevel = 0x80000008,
9cf2cc3d 2101 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2102 },
2103 {
2104 .name = "n270",
3046bb5d 2105 .level = 10,
99b88a17 2106 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2107 .family = 6,
2108 .model = 28,
2109 .stepping = 2,
b9fc20bc 2110 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2111 .features[FEAT_1_EDX] =
27861ecc 2112 PPRO_FEATURES |
b9fc20bc
EH		 2113 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2114 CPUID_ACPI | CPUID_SS,
c6dc6f63 2115 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2116 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2117 * CPUID_EXT_XTPR */
0514ef2f 2118 .features[FEAT_1_ECX] =
27861ecc 2119 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2120 CPUID_EXT_MOVBE,
0514ef2f 2121 .features[FEAT_8000_0001_EDX] =
60032ac0 2122 CPUID_EXT2_NX,
0514ef2f 2123 .features[FEAT_8000_0001_ECX] =
27861ecc 2124 CPUID_EXT3_LAHF_LM,
3046bb5d 2125 .xlevel = 0x80000008,
c6dc6f63
AP		 2126 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2127 },
3eca4642
EH		 2128 {
2129 .name = "Conroe",
3046bb5d 2130 .level = 10,
99b88a17 2131 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2132 .family = 6,
ffce9ebb 2133 .model = 15,
3eca4642 2134 .stepping = 3,
0514ef2f 2135 .features[FEAT_1_EDX] =
b3a4f0b1 2136 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2137 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2138 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2139 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2140 CPUID_DE | CPUID_FP87,
0514ef2f 2141 .features[FEAT_1_ECX] =
27861ecc 2142 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2143 .features[FEAT_8000_0001_EDX] =
27861ecc 2144 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2145 .features[FEAT_8000_0001_ECX] =
27861ecc 2146 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2147 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2148 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2149 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2150 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2151 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2152 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2153 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2154 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2155 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2156 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2157 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2158 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2159 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2160 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2161 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2162 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2163 .features[FEAT_VMX_SECONDARY_CTLS] =
2164 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2165 .xlevel = 0x80000008,
3eca4642
EH		 2166 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2167 },
2168 {
2169 .name = "Penryn",
3046bb5d 2170 .level = 10,
99b88a17 2171 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2172 .family = 6,
ffce9ebb 2173 .model = 23,
3eca4642 2174 .stepping = 3,
0514ef2f 2175 .features[FEAT_1_EDX] =
b3a4f0b1 2176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2180 CPUID_DE | CPUID_FP87,
0514ef2f 2181 .features[FEAT_1_ECX] =
27861ecc 2182 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2183 CPUID_EXT_SSE3,
0514ef2f 2184 .features[FEAT_8000_0001_EDX] =
27861ecc 2185 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2186 .features[FEAT_8000_0001_ECX] =
27861ecc 2187 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2188 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2189 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2190 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2191 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2192 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2193 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2194 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2195 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2196 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2197 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2198 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2199 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2200 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2201 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2202 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2203 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2204 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2205 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2206 .features[FEAT_VMX_SECONDARY_CTLS] =
2207 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2208 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2209 .xlevel = 0x80000008,
3eca4642
EH		 2210 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2211 },
2212 {
2213 .name = "Nehalem",
3046bb5d 2214 .level = 11,
99b88a17 2215 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2216 .family = 6,
ffce9ebb 2217 .model = 26,
3eca4642 2218 .stepping = 3,
0514ef2f 2219 .features[FEAT_1_EDX] =
b3a4f0b1 2220 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2221 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2222 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2223 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2224 CPUID_DE | CPUID_FP87,
0514ef2f 2225 .features[FEAT_1_ECX] =
27861ecc 2226 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2227 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2228 .features[FEAT_8000_0001_EDX] =
27861ecc 2229 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2230 .features[FEAT_8000_0001_ECX] =
27861ecc 2231 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2232 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2233 MSR_VMX_BASIC_TRUE_CTLS,
2234 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2235 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2236 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2237 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2238 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2239 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2240 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2241 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2242 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2243 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2244 .features[FEAT_VMX_EXIT_CTLS] =
2245 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2246 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2247 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2248 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2249 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2250 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2251 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2252 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2253 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2254 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2255 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2256 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2257 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2258 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2259 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2260 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2261 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2262 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2263 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2264 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2265 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2266 .features[FEAT_VMX_SECONDARY_CTLS] =
2267 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2268 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2269 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2270 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2271 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2272 .xlevel = 0x80000008,
3eca4642 2273 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2274 .versions = (X86CPUVersionDefinition[]) {
2275 { .version = 1 },
2276 {
2277 .version = 2,
53db89d9 2278 .alias = "Nehalem-IBRS",
d86a7088
EH		 2279 .props = (PropValue[]) {
2280 { "spec-ctrl", "on" },
2281 { "model-id",
2282 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2283 { /* end of list */ }
2284 }
2285 },
2286 { /* end of list */ }
2287 }
3eca4642
EH		 2288 },
2289 {
2290 .name = "Westmere",
2291 .level = 11,
99b88a17 2292 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2293 .family = 6,
2294 .model = 44,
2295 .stepping = 1,
0514ef2f 2296 .features[FEAT_1_EDX] =
b3a4f0b1 2297 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2298 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2299 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2300 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2301 CPUID_DE | CPUID_FP87,
0514ef2f 2302 .features[FEAT_1_ECX] =
27861ecc 2303 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2304 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2305 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2306 .features[FEAT_8000_0001_EDX] =
27861ecc 2307 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2308 .features[FEAT_8000_0001_ECX] =
27861ecc 2309 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2310 .features[FEAT_6_EAX] =
2311 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2312 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2313 MSR_VMX_BASIC_TRUE_CTLS,
2314 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2315 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2316 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2317 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2318 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2319 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2320 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2321 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2322 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2323 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2324 .features[FEAT_VMX_EXIT_CTLS] =
2325 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2326 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2327 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2328 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2329 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2330 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2331 MSR_VMX_MISC_STORE_LMA,
2332 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2333 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2334 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2335 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2336 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2337 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2338 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2339 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2340 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2341 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2342 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2343 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2344 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2345 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2346 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2347 .features[FEAT_VMX_SECONDARY_CTLS] =
2348 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2349 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2350 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2351 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2352 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2353 .xlevel = 0x80000008,
3eca4642 2354 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2355 .versions = (X86CPUVersionDefinition[]) {
2356 { .version = 1 },
2357 {
2358 .version = 2,
53db89d9 2359 .alias = "Westmere-IBRS",
d86a7088
EH		 2360 .props = (PropValue[]) {
2361 { "spec-ctrl", "on" },
2362 { "model-id",
2363 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2364 { /* end of list */ }
2365 }
2366 },
2367 { /* end of list */ }
2368 }
3eca4642
EH		 2369 },
2370 {
2371 .name = "SandyBridge",
2372 .level = 0xd,
99b88a17 2373 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2374 .family = 6,
2375 .model = 42,
2376 .stepping = 1,
0514ef2f 2377 .features[FEAT_1_EDX] =
b3a4f0b1 2378 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2379 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2380 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2381 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2382 CPUID_DE | CPUID_FP87,
0514ef2f 2383 .features[FEAT_1_ECX] =
27861ecc 2384 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2385 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2386 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2387 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2388 CPUID_EXT_SSE3,
0514ef2f 2389 .features[FEAT_8000_0001_EDX] =
27861ecc 2390 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2391 CPUID_EXT2_SYSCALL,
0514ef2f 2392 .features[FEAT_8000_0001_ECX] =
27861ecc 2393 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2394 .features[FEAT_XSAVE] =
2395 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2396 .features[FEAT_6_EAX] =
2397 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2398 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2399 MSR_VMX_BASIC_TRUE_CTLS,
2400 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2401 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2402 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2403 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2404 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2405 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2406 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2407 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2408 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2409 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2410 .features[FEAT_VMX_EXIT_CTLS] =
2411 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2412 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2413 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2414 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2415 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2416 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2417 MSR_VMX_MISC_STORE_LMA,
2418 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2419 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2420 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2421 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2422 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2423 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2424 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2425 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2426 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2427 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2428 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2429 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2430 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2431 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2432 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2433 .features[FEAT_VMX_SECONDARY_CTLS] =
2434 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2435 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2436 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2437 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2438 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2439 .xlevel = 0x80000008,
3eca4642 2440 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2441 .versions = (X86CPUVersionDefinition[]) {
2442 { .version = 1 },
2443 {
2444 .version = 2,
53db89d9 2445 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2446 .props = (PropValue[]) {
2447 { "spec-ctrl", "on" },
2448 { "model-id",
2449 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2450 { /* end of list */ }
2451 }
2452 },
2453 { /* end of list */ }
2454 }
3eca4642 2455 },
2f9ac42a
PB		 2456 {
2457 .name = "IvyBridge",
2458 .level = 0xd,
2459 .vendor = CPUID_VENDOR_INTEL,
2460 .family = 6,
2461 .model = 58,
2462 .stepping = 9,
2463 .features[FEAT_1_EDX] =
2464 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2465 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2466 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2467 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2468 CPUID_DE | CPUID_FP87,
2469 .features[FEAT_1_ECX] =
2470 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2471 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2472 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2473 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2474 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2475 .features[FEAT_7_0_EBX] =
2476 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2477 CPUID_7_0_EBX_ERMS,
2478 .features[FEAT_8000_0001_EDX] =
2479 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2480 CPUID_EXT2_SYSCALL,
2481 .features[FEAT_8000_0001_ECX] =
2482 CPUID_EXT3_LAHF_LM,
2483 .features[FEAT_XSAVE] =
2484 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2485 .features[FEAT_6_EAX] =
2486 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2487 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2488 MSR_VMX_BASIC_TRUE_CTLS,
2489 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2490 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2491 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2492 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2493 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2494 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2495 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2496 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2497 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2498 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2499 .features[FEAT_VMX_EXIT_CTLS] =
2500 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2501 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2502 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2503 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2504 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2505 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2506 MSR_VMX_MISC_STORE_LMA,
2507 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2508 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2509 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2510 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2511 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2512 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2513 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2514 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2515 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2516 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2517 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2518 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2519 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2520 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2521 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2522 .features[FEAT_VMX_SECONDARY_CTLS] =
2523 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2524 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2525 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2526 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2527 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2528 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2529 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2530 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2531 .xlevel = 0x80000008,
2f9ac42a 2532 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2533 .versions = (X86CPUVersionDefinition[]) {
2534 { .version = 1 },
2535 {
2536 .version = 2,
53db89d9 2537 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2538 .props = (PropValue[]) {
2539 { "spec-ctrl", "on" },
2540 { "model-id",
2541 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2542 { /* end of list */ }
2543 }
2544 },
2545 { /* end of list */ }
2546 }
2f9ac42a 2547 },
ac96c413 2548 {
37507094
EH		 2549 .name = "Haswell",
2550 .level = 0xd,
99b88a17 2551 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2552 .family = 6,
2553 .model = 60,
ec56a4a7 2554 .stepping = 4,
0514ef2f 2555 .features[FEAT_1_EDX] =
b3a4f0b1 2556 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2557 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2558 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2559 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2560 CPUID_DE | CPUID_FP87,
0514ef2f 2561 .features[FEAT_1_ECX] =
27861ecc 2562 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2563 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2564 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2565 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2566 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2567 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2568 .features[FEAT_8000_0001_EDX] =
27861ecc 2569 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2570 CPUID_EXT2_SYSCALL,
0514ef2f 2571 .features[FEAT_8000_0001_ECX] =
becb6667 2572 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2573 .features[FEAT_7_0_EBX] =
27861ecc 2574 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2575 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2576 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2577 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2578 .features[FEAT_XSAVE] =
2579 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2580 .features[FEAT_6_EAX] =
2581 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2582 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2583 MSR_VMX_BASIC_TRUE_CTLS,
2584 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2585 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2586 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2587 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2588 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2589 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2590 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2591 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2592 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2593 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2594 .features[FEAT_VMX_EXIT_CTLS] =
2595 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2596 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2597 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2598 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2599 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2600 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2601 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2602 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2603 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2604 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2605 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2606 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2607 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2608 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2609 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2610 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2611 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2612 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2613 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2614 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2615 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2616 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2617 .features[FEAT_VMX_SECONDARY_CTLS] =
2618 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2619 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2620 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2621 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2622 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2623 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2624 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2625 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2626 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2627 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2628 .xlevel = 0x80000008,
37507094 2629 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2630 .versions = (X86CPUVersionDefinition[]) {
2631 { .version = 1 },
2632 {
2633 .version = 2,
53db89d9 2634 .alias = "Haswell-noTSX",
d86a7088
EH		 2635 .props = (PropValue[]) {
2636 { "hle", "off" },
2637 { "rtm", "off" },
2638 { "stepping", "1" },
2639 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2640 { /* end of list */ }
2641 },
2642 },
2643 {
2644 .version = 3,
53db89d9 2645 .alias = "Haswell-IBRS",
d86a7088
EH		 2646 .props = (PropValue[]) {
2647 /* Restore TSX features removed by -v2 above */
2648 { "hle", "on" },
2649 { "rtm", "on" },
2650 /*
2651 * Haswell and Haswell-IBRS had stepping=4 in
2652 * QEMU 4.0 and older
2653 */
2654 { "stepping", "4" },
2655 { "spec-ctrl", "on" },
2656 { "model-id",
2657 "Intel Core Processor (Haswell, IBRS)" },
2658 { /* end of list */ }
2659 }
2660 },
2661 {
2662 .version = 4,
53db89d9 2663 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2664 .props = (PropValue[]) {
2665 { "hle", "off" },
2666 { "rtm", "off" },
2667 /* spec-ctrl was already enabled by -v3 above */
2668 { "stepping", "1" },
2669 { "model-id",
2670 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2671 { /* end of list */ }
2672 }
2673 },
2674 { /* end of list */ }
2675 }
37507094 2676 },
ece01354
EH		 2677 {
2678 .name = "Broadwell",
2679 .level = 0xd,
2680 .vendor = CPUID_VENDOR_INTEL,
2681 .family = 6,
2682 .model = 61,
2683 .stepping = 2,
2684 .features[FEAT_1_EDX] =
b3a4f0b1 2685 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2686 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2687 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2688 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2689 CPUID_DE | CPUID_FP87,
2690 .features[FEAT_1_ECX] =
2691 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2692 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2693 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2694 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2695 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2696 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2697 .features[FEAT_8000_0001_EDX] =
2698 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2699 CPUID_EXT2_SYSCALL,
2700 .features[FEAT_8000_0001_ECX] =
becb6667 2701 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2702 .features[FEAT_7_0_EBX] =
2703 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2704 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2705 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2706 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2707 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2708 .features[FEAT_XSAVE] =
2709 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2710 .features[FEAT_6_EAX] =
2711 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2712 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2713 MSR_VMX_BASIC_TRUE_CTLS,
2714 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2715 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2716 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2717 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2718 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2719 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2720 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2721 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2722 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2723 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2724 .features[FEAT_VMX_EXIT_CTLS] =
2725 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2726 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2727 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2728 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2729 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2730 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2731 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2732 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2733 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2734 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2735 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2736 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2737 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2738 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2739 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2740 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2741 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2742 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2743 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2744 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2745 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2746 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2747 .features[FEAT_VMX_SECONDARY_CTLS] =
2748 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2749 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2750 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2751 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2752 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2753 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2754 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2755 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2756 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2757 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2758 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2759 .xlevel = 0x80000008,
ece01354 2760 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2761 .versions = (X86CPUVersionDefinition[]) {
2762 { .version = 1 },
2763 {
2764 .version = 2,
53db89d9 2765 .alias = "Broadwell-noTSX",
d86a7088
EH		 2766 .props = (PropValue[]) {
2767 { "hle", "off" },
2768 { "rtm", "off" },
2769 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2770 { /* end of list */ }
2771 },
2772 },
2773 {
2774 .version = 3,
53db89d9 2775 .alias = "Broadwell-IBRS",
d86a7088
EH		 2776 .props = (PropValue[]) {
2777 /* Restore TSX features removed by -v2 above */
2778 { "hle", "on" },
2779 { "rtm", "on" },
2780 { "spec-ctrl", "on" },
2781 { "model-id",
2782 "Intel Core Processor (Broadwell, IBRS)" },
2783 { /* end of list */ }
2784 }
2785 },
2786 {
2787 .version = 4,
53db89d9 2788 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2789 .props = (PropValue[]) {
2790 { "hle", "off" },
2791 { "rtm", "off" },
2792 /* spec-ctrl was already enabled by -v3 above */
2793 { "model-id",
2794 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2795 { /* end of list */ }
2796 }
2797 },
2798 { /* end of list */ }
2799 }
ece01354 2800 },
f6f949e9
EH		 2801 {
2802 .name = "Skylake-Client",
2803 .level = 0xd,
2804 .vendor = CPUID_VENDOR_INTEL,
2805 .family = 6,
2806 .model = 94,
2807 .stepping = 3,
2808 .features[FEAT_1_EDX] =
2809 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2810 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2811 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2812 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2813 CPUID_DE | CPUID_FP87,
2814 .features[FEAT_1_ECX] =
2815 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2816 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2817 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2818 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2819 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2820 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2821 .features[FEAT_8000_0001_EDX] =
2822 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2823 CPUID_EXT2_SYSCALL,
2824 .features[FEAT_8000_0001_ECX] =
2825 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2826 .features[FEAT_7_0_EBX] =
2827 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2828 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2829 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2830 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2831 CPUID_7_0_EBX_SMAP,
7bde6b18 2832 /* XSAVES is added in version 4 */
f6f949e9
EH		 2833 .features[FEAT_XSAVE] =
2834 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2835 CPUID_XSAVE_XGETBV1,
2836 .features[FEAT_6_EAX] =
2837 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2838 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2839 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2840 MSR_VMX_BASIC_TRUE_CTLS,
2841 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2842 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2843 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2844 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2845 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2846 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2847 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2848 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2849 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2850 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2851 .features[FEAT_VMX_EXIT_CTLS] =
2852 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2853 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2854 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2855 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2856 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2857 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2858 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2859 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2860 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2861 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2862 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2863 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2864 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2865 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2866 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2867 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2868 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2869 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2870 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2871 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2872 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2873 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2874 .features[FEAT_VMX_SECONDARY_CTLS] =
2875 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2876 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2877 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2878 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2879 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2880 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2881 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2882 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2883 .xlevel = 0x80000008,
2884 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2885 .versions = (X86CPUVersionDefinition[]) {
2886 { .version = 1 },
2887 {
2888 .version = 2,
53db89d9 2889 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2890 .props = (PropValue[]) {
2891 { "spec-ctrl", "on" },
2892 { "model-id",
2893 "Intel Core Processor (Skylake, IBRS)" },
2894 { /* end of list */ }
2895 }
2896 },
9ab2237f
EH		 2897 {
2898 .version = 3,
02fa60d1 2899 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2900 .props = (PropValue[]) {
2901 { "hle", "off" },
2902 { "rtm", "off" },
673b0add
KC		 2903 { "model-id",
2904 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2905 { /* end of list */ }
2906 }
2907 },
7bde6b18
VK		 2908 {
2909 .version = 4,
2910 .note = "IBRS, XSAVES, no TSX",
2911 .props = (PropValue[]) {
2912 { "xsaves", "on" },
2913 { "vmx-xsaves", "on" },
2914 { /* end of list */ }
2915 }
2916 },
d86a7088
EH		 2917 { /* end of list */ }
2918 }
f6f949e9 2919 },
53f9a6f4
BF		 2920 {
2921 .name = "Skylake-Server",
2922 .level = 0xd,
2923 .vendor = CPUID_VENDOR_INTEL,
2924 .family = 6,
2925 .model = 85,
2926 .stepping = 4,
2927 .features[FEAT_1_EDX] =
2928 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2929 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2930 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2931 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2932 CPUID_DE | CPUID_FP87,
2933 .features[FEAT_1_ECX] =
2934 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2935 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2936 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2937 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2938 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2939 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2940 .features[FEAT_8000_0001_EDX] =
2941 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2942 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2943 .features[FEAT_8000_0001_ECX] =
2944 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2945 .features[FEAT_7_0_EBX] =
2946 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2947 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2948 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2949 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2950 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2951 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2952 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2953 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2954 .features[FEAT_7_0_ECX] =
2955 CPUID_7_0_ECX_PKU,
7bde6b18 2956 /* XSAVES is added in version 5 */
53f9a6f4
BF		 2957 .features[FEAT_XSAVE] =
2958 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2959 CPUID_XSAVE_XGETBV1,
2960 .features[FEAT_6_EAX] =
2961 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2962 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2963 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2964 MSR_VMX_BASIC_TRUE_CTLS,
2965 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2966 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2967 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2968 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2969 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2970 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2971 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2972 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2973 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2974 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2975 .features[FEAT_VMX_EXIT_CTLS] =
2976 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2977 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2978 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2979 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2980 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2981 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2982 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2983 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2984 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2985 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2986 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2987 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2988 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2989 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2990 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2991 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2992 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2993 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2994 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2995 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2996 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2997 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2998 .features[FEAT_VMX_SECONDARY_CTLS] =
2999 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3000 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3001 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3002 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3003 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3004 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3005 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3006 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3007 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3008 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 3009 .xlevel = 0x80000008,
3010 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 3011 .versions = (X86CPUVersionDefinition[]) {
3012 { .version = 1 },
3013 {
3014 .version = 2,
53db89d9 3015 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 3016 .props = (PropValue[]) {
3017 /* clflushopt was not added to Skylake-Server-IBRS */
3018 /* TODO: add -v3 including clflushopt */
3019 { "clflushopt", "off" },
3020 { "spec-ctrl", "on" },
3021 { "model-id",
3022 "Intel Xeon Processor (Skylake, IBRS)" },
3023 { /* end of list */ }
3024 }
3025 },
9ab2237f
EH		 3026 {
3027 .version = 3,
02fa60d1 3028 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3029 .props = (PropValue[]) {
3030 { "hle", "off" },
3031 { "rtm", "off" },
673b0add
KC		 3032 { "model-id",
3033 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3034 { /* end of list */ }
3035 }
3036 },
644e3c5d
CQ		 3037 {
3038 .version = 4,
3039 .props = (PropValue[]) {
3040 { "vmx-eptp-switching", "on" },
3041 { /* end of list */ }
3042 }
3043 },
7bde6b18
VK		 3044 {
3045 .version = 5,
3046 .note = "IBRS, XSAVES, EPT switching, no TSX",
3047 .props = (PropValue[]) {
3048 { "xsaves", "on" },
3049 { "vmx-xsaves", "on" },
3050 { /* end of list */ }
3051 }
3052 },
d86a7088
EH		 3053 { /* end of list */ }
3054 }
53f9a6f4 3055 },
c7a88b52
TX		 3056 {
3057 .name = "Cascadelake-Server",
3058 .level = 0xd,
3059 .vendor = CPUID_VENDOR_INTEL,
3060 .family = 6,
3061 .model = 85,
b0a19803 3062 .stepping = 6,
c7a88b52
TX		 3063 .features[FEAT_1_EDX] =
3064 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3065 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3066 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3067 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3068 CPUID_DE | CPUID_FP87,
3069 .features[FEAT_1_ECX] =
3070 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3071 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3072 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3073 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3074 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3075 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3076 .features[FEAT_8000_0001_EDX] =
3077 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3078 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3079 .features[FEAT_8000_0001_ECX] =
3080 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3081 .features[FEAT_7_0_EBX] =
3082 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3083 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3084 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3085 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3086 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3087 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3088 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3089 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3090 .features[FEAT_7_0_ECX] =
bb4928c7 3091 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3092 CPUID_7_0_ECX_AVX512VNNI,
3093 .features[FEAT_7_0_EDX] =
3094 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3095 /* XSAVES is added in version 5 */
c7a88b52
TX		 3096 .features[FEAT_XSAVE] =
3097 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3098 CPUID_XSAVE_XGETBV1,
3099 .features[FEAT_6_EAX] =
3100 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3101 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3102 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3103 MSR_VMX_BASIC_TRUE_CTLS,
3104 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3105 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3106 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3107 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3108 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3109 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3110 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3111 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3112 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3113 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3114 .features[FEAT_VMX_EXIT_CTLS] =
3115 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3116 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3117 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3118 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3119 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3120 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3121 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3122 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3123 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3124 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3125 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3126 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3127 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3128 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3129 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3130 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3131 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3132 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3133 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3134 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3135 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3136 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3137 .features[FEAT_VMX_SECONDARY_CTLS] =
3138 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3139 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3140 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3141 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3142 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3143 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3144 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3145 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3146 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3147 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3148 .xlevel = 0x80000008,
3149 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3150 .versions = (X86CPUVersionDefinition[]) {
3151 { .version = 1 },
3152 { .version = 2,
47f0d11d 3153 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3154 .props = (PropValue[]) {
3155 { "arch-capabilities", "on" },
3156 { "rdctl-no", "on" },
3157 { "ibrs-all", "on" },
3158 { "skip-l1dfl-vmentry", "on" },
3159 { "mds-no", "on" },
3160 { /* end of list */ }
3161 },
3162 },
9ab2237f 3163 { .version = 3,
02fa60d1 3164 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3165 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3166 .props = (PropValue[]) {
3167 { "hle", "off" },
3168 { "rtm", "off" },
3169 { /* end of list */ }
3170 },
3171 },
644e3c5d
CQ		 3172 { .version = 4,
3173 .note = "ARCH_CAPABILITIES, no TSX",
3174 .props = (PropValue[]) {
3175 { "vmx-eptp-switching", "on" },
3176 { /* end of list */ }
3177 },
3178 },
7bde6b18
VK		 3179 { .version = 5,
3180 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3181 .props = (PropValue[]) {
3182 { "xsaves", "on" },
3183 { "vmx-xsaves", "on" },
3184 { /* end of list */ }
3185 },
3186 },
fd63c6d1
EH		 3187 { /* end of list */ }
3188 }
c7a88b52 3189 },
22a866b6
CZ		 3190 {
3191 .name = "Cooperlake",
3192 .level = 0xd,
3193 .vendor = CPUID_VENDOR_INTEL,
3194 .family = 6,
3195 .model = 85,
3196 .stepping = 10,
3197 .features[FEAT_1_EDX] =
3198 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3199 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3200 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3201 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3202 CPUID_DE | CPUID_FP87,
3203 .features[FEAT_1_ECX] =
3204 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3205 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3206 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3207 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3208 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3209 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3210 .features[FEAT_8000_0001_EDX] =
3211 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3212 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3213 .features[FEAT_8000_0001_ECX] =
3214 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3215 .features[FEAT_7_0_EBX] =
3216 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3217 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3218 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3219 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3220 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3221 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3222 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3223 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3224 .features[FEAT_7_0_ECX] =
3225 CPUID_7_0_ECX_PKU |
3226 CPUID_7_0_ECX_AVX512VNNI,
3227 .features[FEAT_7_0_EDX] =
3228 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3229 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3230 .features[FEAT_ARCH_CAPABILITIES] =
3231 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3232 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3233 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3234 .features[FEAT_7_1_EAX] =
f429dbf8 3235 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3236 /* XSAVES is added in version 2 */
22a866b6
CZ		 3237 .features[FEAT_XSAVE] =
3238 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3239 CPUID_XSAVE_XGETBV1,
3240 .features[FEAT_6_EAX] =
3241 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3242 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3243 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3244 MSR_VMX_BASIC_TRUE_CTLS,
3245 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3246 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3247 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3248 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3249 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3250 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3251 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3252 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3253 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3254 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3255 .features[FEAT_VMX_EXIT_CTLS] =
3256 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3257 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3258 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3259 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3260 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3261 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3262 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3263 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3264 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3265 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3266 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3267 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3268 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3269 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3270 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3271 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3272 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3273 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3274 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3275 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3276 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3277 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3278 .features[FEAT_VMX_SECONDARY_CTLS] =
3279 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3280 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3281 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3282 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3283 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3284 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3285 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3286 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3287 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3288 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3289 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3290 .xlevel = 0x80000008,
3291 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3292 .versions = (X86CPUVersionDefinition[]) {
3293 { .version = 1 },
3294 { .version = 2,
3295 .note = "XSAVES",
3296 .props = (PropValue[]) {
3297 { "xsaves", "on" },
3298 { "vmx-xsaves", "on" },
3299 { /* end of list */ }
3300 },
3301 },
3302 { /* end of list */ }
3303 }
22a866b6 3304 },
8a11c62d
RH		 3305 {
3306 .name = "Icelake-Server",
3307 .level = 0xd,
3308 .vendor = CPUID_VENDOR_INTEL,
3309 .family = 6,
3310 .model = 134,
3311 .stepping = 0,
3312 .features[FEAT_1_EDX] =
3313 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3314 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3315 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3316 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3317 CPUID_DE | CPUID_FP87,
3318 .features[FEAT_1_ECX] =
3319 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3320 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3321 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3322 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3323 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3324 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3325 .features[FEAT_8000_0001_EDX] =
3326 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3327 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3328 .features[FEAT_8000_0001_ECX] =
3329 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3330 .features[FEAT_8000_0008_EBX] =
3331 CPUID_8000_0008_EBX_WBNOINVD,
3332 .features[FEAT_7_0_EBX] =
3333 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3334 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3335 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3336 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3337 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3338 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3339 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3340 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3341 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3342 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3343 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3344 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3345 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3346 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3347 .features[FEAT_7_0_EDX] =
76e5a4d5 3348 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3349 /* XSAVES is added in version 5 */
8a11c62d
RH		 3350 .features[FEAT_XSAVE] =
3351 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3352 CPUID_XSAVE_XGETBV1,
3353 .features[FEAT_6_EAX] =
3354 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3355 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3356 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3357 MSR_VMX_BASIC_TRUE_CTLS,
3358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3359 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3360 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3361 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3362 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3363 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3364 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3365 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3366 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3367 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3368 .features[FEAT_VMX_EXIT_CTLS] =
3369 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3370 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3371 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3372 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3373 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3374 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3375 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3376 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3377 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3378 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3379 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3380 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3381 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3382 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3383 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3384 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3385 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3386 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3387 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3388 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3389 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3390 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3391 .features[FEAT_VMX_SECONDARY_CTLS] =
3392 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3393 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3394 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3395 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3396 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3397 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3398 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3399 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3400 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3401 .xlevel = 0x80000008,
3402 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3403 .versions = (X86CPUVersionDefinition[]) {
3404 { .version = 1 },
3405 {
3406 .version = 2,
47f0d11d 3407 .note = "no TSX",
02fa60d1 3408 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3409 .props = (PropValue[]) {
3410 { "hle", "off" },
3411 { "rtm", "off" },
3412 { /* end of list */ }
3413 },
3414 },
d965dc35
XL		 3415 {
3416 .version = 3,
3417 .props = (PropValue[]) {
3418 { "arch-capabilities", "on" },
3419 { "rdctl-no", "on" },
3420 { "ibrs-all", "on" },
3421 { "skip-l1dfl-vmentry", "on" },
3422 { "mds-no", "on" },
3423 { "pschange-mc-no", "on" },
3424 { "taa-no", "on" },
3425 { /* end of list */ }
3426 },
3427 },
e0013791
CQ		 3428 {
3429 .version = 4,
3430 .props = (PropValue[]) {
3431 { "sha-ni", "on" },
3432 { "avx512ifma", "on" },
3433 { "rdpid", "on" },
3434 { "fsrm", "on" },
3435 { "vmx-rdseed-exit", "on" },
3436 { "vmx-pml", "on" },
3437 { "vmx-eptp-switching", "on" },
3438 { "model", "106" },
3439 { /* end of list */ }
3440 },
3441 },
7bde6b18
VK		 3442 {
3443 .version = 5,
3444 .note = "XSAVES",
3445 .props = (PropValue[]) {
3446 { "xsaves", "on" },
3447 { "vmx-xsaves", "on" },
3448 { /* end of list */ }
3449 },
3450 },
12cab535
VK		 3451 {
3452 .version = 6,
3453 .note = "5-level EPT",
3454 .props = (PropValue[]) {
3455 { "vmx-page-walk-5", "on" },
3456 { /* end of list */ }
3457 },
3458 },
9ab2237f
EH		 3459 { /* end of list */ }
3460 }
8a11c62d 3461 },
8b44d860
TX		 3462 {
3463 .name = "Denverton",
3464 .level = 21,
3465 .vendor = CPUID_VENDOR_INTEL,
3466 .family = 6,
3467 .model = 95,
3468 .stepping = 1,
3469 .features[FEAT_1_EDX] =
3470 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3471 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3472 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3473 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3474 CPUID_SSE | CPUID_SSE2,
3475 .features[FEAT_1_ECX] =
3476 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3477 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3478 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3479 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3480 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3481 .features[FEAT_8000_0001_EDX] =
3482 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3483 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3484 .features[FEAT_8000_0001_ECX] =
3485 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3486 .features[FEAT_7_0_EBX] =
3487 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3488 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3489 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3490 .features[FEAT_7_0_EDX] =
3491 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3492 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3493 /* XSAVES is added in version 3 */
8b44d860
TX		 3494 .features[FEAT_XSAVE] =
3495 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3496 .features[FEAT_6_EAX] =
3497 CPUID_6_EAX_ARAT,
3498 .features[FEAT_ARCH_CAPABILITIES] =
3499 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3500 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3501 MSR_VMX_BASIC_TRUE_CTLS,
3502 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3503 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3504 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3505 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3506 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3507 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3508 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3509 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3510 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3511 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3512 .features[FEAT_VMX_EXIT_CTLS] =
3513 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3514 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3515 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3516 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3517 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3518 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3519 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3520 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3521 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3522 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3523 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3524 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3525 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3526 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3527 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3528 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3529 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3530 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3531 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3532 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3533 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3534 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3535 .features[FEAT_VMX_SECONDARY_CTLS] =
3536 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3537 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3538 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3539 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3540 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3541 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3542 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3543 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3544 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3545 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3546 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3547 .xlevel = 0x80000008,
3548 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3549 .versions = (X86CPUVersionDefinition[]) {
3550 { .version = 1 },
3551 {
3552 .version = 2,
47f0d11d 3553 .note = "no MPX, no MONITOR",
ab0c942c
TX		 3554 .props = (PropValue[]) {
3555 { "monitor", "off" },
3556 { "mpx", "off" },
3557 { /* end of list */ },
3558 },
3559 },
7bde6b18
VK		 3560 {
3561 .version = 3,
3562 .note = "XSAVES, no MPX, no MONITOR",
3563 .props = (PropValue[]) {
3564 { "xsaves", "on" },
3565 { "vmx-xsaves", "on" },
3566 { /* end of list */ },
3567 },
3568 },
ab0c942c
TX		 3569 { /* end of list */ },
3570 },
8b44d860 3571 },
0b18874b 3572 {
ff656fcd 3573 .name = "Snowridge",
0b18874b
PL		 3574 .level = 27,
3575 .vendor = CPUID_VENDOR_INTEL,
3576 .family = 6,
3577 .model = 134,
3578 .stepping = 1,
3579 .features[FEAT_1_EDX] =
3580 /* missing: CPUID_PN CPUID_IA64 */
3581 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3582 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3583 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3584 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3585 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3586 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3587 CPUID_MMX |
3588 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3589 .features[FEAT_1_ECX] =
3590 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3591 CPUID_EXT_SSSE3 |
3592 CPUID_EXT_CX16 |
3593 CPUID_EXT_SSE41 |
3594 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3595 CPUID_EXT_POPCNT |
3596 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3597 CPUID_EXT_RDRAND,
3598 .features[FEAT_8000_0001_EDX] =
3599 CPUID_EXT2_SYSCALL |
3600 CPUID_EXT2_NX |
3601 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3602 CPUID_EXT2_LM,
3603 .features[FEAT_8000_0001_ECX] =
3604 CPUID_EXT3_LAHF_LM |
3605 CPUID_EXT3_3DNOWPREFETCH,
3606 .features[FEAT_7_0_EBX] =
3607 CPUID_7_0_EBX_FSGSBASE |
3608 CPUID_7_0_EBX_SMEP |
3609 CPUID_7_0_EBX_ERMS |
3610 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3611 CPUID_7_0_EBX_RDSEED |
3612 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3613 CPUID_7_0_EBX_CLWB |
3614 CPUID_7_0_EBX_SHA_NI,
3615 .features[FEAT_7_0_ECX] =
3616 CPUID_7_0_ECX_UMIP |
3617 /* missing bit 5 */
3618 CPUID_7_0_ECX_GFNI |
3619 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3620 CPUID_7_0_ECX_MOVDIR64B,
3621 .features[FEAT_7_0_EDX] =
3622 CPUID_7_0_EDX_SPEC_CTRL |
3623 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3624 CPUID_7_0_EDX_CORE_CAPABILITY,
3625 .features[FEAT_CORE_CAPABILITY] =
3626 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7bde6b18 3627 /* XSAVES is is added in version 3 */
0b18874b
PL		 3628 .features[FEAT_XSAVE] =
3629 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3630 CPUID_XSAVE_XGETBV1,
3631 .features[FEAT_6_EAX] =
3632 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3633 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3634 MSR_VMX_BASIC_TRUE_CTLS,
3635 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3636 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3637 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3638 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3639 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3640 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3641 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3642 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3643 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3644 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3645 .features[FEAT_VMX_EXIT_CTLS] =
3646 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3647 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3648 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3649 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3650 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3651 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3652 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3653 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3654 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3655 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3656 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3657 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3658 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3659 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3660 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3661 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3662 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3663 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3664 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3665 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3666 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3667 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3668 .features[FEAT_VMX_SECONDARY_CTLS] =
3669 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3670 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3671 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3672 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3673 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3674 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3675 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3676 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3677 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3678 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3679 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3680 .xlevel = 0x80000008,
3681 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3682 .versions = (X86CPUVersionDefinition[]) {
3683 { .version = 1 },
3684 {
3685 .version = 2,
3686 .props = (PropValue[]) {
3687 { "mpx", "off" },
3688 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3689 { /* end of list */ },
3690 },
3691 },
7bde6b18
VK		 3692 {
3693 .version = 3,
3694 .note = "XSAVES, no MPX",
3695 .props = (PropValue[]) {
3696 { "xsaves", "on" },
3697 { "vmx-xsaves", "on" },
3698 { /* end of list */ },
3699 },
3700 },
56bb24e5
CQ		 3701 {
3702 .version = 4,
07db29f2 3703 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 3704 .props = (PropValue[]) {
3705 { "split-lock-detect", "off" },
07db29f2 3706 { "core-capability", "off" },
56bb24e5
CQ		 3707 { /* end of list */ },
3708 },
3709 },
69edb0f3
XL		 3710 { /* end of list */ },
3711 },
0b18874b 3712 },
a1849515
BF		 3713 {
3714 .name = "KnightsMill",
3715 .level = 0xd,
3716 .vendor = CPUID_VENDOR_INTEL,
3717 .family = 6,
3718 .model = 133,
3719 .stepping = 0,
3720 .features[FEAT_1_EDX] =
3721 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3722 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3723 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3724 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3725 CPUID_PSE | CPUID_DE | CPUID_FP87,
3726 .features[FEAT_1_ECX] =
3727 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3728 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3729 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3730 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3731 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3732 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3733 .features[FEAT_8000_0001_EDX] =
3734 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3735 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3736 .features[FEAT_8000_0001_ECX] =
3737 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3738 .features[FEAT_7_0_EBX] =
3739 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3740 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3741 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3742 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3743 CPUID_7_0_EBX_AVX512ER,
3744 .features[FEAT_7_0_ECX] =
3745 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3746 .features[FEAT_7_0_EDX] =
3747 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3748 .features[FEAT_XSAVE] =
3749 CPUID_XSAVE_XSAVEOPT,
3750 .features[FEAT_6_EAX] =
3751 CPUID_6_EAX_ARAT,
3752 .xlevel = 0x80000008,
3753 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3754 },
3eca4642
EH		 3755 {
3756 .name = "Opteron_G1",
3757 .level = 5,
99b88a17 3758 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3759 .family = 15,
3760 .model = 6,
3761 .stepping = 1,
0514ef2f 3762 .features[FEAT_1_EDX] =
b3a4f0b1 3763 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3764 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3765 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3766 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3767 CPUID_DE | CPUID_FP87,
0514ef2f 3768 .features[FEAT_1_ECX] =
27861ecc 3769 CPUID_EXT_SSE3,
0514ef2f 3770 .features[FEAT_8000_0001_EDX] =
2a923a29 3771 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3772 .xlevel = 0x80000008,
3773 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3774 },
3775 {
3776 .name = "Opteron_G2",
3777 .level = 5,
99b88a17 3778 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3779 .family = 15,
3780 .model = 6,
3781 .stepping = 1,
0514ef2f 3782 .features[FEAT_1_EDX] =
b3a4f0b1 3783 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3784 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3785 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3786 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3787 CPUID_DE | CPUID_FP87,
0514ef2f 3788 .features[FEAT_1_ECX] =
27861ecc 3789 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3790 .features[FEAT_8000_0001_EDX] =
2a923a29 3791 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3792 .features[FEAT_8000_0001_ECX] =
27861ecc 3793 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3794 .xlevel = 0x80000008,
3795 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3796 },
3797 {
3798 .name = "Opteron_G3",
3799 .level = 5,
99b88a17 3800 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3801 .family = 16,
3802 .model = 2,
3803 .stepping = 3,
0514ef2f 3804 .features[FEAT_1_EDX] =
b3a4f0b1 3805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3809 CPUID_DE | CPUID_FP87,
0514ef2f 3810 .features[FEAT_1_ECX] =
27861ecc 3811 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3812 CPUID_EXT_SSE3,
0514ef2f 3813 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3814 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3815 CPUID_EXT2_RDTSCP,
0514ef2f 3816 .features[FEAT_8000_0001_ECX] =
27861ecc 3817 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3818 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3819 .xlevel = 0x80000008,
3820 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3821 },
3822 {
3823 .name = "Opteron_G4",
3824 .level = 0xd,
99b88a17 3825 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3826 .family = 21,
3827 .model = 1,
3828 .stepping = 2,
0514ef2f 3829 .features[FEAT_1_EDX] =
b3a4f0b1 3830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3834 CPUID_DE | CPUID_FP87,
0514ef2f 3835 .features[FEAT_1_ECX] =
27861ecc 3836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3837 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3838 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3839 CPUID_EXT_SSE3,
0514ef2f 3840 .features[FEAT_8000_0001_EDX] =
2a923a29 3841 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3842 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3843 .features[FEAT_8000_0001_ECX] =
27861ecc 3844 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3845 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3846 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3847 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3848 .features[FEAT_SVM] =
3849 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3850 /* no xsaveopt! */
3eca4642
EH		 3851 .xlevel = 0x8000001A,
3852 .model_id = "AMD Opteron 62xx class CPU",
3853 },
021941b9
AP		 3854 {
3855 .name = "Opteron_G5",
3856 .level = 0xd,
99b88a17 3857 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3858 .family = 21,
3859 .model = 2,
3860 .stepping = 0,
0514ef2f 3861 .features[FEAT_1_EDX] =
b3a4f0b1 3862 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3863 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3864 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3865 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3866 CPUID_DE | CPUID_FP87,
0514ef2f 3867 .features[FEAT_1_ECX] =
27861ecc 3868 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3869 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3870 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3871 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3872 .features[FEAT_8000_0001_EDX] =
2a923a29 3873 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3874 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3875 .features[FEAT_8000_0001_ECX] =
27861ecc 3876 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3877 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3878 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3879 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3880 .features[FEAT_SVM] =
3881 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3882 /* no xsaveopt! */
021941b9
AP		 3883 .xlevel = 0x8000001A,
3884 .model_id = "AMD Opteron 63xx class CPU",
3885 },
2e2efc7d
BS		 3886 {
3887 .name = "EPYC",
3888 .level = 0xd,
3889 .vendor = CPUID_VENDOR_AMD,
3890 .family = 23,
3891 .model = 1,
3892 .stepping = 2,
3893 .features[FEAT_1_EDX] =
3894 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3895 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3896 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3897 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3898 CPUID_VME | CPUID_FP87,
3899 .features[FEAT_1_ECX] =
3900 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3901 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3902 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3903 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3904 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3905 .features[FEAT_8000_0001_EDX] =
3906 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3907 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3908 CPUID_EXT2_SYSCALL,
3909 .features[FEAT_8000_0001_ECX] =
3910 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3911 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3912 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3913 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3914 .features[FEAT_7_0_EBX] =
3915 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3916 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3917 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3918 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3919 .features[FEAT_XSAVE] =
3920 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3921 CPUID_XSAVE_XGETBV1,
3922 .features[FEAT_6_EAX] =
3923 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3924 .features[FEAT_SVM] =
3925 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3926 .xlevel = 0x8000001E,
2e2efc7d 3927 .model_id = "AMD EPYC Processor",
fe52acd2 3928 .cache_info = &epyc_cache_info,
d86a7088
EH		 3929 .versions = (X86CPUVersionDefinition[]) {
3930 { .version = 1 },
3931 {
3932 .version = 2,
53db89d9 3933 .alias = "EPYC-IBPB",
d86a7088
EH		 3934 .props = (PropValue[]) {
3935 { "ibpb", "on" },
3936 { "model-id",
3937 "AMD EPYC Processor (with IBPB)" },
3938 { /* end of list */ }
3939 }
3940 },
a16e8dbc
MB		 3941 {
3942 .version = 3,
3943 .props = (PropValue[]) {
3944 { "ibpb", "on" },
3945 { "perfctr-core", "on" },
3946 { "clzero", "on" },
3947 { "xsaveerptr", "on" },
3948 { "xsaves", "on" },
3949 { "model-id",
3950 "AMD EPYC Processor" },
3951 { /* end of list */ }
3952 }
3953 },
d86a7088
EH		 3954 { /* end of list */ }
3955 }
2e2efc7d 3956 },
8d031cec
PW		 3957 {
3958 .name = "Dhyana",
3959 .level = 0xd,
3960 .vendor = CPUID_VENDOR_HYGON,
3961 .family = 24,
3962 .model = 0,
3963 .stepping = 1,
3964 .features[FEAT_1_EDX] =
3965 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3966 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3967 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3968 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3969 CPUID_VME | CPUID_FP87,
3970 .features[FEAT_1_ECX] =
3971 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3972 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3973 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3974 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3975 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
3976 .features[FEAT_8000_0001_EDX] =
3977 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3978 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3979 CPUID_EXT2_SYSCALL,
3980 .features[FEAT_8000_0001_ECX] =
3981 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3982 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3983 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3984 CPUID_EXT3_TOPOEXT,
3985 .features[FEAT_8000_0008_EBX] =
3986 CPUID_8000_0008_EBX_IBPB,
3987 .features[FEAT_7_0_EBX] =
3988 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3989 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3990 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 3991 /* XSAVES is added in version 2 */
8d031cec
PW		 3992 .features[FEAT_XSAVE] =
3993 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3994 CPUID_XSAVE_XGETBV1,
3995 .features[FEAT_6_EAX] =
3996 CPUID_6_EAX_ARAT,
3997 .features[FEAT_SVM] =
3998 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3999 .xlevel = 0x8000001E,
4000 .model_id = "Hygon Dhyana Processor",
4001 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4002 .versions = (X86CPUVersionDefinition[]) {
4003 { .version = 1 },
4004 { .version = 2,
4005 .note = "XSAVES",
4006 .props = (PropValue[]) {
4007 { "xsaves", "on" },
4008 { /* end of list */ }
4009 },
4010 },
4011 { /* end of list */ }
4012 }
8d031cec 4013 },
143c30d4
MB		 4014 {
4015 .name = "EPYC-Rome",
4016 .level = 0xd,
4017 .vendor = CPUID_VENDOR_AMD,
4018 .family = 23,
4019 .model = 49,
4020 .stepping = 0,
4021 .features[FEAT_1_EDX] =
4022 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4023 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4024 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4025 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4026 CPUID_VME | CPUID_FP87,
4027 .features[FEAT_1_ECX] =
4028 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4029 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4030 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4031 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4032 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4033 .features[FEAT_8000_0001_EDX] =
4034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4035 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4036 CPUID_EXT2_SYSCALL,
4037 .features[FEAT_8000_0001_ECX] =
4038 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4039 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4040 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4041 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4042 .features[FEAT_8000_0008_EBX] =
4043 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4044 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4045 CPUID_8000_0008_EBX_STIBP,
4046 .features[FEAT_7_0_EBX] =
4047 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4048 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4049 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4050 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4051 .features[FEAT_7_0_ECX] =
4052 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4053 .features[FEAT_XSAVE] =
4054 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4055 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4056 .features[FEAT_6_EAX] =
4057 CPUID_6_EAX_ARAT,
4058 .features[FEAT_SVM] =
4059 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4060 .xlevel = 0x8000001E,
4061 .model_id = "AMD EPYC-Rome Processor",
4062 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4063 .versions = (X86CPUVersionDefinition[]) {
4064 { .version = 1 },
4065 {
4066 .version = 2,
4067 .props = (PropValue[]) {
4068 { "ibrs", "on" },
4069 { "amd-ssbd", "on" },
4070 { /* end of list */ }
4071 }
4072 },
4073 { /* end of list */ }
4074 }
143c30d4 4075 },
623972ce
BM		 4076 {
4077 .name = "EPYC-Milan",
4078 .level = 0xd,
4079 .vendor = CPUID_VENDOR_AMD,
4080 .family = 25,
4081 .model = 1,
4082 .stepping = 1,
4083 .features[FEAT_1_EDX] =
4084 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4085 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4086 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4087 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4088 CPUID_VME | CPUID_FP87,
4089 .features[FEAT_1_ECX] =
4090 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4091 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4092 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4093 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4094 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4095 CPUID_EXT_PCID,
4096 .features[FEAT_8000_0001_EDX] =
4097 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4098 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4099 CPUID_EXT2_SYSCALL,
4100 .features[FEAT_8000_0001_ECX] =
4101 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4102 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4103 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4104 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4105 .features[FEAT_8000_0008_EBX] =
4106 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4107 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4108 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4109 CPUID_8000_0008_EBX_AMD_SSBD,
4110 .features[FEAT_7_0_EBX] =
4111 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4112 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4113 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4114 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4115 CPUID_7_0_EBX_INVPCID,
4116 .features[FEAT_7_0_ECX] =
4117 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4118 .features[FEAT_7_0_EDX] =
4119 CPUID_7_0_EDX_FSRM,
4120 .features[FEAT_XSAVE] =
4121 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4122 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4123 .features[FEAT_6_EAX] =
4124 CPUID_6_EAX_ARAT,
4125 .features[FEAT_SVM] =
4126 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4127 .xlevel = 0x8000001E,
4128 .model_id = "AMD EPYC-Milan Processor",
4129 .cache_info = &epyc_milan_cache_info,
4130 },
c6dc6f63
AP		 4131};
4132
ad183928
EH		 4133/*
4134 * We resolve CPU model aliases using -v1 when using "-machine
4135 * none", but this is just for compatibility while libvirt isn't
4136 * adapted to resolve CPU model versions before creating VMs.
32048d72 4137 * See "Runnability guarantee of CPU models" at
a476b216 4138 * docs/about/deprecated.rst.
ad183928
EH		 4139 */
4140X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4141
4142void x86_cpu_set_default_version(X86CPUVersion version)
4143{
4144 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4145 assert(version != CPU_VERSION_AUTO);
4146 default_cpu_version = version;
4147}
4148
dcafd1ef
EH		 4149static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4150{
4151 int v = 0;
4152 const X86CPUVersionDefinition *vdef =
4153 x86_cpu_def_get_versions(model->cpudef);
4154 while (vdef->version) {
4155 v = vdef->version;
4156 vdef++;
4157 }
4158 return v;
4159}
4160
4161/* Return the actual version being used for a specific CPU model */
4162static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4163{
4164 X86CPUVersion v = model->version;
0788a56b
EH		 4165 if (v == CPU_VERSION_AUTO) {
4166 v = default_cpu_version;
4167 }
dcafd1ef
EH		 4168 if (v == CPU_VERSION_LATEST) {
4169 return x86_cpu_model_last_version(model);
4170 }
4171 return v;
4172}
4173
c62f2630 4174static Property max_x86_cpu_properties[] = {
120eee7d 4175 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4176 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4177 DEFINE_PROP_END_OF_LIST()
4178};
4179
c62f2630 4180static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4181{
84f1b92f 4182 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4183 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4184
f48c8837 4185 xcc->ordering = 9;
6e746f30 4186
ee465a3e 4187 xcc->model_description =
c62f2630 4188 "Enables all features supported by the accelerator in the current host";
d940ee9b 4189
4f67d30b 4190 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4191}
4192
c62f2630 4193static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4194{
4195 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4196
4d1b279b
EH		 4197 /* We can't fill the features array here because we don't know yet if
4198 * "migratable" is true or false.
4199 */
44bd8e53 4200 cpu->max_features = true;
5325cc34 4201 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4202
4203 /*
4204 * these defaults are used for TCG and all other accelerators
4205 * besides KVM and HVF, which overwrite these values
4206 */
4207 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4208 &error_abort);
40b3cc35
DB		 4209#ifdef TARGET_X86_64
4210 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort);
4211 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort);
4212 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort);
4213#else
f5cc5a5c
CF		 4214 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4215 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4216 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
40b3cc35 4217#endif
f5cc5a5c
CF		 4218 object_property_set_str(OBJECT(cpu), "model-id",
4219 "QEMU TCG CPU version " QEMU_HW_VERSION,
4220 &error_abort);
c6dc6f63
AP		 4221}
4222
c62f2630
EH		 4223static const TypeInfo max_x86_cpu_type_info = {
4224 .name = X86_CPU_TYPE_NAME("max"),
4225 .parent = TYPE_X86_CPU,
4226 .instance_init = max_x86_cpu_initfn,
4227 .class_init = max_x86_cpu_class_init,
4228};
4229
07585923
RH		 4230static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4231{
4232 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4233
4234 switch (f->type) {
4235 case CPUID_FEATURE_WORD:
4236 {
4237 const char *reg = get_register_name_32(f->cpuid.reg);
4238 assert(reg);
4239 return g_strdup_printf("CPUID.%02XH:%s",
4240 f->cpuid.eax, reg);
4241 }
4242 case MSR_FEATURE_WORD:
4243 return g_strdup_printf("MSR(%02XH)",
4244 f->msr.index);
4245 }
4246
4247 return NULL;
4248}
4249
245edd0c 4250static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4251{
245edd0c
PB		 4252 FeatureWord w;
4253
4254 for (w = 0; w < FEATURE_WORDS; w++) {
4255 if (cpu->filtered_features[w]) {
4256 return true;
4257 }
4258 }
4259
4260 return false;
4261}
4262
ede146c2 4263static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4264 const char *verbose_prefix)
4265{
4266 CPUX86State *env = &cpu->env;
8459e396 4267 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4268 int i;
4269
245edd0c
PB		 4270 if (!cpu->force_features) {
4271 env->features[w] &= ~mask;
4272 }
4273 cpu->filtered_features[w] |= mask;
4274
4275 if (!verbose_prefix) {
4276 return;
4277 }
4278
ede146c2
PB		 4279 for (i = 0; i < 64; ++i) {
4280 if ((1ULL << i) & mask) {
88703ce2 4281 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4282 warn_report("%s: %s%s%s [bit %d]",
4283 verbose_prefix,
07585923 4284 feat_word_str,
8297be80
AF		 4285 f->feat_names[i] ? "." : "",
4286 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4287 }
857aee33 4288 }
c6dc6f63
AP		 4289}
4290
d7bce999
EB		 4291static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4292 const char *name, void *opaque,
4293 Error **errp)
95b8519d
AF		 4294{
4295 X86CPU *cpu = X86_CPU(obj);
4296 CPUX86State *env = &cpu->env;
4297 int64_t value;
4298
4299 value = (env->cpuid_version >> 8) & 0xf;
4300 if (value == 0xf) {
4301 value += (env->cpuid_version >> 20) & 0xff;
4302 }
51e72bc1 4303 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4304}
4305
d7bce999
EB		 4306static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4307 const char *name, void *opaque,
4308 Error **errp)
ed5e1ec3 4309{
71ad61d3
AF		 4310 X86CPU *cpu = X86_CPU(obj);
4311 CPUX86State *env = &cpu->env;
4312 const int64_t min = 0;
4313 const int64_t max = 0xff + 0xf;
4314 int64_t value;
4315
668f62ec 4316 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 4317 return;
4318 }
4319 if (value < min || value > max) {
c6bd8c70
MA		 4320 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4321 name ? name : "null", value, min, max);
71ad61d3
AF		 4322 return;
4323 }
4324
ed5e1ec3 4325 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4326 if (value > 0x0f) {
4327 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4328 } else {
71ad61d3 4329 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4330 }
4331}
4332
d7bce999
EB		 4333static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4334 const char *name, void *opaque,
4335 Error **errp)
67e30c83
AF		 4336{
4337 X86CPU *cpu = X86_CPU(obj);
4338 CPUX86State *env = &cpu->env;
4339 int64_t value;
4340
4341 value = (env->cpuid_version >> 4) & 0xf;
4342 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4343 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4344}
4345
d7bce999
EB		 4346static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4347 const char *name, void *opaque,
4348 Error **errp)
b0704cbd 4349{
c5291a4f
AF		 4350 X86CPU *cpu = X86_CPU(obj);
4351 CPUX86State *env = &cpu->env;
4352 const int64_t min = 0;
4353 const int64_t max = 0xff;
4354 int64_t value;
4355
668f62ec 4356 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 4357 return;
4358 }
4359 if (value < min || value > max) {
c6bd8c70
MA		 4360 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4361 name ? name : "null", value, min, max);
c5291a4f
AF		 4362 return;
4363 }
4364
b0704cbd 4365 env->cpuid_version &= ~0xf00f0;
c5291a4f 4366 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4367}
4368
35112e41 4369static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4370 const char *name, void *opaque,
35112e41
AF		 4371 Error **errp)
4372{
4373 X86CPU *cpu = X86_CPU(obj);
4374 CPUX86State *env = &cpu->env;
4375 int64_t value;
4376
4377 value = env->cpuid_version & 0xf;
51e72bc1 4378 visit_type_int(v, name, &value, errp);
35112e41
AF		 4379}
4380
036e2222 4381static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4382 const char *name, void *opaque,
036e2222 4383 Error **errp)
38c3dc46 4384{
036e2222
AF		 4385 X86CPU *cpu = X86_CPU(obj);
4386 CPUX86State *env = &cpu->env;
4387 const int64_t min = 0;
4388 const int64_t max = 0xf;
4389 int64_t value;
4390
668f62ec 4391 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 4392 return;
4393 }
4394 if (value < min || value > max) {
c6bd8c70
MA		 4395 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4396 name ? name : "null", value, min, max);
036e2222
AF		 4397 return;
4398 }
4399
38c3dc46 4400 env->cpuid_version &= ~0xf;
036e2222 4401 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4402}
4403
d480e1af
AF		 4404static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4405{
4406 X86CPU *cpu = X86_CPU(obj);
4407 CPUX86State *env = &cpu->env;
4408 char *value;
d480e1af 4409
e42a92ae 4410 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4411 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4412 env->cpuid_vendor3);
d480e1af
AF		 4413 return value;
4414}
4415
4416static void x86_cpuid_set_vendor(Object *obj, const char *value,
4417 Error **errp)
4418{
4419 X86CPU *cpu = X86_CPU(obj);
4420 CPUX86State *env = &cpu->env;
4421 int i;
4422
9df694ee 4423 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4424 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4425 return;
4426 }
4427
4428 env->cpuid_vendor1 = 0;
4429 env->cpuid_vendor2 = 0;
4430 env->cpuid_vendor3 = 0;
4431 for (i = 0; i < 4; i++) {
4432 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4433 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4434 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4435 }
d480e1af
AF		 4436}
4437
63e886eb
AF		 4438static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4439{
4440 X86CPU *cpu = X86_CPU(obj);
4441 CPUX86State *env = &cpu->env;
4442 char *value;
4443 int i;
4444
4445 value = g_malloc(48 + 1);
4446 for (i = 0; i < 48; i++) {
4447 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4448 }
4449 value[48] = '\0';
4450 return value;
4451}
4452
938d4c25
AF		 4453static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4454 Error **errp)
dcce6675 4455{
938d4c25
AF		 4456 X86CPU *cpu = X86_CPU(obj);
4457 CPUX86State *env = &cpu->env;
dcce6675
AF		 4458 int c, len, i;
4459
4460 if (model_id == NULL) {
4461 model_id = "";
4462 }
4463 len = strlen(model_id);
d0a6acf4 4464 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4465 for (i = 0; i < 48; i++) {
4466 if (i >= len) {
4467 c = '\0';
4468 } else {
4469 c = (uint8_t)model_id[i];
4470 }
4471 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4472 }
4473}
4474
d7bce999
EB		 4475static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4476 void *opaque, Error **errp)
89e48965
AF		 4477{
4478 X86CPU *cpu = X86_CPU(obj);
4479 int64_t value;
4480
4481 value = cpu->env.tsc_khz * 1000;
51e72bc1 4482 visit_type_int(v, name, &value, errp);
89e48965
AF		 4483}
4484
d7bce999
EB		 4485static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4486 void *opaque, Error **errp)
89e48965
AF		 4487{
4488 X86CPU *cpu = X86_CPU(obj);
4489 const int64_t min = 0;
2e84849a 4490 const int64_t max = INT64_MAX;
89e48965
AF		 4491 int64_t value;
4492
668f62ec 4493 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 4494 return;
4495 }
4496 if (value < min || value > max) {
c6bd8c70
MA		 4497 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4498 name ? name : "null", value, min, max);
89e48965
AF		 4499 return;
4500 }
4501
36f96c4b 4502 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4503}
4504
7e5292b5 4505/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4506static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4507 const char *name, void *opaque,
4508 Error **errp)
8e8aba50 4509{
ede146c2 4510 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4511 FeatureWord w;
8e8aba50
EH		 4512 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4513 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4514 X86CPUFeatureWordInfoList *list = NULL;
4515
4516 for (w = 0; w < FEATURE_WORDS; w++) {
4517 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4518 /*
4519 * We didn't have MSR features when "feature-words" was
4520 * introduced. Therefore skipped other type entries.
4521 */
4522 if (wi->type != CPUID_FEATURE_WORD) {
4523 continue;
4524 }
8e8aba50 4525 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4526 qwi->cpuid_input_eax = wi->cpuid.eax;
4527 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4528 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4529 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4530 qwi->features = array[w];
8e8aba50
EH		 4531
4532 /* List will be in reverse order, but order shouldn't matter */
4533 list_entries[w].next = list;
4534 list_entries[w].value = &word_infos[w];
4535 list = &list_entries[w];
4536 }
4537
6b62d961 4538 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4539}
4540
72ac2e87
IM		 4541/* Convert all '_' in a feature string option name to '-', to make feature
4542 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4543 */
4544static inline void feat2prop(char *s)
4545{
4546 while ((s = strchr(s, '_'))) {
4547 *s = '-';
4548 }
4549}
4550
b54c9377
EH		 4551/* Return the feature property name for a feature flag bit */
4552static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4553{
ede146c2 4554 const char *name;
b54c9377
EH		 4555 /* XSAVE components are automatically enabled by other features,
4556 * so return the original feature name instead
4557 */
301e9067
YW		 4558 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) {
4559 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr;
b54c9377
EH		 4560
4561 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4562 x86_ext_save_areas[comp].bits) {
4563 w = x86_ext_save_areas[comp].feature;
4564 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4565 }
4566 }
4567
ede146c2 4568 assert(bitnr < 64);
b54c9377 4569 assert(w < FEATURE_WORDS);
ede146c2
PB		 4570 name = feature_word_info[w].feat_names[bitnr];
4571 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4572 return name;
b54c9377
EH		 4573}
4574
dc15c051
IM		 4575/* Compatibily hack to maintain legacy +-feat semantic,
4576 * where +-feat overwrites any feature set by
4577 * feat=on|feat even if the later is parsed after +-feat
4578 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4579 */
2fae0d96 4580static GList *plus_features, *minus_features;
dc15c051 4581
83a00f60
EH		 4582static gint compare_string(gconstpointer a, gconstpointer b)
4583{
4584 return g_strcmp0(a, b);
4585}
4586
8f961357
EH		 4587/* Parse "+feature,-feature,feature=foo" CPU feature string
4588 */
62a48a2a 4589static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4590 Error **errp)
8f961357 4591{
8f961357 4592 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4593 static bool cpu_globals_initialized;
83a00f60 4594 bool ambiguous = false;
62a48a2a
IM		 4595
4596 if (cpu_globals_initialized) {
4597 return;
4598 }
4599 cpu_globals_initialized = true;
8f961357 4600
f6750e95
EH		 4601 if (!features) {
4602 return;
4603 }
4604
4605 for (featurestr = strtok(features, ",");
685479bd 4606 featurestr;
f6750e95
EH		 4607 featurestr = strtok(NULL, ",")) {
4608 const char *name;
4609 const char *val = NULL;
4610 char *eq = NULL;
cf2887c9 4611 char num[32];
62a48a2a 4612 GlobalProperty *prop;
c6dc6f63 4613
f6750e95 4614 /* Compatibility syntax: */
c6dc6f63 4615 if (featurestr[0] == '+') {
2fae0d96
EH		 4616 plus_features = g_list_append(plus_features,
4617 g_strdup(featurestr + 1));
f6750e95 4618 continue;
c6dc6f63 4619 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4620 minus_features = g_list_append(minus_features,
4621 g_strdup(featurestr + 1));
f6750e95
EH		 4622 continue;
4623 }
4624
4625 eq = strchr(featurestr, '=');
4626 if (eq) {
4627 *eq++ = 0;
4628 val = eq;
c6dc6f63 4629 } else {
f6750e95 4630 val = "on";
a91987c2 4631 }
f6750e95
EH		 4632
4633 feat2prop(featurestr);
4634 name = featurestr;
4635
83a00f60 4636 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4637 warn_report("Ambiguous CPU model string. "
4638 "Don't mix both \"+%s\" and \"%s=%s\"",
4639 name, name, val);
83a00f60
EH		 4640 ambiguous = true;
4641 }
4642 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4643 warn_report("Ambiguous CPU model string. "
4644 "Don't mix both \"-%s\" and \"%s=%s\"",
4645 name, name, val);
83a00f60
EH		 4646 ambiguous = true;
4647 }
4648
f6750e95
EH		 4649 /* Special case: */
4650 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4651 int ret;
f46bfdbf 4652 uint64_t tsc_freq;
f6750e95 4653
f17fd4fd 4654 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4655 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4656 error_setg(errp, "bad numerical value %s", val);
4657 return;
4658 }
4659 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4660 val = num;
4661 name = "tsc-frequency";
c6dc6f63 4662 }
f6750e95 4663
62a48a2a
IM		 4664 prop = g_new0(typeof(*prop), 1);
4665 prop->driver = typename;
4666 prop->property = g_strdup(name);
4667 prop->value = g_strdup(val);
62a48a2a 4668 qdev_prop_register_global(prop);
f6750e95
EH		 4669 }
4670
83a00f60 4671 if (ambiguous) {
3dc6f869
AF		 4672 warn_report("Compatibility of ambiguous CPU model "
4673 "strings won't be kept on future QEMU versions");
83a00f60 4674 }
c6dc6f63
AP		 4675}
4676
245edd0c 4677static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4678
5a853fc5
EH		 4679/* Build a list with the name of all features on a feature word array */
4680static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 4681 strList **list)
5a853fc5 4682{
c3033fd3 4683 strList **tail = list;
5a853fc5 4684 FeatureWord w;
5a853fc5
EH		 4685
4686 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4687 uint64_t filtered = features[w];
5a853fc5 4688 int i;
ede146c2
PB		 4689 for (i = 0; i < 64; i++) {
4690 if (filtered & (1ULL << i)) {
c3033fd3 4691 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 4692 }
4693 }
4694 }
4695}
4696
506174bf
EH		 4697static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4698 const char *name, void *opaque,
4699 Error **errp)
4700{
4701 X86CPU *xc = X86_CPU(obj);
4702 strList *result = NULL;
4703
4704 x86_cpu_list_feature_names(xc->filtered_features, &result);
4705 visit_type_strList(v, "unavailable-features", &result, errp);
4706}
4707
b54c9377
EH		 4708/* Check for missing features that may prevent the CPU class from
4709 * running using the current machine and accelerator.
4710 */
4711static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
c3033fd3 4712 strList **list)
b54c9377 4713{
c3033fd3 4714 strList **tail = list;
b54c9377 4715 X86CPU *xc;
b54c9377 4716 Error *err = NULL;
b54c9377 4717
d6dcc558 4718 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
c3033fd3 4719 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
b54c9377
EH		 4720 return;
4721 }
4722
3c75e12e 4723 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4724
b8d834a0 4725 x86_cpu_expand_features(xc, &err);
b54c9377 4726 if (err) {
b8d834a0 4727 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4728 * but in case it does, just report the model as not
4729 * runnable at all using the "type" property.
4730 */
c3033fd3 4731 QAPI_LIST_APPEND(tail, g_strdup("type"));
3aa8203e 4732 error_free(err);
b54c9377
EH		 4733 }
4734
245edd0c 4735 x86_cpu_filter_features(xc, false);
b54c9377 4736
c3033fd3 4737 x86_cpu_list_feature_names(xc->filtered_features, tail);
b54c9377
EH		 4738
4739 object_unref(OBJECT(xc));
4740}
4741
8c3329e5 4742/* Print all cpuid feature names in featureset
c6dc6f63 4743 */
0442428a 4744static void listflags(GList *features)
0856579c 4745{
cc643b1e
DB		 4746 size_t len = 0;
4747 GList *tmp;
4748
4749 for (tmp = features; tmp; tmp = tmp->next) {
4750 const char *name = tmp->data;
4751 if ((len + strlen(name) + 1) >= 75) {
0442428a 4752 qemu_printf("\n");
cc643b1e 4753 len = 0;
c6dc6f63 4754 }
0442428a 4755 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4756 len += strlen(name) + 1;
8c3329e5 4757 }
0442428a 4758 qemu_printf("\n");
c6dc6f63
AP		 4759}
4760
f48c8837 4761/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4762static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4763{
4764 ObjectClass *class_a = (ObjectClass *)a;
4765 ObjectClass *class_b = (ObjectClass *)b;
4766 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4767 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4768 int ret;
ee465a3e 4769
f48c8837 4770 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4771 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4772 } else {
88703ce2
EH		 4773 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4774 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4775 ret = strcmp(name_a, name_b);
ee465a3e 4776 }
c7dbff4b 4777 return ret;
ee465a3e
EH		 4778}
4779
4780static GSList *get_sorted_cpu_model_list(void)
4781{
4782 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4783 list = g_slist_sort(list, x86_cpu_list_compare);
4784 return list;
4785}
4786
164e779c
EH		 4787static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4788{
3c75e12e 4789 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4790 char *r = object_property_get_str(obj, "model-id", &error_abort);
4791 object_unref(obj);
4792 return r;
4793}
4794
0788a56b
EH		 4795static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4796{
4797 X86CPUVersion version;
4798
4799 if (!cc->model || !cc->model->is_alias) {
4800 return NULL;
4801 }
4802 version = x86_cpu_model_resolve_version(cc->model);
4803 if (version <= 0) {
4804 return NULL;
4805 }
4806 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4807}
4808
ee465a3e
EH		 4809static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4810{
4811 ObjectClass *oc = data;
4812 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4813 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4814 g_autofree char *desc = g_strdup(cc->model_description);
4815 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4816 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4817
0788a56b
EH		 4818 if (!desc && alias_of) {
4819 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4820 desc = g_strdup("(alias configured by machine type)");
4821 } else {
4822 desc = g_strdup_printf("(alias of %s)", alias_of);
4823 }
4824 }
c63938df
TX		 4825 if (!desc && cc->model && cc->model->note) {
4826 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4827 }
164e779c 4828 if (!desc) {
c63938df 4829 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4830 }
4831
61848717 4832 qemu_printf("x86 %-20s %s\n", name, desc);
ee465a3e
EH		 4833}
4834
4835/* list available CPU models and flags */
0442428a 4836void x86_cpu_list(void)
c6dc6f63 4837{
cc643b1e 4838 int i, j;
ee465a3e 4839 GSList *list;
cc643b1e 4840 GList *names = NULL;
c6dc6f63 4841
0442428a 4842 qemu_printf("Available CPUs:\n");
ee465a3e 4843 list = get_sorted_cpu_model_list();
0442428a 4844 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4845 g_slist_free(list);
21ad7789 4846
cc643b1e 4847 names = NULL;
3af60be2
JK		 4848 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4849 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4850 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4851 if (fw->feat_names[j]) {
4852 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4853 }
4854 }
3af60be2 4855 }
cc643b1e
DB		 4856
4857 names = g_list_sort(names, (GCompareFunc)strcmp);
4858
0442428a
MA		 4859 qemu_printf("\nRecognized CPUID flags:\n");
4860 listflags(names);
4861 qemu_printf("\n");
cc643b1e 4862 g_list_free(names);
c6dc6f63
AP		 4863}
4864
ee465a3e
EH		 4865static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4866{
4867 ObjectClass *oc = data;
4868 X86CPUClass *cc = X86_CPU_CLASS(oc);
4869 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 4870 CpuDefinitionInfo *info;
4871
4872 info = g_malloc0(sizeof(*info));
4873 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4874 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4875 info->has_unavailable_features = true;
8ed877b7 4876 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4877 info->migration_safe = cc->migration_safe;
4878 info->has_migration_safe = true;
5adbed30 4879 info->q_static = cc->static_model;
61ad65d0
RH		 4880 if (cc->model && cc->model->cpudef->deprecation_note) {
4881 info->deprecated = true;
4882 } else {
4883 info->deprecated = false;
4884 }
0788a56b
EH		 4885 /*
4886 * Old machine types won't report aliases, so that alias translation
4887 * doesn't break compatibility with previous QEMU versions.
4888 */
4889 if (default_cpu_version != CPU_VERSION_LEGACY) {
4890 info->alias_of = x86_cpu_class_get_alias_of(cc);
4891 info->has_alias_of = !!info->alias_of;
4892 }
ee465a3e 4893
54aa3de7 4894 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 4895}
4896
25a9d6ca 4897CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4898{
4899 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4900 GSList *list = get_sorted_cpu_model_list();
4901 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4902 g_slist_free(list);
e3966126
AL		 4903 return cpu_list;
4904}
4905
58f7db26
PB		 4906uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4907 bool migratable_only)
27418adf
EH		 4908{
4909 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4910 uint64_t r = 0;
27418adf 4911
fefb41bf 4912 if (kvm_enabled()) {
07585923
RH		 4913 switch (wi->type) {
4914 case CPUID_FEATURE_WORD:
4915 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4916 wi->cpuid.ecx,
4917 wi->cpuid.reg);
4918 break;
4919 case MSR_FEATURE_WORD:
d86f9636
RH		 4920 r = kvm_arch_get_supported_msr_feature(kvm_state,
4921 wi->msr.index);
07585923
RH		 4922 break;
4923 }
d6dcc558 4924 } else if (hvf_enabled()) {
07585923
RH		 4925 if (wi->type != CPUID_FEATURE_WORD) {
4926 return 0;
4927 }
4928 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4929 wi->cpuid.ecx,
4930 wi->cpuid.reg);
fefb41bf 4931 } else if (tcg_enabled()) {
84f1b92f 4932 r = wi->tcg_features;
fefb41bf
EH		 4933 } else {
4934 return ~0;
4935 }
5ea9e9e2
PB		 4936#ifndef TARGET_X86_64
4937 if (w == FEAT_8000_0001_EDX) {
4938 r &= ~CPUID_EXT2_LM;
4939 }
4940#endif
84f1b92f
EH		 4941 if (migratable_only) {
4942 r &= x86_cpu_get_migratable_flags(w);
4943 }
4944 return r;
27418adf
EH		 4945}
4946
d19d6ffa
PB		 4947static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
4948 uint32_t *eax, uint32_t *ebx,
4949 uint32_t *ecx, uint32_t *edx)
4950{
4951 if (kvm_enabled()) {
4952 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX);
4953 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX);
4954 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX);
4955 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX);
4956 } else if (hvf_enabled()) {
4957 *eax = hvf_get_supported_cpuid(func, index, R_EAX);
4958 *ebx = hvf_get_supported_cpuid(func, index, R_EBX);
4959 *ecx = hvf_get_supported_cpuid(func, index, R_ECX);
4960 *edx = hvf_get_supported_cpuid(func, index, R_EDX);
4961 } else {
4962 *eax = 0;
4963 *ebx = 0;
4964 *ecx = 0;
4965 *edx = 0;
4966 }
4967}
4968
798d8ec0
PB		 4969static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index,
4970 uint32_t *eax, uint32_t *ebx,
4971 uint32_t *ecx, uint32_t *edx)
4972{
4973 uint32_t level, unused;
4974
4975 /* Only return valid host leaves. */
4976 switch (func) {
4977 case 2:
4978 case 4:
4979 host_cpuid(0, 0, &level, &unused, &unused, &unused);
4980 break;
4981 case 0x80000005:
4982 case 0x80000006:
4983 case 0x8000001d:
4984 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused);
4985 break;
4986 default:
4987 return;
4988 }
4989
4990 if (func > level) {
4991 *eax = 0;
4992 *ebx = 0;
4993 *ecx = 0;
4994 *edx = 0;
4995 } else {
4996 host_cpuid(func, index, eax, ebx, ecx, edx);
4997 }
4998}
4999
5b8978d8
CF		 5000/*
5001 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5002 */
f5cc5a5c 5003void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5004{
5005 PropValue *pv;
5006 for (pv = props; pv->prop; pv++) {
5007 if (!pv->value) {
5008 continue;
5009 }
5325cc34 5010 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5011 &error_abort);
5012 }
5013}
5014
5b8978d8
CF		 5015/*
5016 * Apply properties for the CPU model version specified in model.
5017 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5018 */
5019
dcafd1ef
EH		 5020static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5021{
5022 const X86CPUVersionDefinition *vdef;
5023 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5024
5025 if (version == CPU_VERSION_LEGACY) {
5026 return;
5027 }
5028
5029 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5030 PropValue *p;
5031
5032 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5033 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5034 &error_abort);
5035 }
5036
5037 if (vdef->version == version) {
5038 break;
5039 }
5040 }
5041
5042 /*
5043 * If we reached the end of the list, version number was invalid
5044 */
5045 assert(vdef->version == version);
5046}
5047
5b8978d8
CF		 5048/*
5049 * Load data from X86CPUDefinition into a X86CPU object.
5050 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 5051 */
49e2fa85 5052static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5053{
e11fd689 5054 const X86CPUDefinition *def = model->cpudef;
61dcd775 5055 CPUX86State *env = &cpu->env;
e1c224b4 5056 FeatureWord w;
c6dc6f63 5057
f99fd7ca
EH		 5058 /*NOTE: any property set by this function should be returned by
5059 * x86_cpu_static_props(), so static expansion of
5060 * query-cpu-model-expansion is always complete.
5061 */
5062
c39c0edf 5063 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5064 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5065 &error_abort);
5325cc34 5066 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5067 &error_abort);
5068
5325cc34
MA		 5069 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5070 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5071 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5072 &error_abort);
5325cc34 5073 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5074 &error_abort);
e1c224b4
EH		 5075 for (w = 0; w < FEATURE_WORDS; w++) {
5076 env->features[w] = def->features[w];
5077 }
82beb536 5078
a9f27ea9
EH		 5079 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5080 cpu->legacy_cache = !def->cache_info;
ab8f992e 5081
82beb536 5082 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5083
5084 /* sysenter isn't supported in compatibility mode on AMD,
5085 * syscall isn't supported in compatibility mode on Intel.
5086 * Normally we advertise the actual CPU vendor, but you can
5087 * override this using the 'vendor' property if you want to use
5088 * KVM's sysenter/syscall emulation in compatibility mode and
5089 * when doing cross vendor migration
5090 */
7c08db30 5091
f5cc5a5c
CF		 5092 /*
5093 * vendor property is set here but then overloaded with the
5094 * host cpu vendor for KVM and HVF.
5095 */
5096 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5097
dcafd1ef 5098 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5099
5100 /*
5101 * Properties in versioned CPU model are not user specified features.
5102 * We can simply clear env->user_features here since it will be filled later
5103 * in x86_cpu_expand_features() based on plus_features and minus_features.
5104 */
5105 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5106}
5107
00fcd100
AB		 5108static gchar *x86_gdb_arch_name(CPUState *cs)
5109{
5110#ifdef TARGET_X86_64
5111 return g_strdup("i386:x86-64");
5112#else
5113 return g_strdup("i386");
5114#endif
5115}
5116
d940ee9b
EH		 5117static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5118{
dcafd1ef 5119 X86CPUModel *model = data;
d940ee9b 5120 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5121 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5122
dcafd1ef 5123 xcc->model = model;
bd72159d 5124 xcc->migration_safe = true;
61ad65d0 5125 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5126}
5127
dcafd1ef 5128static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5129{
88703ce2 5130 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5131 TypeInfo ti = {
5132 .name = typename,
5133 .parent = TYPE_X86_CPU,
5134 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5135 .class_data = model,
d940ee9b
EH		 5136 };
5137
dcafd1ef 5138 type_register(&ti);
dcafd1ef
EH		 5139}
5140
5b8978d8
CF		 5141
5142/*
5143 * register builtin_x86_defs;
5144 * "max", "base" and subclasses ("host") are not registered here.
5145 * See x86_cpu_register_types for all model registrations.
5146 */
e11fd689 5147static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5148{
5149 X86CPUModel *m;
5150 const X86CPUVersionDefinition *vdef;
dcafd1ef 5151
2a923a29
EH		 5152 /* AMD aliases are handled at runtime based on CPUID vendor, so
5153 * they shouldn't be set on the CPU model table.
5154 */
5155 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5156 /* catch mistakes instead of silently truncating model_id when too long */
5157 assert(def->model_id && strlen(def->model_id) <= 48);
5158
dcafd1ef
EH		 5159 /* Unversioned model: */
5160 m = g_new0(X86CPUModel, 1);
5161 m->cpudef = def;
0788a56b
EH		 5162 m->version = CPU_VERSION_AUTO;
5163 m->is_alias = true;
dcafd1ef
EH		 5164 x86_register_cpu_model_type(def->name, m);
5165
5166 /* Versioned models: */
5167
5168 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5169 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5170 g_autofree char *name =
5171 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5172 m->cpudef = def;
5173 m->version = vdef->version;
c63938df 5174 m->note = vdef->note;
dcafd1ef 5175 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5176
5177 if (vdef->alias) {
5178 X86CPUModel *am = g_new0(X86CPUModel, 1);
5179 am->cpudef = def;
5180 am->version = vdef->version;
0788a56b 5181 am->is_alias = true;
53db89d9
EH		 5182 x86_register_cpu_model_type(vdef->alias, am);
5183 }
dcafd1ef 5184 }
2a923a29 5185
d940ee9b
EH		 5186}
5187
97afb47e
LL		 5188uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
5189{
5190 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5191 return 57; /* 57 bits virtual */
5192 } else {
5193 return 48; /* 48 bits virtual */
5194 }
5195}
5196
c6dc6f63
AP		 5197void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5198 uint32_t *eax, uint32_t *ebx,
5199 uint32_t *ecx, uint32_t *edx)
5200{
6aa9e42f
RH		 5201 X86CPU *cpu = env_archcpu(env);
5202 CPUState *cs = env_cpu(env);
d65af288 5203 uint32_t die_offset;
4ed3d478 5204 uint32_t limit;
1ce36bfe 5205 uint32_t signature[3];
f20dec0b
BM		 5206 X86CPUTopoInfo topo_info;
5207
5208 topo_info.dies_per_pkg = env->nr_dies;
5209 topo_info.cores_per_die = cs->nr_cores;
5210 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5211
4ed3d478
DB		 5212 /* Calculate & apply limits for different index ranges */
5213 if (index >= 0xC0000000) {
5214 limit = env->cpuid_xlevel2;
5215 } else if (index >= 0x80000000) {
5216 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5217 } else if (index >= 0x40000000) {
5218 limit = 0x40000001;
c6dc6f63 5219 } else {
4ed3d478
DB		 5220 limit = env->cpuid_level;
5221 }
5222
5223 if (index > limit) {
5224 /* Intel documentation states that invalid EAX input will
5225 * return the same information as EAX=cpuid_level
5226 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5227 */
5228 index = env->cpuid_level;
c6dc6f63
AP		 5229 }
5230
5231 switch(index) {
5232 case 0:
5233 *eax = env->cpuid_level;
5eb2f7a4
EH		 5234 *ebx = env->cpuid_vendor1;
5235 *edx = env->cpuid_vendor2;
5236 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5237 break;
5238 case 1:
5239 *eax = env->cpuid_version;
7e72a45c
EH		 5240 *ebx = (cpu->apic_id << 24) |
5241 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5242 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5243 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5244 *ecx |= CPUID_EXT_OSXSAVE;
5245 }
0514ef2f 5246 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5247 if (cs->nr_cores * cs->nr_threads > 1) {
5248 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5249 *edx |= CPUID_HT;
c6dc6f63 5250 }
ea39f9b6
LX		 5251 if (!cpu->enable_pmu) {
5252 *ecx &= ~CPUID_EXT_PDCM;
5253 }
c6dc6f63
AP		 5254 break;
5255 case 2:
5256 /* cache info: needed for Pentium Pro compatibility */
787aaf57 5257 if (cpu->cache_info_passthrough) {
798d8ec0 5258 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57 5259 break;
a7a0da84
MR		 5260 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5261 *eax = *ebx = *ecx = *edx = 0;
5262 break;
787aaf57 5263 }
5e891bf8 5264 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5265 *ebx = 0;
14c985cf
LM		 5266 if (!cpu->enable_l3_cache) {
5267 *ecx = 0;
5268 } else {
a9f27ea9 5269 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5270 }
a9f27ea9
EH		 5271 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5272 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5273 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5274 break;
5275 case 4:
5276 /* cache info: needed for Core compatibility */
787aaf57 5277 if (cpu->cache_info_passthrough) {
798d8ec0 5278 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5279 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5280 *eax &= ~0xFC000000;
7e3482f8
EH		 5281 if ((*eax & 31) && cs->nr_cores > 1) {
5282 *eax |= (cs->nr_cores - 1) << 26;
5283 }
a7a0da84
MR		 5284 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
5285 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5286 } else {
2f7a21c4 5287 *eax = 0;
76c2975a 5288 switch (count) {
c6dc6f63 5289 case 0: /* L1 dcache info */
a9f27ea9
EH		 5290 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5291 1, cs->nr_cores,
7e3482f8 5292 eax, ebx, ecx, edx);
c6dc6f63
AP		 5293 break;
5294 case 1: /* L1 icache info */
a9f27ea9
EH		 5295 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5296 1, cs->nr_cores,
7e3482f8 5297 eax, ebx, ecx, edx);
c6dc6f63
AP		 5298 break;
5299 case 2: /* L2 cache info */
a9f27ea9
EH		 5300 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5301 cs->nr_threads, cs->nr_cores,
7e3482f8 5302 eax, ebx, ecx, edx);
c6dc6f63 5303 break;
14c985cf 5304 case 3: /* L3 cache info */
f20dec0b 5305 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5306 if (cpu->enable_l3_cache) {
a9f27ea9 5307 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5308 (1 << die_offset), cs->nr_cores,
7e3482f8 5309 eax, ebx, ecx, edx);
14c985cf
LM		 5310 break;
5311 }
7e3482f8 5312 /* fall through */
c6dc6f63 5313 default: /* end of info */
7e3482f8 5314 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5315 break;
76c2975a
PB		 5316 }
5317 }
c6dc6f63
AP		 5318 break;
5319 case 5:
2266d443
MT		 5320 /* MONITOR/MWAIT Leaf */
5321 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5322 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5323 *ecx = cpu->mwait.ecx; /* flags */
5324 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5325 break;
5326 case 6:
5327 /* Thermal and Power Leaf */
28b8e4d0 5328 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5329 *ebx = 0;
5330 *ecx = 0;
5331 *edx = 0;
5332 break;
f7911686 5333 case 7:
13526728
EH		 5334 /* Structured Extended Feature Flags Enumeration Leaf */
5335 if (count == 0) {
80db491d
JL		 5336 /* Maximum ECX value for sub-leaves */
5337 *eax = env->cpuid_level_func7;
0514ef2f 5338 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5339 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5340 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5341 *ecx |= CPUID_7_0_ECX_OSPKE;
5342 }
95ea69fb 5343 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 5344
5345 /*
5346 * SGX cannot be emulated in software. If hardware does not
5347 * support enabling SGX and/or SGX flexible launch control,
5348 * then we need to update the VM's CPUID values accordingly.
5349 */
5350 if ((*ebx & CPUID_7_0_EBX_SGX) &&
5351 (!kvm_enabled() ||
5352 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) &
5353 CPUID_7_0_EBX_SGX))) {
5354 *ebx &= ~CPUID_7_0_EBX_SGX;
5355 }
5356
5357 if ((*ecx & CPUID_7_0_ECX_SGX_LC) &&
5358 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() ||
5359 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) &
5360 CPUID_7_0_ECX_SGX_LC))) {
5361 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
5362 }
80db491d
JL		 5363 } else if (count == 1) {
5364 *eax = env->features[FEAT_7_1_EAX];
5365 *ebx = 0;
5366 *ecx = 0;
5367 *edx = 0;
f7911686
YW		 5368 } else {
5369 *eax = 0;
5370 *ebx = 0;
5371 *ecx = 0;
5372 *edx = 0;
5373 }
5374 break;
c6dc6f63
AP		 5375 case 9:
5376 /* Direct Cache Access Information Leaf */
5377 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5378 *ebx = 0;
5379 *ecx = 0;
5380 *edx = 0;
5381 break;
5382 case 0xA:
5383 /* Architectural Performance Monitoring Leaf */
d19d6ffa
PB		 5384 if (accel_uses_host_cpuid() && cpu->enable_pmu) {
5385 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx);
a0fa8208
GN		 5386 } else {
5387 *eax = 0;
5388 *ebx = 0;
5389 *ecx = 0;
5390 *edx = 0;
5391 }
c6dc6f63 5392 break;
5232d00a
RK		 5393 case 0xB:
5394 /* Extended Topology Enumeration Leaf */
5395 if (!cpu->enable_cpuid_0xb) {
5396 *eax = *ebx = *ecx = *edx = 0;
5397 break;
5398 }
5399
5400 *ecx = count & 0xff;
5401 *edx = cpu->apic_id;
5402
5403 switch (count) {
5404 case 0:
f20dec0b 5405 *eax = apicid_core_offset(&topo_info);
eab60fb9 5406 *ebx = cs->nr_threads;
5232d00a
RK		 5407 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5408 break;
5409 case 1:
fb49865d 5410 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5411 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5412 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5413 break;
5414 default:
5415 *eax = 0;
5416 *ebx = 0;
5417 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5418 }
5419
a94e1428
LX		 5420 assert(!(*eax & ~0x1f));
5421 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5422 break;
5423 case 0x1F:
5424 /* V2 Extended Topology Enumeration Leaf */
5425 if (env->nr_dies < 2) {
5426 *eax = *ebx = *ecx = *edx = 0;
5427 break;
5428 }
5429
5430 *ecx = count & 0xff;
5431 *edx = cpu->apic_id;
5432 switch (count) {
5433 case 0:
f20dec0b 5434 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5435 *ebx = cs->nr_threads;
5436 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5437 break;
5438 case 1:
f20dec0b 5439 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5440 *ebx = cs->nr_cores * cs->nr_threads;
5441 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5442 break;
5443 case 2:
fb49865d 5444 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5445 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5446 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5447 break;
5448 default:
5449 *eax = 0;
5450 *ebx = 0;
5451 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5452 }
5232d00a
RK		 5453 assert(!(*eax & ~0x1f));
5454 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5455 break;
2560f19f 5456 case 0xD: {
51e49430 5457 /* Processor Extended State */
2560f19f
PB		 5458 *eax = 0;
5459 *ebx = 0;
5460 *ecx = 0;
5461 *edx = 0;
19dc85db 5462 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5463 break;
5464 }
4928cd6d 5465
2560f19f 5466 if (count == 0) {
301e9067
YW		 5467 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false);
5468 *eax = env->features[FEAT_XSAVE_XCR0_LO];
5469 *edx = env->features[FEAT_XSAVE_XCR0_HI];
76ecd7a5
BS		 5470 /*
5471 * The initial value of xcr0 and ebx == 0, On host without kvm
5472 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5473 * even through guest update xcr0, this will crash some legacy guest
5474 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5475 */
301e9067 5476 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false);
2560f19f 5477 } else if (count == 1) {
301e9067
YW		 5478 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) |
5479 x86_cpu_xsave_xss_components(cpu);
5480
0bb0b2d2 5481 *eax = env->features[FEAT_XSAVE];
301e9067
YW		 5482 *ebx = xsave_area_size(xstate, true);
5483 *ecx = env->features[FEAT_XSAVE_XSS_LO];
5484 *edx = env->features[FEAT_XSAVE_XSS_HI];
f4f1110e 5485 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
301e9067
YW		 5486 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5487
5488 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) {
33f373d7
LJ		 5489 *eax = esa->size;
5490 *ebx = esa->offset;
0f17f6b3
JL		 5491 *ecx = esa->ecx &
5492 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
301e9067
YW		 5493 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) {
5494 *eax = esa->size;
5495 *ebx = 0;
5496 *ecx = 1;
2560f19f 5497 }
51e49430
SY		 5498 }
5499 break;
2560f19f 5500 }
1dec2e1f
SC		 5501 case 0x12:
5502#ifndef CONFIG_USER_ONLY
5503 if (!kvm_enabled() ||
5504 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
5505 *eax = *ebx = *ecx = *edx = 0;
5506 break;
5507 }
5508
5509 /*
5510 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
5511 * the EPC properties, e.g. confidentiality and integrity, from the
5512 * host's first EPC section, i.e. assume there is one EPC section or
5513 * that all EPC sections have the same security properties.
5514 */
5515 if (count > 1) {
5516 uint64_t epc_addr, epc_size;
5517
5518 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
5519 *eax = *ebx = *ecx = *edx = 0;
5520 break;
5521 }
5522 host_cpuid(index, 2, eax, ebx, ecx, edx);
5523 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
5524 *ebx = (uint32_t)(epc_addr >> 32);
5525 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
5526 *edx = (uint32_t)(epc_size >> 32);
5527 break;
5528 }
5529
5530 /*
5531 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
5532 * and KVM, i.e. QEMU cannot emulate features to override what KVM
5533 * supports. Features can be further restricted by userspace, but not
5534 * made more permissive.
5535 */
d19d6ffa 5536 x86_cpu_get_supported_cpuid(0x12, index, eax, ebx, ecx, edx);
1dec2e1f
SC		 5537
5538 if (count == 0) {
5539 *eax &= env->features[FEAT_SGX_12_0_EAX];
5540 *ebx &= env->features[FEAT_SGX_12_0_EBX];
5541 } else {
5542 *eax &= env->features[FEAT_SGX_12_1_EAX];
5543 *ebx &= 0; /* ebx reserve */
301e9067
YW		 5544 *ecx &= env->features[FEAT_XSAVE_XSS_LO];
5545 *edx &= env->features[FEAT_XSAVE_XSS_HI];
1dec2e1f
SC		 5546
5547 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
5548 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
5549
5550 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 5551 if ((*eax & (1U << 4)) &&
5552 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
5553 *eax &= ~(1U << 4);
5554 }
1dec2e1f
SC		 5555 }
5556#endif
5557 break;
e37a5c7f
CP		 5558 case 0x14: {
5559 /* Intel Processor Trace Enumeration */
5560 *eax = 0;
5561 *ebx = 0;
5562 *ecx = 0;
5563 *edx = 0;
5564 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5565 !kvm_enabled()) {
5566 break;
5567 }
5568
5569 if (count == 0) {
5570 *eax = INTEL_PT_MAX_SUBLEAF;
5571 *ebx = INTEL_PT_MINIMAL_EBX;
5572 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 5573 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5574 *ecx |= CPUID_14_0_ECX_LIP;
5575 }
e37a5c7f
CP		 5576 } else if (count == 1) {
5577 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5578 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5579 }
5580 break;
5581 }
f21a4817
JL		 5582 case 0x1D: {
5583 /* AMX TILE */
5584 *eax = 0;
5585 *ebx = 0;
5586 *ecx = 0;
5587 *edx = 0;
5588 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
5589 break;
5590 }
5591
5592 if (count == 0) {
5593 /* Highest numbered palette subleaf */
5594 *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
5595 } else if (count == 1) {
5596 *eax = INTEL_AMX_TOTAL_TILE_BYTES |
5597 (INTEL_AMX_BYTES_PER_TILE << 16);
5598 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
5599 *ecx = INTEL_AMX_TILE_MAX_ROWS;
5600 }
5601 break;
5602 }
5603 case 0x1E: {
5604 /* AMX TMUL */
5605 *eax = 0;
5606 *ebx = 0;
5607 *ecx = 0;
5608 *edx = 0;
5609 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
5610 break;
5611 }
5612
5613 if (count == 0) {
5614 /* Highest numbered palette subleaf */
5615 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
5616 }
5617 break;
5618 }
1ce36bfe
DB		 5619 case 0x40000000:
5620 /*
5621 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5622 * set here, but we restrict to TCG none the less.
5623 */
5624 if (tcg_enabled() && cpu->expose_tcg) {
5625 memcpy(signature, "TCGTCGTCGTCG", 12);
5626 *eax = 0x40000001;
5627 *ebx = signature[0];
5628 *ecx = signature[1];
5629 *edx = signature[2];
5630 } else {
5631 *eax = 0;
5632 *ebx = 0;
5633 *ecx = 0;
5634 *edx = 0;
5635 }
5636 break;
5637 case 0x40000001:
5638 *eax = 0;
5639 *ebx = 0;
5640 *ecx = 0;
5641 *edx = 0;
5642 break;
c6dc6f63
AP		 5643 case 0x80000000:
5644 *eax = env->cpuid_xlevel;
5645 *ebx = env->cpuid_vendor1;
5646 *edx = env->cpuid_vendor2;
5647 *ecx = env->cpuid_vendor3;
5648 break;
5649 case 0x80000001:
5650 *eax = env->cpuid_version;
5651 *ebx = 0;
0514ef2f
EH		 5652 *ecx = env->features[FEAT_8000_0001_ECX];
5653 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5654
5655 /* The Linux kernel checks for the CMPLegacy bit and
5656 * discards multiple thread information if it is set.
cb8d4c8f 5657 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5658 */
ce3960eb 5659 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5660 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5661 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5662 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5663 *ecx |= 1 << 1; /* CmpLegacy bit */
5664 }
5665 }
c6dc6f63
AP		 5666 break;
5667 case 0x80000002:
5668 case 0x80000003:
5669 case 0x80000004:
5670 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5671 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5672 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5673 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5674 break;
5675 case 0x80000005:
5676 /* cache info (L1 cache) */
787aaf57 5677 if (cpu->cache_info_passthrough) {
798d8ec0 5678 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 5679 break;
5680 }
78ee6bd0 5681 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 5682 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 5683 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 5684 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5685 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5686 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5687 break;
5688 case 0x80000006:
5689 /* cache info (L2 cache) */
787aaf57 5690 if (cpu->cache_info_passthrough) {
798d8ec0 5691 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 5692 break;
5693 }
78ee6bd0
PMD		 5694 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5695 (L2_DTLB_2M_ENTRIES << 16) |
5696 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 5697 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 5698 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5699 (L2_DTLB_4K_ENTRIES << 16) |
5700 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 5701 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5702 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5703 cpu->enable_l3_cache ?
5704 env->cache_info_amd.l3_cache : NULL,
5705 ecx, edx);
c6dc6f63 5706 break;
303752a9
MT		 5707 case 0x80000007:
5708 *eax = 0;
5709 *ebx = 0;
5710 *ecx = 0;
5711 *edx = env->features[FEAT_8000_0007_EDX];
5712 break;
c6dc6f63
AP		 5713 case 0x80000008:
5714 /* virtual & phys address size in low 2 bytes. */
97afb47e 5715 *eax = cpu->phys_bits;
0514ef2f 5716 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 5717 /* 64 bit processor */
97afb47e 5718 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
c6dc6f63 5719 }
1b3420e1 5720 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 5721 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 5722 /*
5723 * Bits 15:12 is "The number of bits in the initial
5724 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 5725 * thread ID within a package".
cac9edfc
BM		 5726 * Bits 7:0 is "The number of threads in the package is NC+1"
5727 */
fb49865d 5728 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 5729 ((cs->nr_cores * cs->nr_threads) - 1);
5730 } else {
5731 *ecx = 0;
c6dc6f63 5732 }
cac9edfc 5733 *edx = 0;
c6dc6f63
AP		 5734 break;
5735 case 0x8000000A:
0514ef2f 5736 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5737 *eax = 0x00000001; /* SVM Revision */
5738 *ebx = 0x00000010; /* nr of ASIDs */
5739 *ecx = 0;
0514ef2f 5740 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5741 } else {
5742 *eax = 0;
5743 *ebx = 0;
5744 *ecx = 0;
5745 *edx = 0;
5746 }
c6dc6f63 5747 break;
8f4202fb
BM		 5748 case 0x8000001D:
5749 *eax = 0;
a4e0b436 5750 if (cpu->cache_info_passthrough) {
798d8ec0 5751 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
a4e0b436
SL		 5752 break;
5753 }
8f4202fb
BM		 5754 switch (count) {
5755 case 0: /* L1 dcache info */
2f084d1e
BM		 5756 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5757 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5758 break;
5759 case 1: /* L1 icache info */
2f084d1e
BM		 5760 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5761 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5762 break;
5763 case 2: /* L2 cache info */
2f084d1e
BM		 5764 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5765 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5766 break;
5767 case 3: /* L3 cache info */
2f084d1e
BM		 5768 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5769 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5770 break;
5771 default: /* end of info */
5772 *eax = *ebx = *ecx = *edx = 0;
5773 break;
5774 }
5775 break;
ed78467a 5776 case 0x8000001E:
35ac5dfb
BM		 5777 if (cpu->core_id <= 255) {
5778 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5779 } else {
5780 *eax = 0;
5781 *ebx = 0;
5782 *ecx = 0;
5783 *edx = 0;
5784 }
ed78467a 5785 break;
b3baa152
BW		 5786 case 0xC0000000:
5787 *eax = env->cpuid_xlevel2;
5788 *ebx = 0;
5789 *ecx = 0;
5790 *edx = 0;
5791 break;
5792 case 0xC0000001:
5793 /* Support for VIA CPU's CPUID instruction */
5794 *eax = env->cpuid_version;
5795 *ebx = 0;
5796 *ecx = 0;
0514ef2f 5797 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5798 break;
5799 case 0xC0000002:
5800 case 0xC0000003:
5801 case 0xC0000004:
5802 /* Reserved for the future, and now filled with zero */
5803 *eax = 0;
5804 *ebx = 0;
5805 *ecx = 0;
5806 *edx = 0;
5807 break;
6cb8f2a6 5808 case 0x8000001F:
02eacf31
PMD		 5809 *eax = *ebx = *ecx = *edx = 0;
5810 if (sev_enabled()) {
5811 *eax = 0x2;
5812 *eax |= sev_es_enabled() ? 0x8 : 0;
5813 *ebx = sev_get_cbit_position();
5814 *ebx |= sev_get_reduced_phys_bits() << 6;
5815 }
6cb8f2a6 5816 break;
c6dc6f63
AP		 5817 default:
5818 /* reserved values: zero */
5819 *eax = 0;
5820 *ebx = 0;
5821 *ecx = 0;
5822 *edx = 0;
5823 break;
5824 }
5825}
5fd2087a 5826
db888065
SC		 5827static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
5828{
5829#ifndef CONFIG_USER_ONLY
5830 /* Those default values are defined in Skylake HW */
5831 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
5832 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
5833 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
5834 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
5835#endif
5836}
5837
781c67ca 5838static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5839{
781c67ca 5840 CPUState *s = CPU(dev);
5fd2087a
AF		 5841 X86CPU *cpu = X86_CPU(s);
5842 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5843 CPUX86State *env = &cpu->env;
a114d25d
RH		 5844 target_ulong cr4;
5845 uint64_t xcr0;
c1958aea
AF		 5846 int i;
5847
781c67ca 5848 xcc->parent_reset(dev);
5fd2087a 5849
5e992a8e 5850 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5851
c1958aea
AF		 5852 env->old_exception = -1;
5853
5854 /* init to reset state */
e3126a5c 5855 env->int_ctl = 0;
c1958aea 5856 env->hflags2 |= HF2_GIF_MASK;
b67e2796 5857 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 5858 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 5859
5860 cpu_x86_update_cr0(env, 0x60000010);
5861 env->a20_mask = ~0x0;
5862 env->smbase = 0x30000;
e13713db 5863 env->msr_smi_count = 0;
c1958aea
AF		 5864
5865 env->idt.limit = 0xffff;
5866 env->gdt.limit = 0xffff;
5867 env->ldt.limit = 0xffff;
5868 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5869 env->tr.limit = 0xffff;
5870 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5871
5872 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5873 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5874 DESC_R_MASK | DESC_A_MASK);
5875 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5876 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5877 DESC_A_MASK);
5878 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5879 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5880 DESC_A_MASK);
5881 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5882 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5883 DESC_A_MASK);
5884 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5885 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5886 DESC_A_MASK);
5887 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5888 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5889 DESC_A_MASK);
5890
5891 env->eip = 0xfff0;
5892 env->regs[R_EDX] = env->cpuid_version;
5893
5894 env->eflags = 0x2;
5895
5896 /* FPU init */
5897 for (i = 0; i < 8; i++) {
5898 env->fptags[i] = 1;
5899 }
5bde1407 5900 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5901
5902 env->mxcsr = 0x1f80;
a114d25d
RH		 5903 /* All units are in INIT state. */
5904 env->xstate_bv = 0;
c1958aea
AF		 5905
5906 env->pat = 0x0007040600070406ULL;
5286c366
PB		 5907
5908 if (kvm_enabled()) {
5909 /*
5910 * KVM handles TSC = 0 specially and thinks we are hot-plugging
5911 * a new CPU, use 1 instead to force a reset.
5912 */
5913 if (env->tsc != 0) {
5914 env->tsc = 1;
5915 }
5916 } else {
5917 env->tsc = 0;
5918 }
5919
c1958aea 5920 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5921 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5922 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5923 }
c1958aea
AF		 5924
5925 memset(env->dr, 0, sizeof(env->dr));
5926 env->dr[6] = DR6_FIXED_1;
5927 env->dr[7] = DR7_FIXED_1;
b3310ab3 5928 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5929 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5930
a114d25d 5931 cr4 = 0;
cfc3b074 5932 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5933
5934#ifdef CONFIG_USER_ONLY
5935 /* Enable all the features for user-mode. */
5936 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5937 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5938 }
0f70ed47
PB		 5939 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5940 const ExtSaveArea *esa = &x86_ext_save_areas[i];
301e9067
YW		 5941 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
5942 continue;
5943 }
9646f492 5944 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5945 xcr0 |= 1ull << i;
5946 }
a114d25d 5947 }
0f70ed47 5948
a114d25d
RH		 5949 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5950 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5951 }
07929f2a
RH		 5952 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5953 cr4 |= CR4_FSGSBASE_MASK;
5954 }
a114d25d
RH		 5955#endif
5956
5957 env->xcr0 = xcr0;
5958 cpu_x86_update_cr4(env, cr4);
0522604b 5959
9db2efd9
AW		 5960 /*
5961 * SDM 11.11.5 requires:
5962 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5963 * - IA32_MTRR_PHYSMASKn.V = 0
5964 * All other bits are undefined. For simplification, zero it all.
5965 */
5966 env->mtrr_deftype = 0;
5967 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
5968 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
5969
b7394c83 5970 env->interrupt_injected = -1;
fd13f23b
LA		 5971 env->exception_nr = -1;
5972 env->exception_pending = 0;
5973 env->exception_injected = 0;
5974 env->exception_has_payload = false;
5975 env->exception_payload = 0;
b7394c83 5976 env->nmi_injected = false;
dd673288
IM		 5977#if !defined(CONFIG_USER_ONLY)
5978 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 5979 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 5980
259186a7 5981 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 5982
5983 if (kvm_enabled()) {
5984 kvm_arch_reset_vcpu(cpu);
5985 }
db888065
SC		 5986
5987 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862 5988
3e4546d5 5989 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
cabf9862 5990
dd673288 5991#endif
5fd2087a
AF		 5992}
5993
de024815
AF		 5994static void mce_init(X86CPU *cpu)
5995{
5996 CPUX86State *cenv = &cpu->env;
5997 unsigned int bank;
5998
5999 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 6000 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 6001 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 6002 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6003 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 6004 cenv->mcg_ctl = ~(uint64_t)0;
6005 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6006 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6007 }
6008 }
6009}
6010
c39c0edf
EH		 6011static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6012{
6013 if (*min < value) {
6014 *min = value;
6015 }
6016}
6017
6018/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6019static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6020{
6021 CPUX86State *env = &cpu->env;
6022 FeatureWordInfo *fi = &feature_word_info[w];
07585923 6023 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 6024 uint32_t region = eax & 0xF0000000;
6025
07585923 6026 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 6027 if (!env->features[w]) {
6028 return;
6029 }
6030
6031 switch (region) {
6032 case 0x00000000:
6033 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6034 break;
6035 case 0x80000000:
6036 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6037 break;
6038 case 0xC0000000:
6039 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6040 break;
6041 }
80db491d
JL		 6042
6043 if (eax == 7) {
6044 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6045 fi->cpuid.ecx);
6046 }
c39c0edf
EH		 6047}
6048
2ca8a8be
EH		 6049/* Calculate XSAVE components based on the configured CPU feature flags */
6050static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6051{
6052 CPUX86State *env = &cpu->env;
6053 int i;
96193c22 6054 uint64_t mask;
19db68ca 6055 static bool request_perm;
2ca8a8be
EH		 6056
6057 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
301e9067
YW		 6058 env->features[FEAT_XSAVE_XCR0_LO] = 0;
6059 env->features[FEAT_XSAVE_XCR0_HI] = 0;
2ca8a8be
EH		 6060 return;
6061 }
6062
e3c9022b
EH		 6063 mask = 0;
6064 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6065 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6066 if (env->features[esa->feature] & esa->bits) {
96193c22 6067 mask |= (1ULL << i);
2ca8a8be
EH		 6068 }
6069 }
6070
19db68ca
YZ		 6071 /* Only request permission for first vcpu */
6072 if (kvm_enabled() && !request_perm) {
6073 kvm_request_xsave_components(cpu, mask);
6074 request_perm = true;
6075 }
6076
301e9067
YW		 6077 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK;
6078 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32;
6079 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK;
6080 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32;
2ca8a8be
EH		 6081}
6082
b8d834a0
EH		 6083/***** Steps involved on loading and filtering CPUID data
6084 *
6085 * When initializing and realizing a CPU object, the steps
6086 * involved in setting up CPUID data are:
6087 *
6088 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6089 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6090 * transparent, as it is done automatically by instance_init.
6091 * No code should need to look at X86CPUDefinition structs
6092 * outside instance_init.
6093 *
6094 * 2) CPU expansion. This is done by realize before CPUID
6095 * filtering, and will make sure host/accelerator data is
6096 * loaded for CPU models that depend on host capabilities
6097 * (e.g. "host"). Done by x86_cpu_expand_features().
6098 *
6099 * 3) CPUID filtering. This initializes extra data related to
6100 * CPUID, and checks if the host supports all capabilities
6101 * required by the CPU. Runnability of a CPU model is
6102 * determined at this step. Done by x86_cpu_filter_features().
6103 *
6104 * Some operations don't require all steps to be performed.
6105 * More precisely:
6106 *
6107 * - CPU instance creation (instance_init) will run only CPU
6108 * model loading. CPU expansion can't run at instance_init-time
6109 * because host/accelerator data may be not available yet.
6110 * - CPU realization will perform both CPU model expansion and CPUID
6111 * filtering, and return an error in case one of them fails.
6112 * - query-cpu-definitions needs to run all 3 steps. It needs
6113 * to run CPUID filtering, as the 'unavailable-features'
6114 * field is set based on the filtering results.
6115 * - The query-cpu-model-expansion QMP command only needs to run
6116 * CPU model loading and CPU expansion. It should not filter
6117 * any CPUID data based on host capabilities.
6118 */
6119
6120/* Expand CPU configuration data, based on configured features
6121 * and host/accelerator capabilities when appropriate.
6122 */
79f1a68a 6123void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6124{
b34d12d1 6125 CPUX86State *env = &cpu->env;
dc15c051 6126 FeatureWord w;
99e24dbd 6127 int i;
2fae0d96 6128 GList *l;
9886e834 6129
99e24dbd
PB		 6130 for (l = plus_features; l; l = l->next) {
6131 const char *prop = l->data;
992861fb
MA		 6132 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6133 return;
99e24dbd
PB		 6134 }
6135 }
6136
6137 for (l = minus_features; l; l = l->next) {
6138 const char *prop = l->data;
992861fb
MA		 6139 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6140 return;
99e24dbd
PB		 6141 }
6142 }
6143
d4a606b3
EH		 6144 /*TODO: Now cpu->max_features doesn't overwrite features
6145 * set using QOM properties, and we can convert
dc15c051
IM		 6146 * plus_features & minus_features to global properties
6147 * inside x86_cpu_parse_featurestr() too.
6148 */
44bd8e53 6149 if (cpu->max_features) {
dc15c051 6150 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6151 /* Override only features that weren't set explicitly
6152 * by the user.
6153 */
6154 env->features[w] |=
6155 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 6156 ~env->user_features[w] &
0d914f39 6157 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6158 }
6159 }
6160
99e24dbd
PB		 6161 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6162 FeatureDep *d = &feature_dependencies[i];
6163 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6164 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6165
99e24dbd
PB		 6166 /* Not an error unless the dependent feature was added explicitly. */
6167 mark_unavailable_features(cpu, d->to.index,
6168 unavailable_features & env->user_features[d->to.index],
6169 "This feature depends on other features that were not requested");
6170
99e24dbd 6171 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6172 }
dc15c051
IM		 6173 }
6174
aec661de
EH		 6175 if (!kvm_enabled() || !cpu->expose_kvm) {
6176 env->features[FEAT_KVM] = 0;
6177 }
6178
2ca8a8be 6179 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6180
6181 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6182 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6183 if (cpu->full_cpuid_auto_level) {
6184 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6185 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6186 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6187 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6188 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6189 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6190 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6191 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6192 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6193 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6194 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6195 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6196
6197 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 6198 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6199 if (cpu->intel_pt_auto_level) {
6200 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6201 } else if (cpu->env.cpuid_min_level < 0x14) {
6202 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6203 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 6204 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 6205 }
f24c3a79
LK		 6206 }
6207
760746ac
ZP		 6208 /*
6209 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6210 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6211 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6212 * cpu->vendor_cpuid_only has been unset for compatibility with older
6213 * machine types.
6214 */
6215 if ((env->nr_dies > 1) &&
6216 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 6217 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6218 }
6219
0c3d7c00
EH		 6220 /* SVM requires CPUID[0x8000000A] */
6221 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6222 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6223 }
6cb8f2a6
BS		 6224
6225 /* SEV requires CPUID[0x8000001F] */
6226 if (sev_enabled()) {
6227 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6228 }
dca6cffc
SC		 6229
6230 /* SGX requires CPUID[0x12] for EPC enumeration */
6231 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
6232 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
6233 }
c39c0edf
EH		 6234 }
6235
6236 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6237 if (env->cpuid_level_func7 == UINT32_MAX) {
6238 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6239 }
c39c0edf
EH		 6240 if (env->cpuid_level == UINT32_MAX) {
6241 env->cpuid_level = env->cpuid_min_level;
6242 }
6243 if (env->cpuid_xlevel == UINT32_MAX) {
6244 env->cpuid_xlevel = env->cpuid_min_xlevel;
6245 }
6246 if (env->cpuid_xlevel2 == UINT32_MAX) {
6247 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6248 }
071ce4b0
VK		 6249
6250 if (kvm_enabled()) {
6251 kvm_hyperv_expand_features(cpu, errp);
6252 }
41f3d4d6
EH		 6253}
6254
b8d834a0
EH		 6255/*
6256 * Finishes initialization of CPUID data, filters CPU feature
6257 * words based on host availability of each feature.
6258 *
6259 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6260 */
245edd0c 6261static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6262{
6263 CPUX86State *env = &cpu->env;
6264 FeatureWord w;
245edd0c
PB		 6265 const char *prefix = NULL;
6266
6267 if (verbose) {
6268 prefix = accel_uses_host_cpuid()
6269 ? "host doesn't support requested feature"
6270 : "TCG doesn't support requested feature";
6271 }
b8d834a0
EH		 6272
6273 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6274 uint64_t host_feat =
b8d834a0 6275 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6276 uint64_t requested_features = env->features[w];
6277 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6278 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6279 }
6280
e37a5c7f
CP		 6281 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6282 kvm_enabled()) {
6283 KVMState *s = CPU(cpu)->kvm_state;
6284 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6285 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6286 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6287 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6288 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6289
6290 if (!eax_0 ||
6291 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6292 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6293 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6294 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6295 INTEL_PT_ADDR_RANGES_NUM) ||
6296 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 6297 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 6298 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6299 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 6300 /*
6301 * Processor Trace capabilities aren't configurable, so if the
6302 * host can't emulate the capabilities we report on
6303 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6304 */
245edd0c 6305 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6306 }
6307 }
b8d834a0
EH		 6308}
6309
08856771
VK		 6310static void x86_cpu_hyperv_realize(X86CPU *cpu)
6311{
6312 size_t len;
6313
6314 /* Hyper-V vendor id */
6315 if (!cpu->hyperv_vendor) {
4519259a
VK		 6316 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
6317 &error_abort);
6318 }
6319 len = strlen(cpu->hyperv_vendor);
6320 if (len > 12) {
6321 warn_report("hv-vendor-id truncated to 12 characters");
6322 len = 12;
08856771 6323 }
4519259a
VK		 6324 memset(cpu->hyperv_vendor_id, 0, 12);
6325 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 6326
6327 /* 'Hv#1' interface identification*/
6328 cpu->hyperv_interface_id[0] = 0x31237648;
6329 cpu->hyperv_interface_id[1] = 0;
6330 cpu->hyperv_interface_id[2] = 0;
6331 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 6332
23eb5d03
VK		 6333 /* Hypervisor implementation limits */
6334 cpu->hyperv_limits[0] = 64;
6335 cpu->hyperv_limits[1] = 0;
6336 cpu->hyperv_limits[2] = 0;
08856771
VK		 6337}
6338
41f3d4d6
EH		 6339static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6340{
6341 CPUState *cs = CPU(dev);
6342 X86CPU *cpu = X86_CPU(dev);
6343 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6344 CPUX86State *env = &cpu->env;
6345 Error *local_err = NULL;
6346 static bool ht_warned;
f06d8a18 6347 unsigned requested_lbr_fmt;
41f3d4d6 6348
41f3d4d6
EH		 6349 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6350 error_setg(errp, "apic-id property was not initialized properly");
6351 return;
6352 }
6353
662175b9
CF		 6354 /*
6355 * Process Hyper-V enlightenments.
6356 * Note: this currently has to happen before the expansion of CPU features.
6357 */
6358 x86_cpu_hyperv_realize(cpu);
6359
b8d834a0 6360 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6361 if (local_err) {
6362 goto out;
6363 }
6364
f06d8a18
YW		 6365 /*
6366 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
6367 * with user-provided setting.
6368 */
6369 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) {
6370 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) {
6371 error_setg(errp, "invalid lbr-fmt");
6372 return;
6373 }
6374 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT;
6375 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt;
6376 }
6377
6378 /*
6379 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
6380 * 3)vPMU LBR format matches that of host setting.
6381 */
6382 requested_lbr_fmt =
6383 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT;
6384 if (requested_lbr_fmt && kvm_enabled()) {
6385 uint64_t host_perf_cap =
6386 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false);
6387 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT;
6388
6389 if (!cpu->enable_pmu) {
6390 error_setg(errp, "vPMU: LBR is unsupported without pmu=on");
6391 return;
6392 }
6393 if (requested_lbr_fmt != host_lbr_fmt) {
6394 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match "
6395 "the host value (0x%x).",
6396 requested_lbr_fmt, host_lbr_fmt);
6397 return;
6398 }
6399 }
6400
245edd0c
PB		 6401 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6402
6403 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6404 error_setg(&local_err,
6405 accel_uses_host_cpuid() ?
6406 "Host doesn't support requested features" :
6407 "TCG doesn't support requested features");
6408 goto out;
9997cf7b
EH		 6409 }
6410
9b15cd9e
IM		 6411 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6412 * CPUID[1].EDX.
6413 */
e48638fd 6414 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6415 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6416 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6417 & CPUID_EXT2_AMD_ALIASES);
6418 }
6419
db888065
SC		 6420 x86_cpu_set_sgxlepubkeyhash(env);
6421
662175b9
CF		 6422 /*
6423 * note: the call to the framework needs to happen after feature expansion,
6424 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
6425 * These may be set by the accel-specific code,
6426 * and the results are subsequently checked / assumed in this function.
6427 */
6428 cpu_exec_realizefn(cs, &local_err);
6429 if (local_err != NULL) {
6430 error_propagate(errp, local_err);
6431 return;
6432 }
6433
6434 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6435 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6436 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6437 goto out;
6438 }
6439
6440 if (cpu->ucode_rev == 0) {
6441 /*
6442 * The default is the same as KVM's. Note that this check
6443 * needs to happen after the evenual setting of ucode_rev in
6444 * accel-specific code in cpu_exec_realizefn.
6445 */
6446 if (IS_AMD_CPU(env)) {
6447 cpu->ucode_rev = 0x01000065;
6448 } else {
6449 cpu->ucode_rev = 0x100000000ULL;
6450 }
6451 }
6452
6453 /*
6454 * mwait extended info: needed for Core compatibility
6455 * We always wake on interrupt even if host does not have the capability.
6456 *
6457 * requires the accel-specific code in cpu_exec_realizefn to
6458 * have already acquired the CPUID data into cpu->mwait.
6459 */
6460 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6461
11f6fee5
DDAG		 6462 /* For 64bit systems think about the number of physical bits to present.
6463 * ideally this should be the same as the host; anything other than matching
6464 * the host can cause incorrect guest behaviour.
6465 * QEMU used to pick the magic value of 40 bits that corresponds to
6466 * consumer AMD devices but nothing else.
662175b9
CF		 6467 *
6468 * Note that this code assumes features expansion has already been done
6469 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
6470 * phys_bits adjustments to match the host have been already done in
6471 * accel-specific code in cpu_exec_realizefn.
11f6fee5 6472 */
af45907a 6473 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 6474 if (cpu->phys_bits &&
6475 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6476 cpu->phys_bits < 32)) {
6477 error_setg(errp, "phys-bits should be between 32 and %u "
6478 " (but is %u)",
6479 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6480 return;
af45907a 6481 }
f5cc5a5c
CF		 6482 /*
6483 * 0 means it was not explicitly set by the user (or by machine
6484 * compat_props or by the host code in host-cpu.c).
6485 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 6486 */
6487 if (cpu->phys_bits == 0) {
6488 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6489 }
af45907a
DDAG		 6490 } else {
6491 /* For 32 bit systems don't use the user set value, but keep
6492 * phys_bits consistent with what we tell the guest.
6493 */
6494 if (cpu->phys_bits != 0) {
6495 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6496 return;
6497 }
fefb41bf 6498
af45907a
DDAG		 6499 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6500 cpu->phys_bits = 36;
6501 } else {
6502 cpu->phys_bits = 32;
6503 }
6504 }
a9f27ea9
EH		 6505
6506 /* Cache information initialization */
6507 if (!cpu->legacy_cache) {
dcafd1ef 6508 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6509 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6510 error_setg(errp,
6511 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6512 return;
6513 }
6514 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6515 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6516 } else {
6517 /* Build legacy cache information */
6518 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6519 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6520 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6521 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6522
6523 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6524 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6525 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6526 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6527
6528 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6529 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6530 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6531 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6532 }
6533
65dee380 6534#ifndef CONFIG_USER_ONLY
0e11fc69 6535 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6536 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6537
0e11fc69 6538 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6539 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6540 if (local_err != NULL) {
4dc1f449 6541 goto out;
bdeec802
IM		 6542 }
6543 }
65dee380
IM		 6544#endif
6545
7a059953 6546 mce_init(cpu);
2001d0cd 6547
14a10fc3 6548 qemu_init_vcpu(cs);
d3c64d6a 6549
6b2942f9
BM		 6550 /*
6551 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6552 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6553 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6554 * users a warning.
6555 *
6556 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6557 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6558 */
0765691e
MA		 6559 if (IS_AMD_CPU(env) &&
6560 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6561 cs->nr_threads > 1 && !ht_warned) {
6562 warn_report("This family of AMD CPU doesn't support "
6563 "hyperthreading(%d)",
6564 cs->nr_threads);
6565 error_printf("Please configure -smp options properly"
6566 " or try enabling topoext feature.\n");
6567 ht_warned = true;
e48638fd
WH		 6568 }
6569
79f1a68a 6570#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 6571 x86_cpu_apic_realize(cpu, &local_err);
6572 if (local_err != NULL) {
6573 goto out;
6574 }
79f1a68a 6575#endif /* !CONFIG_USER_ONLY */
14a10fc3 6576 cpu_reset(cs);
2b6f294c 6577
4dc1f449 6578 xcc->parent_realize(dev, &local_err);
2001d0cd 6579
4dc1f449
IM		 6580out:
6581 if (local_err != NULL) {
6582 error_propagate(errp, local_err);
6583 return;
6584 }
7a059953
AF		 6585}
6586
b69c3c21 6587static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 6588{
6589 X86CPU *cpu = X86_CPU(dev);
7bbc124e 6590 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 6591
6592#ifndef CONFIG_USER_ONLY
6593 cpu_remove_sync(CPU(dev));
6594 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6595#endif
6596
6597 if (cpu->apic_state) {
6598 object_unparent(OBJECT(cpu->apic_state));
6599 cpu->apic_state = NULL;
6600 }
7bbc124e 6601
b69c3c21 6602 xcc->parent_unrealize(dev);
c884776e
IM		 6603}
6604
38e5c119 6605typedef struct BitProperty {
a7b0ffac 6606 FeatureWord w;
ede146c2 6607 uint64_t mask;
38e5c119
EH		 6608} BitProperty;
6609
d7bce999
EB		 6610static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6611 void *opaque, Error **errp)
38e5c119 6612{
a7b0ffac 6613 X86CPU *cpu = X86_CPU(obj);
38e5c119 6614 BitProperty *fp = opaque;
ede146c2 6615 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6616 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6617 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6618}
6619
d7bce999
EB		 6620static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6621 void *opaque, Error **errp)
38e5c119
EH		 6622{
6623 DeviceState *dev = DEVICE(obj);
a7b0ffac 6624 X86CPU *cpu = X86_CPU(obj);
38e5c119 6625 BitProperty *fp = opaque;
38e5c119
EH		 6626 bool value;
6627
6628 if (dev->realized) {
6629 qdev_prop_set_after_realize(dev, name, errp);
6630 return;
6631 }
6632
668f62ec 6633 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 6634 return;
6635 }
6636
6637 if (value) {
a7b0ffac 6638 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6639 } else {
a7b0ffac 6640 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6641 }
d4a606b3 6642 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6643}
6644
38e5c119
EH		 6645/* Register a boolean property to get/set a single bit in a uint32_t field.
6646 *
6647 * The same property name can be registered multiple times to make it affect
6648 * multiple bits in the same FeatureWord. In that case, the getter will return
6649 * true only if all bits are set.
6650 */
f5730c69 6651static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 6652 const char *prop_name,
a7b0ffac 6653 FeatureWord w,
38e5c119
EH		 6654 int bitnr)
6655{
f5730c69 6656 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 6657 BitProperty *fp;
6658 ObjectProperty *op;
ede146c2 6659 uint64_t mask = (1ULL << bitnr);
38e5c119 6660
f5730c69 6661 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 6662 if (op) {
6663 fp = op->opaque;
a7b0ffac 6664 assert(fp->w == w);
38e5c119
EH		 6665 fp->mask |= mask;
6666 } else {
6667 fp = g_new0(BitProperty, 1);
a7b0ffac 6668 fp->w = w;
38e5c119 6669 fp->mask = mask;
f5730c69
EH		 6670 object_class_property_add(oc, prop_name, "bool",
6671 x86_cpu_get_bit_prop,
6672 x86_cpu_set_bit_prop,
6673 NULL, fp);
38e5c119
EH		 6674 }
6675}
6676
f5730c69 6677static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 6678 FeatureWord w,
6679 int bitnr)
6680{
38e5c119 6681 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6682 const char *name = fi->feat_names[bitnr];
38e5c119 6683
16d2fcaa 6684 if (!name) {
38e5c119
EH		 6685 return;
6686 }
6687
fc7dfd20
EH		 6688 /* Property names should use "-" instead of "_".
6689 * Old names containing underscores are registered as aliases
6690 * using object_property_add_alias()
6691 */
16d2fcaa
EH		 6692 assert(!strchr(name, '_'));
6693 /* aliases don't use "|" delimiters anymore, they are registered
6694 * manually using object_property_add_alias() */
6695 assert(!strchr(name, '|'));
f5730c69 6696 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 6697}
6698
4db4385a
CF		 6699static void x86_cpu_post_initfn(Object *obj)
6700{
6701 accel_cpu_instance_init(CPU(obj));
6702}
6703
de024815
AF		 6704static void x86_cpu_initfn(Object *obj)
6705{
6706 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6707 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 6708 CPUX86State *env = &cpu->env;
6709
c26ae610 6710 env->nr_dies = 1;
7506ed90 6711 cpu_set_cpustate_pointers(cpu);
71ad61d3 6712
8e8aba50
EH		 6713 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6714 x86_cpu_get_feature_words,
d2623129 6715 NULL, NULL, (void *)env->features);
7e5292b5
EH		 6716 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6717 x86_cpu_get_feature_words,
d2623129 6718 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 6719
d2623129
MA		 6720 object_property_add_alias(obj, "sse3", obj, "pni");
6721 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6722 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6723 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6724 object_property_add_alias(obj, "xd", obj, "nx");
6725 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6726 object_property_add_alias(obj, "i64", obj, "lm");
6727
6728 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6729 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6730 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6731 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6732 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6733 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6734 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6735 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6736 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6737 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6738 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 6739 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 6740 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6741 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6742 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6743 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6744 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6745 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6746 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6747 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6748 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6749 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6750 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 6751
e1f9a8e8 6752 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
f06d8a18
YW		 6753 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;
6754 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt");
e1f9a8e8 6755
dcafd1ef 6756 if (xcc->model) {
49e2fa85 6757 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 6758 }
de024815
AF		 6759}
6760
997395d3
IM		 6761static int64_t x86_cpu_get_arch_id(CPUState *cs)
6762{
6763 X86CPU *cpu = X86_CPU(cs);
997395d3 6764
7e72a45c 6765 return cpu->apic_id;
997395d3
IM		 6766}
6767
6bc0d6a0 6768#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 6769static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6770{
6771 X86CPU *cpu = X86_CPU(cs);
6772
6773 return cpu->env.cr[0] & CR0_PG_MASK;
6774}
6bc0d6a0 6775#endif /* !CONFIG_USER_ONLY */
444d5590 6776
f45748f1
AF		 6777static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6778{
6779 X86CPU *cpu = X86_CPU(cs);
6780
6781 cpu->env.eip = value;
6782}
6783
92d5f1a4 6784int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6785{
6786 X86CPU *cpu = X86_CPU(cs);
6787 CPUX86State *env = &cpu->env;
6788
92d5f1a4
PB		 6789#if !defined(CONFIG_USER_ONLY)
6790 if (interrupt_request & CPU_INTERRUPT_POLL) {
6791 return CPU_INTERRUPT_POLL;
6792 }
6793#endif
6794 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6795 return CPU_INTERRUPT_SIPI;
6796 }
6797
6798 if (env->hflags2 & HF2_GIF_MASK) {
6799 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6800 !(env->hflags & HF_SMM_MASK)) {
6801 return CPU_INTERRUPT_SMI;
6802 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6803 !(env->hflags2 & HF2_NMI_MASK)) {
6804 return CPU_INTERRUPT_NMI;
6805 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6806 return CPU_INTERRUPT_MCE;
6807 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6808 (((env->hflags2 & HF2_VINTR_MASK) &&
6809 (env->hflags2 & HF2_HIF_MASK)) ||
6810 (!(env->hflags2 & HF2_VINTR_MASK) &&
6811 (env->eflags & IF_MASK &&
6812 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6813 return CPU_INTERRUPT_HARD;
6814#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 6815 } else if (env->hflags2 & HF2_VGIF_MASK) {
6816 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 6817 (env->eflags & IF_MASK) &&
6818 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 6819 return CPU_INTERRUPT_VIRQ;
6820 }
92d5f1a4
PB		 6821#endif
6822 }
6823 }
6824
6825 return 0;
6826}
6827
6828static bool x86_cpu_has_work(CPUState *cs)
6829{
6830 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 6831}
6832
f50f3dd5
RH		 6833static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6834{
6835 X86CPU *cpu = X86_CPU(cs);
6836 CPUX86State *env = &cpu->env;
6837
6838 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6839 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6840 : bfd_mach_i386_i8086);
b666d2a4
RH		 6841
6842 info->cap_arch = CS_ARCH_X86;
6843 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6844 : env->hflags & HF_CS32_MASK ? CS_MODE_32
6845 : CS_MODE_16);
15fa1a0a
RH		 6846 info->cap_insn_unit = 1;
6847 info->cap_insn_split = 8;
f50f3dd5
RH		 6848}
6849
35b1b927
TW		 6850void x86_update_hflags(CPUX86State *env)
6851{
6852 uint32_t hflags;
6853#define HFLAG_COPY_MASK \
6854 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6855 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6856 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6857 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6858
6859 hflags = env->hflags & HFLAG_COPY_MASK;
6860 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6861 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6862 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6863 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6864 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6865
6866 if (env->cr[4] & CR4_OSFXSR_MASK) {
6867 hflags |= HF_OSFXSR_MASK;
6868 }
6869
6870 if (env->efer & MSR_EFER_LMA) {
6871 hflags |= HF_LMA_MASK;
6872 }
6873
6874 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6875 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6876 } else {
6877 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6878 (DESC_B_SHIFT - HF_CS32_SHIFT);
6879 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6880 (DESC_B_SHIFT - HF_SS32_SHIFT);
6881 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6882 !(hflags & HF_CS32_MASK)) {
6883 hflags |= HF_ADDSEG_MASK;
6884 } else {
6885 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6886 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6887 }
6888 }
6889 env->hflags = hflags;
6890}
6891
9337e3b6 6892static Property x86_cpu_properties[] = {
2da00e31
IM		 6893#ifdef CONFIG_USER_ONLY
6894 /* apic_id = 0 by default for *-user, see commit 9886e834 */
6895 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 6896 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6897 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 6898 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 6899 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 6900#else
6901 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 6902 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6903 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 6904 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 6905 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 6906#endif
15f8b142 6907 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 6908 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
f06d8a18 6909 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
2d384d7c 6910
915aee93 6911 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 6912 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 6913 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
6914 HYPERV_FEAT_RELAXED, 0),
6915 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
6916 HYPERV_FEAT_VAPIC, 0),
6917 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
6918 HYPERV_FEAT_TIME, 0),
6919 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
6920 HYPERV_FEAT_CRASH, 0),
6921 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
6922 HYPERV_FEAT_RESET, 0),
6923 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
6924 HYPERV_FEAT_VPINDEX, 0),
6925 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
6926 HYPERV_FEAT_RUNTIME, 0),
6927 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
6928 HYPERV_FEAT_SYNIC, 0),
6929 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
6930 HYPERV_FEAT_STIMER, 0),
6931 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
6932 HYPERV_FEAT_FREQUENCIES, 0),
6933 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
6934 HYPERV_FEAT_REENLIGHTENMENT, 0),
6935 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
6936 HYPERV_FEAT_TLBFLUSH, 0),
6937 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
6938 HYPERV_FEAT_EVMCS, 0),
6939 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
6940 HYPERV_FEAT_IPI, 0),
128531d9
VK		 6941 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
6942 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 6943 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
6944 HYPERV_FEAT_AVIC, 0),
30d6ff66
VK		 6945 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
6946 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
73d24074
JD		 6947 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
6948 HYPERV_FEAT_SYNDBG, 0),
e48ddcc6 6949 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 6950 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 6951
af7228b8
VK		 6952 /* WS2008R2 identify by default */
6953 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 6954 0x3839),
af7228b8 6955 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 6956 0x000A),
af7228b8 6957 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 6958 0x0000),
af7228b8
VK		 6959 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
6960 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
6961 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
6962
15e41345 6963 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 6964 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 6965 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 6966 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 6967 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 6968 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 6969 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 6970 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 6971 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
6972 UINT32_MAX),
c39c0edf
EH		 6973 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
6974 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
6975 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
6976 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
6977 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
6978 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 6979 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 6980 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 6981 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 6982 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 6983 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 6984 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 6985 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 6986 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
6987 false),
988f7b8b
VK		 6988 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
6989 false),
0b564e6f 6990 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 6991 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 6992 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
6993 true),
ab8f992e 6994 /*
a9f27ea9
EH		 6995 * lecacy_cache defaults to true unless the CPU model provides its
6996 * own cache information (see x86_cpu_load_def()).
ab8f992e 6997 */
a9f27ea9 6998 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 6999
7000 /*
7001 * From "Requirements for Implementing the Microsoft
7002 * Hypervisor Interface":
7003 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7004 *
7005 * "Starting with Windows Server 2012 and Windows 8, if
7006 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7007 * the hypervisor imposes no specific limit to the number of VPs.
7008 * In this case, Windows Server 2012 guest VMs may use more than
7009 * 64 VPs, up to the maximum supported number of processors applicable
7010 * to the specific Windows version being used."
7011 */
7012 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 7013 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7014 false),
f24c3a79
LK		 7015 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7016 true),
9337e3b6
EH		 7017 DEFINE_PROP_END_OF_LIST()
7018};
7019
8b80bd28
PMD		 7020#ifndef CONFIG_USER_ONLY
7021#include "hw/core/sysemu-cpu-ops.h"
7022
7023static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 7024 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 7025 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 7026 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 7027 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 7028 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 7029 .write_elf32_note = x86_cpu_write_elf32_note,
7030 .write_elf64_note = x86_cpu_write_elf64_note,
7031 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
7032 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 7033 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 7034};
7035#endif
7036
5fd2087a
AF		 7037static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7038{
7039 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7040 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 7041 DeviceClass *dc = DEVICE_CLASS(oc);
f5730c69 7042 FeatureWord w;
2b6f294c 7043
bf853881
PMD		 7044 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7045 &xcc->parent_realize);
7046 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7047 &xcc->parent_unrealize);
4f67d30b 7048 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 7049
781c67ca 7050 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 7051 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 7052
500050d1 7053 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 7054 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 7055 cc->has_work = x86_cpu_has_work;
878096ee 7056 cc->dump_state = x86_cpu_dump_state;
f45748f1 7057 cc->set_pc = x86_cpu_set_pc;
5b50e790
AF		 7058 cc->gdb_read_register = x86_cpu_gdb_read_register;
7059 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 7060 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 7061
5d004421 7062#ifndef CONFIG_USER_ONLY
8b80bd28 7063 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 7064#endif /* !CONFIG_USER_ONLY */
7065
00fcd100
AB		 7066 cc->gdb_arch_name = x86_gdb_arch_name;
7067#ifdef TARGET_X86_64
b8158192 7068 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 7069 cc->gdb_num_core_regs = 66;
00fcd100 7070#else
b8158192 7071 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 7072 cc->gdb_num_core_regs = 50;
74d7fc7f 7073#endif
f50f3dd5 7074 cc->disas_set_info = x86_disas_set_info;
4c315c27 7075
e90f2a8c 7076 dc->user_creatable = true;
3e0dceaf
EH		 7077
7078 object_class_property_add(oc, "family", "int",
7079 x86_cpuid_version_get_family,
7080 x86_cpuid_version_set_family, NULL, NULL);
7081 object_class_property_add(oc, "model", "int",
7082 x86_cpuid_version_get_model,
7083 x86_cpuid_version_set_model, NULL, NULL);
7084 object_class_property_add(oc, "stepping", "int",
7085 x86_cpuid_version_get_stepping,
7086 x86_cpuid_version_set_stepping, NULL, NULL);
7087 object_class_property_add_str(oc, "vendor",
7088 x86_cpuid_get_vendor,
7089 x86_cpuid_set_vendor);
7090 object_class_property_add_str(oc, "model-id",
7091 x86_cpuid_get_model_id,
7092 x86_cpuid_set_model_id);
7093 object_class_property_add(oc, "tsc-frequency", "int",
7094 x86_cpuid_get_tsc_freq,
7095 x86_cpuid_set_tsc_freq, NULL, NULL);
7096 /*
7097 * The "unavailable-features" property has the same semantics as
7098 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7099 * QMP command: they list the features that would have prevented the
7100 * CPU from running if the "enforce" flag was set.
7101 */
7102 object_class_property_add(oc, "unavailable-features", "strList",
7103 x86_cpu_get_unavailable_features,
7104 NULL, NULL, NULL);
7105
7106#if !defined(CONFIG_USER_ONLY)
7107 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7108 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7109#endif
7110
f5730c69
EH		 7111 for (w = 0; w < FEATURE_WORDS; w++) {
7112 int bitnr;
7113 for (bitnr = 0; bitnr < 64; bitnr++) {
7114 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
7115 }
7116 }
5fd2087a
AF		 7117}
7118
7119static const TypeInfo x86_cpu_type_info = {
7120 .name = TYPE_X86_CPU,
7121 .parent = TYPE_CPU,
7122 .instance_size = sizeof(X86CPU),
de024815 7123 .instance_init = x86_cpu_initfn,
4db4385a
CF		 7124 .instance_post_init = x86_cpu_post_initfn,
7125
d940ee9b 7126 .abstract = true,
5fd2087a
AF		 7127 .class_size = sizeof(X86CPUClass),
7128 .class_init = x86_cpu_common_class_init,
7129};
7130
5adbed30
EH		 7131/* "base" CPU model, used by query-cpu-model-expansion */
7132static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7133{
7134 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7135
7136 xcc->static_model = true;
7137 xcc->migration_safe = true;
7138 xcc->model_description = "base CPU model type with no features enabled";
7139 xcc->ordering = 8;
7140}
7141
7142static const TypeInfo x86_base_cpu_type_info = {
7143 .name = X86_CPU_TYPE_NAME("base"),
7144 .parent = TYPE_X86_CPU,
7145 .class_init = x86_cpu_base_class_init,
7146};
7147
5fd2087a
AF		 7148static void x86_cpu_register_types(void)
7149{
d940ee9b
EH		 7150 int i;
7151
5fd2087a 7152 type_register_static(&x86_cpu_type_info);
d940ee9b 7153 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7154 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7155 }
c62f2630 7156 type_register_static(&max_x86_cpu_type_info);
5adbed30 7157 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 7158}
7159
7160type_init(x86_cpu_register_types)
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