]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/cpu.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
gdbstub: Infer number of core registers from XML
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63 1/*
79f1a68a 2 * i386 CPUID, CPU class, definitions, models
c6dc6f63
AP		 3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
d9ff33ad 9 * version 2.1 of the License, or (at your option) any later version.
c6dc6f63
AP		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
0442428a 23#include "qemu/qemu-print.h"
15e09912 24#include "qemu/hw-version.h"
c6dc6f63 25#include "cpu.h"
ed69e831 26#include "tcg/helper-tcg.h"
d6dcc558 27#include "sysemu/hvf.h"
044431cf 28#include "hvf/hvf-i386.h"
a9dc68d9 29#include "kvm/kvm_i386.h"
93777de3 30#include "sev.h"
f83aeeae 31#include "qapi/error.h"
cc37d98b 32#include "qemu/error-report.h"
8ac25c84 33#include "qapi/qapi-visit-machine.h"
7b1b5d19 34#include "qapi/qmp/qerror.h"
1814eab6 35#include "standard-headers/asm-x86/kvm_para.h"
53a89e26 36#include "hw/qdev-properties.h"
5232d00a 37#include "hw/i386/topology.h"
bdeec802 38#ifndef CONFIG_USER_ONLY
c0f6cd9f 39#include "sysemu/reset.h"
390dbc6e 40#include "qapi/qapi-commands-machine-target.h"
2001d0cd 41#include "exec/address-spaces.h"
0e11fc69 42#include "hw/boards.h"
1dec2e1f 43#include "hw/i386/sgx-epc.h"
bdeec802
IM		 44#endif
45
b666d2a4 46#include "disas/capstone.h"
79f1a68a 47#include "cpu-internal.h"
b666d2a4 48
123fa102
TH		 49static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
50
7e3482f8
EH		 51/* Helpers for building CPUID[2] descriptors: */
52
53struct CPUID2CacheDescriptorInfo {
54 enum CacheType type;
55 int level;
56 int size;
57 int line_size;
58 int associativity;
59};
5e891bf8 60
7e3482f8
EH		 61/*
62 * Known CPUID 2 cache descriptors.
63 * From Intel SDM Volume 2A, CPUID instruction
64 */
65struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 67 .associativity = 4, .line_size = 32, },
5f00335a 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 69 .associativity = 4, .line_size = 32, },
5f00335a 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 71 .associativity = 4, .line_size = 64, },
5f00335a 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 73 .associativity = 2, .line_size = 32, },
5f00335a 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 75 .associativity = 4, .line_size = 32, },
5f00335a 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 77 .associativity = 4, .line_size = 64, },
5f00335a 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 79 .associativity = 6, .line_size = 64, },
5f00335a 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 81 .associativity = 2, .line_size = 64, },
5f00335a 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 83 .associativity = 8, .line_size = 64, },
84 /* lines per sector is not supported cpuid2_cache_descriptor(),
85 * so descriptors 0x22, 0x23 are not included
86 */
5f00335a 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 88 .associativity = 16, .line_size = 64, },
89 /* lines per sector is not supported cpuid2_cache_descriptor(),
90 * so descriptors 0x25, 0x20 are not included
91 */
5f00335a 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 93 .associativity = 8, .line_size = 64, },
5f00335a 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 95 .associativity = 8, .line_size = 64, },
5f00335a 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 97 .associativity = 4, .line_size = 32, },
5f00335a 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 99 .associativity = 4, .line_size = 32, },
5f00335a 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 101 .associativity = 4, .line_size = 32, },
5f00335a 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 103 .associativity = 4, .line_size = 32, },
5f00335a 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 105 .associativity = 4, .line_size = 32, },
5f00335a 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 107 .associativity = 4, .line_size = 64, },
5f00335a 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 109 .associativity = 8, .line_size = 64, },
5f00335a 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 111 .associativity = 12, .line_size = 64, },
112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 114 .associativity = 12, .line_size = 64, },
5f00335a 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 116 .associativity = 16, .line_size = 64, },
5f00335a 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 118 .associativity = 12, .line_size = 64, },
5f00335a 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 120 .associativity = 16, .line_size = 64, },
5f00335a 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 122 .associativity = 24, .line_size = 64, },
5f00335a 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 124 .associativity = 8, .line_size = 64, },
5f00335a 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 126 .associativity = 4, .line_size = 64, },
5f00335a 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 128 .associativity = 4, .line_size = 64, },
5f00335a 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 130 .associativity = 4, .line_size = 64, },
5f00335a 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 132 .associativity = 4, .line_size = 64, },
133 /* lines per sector is not supported cpuid2_cache_descriptor(),
134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
135 */
5f00335a 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 139 .associativity = 2, .line_size = 64, },
5f00335a 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 141 .associativity = 8, .line_size = 64, },
5f00335a 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 143 .associativity = 8, .line_size = 32, },
5f00335a 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 145 .associativity = 8, .line_size = 32, },
5f00335a 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 147 .associativity = 8, .line_size = 32, },
5f00335a 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 149 .associativity = 8, .line_size = 32, },
5f00335a 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 151 .associativity = 4, .line_size = 64, },
5f00335a 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 153 .associativity = 8, .line_size = 64, },
5f00335a 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 155 .associativity = 4, .line_size = 64, },
5f00335a 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 157 .associativity = 4, .line_size = 64, },
5f00335a 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 159 .associativity = 4, .line_size = 64, },
5f00335a 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 161 .associativity = 8, .line_size = 64, },
5f00335a 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 163 .associativity = 8, .line_size = 64, },
5f00335a 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 165 .associativity = 8, .line_size = 64, },
5f00335a 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 167 .associativity = 12, .line_size = 64, },
5f00335a 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 169 .associativity = 12, .line_size = 64, },
5f00335a 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 171 .associativity = 12, .line_size = 64, },
5f00335a 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 173 .associativity = 16, .line_size = 64, },
5f00335a 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 175 .associativity = 16, .line_size = 64, },
5f00335a 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 177 .associativity = 16, .line_size = 64, },
5f00335a 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 179 .associativity = 24, .line_size = 64, },
5f00335a 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 181 .associativity = 24, .line_size = 64, },
5f00335a 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 183 .associativity = 24, .line_size = 64, },
184};
185
186/*
187 * "CPUID leaf 2 does not report cache descriptor information,
188 * use CPUID leaf 4 to query cache parameters"
189 */
190#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 191
7e3482f8
EH		 192/*
193 * Return a CPUID 2 cache descriptor for a given cache.
194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
195 */
196static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
197{
198 int i;
199
200 assert(cache->size > 0);
201 assert(cache->level > 0);
202 assert(cache->line_size > 0);
203 assert(cache->associativity > 0);
204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
206 if (d->level == cache->level && d->type == cache->type &&
207 d->size == cache->size && d->line_size == cache->line_size &&
208 d->associativity == cache->associativity) {
209 return i;
210 }
211 }
5e891bf8 212
7e3482f8
EH		 213 return CACHE_DESCRIPTOR_UNAVAILABLE;
214}
5e891bf8
EH		 215
216/* CPUID Leaf 4 constants: */
217
218/* EAX: */
7e3482f8
EH		 219#define CACHE_TYPE_D 1
220#define CACHE_TYPE_I 2
221#define CACHE_TYPE_UNIFIED 3
5e891bf8 222
7e3482f8 223#define CACHE_LEVEL(l) (l << 5)
5e891bf8 224
7e3482f8 225#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 226
227/* EDX: */
7e3482f8
EH		 228#define CACHE_NO_INVD_SHARING (1 << 0)
229#define CACHE_INCLUSIVE (1 << 1)
230#define CACHE_COMPLEX_IDX (1 << 2)
231
232/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 233#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
236 0 /* Invalid value */)
7e3482f8
EH		 237
238
239/* Encode cache info for CPUID[4] */
240static void encode_cache_cpuid4(CPUCacheInfo *cache,
241 int num_apic_ids, int num_cores,
242 uint32_t *eax, uint32_t *ebx,
243 uint32_t *ecx, uint32_t *edx)
244{
245 assert(cache->size == cache->line_size * cache->associativity *
246 cache->partitions * cache->sets);
247
248 assert(num_apic_ids > 0);
249 *eax = CACHE_TYPE(cache->type) |
250 CACHE_LEVEL(cache->level) |
251 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
252 ((num_cores - 1) << 26) |
253 ((num_apic_ids - 1) << 14);
254
255 assert(cache->line_size > 0);
256 assert(cache->partitions > 0);
257 assert(cache->associativity > 0);
258 /* We don't implement fully-associative caches */
259 assert(cache->associativity < cache->sets);
260 *ebx = (cache->line_size - 1) |
261 ((cache->partitions - 1) << 12) |
262 ((cache->associativity - 1) << 22);
263
264 assert(cache->sets > 0);
265 *ecx = cache->sets - 1;
266
267 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
268 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
269 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
270}
271
272/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
273static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
274{
275 assert(cache->size % 1024 == 0);
276 assert(cache->lines_per_tag > 0);
277 assert(cache->associativity > 0);
278 assert(cache->line_size > 0);
279 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
280 (cache->lines_per_tag << 8) | (cache->line_size);
281}
5e891bf8
EH		 282
283#define ASSOC_FULL 0xFF
284
285/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
286#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
287 a == 2 ? 0x2 : \
288 a == 4 ? 0x4 : \
289 a == 8 ? 0x6 : \
290 a == 16 ? 0x8 : \
291 a == 32 ? 0xA : \
292 a == 48 ? 0xB : \
293 a == 64 ? 0xC : \
294 a == 96 ? 0xD : \
295 a == 128 ? 0xE : \
296 a == ASSOC_FULL ? 0xF : \
297 0 /* invalid value */)
298
7e3482f8
EH		 299/*
300 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
301 * @l3 can be NULL.
302 */
303static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
304 CPUCacheInfo *l3,
305 uint32_t *ecx, uint32_t *edx)
306{
307 assert(l2->size % 1024 == 0);
308 assert(l2->associativity > 0);
309 assert(l2->lines_per_tag > 0);
310 assert(l2->line_size > 0);
311 *ecx = ((l2->size / 1024) << 16) |
312 (AMD_ENC_ASSOC(l2->associativity) << 12) |
313 (l2->lines_per_tag << 8) | (l2->line_size);
314
315 if (l3) {
316 assert(l3->size % (512 * 1024) == 0);
317 assert(l3->associativity > 0);
318 assert(l3->lines_per_tag > 0);
319 assert(l3->line_size > 0);
320 *edx = ((l3->size / (512 * 1024)) << 18) |
321 (AMD_ENC_ASSOC(l3->associativity) << 12) |
322 (l3->lines_per_tag << 8) | (l3->line_size);
323 } else {
324 *edx = 0;
325 }
326}
5e891bf8 327
8f4202fb 328/* Encode cache info for CPUID[8000001D] */
2f084d1e
BM		 329static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
330 X86CPUTopoInfo *topo_info,
331 uint32_t *eax, uint32_t *ebx,
332 uint32_t *ecx, uint32_t *edx)
8f4202fb 333{
2f084d1e 334 uint32_t l3_threads;
8f4202fb
BM		 335 assert(cache->size == cache->line_size * cache->associativity *
336 cache->partitions * cache->sets);
337
338 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
339 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
340
341 /* L3 is shared among multiple cores */
342 if (cache->level == 3) {
2f084d1e
BM		 343 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
344 *eax |= (l3_threads - 1) << 14;
8f4202fb 345 } else {
2f084d1e 346 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 347 }
348
349 assert(cache->line_size > 0);
350 assert(cache->partitions > 0);
351 assert(cache->associativity > 0);
352 /* We don't implement fully-associative caches */
353 assert(cache->associativity < cache->sets);
354 *ebx = (cache->line_size - 1) |
355 ((cache->partitions - 1) << 12) |
356 ((cache->associativity - 1) << 22);
357
358 assert(cache->sets > 0);
359 *ecx = cache->sets - 1;
360
361 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
362 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
363 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
364}
365
ed78467a 366/* Encode cache info for CPUID[8000001E] */
31ada106
BM		 367static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
368 uint32_t *eax, uint32_t *ebx,
369 uint32_t *ecx, uint32_t *edx)
ed78467a 370{
31ada106
BM		 371 X86CPUTopoIDs topo_ids;
372
373 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
ed78467a 374
ed78467a 375 *eax = cpu->apic_id;
31ada106 376
ed78467a 377 /*
31ada106
BM		 378 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
379 * Read-only. Reset: 0000_XXXXh.
380 * See Core::X86::Cpuid::ExtApicId.
381 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
382 * Bits Description
383 * 31:16 Reserved.
384 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
385 * The number of threads per core is ThreadsPerCore+1.
386 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
387 *
388 * NOTE: CoreId is already part of apic_id. Just use it. We can
389 * use all the 8 bits to represent the core_id here.
ed78467a 390 */
31ada106
BM		 391 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
392
ed78467a 393 /*
31ada106
BM		 394 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
395 * Read-only. Reset: 0000_0XXXh.
396 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
397 * Bits Description
398 * 31:11 Reserved.
399 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
400 * ValidValues:
401 * Value Description
402 * 000b 1 node per processor.
403 * 001b 2 nodes per processor.
404 * 010b Reserved.
405 * 011b 4 nodes per processor.
406 * 111b-100b Reserved.
407 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
408 *
409 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
410 * But users can create more nodes than the actual hardware can
411 * support. To genaralize we can use all the upper 8 bits for nodes.
412 * NodeId is combination of node and socket_id which is already decoded
413 * in apic_id. Just use it by shifting.
ed78467a 414 */
31ada106
BM		 415 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
416 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
417
ed78467a
BM		 418 *edx = 0;
419}
420
ab8f992e
BM		 421/*
422 * Definitions of the hardcoded cache entries we expose:
423 * These are legacy cache values. If there is a need to change any
424 * of these values please use builtin_x86_defs
425 */
5e891bf8
EH		 426
427/* L1 data cache: */
ab8f992e 428static CPUCacheInfo legacy_l1d_cache = {
5f00335a 429 .type = DATA_CACHE,
7e3482f8
EH		 430 .level = 1,
431 .size = 32 * KiB,
432 .self_init = 1,
433 .line_size = 64,
434 .associativity = 8,
435 .sets = 64,
436 .partitions = 1,
437 .no_invd_sharing = true,
438};
439
5e891bf8 440/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 441static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 442 .type = DATA_CACHE,
7e3482f8
EH		 443 .level = 1,
444 .size = 64 * KiB,
445 .self_init = 1,
446 .line_size = 64,
447 .associativity = 2,
448 .sets = 512,
449 .partitions = 1,
450 .lines_per_tag = 1,
451 .no_invd_sharing = true,
452};
5e891bf8
EH		 453
454/* L1 instruction cache: */
ab8f992e 455static CPUCacheInfo legacy_l1i_cache = {
5f00335a 456 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 457 .level = 1,
458 .size = 32 * KiB,
459 .self_init = 1,
460 .line_size = 64,
461 .associativity = 8,
462 .sets = 64,
463 .partitions = 1,
464 .no_invd_sharing = true,
465};
466
5e891bf8 467/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 468static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 469 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 470 .level = 1,
471 .size = 64 * KiB,
472 .self_init = 1,
473 .line_size = 64,
474 .associativity = 2,
475 .sets = 512,
476 .partitions = 1,
477 .lines_per_tag = 1,
478 .no_invd_sharing = true,
479};
5e891bf8
EH		 480
481/* Level 2 unified cache: */
ab8f992e 482static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 483 .type = UNIFIED_CACHE,
484 .level = 2,
485 .size = 4 * MiB,
486 .self_init = 1,
487 .line_size = 64,
488 .associativity = 16,
489 .sets = 4096,
490 .partitions = 1,
491 .no_invd_sharing = true,
492};
493
5e891bf8 494/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 495static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 496 .type = UNIFIED_CACHE,
497 .level = 2,
498 .size = 2 * MiB,
499 .line_size = 64,
500 .associativity = 8,
501};
502
503
5e891bf8 504/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 505static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 506 .type = UNIFIED_CACHE,
507 .level = 2,
508 .size = 512 * KiB,
509 .line_size = 64,
510 .lines_per_tag = 1,
511 .associativity = 16,
512 .sets = 512,
513 .partitions = 1,
514};
5e891bf8 515
14c985cf 516/* Level 3 unified cache: */
ab8f992e 517static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 518 .type = UNIFIED_CACHE,
519 .level = 3,
520 .size = 16 * MiB,
521 .line_size = 64,
522 .associativity = 16,
523 .sets = 16384,
524 .partitions = 1,
525 .lines_per_tag = 1,
526 .self_init = true,
527 .inclusive = true,
528 .complex_indexing = true,
529};
5e891bf8
EH		 530
531/* TLB definitions: */
532
533#define L1_DTLB_2M_ASSOC 1
534#define L1_DTLB_2M_ENTRIES 255
535#define L1_DTLB_4K_ASSOC 1
536#define L1_DTLB_4K_ENTRIES 255
537
538#define L1_ITLB_2M_ASSOC 1
539#define L1_ITLB_2M_ENTRIES 255
540#define L1_ITLB_4K_ASSOC 1
541#define L1_ITLB_4K_ENTRIES 255
542
543#define L2_DTLB_2M_ASSOC 0 /* disabled */
544#define L2_DTLB_2M_ENTRIES 0 /* disabled */
545#define L2_DTLB_4K_ASSOC 4
546#define L2_DTLB_4K_ENTRIES 512
547
548#define L2_ITLB_2M_ASSOC 0 /* disabled */
549#define L2_ITLB_2M_ENTRIES 0 /* disabled */
550#define L2_ITLB_4K_ASSOC 4
551#define L2_ITLB_4K_ENTRIES 512
552
e37a5c7f
CP		 553/* CPUID Leaf 0x14 constants: */
554#define INTEL_PT_MAX_SUBLEAF 0x1
555/*
556 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
557 * MSR can be accessed;
558 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
559 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
560 * of Intel PT MSRs across warm reset;
561 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
562 */
563#define INTEL_PT_MINIMAL_EBX 0xf
564/*
565 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
566 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
567 * accessed;
568 * bit[01]: ToPA tables can hold any number of output entries, up to the
569 * maximum allowed by the MaskOrTableOffset field of
570 * IA32_RTIT_OUTPUT_MASK_PTRS;
571 * bit[02]: Support Single-Range Output scheme;
572 */
573#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 574/* generated packets which contain IP payloads have LIP values */
575#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 576#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
577#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
578#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
579#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
580#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 581
f21a4817
JL		 582/* CPUID Leaf 0x1D constants: */
583#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
584#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
585#define INTEL_AMX_BYTES_PER_TILE 0x400
586#define INTEL_AMX_BYTES_PER_ROW 0x40
587#define INTEL_AMX_TILE_MAX_NAMES 0x8
588#define INTEL_AMX_TILE_MAX_ROWS 0x10
589
590/* CPUID Leaf 0x1E constants: */
591#define INTEL_AMX_TMUL_MAX_K 0x10
592#define INTEL_AMX_TMUL_MAX_N 0x40
593
f5cc5a5c
CF		 594void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
595 uint32_t vendor2, uint32_t vendor3)
99b88a17
IM		 596{
597 int i;
598 for (i = 0; i < 4; i++) {
599 dst[i] = vendor1 >> (8 * i);
600 dst[i + 4] = vendor2 >> (8 * i);
601 dst[i + 8] = vendor3 >> (8 * i);
602 }
603 dst[CPUID_VENDOR_SZ] = '\0';
604}
605
621626ce
EH		 606#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
607#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
608 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
609#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
610 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
611 CPUID_PSE36 | CPUID_FXSR)
612#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
613#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
614 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
615 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
616 CPUID_PAE | CPUID_SEP | CPUID_APIC)
617
618#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
619 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
620 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
621 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 622 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 623 /* partly implemented:
624 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
625 /* missing:
626 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
d903259d
PB		 627
628/*
629 * Kernel-only features that can be shown to usermode programs even if
630 * they aren't actually supported by TCG, because qemu-user only runs
631 * in CPL=3; remove them if they are ever implemented for system emulation.
632 */
633#if defined CONFIG_USER_ONLY
774204cf
BQM		 634#define CPUID_EXT_KERNEL_FEATURES \
635 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER)
d903259d
PB		 636#else
637#define CPUID_EXT_KERNEL_FEATURES 0
638#endif
621626ce
EH		 639#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
2872b0f3 644 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
774204cf 645 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES)
621626ce
EH		 646 /* missing:
647 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
2872b0f3 648 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
621626ce 649 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
774204cf
BQM		 650 CPUID_EXT_TSC_DEADLINE_TIMER
651 */
621626ce
EH		 652
653#ifdef TARGET_X86_64
63fd8ef0 654#define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM
621626ce
EH		 655#else
656#define TCG_EXT2_X86_64_FEATURES 0
657#endif
658
d903259d
PB		 659/*
660 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable
661 * in usermode or by 32-bit programs. Those are added to supported
662 * TCG features unconditionally in user-mode emulation mode. This may
663 * indeed seem strange or incorrect, but it works because code running
664 * under usermode emulation cannot access them.
665 *
666 * Even for long mode, qemu-i386 is not running "a userspace program on a
667 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
668 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit
669 * but again the difference is only visible in kernel mode.
670 */
40a205da
PB		 671#if defined CONFIG_LINUX_USER
672#define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR)
673#elif defined CONFIG_USER_ONLY
674/* FIXME: Long mode not yet supported for i386 bsd-user */
d903259d
PB		 675#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
676#else
677#define CPUID_EXT2_KERNEL_FEATURES 0
678#endif
679
621626ce
EH		 680#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
681 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
682 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
d903259d
PB		 683 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \
684 CPUID_EXT2_KERNEL_FEATURES)
685
686#if defined CONFIG_USER_ONLY
687#define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW
688#else
689#define CPUID_EXT3_KERNEL_FEATURES 0
690#endif
691
621626ce 692#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
8afce497 693 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
d903259d
PB		 694 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES)
695
621626ce 696#define TCG_EXT4_FEATURES 0
d903259d
PB		 697
698#if defined CONFIG_USER_ONLY
699#define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI)
700#else
701#define CPUID_SVM_KERNEL_FEATURES 0
702#endif
900eeca5 703#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
d903259d
PB		 704 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES)
705
621626ce 706#define TCG_KVM_FEATURES 0
d903259d
PB		 707
708#if defined CONFIG_USER_ONLY
709#define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID
710#else
711#define CPUID_7_0_EBX_KERNEL_FEATURES 0
712#endif
621626ce 713#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 714 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
715 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386 716 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
d903259d 717 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \
e582b629 718 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES)
621626ce 719 /* missing:
2f8a21d8 720 CPUID_7_0_EBX_HLE
691925e5 721 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
6750485b 722
1da389c5 723#if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX
6750485b
PB		 724#define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
725#else
726#define TCG_7_0_ECX_RDPID 0
727#endif
637f1ee3 728#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
9ccb9784 729 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6750485b
PB		 730 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
731 TCG_7_0_ECX_RDPID)
732
d903259d
PB		 733#if defined CONFIG_USER_ONLY
734#define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \
735 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD)
736#else
737#define CPUID_7_0_EDX_KERNEL_FEATURES 0
738#endif
739#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES)
740
58794f64 741#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
405c7c07 742 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD)
eaaa197d 743#define TCG_7_1_EDX_FEATURES 0
9dd8b710 744#define TCG_7_2_EDX_FEATURES 0
303752a9 745#define TCG_APM_FEATURES 0
28b8e4d0 746#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 747#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
748 /* missing:
749 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
d1615ea5 750#define TCG_14_0_ECX_FEATURES 0
4b841a79 751#define TCG_SGX_12_0_EAX_FEATURES 0
120ca112 752#define TCG_SGX_12_0_EBX_FEATURES 0
165981a5 753#define TCG_SGX_12_1_EAX_FEATURES 0
621626ce 754
d903259d
PB		 755#if defined CONFIG_USER_ONLY
756#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
757 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \
758 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \
759 CPUID_8000_0008_EBX_AMD_PSFD)
760#else
761#define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
762#endif
763
431c51e9 764#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
d903259d 765 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES)
1420dd6a 766
79f1a68a 767FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 768 [FEAT_1_EDX] = {
07585923 769 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 770 .feat_names = {
771 "fpu", "vme", "de", "pse",
772 "tsc", "msr", "pae", "mce",
773 "cx8", "apic", NULL, "sep",
774 "mtrr", "pge", "mca", "cmov",
775 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
776 NULL, "ds" /* Intel dts */, "acpi", "mmx",
777 "fxsr", "sse", "sse2", "ss",
778 "ht" /* Intel htt */, "tm", "ia64", "pbe",
779 },
07585923 780 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 781 .tcg_features = TCG_FEATURES,
83629b14 782 .no_autoenable_flags = CPUID_HT,
bffd67b0
EH		 783 },
784 [FEAT_1_ECX] = {
07585923 785 .type = CPUID_FEATURE_WORD,
2d5312da 786 .feat_names = {
16d2fcaa 787 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 788 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 789 "tm2", "ssse3", "cid", NULL,
790 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 791 NULL, "pcid", "dca", "sse4.1",
792 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 793 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 794 "avx", "f16c", "rdrand", "hypervisor",
795 },
07585923 796 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 797 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 798 },
2d5312da
EH		 799 /* Feature names that are already defined on feature_name[] but
800 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
801 * names on feat_names below. They are copied automatically
802 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
803 */
bffd67b0 804 [FEAT_8000_0001_EDX] = {
07585923 805 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 806 .feat_names = {
807 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
808 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
809 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
810 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
811 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 812 "nx", NULL, "mmxext", NULL /* mmx */,
813 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
814 NULL, "lm", "3dnowext", "3dnow",
2d5312da 815 },
07585923 816 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 817 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 818 },
819 [FEAT_8000_0001_ECX] = {
07585923 820 .type = CPUID_FEATURE_WORD,
2d5312da 821 .feat_names = {
fc7dfd20 822 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 823 "cr8legacy", "abm", "sse4a", "misalignsse",
824 "3dnowprefetch", "osvw", "ibs", "xop",
825 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 826 "fma4", "tce", NULL, "nodeid-msr",
827 NULL, "tbm", "topoext", "perfctr-core",
828 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 829 NULL, NULL, NULL, NULL,
830 },
07585923 831 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 832 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 833 /*
834 * TOPOEXT is always allowed but can't be enabled blindly by
835 * "-cpu host", as it requires consistent cache topology info
836 * to be provided so it doesn't confuse guests.
837 */
838 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 839 },
89e49c8b 840 [FEAT_C000_0001_EDX] = {
07585923 841 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 842 .feat_names = {
843 NULL, NULL, "xstore", "xstore-en",
844 NULL, NULL, "xcrypt", "xcrypt-en",
845 "ace2", "ace2-en", "phe", "phe-en",
846 "pmm", "pmm-en", NULL, NULL,
847 NULL, NULL, NULL, NULL,
848 NULL, NULL, NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 },
07585923 852 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 853 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 854 },
bffd67b0 855 [FEAT_KVM] = {
07585923 856 .type = CPUID_FEATURE_WORD,
2d5312da 857 .feat_names = {
fc7dfd20
EH		 858 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
859 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
eba97806 860 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi",
c1bb5418 861 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
2d5312da
EH		 862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 "kvmclock-stable-bit", NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 },
07585923 867 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 868 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 869 },
be777326 870 [FEAT_KVM_HINTS] = {
07585923 871 .type = CPUID_FEATURE_WORD,
be777326
WL		 872 .feat_names = {
873 "kvm-hint-dedicated", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 NULL, NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
07585923 882 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 883 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 884 /*
885 * KVM hints aren't auto-enabled by -cpu host, they need to be
886 * explicitly enabled in the command-line.
887 */
888 .no_autoenable_flags = ~0U,
be777326 889 },
bffd67b0 890 [FEAT_SVM] = {
07585923 891 .type = CPUID_FEATURE_WORD,
2d5312da 892 .feat_names = {
fc7dfd20
EH		 893 "npt", "lbrv", "svm-lock", "nrip-save",
894 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
895 NULL, NULL, "pause-filter", NULL,
5447089c
WH		 896 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
897 "vgif", NULL, NULL, NULL,
2d5312da 898 NULL, NULL, NULL, NULL,
62a798d4 899 NULL, "vnmi", NULL, NULL,
5447089c 900 "svme-addr-chk", NULL, NULL, NULL,
2d5312da 901 },
07585923 902 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 903 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 904 },
905 [FEAT_7_0_EBX] = {
07585923 906 .type = CPUID_FEATURE_WORD,
2d5312da 907 .feat_names = {
5c76b651 908 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
2d5312da
EH		 909 "hle", "avx2", NULL, "smep",
910 "bmi2", "erms", "invpcid", "rtm",
911 NULL, NULL, "mpx", NULL,
912 "avx512f", "avx512dq", "rdseed", "adx",
913 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 914 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 915 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 916 },
07585923
RH		 917 .cpuid = {
918 .eax = 7,
919 .needs_ecx = true, .ecx = 0,
920 .reg = R_EBX,
921 },
37ce3522 922 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 923 },
f74eefe0 924 [FEAT_7_0_ECX] = {
07585923 925 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 926 .feat_names = {
927 NULL, "avx512vbmi", "umip", "pku",
67192a29 928 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 929 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
930 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 931 "la57", NULL, NULL, NULL,
2d5312da 932 NULL, NULL, "rdpid", NULL,
06e878b4 933 "bus-lock-detect", "cldemote", NULL, "movdiri",
5c76b651 934 "movdir64b", NULL, "sgxlc", "pks",
2d5312da 935 },
07585923
RH		 936 .cpuid = {
937 .eax = 7,
938 .needs_ecx = true, .ecx = 0,
939 .reg = R_ECX,
940 },
f74eefe0
HH		 941 .tcg_features = TCG_7_0_ECX_FEATURES,
942 },
95ea69fb 943 [FEAT_7_0_EDX] = {
07585923 944 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 945 .feat_names = {
946 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
5cb287d2 947 "fsrm", NULL, NULL, NULL,
353f98c9 948 "avx512-vp2intersect", NULL, "md-clear", NULL,
5dd13f2a 949 NULL, NULL, "serialize", NULL,
c3c67679 950 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr",
f21a4817
JL		 951 NULL, NULL, "amx-bf16", "avx512-fp16",
952 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
0e7e3bf1 953 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
95ea69fb 954 },
07585923
RH		 955 .cpuid = {
956 .eax = 7,
957 .needs_ecx = true, .ecx = 0,
958 .reg = R_EDX,
959 },
95ea69fb
LK		 960 .tcg_features = TCG_7_0_EDX_FEATURES,
961 },
80db491d
JL		 962 [FEAT_7_1_EAX] = {
963 .type = CPUID_FEATURE_WORD,
964 .feat_names = {
965 NULL, NULL, NULL, NULL,
a9ce107f 966 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
58794f64
PB		 967 NULL, NULL, "fzrm", "fsrs",
968 "fsrc", NULL, NULL, NULL,
80db491d 969 NULL, NULL, NULL, NULL,
a957a884 970 NULL, "amx-fp16", NULL, "avx-ifma",
80db491d
JL		 971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 },
974 .cpuid = {
975 .eax = 7,
976 .needs_ecx = true, .ecx = 1,
977 .reg = R_EAX,
978 },
979 .tcg_features = TCG_7_1_EAX_FEATURES,
980 },
eaaa197d
JC		 981 [FEAT_7_1_EDX] = {
982 .type = CPUID_FEATURE_WORD,
983 .feat_names = {
984 NULL, NULL, NULL, NULL,
ecd2e6ca 985 "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
3e76bafb 986 "amx-complex", NULL, NULL, NULL,
d1a11115 987 NULL, NULL, "prefetchiti", NULL,
eaaa197d
JC		 988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
993 .cpuid = {
994 .eax = 7,
995 .needs_ecx = true, .ecx = 1,
996 .reg = R_EDX,
997 },
998 .tcg_features = TCG_7_1_EDX_FEATURES,
999 },
9dd8b710
TS		 1000 [FEAT_7_2_EDX] = {
1001 .type = CPUID_FEATURE_WORD,
1002 .feat_names = {
1003 NULL, NULL, NULL, NULL,
1004 NULL, "mcdt-no", NULL, NULL,
1005 NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 },
1012 .cpuid = {
1013 .eax = 7,
1014 .needs_ecx = true, .ecx = 2,
1015 .reg = R_EDX,
1016 },
1017 .tcg_features = TCG_7_2_EDX_FEATURES,
1018 },
303752a9 1019 [FEAT_8000_0007_EDX] = {
07585923 1020 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1021 .feat_names = {
1022 NULL, NULL, NULL, NULL,
1023 NULL, NULL, NULL, NULL,
1024 "invtsc", NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 NULL, NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 },
07585923 1031 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1032 .tcg_features = TCG_APM_FEATURES,
1033 .unmigratable_flags = CPUID_APM_INVTSC,
1034 },
1b3420e1 1035 [FEAT_8000_0008_EBX] = {
07585923 1036 .type = CPUID_FEATURE_WORD,
1b3420e1 1037 .feat_names = {
e900135d 1038 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 1039 NULL, NULL, NULL, NULL,
59a80a19 1040 NULL, "wbnoinvd", NULL, NULL,
623972ce 1041 "ibpb", NULL, "ibrs", "amd-stibp",
bb039a23 1042 NULL, "stibp-always-on", NULL, NULL,
1b3420e1 1043 NULL, NULL, NULL, NULL,
254790a9 1044 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
bb039a23 1045 "amd-psfd", NULL, NULL, NULL,
1b3420e1 1046 },
07585923 1047 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1420dd6a 1048 .tcg_features = TCG_8000_0008_EBX,
1b3420e1
EH		 1049 .unmigratable_flags = 0,
1050 },
b70eec31
BM		 1051 [FEAT_8000_0021_EAX] = {
1052 .type = CPUID_FEATURE_WORD,
1053 .feat_names = {
1054 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
1055 NULL, NULL, "null-sel-clr-base", NULL,
62a798d4 1056 "auto-ibrs", NULL, NULL, NULL,
b70eec31
BM		 1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL,
1062 },
1063 .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
1064 .tcg_features = 0,
1065 .unmigratable_flags = 0,
1066 },
0bb0b2d2 1067 [FEAT_XSAVE] = {
07585923 1068 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1069 .feat_names = {
1070 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
f21a4817 1071 "xfd", NULL, NULL, NULL,
2d5312da
EH		 1072 NULL, NULL, NULL, NULL,
1073 NULL, NULL, NULL, NULL,
1074 NULL, NULL, NULL, NULL,
1075 NULL, NULL, NULL, NULL,
1076 NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL,
1078 },
07585923
RH		 1079 .cpuid = {
1080 .eax = 0xd,
1081 .needs_ecx = true, .ecx = 1,
1082 .reg = R_EAX,
1083 },
c9cfe8f9 1084 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1085 },
301e9067
YW		 1086 [FEAT_XSAVE_XSS_LO] = {
1087 .type = CPUID_FEATURE_WORD,
1088 .feat_names = {
1089 NULL, NULL, NULL, NULL,
1090 NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, NULL,
1092 NULL, NULL, NULL, NULL,
1093 NULL, NULL, NULL, NULL,
1094 NULL, NULL, NULL, NULL,
1095 NULL, NULL, NULL, NULL,
1096 NULL, NULL, NULL, NULL,
1097 },
1098 .cpuid = {
1099 .eax = 0xD,
1100 .needs_ecx = true,
1101 .ecx = 1,
1102 .reg = R_ECX,
1103 },
1104 },
1105 [FEAT_XSAVE_XSS_HI] = {
1106 .type = CPUID_FEATURE_WORD,
1107 .cpuid = {
1108 .eax = 0xD,
1109 .needs_ecx = true,
1110 .ecx = 1,
1111 .reg = R_EDX
1112 },
1113 },
28b8e4d0 1114 [FEAT_6_EAX] = {
07585923 1115 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1116 .feat_names = {
1117 NULL, NULL, "arat", NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
07585923 1126 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1127 .tcg_features = TCG_6_EAX_FEATURES,
1128 },
301e9067 1129 [FEAT_XSAVE_XCR0_LO] = {
07585923
RH		 1130 .type = CPUID_FEATURE_WORD,
1131 .cpuid = {
1132 .eax = 0xD,
1133 .needs_ecx = true, .ecx = 0,
1134 .reg = R_EAX,
1135 },
96193c22 1136 .tcg_features = ~0U,
6fb2fff7
EH		 1137 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1138 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1139 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1140 XSTATE_PKRU_MASK,
96193c22 1141 },
301e9067 1142 [FEAT_XSAVE_XCR0_HI] = {
07585923
RH		 1143 .type = CPUID_FEATURE_WORD,
1144 .cpuid = {
1145 .eax = 0xD,
1146 .needs_ecx = true, .ecx = 0,
1147 .reg = R_EDX,
1148 },
96193c22
EH		 1149 .tcg_features = ~0U,
1150 },
d86f9636
RH		 1151 /*Below are MSR exposed features*/
1152 [FEAT_ARCH_CAPABILITIES] = {
1153 .type = MSR_FEATURE_WORD,
1154 .feat_names = {
1155 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1156 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1157 "taa-no", NULL, NULL, NULL,
5bef742c 1158 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no",
22e1094c 1159 NULL, "fb-clear", NULL, NULL,
d86f9636 1160 NULL, NULL, NULL, NULL,
3a2a1f97 1161 "pbrsb-no", NULL, "gds-no", NULL,
d86f9636
RH		 1162 NULL, NULL, NULL, NULL,
1163 },
1164 .msr = {
1165 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636 1166 },
9fb4f5f5
PB		 1167 /*
1168 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which
1169 * cannot be read from user mode. Therefore, it has no impact
1170 > on any user-mode operation, and warnings about unsupported
1171 * features do not matter.
1172 */
1173 .tcg_features = ~0U,
d86f9636 1174 },
597360c0
XL		 1175 [FEAT_CORE_CAPABILITY] = {
1176 .type = MSR_FEATURE_WORD,
1177 .feat_names = {
1178 NULL, NULL, NULL, NULL,
1179 NULL, "split-lock-detect", NULL, NULL,
1180 NULL, NULL, NULL, NULL,
1181 NULL, NULL, NULL, NULL,
1182 NULL, NULL, NULL, NULL,
1183 NULL, NULL, NULL, NULL,
1184 NULL, NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 },
1187 .msr = {
1188 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1189 },
1190 },
ea39f9b6
LX		 1191 [FEAT_PERF_CAPABILITIES] = {
1192 .type = MSR_FEATURE_WORD,
1193 .feat_names = {
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 NULL, "full-width-write", NULL, NULL,
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 NULL, NULL, NULL, NULL,
1202 },
1203 .msr = {
1204 .index = MSR_IA32_PERF_CAPABILITIES,
1205 },
1206 },
20a78b02
PB		 1207
1208 [FEAT_VMX_PROCBASED_CTLS] = {
1209 .type = MSR_FEATURE_WORD,
1210 .feat_names = {
1211 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1212 NULL, NULL, NULL, "vmx-hlt-exit",
1213 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1214 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1215 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1216 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1217 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1218 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1219 },
1220 .msr = {
1221 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1222 }
1223 },
1224
1225 [FEAT_VMX_SECONDARY_CTLS] = {
1226 .type = MSR_FEATURE_WORD,
1227 .feat_names = {
1228 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1229 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1230 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1231 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1232 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1233 "vmx-xsaves", NULL, NULL, NULL,
33cc8826 1234 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
20a78b02
PB		 1235 NULL, NULL, NULL, NULL,
1236 },
1237 .msr = {
1238 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1239 }
1240 },
1241
1242 [FEAT_VMX_PINBASED_CTLS] = {
1243 .type = MSR_FEATURE_WORD,
1244 .feat_names = {
1245 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1246 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1247 NULL, NULL, NULL, NULL,
1248 NULL, NULL, NULL, NULL,
1249 NULL, NULL, NULL, NULL,
1250 NULL, NULL, NULL, NULL,
1251 NULL, NULL, NULL, NULL,
1252 NULL, NULL, NULL, NULL,
1253 },
1254 .msr = {
1255 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1256 }
1257 },
1258
1259 [FEAT_VMX_EXIT_CTLS] = {
1260 .type = MSR_FEATURE_WORD,
1261 /*
1262 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1263 * the LM CPUID bit.
1264 */
1265 .feat_names = {
1266 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1267 NULL, NULL, NULL, NULL,
1268 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1269 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1270 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1271 "vmx-exit-save-efer", "vmx-exit-load-efer",
1272 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1273 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
52a44ad2 1274 NULL, "vmx-exit-load-pkrs", NULL, NULL,
20a78b02
PB		 1275 },
1276 .msr = {
1277 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1278 }
1279 },
1280
1281 [FEAT_VMX_ENTRY_CTLS] = {
1282 .type = MSR_FEATURE_WORD,
1283 .feat_names = {
1284 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1285 NULL, NULL, NULL, NULL,
1286 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1287 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1288 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
52a44ad2 1289 NULL, NULL, "vmx-entry-load-pkrs", NULL,
20a78b02
PB		 1290 NULL, NULL, NULL, NULL,
1291 NULL, NULL, NULL, NULL,
1292 },
1293 .msr = {
1294 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1295 }
1296 },
1297
1298 [FEAT_VMX_MISC] = {
1299 .type = MSR_FEATURE_WORD,
1300 .feat_names = {
1301 NULL, NULL, NULL, NULL,
1302 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1303 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1304 NULL, NULL, NULL, NULL,
1305 NULL, NULL, NULL, NULL,
1306 NULL, NULL, NULL, NULL,
1307 NULL, NULL, NULL, NULL,
1308 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1309 },
1310 .msr = {
1311 .index = MSR_IA32_VMX_MISC,
1312 }
1313 },
1314
1315 [FEAT_VMX_EPT_VPID_CAPS] = {
1316 .type = MSR_FEATURE_WORD,
1317 .feat_names = {
1318 "vmx-ept-execonly", NULL, NULL, NULL,
1319 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1320 NULL, NULL, NULL, NULL,
1321 NULL, NULL, NULL, NULL,
1322 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1323 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1324 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1325 NULL, NULL, NULL, NULL,
1326 "vmx-invvpid", NULL, NULL, NULL,
1327 NULL, NULL, NULL, NULL,
1328 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1329 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1330 NULL, NULL, NULL, NULL,
1331 NULL, NULL, NULL, NULL,
1332 NULL, NULL, NULL, NULL,
1333 NULL, NULL, NULL, NULL,
1334 NULL, NULL, NULL, NULL,
1335 },
1336 .msr = {
1337 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1338 }
1339 },
1340
1341 [FEAT_VMX_BASIC] = {
1342 .type = MSR_FEATURE_WORD,
1343 .feat_names = {
1344 [54] = "vmx-ins-outs",
1345 [55] = "vmx-true-ctls",
0c49c918 1346 [56] = "vmx-any-errcode",
20a78b02
PB		 1347 },
1348 .msr = {
1349 .index = MSR_IA32_VMX_BASIC,
1350 },
1351 /* Just to be safe - we don't support setting the MSEG version field. */
1352 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1353 },
1354
1355 [FEAT_VMX_VMFUNC] = {
1356 .type = MSR_FEATURE_WORD,
1357 .feat_names = {
1358 [0] = "vmx-eptp-switching",
1359 },
1360 .msr = {
1361 .index = MSR_IA32_VMX_VMFUNC,
1362 }
1363 },
1364
d1615ea5
LK		 1365 [FEAT_14_0_ECX] = {
1366 .type = CPUID_FEATURE_WORD,
1367 .feat_names = {
1368 NULL, NULL, NULL, NULL,
1369 NULL, NULL, NULL, NULL,
1370 NULL, NULL, NULL, NULL,
1371 NULL, NULL, NULL, NULL,
1372 NULL, NULL, NULL, NULL,
1373 NULL, NULL, NULL, NULL,
1374 NULL, NULL, NULL, NULL,
1375 NULL, NULL, NULL, "intel-pt-lip",
1376 },
1377 .cpuid = {
1378 .eax = 0x14,
1379 .needs_ecx = true, .ecx = 0,
1380 .reg = R_ECX,
1381 },
1382 .tcg_features = TCG_14_0_ECX_FEATURES,
1383 },
1384
4b841a79
SC		 1385 [FEAT_SGX_12_0_EAX] = {
1386 .type = CPUID_FEATURE_WORD,
1387 .feat_names = {
1388 "sgx1", "sgx2", NULL, NULL,
1389 NULL, NULL, NULL, NULL,
d45f24fe 1390 NULL, NULL, NULL, "sgx-edeccssa",
4b841a79
SC		 1391 NULL, NULL, NULL, NULL,
1392 NULL, NULL, NULL, NULL,
1393 NULL, NULL, NULL, NULL,
1394 NULL, NULL, NULL, NULL,
1395 NULL, NULL, NULL, NULL,
1396 },
1397 .cpuid = {
1398 .eax = 0x12,
1399 .needs_ecx = true, .ecx = 0,
1400 .reg = R_EAX,
1401 },
1402 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1403 },
120ca112
SC		 1404
1405 [FEAT_SGX_12_0_EBX] = {
1406 .type = CPUID_FEATURE_WORD,
1407 .feat_names = {
1408 "sgx-exinfo" , NULL, NULL, NULL,
1409 NULL, NULL, NULL, NULL,
1410 NULL, NULL, NULL, NULL,
1411 NULL, NULL, NULL, NULL,
1412 NULL, NULL, NULL, NULL,
1413 NULL, NULL, NULL, NULL,
1414 NULL, NULL, NULL, NULL,
1415 NULL, NULL, NULL, NULL,
1416 },
1417 .cpuid = {
1418 .eax = 0x12,
1419 .needs_ecx = true, .ecx = 0,
1420 .reg = R_EBX,
1421 },
1422 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1423 },
165981a5
SC		 1424
1425 [FEAT_SGX_12_1_EAX] = {
1426 .type = CPUID_FEATURE_WORD,
1427 .feat_names = {
1428 NULL, "sgx-debug", "sgx-mode64", NULL,
1429 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
d45f24fe 1430 NULL, NULL, "sgx-aex-notify", NULL,
165981a5
SC		 1431 NULL, NULL, NULL, NULL,
1432 NULL, NULL, NULL, NULL,
1433 NULL, NULL, NULL, NULL,
1434 NULL, NULL, NULL, NULL,
1435 NULL, NULL, NULL, NULL,
1436 },
1437 .cpuid = {
1438 .eax = 0x12,
1439 .needs_ecx = true, .ecx = 1,
1440 .reg = R_EAX,
1441 },
1442 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1443 },
5ef57876
EH		 1444};
1445
99e24dbd
PB		 1446typedef struct FeatureMask {
1447 FeatureWord index;
ede146c2 1448 uint64_t mask;
99e24dbd
PB		 1449} FeatureMask;
1450
1451typedef struct FeatureDep {
1452 FeatureMask from, to;
1453} FeatureDep;
1454
1455static FeatureDep feature_dependencies[] = {
1456 {
1457 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1458 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1459 },
1460 {
1461 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1462 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1463 },
ea39f9b6
LX		 1464 {
1465 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1466 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1467 },
20a78b02
PB		 1468 {
1469 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1470 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1471 },
1472 {
1473 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1474 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1475 },
1476 {
1477 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1478 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1479 },
1480 {
1481 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1482 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1483 },
1484 {
1485 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1486 .to = { FEAT_VMX_MISC, ~0ull },
1487 },
1488 {
1489 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1490 .to = { FEAT_VMX_BASIC, ~0ull },
1491 },
1492 {
1493 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1494 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1495 },
1496 {
1497 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1498 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1499 },
1500 {
1501 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1502 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1503 },
1504 {
1505 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1506 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1507 },
1508 {
1509 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1510 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1511 },
267b5e7e
MS		 1512 {
1513 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1514 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS },
1515 },
1516 {
1517 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX },
1518 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS },
1519 },
20a78b02
PB		 1520 {
1521 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1522 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1523 },
d1615ea5
LK		 1524 {
1525 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1526 .to = { FEAT_14_0_ECX, ~0ull },
1527 },
20a78b02
PB		 1528 {
1529 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1530 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1531 },
1532 {
1533 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1534 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1535 },
1536 {
1537 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1538 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1539 },
1540 {
1541 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1542 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1543 },
1544 {
1545 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1546 .to = { FEAT_VMX_VMFUNC, ~0ull },
1547 },
730319ae
EH		 1548 {
1549 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1550 .to = { FEAT_SVM, ~0ull },
1551 },
33cc8826
AK		 1552 {
1553 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
1554 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
1555 },
99e24dbd
PB		 1556};
1557
8e8aba50
EH		 1558typedef struct X86RegisterInfo32 {
1559 /* Name of register */
1560 const char *name;
1561 /* QAPI enum value register */
1562 X86CPURegister32 qapi_enum;
1563} X86RegisterInfo32;
1564
1565#define REGISTER(reg) \
5d371f41 1566 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1567static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1568 REGISTER(EAX),
1569 REGISTER(ECX),
1570 REGISTER(EDX),
1571 REGISTER(EBX),
1572 REGISTER(ESP),
1573 REGISTER(EBP),
1574 REGISTER(ESI),
1575 REGISTER(EDI),
1576};
1577#undef REGISTER
1578
301e9067 1579/* CPUID feature bits available in XSS */
10f0abcb 1580#define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
301e9067 1581
fea45008 1582ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
e3c9022b
EH		 1583 [XSTATE_FP_BIT] = {
1584 /* x87 FP state component is always enabled if XSAVE is supported */
1585 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1586 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1587 },
1588 [XSTATE_SSE_BIT] = {
1589 /* SSE state component is always enabled if XSAVE is supported */
1590 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
e3c9022b
EH		 1591 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1592 },
cfc3b074
PB		 1593 [XSTATE_YMM_BIT] =
1594 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6 1595 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1596 [XSTATE_BNDREGS_BIT] =
1597 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1598 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1599 [XSTATE_BNDCSR_BIT] =
1600 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6 1601 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1602 [XSTATE_OPMASK_BIT] =
1603 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1604 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1605 [XSTATE_ZMM_Hi256_BIT] =
1606 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1607 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1608 [XSTATE_Hi16_ZMM_BIT] =
1609 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6 1610 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1611 [XSTATE_PKRU_BIT] =
1612 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6 1613 .size = sizeof(XSavePKRU) },
10f0abcb
YW		 1614 [XSTATE_ARCH_LBR_BIT] = {
1615 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR,
1616 .offset = 0 /*supervisor mode component, offset = 0 */,
1617 .size = sizeof(XSavesArchLBR) },
1f16764f
JL		 1618 [XSTATE_XTILE_CFG_BIT] = {
1619 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1620 .size = sizeof(XSaveXTILECFG),
1621 },
1622 [XSTATE_XTILE_DATA_BIT] = {
1623 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
1624 .size = sizeof(XSaveXTILEDATA)
1625 },
2560f19f 1626};
8e8aba50 1627
5d245678 1628uint32_t xsave_area_size(uint64_t mask, bool compacted)
1fda6198 1629{
301e9067
YW		 1630 uint64_t ret = x86_ext_save_areas[0].size;
1631 const ExtSaveArea *esa;
1632 uint32_t offset = 0;
1fda6198 1633 int i;
1fda6198 1634
301e9067
YW		 1635 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1636 esa = &x86_ext_save_areas[i];
1fda6198 1637 if ((mask >> i) & 1) {
301e9067
YW		 1638 offset = compacted ? ret : esa->offset;
1639 ret = MAX(ret, offset + esa->size);
1fda6198
EH		 1640 }
1641 }
1642 return ret;
1643}
1644
d6dcc558
SAGDR		 1645static inline bool accel_uses_host_cpuid(void)
1646{
1647 return kvm_enabled() || hvf_enabled();
1648}
1649
301e9067 1650static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu)
96193c22 1651{
301e9067
YW		 1652 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 |
1653 cpu->env.features[FEAT_XSAVE_XCR0_LO];
96193c22
EH		 1654}
1655
ed69e831
CF		 1656/* Return name of 32-bit register, from a R_* constant */
1657static const char *get_register_name_32(unsigned int reg)
8b4beddc 1658{
31ccdde2 1659 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1660 return NULL;
1661 }
8e8aba50 1662 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1663}
1664
301e9067
YW		 1665static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu)
1666{
1667 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 |
1668 cpu->env.features[FEAT_XSAVE_XSS_LO];
1669}
1670
84f1b92f
EH		 1671/*
1672 * Returns the set of feature flags that are supported and migratable by
1673 * QEMU, for a given FeatureWord.
1674 */
ede146c2 1675static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1676{
1677 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1678 uint64_t r = 0;
84f1b92f
EH		 1679 int i;
1680
ede146c2
PB		 1681 for (i = 0; i < 64; i++) {
1682 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1683
1684 /* If the feature name is known, it is implicitly considered migratable,
1685 * unless it is explicitly set in unmigratable_flags */
1686 if ((wi->migratable_flags & f) ||
1687 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1688 r |= f;
84f1b92f 1689 }
84f1b92f
EH		 1690 }
1691 return r;
1692}
1693
bb44e0d1
JK		 1694void host_cpuid(uint32_t function, uint32_t count,
1695 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1696{
a1fd24af
AL		 1697 uint32_t vec[4];
1698
1699#ifdef __x86_64__
1700 asm volatile("cpuid"
1701 : "=a"(vec[0]), "=b"(vec[1]),
1702 "=c"(vec[2]), "=d"(vec[3])
1703 : "0"(function), "c"(count) : "cc");
c1f41226 1704#elif defined(__i386__)
a1fd24af
AL		 1705 asm volatile("pusha \n\t"
1706 "cpuid \n\t"
1707 "mov %%eax, 0(%2) \n\t"
1708 "mov %%ebx, 4(%2) \n\t"
1709 "mov %%ecx, 8(%2) \n\t"
1710 "mov %%edx, 12(%2) \n\t"
1711 "popa"
1712 : : "a"(function), "c"(count), "S"(vec)
1713 : "memory", "cc");
c1f41226
EH		 1714#else
1715 abort();
a1fd24af
AL		 1716#endif
1717
bdde476a 1718 if (eax)
a1fd24af 1719 *eax = vec[0];
bdde476a 1720 if (ebx)
a1fd24af 1721 *ebx = vec[1];
bdde476a 1722 if (ecx)
a1fd24af 1723 *ecx = vec[2];
bdde476a 1724 if (edx)
a1fd24af 1725 *edx = vec[3];
bdde476a 1726}
c6dc6f63 1727
d940ee9b
EH		 1728/* CPU class name definitions: */
1729
d940ee9b
EH		 1730/* Return type name for a given CPU model name
1731 * Caller is responsible for freeing the returned string.
1732 */
1733static char *x86_cpu_type_name(const char *model_name)
1734{
1735 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1736}
1737
500050d1
AF		 1738static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1739{
88703ce2
EH		 1740 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1741 return object_class_by_name(typename);
500050d1
AF		 1742}
1743
104494ea
IM		 1744static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1745{
1746 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1747 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
4b26aa9f 1748 return cpu_model_from_type(class_name);
104494ea
IM		 1749}
1750
dcafd1ef
EH		 1751typedef struct X86CPUVersionDefinition {
1752 X86CPUVersion version;
53db89d9 1753 const char *alias;
c63938df 1754 const char *note;
dcafd1ef 1755 PropValue *props;
cca0a000 1756 const CPUCaches *const cache_info;
dcafd1ef
EH		 1757} X86CPUVersionDefinition;
1758
1759/* Base definition for a CPU model */
1760typedef struct X86CPUDefinition {
c6dc6f63
AP		 1761 const char *name;
1762 uint32_t level;
90e4b0c3 1763 uint32_t xlevel;
99b88a17
IM		 1764 /* vendor is zero-terminated, 12 character ASCII string */
1765 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1766 int family;
1767 int model;
1768 int stepping;
0514ef2f 1769 FeatureWordArray features;
807e9869 1770 const char *model_id;
e845de38 1771 const CPUCaches *const cache_info;
dcafd1ef
EH		 1772 /*
1773 * Definitions for alternative versions of CPU model.
1774 * List is terminated by item with version == 0.
1775 * If NULL, version 1 will be registered automatically.
1776 */
1777 const X86CPUVersionDefinition *versions;
61ad65d0 1778 const char *deprecation_note;
dcafd1ef
EH		 1779} X86CPUDefinition;
1780
1781/* Reference to a specific CPU model version */
1782struct X86CPUModel {
1783 /* Base CPU definition */
e11fd689 1784 const X86CPUDefinition *cpudef;
dcafd1ef
EH		 1785 /* CPU model version */
1786 X86CPUVersion version;
c63938df 1787 const char *note;
0788a56b
EH		 1788 /*
1789 * If true, this is an alias CPU model.
1790 * This matters only for "-cpu help" and query-cpu-definitions
1791 */
1792 bool is_alias;
d940ee9b 1793};
c6dc6f63 1794
dcafd1ef 1795/* Get full model name for CPU version */
e11fd689 1796static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
dcafd1ef
EH		 1797 X86CPUVersion version)
1798{
1799 assert(version > 0);
1800 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1801}
1802
e11fd689
PMD		 1803static const X86CPUVersionDefinition *
1804x86_cpu_def_get_versions(const X86CPUDefinition *def)
dcafd1ef
EH		 1805{
1806 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1807 static const X86CPUVersionDefinition default_version_list[] = {
1808 { 1 },
1809 { /* end of list */ }
1810 };
1811
1812 return def->versions ?: default_version_list;
1813}
1814
e845de38 1815static const CPUCaches epyc_cache_info = {
a9f27ea9 1816 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1817 .type = DATA_CACHE,
fe52acd2
BM		 1818 .level = 1,
1819 .size = 32 * KiB,
1820 .line_size = 64,
1821 .associativity = 8,
1822 .partitions = 1,
1823 .sets = 64,
1824 .lines_per_tag = 1,
1825 .self_init = 1,
1826 .no_invd_sharing = true,
1827 },
a9f27ea9 1828 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1829 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1830 .level = 1,
1831 .size = 64 * KiB,
1832 .line_size = 64,
1833 .associativity = 4,
1834 .partitions = 1,
1835 .sets = 256,
1836 .lines_per_tag = 1,
1837 .self_init = 1,
1838 .no_invd_sharing = true,
1839 },
a9f27ea9 1840 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1841 .type = UNIFIED_CACHE,
1842 .level = 2,
1843 .size = 512 * KiB,
1844 .line_size = 64,
1845 .associativity = 8,
1846 .partitions = 1,
1847 .sets = 1024,
1848 .lines_per_tag = 1,
1849 },
a9f27ea9 1850 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1851 .type = UNIFIED_CACHE,
1852 .level = 3,
1853 .size = 8 * MiB,
1854 .line_size = 64,
1855 .associativity = 16,
1856 .partitions = 1,
1857 .sets = 8192,
1858 .lines_per_tag = 1,
1859 .self_init = true,
1860 .inclusive = true,
1861 .complex_indexing = true,
1862 },
1863};
1864
d7c72735
MR		 1865static CPUCaches epyc_v4_cache_info = {
1866 .l1d_cache = &(CPUCacheInfo) {
1867 .type = DATA_CACHE,
1868 .level = 1,
1869 .size = 32 * KiB,
1870 .line_size = 64,
1871 .associativity = 8,
1872 .partitions = 1,
1873 .sets = 64,
1874 .lines_per_tag = 1,
1875 .self_init = 1,
1876 .no_invd_sharing = true,
1877 },
1878 .l1i_cache = &(CPUCacheInfo) {
1879 .type = INSTRUCTION_CACHE,
1880 .level = 1,
1881 .size = 64 * KiB,
1882 .line_size = 64,
1883 .associativity = 4,
1884 .partitions = 1,
1885 .sets = 256,
1886 .lines_per_tag = 1,
1887 .self_init = 1,
1888 .no_invd_sharing = true,
1889 },
1890 .l2_cache = &(CPUCacheInfo) {
1891 .type = UNIFIED_CACHE,
1892 .level = 2,
1893 .size = 512 * KiB,
1894 .line_size = 64,
1895 .associativity = 8,
1896 .partitions = 1,
1897 .sets = 1024,
1898 .lines_per_tag = 1,
1899 },
1900 .l3_cache = &(CPUCacheInfo) {
1901 .type = UNIFIED_CACHE,
1902 .level = 3,
1903 .size = 8 * MiB,
1904 .line_size = 64,
1905 .associativity = 16,
1906 .partitions = 1,
1907 .sets = 8192,
1908 .lines_per_tag = 1,
1909 .self_init = true,
1910 .inclusive = true,
1911 .complex_indexing = false,
1912 },
1913};
1914
e845de38 1915static const CPUCaches epyc_rome_cache_info = {
143c30d4
MB		 1916 .l1d_cache = &(CPUCacheInfo) {
1917 .type = DATA_CACHE,
1918 .level = 1,
1919 .size = 32 * KiB,
1920 .line_size = 64,
1921 .associativity = 8,
1922 .partitions = 1,
1923 .sets = 64,
1924 .lines_per_tag = 1,
1925 .self_init = 1,
1926 .no_invd_sharing = true,
1927 },
1928 .l1i_cache = &(CPUCacheInfo) {
1929 .type = INSTRUCTION_CACHE,
1930 .level = 1,
1931 .size = 32 * KiB,
1932 .line_size = 64,
1933 .associativity = 8,
1934 .partitions = 1,
1935 .sets = 64,
1936 .lines_per_tag = 1,
1937 .self_init = 1,
1938 .no_invd_sharing = true,
1939 },
1940 .l2_cache = &(CPUCacheInfo) {
1941 .type = UNIFIED_CACHE,
1942 .level = 2,
1943 .size = 512 * KiB,
1944 .line_size = 64,
1945 .associativity = 8,
1946 .partitions = 1,
1947 .sets = 1024,
1948 .lines_per_tag = 1,
1949 },
1950 .l3_cache = &(CPUCacheInfo) {
1951 .type = UNIFIED_CACHE,
1952 .level = 3,
1953 .size = 16 * MiB,
1954 .line_size = 64,
1955 .associativity = 16,
1956 .partitions = 1,
1957 .sets = 16384,
1958 .lines_per_tag = 1,
1959 .self_init = true,
1960 .inclusive = true,
1961 .complex_indexing = true,
1962 },
1963};
1964
d7c72735
MR		 1965static const CPUCaches epyc_rome_v3_cache_info = {
1966 .l1d_cache = &(CPUCacheInfo) {
1967 .type = DATA_CACHE,
1968 .level = 1,
1969 .size = 32 * KiB,
1970 .line_size = 64,
1971 .associativity = 8,
1972 .partitions = 1,
1973 .sets = 64,
1974 .lines_per_tag = 1,
1975 .self_init = 1,
1976 .no_invd_sharing = true,
1977 },
1978 .l1i_cache = &(CPUCacheInfo) {
1979 .type = INSTRUCTION_CACHE,
1980 .level = 1,
1981 .size = 32 * KiB,
1982 .line_size = 64,
1983 .associativity = 8,
1984 .partitions = 1,
1985 .sets = 64,
1986 .lines_per_tag = 1,
1987 .self_init = 1,
1988 .no_invd_sharing = true,
1989 },
1990 .l2_cache = &(CPUCacheInfo) {
1991 .type = UNIFIED_CACHE,
1992 .level = 2,
1993 .size = 512 * KiB,
1994 .line_size = 64,
1995 .associativity = 8,
1996 .partitions = 1,
1997 .sets = 1024,
1998 .lines_per_tag = 1,
1999 },
2000 .l3_cache = &(CPUCacheInfo) {
2001 .type = UNIFIED_CACHE,
2002 .level = 3,
2003 .size = 16 * MiB,
2004 .line_size = 64,
2005 .associativity = 16,
2006 .partitions = 1,
2007 .sets = 16384,
2008 .lines_per_tag = 1,
2009 .self_init = true,
2010 .inclusive = true,
2011 .complex_indexing = false,
2012 },
2013};
2014
e845de38 2015static const CPUCaches epyc_milan_cache_info = {
623972ce
BM		 2016 .l1d_cache = &(CPUCacheInfo) {
2017 .type = DATA_CACHE,
2018 .level = 1,
2019 .size = 32 * KiB,
2020 .line_size = 64,
2021 .associativity = 8,
2022 .partitions = 1,
2023 .sets = 64,
2024 .lines_per_tag = 1,
2025 .self_init = 1,
2026 .no_invd_sharing = true,
2027 },
2028 .l1i_cache = &(CPUCacheInfo) {
2029 .type = INSTRUCTION_CACHE,
2030 .level = 1,
2031 .size = 32 * KiB,
2032 .line_size = 64,
2033 .associativity = 8,
2034 .partitions = 1,
2035 .sets = 64,
2036 .lines_per_tag = 1,
2037 .self_init = 1,
2038 .no_invd_sharing = true,
2039 },
2040 .l2_cache = &(CPUCacheInfo) {
2041 .type = UNIFIED_CACHE,
2042 .level = 2,
2043 .size = 512 * KiB,
2044 .line_size = 64,
2045 .associativity = 8,
2046 .partitions = 1,
2047 .sets = 1024,
2048 .lines_per_tag = 1,
2049 },
2050 .l3_cache = &(CPUCacheInfo) {
2051 .type = UNIFIED_CACHE,
2052 .level = 3,
2053 .size = 32 * MiB,
2054 .line_size = 64,
2055 .associativity = 16,
2056 .partitions = 1,
2057 .sets = 32768,
2058 .lines_per_tag = 1,
2059 .self_init = true,
2060 .inclusive = true,
2061 .complex_indexing = true,
2062 },
2063};
2064
27f03be6
BM		 2065static const CPUCaches epyc_milan_v2_cache_info = {
2066 .l1d_cache = &(CPUCacheInfo) {
2067 .type = DATA_CACHE,
2068 .level = 1,
2069 .size = 32 * KiB,
2070 .line_size = 64,
2071 .associativity = 8,
2072 .partitions = 1,
2073 .sets = 64,
2074 .lines_per_tag = 1,
2075 .self_init = 1,
2076 .no_invd_sharing = true,
2077 },
2078 .l1i_cache = &(CPUCacheInfo) {
2079 .type = INSTRUCTION_CACHE,
2080 .level = 1,
2081 .size = 32 * KiB,
2082 .line_size = 64,
2083 .associativity = 8,
2084 .partitions = 1,
2085 .sets = 64,
2086 .lines_per_tag = 1,
2087 .self_init = 1,
2088 .no_invd_sharing = true,
2089 },
2090 .l2_cache = &(CPUCacheInfo) {
2091 .type = UNIFIED_CACHE,
2092 .level = 2,
2093 .size = 512 * KiB,
2094 .line_size = 64,
2095 .associativity = 8,
2096 .partitions = 1,
2097 .sets = 1024,
2098 .lines_per_tag = 1,
2099 },
2100 .l3_cache = &(CPUCacheInfo) {
2101 .type = UNIFIED_CACHE,
2102 .level = 3,
2103 .size = 32 * MiB,
2104 .line_size = 64,
2105 .associativity = 16,
2106 .partitions = 1,
2107 .sets = 32768,
2108 .lines_per_tag = 1,
2109 .self_init = true,
2110 .inclusive = true,
2111 .complex_indexing = false,
2112 },
2113};
2114
166b1741
BM		 2115static const CPUCaches epyc_genoa_cache_info = {
2116 .l1d_cache = &(CPUCacheInfo) {
2117 .type = DATA_CACHE,
2118 .level = 1,
2119 .size = 32 * KiB,
2120 .line_size = 64,
2121 .associativity = 8,
2122 .partitions = 1,
2123 .sets = 64,
2124 .lines_per_tag = 1,
2125 .self_init = 1,
2126 .no_invd_sharing = true,
2127 },
2128 .l1i_cache = &(CPUCacheInfo) {
2129 .type = INSTRUCTION_CACHE,
2130 .level = 1,
2131 .size = 32 * KiB,
2132 .line_size = 64,
2133 .associativity = 8,
2134 .partitions = 1,
2135 .sets = 64,
2136 .lines_per_tag = 1,
2137 .self_init = 1,
2138 .no_invd_sharing = true,
2139 },
2140 .l2_cache = &(CPUCacheInfo) {
2141 .type = UNIFIED_CACHE,
2142 .level = 2,
2143 .size = 1 * MiB,
2144 .line_size = 64,
2145 .associativity = 8,
2146 .partitions = 1,
2147 .sets = 2048,
2148 .lines_per_tag = 1,
2149 },
2150 .l3_cache = &(CPUCacheInfo) {
2151 .type = UNIFIED_CACHE,
2152 .level = 3,
2153 .size = 32 * MiB,
2154 .line_size = 64,
2155 .associativity = 16,
2156 .partitions = 1,
2157 .sets = 32768,
2158 .lines_per_tag = 1,
2159 .self_init = true,
2160 .inclusive = true,
2161 .complex_indexing = false,
2162 },
2163};
2164
0723cc8a
PB		 2165/* The following VMX features are not supported by KVM and are left out in the
2166 * CPU definitions:
2167 *
2168 * Dual-monitor support (all processors)
2169 * Entry to SMM
2170 * Deactivate dual-monitor treatment
2171 * Number of CR3-target values
2172 * Shutdown activity state
2173 * Wait-for-SIPI activity state
2174 * PAUSE-loop exiting (Westmere and newer)
2175 * EPT-violation #VE (Broadwell and newer)
2176 * Inject event with insn length=0 (Skylake and newer)
2177 * Conceal non-root operation from PT
2178 * Conceal VM exits from PT
2179 * Conceal VM entries from PT
2180 * Enable ENCLS exiting
2181 * Mode-based execute control (XS/XU)
f70c1c06 2182 * TSC scaling (Skylake Server and newer)
0723cc8a
PB		 2183 * GPA translation for PT (IceLake and newer)
2184 * User wait and pause
2185 * ENCLV exiting
2186 * Load IA32_RTIT_CTL
2187 * Clear IA32_RTIT_CTL
2188 * Advanced VM-exit information for EPT violations
2189 * Sub-page write permissions
2190 * PT in VMX operation
2191 */
2192
e11fd689 2193static const X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 2194 {
2195 .name = "qemu64",
3046bb5d 2196 .level = 0xd,
99b88a17 2197 .vendor = CPUID_VENDOR_AMD,
b7c29017
DB		 2198 .family = 15,
2199 .model = 107,
2200 .stepping = 1,
0514ef2f 2201 .features[FEAT_1_EDX] =
27861ecc 2202 PPRO_FEATURES |
c6dc6f63 2203 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 2204 CPUID_PSE36,
0514ef2f 2205 .features[FEAT_1_ECX] =
6aa91e4a 2206 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 2207 .features[FEAT_8000_0001_EDX] =
c6dc6f63 2208 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2209 .features[FEAT_8000_0001_ECX] =
71195672 2210 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 2211 .xlevel = 0x8000000A,
9cf2cc3d 2212 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2213 },
2214 {
2215 .name = "phenom",
2216 .level = 5,
99b88a17 2217 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2218 .family = 16,
2219 .model = 2,
2220 .stepping = 3,
b9fc20bc 2221 /* Missing: CPUID_HT */
0514ef2f 2222 .features[FEAT_1_EDX] =
27861ecc 2223 PPRO_FEATURES |
c6dc6f63 2224 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 2225 CPUID_PSE36 | CPUID_VME,
0514ef2f 2226 .features[FEAT_1_ECX] =
27861ecc 2227 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 2228 CPUID_EXT_POPCNT,
0514ef2f 2229 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2230 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
2231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 2232 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 2233 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2234 CPUID_EXT3_CR8LEG,
2235 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2236 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 2237 .features[FEAT_8000_0001_ECX] =
27861ecc 2238 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 2239 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 2240 /* Missing: CPUID_SVM_LBRV */
0514ef2f 2241 .features[FEAT_SVM] =
b9fc20bc 2242 CPUID_SVM_NPT,
c6dc6f63
AP		 2243 .xlevel = 0x8000001A,
2244 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
2245 },
2246 {
2247 .name = "core2duo",
2248 .level = 10,
99b88a17 2249 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2250 .family = 6,
2251 .model = 15,
2252 .stepping = 11,
b9fc20bc 2253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2254 .features[FEAT_1_EDX] =
27861ecc 2255 PPRO_FEATURES |
c6dc6f63 2256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 2257 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
2258 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 2259 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2260 .features[FEAT_1_ECX] =
27861ecc 2261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 2262 CPUID_EXT_CX16,
0514ef2f 2263 .features[FEAT_8000_0001_EDX] =
27861ecc 2264 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2265 .features[FEAT_8000_0001_ECX] =
27861ecc 2266 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2269 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2271 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2272 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2273 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2274 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2275 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2276 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2277 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2278 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2279 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2280 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2281 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2282 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2283 .features[FEAT_VMX_SECONDARY_CTLS] =
2284 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 2285 .xlevel = 0x80000008,
2286 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
2287 },
2288 {
2289 .name = "kvm64",
3046bb5d 2290 .level = 0xd,
99b88a17 2291 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2292 .family = 15,
2293 .model = 6,
2294 .stepping = 1,
b3a4f0b1 2295 /* Missing: CPUID_HT */
0514ef2f 2296 .features[FEAT_1_EDX] =
b3a4f0b1 2297 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 2298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
2299 CPUID_PSE36,
2300 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 2301 .features[FEAT_1_ECX] =
27861ecc 2302 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 2303 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 2304 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2306 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2307 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2308 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2309 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 2310 .features[FEAT_8000_0001_ECX] =
27861ecc 2311 0,
0723cc8a
PB		 2312 /* VMX features from Cedar Mill/Prescott */
2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2314 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2315 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2316 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2317 VMX_PIN_BASED_NMI_EXITING,
2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 2326 .xlevel = 0x80000008,
2327 .model_id = "Common KVM processor"
2328 },
c6dc6f63
AP		 2329 {
2330 .name = "qemu32",
2331 .level = 4,
99b88a17 2332 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2333 .family = 6,
f8e6a11a 2334 .model = 6,
c6dc6f63 2335 .stepping = 3,
0514ef2f 2336 .features[FEAT_1_EDX] =
27861ecc 2337 PPRO_FEATURES,
0514ef2f 2338 .features[FEAT_1_ECX] =
6aa91e4a 2339 CPUID_EXT_SSE3,
58012d66 2340 .xlevel = 0x80000004,
9cf2cc3d 2341 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 2342 },
eafaf1e5
AP		 2343 {
2344 .name = "kvm32",
2345 .level = 5,
99b88a17 2346 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 2347 .family = 15,
2348 .model = 6,
2349 .stepping = 1,
0514ef2f 2350 .features[FEAT_1_EDX] =
b3a4f0b1 2351 PPRO_FEATURES | CPUID_VME |
eafaf1e5 2352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 2353 .features[FEAT_1_ECX] =
27861ecc 2354 CPUID_EXT_SSE3,
0514ef2f 2355 .features[FEAT_8000_0001_ECX] =
27861ecc 2356 0,
0723cc8a
PB		 2357 /* VMX features from Yonah */
2358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2359 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2360 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2361 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2362 VMX_PIN_BASED_NMI_EXITING,
2363 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2364 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2365 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2366 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2367 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2368 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2369 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 2370 .xlevel = 0x80000008,
2371 .model_id = "Common 32-bit KVM processor"
2372 },
c6dc6f63
AP		 2373 {
2374 .name = "coreduo",
2375 .level = 10,
99b88a17 2376 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2377 .family = 6,
2378 .model = 14,
2379 .stepping = 8,
b9fc20bc 2380 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2381 .features[FEAT_1_EDX] =
27861ecc 2382 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 2383 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2384 CPUID_SS,
2385 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 2386 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 2387 .features[FEAT_1_ECX] =
e93abc14 2388 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 2389 .features[FEAT_8000_0001_EDX] =
27861ecc 2390 CPUID_EXT2_NX,
0723cc8a
PB		 2391 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2392 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2393 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2394 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2395 VMX_PIN_BASED_NMI_EXITING,
2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2402 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 2403 .xlevel = 0x80000008,
2404 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2405 },
2406 {
2407 .name = "486",
58012d66 2408 .level = 1,
99b88a17 2409 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2410 .family = 4,
b2a856d9 2411 .model = 8,
c6dc6f63 2412 .stepping = 0,
0514ef2f 2413 .features[FEAT_1_EDX] =
27861ecc 2414 I486_FEATURES,
c6dc6f63 2415 .xlevel = 0,
807e9869 2416 .model_id = "",
c6dc6f63
AP		 2417 },
2418 {
2419 .name = "pentium",
2420 .level = 1,
99b88a17 2421 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2422 .family = 5,
2423 .model = 4,
2424 .stepping = 3,
0514ef2f 2425 .features[FEAT_1_EDX] =
27861ecc 2426 PENTIUM_FEATURES,
c6dc6f63 2427 .xlevel = 0,
807e9869 2428 .model_id = "",
c6dc6f63
AP		 2429 },
2430 {
2431 .name = "pentium2",
2432 .level = 2,
99b88a17 2433 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2434 .family = 6,
2435 .model = 5,
2436 .stepping = 2,
0514ef2f 2437 .features[FEAT_1_EDX] =
27861ecc 2438 PENTIUM2_FEATURES,
c6dc6f63 2439 .xlevel = 0,
807e9869 2440 .model_id = "",
c6dc6f63
AP		 2441 },
2442 {
2443 .name = "pentium3",
3046bb5d 2444 .level = 3,
99b88a17 2445 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2446 .family = 6,
2447 .model = 7,
2448 .stepping = 3,
0514ef2f 2449 .features[FEAT_1_EDX] =
27861ecc 2450 PENTIUM3_FEATURES,
c6dc6f63 2451 .xlevel = 0,
807e9869 2452 .model_id = "",
c6dc6f63
AP		 2453 },
2454 {
2455 .name = "athlon",
2456 .level = 2,
99b88a17 2457 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2458 .family = 6,
2459 .model = 2,
2460 .stepping = 3,
0514ef2f 2461 .features[FEAT_1_EDX] =
27861ecc 2462 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2463 CPUID_MCA,
0514ef2f 2464 .features[FEAT_8000_0001_EDX] =
60032ac0 2465 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2466 .xlevel = 0x80000008,
9cf2cc3d 2467 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2468 },
2469 {
2470 .name = "n270",
3046bb5d 2471 .level = 10,
99b88a17 2472 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2473 .family = 6,
2474 .model = 28,
2475 .stepping = 2,
b9fc20bc 2476 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2477 .features[FEAT_1_EDX] =
27861ecc 2478 PPRO_FEATURES |
b9fc20bc
EH		 2479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2480 CPUID_ACPI | CPUID_SS,
c6dc6f63 2481 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2482 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2483 * CPUID_EXT_XTPR */
0514ef2f 2484 .features[FEAT_1_ECX] =
27861ecc 2485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2486 CPUID_EXT_MOVBE,
0514ef2f 2487 .features[FEAT_8000_0001_EDX] =
60032ac0 2488 CPUID_EXT2_NX,
0514ef2f 2489 .features[FEAT_8000_0001_ECX] =
27861ecc 2490 CPUID_EXT3_LAHF_LM,
3046bb5d 2491 .xlevel = 0x80000008,
c6dc6f63
AP		 2492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2493 },
3eca4642
EH		 2494 {
2495 .name = "Conroe",
3046bb5d 2496 .level = 10,
99b88a17 2497 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2498 .family = 6,
ffce9ebb 2499 .model = 15,
3eca4642 2500 .stepping = 3,
0514ef2f 2501 .features[FEAT_1_EDX] =
b3a4f0b1 2502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2506 CPUID_DE | CPUID_FP87,
0514ef2f 2507 .features[FEAT_1_ECX] =
27861ecc 2508 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2509 .features[FEAT_8000_0001_EDX] =
27861ecc 2510 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2511 .features[FEAT_8000_0001_ECX] =
27861ecc 2512 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2513 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2514 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2515 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2529 .features[FEAT_VMX_SECONDARY_CTLS] =
2530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2531 .xlevel = 0x80000008,
3eca4642
EH		 2532 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2533 },
2534 {
2535 .name = "Penryn",
3046bb5d 2536 .level = 10,
99b88a17 2537 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2538 .family = 6,
ffce9ebb 2539 .model = 23,
3eca4642 2540 .stepping = 3,
0514ef2f 2541 .features[FEAT_1_EDX] =
b3a4f0b1 2542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2546 CPUID_DE | CPUID_FP87,
0514ef2f 2547 .features[FEAT_1_ECX] =
27861ecc 2548 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2549 CPUID_EXT_SSE3,
0514ef2f 2550 .features[FEAT_8000_0001_EDX] =
27861ecc 2551 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2552 .features[FEAT_8000_0001_ECX] =
27861ecc 2553 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2555 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2556 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2572 .features[FEAT_VMX_SECONDARY_CTLS] =
2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2574 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2575 .xlevel = 0x80000008,
3eca4642
EH		 2576 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2577 },
2578 {
2579 .name = "Nehalem",
3046bb5d 2580 .level = 11,
99b88a17 2581 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2582 .family = 6,
ffce9ebb 2583 .model = 26,
3eca4642 2584 .stepping = 3,
0514ef2f 2585 .features[FEAT_1_EDX] =
b3a4f0b1 2586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2590 CPUID_DE | CPUID_FP87,
0514ef2f 2591 .features[FEAT_1_ECX] =
27861ecc 2592 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2594 .features[FEAT_8000_0001_EDX] =
27861ecc 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2596 .features[FEAT_8000_0001_ECX] =
27861ecc 2597 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2599 MSR_VMX_BASIC_TRUE_CTLS,
2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2610 .features[FEAT_VMX_EXIT_CTLS] =
2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2617 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2618 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2619 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2620 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2621 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2622 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2623 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2624 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2625 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2626 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2627 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2628 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2629 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2630 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2631 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2632 .features[FEAT_VMX_SECONDARY_CTLS] =
2633 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2634 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2635 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2636 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2637 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2638 .xlevel = 0x80000008,
3eca4642 2639 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2640 .versions = (X86CPUVersionDefinition[]) {
2641 { .version = 1 },
2642 {
2643 .version = 2,
53db89d9 2644 .alias = "Nehalem-IBRS",
d86a7088
EH		 2645 .props = (PropValue[]) {
2646 { "spec-ctrl", "on" },
2647 { "model-id",
2648 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2649 { /* end of list */ }
2650 }
2651 },
2652 { /* end of list */ }
2653 }
3eca4642
EH		 2654 },
2655 {
2656 .name = "Westmere",
2657 .level = 11,
99b88a17 2658 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2659 .family = 6,
2660 .model = 44,
2661 .stepping = 1,
0514ef2f 2662 .features[FEAT_1_EDX] =
b3a4f0b1 2663 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2664 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2665 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2666 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2667 CPUID_DE | CPUID_FP87,
0514ef2f 2668 .features[FEAT_1_ECX] =
27861ecc 2669 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2670 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2671 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2672 .features[FEAT_8000_0001_EDX] =
27861ecc 2673 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2674 .features[FEAT_8000_0001_ECX] =
27861ecc 2675 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2676 .features[FEAT_6_EAX] =
2677 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2678 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2679 MSR_VMX_BASIC_TRUE_CTLS,
2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2682 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2683 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2684 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2685 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2686 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2687 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2690 .features[FEAT_VMX_EXIT_CTLS] =
2691 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2692 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2693 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2694 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2695 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2696 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2697 MSR_VMX_MISC_STORE_LMA,
2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2699 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2700 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2701 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2705 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2706 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2707 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2708 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2709 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2711 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2713 .features[FEAT_VMX_SECONDARY_CTLS] =
2714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2715 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2716 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2719 .xlevel = 0x80000008,
3eca4642 2720 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2721 .versions = (X86CPUVersionDefinition[]) {
2722 { .version = 1 },
2723 {
2724 .version = 2,
53db89d9 2725 .alias = "Westmere-IBRS",
d86a7088
EH		 2726 .props = (PropValue[]) {
2727 { "spec-ctrl", "on" },
2728 { "model-id",
2729 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2730 { /* end of list */ }
2731 }
2732 },
2733 { /* end of list */ }
2734 }
3eca4642
EH		 2735 },
2736 {
2737 .name = "SandyBridge",
2738 .level = 0xd,
99b88a17 2739 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2740 .family = 6,
2741 .model = 42,
2742 .stepping = 1,
0514ef2f 2743 .features[FEAT_1_EDX] =
b3a4f0b1 2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2748 CPUID_DE | CPUID_FP87,
0514ef2f 2749 .features[FEAT_1_ECX] =
27861ecc 2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2751 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2752 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2753 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2754 CPUID_EXT_SSE3,
0514ef2f 2755 .features[FEAT_8000_0001_EDX] =
27861ecc 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2757 CPUID_EXT2_SYSCALL,
0514ef2f 2758 .features[FEAT_8000_0001_ECX] =
27861ecc 2759 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2760 .features[FEAT_XSAVE] =
2761 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2762 .features[FEAT_6_EAX] =
2763 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2764 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2765 MSR_VMX_BASIC_TRUE_CTLS,
2766 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2769 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2771 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2773 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2776 .features[FEAT_VMX_EXIT_CTLS] =
2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2779 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2780 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2782 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2783 MSR_VMX_MISC_STORE_LMA,
2784 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2785 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2787 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2788 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2789 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2790 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2791 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2792 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2793 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2794 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2796 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2799 .features[FEAT_VMX_SECONDARY_CTLS] =
2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2801 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2802 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2804 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2805 .xlevel = 0x80000008,
3eca4642 2806 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2807 .versions = (X86CPUVersionDefinition[]) {
2808 { .version = 1 },
2809 {
2810 .version = 2,
53db89d9 2811 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2812 .props = (PropValue[]) {
2813 { "spec-ctrl", "on" },
2814 { "model-id",
2815 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2816 { /* end of list */ }
2817 }
2818 },
2819 { /* end of list */ }
2820 }
3eca4642 2821 },
2f9ac42a
PB		 2822 {
2823 .name = "IvyBridge",
2824 .level = 0xd,
2825 .vendor = CPUID_VENDOR_INTEL,
2826 .family = 6,
2827 .model = 58,
2828 .stepping = 9,
2829 .features[FEAT_1_EDX] =
2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2834 CPUID_DE | CPUID_FP87,
2835 .features[FEAT_1_ECX] =
2836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2838 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2839 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2840 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2841 .features[FEAT_7_0_EBX] =
2842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2843 CPUID_7_0_EBX_ERMS,
2844 .features[FEAT_8000_0001_EDX] =
2845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2846 CPUID_EXT2_SYSCALL,
2847 .features[FEAT_8000_0001_ECX] =
2848 CPUID_EXT3_LAHF_LM,
2849 .features[FEAT_XSAVE] =
2850 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2851 .features[FEAT_6_EAX] =
2852 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2853 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2854 MSR_VMX_BASIC_TRUE_CTLS,
2855 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2856 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2857 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2858 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2859 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2860 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2861 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2862 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2863 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2865 .features[FEAT_VMX_EXIT_CTLS] =
2866 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2867 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2868 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2869 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2870 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2872 MSR_VMX_MISC_STORE_LMA,
2873 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2874 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2875 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2885 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2886 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2887 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2888 .features[FEAT_VMX_SECONDARY_CTLS] =
2889 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2890 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2891 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2892 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2893 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2894 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2895 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2896 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2897 .xlevel = 0x80000008,
2f9ac42a 2898 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2899 .versions = (X86CPUVersionDefinition[]) {
2900 { .version = 1 },
2901 {
2902 .version = 2,
53db89d9 2903 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2904 .props = (PropValue[]) {
2905 { "spec-ctrl", "on" },
2906 { "model-id",
2907 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2908 { /* end of list */ }
2909 }
2910 },
2911 { /* end of list */ }
2912 }
2f9ac42a 2913 },
ac96c413 2914 {
37507094
EH		 2915 .name = "Haswell",
2916 .level = 0xd,
99b88a17 2917 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2918 .family = 6,
2919 .model = 60,
ec56a4a7 2920 .stepping = 4,
0514ef2f 2921 .features[FEAT_1_EDX] =
b3a4f0b1 2922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2926 CPUID_DE | CPUID_FP87,
0514ef2f 2927 .features[FEAT_1_ECX] =
27861ecc 2928 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2929 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2932 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2933 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2934 .features[FEAT_8000_0001_EDX] =
27861ecc 2935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2936 CPUID_EXT2_SYSCALL,
0514ef2f 2937 .features[FEAT_8000_0001_ECX] =
becb6667 2938 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2939 .features[FEAT_7_0_EBX] =
27861ecc 2940 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2941 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2942 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2943 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2944 .features[FEAT_XSAVE] =
2945 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2946 .features[FEAT_6_EAX] =
2947 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2948 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2949 MSR_VMX_BASIC_TRUE_CTLS,
2950 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2952 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2953 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2954 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2955 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2956 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2957 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2960 .features[FEAT_VMX_EXIT_CTLS] =
2961 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2962 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2963 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2964 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2965 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2967 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2969 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2970 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2975 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2976 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2977 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2978 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2979 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2981 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2982 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2983 .features[FEAT_VMX_SECONDARY_CTLS] =
2984 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2985 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2986 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2987 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2988 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2989 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2990 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2991 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2992 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2993 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2994 .xlevel = 0x80000008,
37507094 2995 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2996 .versions = (X86CPUVersionDefinition[]) {
2997 { .version = 1 },
2998 {
2999 .version = 2,
53db89d9 3000 .alias = "Haswell-noTSX",
d86a7088
EH		 3001 .props = (PropValue[]) {
3002 { "hle", "off" },
3003 { "rtm", "off" },
3004 { "stepping", "1" },
3005 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
3006 { /* end of list */ }
3007 },
3008 },
3009 {
3010 .version = 3,
53db89d9 3011 .alias = "Haswell-IBRS",
d86a7088
EH		 3012 .props = (PropValue[]) {
3013 /* Restore TSX features removed by -v2 above */
3014 { "hle", "on" },
3015 { "rtm", "on" },
3016 /*
3017 * Haswell and Haswell-IBRS had stepping=4 in
3018 * QEMU 4.0 and older
3019 */
3020 { "stepping", "4" },
3021 { "spec-ctrl", "on" },
3022 { "model-id",
3023 "Intel Core Processor (Haswell, IBRS)" },
3024 { /* end of list */ }
3025 }
3026 },
3027 {
3028 .version = 4,
53db89d9 3029 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 3030 .props = (PropValue[]) {
3031 { "hle", "off" },
3032 { "rtm", "off" },
3033 /* spec-ctrl was already enabled by -v3 above */
3034 { "stepping", "1" },
3035 { "model-id",
3036 "Intel Core Processor (Haswell, no TSX, IBRS)" },
3037 { /* end of list */ }
3038 }
3039 },
3040 { /* end of list */ }
3041 }
37507094 3042 },
ece01354
EH		 3043 {
3044 .name = "Broadwell",
3045 .level = 0xd,
3046 .vendor = CPUID_VENDOR_INTEL,
3047 .family = 6,
3048 .model = 61,
3049 .stepping = 2,
3050 .features[FEAT_1_EDX] =
b3a4f0b1 3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3055 CPUID_DE | CPUID_FP87,
3056 .features[FEAT_1_ECX] =
3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 3063 .features[FEAT_8000_0001_EDX] =
3064 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3065 CPUID_EXT2_SYSCALL,
3066 .features[FEAT_8000_0001_ECX] =
becb6667 3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 3068 .features[FEAT_7_0_EBX] =
3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 3073 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 3074 .features[FEAT_XSAVE] =
3075 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 3076 .features[FEAT_6_EAX] =
3077 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3079 MSR_VMX_BASIC_TRUE_CTLS,
3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3090 .features[FEAT_VMX_EXIT_CTLS] =
3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3097 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3113 .features[FEAT_VMX_SECONDARY_CTLS] =
3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3119 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3120 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3121 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3122 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3123 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3124 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 3125 .xlevel = 0x80000008,
ece01354 3126 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 3127 .versions = (X86CPUVersionDefinition[]) {
3128 { .version = 1 },
3129 {
3130 .version = 2,
53db89d9 3131 .alias = "Broadwell-noTSX",
d86a7088
EH		 3132 .props = (PropValue[]) {
3133 { "hle", "off" },
3134 { "rtm", "off" },
3135 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3136 { /* end of list */ }
3137 },
3138 },
3139 {
3140 .version = 3,
53db89d9 3141 .alias = "Broadwell-IBRS",
d86a7088
EH		 3142 .props = (PropValue[]) {
3143 /* Restore TSX features removed by -v2 above */
3144 { "hle", "on" },
3145 { "rtm", "on" },
3146 { "spec-ctrl", "on" },
3147 { "model-id",
3148 "Intel Core Processor (Broadwell, IBRS)" },
3149 { /* end of list */ }
3150 }
3151 },
3152 {
3153 .version = 4,
53db89d9 3154 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 3155 .props = (PropValue[]) {
3156 { "hle", "off" },
3157 { "rtm", "off" },
3158 /* spec-ctrl was already enabled by -v3 above */
3159 { "model-id",
3160 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
3161 { /* end of list */ }
3162 }
3163 },
3164 { /* end of list */ }
3165 }
ece01354 3166 },
f6f949e9
EH		 3167 {
3168 .name = "Skylake-Client",
3169 .level = 0xd,
3170 .vendor = CPUID_VENDOR_INTEL,
3171 .family = 6,
3172 .model = 94,
3173 .stepping = 3,
3174 .features[FEAT_1_EDX] =
3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3179 CPUID_DE | CPUID_FP87,
3180 .features[FEAT_1_ECX] =
3181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3187 .features[FEAT_8000_0001_EDX] =
3188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3189 CPUID_EXT2_SYSCALL,
3190 .features[FEAT_8000_0001_ECX] =
3191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3192 .features[FEAT_7_0_EBX] =
3193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3196 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3197 CPUID_7_0_EBX_SMAP,
7bde6b18 3198 /* XSAVES is added in version 4 */
f6f949e9
EH		 3199 .features[FEAT_XSAVE] =
3200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3201 CPUID_XSAVE_XGETBV1,
3202 .features[FEAT_6_EAX] =
3203 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3204 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3206 MSR_VMX_BASIC_TRUE_CTLS,
3207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3217 .features[FEAT_VMX_EXIT_CTLS] =
3218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3224 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3238 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3240 .features[FEAT_VMX_SECONDARY_CTLS] =
3241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3244 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3245 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3248 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 3249 .xlevel = 0x80000008,
3250 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 3251 .versions = (X86CPUVersionDefinition[]) {
3252 { .version = 1 },
3253 {
3254 .version = 2,
53db89d9 3255 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 3256 .props = (PropValue[]) {
3257 { "spec-ctrl", "on" },
3258 { "model-id",
3259 "Intel Core Processor (Skylake, IBRS)" },
3260 { /* end of list */ }
3261 }
3262 },
9ab2237f
EH		 3263 {
3264 .version = 3,
02fa60d1 3265 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 3266 .props = (PropValue[]) {
3267 { "hle", "off" },
3268 { "rtm", "off" },
673b0add
KC		 3269 { "model-id",
3270 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3271 { /* end of list */ }
3272 }
3273 },
7bde6b18
VK		 3274 {
3275 .version = 4,
3276 .note = "IBRS, XSAVES, no TSX",
3277 .props = (PropValue[]) {
3278 { "xsaves", "on" },
3279 { "vmx-xsaves", "on" },
3280 { /* end of list */ }
3281 }
3282 },
d86a7088
EH		 3283 { /* end of list */ }
3284 }
f6f949e9 3285 },
53f9a6f4
BF		 3286 {
3287 .name = "Skylake-Server",
3288 .level = 0xd,
3289 .vendor = CPUID_VENDOR_INTEL,
3290 .family = 6,
3291 .model = 85,
3292 .stepping = 4,
3293 .features[FEAT_1_EDX] =
3294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3298 CPUID_DE | CPUID_FP87,
3299 .features[FEAT_1_ECX] =
3300 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3301 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3302 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3303 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3304 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3305 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3306 .features[FEAT_8000_0001_EDX] =
3307 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3308 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3309 .features[FEAT_8000_0001_ECX] =
3310 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3311 .features[FEAT_7_0_EBX] =
3312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3313 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3314 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3315 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3316 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 3317 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 3319 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 3320 .features[FEAT_7_0_ECX] =
3321 CPUID_7_0_ECX_PKU,
7bde6b18 3322 /* XSAVES is added in version 5 */
53f9a6f4
BF		 3323 .features[FEAT_XSAVE] =
3324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3325 CPUID_XSAVE_XGETBV1,
3326 .features[FEAT_6_EAX] =
3327 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3330 MSR_VMX_BASIC_TRUE_CTLS,
3331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3341 .features[FEAT_VMX_EXIT_CTLS] =
3342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3362 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3364 .features[FEAT_VMX_SECONDARY_CTLS] =
3365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3374 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 3375 .xlevel = 0x80000008,
3376 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 3377 .versions = (X86CPUVersionDefinition[]) {
3378 { .version = 1 },
3379 {
3380 .version = 2,
53db89d9 3381 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 3382 .props = (PropValue[]) {
3383 /* clflushopt was not added to Skylake-Server-IBRS */
3384 /* TODO: add -v3 including clflushopt */
3385 { "clflushopt", "off" },
3386 { "spec-ctrl", "on" },
3387 { "model-id",
3388 "Intel Xeon Processor (Skylake, IBRS)" },
3389 { /* end of list */ }
3390 }
3391 },
9ab2237f
EH		 3392 {
3393 .version = 3,
02fa60d1 3394 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 3395 .props = (PropValue[]) {
3396 { "hle", "off" },
3397 { "rtm", "off" },
673b0add
KC		 3398 { "model-id",
3399 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 3400 { /* end of list */ }
3401 }
3402 },
644e3c5d
CQ		 3403 {
3404 .version = 4,
3405 .props = (PropValue[]) {
3406 { "vmx-eptp-switching", "on" },
3407 { /* end of list */ }
3408 }
3409 },
7bde6b18
VK		 3410 {
3411 .version = 5,
3412 .note = "IBRS, XSAVES, EPT switching, no TSX",
3413 .props = (PropValue[]) {
3414 { "xsaves", "on" },
3415 { "vmx-xsaves", "on" },
3416 { /* end of list */ }
3417 }
3418 },
d86a7088
EH		 3419 { /* end of list */ }
3420 }
53f9a6f4 3421 },
c7a88b52
TX		 3422 {
3423 .name = "Cascadelake-Server",
3424 .level = 0xd,
3425 .vendor = CPUID_VENDOR_INTEL,
3426 .family = 6,
3427 .model = 85,
b0a19803 3428 .stepping = 6,
c7a88b52
TX		 3429 .features[FEAT_1_EDX] =
3430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3434 CPUID_DE | CPUID_FP87,
3435 .features[FEAT_1_ECX] =
3436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3442 .features[FEAT_8000_0001_EDX] =
3443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3445 .features[FEAT_8000_0001_ECX] =
3446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3447 .features[FEAT_7_0_EBX] =
3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3456 .features[FEAT_7_0_ECX] =
bb4928c7 3457 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3458 CPUID_7_0_ECX_AVX512VNNI,
3459 .features[FEAT_7_0_EDX] =
3460 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3461 /* XSAVES is added in version 5 */
c7a88b52
TX		 3462 .features[FEAT_XSAVE] =
3463 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3464 CPUID_XSAVE_XGETBV1,
3465 .features[FEAT_6_EAX] =
3466 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3467 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3469 MSR_VMX_BASIC_TRUE_CTLS,
3470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3480 .features[FEAT_VMX_EXIT_CTLS] =
3481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3501 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3503 .features[FEAT_VMX_SECONDARY_CTLS] =
3504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3513 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3514 .xlevel = 0x80000008,
3515 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3516 .versions = (X86CPUVersionDefinition[]) {
3517 { .version = 1 },
3518 { .version = 2,
47f0d11d 3519 .note = "ARCH_CAPABILITIES",
fd63c6d1
EH		 3520 .props = (PropValue[]) {
3521 { "arch-capabilities", "on" },
3522 { "rdctl-no", "on" },
3523 { "ibrs-all", "on" },
3524 { "skip-l1dfl-vmentry", "on" },
3525 { "mds-no", "on" },
3526 { /* end of list */ }
3527 },
3528 },
9ab2237f 3529 { .version = 3,
02fa60d1 3530 .alias = "Cascadelake-Server-noTSX",
47f0d11d 3531 .note = "ARCH_CAPABILITIES, no TSX",
9ab2237f
EH		 3532 .props = (PropValue[]) {
3533 { "hle", "off" },
3534 { "rtm", "off" },
3535 { /* end of list */ }
3536 },
3537 },
644e3c5d
CQ		 3538 { .version = 4,
3539 .note = "ARCH_CAPABILITIES, no TSX",
3540 .props = (PropValue[]) {
3541 { "vmx-eptp-switching", "on" },
3542 { /* end of list */ }
3543 },
3544 },
7bde6b18
VK		 3545 { .version = 5,
3546 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3547 .props = (PropValue[]) {
3548 { "xsaves", "on" },
3549 { "vmx-xsaves", "on" },
3550 { /* end of list */ }
3551 },
3552 },
fd63c6d1
EH		 3553 { /* end of list */ }
3554 }
c7a88b52 3555 },
22a866b6
CZ		 3556 {
3557 .name = "Cooperlake",
3558 .level = 0xd,
3559 .vendor = CPUID_VENDOR_INTEL,
3560 .family = 6,
3561 .model = 85,
3562 .stepping = 10,
3563 .features[FEAT_1_EDX] =
3564 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3568 CPUID_DE | CPUID_FP87,
3569 .features[FEAT_1_ECX] =
3570 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3571 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3572 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3573 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3574 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3575 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3576 .features[FEAT_8000_0001_EDX] =
3577 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3578 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3579 .features[FEAT_8000_0001_ECX] =
3580 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3581 .features[FEAT_7_0_EBX] =
3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3590 .features[FEAT_7_0_ECX] =
3591 CPUID_7_0_ECX_PKU |
3592 CPUID_7_0_ECX_AVX512VNNI,
3593 .features[FEAT_7_0_EDX] =
3594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3595 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3596 .features[FEAT_ARCH_CAPABILITIES] =
3597 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3598 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3599 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6 3600 .features[FEAT_7_1_EAX] =
f429dbf8 3601 CPUID_7_1_EAX_AVX512_BF16,
7bde6b18 3602 /* XSAVES is added in version 2 */
22a866b6
CZ		 3603 .features[FEAT_XSAVE] =
3604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3605 CPUID_XSAVE_XGETBV1,
3606 .features[FEAT_6_EAX] =
3607 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3608 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3610 MSR_VMX_BASIC_TRUE_CTLS,
3611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3621 .features[FEAT_VMX_EXIT_CTLS] =
3622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3642 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3644 .features[FEAT_VMX_SECONDARY_CTLS] =
3645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3656 .xlevel = 0x80000008,
3657 .model_id = "Intel Xeon Processor (Cooperlake)",
7bde6b18
VK		 3658 .versions = (X86CPUVersionDefinition[]) {
3659 { .version = 1 },
3660 { .version = 2,
3661 .note = "XSAVES",
3662 .props = (PropValue[]) {
3663 { "xsaves", "on" },
3664 { "vmx-xsaves", "on" },
3665 { /* end of list */ }
3666 },
3667 },
3668 { /* end of list */ }
3669 }
22a866b6 3670 },
8a11c62d
RH		 3671 {
3672 .name = "Icelake-Server",
3673 .level = 0xd,
3674 .vendor = CPUID_VENDOR_INTEL,
3675 .family = 6,
3676 .model = 134,
3677 .stepping = 0,
3678 .features[FEAT_1_EDX] =
3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3683 CPUID_DE | CPUID_FP87,
3684 .features[FEAT_1_ECX] =
3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3691 .features[FEAT_8000_0001_EDX] =
3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3694 .features[FEAT_8000_0001_ECX] =
3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3696 .features[FEAT_8000_0008_EBX] =
3697 CPUID_8000_0008_EBX_WBNOINVD,
3698 .features[FEAT_7_0_EBX] =
3699 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3700 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3701 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3702 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3703 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3704 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3705 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3706 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3707 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3708 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3709 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3710 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3711 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3712 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3713 .features[FEAT_7_0_EDX] =
76e5a4d5 3714 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 3715 /* XSAVES is added in version 5 */
8a11c62d
RH		 3716 .features[FEAT_XSAVE] =
3717 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3718 CPUID_XSAVE_XGETBV1,
3719 .features[FEAT_6_EAX] =
3720 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3721 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3723 MSR_VMX_BASIC_TRUE_CTLS,
3724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3734 .features[FEAT_VMX_EXIT_CTLS] =
3735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3755 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3757 .features[FEAT_VMX_SECONDARY_CTLS] =
3758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3767 .xlevel = 0x80000008,
3768 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3769 .versions = (X86CPUVersionDefinition[]) {
3770 { .version = 1 },
3771 {
3772 .version = 2,
47f0d11d 3773 .note = "no TSX",
02fa60d1 3774 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3775 .props = (PropValue[]) {
3776 { "hle", "off" },
3777 { "rtm", "off" },
3778 { /* end of list */ }
3779 },
3780 },
d965dc35
XL		 3781 {
3782 .version = 3,
3783 .props = (PropValue[]) {
3784 { "arch-capabilities", "on" },
3785 { "rdctl-no", "on" },
3786 { "ibrs-all", "on" },
3787 { "skip-l1dfl-vmentry", "on" },
3788 { "mds-no", "on" },
3789 { "pschange-mc-no", "on" },
3790 { "taa-no", "on" },
3791 { /* end of list */ }
3792 },
3793 },
e0013791
CQ		 3794 {
3795 .version = 4,
3796 .props = (PropValue[]) {
3797 { "sha-ni", "on" },
3798 { "avx512ifma", "on" },
3799 { "rdpid", "on" },
3800 { "fsrm", "on" },
3801 { "vmx-rdseed-exit", "on" },
3802 { "vmx-pml", "on" },
3803 { "vmx-eptp-switching", "on" },
3804 { "model", "106" },
3805 { /* end of list */ }
3806 },
3807 },
7bde6b18
VK		 3808 {
3809 .version = 5,
3810 .note = "XSAVES",
3811 .props = (PropValue[]) {
3812 { "xsaves", "on" },
3813 { "vmx-xsaves", "on" },
3814 { /* end of list */ }
3815 },
3816 },
12cab535
VK		 3817 {
3818 .version = 6,
3819 .note = "5-level EPT",
3820 .props = (PropValue[]) {
3821 { "vmx-page-walk-5", "on" },
3822 { /* end of list */ }
3823 },
3824 },
9ab2237f
EH		 3825 { /* end of list */ }
3826 }
8a11c62d 3827 },
7eb061b0
WL		 3828 {
3829 .name = "SapphireRapids",
3830 .level = 0x20,
3831 .vendor = CPUID_VENDOR_INTEL,
3832 .family = 6,
3833 .model = 143,
3834 .stepping = 4,
3835 /*
3836 * please keep the ascending order so that we can have a clear view of
3837 * bit position of each feature.
3838 */
3839 .features[FEAT_1_EDX] =
3840 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3841 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3842 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3843 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3844 CPUID_SSE | CPUID_SSE2,
3845 .features[FEAT_1_ECX] =
3846 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
3847 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
3848 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3849 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
3850 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3851 .features[FEAT_8000_0001_EDX] =
3852 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3853 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3854 .features[FEAT_8000_0001_ECX] =
3855 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
3856 .features[FEAT_8000_0008_EBX] =
3857 CPUID_8000_0008_EBX_WBNOINVD,
3858 .features[FEAT_7_0_EBX] =
3859 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
3860 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
3861 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
3862 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3863 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
3864 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
3865 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
3866 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
3867 .features[FEAT_7_0_ECX] =
3868 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3869 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3870 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3871 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3872 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
3873 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
3874 .features[FEAT_7_0_EDX] =
3875 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
3876 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
3877 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
3878 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
3879 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3880 .features[FEAT_ARCH_CAPABILITIES] =
3881 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3882 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3883 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3884 .features[FEAT_XSAVE] =
3885 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3886 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
3887 .features[FEAT_6_EAX] =
3888 CPUID_6_EAX_ARAT,
3889 .features[FEAT_7_1_EAX] =
3890 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
3891 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
3892 .features[FEAT_VMX_BASIC] =
3893 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
3894 .features[FEAT_VMX_ENTRY_CTLS] =
3895 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
3896 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
3897 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
3898 .features[FEAT_VMX_EPT_VPID_CAPS] =
3899 MSR_VMX_EPT_EXECONLY |
3900 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
3901 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
3902 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
3903 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3904 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3905 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
3906 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
3908 .features[FEAT_VMX_EXIT_CTLS] =
3909 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3910 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
3912 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3913 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3914 .features[FEAT_VMX_MISC] =
3915 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
3916 MSR_VMX_MISC_VMWRITE_VMEXIT,
3917 .features[FEAT_VMX_PINBASED_CTLS] =
3918 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
3919 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
3920 VMX_PIN_BASED_POSTED_INTR,
3921 .features[FEAT_VMX_PROCBASED_CTLS] =
3922 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3923 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3924 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3925 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3926 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3927 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3928 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
3929 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
3930 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3931 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
3932 VMX_CPU_BASED_PAUSE_EXITING |
3933 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3934 .features[FEAT_VMX_SECONDARY_CTLS] =
3935 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3936 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
3937 VMX_SECONDARY_EXEC_RDTSCP |
3938 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3939 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
3940 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3941 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3942 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3943 VMX_SECONDARY_EXEC_RDRAND_EXITING |
3944 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3945 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3946 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
3947 VMX_SECONDARY_EXEC_XSAVES,
3948 .features[FEAT_VMX_VMFUNC] =
3949 MSR_VMX_VMFUNC_EPT_SWITCHING,
3950 .xlevel = 0x80000008,
3951 .model_id = "Intel Xeon Processor (SapphireRapids)",
3952 .versions = (X86CPUVersionDefinition[]) {
3953 { .version = 1 },
3baf7ae6
LW		 3954 {
3955 .version = 2,
3956 .props = (PropValue[]) {
3957 { "sbdr-ssdp-no", "on" },
3958 { "fbsdp-no", "on" },
3959 { "psdp-no", "on" },
3960 { /* end of list */ }
3961 }
3962 },
3963 { /* end of list */ }
3964 }
7eb061b0 3965 },
6d5e9694
TS		 3966 {
3967 .name = "GraniteRapids",
3968 .level = 0x20,
3969 .vendor = CPUID_VENDOR_INTEL,
3970 .family = 6,
3971 .model = 173,
3972 .stepping = 0,
3973 /*
3974 * please keep the ascending order so that we can have a clear view of
3975 * bit position of each feature.
3976 */
3977 .features[FEAT_1_EDX] =
3978 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3979 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3980 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3981 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3982 CPUID_SSE | CPUID_SSE2,
3983 .features[FEAT_1_ECX] =
3984 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
3985 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
3986 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3987 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
3988 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3989 .features[FEAT_8000_0001_EDX] =
3990 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3991 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3992 .features[FEAT_8000_0001_ECX] =
3993 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
3994 .features[FEAT_8000_0008_EBX] =
3995 CPUID_8000_0008_EBX_WBNOINVD,
3996 .features[FEAT_7_0_EBX] =
3997 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
3998 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
3999 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
4000 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
4001 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
4002 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
4003 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
4004 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
4005 .features[FEAT_7_0_ECX] =
4006 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
4007 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
4008 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
4009 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
4010 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
4011 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
4012 .features[FEAT_7_0_EDX] =
4013 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
4014 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
4015 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
4016 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
4017 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
4018 .features[FEAT_ARCH_CAPABILITIES] =
4019 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
4020 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
4021 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO |
4022 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO |
4023 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO,
4024 .features[FEAT_XSAVE] =
4025 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4026 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
4027 .features[FEAT_6_EAX] =
4028 CPUID_6_EAX_ARAT,
4029 .features[FEAT_7_1_EAX] =
4030 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
4031 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC |
4032 CPUID_7_1_EAX_AMX_FP16,
4033 .features[FEAT_7_1_EDX] =
4034 CPUID_7_1_EDX_PREFETCHITI,
4035 .features[FEAT_7_2_EDX] =
4036 CPUID_7_2_EDX_MCDT_NO,
4037 .features[FEAT_VMX_BASIC] =
4038 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
4039 .features[FEAT_VMX_ENTRY_CTLS] =
4040 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
4041 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
4042 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
4043 .features[FEAT_VMX_EPT_VPID_CAPS] =
4044 MSR_VMX_EPT_EXECONLY |
4045 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
4046 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
4047 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
4048 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4049 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4050 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
4051 MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4052 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4053 .features[FEAT_VMX_EXIT_CTLS] =
4054 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4055 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4056 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
4057 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4058 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4059 .features[FEAT_VMX_MISC] =
4060 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
4061 MSR_VMX_MISC_VMWRITE_VMEXIT,
4062 .features[FEAT_VMX_PINBASED_CTLS] =
4063 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
4064 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
4065 VMX_PIN_BASED_POSTED_INTR,
4066 .features[FEAT_VMX_PROCBASED_CTLS] =
4067 VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4068 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4069 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4070 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4071 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4072 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4073 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
4074 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
4075 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4076 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
4077 VMX_CPU_BASED_PAUSE_EXITING |
4078 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4079 .features[FEAT_VMX_SECONDARY_CTLS] =
4080 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4081 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
4082 VMX_SECONDARY_EXEC_RDTSCP |
4083 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4084 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
4085 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4086 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4087 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4088 VMX_SECONDARY_EXEC_RDRAND_EXITING |
4089 VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4090 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4091 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
4092 VMX_SECONDARY_EXEC_XSAVES,
4093 .features[FEAT_VMX_VMFUNC] =
4094 MSR_VMX_VMFUNC_EPT_SWITCHING,
4095 .xlevel = 0x80000008,
4096 .model_id = "Intel Xeon Processor (GraniteRapids)",
4097 .versions = (X86CPUVersionDefinition[]) {
4098 { .version = 1 },
4099 { /* end of list */ },
4100 },
4101 },
8b44d860
TX		 4102 {
4103 .name = "Denverton",
4104 .level = 21,
4105 .vendor = CPUID_VENDOR_INTEL,
4106 .family = 6,
4107 .model = 95,
4108 .stepping = 1,
4109 .features[FEAT_1_EDX] =
4110 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
4111 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
4112 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
4113 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
4114 CPUID_SSE | CPUID_SSE2,
4115 .features[FEAT_1_ECX] =
4116 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
4117 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
4118 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
4119 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
4120 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
4121 .features[FEAT_8000_0001_EDX] =
4122 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
4123 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
4124 .features[FEAT_8000_0001_ECX] =
4125 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
4126 .features[FEAT_7_0_EBX] =
4127 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
4128 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
4129 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
4130 .features[FEAT_7_0_EDX] =
4131 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
4132 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
7bde6b18 4133 /* XSAVES is added in version 3 */
8b44d860
TX		 4134 .features[FEAT_XSAVE] =
4135 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
4136 .features[FEAT_6_EAX] =
4137 CPUID_6_EAX_ARAT,
4138 .features[FEAT_ARCH_CAPABILITIES] =
4139 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 4140 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4141 MSR_VMX_BASIC_TRUE_CTLS,
4142 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4143 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4144 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4145 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4146 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4147 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4148 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4149 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4150 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4151 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4152 .features[FEAT_VMX_EXIT_CTLS] =
4153 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4154 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4155 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4156 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4157 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4158 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4159 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4160 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4161 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4162 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4163 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4164 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4165 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4166 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4167 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4168 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4169 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4170 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4171 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4172 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4173 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4174 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4175 .features[FEAT_VMX_SECONDARY_CTLS] =
4176 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4177 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4178 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4179 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4180 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4181 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4182 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4183 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4184 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4185 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4186 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 4187 .xlevel = 0x80000008,
4188 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 4189 .versions = (X86CPUVersionDefinition[]) {
4190 { .version = 1 },
4191 {
4192 .version = 2,
47f0d11d 4193 .note = "no MPX, no MONITOR",
ab0c942c
TX		 4194 .props = (PropValue[]) {
4195 { "monitor", "off" },
4196 { "mpx", "off" },
4197 { /* end of list */ },
4198 },
4199 },
7bde6b18
VK		 4200 {
4201 .version = 3,
4202 .note = "XSAVES, no MPX, no MONITOR",
4203 .props = (PropValue[]) {
4204 { "xsaves", "on" },
4205 { "vmx-xsaves", "on" },
4206 { /* end of list */ },
4207 },
4208 },
ab0c942c
TX		 4209 { /* end of list */ },
4210 },
8b44d860 4211 },
0b18874b 4212 {
ff656fcd 4213 .name = "Snowridge",
0b18874b
PL		 4214 .level = 27,
4215 .vendor = CPUID_VENDOR_INTEL,
4216 .family = 6,
4217 .model = 134,
4218 .stepping = 1,
4219 .features[FEAT_1_EDX] =
4220 /* missing: CPUID_PN CPUID_IA64 */
4221 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
4222 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
4223 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
4224 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
4225 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
4226 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
4227 CPUID_MMX |
4228 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
4229 .features[FEAT_1_ECX] =
4230 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 4231 CPUID_EXT_SSSE3 |
4232 CPUID_EXT_CX16 |
4233 CPUID_EXT_SSE41 |
4234 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
4235 CPUID_EXT_POPCNT |
4236 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
4237 CPUID_EXT_RDRAND,
4238 .features[FEAT_8000_0001_EDX] =
4239 CPUID_EXT2_SYSCALL |
4240 CPUID_EXT2_NX |
4241 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
4242 CPUID_EXT2_LM,
4243 .features[FEAT_8000_0001_ECX] =
4244 CPUID_EXT3_LAHF_LM |
4245 CPUID_EXT3_3DNOWPREFETCH,
4246 .features[FEAT_7_0_EBX] =
4247 CPUID_7_0_EBX_FSGSBASE |
4248 CPUID_7_0_EBX_SMEP |
4249 CPUID_7_0_EBX_ERMS |
4250 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
4251 CPUID_7_0_EBX_RDSEED |
4252 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4253 CPUID_7_0_EBX_CLWB |
4254 CPUID_7_0_EBX_SHA_NI,
4255 .features[FEAT_7_0_ECX] =
4256 CPUID_7_0_ECX_UMIP |
4257 /* missing bit 5 */
4258 CPUID_7_0_ECX_GFNI |
4259 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
4260 CPUID_7_0_ECX_MOVDIR64B,
4261 .features[FEAT_7_0_EDX] =
4262 CPUID_7_0_EDX_SPEC_CTRL |
4263 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
4264 CPUID_7_0_EDX_CORE_CAPABILITY,
4265 .features[FEAT_CORE_CAPABILITY] =
4266 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
7a21bee2 4267 /* XSAVES is added in version 3 */
0b18874b
PL		 4268 .features[FEAT_XSAVE] =
4269 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4270 CPUID_XSAVE_XGETBV1,
4271 .features[FEAT_6_EAX] =
4272 CPUID_6_EAX_ARAT,
0723cc8a
PB		 4273 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4274 MSR_VMX_BASIC_TRUE_CTLS,
4275 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4276 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4277 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4278 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4279 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4280 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4281 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4282 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4283 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4284 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4285 .features[FEAT_VMX_EXIT_CTLS] =
4286 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4287 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4288 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4289 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4290 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4291 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4292 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4293 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4294 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4295 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4296 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4297 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4298 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4299 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4300 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4301 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4302 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4303 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4304 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4305 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4306 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4307 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4308 .features[FEAT_VMX_SECONDARY_CTLS] =
4309 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4310 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4311 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4312 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4313 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4314 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4315 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4316 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4317 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4318 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4319 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 4320 .xlevel = 0x80000008,
4321 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 4322 .versions = (X86CPUVersionDefinition[]) {
4323 { .version = 1 },
4324 {
4325 .version = 2,
4326 .props = (PropValue[]) {
4327 { "mpx", "off" },
4328 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4329 { /* end of list */ },
4330 },
4331 },
7bde6b18
VK		 4332 {
4333 .version = 3,
4334 .note = "XSAVES, no MPX",
4335 .props = (PropValue[]) {
4336 { "xsaves", "on" },
4337 { "vmx-xsaves", "on" },
4338 { /* end of list */ },
4339 },
4340 },
56bb24e5
CQ		 4341 {
4342 .version = 4,
07db29f2 4343 .note = "no split lock detect, no core-capability",
56bb24e5
CQ		 4344 .props = (PropValue[]) {
4345 { "split-lock-detect", "off" },
07db29f2 4346 { "core-capability", "off" },
56bb24e5
CQ		 4347 { /* end of list */ },
4348 },
4349 },
69edb0f3
XL		 4350 { /* end of list */ },
4351 },
0b18874b 4352 },
a1849515
BF		 4353 {
4354 .name = "KnightsMill",
4355 .level = 0xd,
4356 .vendor = CPUID_VENDOR_INTEL,
4357 .family = 6,
4358 .model = 133,
4359 .stepping = 0,
4360 .features[FEAT_1_EDX] =
4361 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
4362 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
4363 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
4364 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
4365 CPUID_PSE | CPUID_DE | CPUID_FP87,
4366 .features[FEAT_1_ECX] =
4367 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
4368 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
4369 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
4370 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4371 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
4372 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
4373 .features[FEAT_8000_0001_EDX] =
4374 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
4375 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
4376 .features[FEAT_8000_0001_ECX] =
4377 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
4378 .features[FEAT_7_0_EBX] =
4379 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4380 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4381 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
4382 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
4383 CPUID_7_0_EBX_AVX512ER,
4384 .features[FEAT_7_0_ECX] =
4385 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
4386 .features[FEAT_7_0_EDX] =
4387 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
4388 .features[FEAT_XSAVE] =
4389 CPUID_XSAVE_XSAVEOPT,
4390 .features[FEAT_6_EAX] =
4391 CPUID_6_EAX_ARAT,
4392 .xlevel = 0x80000008,
4393 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
4394 },
3eca4642
EH		 4395 {
4396 .name = "Opteron_G1",
4397 .level = 5,
99b88a17 4398 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4399 .family = 15,
4400 .model = 6,
4401 .stepping = 1,
0514ef2f 4402 .features[FEAT_1_EDX] =
b3a4f0b1 4403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4407 CPUID_DE | CPUID_FP87,
0514ef2f 4408 .features[FEAT_1_ECX] =
27861ecc 4409 CPUID_EXT_SSE3,
0514ef2f 4410 .features[FEAT_8000_0001_EDX] =
2a923a29 4411 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 4412 .xlevel = 0x80000008,
4413 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
4414 },
4415 {
4416 .name = "Opteron_G2",
4417 .level = 5,
99b88a17 4418 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4419 .family = 15,
4420 .model = 6,
4421 .stepping = 1,
0514ef2f 4422 .features[FEAT_1_EDX] =
b3a4f0b1 4423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4427 CPUID_DE | CPUID_FP87,
0514ef2f 4428 .features[FEAT_1_ECX] =
27861ecc 4429 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 4430 .features[FEAT_8000_0001_EDX] =
2a923a29 4431 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 4432 .features[FEAT_8000_0001_ECX] =
27861ecc 4433 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4434 .xlevel = 0x80000008,
4435 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
4436 },
4437 {
4438 .name = "Opteron_G3",
4439 .level = 5,
99b88a17 4440 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 4441 .family = 16,
4442 .model = 2,
4443 .stepping = 3,
0514ef2f 4444 .features[FEAT_1_EDX] =
b3a4f0b1 4445 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4446 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4447 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4448 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4449 CPUID_DE | CPUID_FP87,
0514ef2f 4450 .features[FEAT_1_ECX] =
27861ecc 4451 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 4452 CPUID_EXT_SSE3,
0514ef2f 4453 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 4454 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
4455 CPUID_EXT2_RDTSCP,
0514ef2f 4456 .features[FEAT_8000_0001_ECX] =
27861ecc 4457 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 4458 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 4459 .xlevel = 0x80000008,
4460 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
4461 },
4462 {
4463 .name = "Opteron_G4",
4464 .level = 0xd,
99b88a17 4465 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 4466 .family = 21,
4467 .model = 1,
4468 .stepping = 2,
0514ef2f 4469 .features[FEAT_1_EDX] =
b3a4f0b1 4470 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4471 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4472 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4473 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4474 CPUID_DE | CPUID_FP87,
0514ef2f 4475 .features[FEAT_1_ECX] =
27861ecc 4476 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 4477 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4478 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
4479 CPUID_EXT_SSE3,
0514ef2f 4480 .features[FEAT_8000_0001_EDX] =
2a923a29 4481 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4482 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4483 .features[FEAT_8000_0001_ECX] =
27861ecc 4484 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4485 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4486 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4487 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4488 .features[FEAT_SVM] =
4489 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4490 /* no xsaveopt! */
3eca4642
EH		 4491 .xlevel = 0x8000001A,
4492 .model_id = "AMD Opteron 62xx class CPU",
4493 },
021941b9
AP		 4494 {
4495 .name = "Opteron_G5",
4496 .level = 0xd,
99b88a17 4497 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 4498 .family = 21,
4499 .model = 2,
4500 .stepping = 0,
0514ef2f 4501 .features[FEAT_1_EDX] =
b3a4f0b1 4502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 4503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
4504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
4505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
4506 CPUID_DE | CPUID_FP87,
0514ef2f 4507 .features[FEAT_1_ECX] =
27861ecc 4508 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 4509 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
4510 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4511 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 4512 .features[FEAT_8000_0001_EDX] =
2a923a29 4513 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 4514 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 4515 .features[FEAT_8000_0001_ECX] =
27861ecc 4516 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 4517 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
4518 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
4519 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 4520 .features[FEAT_SVM] =
4521 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 4522 /* no xsaveopt! */
021941b9
AP		 4523 .xlevel = 0x8000001A,
4524 .model_id = "AMD Opteron 63xx class CPU",
4525 },
2e2efc7d
BS		 4526 {
4527 .name = "EPYC",
4528 .level = 0xd,
4529 .vendor = CPUID_VENDOR_AMD,
4530 .family = 23,
4531 .model = 1,
4532 .stepping = 2,
4533 .features[FEAT_1_EDX] =
4534 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4535 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4536 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4537 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4538 CPUID_VME | CPUID_FP87,
4539 .features[FEAT_1_ECX] =
4540 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4541 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4542 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4543 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4544 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4545 .features[FEAT_8000_0001_EDX] =
4546 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4547 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4548 CPUID_EXT2_SYSCALL,
4549 .features[FEAT_8000_0001_ECX] =
4550 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4551 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 4552 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4553 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 4554 .features[FEAT_7_0_EBX] =
4555 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4556 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4557 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4558 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 4559 .features[FEAT_XSAVE] =
4560 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4561 CPUID_XSAVE_XGETBV1,
4562 .features[FEAT_6_EAX] =
4563 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 4564 .features[FEAT_SVM] =
4565 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 4566 .xlevel = 0x8000001E,
2e2efc7d 4567 .model_id = "AMD EPYC Processor",
fe52acd2 4568 .cache_info = &epyc_cache_info,
d86a7088
EH		 4569 .versions = (X86CPUVersionDefinition[]) {
4570 { .version = 1 },
4571 {
4572 .version = 2,
53db89d9 4573 .alias = "EPYC-IBPB",
d86a7088
EH		 4574 .props = (PropValue[]) {
4575 { "ibpb", "on" },
4576 { "model-id",
4577 "AMD EPYC Processor (with IBPB)" },
4578 { /* end of list */ }
4579 }
4580 },
a16e8dbc
MB		 4581 {
4582 .version = 3,
4583 .props = (PropValue[]) {
4584 { "ibpb", "on" },
4585 { "perfctr-core", "on" },
4586 { "clzero", "on" },
4587 { "xsaveerptr", "on" },
4588 { "xsaves", "on" },
4589 { "model-id",
4590 "AMD EPYC Processor" },
4591 { /* end of list */ }
4592 }
4593 },
d7c72735
MR		 4594 {
4595 .version = 4,
4596 .props = (PropValue[]) {
4597 { "model-id",
4598 "AMD EPYC-v4 Processor" },
4599 { /* end of list */ }
4600 },
4601 .cache_info = &epyc_v4_cache_info
4602 },
d86a7088
EH		 4603 { /* end of list */ }
4604 }
2e2efc7d 4605 },
8d031cec
PW		 4606 {
4607 .name = "Dhyana",
4608 .level = 0xd,
4609 .vendor = CPUID_VENDOR_HYGON,
4610 .family = 24,
4611 .model = 0,
4612 .stepping = 1,
4613 .features[FEAT_1_EDX] =
4614 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4615 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4616 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4617 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4618 CPUID_VME | CPUID_FP87,
4619 .features[FEAT_1_ECX] =
4620 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4621 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4622 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4623 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4624 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4625 .features[FEAT_8000_0001_EDX] =
4626 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4627 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4628 CPUID_EXT2_SYSCALL,
4629 .features[FEAT_8000_0001_ECX] =
4630 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4631 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4632 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4633 CPUID_EXT3_TOPOEXT,
4634 .features[FEAT_8000_0008_EBX] =
4635 CPUID_8000_0008_EBX_IBPB,
4636 .features[FEAT_7_0_EBX] =
4637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4638 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4639 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
7bde6b18 4640 /* XSAVES is added in version 2 */
8d031cec
PW		 4641 .features[FEAT_XSAVE] =
4642 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4643 CPUID_XSAVE_XGETBV1,
4644 .features[FEAT_6_EAX] =
4645 CPUID_6_EAX_ARAT,
4646 .features[FEAT_SVM] =
4647 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4648 .xlevel = 0x8000001E,
4649 .model_id = "Hygon Dhyana Processor",
4650 .cache_info = &epyc_cache_info,
7bde6b18
VK		 4651 .versions = (X86CPUVersionDefinition[]) {
4652 { .version = 1 },
4653 { .version = 2,
4654 .note = "XSAVES",
4655 .props = (PropValue[]) {
4656 { "xsaves", "on" },
4657 { /* end of list */ }
4658 },
4659 },
4660 { /* end of list */ }
4661 }
8d031cec 4662 },
143c30d4
MB		 4663 {
4664 .name = "EPYC-Rome",
4665 .level = 0xd,
4666 .vendor = CPUID_VENDOR_AMD,
4667 .family = 23,
4668 .model = 49,
4669 .stepping = 0,
4670 .features[FEAT_1_EDX] =
4671 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4672 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4673 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4674 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4675 CPUID_VME | CPUID_FP87,
4676 .features[FEAT_1_ECX] =
4677 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4678 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4679 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4680 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4681 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4682 .features[FEAT_8000_0001_EDX] =
4683 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4684 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4685 CPUID_EXT2_SYSCALL,
4686 .features[FEAT_8000_0001_ECX] =
4687 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4688 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4689 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4690 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4691 .features[FEAT_8000_0008_EBX] =
4692 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4693 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4694 CPUID_8000_0008_EBX_STIBP,
4695 .features[FEAT_7_0_EBX] =
4696 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4697 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4698 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4699 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4700 .features[FEAT_7_0_ECX] =
4701 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4702 .features[FEAT_XSAVE] =
4703 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4704 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4705 .features[FEAT_6_EAX] =
4706 CPUID_6_EAX_ARAT,
4707 .features[FEAT_SVM] =
4708 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4709 .xlevel = 0x8000001E,
4710 .model_id = "AMD EPYC-Rome Processor",
4711 .cache_info = &epyc_rome_cache_info,
cdeaed27
BM		 4712 .versions = (X86CPUVersionDefinition[]) {
4713 { .version = 1 },
4714 {
4715 .version = 2,
4716 .props = (PropValue[]) {
4717 { "ibrs", "on" },
4718 { "amd-ssbd", "on" },
4719 { /* end of list */ }
4720 }
4721 },
d7c72735
MR		 4722 {
4723 .version = 3,
4724 .props = (PropValue[]) {
4725 { "model-id",
4726 "AMD EPYC-Rome-v3 Processor" },
4727 { /* end of list */ }
4728 },
4729 .cache_info = &epyc_rome_v3_cache_info
4730 },
fb00aa61
MD		 4731 {
4732 .version = 4,
4733 .props = (PropValue[]) {
4734 /* Erratum 1386 */
4735 { "model-id",
4736 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
4737 { "xsaves", "off" },
4738 { /* end of list */ }
4739 },
4740 },
cdeaed27
BM		 4741 { /* end of list */ }
4742 }
143c30d4 4743 },
623972ce
BM		 4744 {
4745 .name = "EPYC-Milan",
4746 .level = 0xd,
4747 .vendor = CPUID_VENDOR_AMD,
4748 .family = 25,
4749 .model = 1,
4750 .stepping = 1,
4751 .features[FEAT_1_EDX] =
4752 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4753 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4754 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4755 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4756 CPUID_VME | CPUID_FP87,
4757 .features[FEAT_1_ECX] =
4758 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4759 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4760 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4761 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4762 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4763 CPUID_EXT_PCID,
4764 .features[FEAT_8000_0001_EDX] =
4765 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4766 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4767 CPUID_EXT2_SYSCALL,
4768 .features[FEAT_8000_0001_ECX] =
4769 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4770 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4771 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4772 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4773 .features[FEAT_8000_0008_EBX] =
4774 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4775 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4776 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4777 CPUID_8000_0008_EBX_AMD_SSBD,
4778 .features[FEAT_7_0_EBX] =
4779 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4780 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4781 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4782 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4783 CPUID_7_0_EBX_INVPCID,
4784 .features[FEAT_7_0_ECX] =
4785 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4786 .features[FEAT_7_0_EDX] =
4787 CPUID_7_0_EDX_FSRM,
4788 .features[FEAT_XSAVE] =
4789 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4790 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4791 .features[FEAT_6_EAX] =
4792 CPUID_6_EAX_ARAT,
4793 .features[FEAT_SVM] =
4794 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4795 .xlevel = 0x8000001E,
4796 .model_id = "AMD EPYC-Milan Processor",
4797 .cache_info = &epyc_milan_cache_info,
27f03be6
BM		 4798 .versions = (X86CPUVersionDefinition[]) {
4799 { .version = 1 },
4800 {
4801 .version = 2,
4802 .props = (PropValue[]) {
4803 { "model-id",
4804 "AMD EPYC-Milan-v2 Processor" },
4805 { "vaes", "on" },
4806 { "vpclmulqdq", "on" },
4807 { "stibp-always-on", "on" },
4808 { "amd-psfd", "on" },
4809 { "no-nested-data-bp", "on" },
4810 { "lfence-always-serializing", "on" },
4811 { "null-sel-clr-base", "on" },
4812 { /* end of list */ }
4813 },
4814 .cache_info = &epyc_milan_v2_cache_info
4815 },
4816 { /* end of list */ }
4817 }
623972ce 4818 },
166b1741
BM		 4819 {
4820 .name = "EPYC-Genoa",
4821 .level = 0xd,
4822 .vendor = CPUID_VENDOR_AMD,
4823 .family = 25,
4824 .model = 17,
4825 .stepping = 0,
4826 .features[FEAT_1_EDX] =
4827 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4828 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4829 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4830 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4831 CPUID_VME | CPUID_FP87,
4832 .features[FEAT_1_ECX] =
4833 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4834 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4835 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4836 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA |
4837 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ |
4838 CPUID_EXT_SSE3,
4839 .features[FEAT_8000_0001_EDX] =
4840 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4841 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4842 CPUID_EXT2_SYSCALL,
4843 .features[FEAT_8000_0001_ECX] =
4844 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4845 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4846 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4847 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4848 .features[FEAT_8000_0008_EBX] =
4849 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4850 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4851 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4852 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON |
4853 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD,
4854 .features[FEAT_8000_0021_EAX] =
4855 CPUID_8000_0021_EAX_No_NESTED_DATA_BP |
4856 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING |
4857 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE |
4858 CPUID_8000_0021_EAX_AUTO_IBRS,
4859 .features[FEAT_7_0_EBX] =
4860 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4861 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
4862 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F |
4863 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4864 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
4865 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
4866 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
4867 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
4868 .features[FEAT_7_0_ECX] =
4869 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
4870 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
4871 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
4872 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
4873 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
4874 CPUID_7_0_ECX_RDPID,
4875 .features[FEAT_7_0_EDX] =
4876 CPUID_7_0_EDX_FSRM,
4877 .features[FEAT_7_1_EAX] =
4878 CPUID_7_1_EAX_AVX512_BF16,
4879 .features[FEAT_XSAVE] =
4880 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4881 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4882 .features[FEAT_6_EAX] =
4883 CPUID_6_EAX_ARAT,
4884 .features[FEAT_SVM] =
4885 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI |
4886 CPUID_SVM_SVME_ADDR_CHK,
4887 .xlevel = 0x80000022,
4888 .model_id = "AMD EPYC-Genoa Processor",
4889 .cache_info = &epyc_genoa_cache_info,
4890 },
c6dc6f63
AP		 4891};
4892
ad183928
EH		 4893/*
4894 * We resolve CPU model aliases using -v1 when using "-machine
4895 * none", but this is just for compatibility while libvirt isn't
4896 * adapted to resolve CPU model versions before creating VMs.
32048d72 4897 * See "Runnability guarantee of CPU models" at
a476b216 4898 * docs/about/deprecated.rst.
ad183928
EH		 4899 */
4900X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4901
4902void x86_cpu_set_default_version(X86CPUVersion version)
4903{
4904 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4905 assert(version != CPU_VERSION_AUTO);
4906 default_cpu_version = version;
4907}
4908
dcafd1ef
EH		 4909static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4910{
4911 int v = 0;
4912 const X86CPUVersionDefinition *vdef =
4913 x86_cpu_def_get_versions(model->cpudef);
4914 while (vdef->version) {
4915 v = vdef->version;
4916 vdef++;
4917 }
4918 return v;
4919}
4920
4921/* Return the actual version being used for a specific CPU model */
4922static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4923{
4924 X86CPUVersion v = model->version;
0788a56b
EH		 4925 if (v == CPU_VERSION_AUTO) {
4926 v = default_cpu_version;
4927 }
dcafd1ef
EH		 4928 if (v == CPU_VERSION_LATEST) {
4929 return x86_cpu_model_last_version(model);
4930 }
4931 return v;
4932}
4933
c62f2630 4934static Property max_x86_cpu_properties[] = {
120eee7d 4935 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4936 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4937 DEFINE_PROP_END_OF_LIST()
4938};
4939
123fa102
TH		 4940static void max_x86_cpu_realize(DeviceState *dev, Error **errp)
4941{
4942 Object *obj = OBJECT(dev);
4943
4944 if (!object_property_get_int(obj, "family", &error_abort)) {
4945 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4946 object_property_set_int(obj, "family", 15, &error_abort);
4947 object_property_set_int(obj, "model", 107, &error_abort);
4948 object_property_set_int(obj, "stepping", 1, &error_abort);
4949 } else {
4950 object_property_set_int(obj, "family", 6, &error_abort);
4951 object_property_set_int(obj, "model", 6, &error_abort);
4952 object_property_set_int(obj, "stepping", 3, &error_abort);
4953 }
4954 }
4955
4956 x86_cpu_realizefn(dev, errp);
4957}
4958
c62f2630 4959static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4960{
84f1b92f 4961 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4962 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4963
f48c8837 4964 xcc->ordering = 9;
6e746f30 4965
ee465a3e 4966 xcc->model_description =
c62f2630 4967 "Enables all features supported by the accelerator in the current host";
d940ee9b 4968
4f67d30b 4969 device_class_set_props(dc, max_x86_cpu_properties);
123fa102 4970 dc->realize = max_x86_cpu_realize;
d940ee9b
EH		 4971}
4972
c62f2630 4973static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4974{
4975 X86CPU *cpu = X86_CPU(obj);
d940ee9b 4976
4d1b279b
EH		 4977 /* We can't fill the features array here because we don't know yet if
4978 * "migratable" is true or false.
4979 */
44bd8e53 4980 cpu->max_features = true;
5325cc34 4981 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
f5cc5a5c
CF		 4982
4983 /*
4984 * these defaults are used for TCG and all other accelerators
4985 * besides KVM and HVF, which overwrite these values
4986 */
4987 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4988 &error_abort);
f5cc5a5c
CF		 4989 object_property_set_str(OBJECT(cpu), "model-id",
4990 "QEMU TCG CPU version " QEMU_HW_VERSION,
4991 &error_abort);
c6dc6f63
AP		 4992}
4993
c62f2630
EH		 4994static const TypeInfo max_x86_cpu_type_info = {
4995 .name = X86_CPU_TYPE_NAME("max"),
4996 .parent = TYPE_X86_CPU,
4997 .instance_init = max_x86_cpu_initfn,
4998 .class_init = max_x86_cpu_class_init,
4999};
5000
07585923
RH		 5001static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
5002{
5003 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
5004
5005 switch (f->type) {
5006 case CPUID_FEATURE_WORD:
5007 {
5008 const char *reg = get_register_name_32(f->cpuid.reg);
5009 assert(reg);
5010 return g_strdup_printf("CPUID.%02XH:%s",
5011 f->cpuid.eax, reg);
5012 }
5013 case MSR_FEATURE_WORD:
5014 return g_strdup_printf("MSR(%02XH)",
5015 f->msr.index);
5016 }
5017
5018 return NULL;
5019}
5020
245edd0c 5021static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 5022{
245edd0c
PB		 5023 FeatureWord w;
5024
5025 for (w = 0; w < FEATURE_WORDS; w++) {
5026 if (cpu->filtered_features[w]) {
5027 return true;
5028 }
5029 }
5030
5031 return false;
5032}
5033
ede146c2 5034static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 5035 const char *verbose_prefix)
5036{
5037 CPUX86State *env = &cpu->env;
8459e396 5038 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 5039 int i;
5040
245edd0c
PB		 5041 if (!cpu->force_features) {
5042 env->features[w] &= ~mask;
5043 }
5044 cpu->filtered_features[w] |= mask;
5045
5046 if (!verbose_prefix) {
5047 return;
5048 }
5049
ede146c2
PB		 5050 for (i = 0; i < 64; ++i) {
5051 if ((1ULL << i) & mask) {
88703ce2 5052 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 5053 warn_report("%s: %s%s%s [bit %d]",
5054 verbose_prefix,
07585923 5055 feat_word_str,
8297be80
AF		 5056 f->feat_names[i] ? "." : "",
5057 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 5058 }
857aee33 5059 }
c6dc6f63
AP		 5060}
5061
d7bce999
EB		 5062static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
5063 const char *name, void *opaque,
5064 Error **errp)
95b8519d
AF		 5065{
5066 X86CPU *cpu = X86_CPU(obj);
5067 CPUX86State *env = &cpu->env;
5068 int64_t value;
5069
5070 value = (env->cpuid_version >> 8) & 0xf;
5071 if (value == 0xf) {
5072 value += (env->cpuid_version >> 20) & 0xff;
5073 }
51e72bc1 5074 visit_type_int(v, name, &value, errp);
95b8519d
AF		 5075}
5076
d7bce999
EB		 5077static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
5078 const char *name, void *opaque,
5079 Error **errp)
ed5e1ec3 5080{
71ad61d3
AF		 5081 X86CPU *cpu = X86_CPU(obj);
5082 CPUX86State *env = &cpu->env;
5083 const int64_t min = 0;
5084 const int64_t max = 0xff + 0xf;
5085 int64_t value;
5086
668f62ec 5087 if (!visit_type_int(v, name, &value, errp)) {
71ad61d3
AF		 5088 return;
5089 }
5090 if (value < min || value > max) {
c6bd8c70
MA		 5091 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5092 name ? name : "null", value, min, max);
71ad61d3
AF		 5093 return;
5094 }
5095
ed5e1ec3 5096 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 5097 if (value > 0x0f) {
5098 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 5099 } else {
71ad61d3 5100 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 5101 }
5102}
5103
d7bce999
EB		 5104static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
5105 const char *name, void *opaque,
5106 Error **errp)
67e30c83
AF		 5107{
5108 X86CPU *cpu = X86_CPU(obj);
5109 CPUX86State *env = &cpu->env;
5110 int64_t value;
5111
5112 value = (env->cpuid_version >> 4) & 0xf;
5113 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 5114 visit_type_int(v, name, &value, errp);
67e30c83
AF		 5115}
5116
d7bce999
EB		 5117static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
5118 const char *name, void *opaque,
5119 Error **errp)
b0704cbd 5120{
c5291a4f
AF		 5121 X86CPU *cpu = X86_CPU(obj);
5122 CPUX86State *env = &cpu->env;
5123 const int64_t min = 0;
5124 const int64_t max = 0xff;
5125 int64_t value;
5126
668f62ec 5127 if (!visit_type_int(v, name, &value, errp)) {
c5291a4f
AF		 5128 return;
5129 }
5130 if (value < min || value > max) {
c6bd8c70
MA		 5131 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5132 name ? name : "null", value, min, max);
c5291a4f
AF		 5133 return;
5134 }
5135
b0704cbd 5136 env->cpuid_version &= ~0xf00f0;
c5291a4f 5137 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 5138}
5139
35112e41 5140static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 5141 const char *name, void *opaque,
35112e41
AF		 5142 Error **errp)
5143{
5144 X86CPU *cpu = X86_CPU(obj);
5145 CPUX86State *env = &cpu->env;
5146 int64_t value;
5147
5148 value = env->cpuid_version & 0xf;
51e72bc1 5149 visit_type_int(v, name, &value, errp);
35112e41
AF		 5150}
5151
036e2222 5152static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 5153 const char *name, void *opaque,
036e2222 5154 Error **errp)
38c3dc46 5155{
036e2222
AF		 5156 X86CPU *cpu = X86_CPU(obj);
5157 CPUX86State *env = &cpu->env;
5158 const int64_t min = 0;
5159 const int64_t max = 0xf;
5160 int64_t value;
5161
668f62ec 5162 if (!visit_type_int(v, name, &value, errp)) {
036e2222
AF		 5163 return;
5164 }
5165 if (value < min || value > max) {
c6bd8c70
MA		 5166 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5167 name ? name : "null", value, min, max);
036e2222
AF		 5168 return;
5169 }
5170
38c3dc46 5171 env->cpuid_version &= ~0xf;
036e2222 5172 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 5173}
5174
d480e1af
AF		 5175static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
5176{
5177 X86CPU *cpu = X86_CPU(obj);
5178 CPUX86State *env = &cpu->env;
5179 char *value;
d480e1af 5180
e42a92ae 5181 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 5182 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
5183 env->cpuid_vendor3);
d480e1af
AF		 5184 return value;
5185}
5186
5187static void x86_cpuid_set_vendor(Object *obj, const char *value,
5188 Error **errp)
5189{
5190 X86CPU *cpu = X86_CPU(obj);
5191 CPUX86State *env = &cpu->env;
5192 int i;
5193
9df694ee 5194 if (strlen(value) != CPUID_VENDOR_SZ) {
298d8b12
MA		 5195 error_setg(errp, "value of property 'vendor' must consist of"
5196 " exactly " stringify(CPUID_VENDOR_SZ) " characters");
d480e1af
AF		 5197 return;
5198 }
5199
5200 env->cpuid_vendor1 = 0;
5201 env->cpuid_vendor2 = 0;
5202 env->cpuid_vendor3 = 0;
5203 for (i = 0; i < 4; i++) {
5204 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
5205 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
5206 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
5207 }
d480e1af
AF		 5208}
5209
63e886eb
AF		 5210static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
5211{
5212 X86CPU *cpu = X86_CPU(obj);
5213 CPUX86State *env = &cpu->env;
5214 char *value;
5215 int i;
5216
5217 value = g_malloc(48 + 1);
5218 for (i = 0; i < 48; i++) {
5219 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
5220 }
5221 value[48] = '\0';
5222 return value;
5223}
5224
938d4c25
AF		 5225static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
5226 Error **errp)
dcce6675 5227{
938d4c25
AF		 5228 X86CPU *cpu = X86_CPU(obj);
5229 CPUX86State *env = &cpu->env;
dcce6675
AF		 5230 int c, len, i;
5231
5232 if (model_id == NULL) {
5233 model_id = "";
5234 }
5235 len = strlen(model_id);
d0a6acf4 5236 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 5237 for (i = 0; i < 48; i++) {
5238 if (i >= len) {
5239 c = '\0';
5240 } else {
5241 c = (uint8_t)model_id[i];
5242 }
5243 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
5244 }
5245}
5246
d7bce999
EB		 5247static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
5248 void *opaque, Error **errp)
89e48965
AF		 5249{
5250 X86CPU *cpu = X86_CPU(obj);
5251 int64_t value;
5252
5253 value = cpu->env.tsc_khz * 1000;
51e72bc1 5254 visit_type_int(v, name, &value, errp);
89e48965
AF		 5255}
5256
d7bce999
EB		 5257static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
5258 void *opaque, Error **errp)
89e48965
AF		 5259{
5260 X86CPU *cpu = X86_CPU(obj);
5261 const int64_t min = 0;
2e84849a 5262 const int64_t max = INT64_MAX;
89e48965
AF		 5263 int64_t value;
5264
668f62ec 5265 if (!visit_type_int(v, name, &value, errp)) {
89e48965
AF		 5266 return;
5267 }
5268 if (value < min || value > max) {
c6bd8c70
MA		 5269 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
5270 name ? name : "null", value, min, max);
89e48965
AF		 5271 return;
5272 }
5273
36f96c4b 5274 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 5275}
5276
7e5292b5 5277/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 5278static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
5279 const char *name, void *opaque,
5280 Error **errp)
8e8aba50 5281{
ede146c2 5282 uint64_t *array = (uint64_t *)opaque;
8e8aba50 5283 FeatureWord w;
8e8aba50
EH		 5284 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
5285 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
5286 X86CPUFeatureWordInfoList *list = NULL;
5287
5288 for (w = 0; w < FEATURE_WORDS; w++) {
5289 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 5290 /*
5291 * We didn't have MSR features when "feature-words" was
5292 * introduced. Therefore skipped other type entries.
5293 */
5294 if (wi->type != CPUID_FEATURE_WORD) {
5295 continue;
5296 }
8e8aba50 5297 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 5298 qwi->cpuid_input_eax = wi->cpuid.eax;
5299 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
5300 qwi->cpuid_input_ecx = wi->cpuid.ecx;
5301 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 5302 qwi->features = array[w];
8e8aba50
EH		 5303
5304 /* List will be in reverse order, but order shouldn't matter */
5305 list_entries[w].next = list;
5306 list_entries[w].value = &word_infos[w];
5307 list = &list_entries[w];
5308 }
5309
6b62d961 5310 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 5311}
5312
72ac2e87
IM		 5313/* Convert all '_' in a feature string option name to '-', to make feature
5314 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5315 */
5316static inline void feat2prop(char *s)
5317{
5318 while ((s = strchr(s, '_'))) {
5319 *s = '-';
5320 }
5321}
5322
b54c9377
EH		 5323/* Return the feature property name for a feature flag bit */
5324static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
5325{
ede146c2 5326 const char *name;
b54c9377
EH		 5327 /* XSAVE components are automatically enabled by other features,
5328 * so return the original feature name instead
5329 */
301e9067
YW		 5330 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) {
5331 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr;
b54c9377
EH		 5332
5333 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
5334 x86_ext_save_areas[comp].bits) {
5335 w = x86_ext_save_areas[comp].feature;
5336 bitnr = ctz32(x86_ext_save_areas[comp].bits);
5337 }
5338 }
5339
ede146c2 5340 assert(bitnr < 64);
b54c9377 5341 assert(w < FEATURE_WORDS);
ede146c2
PB		 5342 name = feature_word_info[w].feat_names[bitnr];
5343 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
5344 return name;
b54c9377
EH		 5345}
5346
bad5cfcd 5347/* Compatibility hack to maintain legacy +-feat semantic,
dc15c051
IM		 5348 * where +-feat overwrites any feature set by
5349 * feat=on|feat even if the later is parsed after +-feat
5350 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5351 */
2fae0d96 5352static GList *plus_features, *minus_features;
dc15c051 5353
83a00f60
EH		 5354static gint compare_string(gconstpointer a, gconstpointer b)
5355{
5356 return g_strcmp0(a, b);
5357}
5358
8f961357
EH		 5359/* Parse "+feature,-feature,feature=foo" CPU feature string
5360 */
62a48a2a 5361static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 5362 Error **errp)
8f961357 5363{
8f961357 5364 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 5365 static bool cpu_globals_initialized;
83a00f60 5366 bool ambiguous = false;
62a48a2a
IM		 5367
5368 if (cpu_globals_initialized) {
5369 return;
5370 }
5371 cpu_globals_initialized = true;
8f961357 5372
f6750e95
EH		 5373 if (!features) {
5374 return;
5375 }
5376
5377 for (featurestr = strtok(features, ",");
685479bd 5378 featurestr;
f6750e95
EH		 5379 featurestr = strtok(NULL, ",")) {
5380 const char *name;
5381 const char *val = NULL;
5382 char *eq = NULL;
cf2887c9 5383 char num[32];
62a48a2a 5384 GlobalProperty *prop;
c6dc6f63 5385
f6750e95 5386 /* Compatibility syntax: */
c6dc6f63 5387 if (featurestr[0] == '+') {
2fae0d96
EH		 5388 plus_features = g_list_append(plus_features,
5389 g_strdup(featurestr + 1));
f6750e95 5390 continue;
c6dc6f63 5391 } else if (featurestr[0] == '-') {
2fae0d96
EH		 5392 minus_features = g_list_append(minus_features,
5393 g_strdup(featurestr + 1));
f6750e95
EH		 5394 continue;
5395 }
5396
5397 eq = strchr(featurestr, '=');
5398 if (eq) {
5399 *eq++ = 0;
5400 val = eq;
c6dc6f63 5401 } else {
f6750e95 5402 val = "on";
a91987c2 5403 }
f6750e95
EH		 5404
5405 feat2prop(featurestr);
5406 name = featurestr;
5407
83a00f60 5408 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 5409 warn_report("Ambiguous CPU model string. "
5410 "Don't mix both \"+%s\" and \"%s=%s\"",
5411 name, name, val);
83a00f60
EH		 5412 ambiguous = true;
5413 }
5414 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 5415 warn_report("Ambiguous CPU model string. "
5416 "Don't mix both \"-%s\" and \"%s=%s\"",
5417 name, name, val);
83a00f60
EH		 5418 ambiguous = true;
5419 }
5420
f6750e95
EH		 5421 /* Special case: */
5422 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 5423 int ret;
f46bfdbf 5424 uint64_t tsc_freq;
f6750e95 5425
f17fd4fd 5426 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 5427 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 5428 error_setg(errp, "bad numerical value %s", val);
5429 return;
5430 }
5431 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
5432 val = num;
5433 name = "tsc-frequency";
c6dc6f63 5434 }
f6750e95 5435
62a48a2a
IM		 5436 prop = g_new0(typeof(*prop), 1);
5437 prop->driver = typename;
5438 prop->property = g_strdup(name);
5439 prop->value = g_strdup(val);
62a48a2a 5440 qdev_prop_register_global(prop);
f6750e95
EH		 5441 }
5442
83a00f60 5443 if (ambiguous) {
3dc6f869
AF		 5444 warn_report("Compatibility of ambiguous CPU model "
5445 "strings won't be kept on future QEMU versions");
83a00f60 5446 }
c6dc6f63
AP		 5447}
5448
245edd0c 5449static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 5450
5a853fc5
EH		 5451/* Build a list with the name of all features on a feature word array */
5452static void x86_cpu_list_feature_names(FeatureWordArray features,
c3033fd3 5453 strList **list)
5a853fc5 5454{
c3033fd3 5455 strList **tail = list;
5a853fc5 5456 FeatureWord w;
5a853fc5
EH		 5457
5458 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 5459 uint64_t filtered = features[w];
5a853fc5 5460 int i;
ede146c2
PB		 5461 for (i = 0; i < 64; i++) {
5462 if (filtered & (1ULL << i)) {
c3033fd3 5463 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
5a853fc5
EH		 5464 }
5465 }
5466 }
5467}
5468
506174bf
EH		 5469static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
5470 const char *name, void *opaque,
5471 Error **errp)
5472{
5473 X86CPU *xc = X86_CPU(obj);
5474 strList *result = NULL;
5475
5476 x86_cpu_list_feature_names(xc->filtered_features, &result);
5477 visit_type_strList(v, "unavailable-features", &result, errp);
5478}
5479
8c3329e5 5480/* Print all cpuid feature names in featureset
c6dc6f63 5481 */
0442428a 5482static void listflags(GList *features)
0856579c 5483{
cc643b1e
DB		 5484 size_t len = 0;
5485 GList *tmp;
5486
5487 for (tmp = features; tmp; tmp = tmp->next) {
5488 const char *name = tmp->data;
5489 if ((len + strlen(name) + 1) >= 75) {
0442428a 5490 qemu_printf("\n");
cc643b1e 5491 len = 0;
c6dc6f63 5492 }
0442428a 5493 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 5494 len += strlen(name) + 1;
8c3329e5 5495 }
0442428a 5496 qemu_printf("\n");
c6dc6f63
AP		 5497}
5498
f48c8837 5499/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 5500static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
5501{
5502 ObjectClass *class_a = (ObjectClass *)a;
5503 ObjectClass *class_b = (ObjectClass *)b;
5504 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
5505 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 5506 int ret;
ee465a3e 5507
f48c8837 5508 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 5509 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 5510 } else {
88703ce2
EH		 5511 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
5512 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 5513 ret = strcmp(name_a, name_b);
ee465a3e 5514 }
c7dbff4b 5515 return ret;
ee465a3e
EH		 5516}
5517
5518static GSList *get_sorted_cpu_model_list(void)
5519{
5520 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
5521 list = g_slist_sort(list, x86_cpu_list_compare);
5522 return list;
5523}
5524
164e779c
EH		 5525static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
5526{
3c75e12e 5527 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 5528 char *r = object_property_get_str(obj, "model-id", &error_abort);
5529 object_unref(obj);
5530 return r;
5531}
5532
0788a56b
EH		 5533static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
5534{
5535 X86CPUVersion version;
5536
5537 if (!cc->model || !cc->model->is_alias) {
5538 return NULL;
5539 }
5540 version = x86_cpu_model_resolve_version(cc->model);
5541 if (version <= 0) {
5542 return NULL;
5543 }
5544 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
5545}
5546
ee465a3e
EH		 5547static void x86_cpu_list_entry(gpointer data, gpointer user_data)
5548{
5549 ObjectClass *oc = data;
5550 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 5551 g_autofree char *name = x86_cpu_class_get_model_name(cc);
5552 g_autofree char *desc = g_strdup(cc->model_description);
5553 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 5554 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 5555
0788a56b
EH		 5556 if (!desc && alias_of) {
5557 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
5558 desc = g_strdup("(alias configured by machine type)");
5559 } else {
5560 desc = g_strdup_printf("(alias of %s)", alias_of);
5561 }
5562 }
c63938df
TX		 5563 if (!desc && cc->model && cc->model->note) {
5564 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
5565 }
164e779c 5566 if (!desc) {
c63938df 5567 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 5568 }
5569
5dfa9e86
DB		 5570 if (cc->model && cc->model->cpudef->deprecation_note) {
5571 g_autofree char *olddesc = desc;
5572 desc = g_strdup_printf("%s (deprecated)", olddesc);
5573 }
5574
61848717 5575 qemu_printf("x86 %-20s %s\n", name, desc);
ee465a3e
EH		 5576}
5577
5578/* list available CPU models and flags */
0442428a 5579void x86_cpu_list(void)
c6dc6f63 5580{
cc643b1e 5581 int i, j;
ee465a3e 5582 GSList *list;
cc643b1e 5583 GList *names = NULL;
c6dc6f63 5584
0442428a 5585 qemu_printf("Available CPUs:\n");
ee465a3e 5586 list = get_sorted_cpu_model_list();
0442428a 5587 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 5588 g_slist_free(list);
21ad7789 5589
cc643b1e 5590 names = NULL;
3af60be2
JK		 5591 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
5592 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 5593 for (j = 0; j < 64; j++) {
cc643b1e
DB		 5594 if (fw->feat_names[j]) {
5595 names = g_list_append(names, (gpointer)fw->feat_names[j]);
5596 }
5597 }
3af60be2 5598 }
cc643b1e
DB		 5599
5600 names = g_list_sort(names, (GCompareFunc)strcmp);
5601
0442428a
MA		 5602 qemu_printf("\nRecognized CPUID flags:\n");
5603 listflags(names);
5604 qemu_printf("\n");
cc643b1e 5605 g_list_free(names);
c6dc6f63
AP		 5606}
5607
390dbc6e
PMD		 5608#ifndef CONFIG_USER_ONLY
5609
5610/* Check for missing features that may prevent the CPU class from
5611 * running using the current machine and accelerator.
5612 */
5613static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
5614 strList **list)
5615{
5616 strList **tail = list;
5617 X86CPU *xc;
5618 Error *err = NULL;
5619
5620 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
5621 QAPI_LIST_APPEND(tail, g_strdup("kvm"));
5622 return;
5623 }
5624
5625 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5626
5627 x86_cpu_expand_features(xc, &err);
5628 if (err) {
5629 /* Errors at x86_cpu_expand_features should never happen,
5630 * but in case it does, just report the model as not
5631 * runnable at all using the "type" property.
5632 */
5633 QAPI_LIST_APPEND(tail, g_strdup("type"));
5634 error_free(err);
5635 }
5636
5637 x86_cpu_filter_features(xc, false);
5638
5639 x86_cpu_list_feature_names(xc->filtered_features, tail);
5640
5641 object_unref(OBJECT(xc));
5642}
5643
ee465a3e
EH		 5644static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
5645{
5646 ObjectClass *oc = data;
5647 X86CPUClass *cc = X86_CPU_CLASS(oc);
5648 CpuDefinitionInfoList **cpu_list = user_data;
ee465a3e
EH		 5649 CpuDefinitionInfo *info;
5650
5651 info = g_malloc0(sizeof(*info));
5652 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 5653 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
5654 info->has_unavailable_features = true;
8ed877b7 5655 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 5656 info->migration_safe = cc->migration_safe;
5657 info->has_migration_safe = true;
5adbed30 5658 info->q_static = cc->static_model;
61ad65d0
RH		 5659 if (cc->model && cc->model->cpudef->deprecation_note) {
5660 info->deprecated = true;
5661 } else {
5662 info->deprecated = false;
5663 }
0788a56b
EH		 5664 /*
5665 * Old machine types won't report aliases, so that alias translation
5666 * doesn't break compatibility with previous QEMU versions.
5667 */
5668 if (default_cpu_version != CPU_VERSION_LEGACY) {
5669 info->alias_of = x86_cpu_class_get_alias_of(cc);
0788a56b 5670 }
ee465a3e 5671
54aa3de7 5672 QAPI_LIST_PREPEND(*cpu_list, info);
ee465a3e
EH		 5673}
5674
25a9d6ca 5675CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 5676{
5677 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 5678 GSList *list = get_sorted_cpu_model_list();
5679 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5680 g_slist_free(list);
e3966126
AL		 5681 return cpu_list;
5682}
5683
390dbc6e
PMD		 5684#endif /* !CONFIG_USER_ONLY */
5685
58f7db26
PB		 5686uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5687 bool migratable_only)
27418adf
EH		 5688{
5689 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 5690 uint64_t r = 0;
27418adf 5691
fefb41bf 5692 if (kvm_enabled()) {
07585923
RH		 5693 switch (wi->type) {
5694 case CPUID_FEATURE_WORD:
5695 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5696 wi->cpuid.ecx,
5697 wi->cpuid.reg);
5698 break;
5699 case MSR_FEATURE_WORD:
d86f9636
RH		 5700 r = kvm_arch_get_supported_msr_feature(kvm_state,
5701 wi->msr.index);
07585923
RH		 5702 break;
5703 }
d6dcc558 5704 } else if (hvf_enabled()) {
07585923
RH		 5705 if (wi->type != CPUID_FEATURE_WORD) {
5706 return 0;
5707 }
5708 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5709 wi->cpuid.ecx,
5710 wi->cpuid.reg);
fefb41bf 5711 } else if (tcg_enabled()) {
84f1b92f 5712 r = wi->tcg_features;
fefb41bf
EH		 5713 } else {
5714 return ~0;
5715 }
5ea9e9e2
PB		 5716#ifndef TARGET_X86_64
5717 if (w == FEAT_8000_0001_EDX) {
40a205da
PB		 5718 /*
5719 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no
5720 * way for userspace to get out of its 32-bit jail, we can leave
5721 * the LM bit set.
5722 */
5723 uint32_t unavail = tcg_enabled()
5724 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES
5725 : CPUID_EXT2_LM;
5726 r &= ~unavail;
5ea9e9e2
PB		 5727 }
5728#endif
84f1b92f
EH		 5729 if (migratable_only) {
5730 r &= x86_cpu_get_migratable_flags(w);
5731 }
5732 return r;
27418adf
EH		 5733}
5734
d19d6ffa
PB		 5735static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index,
5736 uint32_t *eax, uint32_t *ebx,
5737 uint32_t *ecx, uint32_t *edx)
5738{
5739 if (kvm_enabled()) {
5740 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX);
5741 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX);
5742 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX);
5743 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX);
5744 } else if (hvf_enabled()) {
5745 *eax = hvf_get_supported_cpuid(func, index, R_EAX);
5746 *ebx = hvf_get_supported_cpuid(func, index, R_EBX);
5747 *ecx = hvf_get_supported_cpuid(func, index, R_ECX);
5748 *edx = hvf_get_supported_cpuid(func, index, R_EDX);
5749 } else {
5750 *eax = 0;
5751 *ebx = 0;
5752 *ecx = 0;
5753 *edx = 0;
5754 }
5755}
5756
798d8ec0
PB		 5757static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index,
5758 uint32_t *eax, uint32_t *ebx,
5759 uint32_t *ecx, uint32_t *edx)
5760{
5761 uint32_t level, unused;
5762
5763 /* Only return valid host leaves. */
5764 switch (func) {
5765 case 2:
5766 case 4:
5767 host_cpuid(0, 0, &level, &unused, &unused, &unused);
5768 break;
5769 case 0x80000005:
5770 case 0x80000006:
5771 case 0x8000001d:
5772 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused);
5773 break;
5774 default:
5775 return;
5776 }
5777
5778 if (func > level) {
5779 *eax = 0;
5780 *ebx = 0;
5781 *ecx = 0;
5782 *edx = 0;
5783 } else {
5784 host_cpuid(func, index, eax, ebx, ecx, edx);
5785 }
5786}
5787
5b8978d8
CF		 5788/*
5789 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5790 */
f5cc5a5c 5791void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5114e842
EH		 5792{
5793 PropValue *pv;
5794 for (pv = props; pv->prop; pv++) {
5795 if (!pv->value) {
5796 continue;
5797 }
5325cc34 5798 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5114e842
EH		 5799 &error_abort);
5800 }
5801}
5802
5b8978d8
CF		 5803/*
5804 * Apply properties for the CPU model version specified in model.
5805 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5806 */
5807
dcafd1ef
EH		 5808static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5809{
5810 const X86CPUVersionDefinition *vdef;
5811 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5812
5813 if (version == CPU_VERSION_LEGACY) {
5814 return;
5815 }
5816
5817 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5818 PropValue *p;
5819
5820 for (p = vdef->props; p && p->prop; p++) {
5325cc34 5821 object_property_parse(OBJECT(cpu), p->prop, p->value,
dcafd1ef
EH		 5822 &error_abort);
5823 }
5824
5825 if (vdef->version == version) {
5826 break;
5827 }
5828 }
5829
5830 /*
5831 * If we reached the end of the list, version number was invalid
5832 */
5833 assert(vdef->version == version);
5834}
5835
cca0a000
MR		 5836static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
5837 X86CPUModel *model)
5838{
5839 const X86CPUVersionDefinition *vdef;
5840 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5841 const CPUCaches *cache_info = model->cpudef->cache_info;
5842
5843 if (version == CPU_VERSION_LEGACY) {
5844 return cache_info;
5845 }
5846
5847 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5848 if (vdef->cache_info) {
5849 cache_info = vdef->cache_info;
5850 }
5851
5852 if (vdef->version == version) {
5853 break;
5854 }
5855 }
5856
5857 assert(vdef->version == version);
5858 return cache_info;
5859}
5860
5b8978d8
CF		 5861/*
5862 * Load data from X86CPUDefinition into a X86CPU object.
5863 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
c080e30e 5864 */
49e2fa85 5865static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
c6dc6f63 5866{
e11fd689 5867 const X86CPUDefinition *def = model->cpudef;
61dcd775 5868 CPUX86State *env = &cpu->env;
e1c224b4 5869 FeatureWord w;
c6dc6f63 5870
f99fd7ca
EH		 5871 /*NOTE: any property set by this function should be returned by
5872 * x86_cpu_static_props(), so static expansion of
5873 * query-cpu-model-expansion is always complete.
5874 */
5875
c39c0edf 5876 /* CPU models only set _minimum_ values for level/xlevel: */
5325cc34 5877 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
49e2fa85 5878 &error_abort);
5325cc34 5879 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
49e2fa85
MA		 5880 &error_abort);
5881
5325cc34
MA		 5882 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5883 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5884 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
49e2fa85 5885 &error_abort);
5325cc34 5886 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
49e2fa85 5887 &error_abort);
e1c224b4
EH		 5888 for (w = 0; w < FEATURE_WORDS; w++) {
5889 env->features[w] = def->features[w];
5890 }
82beb536 5891
a9f27ea9 5892 /* legacy-cache defaults to 'off' if CPU model provides cache info */
cca0a000 5893 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model);
ab8f992e 5894
82beb536 5895 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5896
5897 /* sysenter isn't supported in compatibility mode on AMD,
5898 * syscall isn't supported in compatibility mode on Intel.
5899 * Normally we advertise the actual CPU vendor, but you can
5900 * override this using the 'vendor' property if you want to use
5901 * KVM's sysenter/syscall emulation in compatibility mode and
5902 * when doing cross vendor migration
5903 */
7c08db30 5904
f5cc5a5c
CF		 5905 /*
5906 * vendor property is set here but then overloaded with the
5907 * host cpu vendor for KVM and HVF.
5908 */
5909 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
7c08db30 5910
dcafd1ef 5911 x86_cpu_apply_version_props(cpu, model);
1f43671a
XL		 5912
5913 /*
5914 * Properties in versioned CPU model are not user specified features.
5915 * We can simply clear env->user_features here since it will be filled later
5916 * in x86_cpu_expand_features() based on plus_features and minus_features.
5917 */
5918 memset(&env->user_features, 0, sizeof(env->user_features));
c6dc6f63
AP		 5919}
5920
a6506838 5921static const gchar *x86_gdb_arch_name(CPUState *cs)
00fcd100
AB		 5922{
5923#ifdef TARGET_X86_64
a6506838 5924 return "i386:x86-64";
00fcd100 5925#else
a6506838 5926 return "i386";
00fcd100
AB		 5927#endif
5928}
5929
d940ee9b
EH		 5930static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5931{
dcafd1ef 5932 X86CPUModel *model = data;
d940ee9b 5933 X86CPUClass *xcc = X86_CPU_CLASS(oc);
61ad65d0 5934 CPUClass *cc = CPU_CLASS(oc);
d940ee9b 5935
dcafd1ef 5936 xcc->model = model;
bd72159d 5937 xcc->migration_safe = true;
61ad65d0 5938 cc->deprecation_note = model->cpudef->deprecation_note;
d940ee9b
EH		 5939}
5940
dcafd1ef 5941static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5942{
88703ce2 5943 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5944 TypeInfo ti = {
5945 .name = typename,
5946 .parent = TYPE_X86_CPU,
5947 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5948 .class_data = model,
d940ee9b
EH		 5949 };
5950
dcafd1ef 5951 type_register(&ti);
dcafd1ef
EH		 5952}
5953
5b8978d8
CF		 5954
5955/*
5956 * register builtin_x86_defs;
5957 * "max", "base" and subclasses ("host") are not registered here.
5958 * See x86_cpu_register_types for all model registrations.
5959 */
e11fd689 5960static void x86_register_cpudef_types(const X86CPUDefinition *def)
dcafd1ef
EH		 5961{
5962 X86CPUModel *m;
5963 const X86CPUVersionDefinition *vdef;
dcafd1ef 5964
2a923a29
EH		 5965 /* AMD aliases are handled at runtime based on CPUID vendor, so
5966 * they shouldn't be set on the CPU model table.
5967 */
5968 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5969 /* catch mistakes instead of silently truncating model_id when too long */
5970 assert(def->model_id && strlen(def->model_id) <= 48);
5971
dcafd1ef
EH		 5972 /* Unversioned model: */
5973 m = g_new0(X86CPUModel, 1);
5974 m->cpudef = def;
0788a56b
EH		 5975 m->version = CPU_VERSION_AUTO;
5976 m->is_alias = true;
dcafd1ef
EH		 5977 x86_register_cpu_model_type(def->name, m);
5978
5979 /* Versioned models: */
5980
5981 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
88703ce2
EH		 5982 g_autofree char *name =
5983 x86_cpu_versioned_model_name(def, vdef->version);
637123a2
PB		 5984
5985 m = g_new0(X86CPUModel, 1);
dcafd1ef
EH		 5986 m->cpudef = def;
5987 m->version = vdef->version;
c63938df 5988 m->note = vdef->note;
dcafd1ef 5989 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5990
5991 if (vdef->alias) {
5992 X86CPUModel *am = g_new0(X86CPUModel, 1);
5993 am->cpudef = def;
5994 am->version = vdef->version;
0788a56b 5995 am->is_alias = true;
53db89d9
EH		 5996 x86_register_cpu_model_type(vdef->alias, am);
5997 }
dcafd1ef 5998 }
2a923a29 5999
d940ee9b
EH		 6000}
6001
97afb47e
LL		 6002uint32_t cpu_x86_virtual_addr_width(CPUX86State *env)
6003{
6004 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
6005 return 57; /* 57 bits virtual */
6006 } else {
6007 return 48; /* 48 bits virtual */
6008 }
6009}
6010
c6dc6f63
AP		 6011void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
6012 uint32_t *eax, uint32_t *ebx,
6013 uint32_t *ecx, uint32_t *edx)
6014{
6aa9e42f
RH		 6015 X86CPU *cpu = env_archcpu(env);
6016 CPUState *cs = env_cpu(env);
d65af288 6017 uint32_t die_offset;
4ed3d478 6018 uint32_t limit;
1ce36bfe 6019 uint32_t signature[3];
f20dec0b
BM		 6020 X86CPUTopoInfo topo_info;
6021
6022 topo_info.dies_per_pkg = env->nr_dies;
958ac3c4 6023 topo_info.cores_per_die = cs->nr_cores / env->nr_dies;
f20dec0b 6024 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 6025
4ed3d478
DB		 6026 /* Calculate & apply limits for different index ranges */
6027 if (index >= 0xC0000000) {
6028 limit = env->cpuid_xlevel2;
6029 } else if (index >= 0x80000000) {
6030 limit = env->cpuid_xlevel;
1ce36bfe
DB		 6031 } else if (index >= 0x40000000) {
6032 limit = 0x40000001;
c6dc6f63 6033 } else {
4ed3d478
DB		 6034 limit = env->cpuid_level;
6035 }
6036
6037 if (index > limit) {
6038 /* Intel documentation states that invalid EAX input will
6039 * return the same information as EAX=cpuid_level
6040 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
6041 */
6042 index = env->cpuid_level;
c6dc6f63
AP		 6043 }
6044
6045 switch(index) {
6046 case 0:
6047 *eax = env->cpuid_level;
5eb2f7a4
EH		 6048 *ebx = env->cpuid_vendor1;
6049 *edx = env->cpuid_vendor2;
6050 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 6051 break;
6052 case 1:
6053 *eax = env->cpuid_version;
7e72a45c
EH		 6054 *ebx = (cpu->apic_id << 24) |
6055 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 6056 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 6057 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
6058 *ecx |= CPUID_EXT_OSXSAVE;
6059 }
0514ef2f 6060 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 6061 if (cs->nr_cores * cs->nr_threads > 1) {
6062 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 6063 *edx |= CPUID_HT;
c6dc6f63 6064 }
ea39f9b6
LX		 6065 if (!cpu->enable_pmu) {
6066 *ecx &= ~CPUID_EXT_PDCM;
6067 }
c6dc6f63
AP		 6068 break;
6069 case 2:
6070 /* cache info: needed for Pentium Pro compatibility */
787aaf57 6071 if (cpu->cache_info_passthrough) {
798d8ec0 6072 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57 6073 break;
a7a0da84
MR		 6074 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
6075 *eax = *ebx = *ecx = *edx = 0;
6076 break;
787aaf57 6077 }
5e891bf8 6078 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 6079 *ebx = 0;
14c985cf
LM		 6080 if (!cpu->enable_l3_cache) {
6081 *ecx = 0;
6082 } else {
a9f27ea9 6083 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 6084 }
a9f27ea9
EH		 6085 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
6086 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
6087 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 6088 break;
6089 case 4:
6090 /* cache info: needed for Core compatibility */
787aaf57 6091 if (cpu->cache_info_passthrough) {
798d8ec0 6092 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
d7caf13b
IM		 6093 /*
6094 * QEMU has its own number of cores/logical cpus,
6095 * set 24..14, 31..26 bit to configured values
6096 */
6097 if (*eax & 31) {
6098 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
958ac3c4 6099 int vcpus_per_socket = cs->nr_cores * cs->nr_threads;
d7caf13b
IM		 6100 if (cs->nr_cores > 1) {
6101 *eax &= ~0xFC000000;
6102 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
6103 }
6104 if (host_vcpus_per_cache > vcpus_per_socket) {
6105 *eax &= ~0x3FFC000;
6106 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
6107 }
7e3482f8 6108 }
a7a0da84
MR		 6109 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
6110 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 6111 } else {
2f7a21c4 6112 *eax = 0;
76c2975a 6113 switch (count) {
c6dc6f63 6114 case 0: /* L1 dcache info */
a9f27ea9
EH		 6115 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
6116 1, cs->nr_cores,
7e3482f8 6117 eax, ebx, ecx, edx);
c6dc6f63
AP		 6118 break;
6119 case 1: /* L1 icache info */
a9f27ea9
EH		 6120 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
6121 1, cs->nr_cores,
7e3482f8 6122 eax, ebx, ecx, edx);
c6dc6f63
AP		 6123 break;
6124 case 2: /* L2 cache info */
a9f27ea9
EH		 6125 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
6126 cs->nr_threads, cs->nr_cores,
7e3482f8 6127 eax, ebx, ecx, edx);
c6dc6f63 6128 break;
14c985cf 6129 case 3: /* L3 cache info */
f20dec0b 6130 die_offset = apicid_die_offset(&topo_info);
7e3482f8 6131 if (cpu->enable_l3_cache) {
a9f27ea9 6132 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 6133 (1 << die_offset), cs->nr_cores,
7e3482f8 6134 eax, ebx, ecx, edx);
14c985cf
LM		 6135 break;
6136 }
7e3482f8 6137 /* fall through */
c6dc6f63 6138 default: /* end of info */
7e3482f8 6139 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 6140 break;
76c2975a
PB		 6141 }
6142 }
c6dc6f63
AP		 6143 break;
6144 case 5:
2266d443
MT		 6145 /* MONITOR/MWAIT Leaf */
6146 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
6147 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
6148 *ecx = cpu->mwait.ecx; /* flags */
6149 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 6150 break;
6151 case 6:
6152 /* Thermal and Power Leaf */
28b8e4d0 6153 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 6154 *ebx = 0;
6155 *ecx = 0;
6156 *edx = 0;
6157 break;
f7911686 6158 case 7:
13526728
EH		 6159 /* Structured Extended Feature Flags Enumeration Leaf */
6160 if (count == 0) {
d0474024
PMD		 6161 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused;
6162
80db491d
JL		 6163 /* Maximum ECX value for sub-leaves */
6164 *eax = env->cpuid_level_func7;
0514ef2f 6165 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 6166 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 6167 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
6168 *ecx |= CPUID_7_0_ECX_OSPKE;
6169 }
95ea69fb 6170 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
1dec2e1f
SC		 6171
6172 /*
6173 * SGX cannot be emulated in software. If hardware does not
6174 * support enabling SGX and/or SGX flexible launch control,
6175 * then we need to update the VM's CPUID values accordingly.
6176 */
d0474024
PMD		 6177 x86_cpu_get_supported_cpuid(0x7, 0,
6178 &eax_0_unused, &ebx_0,
6179 &ecx_0, &edx_0_unused);
6180 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) {
1dec2e1f
SC		 6181 *ebx &= ~CPUID_7_0_EBX_SGX;
6182 }
6183
d0474024
PMD		 6184 if ((*ecx & CPUID_7_0_ECX_SGX_LC)
6185 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) {
1dec2e1f
SC		 6186 *ecx &= ~CPUID_7_0_ECX_SGX_LC;
6187 }
80db491d
JL		 6188 } else if (count == 1) {
6189 *eax = env->features[FEAT_7_1_EAX];
eaaa197d 6190 *edx = env->features[FEAT_7_1_EDX];
80db491d
JL		 6191 *ebx = 0;
6192 *ecx = 0;
9dd8b710
TS		 6193 } else if (count == 2) {
6194 *edx = env->features[FEAT_7_2_EDX];
6195 *eax = 0;
6196 *ebx = 0;
6197 *ecx = 0;
f7911686
YW		 6198 } else {
6199 *eax = 0;
6200 *ebx = 0;
6201 *ecx = 0;
6202 *edx = 0;
6203 }
6204 break;
c6dc6f63
AP		 6205 case 9:
6206 /* Direct Cache Access Information Leaf */
6207 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
6208 *ebx = 0;
6209 *ecx = 0;
6210 *edx = 0;
6211 break;
6212 case 0xA:
6213 /* Architectural Performance Monitoring Leaf */
da472f94 6214 if (cpu->enable_pmu) {
d19d6ffa 6215 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx);
a0fa8208
GN		 6216 } else {
6217 *eax = 0;
6218 *ebx = 0;
6219 *ecx = 0;
6220 *edx = 0;
6221 }
c6dc6f63 6222 break;
5232d00a
RK		 6223 case 0xB:
6224 /* Extended Topology Enumeration Leaf */
6225 if (!cpu->enable_cpuid_0xb) {
6226 *eax = *ebx = *ecx = *edx = 0;
6227 break;
6228 }
6229
6230 *ecx = count & 0xff;
6231 *edx = cpu->apic_id;
6232
6233 switch (count) {
6234 case 0:
f20dec0b 6235 *eax = apicid_core_offset(&topo_info);
eab60fb9 6236 *ebx = cs->nr_threads;
5232d00a
RK		 6237 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
6238 break;
6239 case 1:
fb49865d 6240 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 6241 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 6242 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
6243 break;
6244 default:
6245 *eax = 0;
6246 *ebx = 0;
6247 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
6248 }
6249
a94e1428
LX		 6250 assert(!(*eax & ~0x1f));
6251 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
6252 break;
c3c67679 6253 case 0x1C:
da472f94 6254 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
c3c67679
YW		 6255 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx);
6256 *edx = 0;
6257 }
6258 break;
a94e1428
LX		 6259 case 0x1F:
6260 /* V2 Extended Topology Enumeration Leaf */
6261 if (env->nr_dies < 2) {
6262 *eax = *ebx = *ecx = *edx = 0;
6263 break;
6264 }
6265
6266 *ecx = count & 0xff;
6267 *edx = cpu->apic_id;
6268 switch (count) {
6269 case 0:
f20dec0b 6270 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 6271 *ebx = cs->nr_threads;
6272 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
6273 break;
6274 case 1:
f20dec0b 6275 *eax = apicid_die_offset(&topo_info);
958ac3c4 6276 *ebx = topo_info.cores_per_die * topo_info.threads_per_core;
a94e1428
LX		 6277 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
6278 break;
6279 case 2:
fb49865d 6280 *eax = apicid_pkg_offset(&topo_info);
958ac3c4 6281 *ebx = cs->nr_cores * cs->nr_threads;
a94e1428
LX		 6282 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
6283 break;
6284 default:
6285 *eax = 0;
6286 *ebx = 0;
6287 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
6288 }
5232d00a
RK		 6289 assert(!(*eax & ~0x1f));
6290 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
6291 break;
2560f19f 6292 case 0xD: {
51e49430 6293 /* Processor Extended State */
2560f19f
PB		 6294 *eax = 0;
6295 *ebx = 0;
6296 *ecx = 0;
6297 *edx = 0;
19dc85db 6298 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 6299 break;
6300 }
4928cd6d 6301
2560f19f 6302 if (count == 0) {
301e9067
YW		 6303 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false);
6304 *eax = env->features[FEAT_XSAVE_XCR0_LO];
6305 *edx = env->features[FEAT_XSAVE_XCR0_HI];
76ecd7a5
BS		 6306 /*
6307 * The initial value of xcr0 and ebx == 0, On host without kvm
6308 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
6309 * even through guest update xcr0, this will crash some legacy guest
bad5cfcd 6310 * (e.g., CentOS 6), So set ebx == ecx to workaround it.
76ecd7a5 6311 */
301e9067 6312 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false);
2560f19f 6313 } else if (count == 1) {
301e9067
YW		 6314 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) |
6315 x86_cpu_xsave_xss_components(cpu);
6316
0bb0b2d2 6317 *eax = env->features[FEAT_XSAVE];
301e9067
YW		 6318 *ebx = xsave_area_size(xstate, true);
6319 *ecx = env->features[FEAT_XSAVE_XSS_LO];
6320 *edx = env->features[FEAT_XSAVE_XSS_HI];
c3c67679
YW		 6321 if (kvm_enabled() && cpu->enable_pmu &&
6322 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) &&
6323 (*eax & CPUID_XSAVE_XSAVES)) {
6324 *ecx |= XSTATE_ARCH_LBR_MASK;
6325 } else {
6326 *ecx &= ~XSTATE_ARCH_LBR_MASK;
6327 }
da472f94
PMD		 6328 } else if (count == 0xf && cpu->enable_pmu
6329 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
c3c67679 6330 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx);
f4f1110e 6331 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
301e9067
YW		 6332 const ExtSaveArea *esa = &x86_ext_save_areas[count];
6333
6334 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) {
33f373d7
LJ		 6335 *eax = esa->size;
6336 *ebx = esa->offset;
0f17f6b3
JL		 6337 *ecx = esa->ecx &
6338 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
301e9067
YW		 6339 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) {
6340 *eax = esa->size;
6341 *ebx = 0;
6342 *ecx = 1;
2560f19f 6343 }
51e49430
SY		 6344 }
6345 break;
2560f19f 6346 }
1dec2e1f
SC		 6347 case 0x12:
6348#ifndef CONFIG_USER_ONLY
6349 if (!kvm_enabled() ||
6350 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) {
6351 *eax = *ebx = *ecx = *edx = 0;
6352 break;
6353 }
6354
6355 /*
6356 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
6357 * the EPC properties, e.g. confidentiality and integrity, from the
6358 * host's first EPC section, i.e. assume there is one EPC section or
6359 * that all EPC sections have the same security properties.
6360 */
6361 if (count > 1) {
6362 uint64_t epc_addr, epc_size;
6363
6364 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) {
6365 *eax = *ebx = *ecx = *edx = 0;
6366 break;
6367 }
6368 host_cpuid(index, 2, eax, ebx, ecx, edx);
6369 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1;
6370 *ebx = (uint32_t)(epc_addr >> 32);
6371 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf);
6372 *edx = (uint32_t)(epc_size >> 32);
6373 break;
6374 }
6375
6376 /*
6377 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
6378 * and KVM, i.e. QEMU cannot emulate features to override what KVM
6379 * supports. Features can be further restricted by userspace, but not
6380 * made more permissive.
6381 */
b0f3184e 6382 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx);
1dec2e1f
SC		 6383
6384 if (count == 0) {
6385 *eax &= env->features[FEAT_SGX_12_0_EAX];
6386 *ebx &= env->features[FEAT_SGX_12_0_EBX];
6387 } else {
6388 *eax &= env->features[FEAT_SGX_12_1_EAX];
6389 *ebx &= 0; /* ebx reserve */
72497cff
YZ		 6390 *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
6391 *edx &= env->features[FEAT_XSAVE_XCR0_HI];
1dec2e1f
SC		 6392
6393 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
6394 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
6395
6396 /* Access to PROVISIONKEY requires additional credentials. */
c22f5467
SC		 6397 if ((*eax & (1U << 4)) &&
6398 !kvm_enable_sgx_provisioning(cs->kvm_state)) {
6399 *eax &= ~(1U << 4);
6400 }
1dec2e1f
SC		 6401 }
6402#endif
6403 break;
e37a5c7f
CP		 6404 case 0x14: {
6405 /* Intel Processor Trace Enumeration */
6406 *eax = 0;
6407 *ebx = 0;
6408 *ecx = 0;
6409 *edx = 0;
6410 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
6411 !kvm_enabled()) {
6412 break;
6413 }
6414
028ade14
PB		 6415 /*
6416 * If these are changed, they should stay in sync with
6417 * x86_cpu_filter_features().
6418 */
e37a5c7f
CP		 6419 if (count == 0) {
6420 *eax = INTEL_PT_MAX_SUBLEAF;
6421 *ebx = INTEL_PT_MINIMAL_EBX;
6422 *ecx = INTEL_PT_MINIMAL_ECX;
d1615ea5
LK		 6423 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
6424 *ecx |= CPUID_14_0_ECX_LIP;
6425 }
e37a5c7f
CP		 6426 } else if (count == 1) {
6427 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
6428 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
6429 }
6430 break;
6431 }
f21a4817 6432 case 0x1D: {
7eb061b0 6433 /* AMX TILE, for now hardcoded for Sapphire Rapids*/
f21a4817
JL		 6434 *eax = 0;
6435 *ebx = 0;
6436 *ecx = 0;
6437 *edx = 0;
6438 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6439 break;
6440 }
6441
6442 if (count == 0) {
6443 /* Highest numbered palette subleaf */
6444 *eax = INTEL_AMX_TILE_MAX_SUBLEAF;
6445 } else if (count == 1) {
6446 *eax = INTEL_AMX_TOTAL_TILE_BYTES |
6447 (INTEL_AMX_BYTES_PER_TILE << 16);
6448 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16);
6449 *ecx = INTEL_AMX_TILE_MAX_ROWS;
6450 }
6451 break;
6452 }
6453 case 0x1E: {
7eb061b0 6454 /* AMX TMUL, for now hardcoded for Sapphire Rapids */
f21a4817
JL		 6455 *eax = 0;
6456 *ebx = 0;
6457 *ecx = 0;
6458 *edx = 0;
6459 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) {
6460 break;
6461 }
6462
6463 if (count == 0) {
6464 /* Highest numbered palette subleaf */
6465 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8);
6466 }
6467 break;
6468 }
1ce36bfe
DB		 6469 case 0x40000000:
6470 /*
6471 * CPUID code in kvm_arch_init_vcpu() ignores stuff
6472 * set here, but we restrict to TCG none the less.
6473 */
6474 if (tcg_enabled() && cpu->expose_tcg) {
6475 memcpy(signature, "TCGTCGTCGTCG", 12);
6476 *eax = 0x40000001;
6477 *ebx = signature[0];
6478 *ecx = signature[1];
6479 *edx = signature[2];
6480 } else {
6481 *eax = 0;
6482 *ebx = 0;
6483 *ecx = 0;
6484 *edx = 0;
6485 }
6486 break;
6487 case 0x40000001:
6488 *eax = 0;
6489 *ebx = 0;
6490 *ecx = 0;
6491 *edx = 0;
6492 break;
c6dc6f63
AP		 6493 case 0x80000000:
6494 *eax = env->cpuid_xlevel;
6495 *ebx = env->cpuid_vendor1;
6496 *edx = env->cpuid_vendor2;
6497 *ecx = env->cpuid_vendor3;
6498 break;
6499 case 0x80000001:
6500 *eax = env->cpuid_version;
6501 *ebx = 0;
0514ef2f
EH		 6502 *ecx = env->features[FEAT_8000_0001_ECX];
6503 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 6504
6505 /* The Linux kernel checks for the CMPLegacy bit and
6506 * discards multiple thread information if it is set.
cb8d4c8f 6507 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 6508 */
ce3960eb 6509 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 6510 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
6511 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
6512 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 6513 *ecx |= 1 << 1; /* CmpLegacy bit */
6514 }
6515 }
fd5dcb1c
PB		 6516 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 &&
6517 !(env->hflags & HF_LMA_MASK)) {
6518 *edx &= ~CPUID_EXT2_SYSCALL;
6519 }
c6dc6f63
AP		 6520 break;
6521 case 0x80000002:
6522 case 0x80000003:
6523 case 0x80000004:
6524 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
6525 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
6526 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
6527 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
6528 break;
6529 case 0x80000005:
6530 /* cache info (L1 cache) */
787aaf57 6531 if (cpu->cache_info_passthrough) {
798d8ec0 6532 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6533 break;
6534 }
78ee6bd0 6535 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5e891bf8 6536 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
78ee6bd0 6537 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5e891bf8 6538 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6539 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
6540 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 6541 break;
6542 case 0x80000006:
6543 /* cache info (L2 cache) */
787aaf57 6544 if (cpu->cache_info_passthrough) {
798d8ec0 6545 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx);
787aaf57
BC		 6546 break;
6547 }
78ee6bd0
PMD		 6548 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
6549 (L2_DTLB_2M_ENTRIES << 16) |
6550 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5e891bf8 6551 (L2_ITLB_2M_ENTRIES);
78ee6bd0
PMD		 6552 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
6553 (L2_DTLB_4K_ENTRIES << 16) |
6554 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5e891bf8 6555 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 6556 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
6557 cpu->enable_l3_cache ?
6558 env->cache_info_amd.l3_cache : NULL,
6559 ecx, edx);
c6dc6f63 6560 break;
303752a9
MT		 6561 case 0x80000007:
6562 *eax = 0;
6563 *ebx = 0;
6564 *ecx = 0;
6565 *edx = env->features[FEAT_8000_0007_EDX];
6566 break;
c6dc6f63
AP		 6567 case 0x80000008:
6568 /* virtual & phys address size in low 2 bytes. */
97afb47e 6569 *eax = cpu->phys_bits;
0514ef2f 6570 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21 6571 /* 64 bit processor */
97afb47e 6572 *eax |= (cpu_x86_virtual_addr_width(env) << 8);
c6dc6f63 6573 }
1b3420e1 6574 *ebx = env->features[FEAT_8000_0008_EBX];
ce3960eb 6575 if (cs->nr_cores * cs->nr_threads > 1) {
cac9edfc
BM		 6576 /*
6577 * Bits 15:12 is "The number of bits in the initial
6578 * Core::X86::Apic::ApicId[ApicId] value that indicate
fb49865d 6579 * thread ID within a package".
cac9edfc
BM		 6580 * Bits 7:0 is "The number of threads in the package is NC+1"
6581 */
fb49865d 6582 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
cac9edfc
BM		 6583 ((cs->nr_cores * cs->nr_threads) - 1);
6584 } else {
6585 *ecx = 0;
c6dc6f63 6586 }
cac9edfc 6587 *edx = 0;
c6dc6f63
AP		 6588 break;
6589 case 0x8000000A:
0514ef2f 6590 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 6591 *eax = 0x00000001; /* SVM Revision */
6592 *ebx = 0x00000010; /* nr of ASIDs */
6593 *ecx = 0;
0514ef2f 6594 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 6595 } else {
6596 *eax = 0;
6597 *ebx = 0;
6598 *ecx = 0;
6599 *edx = 0;
6600 }
c6dc6f63 6601 break;
8f4202fb
BM		 6602 case 0x8000001D:
6603 *eax = 0;
a4e0b436 6604 if (cpu->cache_info_passthrough) {
798d8ec0 6605 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
a4e0b436
SL		 6606 break;
6607 }
8f4202fb
BM		 6608 switch (count) {
6609 case 0: /* L1 dcache info */
2f084d1e
BM		 6610 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
6611 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6612 break;
6613 case 1: /* L1 icache info */
2f084d1e
BM		 6614 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
6615 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6616 break;
6617 case 2: /* L2 cache info */
2f084d1e
BM		 6618 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
6619 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6620 break;
6621 case 3: /* L3 cache info */
2f084d1e
BM		 6622 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
6623 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 6624 break;
6625 default: /* end of info */
6626 *eax = *ebx = *ecx = *edx = 0;
6627 break;
6628 }
6629 break;
ed78467a 6630 case 0x8000001E:
35ac5dfb
BM		 6631 if (cpu->core_id <= 255) {
6632 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
6633 } else {
6634 *eax = 0;
6635 *ebx = 0;
6636 *ecx = 0;
6637 *edx = 0;
6638 }
ed78467a 6639 break;
b3baa152
BW		 6640 case 0xC0000000:
6641 *eax = env->cpuid_xlevel2;
6642 *ebx = 0;
6643 *ecx = 0;
6644 *edx = 0;
6645 break;
6646 case 0xC0000001:
6647 /* Support for VIA CPU's CPUID instruction */
6648 *eax = env->cpuid_version;
6649 *ebx = 0;
6650 *ecx = 0;
0514ef2f 6651 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 6652 break;
6653 case 0xC0000002:
6654 case 0xC0000003:
6655 case 0xC0000004:
6656 /* Reserved for the future, and now filled with zero */
6657 *eax = 0;
6658 *ebx = 0;
6659 *ecx = 0;
6660 *edx = 0;
6661 break;
6cb8f2a6 6662 case 0x8000001F:
02eacf31
PMD		 6663 *eax = *ebx = *ecx = *edx = 0;
6664 if (sev_enabled()) {
6665 *eax = 0x2;
6666 *eax |= sev_es_enabled() ? 0x8 : 0;
fb6bbafc
TL		 6667 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
6668 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
02eacf31 6669 }
6cb8f2a6 6670 break;
b70eec31
BM		 6671 case 0x80000021:
6672 *eax = env->features[FEAT_8000_0021_EAX];
6673 *ebx = *ecx = *edx = 0;
6674 break;
c6dc6f63
AP		 6675 default:
6676 /* reserved values: zero */
6677 *eax = 0;
6678 *ebx = 0;
6679 *ecx = 0;
6680 *edx = 0;
6681 break;
6682 }
6683}
5fd2087a 6684
db888065
SC		 6685static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
6686{
6687#ifndef CONFIG_USER_ONLY
6688 /* Those default values are defined in Skylake HW */
6689 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
6690 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
6691 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
6692 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
6693#endif
6694}
6695
e86787d3 6696static void x86_cpu_reset_hold(Object *obj)
5fd2087a 6697{
e86787d3 6698 CPUState *s = CPU(obj);
5fd2087a
AF		 6699 X86CPU *cpu = X86_CPU(s);
6700 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
6701 CPUX86State *env = &cpu->env;
a114d25d
RH		 6702 target_ulong cr4;
6703 uint64_t xcr0;
c1958aea
AF		 6704 int i;
6705
e86787d3
PM		 6706 if (xcc->parent_phases.hold) {
6707 xcc->parent_phases.hold(obj);
6708 }
5fd2087a 6709
5e992a8e 6710 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 6711
c1958aea
AF		 6712 env->old_exception = -1;
6713
6714 /* init to reset state */
e3126a5c 6715 env->int_ctl = 0;
c1958aea 6716 env->hflags2 |= HF2_GIF_MASK;
b67e2796 6717 env->hflags2 |= HF2_VGIF_MASK;
b16c0e20 6718 env->hflags &= ~HF_GUEST_MASK;
c1958aea
AF		 6719
6720 cpu_x86_update_cr0(env, 0x60000010);
6721 env->a20_mask = ~0x0;
6722 env->smbase = 0x30000;
e13713db 6723 env->msr_smi_count = 0;
c1958aea
AF		 6724
6725 env->idt.limit = 0xffff;
6726 env->gdt.limit = 0xffff;
6727 env->ldt.limit = 0xffff;
6728 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
6729 env->tr.limit = 0xffff;
6730 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
6731
6732 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
6733 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
6734 DESC_R_MASK | DESC_A_MASK);
6735 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
6736 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6737 DESC_A_MASK);
6738 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
6739 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6740 DESC_A_MASK);
6741 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6742 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6743 DESC_A_MASK);
6744 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6745 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6746 DESC_A_MASK);
6747 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6748 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6749 DESC_A_MASK);
6750
6751 env->eip = 0xfff0;
6752 env->regs[R_EDX] = env->cpuid_version;
6753
6754 env->eflags = 0x2;
6755
6756 /* FPU init */
6757 for (i = 0; i < 8; i++) {
6758 env->fptags[i] = 1;
6759 }
5bde1407 6760 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 6761
6762 env->mxcsr = 0x1f80;
a114d25d
RH		 6763 /* All units are in INIT state. */
6764 env->xstate_bv = 0;
c1958aea
AF		 6765
6766 env->pat = 0x0007040600070406ULL;
5286c366
PB		 6767
6768 if (kvm_enabled()) {
6769 /*
6770 * KVM handles TSC = 0 specially and thinks we are hot-plugging
6771 * a new CPU, use 1 instead to force a reset.
6772 */
6773 if (env->tsc != 0) {
6774 env->tsc = 1;
6775 }
6776 } else {
6777 env->tsc = 0;
6778 }
6779
c1958aea 6780 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 6781 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6782 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6783 }
c1958aea
AF		 6784
6785 memset(env->dr, 0, sizeof(env->dr));
6786 env->dr[6] = DR6_FIXED_1;
6787 env->dr[7] = DR7_FIXED_1;
b3310ab3 6788 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 6789 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 6790
a114d25d 6791 cr4 = 0;
cfc3b074 6792 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 6793
6794#ifdef CONFIG_USER_ONLY
6795 /* Enable all the features for user-mode. */
6796 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 6797 xcr0 |= XSTATE_SSE_MASK;
a114d25d 6798 }
0f70ed47
PB		 6799 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6800 const ExtSaveArea *esa = &x86_ext_save_areas[i];
301e9067
YW		 6801 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) {
6802 continue;
6803 }
9646f492 6804 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 6805 xcr0 |= 1ull << i;
6806 }
a114d25d 6807 }
0f70ed47 6808
a114d25d
RH		 6809 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6810 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6811 }
07929f2a
RH		 6812 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6813 cr4 |= CR4_FSGSBASE_MASK;
6814 }
a114d25d
RH		 6815#endif
6816
6817 env->xcr0 = xcr0;
6818 cpu_x86_update_cr4(env, cr4);
0522604b 6819
9db2efd9
AW		 6820 /*
6821 * SDM 11.11.5 requires:
6822 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6823 * - IA32_MTRR_PHYSMASKn.V = 0
6824 * All other bits are undefined. For simplification, zero it all.
6825 */
6826 env->mtrr_deftype = 0;
6827 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6828 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6829
b7394c83 6830 env->interrupt_injected = -1;
fd13f23b
LA		 6831 env->exception_nr = -1;
6832 env->exception_pending = 0;
6833 env->exception_injected = 0;
6834 env->exception_has_payload = false;
6835 env->exception_payload = 0;
b7394c83 6836 env->nmi_injected = false;
12f89a39 6837 env->triple_fault_pending = false;
dd673288
IM		 6838#if !defined(CONFIG_USER_ONLY)
6839 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 6840 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 6841
259186a7 6842 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 6843
6844 if (kvm_enabled()) {
6845 kvm_arch_reset_vcpu(cpu);
6846 }
db888065
SC		 6847
6848 x86_cpu_set_sgxlepubkeyhash(env);
cabf9862 6849
3e4546d5 6850 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
cabf9862 6851
dd673288 6852#endif
5fd2087a
AF		 6853}
6854
ec19444a
MS		 6855void x86_cpu_after_reset(X86CPU *cpu)
6856{
6857#ifndef CONFIG_USER_ONLY
6858 if (kvm_enabled()) {
6859 kvm_arch_after_reset_vcpu(cpu);
6860 }
6861
6862 if (cpu->apic_state) {
08c4f4db 6863 device_cold_reset(cpu->apic_state);
ec19444a
MS		 6864 }
6865#endif
6866}
6867
de024815
AF		 6868static void mce_init(X86CPU *cpu)
6869{
6870 CPUX86State *cenv = &cpu->env;
6871 unsigned int bank;
6872
6873 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 6874 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 6875 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 6876 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6877 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 6878 cenv->mcg_ctl = ~(uint64_t)0;
6879 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6880 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6881 }
6882 }
6883}
6884
c39c0edf
EH		 6885static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6886{
6887 if (*min < value) {
6888 *min = value;
6889 }
6890}
6891
6892/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6893static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6894{
6895 CPUX86State *env = &cpu->env;
6896 FeatureWordInfo *fi = &feature_word_info[w];
07585923 6897 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 6898 uint32_t region = eax & 0xF0000000;
6899
07585923 6900 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 6901 if (!env->features[w]) {
6902 return;
6903 }
6904
6905 switch (region) {
6906 case 0x00000000:
6907 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6908 break;
6909 case 0x80000000:
6910 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6911 break;
6912 case 0xC0000000:
6913 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6914 break;
6915 }
80db491d
JL		 6916
6917 if (eax == 7) {
6918 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6919 fi->cpuid.ecx);
6920 }
c39c0edf
EH		 6921}
6922
2ca8a8be
EH		 6923/* Calculate XSAVE components based on the configured CPU feature flags */
6924static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6925{
6926 CPUX86State *env = &cpu->env;
6927 int i;
96193c22 6928 uint64_t mask;
19db68ca 6929 static bool request_perm;
2ca8a8be
EH		 6930
6931 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
301e9067
YW		 6932 env->features[FEAT_XSAVE_XCR0_LO] = 0;
6933 env->features[FEAT_XSAVE_XCR0_HI] = 0;
81f5cad3
XL		 6934 env->features[FEAT_XSAVE_XSS_LO] = 0;
6935 env->features[FEAT_XSAVE_XSS_HI] = 0;
2ca8a8be
EH		 6936 return;
6937 }
6938
e3c9022b
EH		 6939 mask = 0;
6940 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6941 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6942 if (env->features[esa->feature] & esa->bits) {
96193c22 6943 mask |= (1ULL << i);
2ca8a8be
EH		 6944 }
6945 }
6946
19db68ca
YZ		 6947 /* Only request permission for first vcpu */
6948 if (kvm_enabled() && !request_perm) {
6949 kvm_request_xsave_components(cpu, mask);
6950 request_perm = true;
6951 }
6952
301e9067 6953 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK;
a11a3651 6954 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32;
301e9067 6955 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK;
a11a3651 6956 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32;
2ca8a8be
EH		 6957}
6958
b8d834a0
EH		 6959/***** Steps involved on loading and filtering CPUID data
6960 *
6961 * When initializing and realizing a CPU object, the steps
6962 * involved in setting up CPUID data are:
6963 *
6964 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6965 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6966 * transparent, as it is done automatically by instance_init.
6967 * No code should need to look at X86CPUDefinition structs
6968 * outside instance_init.
6969 *
6970 * 2) CPU expansion. This is done by realize before CPUID
6971 * filtering, and will make sure host/accelerator data is
6972 * loaded for CPU models that depend on host capabilities
6973 * (e.g. "host"). Done by x86_cpu_expand_features().
6974 *
6975 * 3) CPUID filtering. This initializes extra data related to
6976 * CPUID, and checks if the host supports all capabilities
6977 * required by the CPU. Runnability of a CPU model is
6978 * determined at this step. Done by x86_cpu_filter_features().
6979 *
6980 * Some operations don't require all steps to be performed.
6981 * More precisely:
6982 *
6983 * - CPU instance creation (instance_init) will run only CPU
6984 * model loading. CPU expansion can't run at instance_init-time
6985 * because host/accelerator data may be not available yet.
6986 * - CPU realization will perform both CPU model expansion and CPUID
6987 * filtering, and return an error in case one of them fails.
6988 * - query-cpu-definitions needs to run all 3 steps. It needs
6989 * to run CPUID filtering, as the 'unavailable-features'
6990 * field is set based on the filtering results.
6991 * - The query-cpu-model-expansion QMP command only needs to run
6992 * CPU model loading and CPU expansion. It should not filter
6993 * any CPUID data based on host capabilities.
6994 */
6995
6996/* Expand CPU configuration data, based on configured features
6997 * and host/accelerator capabilities when appropriate.
6998 */
79f1a68a 6999void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 7000{
b34d12d1 7001 CPUX86State *env = &cpu->env;
dc15c051 7002 FeatureWord w;
99e24dbd 7003 int i;
2fae0d96 7004 GList *l;
9886e834 7005
99e24dbd
PB		 7006 for (l = plus_features; l; l = l->next) {
7007 const char *prop = l->data;
992861fb
MA		 7008 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
7009 return;
99e24dbd
PB		 7010 }
7011 }
7012
7013 for (l = minus_features; l; l = l->next) {
7014 const char *prop = l->data;
992861fb
MA		 7015 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
7016 return;
99e24dbd
PB		 7017 }
7018 }
7019
d4a606b3
EH		 7020 /*TODO: Now cpu->max_features doesn't overwrite features
7021 * set using QOM properties, and we can convert
dc15c051
IM		 7022 * plus_features & minus_features to global properties
7023 * inside x86_cpu_parse_featurestr() too.
7024 */
44bd8e53 7025 if (cpu->max_features) {
dc15c051 7026 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 7027 /* Override only features that weren't set explicitly
7028 * by the user.
7029 */
7030 env->features[w] |=
7031 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
78ee6bd0 7032 ~env->user_features[w] &
0d914f39 7033 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 7034 }
7035 }
7036
99e24dbd
PB		 7037 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
7038 FeatureDep *d = &feature_dependencies[i];
7039 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 7040 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 7041
99e24dbd
PB		 7042 /* Not an error unless the dependent feature was added explicitly. */
7043 mark_unavailable_features(cpu, d->to.index,
7044 unavailable_features & env->user_features[d->to.index],
7045 "This feature depends on other features that were not requested");
7046
99e24dbd 7047 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 7048 }
dc15c051
IM		 7049 }
7050
aec661de
EH		 7051 if (!kvm_enabled() || !cpu->expose_kvm) {
7052 env->features[FEAT_KVM] = 0;
7053 }
7054
2ca8a8be 7055 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 7056
7057 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
7058 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
7059 if (cpu->full_cpuid_auto_level) {
7060 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
7061 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
7062 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
7063 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 7064 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
8731336e 7065 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX);
9dd8b710 7066 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX);
c39c0edf
EH		 7067 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
7068 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
7069 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 7070 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 7071 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
7072 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
7073 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 7074
7075 /* Intel Processor Trace requires CPUID[0x14] */
ddc2fc9e
LK		 7076 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
7077 if (cpu->intel_pt_auto_level) {
7078 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
7079 } else if (cpu->env.cpuid_min_level < 0x14) {
7080 mark_unavailable_features(cpu, FEAT_7_0_EBX,
7081 CPUID_7_0_EBX_INTEL_PT,
b7d77f5a 7082 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
ddc2fc9e 7083 }
f24c3a79
LK		 7084 }
7085
760746ac
ZP		 7086 /*
7087 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
7088 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
7089 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
7090 * cpu->vendor_cpuid_only has been unset for compatibility with older
7091 * machine types.
7092 */
7093 if ((env->nr_dies > 1) &&
7094 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) {
a94e1428
LX		 7095 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
7096 }
7097
0c3d7c00
EH		 7098 /* SVM requires CPUID[0x8000000A] */
7099 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
7100 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
7101 }
6cb8f2a6
BS		 7102
7103 /* SEV requires CPUID[0x8000001F] */
7104 if (sev_enabled()) {
7105 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
7106 }
dca6cffc 7107
b70eec31
BM		 7108 if (env->features[FEAT_8000_0021_EAX]) {
7109 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
7110 }
7111
dca6cffc
SC		 7112 /* SGX requires CPUID[0x12] for EPC enumeration */
7113 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
7114 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
7115 }
c39c0edf
EH		 7116 }
7117
7118 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 7119 if (env->cpuid_level_func7 == UINT32_MAX) {
7120 env->cpuid_level_func7 = env->cpuid_min_level_func7;
7121 }
c39c0edf
EH		 7122 if (env->cpuid_level == UINT32_MAX) {
7123 env->cpuid_level = env->cpuid_min_level;
7124 }
7125 if (env->cpuid_xlevel == UINT32_MAX) {
7126 env->cpuid_xlevel = env->cpuid_min_xlevel;
7127 }
7128 if (env->cpuid_xlevel2 == UINT32_MAX) {
7129 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 7130 }
071ce4b0 7131
652a5f22
PMD		 7132 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) {
7133 return;
071ce4b0 7134 }
41f3d4d6
EH		 7135}
7136
b8d834a0
EH		 7137/*
7138 * Finishes initialization of CPUID data, filters CPU feature
7139 * words based on host availability of each feature.
7140 *
7141 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
7142 */
245edd0c 7143static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 7144{
7145 CPUX86State *env = &cpu->env;
7146 FeatureWord w;
245edd0c
PB		 7147 const char *prefix = NULL;
7148
7149 if (verbose) {
7150 prefix = accel_uses_host_cpuid()
7151 ? "host doesn't support requested feature"
7152 : "TCG doesn't support requested feature";
7153 }
b8d834a0
EH		 7154
7155 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 7156 uint64_t host_feat =
b8d834a0 7157 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 7158 uint64_t requested_features = env->features[w];
7159 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 7160 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 7161 }
7162
028ade14
PB		 7163 /*
7164 * Check that KVM actually allows the processor tracing features that
7165 * are advertised by cpu_x86_cpuid(). Keep these two in sync.
7166 */
7167 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
7168 kvm_enabled()) {
d0474024
PMD		 7169 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused;
7170 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused;
7171
7172 x86_cpu_get_supported_cpuid(0x14, 0,
7173 &eax_0, &ebx_0, &ecx_0, &edx_0_unused);
7174 x86_cpu_get_supported_cpuid(0x14, 1,
7175 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused);
e37a5c7f
CP		 7176
7177 if (!eax_0 ||
7178 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
7179 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
7180 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
7181 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
7182 INTEL_PT_ADDR_RANGES_NUM) ||
7183 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96 7184 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
d1615ea5
LK		 7185 ((ecx_0 & CPUID_14_0_ECX_LIP) !=
7186 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
e37a5c7f
CP		 7187 /*
7188 * Processor Trace capabilities aren't configurable, so if the
7189 * host can't emulate the capabilities we report on
7190 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
7191 */
245edd0c 7192 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 7193 }
7194 }
b8d834a0
EH		 7195}
7196
08856771
VK		 7197static void x86_cpu_hyperv_realize(X86CPU *cpu)
7198{
7199 size_t len;
7200
7201 /* Hyper-V vendor id */
7202 if (!cpu->hyperv_vendor) {
4519259a
VK		 7203 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv",
7204 &error_abort);
7205 }
7206 len = strlen(cpu->hyperv_vendor);
7207 if (len > 12) {
7208 warn_report("hv-vendor-id truncated to 12 characters");
7209 len = 12;
08856771 7210 }
4519259a
VK		 7211 memset(cpu->hyperv_vendor_id, 0, 12);
7212 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
735db465
VK		 7213
7214 /* 'Hv#1' interface identification*/
7215 cpu->hyperv_interface_id[0] = 0x31237648;
7216 cpu->hyperv_interface_id[1] = 0;
7217 cpu->hyperv_interface_id[2] = 0;
7218 cpu->hyperv_interface_id[3] = 0;
fb7e31aa 7219
23eb5d03
VK		 7220 /* Hypervisor implementation limits */
7221 cpu->hyperv_limits[0] = 64;
7222 cpu->hyperv_limits[1] = 0;
7223 cpu->hyperv_limits[2] = 0;
08856771
VK		 7224}
7225
41f3d4d6
EH		 7226static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
7227{
7228 CPUState *cs = CPU(dev);
7229 X86CPU *cpu = X86_CPU(dev);
7230 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
7231 CPUX86State *env = &cpu->env;
7232 Error *local_err = NULL;
7233 static bool ht_warned;
f06d8a18 7234 unsigned requested_lbr_fmt;
41f3d4d6 7235
b94b8c60 7236#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
492f8b88 7237 /* Use pc-relative instructions in system-mode */
492f8b88
AJ		 7238 cs->tcg_cflags |= CF_PCREL;
7239#endif
7240
41f3d4d6
EH		 7241 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
7242 error_setg(errp, "apic-id property was not initialized properly");
7243 return;
7244 }
7245
662175b9
CF		 7246 /*
7247 * Process Hyper-V enlightenments.
7248 * Note: this currently has to happen before the expansion of CPU features.
7249 */
7250 x86_cpu_hyperv_realize(cpu);
7251
b8d834a0 7252 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 7253 if (local_err) {
7254 goto out;
7255 }
7256
f06d8a18
YW		 7257 /*
7258 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
7259 * with user-provided setting.
7260 */
7261 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) {
7262 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) {
7263 error_setg(errp, "invalid lbr-fmt");
7264 return;
7265 }
7266 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT;
7267 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt;
7268 }
7269
7270 /*
7271 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
7272 * 3)vPMU LBR format matches that of host setting.
7273 */
7274 requested_lbr_fmt =
7275 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT;
7276 if (requested_lbr_fmt && kvm_enabled()) {
7277 uint64_t host_perf_cap =
7278 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false);
7279 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT;
7280
7281 if (!cpu->enable_pmu) {
7282 error_setg(errp, "vPMU: LBR is unsupported without pmu=on");
7283 return;
7284 }
7285 if (requested_lbr_fmt != host_lbr_fmt) {
7286 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match "
7287 "the host value (0x%x).",
7288 requested_lbr_fmt, host_lbr_fmt);
7289 return;
7290 }
7291 }
7292
245edd0c
PB		 7293 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
7294
7295 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
7296 error_setg(&local_err,
7297 accel_uses_host_cpuid() ?
7298 "Host doesn't support requested features" :
7299 "TCG doesn't support requested features");
7300 goto out;
9997cf7b
EH		 7301 }
7302
9b15cd9e
IM		 7303 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
7304 * CPUID[1].EDX.
7305 */
e48638fd 7306 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 7307 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
7308 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 7309 & CPUID_EXT2_AMD_ALIASES);
7310 }
7311
db888065
SC		 7312 x86_cpu_set_sgxlepubkeyhash(env);
7313
662175b9
CF		 7314 /*
7315 * note: the call to the framework needs to happen after feature expansion,
7316 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
7317 * These may be set by the accel-specific code,
7318 * and the results are subsequently checked / assumed in this function.
7319 */
7320 cpu_exec_realizefn(cs, &local_err);
7321 if (local_err != NULL) {
7322 error_propagate(errp, local_err);
7323 return;
7324 }
7325
7326 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
7327 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
7328 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
7329 goto out;
7330 }
7331
7332 if (cpu->ucode_rev == 0) {
7333 /*
7334 * The default is the same as KVM's. Note that this check
7335 * needs to happen after the evenual setting of ucode_rev in
7336 * accel-specific code in cpu_exec_realizefn.
7337 */
7338 if (IS_AMD_CPU(env)) {
7339 cpu->ucode_rev = 0x01000065;
7340 } else {
7341 cpu->ucode_rev = 0x100000000ULL;
7342 }
7343 }
7344
7345 /*
7346 * mwait extended info: needed for Core compatibility
7347 * We always wake on interrupt even if host does not have the capability.
7348 *
7349 * requires the accel-specific code in cpu_exec_realizefn to
7350 * have already acquired the CPUID data into cpu->mwait.
7351 */
7352 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
7353
11f6fee5
DDAG		 7354 /* For 64bit systems think about the number of physical bits to present.
7355 * ideally this should be the same as the host; anything other than matching
7356 * the host can cause incorrect guest behaviour.
7357 * QEMU used to pick the magic value of 40 bits that corresponds to
7358 * consumer AMD devices but nothing else.
662175b9
CF		 7359 *
7360 * Note that this code assumes features expansion has already been done
7361 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
7362 * phys_bits adjustments to match the host have been already done in
7363 * accel-specific code in cpu_exec_realizefn.
11f6fee5 7364 */
af45907a 7365 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
b8184135
PB		 7366 if (cpu->phys_bits &&
7367 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
7368 cpu->phys_bits < 32)) {
7369 error_setg(errp, "phys-bits should be between 32 and %u "
7370 " (but is %u)",
7371 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
7372 return;
af45907a 7373 }
f5cc5a5c
CF		 7374 /*
7375 * 0 means it was not explicitly set by the user (or by machine
7376 * compat_props or by the host code in host-cpu.c).
7377 * In this case, the default is the value used by TCG (40).
11f6fee5
DDAG		 7378 */
7379 if (cpu->phys_bits == 0) {
7380 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
7381 }
af45907a
DDAG		 7382 } else {
7383 /* For 32 bit systems don't use the user set value, but keep
7384 * phys_bits consistent with what we tell the guest.
7385 */
7386 if (cpu->phys_bits != 0) {
7387 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
7388 return;
7389 }
fefb41bf 7390
d8300542 7391 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) {
af45907a
DDAG		 7392 cpu->phys_bits = 36;
7393 } else {
7394 cpu->phys_bits = 32;
7395 }
7396 }
a9f27ea9
EH		 7397
7398 /* Cache information initialization */
7399 if (!cpu->legacy_cache) {
cca0a000
MR		 7400 const CPUCaches *cache_info =
7401 x86_cpu_get_versioned_cache_info(cpu, xcc->model);
7402
7403 if (!xcc->model || !cache_info) {
88703ce2 7404 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 7405 error_setg(errp,
7406 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 7407 return;
7408 }
7409 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
cca0a000 7410 *cache_info;
a9f27ea9
EH		 7411 } else {
7412 /* Build legacy cache information */
7413 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
7414 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
7415 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
7416 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
7417
7418 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
7419 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
7420 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
7421 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
7422
7423 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
7424 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
7425 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
7426 env->cache_info_amd.l3_cache = &legacy_l3_cache;
7427 }
7428
65dee380 7429#ifndef CONFIG_USER_ONLY
0e11fc69 7430 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 7431 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 7432
0e11fc69 7433 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 7434 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 7435 if (local_err != NULL) {
4dc1f449 7436 goto out;
bdeec802
IM		 7437 }
7438 }
65dee380
IM		 7439#endif
7440
7a059953 7441 mce_init(cpu);
2001d0cd 7442
14a10fc3 7443 qemu_init_vcpu(cs);
d3c64d6a 7444
6b2942f9
BM		 7445 /*
7446 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
7447 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
7448 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 7449 * users a warning.
7450 *
7451 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
7452 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
7453 */
0765691e
MA		 7454 if (IS_AMD_CPU(env) &&
7455 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
7456 cs->nr_threads > 1 && !ht_warned) {
7457 warn_report("This family of AMD CPU doesn't support "
7458 "hyperthreading(%d)",
7459 cs->nr_threads);
7460 error_printf("Please configure -smp options properly"
7461 " or try enabling topoext feature.\n");
7462 ht_warned = true;
e48638fd
WH		 7463 }
7464
79f1a68a 7465#ifndef CONFIG_USER_ONLY
d3c64d6a
IM		 7466 x86_cpu_apic_realize(cpu, &local_err);
7467 if (local_err != NULL) {
7468 goto out;
7469 }
79f1a68a 7470#endif /* !CONFIG_USER_ONLY */
14a10fc3 7471 cpu_reset(cs);
2b6f294c 7472
4dc1f449 7473 xcc->parent_realize(dev, &local_err);
2001d0cd 7474
4dc1f449
IM		 7475out:
7476 if (local_err != NULL) {
7477 error_propagate(errp, local_err);
7478 return;
7479 }
7a059953
AF		 7480}
7481
b69c3c21 7482static void x86_cpu_unrealizefn(DeviceState *dev)
c884776e
IM		 7483{
7484 X86CPU *cpu = X86_CPU(dev);
7bbc124e 7485 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
c884776e
IM		 7486
7487#ifndef CONFIG_USER_ONLY
7488 cpu_remove_sync(CPU(dev));
7489 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
7490#endif
7491
7492 if (cpu->apic_state) {
7493 object_unparent(OBJECT(cpu->apic_state));
7494 cpu->apic_state = NULL;
7495 }
7bbc124e 7496
b69c3c21 7497 xcc->parent_unrealize(dev);
c884776e
IM		 7498}
7499
38e5c119 7500typedef struct BitProperty {
a7b0ffac 7501 FeatureWord w;
ede146c2 7502 uint64_t mask;
38e5c119
EH		 7503} BitProperty;
7504
d7bce999
EB		 7505static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
7506 void *opaque, Error **errp)
38e5c119 7507{
a7b0ffac 7508 X86CPU *cpu = X86_CPU(obj);
38e5c119 7509 BitProperty *fp = opaque;
ede146c2 7510 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 7511 bool value = (f & fp->mask) == fp->mask;
51e72bc1 7512 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 7513}
7514
d7bce999
EB		 7515static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
7516 void *opaque, Error **errp)
38e5c119
EH		 7517{
7518 DeviceState *dev = DEVICE(obj);
a7b0ffac 7519 X86CPU *cpu = X86_CPU(obj);
38e5c119 7520 BitProperty *fp = opaque;
38e5c119
EH		 7521 bool value;
7522
7523 if (dev->realized) {
7524 qdev_prop_set_after_realize(dev, name, errp);
7525 return;
7526 }
7527
668f62ec 7528 if (!visit_type_bool(v, name, &value, errp)) {
38e5c119
EH		 7529 return;
7530 }
7531
7532 if (value) {
a7b0ffac 7533 cpu->env.features[fp->w] |= fp->mask;
38e5c119 7534 } else {
a7b0ffac 7535 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 7536 }
d4a606b3 7537 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 7538}
7539
38e5c119
EH		 7540/* Register a boolean property to get/set a single bit in a uint32_t field.
7541 *
7542 * The same property name can be registered multiple times to make it affect
7543 * multiple bits in the same FeatureWord. In that case, the getter will return
7544 * true only if all bits are set.
7545 */
f5730c69 7546static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
38e5c119 7547 const char *prop_name,
a7b0ffac 7548 FeatureWord w,
38e5c119
EH		 7549 int bitnr)
7550{
f5730c69 7551 ObjectClass *oc = OBJECT_CLASS(xcc);
38e5c119
EH		 7552 BitProperty *fp;
7553 ObjectProperty *op;
ede146c2 7554 uint64_t mask = (1ULL << bitnr);
38e5c119 7555
f5730c69 7556 op = object_class_property_find(oc, prop_name);
38e5c119
EH		 7557 if (op) {
7558 fp = op->opaque;
a7b0ffac 7559 assert(fp->w == w);
38e5c119
EH		 7560 fp->mask |= mask;
7561 } else {
7562 fp = g_new0(BitProperty, 1);
a7b0ffac 7563 fp->w = w;
38e5c119 7564 fp->mask = mask;
f5730c69
EH		 7565 object_class_property_add(oc, prop_name, "bool",
7566 x86_cpu_get_bit_prop,
7567 x86_cpu_set_bit_prop,
7568 NULL, fp);
38e5c119
EH		 7569 }
7570}
7571
f5730c69 7572static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
38e5c119
EH		 7573 FeatureWord w,
7574 int bitnr)
7575{
38e5c119 7576 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 7577 const char *name = fi->feat_names[bitnr];
38e5c119 7578
16d2fcaa 7579 if (!name) {
38e5c119
EH		 7580 return;
7581 }
7582
fc7dfd20
EH		 7583 /* Property names should use "-" instead of "_".
7584 * Old names containing underscores are registered as aliases
7585 * using object_property_add_alias()
7586 */
16d2fcaa
EH		 7587 assert(!strchr(name, '_'));
7588 /* aliases don't use "|" delimiters anymore, they are registered
7589 * manually using object_property_add_alias() */
7590 assert(!strchr(name, '|'));
f5730c69 7591 x86_cpu_register_bit_prop(xcc, name, w, bitnr);
38e5c119
EH		 7592}
7593
4db4385a
CF		 7594static void x86_cpu_post_initfn(Object *obj)
7595{
7596 accel_cpu_instance_init(CPU(obj));
7597}
7598
de024815
AF		 7599static void x86_cpu_initfn(Object *obj)
7600{
7601 X86CPU *cpu = X86_CPU(obj);
d940ee9b 7602 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815
AF		 7603 CPUX86State *env = &cpu->env;
7604
c26ae610 7605 env->nr_dies = 1;
71ad61d3 7606
8e8aba50
EH		 7607 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
7608 x86_cpu_get_feature_words,
d2623129 7609 NULL, NULL, (void *)env->features);
7e5292b5
EH		 7610 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
7611 x86_cpu_get_feature_words,
d2623129 7612 NULL, NULL, (void *)cpu->filtered_features);
d187e08d 7613
d2623129
MA		 7614 object_property_add_alias(obj, "sse3", obj, "pni");
7615 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
7616 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
7617 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
7618 object_property_add_alias(obj, "xd", obj, "nx");
7619 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
7620 object_property_add_alias(obj, "i64", obj, "lm");
7621
7622 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
7623 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
7624 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
7625 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
7626 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
7627 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
7628 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
7629 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
7630 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
7631 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
7632 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
db5daafa 7633 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
d2623129
MA		 7634 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
7635 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
7636 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
7637 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
7638 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
7639 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
7640 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
7641 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
7642 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7643 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7644 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
54b8dc7c 7645
e1f9a8e8 7646 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic");
f06d8a18
YW		 7647 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;
7648 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt");
e1f9a8e8 7649
dcafd1ef 7650 if (xcc->model) {
49e2fa85 7651 x86_cpu_load_model(cpu, xcc->model);
0bacd8b3 7652 }
de024815
AF		 7653}
7654
997395d3
IM		 7655static int64_t x86_cpu_get_arch_id(CPUState *cs)
7656{
7657 X86CPU *cpu = X86_CPU(cs);
997395d3 7658
7e72a45c 7659 return cpu->apic_id;
997395d3
IM		 7660}
7661
6bc0d6a0 7662#if !defined(CONFIG_USER_ONLY)
444d5590
AF		 7663static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7664{
7665 X86CPU *cpu = X86_CPU(cs);
7666
7667 return cpu->env.cr[0] & CR0_PG_MASK;
7668}
6bc0d6a0 7669#endif /* !CONFIG_USER_ONLY */
444d5590 7670
f45748f1
AF		 7671static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7672{
7673 X86CPU *cpu = X86_CPU(cs);
7674
7675 cpu->env.eip = value;
7676}
7677
e4fdf9df
RH		 7678static vaddr x86_cpu_get_pc(CPUState *cs)
7679{
7680 X86CPU *cpu = X86_CPU(cs);
7681
7682 /* Match cpu_get_tb_cpu_state. */
7683 return cpu->env.eip + cpu->env.segs[R_CS].base;
7684}
7685
92d5f1a4 7686int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 7687{
7688 X86CPU *cpu = X86_CPU(cs);
7689 CPUX86State *env = &cpu->env;
7690
92d5f1a4
PB		 7691#if !defined(CONFIG_USER_ONLY)
7692 if (interrupt_request & CPU_INTERRUPT_POLL) {
7693 return CPU_INTERRUPT_POLL;
7694 }
7695#endif
7696 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7697 return CPU_INTERRUPT_SIPI;
7698 }
7699
7700 if (env->hflags2 & HF2_GIF_MASK) {
7701 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7702 !(env->hflags & HF_SMM_MASK)) {
7703 return CPU_INTERRUPT_SMI;
7704 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7705 !(env->hflags2 & HF2_NMI_MASK)) {
7706 return CPU_INTERRUPT_NMI;
7707 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7708 return CPU_INTERRUPT_MCE;
7709 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7710 (((env->hflags2 & HF2_VINTR_MASK) &&
7711 (env->hflags2 & HF2_HIF_MASK)) ||
7712 (!(env->hflags2 & HF2_VINTR_MASK) &&
7713 (env->eflags & IF_MASK &&
7714 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7715 return CPU_INTERRUPT_HARD;
7716#if !defined(CONFIG_USER_ONLY)
b67e2796
LL		 7717 } else if (env->hflags2 & HF2_VGIF_MASK) {
7718 if((interrupt_request & CPU_INTERRUPT_VIRQ) &&
92d5f1a4
PB		 7719 (env->eflags & IF_MASK) &&
7720 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
b67e2796
LL		 7721 return CPU_INTERRUPT_VIRQ;
7722 }
92d5f1a4
PB		 7723#endif
7724 }
7725 }
7726
7727 return 0;
7728}
7729
7730static bool x86_cpu_has_work(CPUState *cs)
7731{
7732 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 7733}
7734
a120d320 7735static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
ace0c5fe
RH		 7736{
7737 CPUX86State *env = cpu_env(cs);
7738
7739 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
7740 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
7741 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
7742}
7743
f50f3dd5
RH		 7744static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7745{
7746 X86CPU *cpu = X86_CPU(cs);
7747 CPUX86State *env = &cpu->env;
7748
7749 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7750 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7751 : bfd_mach_i386_i8086);
b666d2a4
RH		 7752
7753 info->cap_arch = CS_ARCH_X86;
7754 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7755 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7756 : CS_MODE_16);
15fa1a0a
RH		 7757 info->cap_insn_unit = 1;
7758 info->cap_insn_split = 8;
f50f3dd5
RH		 7759}
7760
35b1b927
TW		 7761void x86_update_hflags(CPUX86State *env)
7762{
7763 uint32_t hflags;
7764#define HFLAG_COPY_MASK \
7765 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7766 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7767 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7768 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7769
7770 hflags = env->hflags & HFLAG_COPY_MASK;
7771 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7772 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7773 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7774 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7775 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7776
7777 if (env->cr[4] & CR4_OSFXSR_MASK) {
7778 hflags |= HF_OSFXSR_MASK;
7779 }
7780
7781 if (env->efer & MSR_EFER_LMA) {
7782 hflags |= HF_LMA_MASK;
7783 }
7784
7785 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7786 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7787 } else {
7788 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7789 (DESC_B_SHIFT - HF_CS32_SHIFT);
7790 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7791 (DESC_B_SHIFT - HF_SS32_SHIFT);
7792 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7793 !(hflags & HF_CS32_MASK)) {
7794 hflags |= HF_ADDSEG_MASK;
7795 } else {
7796 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7797 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7798 }
7799 }
7800 env->hflags = hflags;
7801}
7802
9337e3b6 7803static Property x86_cpu_properties[] = {
2da00e31
IM		 7804#ifdef CONFIG_USER_ONLY
7805 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7806 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 7807 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7808 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 7809 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 7810 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 7811#else
7812 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 7813 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7814 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 7815 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 7816 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 7817#endif
15f8b142 7818 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 7819 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
f06d8a18 7820 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),
2d384d7c 7821
915aee93 7822 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
f701c082 7823 HYPERV_SPINLOCK_NEVER_NOTIFY),
2d384d7c
VK		 7824 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7825 HYPERV_FEAT_RELAXED, 0),
7826 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7827 HYPERV_FEAT_VAPIC, 0),
7828 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7829 HYPERV_FEAT_TIME, 0),
7830 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7831 HYPERV_FEAT_CRASH, 0),
7832 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7833 HYPERV_FEAT_RESET, 0),
7834 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7835 HYPERV_FEAT_VPINDEX, 0),
7836 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7837 HYPERV_FEAT_RUNTIME, 0),
7838 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7839 HYPERV_FEAT_SYNIC, 0),
7840 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7841 HYPERV_FEAT_STIMER, 0),
7842 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7843 HYPERV_FEAT_FREQUENCIES, 0),
7844 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7845 HYPERV_FEAT_REENLIGHTENMENT, 0),
7846 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7847 HYPERV_FEAT_TLBFLUSH, 0),
7848 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7849 HYPERV_FEAT_EVMCS, 0),
7850 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7851 HYPERV_FEAT_IPI, 0),
128531d9
VK		 7852 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7853 HYPERV_FEAT_STIMER_DIRECT, 0),
e1f9a8e8
VK		 7854 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features,
7855 HYPERV_FEAT_AVIC, 0),
869840d2
VK		 7856 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features,
7857 HYPERV_FEAT_MSR_BITMAP, 0),
9411e8b6
VK		 7858 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features,
7859 HYPERV_FEAT_XMM_INPUT, 0),
aa6bb5fa
VK		 7860 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features,
7861 HYPERV_FEAT_TLBFLUSH_EXT, 0),
3aae0854
VK		 7862 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features,
7863 HYPERV_FEAT_TLBFLUSH_DIRECT, 0),
30d6ff66
VK		 7864 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7865 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
73d24074
JD		 7866 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features,
7867 HYPERV_FEAT_SYNDBG, 0),
e48ddcc6 7868 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
70367f09 7869 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false),
2d384d7c 7870
af7228b8
VK		 7871 /* WS2008R2 identify by default */
7872 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build,
f701ecec 7873 0x3839),
af7228b8 7874 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major,
f701ecec 7875 0x000A),
af7228b8 7876 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor,
f701ecec 7877 0x0000),
af7228b8
VK		 7878 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0),
7879 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0),
7880 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0),
7881
15e41345 7882 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 7883 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 7884 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 7885 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 7886 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 7887 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 7888 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 7889 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 7890 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7891 UINT32_MAX),
c39c0edf
EH		 7892 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7893 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7894 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7895 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7896 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7897 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 7898 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 7899 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
08856771 7900 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
5232d00a 7901 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
a7a0da84 7902 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
87f8b626 7903 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 7904 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 7905 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7906 false),
988f7b8b
VK		 7907 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,
7908 false),
0b564e6f 7909 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 7910 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 7911 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7912 true),
ab8f992e 7913 /*
a9f27ea9
EH		 7914 * lecacy_cache defaults to true unless the CPU model provides its
7915 * own cache information (see x86_cpu_load_def()).
ab8f992e 7916 */
a9f27ea9 7917 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
f66b8a83 7918 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false),
6c69dfb6
GA		 7919
7920 /*
7921 * From "Requirements for Implementing the Microsoft
7922 * Hypervisor Interface":
7923 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7924 *
7925 * "Starting with Windows Server 2012 and Windows 8, if
7926 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7927 * the hypervisor imposes no specific limit to the number of VPs.
7928 * In this case, Windows Server 2012 guest VMs may use more than
7929 * 64 VPs, up to the maximum supported number of processors applicable
7930 * to the specific Windows version being used."
7931 */
7932 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 7933 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7934 false),
f24c3a79
LK		 7935 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7936 true),
9337e3b6
EH		 7937 DEFINE_PROP_END_OF_LIST()
7938};
7939
8b80bd28
PMD		 7940#ifndef CONFIG_USER_ONLY
7941#include "hw/core/sysemu-cpu-ops.h"
7942
7943static const struct SysemuCPUOps i386_sysemu_ops = {
2b60b62e 7944 .get_memory_mapping = x86_cpu_get_memory_mapping,
6bc0d6a0 7945 .get_paging_enabled = x86_cpu_get_paging_enabled,
08928c6d 7946 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
faf39e82 7947 .asidx_from_attrs = x86_asidx_from_attrs,
83ec01b6 7948 .get_crash_info = x86_cpu_get_crash_info,
715e3c1a
PMD		 7949 .write_elf32_note = x86_cpu_write_elf32_note,
7950 .write_elf64_note = x86_cpu_write_elf64_note,
7951 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
7952 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
feece4d0 7953 .legacy_vmsd = &vmstate_x86_cpu,
8b80bd28
PMD		 7954};
7955#endif
7956
5fd2087a
AF		 7957static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7958{
7959 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7960 CPUClass *cc = CPU_CLASS(oc);
2b6f294c 7961 DeviceClass *dc = DEVICE_CLASS(oc);
e86787d3 7962 ResettableClass *rc = RESETTABLE_CLASS(oc);
f5730c69 7963 FeatureWord w;
2b6f294c 7964
bf853881
PMD		 7965 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7966 &xcc->parent_realize);
7967 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7968 &xcc->parent_unrealize);
4f67d30b 7969 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 7970
e86787d3
PM		 7971 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL,
7972 &xcc->parent_phases);
91b1df8c 7973 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 7974
500050d1 7975 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 7976 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 7977 cc->has_work = x86_cpu_has_work;
ace0c5fe 7978 cc->mmu_index = x86_cpu_mmu_index;
878096ee 7979 cc->dump_state = x86_cpu_dump_state;
f45748f1 7980 cc->set_pc = x86_cpu_set_pc;
e4fdf9df 7981 cc->get_pc = x86_cpu_get_pc;
5b50e790
AF		 7982 cc->gdb_read_register = x86_cpu_gdb_read_register;
7983 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590 7984 cc->get_arch_id = x86_cpu_get_arch_id;
ed69e831 7985
5d004421 7986#ifndef CONFIG_USER_ONLY
8b80bd28 7987 cc->sysemu_ops = &i386_sysemu_ops;
ed69e831
CF		 7988#endif /* !CONFIG_USER_ONLY */
7989
00fcd100
AB		 7990 cc->gdb_arch_name = x86_gdb_arch_name;
7991#ifdef TARGET_X86_64
b8158192 7992 cc->gdb_core_xml_file = "i386-64bit.xml";
00fcd100 7993#else
b8158192 7994 cc->gdb_core_xml_file = "i386-32bit.xml";
74d7fc7f 7995#endif
f50f3dd5 7996 cc->disas_set_info = x86_disas_set_info;
4c315c27 7997
e90f2a8c 7998 dc->user_creatable = true;
3e0dceaf
EH		 7999
8000 object_class_property_add(oc, "family", "int",
8001 x86_cpuid_version_get_family,
8002 x86_cpuid_version_set_family, NULL, NULL);
8003 object_class_property_add(oc, "model", "int",
8004 x86_cpuid_version_get_model,
8005 x86_cpuid_version_set_model, NULL, NULL);
8006 object_class_property_add(oc, "stepping", "int",
8007 x86_cpuid_version_get_stepping,
8008 x86_cpuid_version_set_stepping, NULL, NULL);
8009 object_class_property_add_str(oc, "vendor",
8010 x86_cpuid_get_vendor,
8011 x86_cpuid_set_vendor);
8012 object_class_property_add_str(oc, "model-id",
8013 x86_cpuid_get_model_id,
8014 x86_cpuid_set_model_id);
8015 object_class_property_add(oc, "tsc-frequency", "int",
8016 x86_cpuid_get_tsc_freq,
8017 x86_cpuid_set_tsc_freq, NULL, NULL);
8018 /*
8019 * The "unavailable-features" property has the same semantics as
8020 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
8021 * QMP command: they list the features that would have prevented the
8022 * CPU from running if the "enforce" flag was set.
8023 */
8024 object_class_property_add(oc, "unavailable-features", "strList",
8025 x86_cpu_get_unavailable_features,
8026 NULL, NULL, NULL);
8027
8028#if !defined(CONFIG_USER_ONLY)
8029 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
8030 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
8031#endif
8032
f5730c69
EH		 8033 for (w = 0; w < FEATURE_WORDS; w++) {
8034 int bitnr;
8035 for (bitnr = 0; bitnr < 64; bitnr++) {
8036 x86_cpu_register_feature_bit_props(xcc, w, bitnr);
8037 }
8038 }
5fd2087a
AF		 8039}
8040
8041static const TypeInfo x86_cpu_type_info = {
8042 .name = TYPE_X86_CPU,
8043 .parent = TYPE_CPU,
8044 .instance_size = sizeof(X86CPU),
f669c992 8045 .instance_align = __alignof(X86CPU),
de024815 8046 .instance_init = x86_cpu_initfn,
4db4385a
CF		 8047 .instance_post_init = x86_cpu_post_initfn,
8048
d940ee9b 8049 .abstract = true,
5fd2087a
AF		 8050 .class_size = sizeof(X86CPUClass),
8051 .class_init = x86_cpu_common_class_init,
8052};
8053
5adbed30
EH		 8054/* "base" CPU model, used by query-cpu-model-expansion */
8055static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
8056{
8057 X86CPUClass *xcc = X86_CPU_CLASS(oc);
8058
8059 xcc->static_model = true;
8060 xcc->migration_safe = true;
8061 xcc->model_description = "base CPU model type with no features enabled";
8062 xcc->ordering = 8;
8063}
8064
8065static const TypeInfo x86_base_cpu_type_info = {
8066 .name = X86_CPU_TYPE_NAME("base"),
8067 .parent = TYPE_X86_CPU,
8068 .class_init = x86_cpu_base_class_init,
8069};
8070
5fd2087a
AF		 8071static void x86_cpu_register_types(void)
8072{
d940ee9b
EH		 8073 int i;
8074
5fd2087a 8075 type_register_static(&x86_cpu_type_info);
d940ee9b 8076 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 8077 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 8078 }
c62f2630 8079 type_register_static(&max_x86_cpu_type_info);
5adbed30 8080 type_register_static(&x86_base_cpu_type_info);
5fd2087a
AF		 8081}
8082
8083type_init(x86_cpu_register_types)
QEMU mirror