//\r
// Make sure we are using the correct packing rules per EFI specification\r
//\r
-#if !defined(__GNUC__) && !defined(__ASSEMBLER__)\r
-#pragma pack()\r
+#if !defined (__GNUC__) && !defined (__ASSEMBLER__)\r
+ #pragma pack()\r
#endif\r
\r
-#if defined(_MSC_EXTENSIONS)\r
+#if defined (_MSC_EXTENSIONS)\r
\r
//\r
// Disable some level 4 compilation warnings (same as IA32 and X64)\r
//\r
// Disabling bitfield type checking warnings.\r
//\r
-#pragma warning ( disable : 4214 )\r
+ #pragma warning ( disable : 4214 )\r
\r
//\r
// Disabling the unreferenced formal parameter warnings.\r
//\r
-#pragma warning ( disable : 4100 )\r
+ #pragma warning ( disable : 4100 )\r
\r
//\r
// Disable slightly different base types warning as CHAR8 * can not be set\r
// to a constant string.\r
//\r
-#pragma warning ( disable : 4057 )\r
+ #pragma warning ( disable : 4057 )\r
\r
//\r
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning\r
//\r
-#pragma warning ( disable : 4127 )\r
+ #pragma warning ( disable : 4127 )\r
\r
//\r
// This warning is caused by functions defined but not used. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4505 )\r
+ #pragma warning ( disable : 4505 )\r
\r
//\r
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4206 )\r
+ #pragma warning ( disable : 4206 )\r
\r
//\r
// Disable 'potentially uninitialized local variable X used' warnings\r
//\r
-#pragma warning ( disable : 4701 )\r
+ #pragma warning ( disable : 4701 )\r
\r
//\r
// Disable 'potentially uninitialized local pointer variable X used' warnings\r
//\r
-#pragma warning ( disable : 4703 )\r
-\r
- //\r
- // use Microsoft* C compiler dependent integer width types\r
- //\r
- typedef unsigned __int64 UINT64;\r
- typedef __int64 INT64;\r
- typedef unsigned __int32 UINT32;\r
- typedef __int32 INT32;\r
- typedef unsigned short UINT16;\r
- typedef unsigned short CHAR16;\r
- typedef short INT16;\r
- typedef unsigned char BOOLEAN;\r
- typedef unsigned char UINT8;\r
- typedef char CHAR8;\r
- typedef signed char INT8;\r
+ #pragma warning ( disable : 4703 )\r
+\r
+//\r
+// use Microsoft* C compiler dependent integer width types\r
+//\r
+typedef unsigned __int64 UINT64;\r
+typedef __int64 INT64;\r
+typedef unsigned __int32 UINT32;\r
+typedef __int32 INT32;\r
+typedef unsigned short UINT16;\r
+typedef unsigned short CHAR16;\r
+typedef short INT16;\r
+typedef unsigned char BOOLEAN;\r
+typedef unsigned char UINT8;\r
+typedef char CHAR8;\r
+typedef signed char INT8;\r
\r
#else\r
\r
- //\r
- // Assume standard AARCH64 alignment.\r
- //\r
- typedef unsigned long long UINT64;\r
- typedef long long INT64;\r
- typedef unsigned int UINT32;\r
- typedef int INT32;\r
- typedef unsigned short UINT16;\r
- typedef unsigned short CHAR16;\r
- typedef short INT16;\r
- typedef unsigned char BOOLEAN;\r
- typedef unsigned char UINT8;\r
- typedef char CHAR8;\r
- typedef signed char INT8;\r
+//\r
+// Assume standard AARCH64 alignment.\r
+//\r
+typedef unsigned long long UINT64;\r
+typedef long long INT64;\r
+typedef unsigned int UINT32;\r
+typedef int INT32;\r
+typedef unsigned short UINT16;\r
+typedef unsigned short CHAR16;\r
+typedef short INT16;\r
+typedef unsigned char BOOLEAN;\r
+typedef unsigned char UINT8;\r
+typedef char CHAR8;\r
+typedef signed char INT8;\r
\r
#endif\r
\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef UINT64 UINTN;\r
+typedef UINT64 UINTN;\r
\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef INT64 INTN;\r
+typedef INT64 INTN;\r
\r
//\r
// Processor specific defines\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x8000000000000000ULL\r
+#define MAX_BIT 0x8000000000000000ULL\r
\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
/// Maximum legal AARCH64 address\r
///\r
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
\r
///\r
/// Maximum usable address at boot time (48 bits using 4 KB pages)\r
///\r
-#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL\r
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL\r
\r
///\r
/// Maximum legal AArch64 INTN and UINTN values.\r
///\r
/// Minimum legal AArch64 INTN value.\r
///\r
-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)\r
+#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)\r
\r
///\r
/// The stack alignment required for AARCH64\r
///\r
/// Page allocation granularity for AARCH64\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)\r
\r
//\r
// Modifier to ensure that all protocol member functions and EFI intrinsics\r
\r
// When compiling with Clang, we still use GNU as for the assembler, so we still\r
// need to define the GCC_ASM* macros.\r
-#if defined(__GNUC__) || defined(__clang__)\r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
-\r
- #define GCC_ASM_EXPORT(func__) \\r
+#if defined (__GNUC__) || defined (__clang__)\r
+///\r
+/// For GNU assembly code, .global or .globl can declare global symbols.\r
+/// Define this macro to unify the usage.\r
+///\r
+#define ASM_GLOBAL .globl\r
+\r
+#define GCC_ASM_EXPORT(func__) \\r
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\\r
.type ASM_PFX(func__), %function\r
\r
- #define GCC_ASM_IMPORT(func__) \\r
+#define GCC_ASM_IMPORT(func__) \\r
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)\r
\r
#endif\r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
#define __USER_LABEL_PREFIX__\r
//\r
// Make sure we are using the correct packing rules per EFI specification\r
//\r
-#if !defined(__GNUC__) && !defined(__ASSEMBLER__)\r
-#pragma pack()\r
+#if !defined (__GNUC__) && !defined (__ASSEMBLER__)\r
+ #pragma pack()\r
#endif\r
\r
-#if defined(_MSC_EXTENSIONS)\r
+#if defined (_MSC_EXTENSIONS)\r
\r
//\r
// Disable some level 4 compilation warnings (same as IA32 and X64)\r
//\r
// Disabling bitfield type checking warnings.\r
//\r
-#pragma warning ( disable : 4214 )\r
+ #pragma warning ( disable : 4214 )\r
\r
//\r
// Disabling the unreferenced formal parameter warnings.\r
//\r
-#pragma warning ( disable : 4100 )\r
+ #pragma warning ( disable : 4100 )\r
\r
//\r
// Disable slightly different base types warning as CHAR8 * can not be set\r
// to a constant string.\r
//\r
-#pragma warning ( disable : 4057 )\r
+ #pragma warning ( disable : 4057 )\r
\r
//\r
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning\r
//\r
-#pragma warning ( disable : 4127 )\r
+ #pragma warning ( disable : 4127 )\r
\r
//\r
// This warning is caused by functions defined but not used. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4505 )\r
+ #pragma warning ( disable : 4505 )\r
\r
//\r
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4206 )\r
+ #pragma warning ( disable : 4206 )\r
\r
//\r
// Disable 'potentially uninitialized local variable X used' warnings\r
//\r
-#pragma warning ( disable : 4701 )\r
+ #pragma warning ( disable : 4701 )\r
\r
//\r
// Disable 'potentially uninitialized local pointer variable X used' warnings\r
//\r
-#pragma warning ( disable : 4703 )\r
+ #pragma warning ( disable : 4703 )\r
\r
#endif\r
\r
//\r
// RVCT and MSFT don't support the __builtin_unreachable() macro\r
//\r
-#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS)\r
+#if defined (__ARMCC_VERSION) || defined (_MSC_EXTENSIONS)\r
#define UNREACHABLE()\r
#endif\r
\r
-#if defined(_MSC_EXTENSIONS)\r
- //\r
- // use Microsoft* C compiler dependent integer width types\r
- //\r
- typedef unsigned __int64 UINT64;\r
- typedef __int64 INT64;\r
- typedef unsigned __int32 UINT32;\r
- typedef __int32 INT32;\r
- typedef unsigned short UINT16;\r
- typedef unsigned short CHAR16;\r
- typedef short INT16;\r
- typedef unsigned char BOOLEAN;\r
- typedef unsigned char UINT8;\r
- typedef char CHAR8;\r
- typedef signed char INT8;\r
+#if defined (_MSC_EXTENSIONS)\r
+//\r
+// use Microsoft* C compiler dependent integer width types\r
+//\r
+typedef unsigned __int64 UINT64;\r
+typedef __int64 INT64;\r
+typedef unsigned __int32 UINT32;\r
+typedef __int32 INT32;\r
+typedef unsigned short UINT16;\r
+typedef unsigned short CHAR16;\r
+typedef short INT16;\r
+typedef unsigned char BOOLEAN;\r
+typedef unsigned char UINT8;\r
+typedef char CHAR8;\r
+typedef signed char INT8;\r
#else\r
- //\r
- // Assume standard ARM alignment.\r
- // Need to check portability of long long\r
- //\r
- typedef unsigned long long UINT64;\r
- typedef long long INT64;\r
- typedef unsigned int UINT32;\r
- typedef int INT32;\r
- typedef unsigned short UINT16;\r
- typedef unsigned short CHAR16;\r
- typedef short INT16;\r
- typedef unsigned char BOOLEAN;\r
- typedef unsigned char UINT8;\r
- typedef char CHAR8;\r
- typedef signed char INT8;\r
+//\r
+// Assume standard ARM alignment.\r
+// Need to check portability of long long\r
+//\r
+typedef unsigned long long UINT64;\r
+typedef long long INT64;\r
+typedef unsigned int UINT32;\r
+typedef int INT32;\r
+typedef unsigned short UINT16;\r
+typedef unsigned short CHAR16;\r
+typedef short INT16;\r
+typedef unsigned char BOOLEAN;\r
+typedef unsigned char UINT8;\r
+typedef char CHAR8;\r
+typedef signed char INT8;\r
#endif\r
\r
///\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef UINT32 UINTN;\r
+typedef UINT32 UINTN;\r
\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef INT32 INTN;\r
+typedef INT32 INTN;\r
\r
//\r
// Processor specific defines\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x80000000\r
+#define MAX_BIT 0x80000000\r
\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
-#define MAX_2_BITS 0xC0000000\r
+#define MAX_2_BITS 0xC0000000\r
\r
///\r
/// Maximum legal ARM address\r
///\r
/// Maximum usable address at boot time\r
///\r
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
\r
///\r
/// Maximum legal ARM INTN and UINTN values.\r
///\r
/// Minimum legal ARM INTN value.\r
///\r
-#define MIN_INTN (((INTN)-2147483647) - 1)\r
+#define MIN_INTN (((INTN)-2147483647) - 1)\r
\r
///\r
/// The stack alignment required for ARM\r
///\r
/// Page allocation granularity for ARM\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
\r
//\r
// Modifier to ensure that all protocol member functions and EFI intrinsics\r
\r
// When compiling with Clang, we still use GNU as for the assembler, so we still\r
// need to define the GCC_ASM* macros.\r
-#if defined(__GNUC__) || defined(__clang__)\r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
-\r
- #if !defined(__APPLE__)\r
- ///\r
- /// ARM EABI defines that the linker should not manipulate call relocations\r
- /// (do bl/blx conversion) unless the target symbol has function type.\r
- /// CodeSourcery 2010.09 started requiring the .type to function properly\r
- ///\r
- #define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function\r
-\r
- #define GCC_ASM_EXPORT(func__) \\r
+#if defined (__GNUC__) || defined (__clang__)\r
+///\r
+/// For GNU assembly code, .global or .globl can declare global symbols.\r
+/// Define this macro to unify the usage.\r
+///\r
+#define ASM_GLOBAL .globl\r
+\r
+ #if !defined (__APPLE__)\r
+///\r
+/// ARM EABI defines that the linker should not manipulate call relocations\r
+/// (do bl/blx conversion) unless the target symbol has function type.\r
+/// CodeSourcery 2010.09 started requiring the .type to function properly\r
+///\r
+#define INTERWORK_FUNC(func__) .type ASM_PFX(func__), %function\r
+\r
+#define GCC_ASM_EXPORT(func__) \\r
.global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\\r
.type ASM_PFX(func__), %function\r
\r
- #define GCC_ASM_IMPORT(func__) \\r
+#define GCC_ASM_IMPORT(func__) \\r
.extern _CONCATENATE (__USER_LABEL_PREFIX__, func__)\r
\r
#else\r
- //\r
- // .type not supported by Apple Xcode tools\r
- //\r
- #define INTERWORK_FUNC(func__)\r
+//\r
+// .type not supported by Apple Xcode tools\r
+//\r
+#define INTERWORK_FUNC(func__)\r
\r
- #define GCC_ASM_EXPORT(func__) \\r
+#define GCC_ASM_EXPORT(func__) \\r
.globl _CONCATENATE (__USER_LABEL_PREFIX__, func__) \\r
\r
- #define GCC_ASM_IMPORT(name)\r
+#define GCC_ASM_IMPORT(name)\r
\r
#endif\r
-#elif defined(_MSC_EXTENSIONS)\r
- //\r
- // PRESERVE8 is not supported by the MSFT assembler.\r
- //\r
- #define PRESERVE8\r
+#elif defined (_MSC_EXTENSIONS)\r
+//\r
+// PRESERVE8 is not supported by the MSFT assembler.\r
+//\r
+#define PRESERVE8\r
#endif\r
\r
/**\r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
#define __USER_LABEL_PREFIX__\r
#endif\r
\r
#endif\r
-\r
-\r
\r
**/\r
\r
-\r
#ifndef __BASE_H__\r
#define __BASE_H__\r
\r
//\r
#include <ProcessorBind.h>\r
\r
-#if defined(_MSC_EXTENSIONS)\r
+#if defined (_MSC_EXTENSIONS)\r
//\r
// Disable warning when last field of data structure is a zero sized array.\r
//\r
-#pragma warning ( disable : 4200 )\r
+ #pragma warning ( disable : 4200 )\r
#endif\r
\r
//\r
// if the /OPT:REF linker option is used. We defined a macro as this is a\r
// a non standard extension\r
//\r
-#if defined(_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)\r
- ///\r
- /// Remove global variable from the linked image if there are no references to\r
- /// it after all compiler and linker optimizations have been performed.\r
- ///\r
- ///\r
- #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)\r
+#if defined (_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)\r
+///\r
+/// Remove global variable from the linked image if there are no references to\r
+/// it after all compiler and linker optimizations have been performed.\r
+///\r
+///\r
+#define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)\r
#else\r
- ///\r
- /// Remove the global variable from the linked image if there are no references\r
- /// to it after all compiler and linker optimizations have been performed.\r
- ///\r
- ///\r
- #define GLOBAL_REMOVE_IF_UNREFERENCED\r
+///\r
+/// Remove the global variable from the linked image if there are no references\r
+/// to it after all compiler and linker optimizations have been performed.\r
+///\r
+///\r
+#define GLOBAL_REMOVE_IF_UNREFERENCED\r
#endif\r
\r
//\r
//\r
#ifndef UNREACHABLE\r
#ifdef __GNUC__\r
- ///\r
- /// Signal compilers and analyzers that this call is not reachable. It is\r
- /// up to the compiler to remove any code past that point.\r
- ///\r
- #define UNREACHABLE() __builtin_unreachable ()\r
+///\r
+/// Signal compilers and analyzers that this call is not reachable. It is\r
+/// up to the compiler to remove any code past that point.\r
+///\r
+#define UNREACHABLE() __builtin_unreachable ()\r
#elif defined (__has_feature)\r
#if __has_builtin (__builtin_unreachable)\r
- ///\r
- /// Signal compilers and analyzers that this call is not reachable. It is\r
- /// up to the compiler to remove any code past that point.\r
- ///\r
- #define UNREACHABLE() __builtin_unreachable ()\r
+///\r
+/// Signal compilers and analyzers that this call is not reachable. It is\r
+/// up to the compiler to remove any code past that point.\r
+///\r
+#define UNREACHABLE() __builtin_unreachable ()\r
#endif\r
#endif\r
\r
#ifndef UNREACHABLE\r
- ///\r
- /// Signal compilers and analyzers that this call is not reachable. It is\r
- /// up to the compiler to remove any code past that point.\r
- ///\r
- #define UNREACHABLE()\r
+///\r
+/// Signal compilers and analyzers that this call is not reachable. It is\r
+/// up to the compiler to remove any code past that point.\r
+///\r
+#define UNREACHABLE()\r
#endif\r
#endif\r
\r
//\r
#ifndef NORETURN\r
#if defined (__GNUC__) || defined (__clang__)\r
- ///\r
- /// Signal compilers and analyzers that the function cannot return.\r
- /// It is up to the compiler to remove any code past a call to functions\r
- /// flagged with this attribute.\r
- ///\r
- #define NORETURN __attribute__((noreturn))\r
- #elif defined(_MSC_EXTENSIONS) && !defined(MDE_CPU_EBC)\r
- ///\r
- /// Signal compilers and analyzers that the function cannot return.\r
- /// It is up to the compiler to remove any code past a call to functions\r
- /// flagged with this attribute.\r
- ///\r
- #define NORETURN __declspec(noreturn)\r
+///\r
+/// Signal compilers and analyzers that the function cannot return.\r
+/// It is up to the compiler to remove any code past a call to functions\r
+/// flagged with this attribute.\r
+///\r
+#define NORETURN __attribute__((noreturn))\r
+ #elif defined (_MSC_EXTENSIONS) && !defined (MDE_CPU_EBC)\r
+///\r
+/// Signal compilers and analyzers that the function cannot return.\r
+/// It is up to the compiler to remove any code past a call to functions\r
+/// flagged with this attribute.\r
+///\r
+#define NORETURN __declspec(noreturn)\r
#else\r
- ///\r
- /// Signal compilers and analyzers that the function cannot return.\r
- /// It is up to the compiler to remove any code past a call to functions\r
- /// flagged with this attribute.\r
- ///\r
- #define NORETURN\r
+///\r
+/// Signal compilers and analyzers that the function cannot return.\r
+/// It is up to the compiler to remove any code past a call to functions\r
+/// flagged with this attribute.\r
+///\r
+#define NORETURN\r
#endif\r
#endif\r
\r
#ifndef ANALYZER_UNREACHABLE\r
#ifdef __clang_analyzer__\r
#if __has_builtin (__builtin_unreachable)\r
- ///\r
- /// Signal the analyzer that this call is not reachable.\r
- /// This excludes compilers.\r
- ///\r
- #define ANALYZER_UNREACHABLE() __builtin_unreachable ()\r
+///\r
+/// Signal the analyzer that this call is not reachable.\r
+/// This excludes compilers.\r
+///\r
+#define ANALYZER_UNREACHABLE() __builtin_unreachable ()\r
#endif\r
#endif\r
\r
#ifndef ANALYZER_UNREACHABLE\r
- ///\r
- /// Signal the analyzer that this call is not reachable.\r
- /// This excludes compilers.\r
- ///\r
- #define ANALYZER_UNREACHABLE()\r
+///\r
+/// Signal the analyzer that this call is not reachable.\r
+/// This excludes compilers.\r
+///\r
+#define ANALYZER_UNREACHABLE()\r
#endif\r
#endif\r
\r
#ifndef ANALYZER_NORETURN\r
#ifdef __has_feature\r
#if __has_feature (attribute_analyzer_noreturn)\r
- ///\r
- /// Signal analyzers that the function cannot return.\r
- /// This excludes compilers.\r
- ///\r
- #define ANALYZER_NORETURN __attribute__((analyzer_noreturn))\r
+///\r
+/// Signal analyzers that the function cannot return.\r
+/// This excludes compilers.\r
+///\r
+#define ANALYZER_NORETURN __attribute__((analyzer_noreturn))\r
#endif\r
#endif\r
\r
#ifndef ANALYZER_NORETURN\r
- ///\r
- /// Signal the analyzer that the function cannot return.\r
- /// This excludes compilers.\r
- ///\r
- #define ANALYZER_NORETURN\r
+///\r
+/// Signal the analyzer that the function cannot return.\r
+/// This excludes compilers.\r
+///\r
+#define ANALYZER_NORETURN\r
#endif\r
#endif\r
\r
///\r
#ifndef RETURNS_TWICE\r
#if defined (__GNUC__) || defined (__clang__)\r
- ///\r
- /// Tell the code optimizer that the function will return twice.\r
- /// This prevents wrong optimizations which can cause bugs.\r
- ///\r
- #define RETURNS_TWICE __attribute__((returns_twice))\r
+///\r
+/// Tell the code optimizer that the function will return twice.\r
+/// This prevents wrong optimizations which can cause bugs.\r
+///\r
+#define RETURNS_TWICE __attribute__((returns_twice))\r
#else\r
- ///\r
- /// Tell the code optimizer that the function will return twice.\r
- /// This prevents wrong optimizations which can cause bugs.\r
- ///\r
- #define RETURNS_TWICE\r
+///\r
+/// Tell the code optimizer that the function will return twice.\r
+/// This prevents wrong optimizations which can cause bugs.\r
+///\r
+#define RETURNS_TWICE\r
#endif\r
#endif\r
\r
///\r
/// Private worker functions for ASM_PFX()\r
///\r
-#define _CONCATENATE(a, b) __CONCATENATE(a, b)\r
-#define __CONCATENATE(a, b) a ## b\r
+#define _CONCATENATE(a, b) __CONCATENATE(a, b)\r
+#define __CONCATENATE(a, b) a ## b\r
\r
///\r
/// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix\r
/// on symbols in assembly language.\r
///\r
-#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)\r
+#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)\r
\r
#ifdef __APPLE__\r
- //\r
- // Apple extension that is used by the linker to optimize code size\r
- // with assembly functions. Put at the end of your .S files\r
- //\r
- #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols\r
+//\r
+// Apple extension that is used by the linker to optimize code size\r
+// with assembly functions. Put at the end of your .S files\r
+//\r
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols\r
#else\r
- #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+#define ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
#endif\r
\r
#ifdef __CC_ARM\r
- //\r
- // Older RVCT ARM compilers don't fully support #pragma pack and require __packed\r
- // as a prefix for the structure.\r
- //\r
- #define PACKED __packed\r
+//\r
+// Older RVCT ARM compilers don't fully support #pragma pack and require __packed\r
+// as a prefix for the structure.\r
+//\r
+#define PACKED __packed\r
#else\r
- #define PACKED\r
+#define PACKED\r
#endif\r
\r
///\r
/// Unless otherwise specified, aligned on a 64 bit boundary.\r
///\r
typedef struct {\r
- UINT32 Data1;\r
- UINT16 Data2;\r
- UINT16 Data3;\r
- UINT8 Data4[8];\r
+ UINT32 Data1;\r
+ UINT16 Data2;\r
+ UINT16 Data3;\r
+ UINT8 Data4[8];\r
} GUID;\r
\r
///\r
/// 4-byte buffer. An IPv4 internet protocol address.\r
///\r
typedef struct {\r
- UINT8 Addr[4];\r
+ UINT8 Addr[4];\r
} IPv4_ADDRESS;\r
\r
///\r
/// 16-byte buffer. An IPv6 internet protocol address.\r
///\r
typedef struct {\r
- UINT8 Addr[16];\r
+ UINT8 Addr[16];\r
} IPv6_ADDRESS;\r
\r
//\r
/// _LIST_ENTRY structure definition.\r
///\r
struct _LIST_ENTRY {\r
- LIST_ENTRY *ForwardLink;\r
- LIST_ENTRY *BackLink;\r
+ LIST_ENTRY *ForwardLink;\r
+ LIST_ENTRY *BackLink;\r
};\r
\r
//\r
///\r
/// Datum is read-only.\r
///\r
-#define CONST const\r
+#define CONST const\r
\r
///\r
/// Datum is scoped to the current file or function.\r
///\r
-#define STATIC static\r
+#define STATIC static\r
\r
///\r
/// Undeclared type.\r
///\r
-#define VOID void\r
+#define VOID void\r
\r
//\r
// Modifiers for Data Types used to self document code.\r
/// Boolean false value. UEFI Specification defines this value to be 0,\r
/// but this form is more portable.\r
///\r
-#define FALSE ((BOOLEAN)(0==1))\r
+#define FALSE ((BOOLEAN)(0==1))\r
\r
///\r
/// NULL pointer (VOID *)\r
//\r
// Null character\r
//\r
-#define CHAR_NULL 0x0000\r
+#define CHAR_NULL 0x0000\r
\r
///\r
/// Maximum values for common UEFI Data Types\r
#define MIN_INT32 (((INT32) -2147483647) - 1)\r
#define MIN_INT64 (((INT64) -9223372036854775807LL) - 1)\r
\r
-#define BIT0 0x00000001\r
-#define BIT1 0x00000002\r
-#define BIT2 0x00000004\r
-#define BIT3 0x00000008\r
-#define BIT4 0x00000010\r
-#define BIT5 0x00000020\r
-#define BIT6 0x00000040\r
-#define BIT7 0x00000080\r
-#define BIT8 0x00000100\r
-#define BIT9 0x00000200\r
-#define BIT10 0x00000400\r
-#define BIT11 0x00000800\r
-#define BIT12 0x00001000\r
-#define BIT13 0x00002000\r
-#define BIT14 0x00004000\r
-#define BIT15 0x00008000\r
-#define BIT16 0x00010000\r
-#define BIT17 0x00020000\r
-#define BIT18 0x00040000\r
-#define BIT19 0x00080000\r
-#define BIT20 0x00100000\r
-#define BIT21 0x00200000\r
-#define BIT22 0x00400000\r
-#define BIT23 0x00800000\r
-#define BIT24 0x01000000\r
-#define BIT25 0x02000000\r
-#define BIT26 0x04000000\r
-#define BIT27 0x08000000\r
-#define BIT28 0x10000000\r
-#define BIT29 0x20000000\r
-#define BIT30 0x40000000\r
-#define BIT31 0x80000000\r
-#define BIT32 0x0000000100000000ULL\r
-#define BIT33 0x0000000200000000ULL\r
-#define BIT34 0x0000000400000000ULL\r
-#define BIT35 0x0000000800000000ULL\r
-#define BIT36 0x0000001000000000ULL\r
-#define BIT37 0x0000002000000000ULL\r
-#define BIT38 0x0000004000000000ULL\r
-#define BIT39 0x0000008000000000ULL\r
-#define BIT40 0x0000010000000000ULL\r
-#define BIT41 0x0000020000000000ULL\r
-#define BIT42 0x0000040000000000ULL\r
-#define BIT43 0x0000080000000000ULL\r
-#define BIT44 0x0000100000000000ULL\r
-#define BIT45 0x0000200000000000ULL\r
-#define BIT46 0x0000400000000000ULL\r
-#define BIT47 0x0000800000000000ULL\r
-#define BIT48 0x0001000000000000ULL\r
-#define BIT49 0x0002000000000000ULL\r
-#define BIT50 0x0004000000000000ULL\r
-#define BIT51 0x0008000000000000ULL\r
-#define BIT52 0x0010000000000000ULL\r
-#define BIT53 0x0020000000000000ULL\r
-#define BIT54 0x0040000000000000ULL\r
-#define BIT55 0x0080000000000000ULL\r
-#define BIT56 0x0100000000000000ULL\r
-#define BIT57 0x0200000000000000ULL\r
-#define BIT58 0x0400000000000000ULL\r
-#define BIT59 0x0800000000000000ULL\r
-#define BIT60 0x1000000000000000ULL\r
-#define BIT61 0x2000000000000000ULL\r
-#define BIT62 0x4000000000000000ULL\r
-#define BIT63 0x8000000000000000ULL\r
+#define BIT0 0x00000001\r
+#define BIT1 0x00000002\r
+#define BIT2 0x00000004\r
+#define BIT3 0x00000008\r
+#define BIT4 0x00000010\r
+#define BIT5 0x00000020\r
+#define BIT6 0x00000040\r
+#define BIT7 0x00000080\r
+#define BIT8 0x00000100\r
+#define BIT9 0x00000200\r
+#define BIT10 0x00000400\r
+#define BIT11 0x00000800\r
+#define BIT12 0x00001000\r
+#define BIT13 0x00002000\r
+#define BIT14 0x00004000\r
+#define BIT15 0x00008000\r
+#define BIT16 0x00010000\r
+#define BIT17 0x00020000\r
+#define BIT18 0x00040000\r
+#define BIT19 0x00080000\r
+#define BIT20 0x00100000\r
+#define BIT21 0x00200000\r
+#define BIT22 0x00400000\r
+#define BIT23 0x00800000\r
+#define BIT24 0x01000000\r
+#define BIT25 0x02000000\r
+#define BIT26 0x04000000\r
+#define BIT27 0x08000000\r
+#define BIT28 0x10000000\r
+#define BIT29 0x20000000\r
+#define BIT30 0x40000000\r
+#define BIT31 0x80000000\r
+#define BIT32 0x0000000100000000ULL\r
+#define BIT33 0x0000000200000000ULL\r
+#define BIT34 0x0000000400000000ULL\r
+#define BIT35 0x0000000800000000ULL\r
+#define BIT36 0x0000001000000000ULL\r
+#define BIT37 0x0000002000000000ULL\r
+#define BIT38 0x0000004000000000ULL\r
+#define BIT39 0x0000008000000000ULL\r
+#define BIT40 0x0000010000000000ULL\r
+#define BIT41 0x0000020000000000ULL\r
+#define BIT42 0x0000040000000000ULL\r
+#define BIT43 0x0000080000000000ULL\r
+#define BIT44 0x0000100000000000ULL\r
+#define BIT45 0x0000200000000000ULL\r
+#define BIT46 0x0000400000000000ULL\r
+#define BIT47 0x0000800000000000ULL\r
+#define BIT48 0x0001000000000000ULL\r
+#define BIT49 0x0002000000000000ULL\r
+#define BIT50 0x0004000000000000ULL\r
+#define BIT51 0x0008000000000000ULL\r
+#define BIT52 0x0010000000000000ULL\r
+#define BIT53 0x0020000000000000ULL\r
+#define BIT54 0x0040000000000000ULL\r
+#define BIT55 0x0080000000000000ULL\r
+#define BIT56 0x0100000000000000ULL\r
+#define BIT57 0x0200000000000000ULL\r
+#define BIT58 0x0400000000000000ULL\r
+#define BIT59 0x0800000000000000ULL\r
+#define BIT60 0x1000000000000000ULL\r
+#define BIT61 0x2000000000000000ULL\r
+#define BIT62 0x4000000000000000ULL\r
+#define BIT63 0x8000000000000000ULL\r
\r
#define SIZE_1KB 0x00000400\r
#define SIZE_2KB 0x00000800\r
\r
@return The aligned size.\r
**/\r
-#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))\r
+#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1))\r
\r
-#if defined(__CC_ARM)\r
+#if defined (__CC_ARM)\r
//\r
// RVCT ARM variable argument list support.\r
//\r
/// Variable used to traverse the list of arguments. This type can vary by\r
/// implementation and could be an array or structure.\r
///\r
-#ifdef __APCS_ADSABI\r
- typedef int *va_list[1];\r
- #define VA_LIST va_list\r
-#else\r
- typedef struct __va_list { void *__ap; } va_list;\r
- #define VA_LIST va_list\r
-#endif\r
+ #ifdef __APCS_ADSABI\r
+typedef int *va_list[1];\r
+#define VA_LIST va_list\r
+ #else\r
+typedef struct __va_list {\r
+ void *__ap;\r
+} va_list;\r
+#define VA_LIST va_list\r
+ #endif\r
\r
-#define VA_START(Marker, Parameter) __va_start(Marker, Parameter)\r
+#define VA_START(Marker, Parameter) __va_start(Marker, Parameter)\r
\r
-#define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE)\r
+#define VA_ARG(Marker, TYPE) __va_arg(Marker, TYPE)\r
\r
-#define VA_END(Marker) ((void)0)\r
+#define VA_END(Marker) ((void)0)\r
\r
// For some ARM RVCT compilers, __va_copy is not defined\r
-#ifndef __va_copy\r
- #define __va_copy(dest, src) ((void)((dest) = (src)))\r
-#endif\r
+ #ifndef __va_copy\r
+#define __va_copy(dest, src) ((void)((dest) = (src)))\r
+ #endif\r
\r
-#define VA_COPY(Dest, Start) __va_copy (Dest, Start)\r
+#define VA_COPY(Dest, Start) __va_copy (Dest, Start)\r
\r
-#elif defined(_M_ARM) || defined(_M_ARM64)\r
+#elif defined (_M_ARM) || defined (_M_ARM64)\r
//\r
// MSFT ARM variable argument list support.\r
//\r
\r
-typedef char* VA_LIST;\r
+typedef char *VA_LIST;\r
\r
-#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)\r
-#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))\r
-#define VA_END(Marker) (Marker = (VA_LIST) 0)\r
-#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))\r
+#define VA_START(Marker, Parameter) __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)\r
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))\r
+#define VA_END(Marker) (Marker = (VA_LIST) 0)\r
+#define VA_COPY(Dest, Start) ((void)((Dest) = (Start)))\r
\r
-#elif defined(__GNUC__) || defined(__clang__)\r
+#elif defined (__GNUC__) || defined (__clang__)\r
\r
-#if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS)\r
+ #if defined (MDE_CPU_X64) && !defined (NO_MSABI_VA_FUNCS)\r
//\r
// X64 only. Use MS ABI version of GCC built-in macros for variable argument lists.\r
//\r
\r
#define VA_START(Marker, Parameter) __builtin_ms_va_start (Marker, Parameter)\r
\r
-#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))\r
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))\r
\r
-#define VA_END(Marker) __builtin_ms_va_end (Marker)\r
+#define VA_END(Marker) __builtin_ms_va_end (Marker)\r
\r
-#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)\r
+#define VA_COPY(Dest, Start) __builtin_ms_va_copy (Dest, Start)\r
\r
-#else\r
+ #else\r
//\r
// Use GCC built-in macros for variable argument lists.\r
//\r
\r
#define VA_START(Marker, Parameter) __builtin_va_start (Marker, Parameter)\r
\r
-#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))\r
+#define VA_ARG(Marker, TYPE) ((sizeof (TYPE) < sizeof (UINTN)) ? (TYPE)(__builtin_va_arg (Marker, UINTN)) : (TYPE)(__builtin_va_arg (Marker, TYPE)))\r
\r
-#define VA_END(Marker) __builtin_va_end (Marker)\r
+#define VA_END(Marker) __builtin_va_end (Marker)\r
\r
-#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)\r
+#define VA_COPY(Dest, Start) __builtin_va_copy (Dest, Start)\r
\r
-#endif\r
+ #endif\r
\r
#else\r
///\r
@return A pointer to the beginning of a variable argument list.\r
\r
**/\r
-#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))\r
+#define VA_START(Marker, Parameter) (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF (Parameter)))\r
\r
/**\r
Returns an argument of a specified type from a variable argument list and updates\r
@return An argument of the type specified by TYPE.\r
\r
**/\r
-#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))\r
+#define VA_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE)) - _INT_SIZE_OF (TYPE)))\r
\r
/**\r
Terminates the use of a variable argument list.\r
@param Marker VA_LIST used to traverse the list of arguments.\r
\r
**/\r
-#define VA_END(Marker) (Marker = (VA_LIST) 0)\r
+#define VA_END(Marker) (Marker = (VA_LIST) 0)\r
\r
/**\r
Initializes a VA_LIST as a copy of an existing VA_LIST.\r
///\r
/// Pointer to the start of a variable argument list stored in a memory buffer. Same as UINT8 *.\r
///\r
-typedef UINTN *BASE_LIST;\r
+typedef UINTN *BASE_LIST;\r
\r
/**\r
Returns the size of a data type in sizeof(UINTN) units rounded up to the nearest UINTN boundary.\r
\r
@return The size of TYPE in sizeof (UINTN) units rounded up to the nearest UINTN boundary.\r
**/\r
-#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))\r
+#define _BASE_INT_SIZE_OF(TYPE) ((sizeof (TYPE) + sizeof (UINTN) - 1) / sizeof (UINTN))\r
\r
/**\r
Returns an argument of a specified type from a variable argument list and updates\r
@return An argument of the type specified by TYPE.\r
\r
**/\r
-#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))\r
+#define BASE_ARG(Marker, TYPE) (*(TYPE *) ((Marker += _BASE_INT_SIZE_OF (TYPE)) - _BASE_INT_SIZE_OF (TYPE)))\r
\r
/**\r
The macro that returns the byte offset of a field in a data structure.\r
@return Offset, in bytes, of field.\r
\r
**/\r
-#if (defined(__GNUC__) && __GNUC__ >= 4) || defined(__clang__)\r
-#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))\r
+#if (defined (__GNUC__) && __GNUC__ >= 4) || defined (__clang__)\r
+#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))\r
#endif\r
\r
#ifndef OFFSET_OF\r
-#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))\r
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))\r
#endif\r
\r
/**\r
\r
**/\r
#ifdef MDE_CPU_EBC\r
- #define STATIC_ASSERT(Expression, Message)\r
-#elif defined(_MSC_EXTENSIONS)\r
- #define STATIC_ASSERT static_assert\r
+#define STATIC_ASSERT(Expression, Message)\r
+#elif defined (_MSC_EXTENSIONS)\r
+#define STATIC_ASSERT static_assert\r
#else\r
- #define STATIC_ASSERT _Static_assert\r
+#define STATIC_ASSERT _Static_assert\r
#endif\r
\r
//\r
@return A value up to the next boundary.\r
\r
**/\r
-#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))\r
+#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))\r
\r
/**\r
Adjust a pointer by adding the minimum offset required for it to be aligned on\r
@return Pointer to the aligned address.\r
\r
**/\r
-#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))\r
+#define ALIGN_POINTER(Pointer, Alignment) ((VOID *) (ALIGN_VALUE ((UINTN)(Pointer), (Alignment))))\r
\r
/**\r
Rounds a value up to the next natural boundary for the current CPU.\r
**/\r
#define ALIGN_VARIABLE(Value) ALIGN_VALUE ((Value), sizeof (UINTN))\r
\r
-\r
/**\r
Return the maximum of two operands.\r
\r
@return The value specified by StatusCode with the highest bit set.\r
\r
**/\r
-#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))\r
+#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode)))\r
\r
/**\r
Produces a RETURN_STATUS code with the highest bit clear.\r
@return The value specified by StatusCode with the highest bit clear.\r
\r
**/\r
-#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))\r
+#define ENCODE_WARNING(StatusCode) ((RETURN_STATUS)(StatusCode))\r
\r
/**\r
Returns TRUE if a specified RETURN_STATUS code is an error code.\r
@retval FALSE The high bit of StatusCode is clear.\r
\r
**/\r
-#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)\r
+#define RETURN_ERROR(StatusCode) (((INTN)(RETURN_STATUS)(StatusCode)) < 0)\r
\r
///\r
/// The operation completed successfully.\r
///\r
-#define RETURN_SUCCESS 0\r
+#define RETURN_SUCCESS 0\r
\r
///\r
/// The image failed to load.\r
///\r
-#define RETURN_LOAD_ERROR ENCODE_ERROR (1)\r
+#define RETURN_LOAD_ERROR ENCODE_ERROR (1)\r
\r
///\r
/// The parameter was incorrect.\r
///\r
-#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)\r
+#define RETURN_INVALID_PARAMETER ENCODE_ERROR (2)\r
\r
///\r
/// The operation is not supported.\r
///\r
-#define RETURN_UNSUPPORTED ENCODE_ERROR (3)\r
+#define RETURN_UNSUPPORTED ENCODE_ERROR (3)\r
\r
///\r
/// The buffer was not the proper size for the request.\r
///\r
-#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)\r
+#define RETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4)\r
\r
///\r
/// The buffer was not large enough to hold the requested data.\r
/// The required buffer size is returned in the appropriate\r
/// parameter when this error occurs.\r
///\r
-#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)\r
+#define RETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5)\r
\r
///\r
/// There is no data pending upon return.\r
///\r
-#define RETURN_NOT_READY ENCODE_ERROR (6)\r
+#define RETURN_NOT_READY ENCODE_ERROR (6)\r
\r
///\r
/// The physical device reported an error while attempting the\r
/// operation.\r
///\r
-#define RETURN_DEVICE_ERROR ENCODE_ERROR (7)\r
+#define RETURN_DEVICE_ERROR ENCODE_ERROR (7)\r
\r
///\r
/// The device can not be written to.\r
///\r
-#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)\r
+#define RETURN_WRITE_PROTECTED ENCODE_ERROR (8)\r
\r
///\r
/// The resource has run out.\r
///\r
-#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)\r
+#define RETURN_OUT_OF_RESOURCES ENCODE_ERROR (9)\r
\r
///\r
/// An inconsistency was detected on the file system causing the\r
/// operation to fail.\r
///\r
-#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)\r
+#define RETURN_VOLUME_CORRUPTED ENCODE_ERROR (10)\r
\r
///\r
/// There is no more space on the file system.\r
///\r
-#define RETURN_VOLUME_FULL ENCODE_ERROR (11)\r
+#define RETURN_VOLUME_FULL ENCODE_ERROR (11)\r
\r
///\r
/// The device does not contain any medium to perform the\r
/// operation.\r
///\r
-#define RETURN_NO_MEDIA ENCODE_ERROR (12)\r
+#define RETURN_NO_MEDIA ENCODE_ERROR (12)\r
\r
///\r
/// The medium in the device has changed since the last\r
/// access.\r
///\r
-#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)\r
+#define RETURN_MEDIA_CHANGED ENCODE_ERROR (13)\r
\r
///\r
/// The item was not found.\r
///\r
-#define RETURN_NOT_FOUND ENCODE_ERROR (14)\r
+#define RETURN_NOT_FOUND ENCODE_ERROR (14)\r
\r
///\r
/// Access was denied.\r
///\r
-#define RETURN_ACCESS_DENIED ENCODE_ERROR (15)\r
+#define RETURN_ACCESS_DENIED ENCODE_ERROR (15)\r
\r
///\r
/// The server was not found or did not respond to the request.\r
///\r
-#define RETURN_NO_RESPONSE ENCODE_ERROR (16)\r
+#define RETURN_NO_RESPONSE ENCODE_ERROR (16)\r
\r
///\r
/// A mapping to the device does not exist.\r
///\r
-#define RETURN_NO_MAPPING ENCODE_ERROR (17)\r
+#define RETURN_NO_MAPPING ENCODE_ERROR (17)\r
\r
///\r
/// A timeout time expired.\r
///\r
-#define RETURN_TIMEOUT ENCODE_ERROR (18)\r
+#define RETURN_TIMEOUT ENCODE_ERROR (18)\r
\r
///\r
/// The protocol has not been started.\r
///\r
-#define RETURN_NOT_STARTED ENCODE_ERROR (19)\r
+#define RETURN_NOT_STARTED ENCODE_ERROR (19)\r
\r
///\r
/// The protocol has already been started.\r
///\r
-#define RETURN_ALREADY_STARTED ENCODE_ERROR (20)\r
+#define RETURN_ALREADY_STARTED ENCODE_ERROR (20)\r
\r
///\r
/// The operation was aborted.\r
///\r
-#define RETURN_ABORTED ENCODE_ERROR (21)\r
+#define RETURN_ABORTED ENCODE_ERROR (21)\r
\r
///\r
/// An ICMP error occurred during the network operation.\r
///\r
-#define RETURN_ICMP_ERROR ENCODE_ERROR (22)\r
+#define RETURN_ICMP_ERROR ENCODE_ERROR (22)\r
\r
///\r
/// A TFTP error occurred during the network operation.\r
///\r
-#define RETURN_TFTP_ERROR ENCODE_ERROR (23)\r
+#define RETURN_TFTP_ERROR ENCODE_ERROR (23)\r
\r
///\r
/// A protocol error occurred during the network operation.\r
///\r
-#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)\r
+#define RETURN_PROTOCOL_ERROR ENCODE_ERROR (24)\r
\r
///\r
/// A function encountered an internal version that was\r
///\r
/// The function was not performed due to a security violation.\r
///\r
-#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)\r
+#define RETURN_SECURITY_VIOLATION ENCODE_ERROR (26)\r
\r
///\r
/// A CRC error was detected.\r
///\r
-#define RETURN_CRC_ERROR ENCODE_ERROR (27)\r
+#define RETURN_CRC_ERROR ENCODE_ERROR (27)\r
\r
///\r
/// The beginning or end of media was reached.\r
///\r
-#define RETURN_END_OF_MEDIA ENCODE_ERROR (28)\r
+#define RETURN_END_OF_MEDIA ENCODE_ERROR (28)\r
\r
///\r
/// The end of the file was reached.\r
///\r
-#define RETURN_END_OF_FILE ENCODE_ERROR (31)\r
+#define RETURN_END_OF_FILE ENCODE_ERROR (31)\r
\r
///\r
/// The language specified was invalid.\r
///\r
-#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)\r
+#define RETURN_INVALID_LANGUAGE ENCODE_ERROR (32)\r
\r
///\r
/// The security status of the data is unknown or compromised\r
/// and the data must be updated or replaced to restore a valid\r
/// security status.\r
///\r
-#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)\r
+#define RETURN_COMPROMISED_DATA ENCODE_ERROR (33)\r
\r
///\r
/// A HTTP error occurred during the network operation.\r
///\r
-#define RETURN_HTTP_ERROR ENCODE_ERROR (35)\r
+#define RETURN_HTTP_ERROR ENCODE_ERROR (35)\r
\r
///\r
/// The string contained one or more characters that\r
/// the device could not render and were skipped.\r
///\r
-#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)\r
+#define RETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1)\r
\r
///\r
/// The handle was closed, but the file was not deleted.\r
///\r
-#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)\r
+#define RETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2)\r
\r
///\r
/// The handle was closed, but the data to the file was not\r
/// flushed properly.\r
///\r
-#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)\r
+#define RETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3)\r
\r
///\r
/// The resulting buffer was too small, and the data was\r
/// truncated to the buffer size.\r
///\r
-#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)\r
+#define RETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4)\r
\r
///\r
/// The data has not been updated within the timeframe set by\r
/// local policy for this type of data.\r
///\r
-#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)\r
+#define RETURN_WARN_STALE_DATA ENCODE_WARNING (5)\r
\r
///\r
/// The resulting buffer contains UEFI-compliant file system.\r
///\r
-#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)\r
-\r
+#define RETURN_WARN_FILE_SYSTEM ENCODE_WARNING (6)\r
\r
/**\r
Returns a 16-bit signature built from 2 ASCII characters.\r
@return A 16-bit value built from the two ASCII characters specified by A and B.\r
\r
**/\r
-#define SIGNATURE_16(A, B) ((A) | (B << 8))\r
+#define SIGNATURE_16(A, B) ((A) | (B << 8))\r
\r
/**\r
Returns a 32-bit signature built from 4 ASCII characters.\r
#define SIGNATURE_64(A, B, C, D, E, F, G, H) \\r
(SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))\r
\r
-#if defined(_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)\r
- void * _ReturnAddress(void);\r
+#if defined (_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)\r
+void *\r
+_ReturnAddress (\r
+ void\r
+ );\r
+\r
#pragma intrinsic(_ReturnAddress)\r
- /**\r
- Get the return address of the calling function.\r
\r
- Based on intrinsic function _ReturnAddress that provides the address of\r
- the instruction in the calling function that will be executed after\r
- control returns to the caller.\r
+/**\r
+ Get the return address of the calling function.\r
+\r
+ Based on intrinsic function _ReturnAddress that provides the address of\r
+ the instruction in the calling function that will be executed after\r
+ control returns to the caller.\r
\r
- @param L Return Level.\r
+ @param L Return Level.\r
\r
- @return The return address of the calling function or 0 if L != 0.\r
+ @return The return address of the calling function or 0 if L != 0.\r
\r
- **/\r
- #define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)\r
+**/\r
+#define RETURN_ADDRESS(L) ((L == 0) ? _ReturnAddress() : (VOID *) 0)\r
#elif defined (__GNUC__) || defined (__clang__)\r
- /**\r
- Get the return address of the calling function.\r
\r
- Based on built-in Function __builtin_return_address that returns\r
- the return address of the current function, or of one of its callers.\r
+/**\r
+ Get the return address of the calling function.\r
+\r
+ Based on built-in Function __builtin_return_address that returns\r
+ the return address of the current function, or of one of its callers.\r
\r
- @param L Return Level.\r
+ @param L Return Level.\r
\r
- @return The return address of the calling function.\r
+ @return The return address of the calling function.\r
\r
- **/\r
- #define RETURN_ADDRESS(L) __builtin_return_address (L)\r
+**/\r
+#define RETURN_ADDRESS(L) __builtin_return_address (L)\r
#else\r
- /**\r
- Get the return address of the calling function.\r
\r
- @param L Return Level.\r
+/**\r
+ Get the return address of the calling function.\r
\r
- @return 0 as compilers don't support this feature.\r
+ @param L Return Level.\r
\r
- **/\r
- #define RETURN_ADDRESS(L) ((VOID *) 0)\r
+ @return 0 as compilers don't support this feature.\r
+\r
+**/\r
+#define RETURN_ADDRESS(L) ((VOID *) 0)\r
#endif\r
\r
/**\r
@return The number of elements in Array. The result has type UINTN.\r
\r
**/\r
-#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))\r
+#define ARRAY_SIZE(Array) (sizeof (Array) / sizeof ((Array)[0]))\r
\r
#endif\r
-\r
///\r
/// 1-byte signed value\r
///\r
-typedef signed char INT8;\r
+typedef signed char INT8;\r
///\r
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
/// values are undefined.\r
///\r
-typedef unsigned char BOOLEAN;\r
+typedef unsigned char BOOLEAN;\r
///\r
/// 1-byte unsigned value.\r
///\r
-typedef unsigned char UINT8;\r
+typedef unsigned char UINT8;\r
///\r
/// 1-byte Character.\r
///\r
-typedef char CHAR8;\r
+typedef char CHAR8;\r
///\r
/// 2-byte signed value.\r
///\r
-typedef short INT16;\r
+typedef short INT16;\r
///\r
/// 2-byte unsigned value.\r
///\r
-typedef unsigned short UINT16;\r
+typedef unsigned short UINT16;\r
///\r
/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
///\r
-typedef unsigned short CHAR16;\r
+typedef unsigned short CHAR16;\r
///\r
/// 4-byte signed value.\r
///\r
-typedef int INT32;\r
+typedef int INT32;\r
///\r
/// 4-byte unsigned value.\r
///\r
-typedef unsigned int UINT32;\r
+typedef unsigned int UINT32;\r
///\r
/// 8-byte signed value.\r
///\r
-typedef __int64 INT64;\r
+typedef __int64 INT64;\r
///\r
/// 8-byte unsigned value.\r
///\r
-typedef unsigned __int64 UINT64;\r
+typedef unsigned __int64 UINT64;\r
\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
/// "long" type scales to the processor native size with EBC compiler\r
///\r
-typedef long INTN;\r
+typedef long INTN;\r
///\r
/// The unsigned value of native width. (4 bytes on supported 32-bit processor instructions;\r
/// 8 bytes on supported 64-bit processor instructions)\r
/// "long" type scales to the processor native size with the EBC compiler.\r
///\r
-typedef unsigned long UINTN;\r
+typedef unsigned long UINTN;\r
\r
///\r
/// A value of native width with the highest bit set.\r
/// Scalable macro to set the most significant bit in a natural number.\r
///\r
-#define MAX_BIT ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1))))\r
+#define MAX_BIT ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1))))\r
///\r
/// A value of native width with the two highest bits set.\r
/// Scalable macro to set the most 2 significant bits in a natural number.\r
///\r
/// Maximum legal EBC address\r
///\r
-#define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))\r
+#define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))\r
\r
///\r
/// Maximum usable address at boot time (48 bits using 4 KB pages)\r
///\r
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
\r
///\r
/// Maximum legal EBC INTN and UINTN values.\r
///\r
/// Minimum legal EBC INTN value.\r
///\r
-#define MIN_INTN (((INTN)-MAX_INTN) - 1)\r
+#define MIN_INTN (((INTN)-MAX_INTN) - 1)\r
\r
///\r
/// The stack alignment required for EBC\r
///\r
-#define CPU_STACK_ALIGNMENT sizeof(UINTN)\r
+#define CPU_STACK_ALIGNMENT sizeof(UINTN)\r
\r
///\r
/// Page allocation granularity for EBC\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
\r
///\r
/// Modifier to ensure that all protocol member functions and EFI intrinsics\r
/// EFI intrinsics are required to modify their member functions with EFIAPI.\r
///\r
#ifdef EFIAPI\r
- ///\r
- /// If EFIAPI is already defined, then we use that definition.\r
- ///\r
+///\r
+/// If EFIAPI is already defined, then we use that definition.\r
+///\r
#else\r
#define EFIAPI\r
#endif\r
\r
@return The pointer to the first instruction of a function given a function pointer.\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
#define __USER_LABEL_PREFIX__\r
#endif\r
\r
#endif\r
-\r
0x8868e871, 0xe4f1, 0x11d3, {0xbc, 0x22, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
\r
-#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID\r
+#define ACPI_10_TABLE_GUID ACPI_TABLE_GUID\r
\r
//\r
// ACPI 2.0 or newer tables should use EFI_ACPI_TABLE_GUID.\r
//\r
-#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID\r
+#define EFI_ACPI_20_TABLE_GUID EFI_ACPI_TABLE_GUID\r
\r
-extern EFI_GUID gEfiAcpiTableGuid;\r
-extern EFI_GUID gEfiAcpi10TableGuid;\r
-extern EFI_GUID gEfiAcpi20TableGuid;\r
+extern EFI_GUID gEfiAcpiTableGuid;\r
+extern EFI_GUID gEfiAcpi10TableGuid;\r
+extern EFI_GUID gEfiAcpi20TableGuid;\r
\r
#endif\r
0xfc510ee7, 0xffdc, 0x11d4, {0xbd, 0x41, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
}\r
\r
-extern EFI_GUID gAprioriGuid;\r
+extern EFI_GUID gAprioriGuid;\r
\r
#endif\r
#define PEI_APRIORI_FILE_NAME_GUID \\r
{ 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }\r
\r
-\r
///\r
/// This file must be of type EFI_FV_FILETYPE_FREEFORM and must\r
/// contain a single section of type EFI_SECTION_RAW. For details on\r
/// An array of zero or more EFI_GUID type entries that match the file names of PEIM\r
/// modules in the same Firmware Volume. The maximum number of entries.\r
///\r
- EFI_GUID FileNamesWithinVolume[1];\r
+ EFI_GUID FileNamesWithinVolume[1];\r
} PEI_APRIORI_FILE_CONTENTS;\r
\r
-extern EFI_GUID gPeiAprioriFileNameGuid;\r
+extern EFI_GUID gPeiAprioriFileNameGuid;\r
\r
#endif\r
-\r
//\r
// Alignment of all BTT structures\r
//\r
-#define EFI_BTT_ALIGNMENT 4096\r
+#define EFI_BTT_ALIGNMENT 4096\r
\r
-#define EFI_BTT_INFO_UNUSED_LEN 3968\r
+#define EFI_BTT_INFO_UNUSED_LEN 3968\r
\r
-#define EFI_BTT_INFO_BLOCK_SIG_LEN 16\r
+#define EFI_BTT_INFO_BLOCK_SIG_LEN 16\r
\r
///\r
/// Indicate inconsistent metadata or lost metadata due to unrecoverable media errors.\r
///\r
-#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001\r
+#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR 0x00000001\r
\r
-#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2\r
-#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0\r
+#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2\r
+#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0\r
\r
///\r
/// Block Translation Table (BTT) Info Block\r
/// Signature of the BTT Index Block data structure.\r
/// Shall be "BTT_ARENA_INFO\0\0".\r
///\r
- CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];\r
+ CHAR8 Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];\r
\r
///\r
/// UUID identifying this BTT instance.\r
///\r
- GUID Uuid;\r
+ GUID Uuid;\r
\r
///\r
/// UUID of containing namespace.\r
///\r
- GUID ParentUuid;\r
+ GUID ParentUuid;\r
\r
///\r
/// Attributes of this BTT Info Block.\r
///\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
///\r
/// Major version number. Currently at version 2.\r
///\r
- UINT16 Major;\r
+ UINT16 Major;\r
\r
///\r
/// Minor version number. Currently at version 0.\r
///\r
- UINT16 Minor;\r
+ UINT16 Minor;\r
\r
///\r
/// Advertised LBA size in bytes. I/O requests shall be in this size chunk.\r
///\r
- UINT32 ExternalLbaSize;\r
+ UINT32 ExternalLbaSize;\r
\r
///\r
/// Advertised number of LBAs in this arena.\r
///\r
- UINT32 ExternalNLba;\r
+ UINT32 ExternalNLba;\r
\r
///\r
/// Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512 bytes.\r
///\r
- UINT32 InternalLbaSize;\r
+ UINT32 InternalLbaSize;\r
\r
///\r
/// Number of internal blocks in the arena data area.\r
///\r
- UINT32 InternalNLba;\r
+ UINT32 InternalNLba;\r
\r
///\r
/// Number of free blocks maintained for writes to this arena.\r
///\r
- UINT32 NFree;\r
+ UINT32 NFree;\r
\r
///\r
/// The size of this info block in bytes.\r
///\r
- UINT32 InfoSize;\r
+ UINT32 InfoSize;\r
\r
///\r
/// Offset of next arena, relative to the beginning of this arena.\r
///\r
- UINT64 NextOff;\r
+ UINT64 NextOff;\r
\r
///\r
/// Offset of the data area for this arena, relative to the beginning of this arena.\r
///\r
- UINT64 DataOff;\r
+ UINT64 DataOff;\r
\r
///\r
/// Offset of the map for this arena, relative to the beginning of this arena.\r
///\r
- UINT64 MapOff;\r
+ UINT64 MapOff;\r
\r
///\r
/// Offset of the flog for this arena, relative to the beginning of this arena.\r
///\r
- UINT64 FlogOff;\r
+ UINT64 FlogOff;\r
\r
///\r
/// Offset of the backup copy of this arena's info block, relative to the beginning of this arena.\r
///\r
- UINT64 InfoOff;\r
+ UINT64 InfoOff;\r
\r
///\r
/// Shall be zero.\r
///\r
- CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN];\r
+ CHAR8 Unused[EFI_BTT_INFO_UNUSED_LEN];\r
\r
///\r
/// 64-bit Fletcher64 checksum of all fields.\r
///\r
- UINT64 Checksum;\r
+ UINT64 Checksum;\r
} EFI_BTT_INFO_BLOCK;\r
\r
///\r
///\r
/// Post-map LBA number (block number in this arena's data area)\r
///\r
- UINT32 PostMapLba : 30;\r
+ UINT32 PostMapLba : 30;\r
\r
///\r
/// When set and Zero is not set, reads on this block return an error.\r
/// When set and Zero is set, indicate a map entry in its normal, non-error state.\r
///\r
- UINT32 Error : 1;\r
+ UINT32 Error : 1;\r
\r
///\r
/// When set and Error is not set, reads on this block return a full block of zeros.\r
/// When set and Error is set, indicate a map entry in its normal, non-error state.\r
///\r
- UINT32 Zero : 1;\r
+ UINT32 Zero : 1;\r
} EFI_BTT_MAP_ENTRY;\r
\r
///\r
/// Alignment of each flog structure\r
///\r
-#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64\r
+#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64\r
\r
///\r
/// The BTT Flog is both a free list and a log.\r
///\r
/// Last pre-map LBA written using this flog entry.\r
///\r
- UINT32 Lba0;\r
+ UINT32 Lba0;\r
\r
///\r
/// Old post-map LBA.\r
///\r
- UINT32 OldMap0;\r
+ UINT32 OldMap0;\r
\r
///\r
/// New post-map LBA.\r
///\r
- UINT32 NewMap0;\r
+ UINT32 NewMap0;\r
\r
///\r
/// The Seq0 field in each flog entry is used to determine which set of fields is newer between the two sets\r
/// (Lba0, OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1).\r
///\r
- UINT32 Seq0;\r
+ UINT32 Seq0;\r
\r
///\r
/// Alternate lba entry.\r
///\r
- UINT32 Lba1;\r
+ UINT32 Lba1;\r
\r
///\r
/// Alternate old entry.\r
///\r
- UINT32 OldMap1;\r
+ UINT32 OldMap1;\r
\r
///\r
/// Alternate new entry.\r
///\r
- UINT32 NewMap1;\r
+ UINT32 NewMap1;\r
\r
///\r
/// Alternate Seq entry.\r
///\r
- UINT32 Seq1;\r
+ UINT32 Seq1;\r
} EFI_BTT_FLOG;\r
\r
-extern GUID gEfiBttAbstractionGuid;\r
+extern GUID gEfiBttAbstractionGuid;\r
\r
#endif //_BTT_H_\r
\r
**/\r
\r
-\r
#ifndef _CAPSULE_REPORT_GUID_H__\r
#define _CAPSULE_REPORT_GUID_H__\r
\r
0x39b68c46, 0xf7fb, 0x441b, {0xb6, 0xec, 0x16, 0xb0, 0xf6, 0x98, 0x21, 0xf3 } \\r
}\r
\r
-\r
typedef struct {\r
-\r
///\r
/// Size in bytes of the variable including any data beyond header as specified by CapsuleGuid\r
///\r
- UINT32 VariableTotalSize;\r
+ UINT32 VariableTotalSize;\r
\r
///\r
/// For alignment\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
\r
///\r
/// Guid from EFI_CAPSULE_HEADER\r
///\r
- EFI_GUID CapsuleGuid;\r
+ EFI_GUID CapsuleGuid;\r
\r
///\r
/// Timestamp using system time when processing completed\r
///\r
- EFI_TIME CapsuleProcessed;\r
+ EFI_TIME CapsuleProcessed;\r
\r
///\r
/// Result of the capsule processing. Exact interpretation of any error code may depend\r
/// upon type of capsule processed\r
///\r
- EFI_STATUS CapsuleStatus;\r
+ EFI_STATUS CapsuleStatus;\r
} EFI_CAPSULE_RESULT_VARIABLE_HEADER;\r
\r
-\r
typedef struct {\r
-\r
///\r
/// Version of this structure, currently 0x00000001\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
\r
///\r
/// The index of the payload within the FMP capsule which was processed to generate this report\r
/// Starting from zero\r
///\r
- UINT8 PayloadIndex;\r
+ UINT8 PayloadIndex;\r
\r
///\r
/// The UpdateImageIndex from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER\r
/// (after unsigned conversion from UINT8 to UINT16).\r
///\r
- UINT8 UpdateImageIndex;\r
+ UINT8 UpdateImageIndex;\r
\r
///\r
/// The UpdateImageTypeId Guid from EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER.\r
///\r
- EFI_GUID UpdateImageTypeId;\r
+ EFI_GUID UpdateImageTypeId;\r
\r
///\r
/// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.\r
} EFI_CAPSULE_RESULT_VARIABLE_FMP;\r
\r
typedef struct {\r
-\r
///\r
/// Version of this structure, currently 0x00000001\r
///\r
/// The JSON payload shall conform to a Redfish-defined JSON schema, see DMTF-Redfish\r
/// Specification.\r
///\r
- UINT32 CapsuleId;\r
+ UINT32 CapsuleId;\r
\r
///\r
/// The length of Resp in bytes.\r
///\r
- UINT32 RespLength;\r
+ UINT32 RespLength;\r
\r
///\r
/// Variable length buffer containing the replied JSON payload to the caller who delivered JSON\r
/// capsule to system. The definition of the JSON schema used in the replied payload is beyond\r
/// the scope of this specification.\r
///\r
- UINT8 Resp[];\r
- } EFI_CAPSULE_RESULT_VARIABLE_JSON;\r
+ UINT8 Resp[];\r
+} EFI_CAPSULE_RESULT_VARIABLE_JSON;\r
\r
-extern EFI_GUID gEfiCapsuleReportGuid;\r
+extern EFI_GUID gEfiCapsuleReportGuid;\r
\r
#endif\r
\r
#pragma pack(1)\r
\r
-#define EFI_ERROR_RECORD_SIGNATURE_START SIGNATURE_32('C', 'P', 'E', 'R')\r
-#define EFI_ERROR_RECORD_SIGNATURE_END 0xFFFFFFFF\r
+#define EFI_ERROR_RECORD_SIGNATURE_START SIGNATURE_32('C', 'P', 'E', 'R')\r
+#define EFI_ERROR_RECORD_SIGNATURE_END 0xFFFFFFFF\r
\r
-#define EFI_ERROR_RECORD_REVISION 0x0101\r
+#define EFI_ERROR_RECORD_REVISION 0x0101\r
\r
///\r
/// Error Severity in Error Record Header and Error Section Descriptor\r
///@{\r
-#define EFI_GENERIC_ERROR_RECOVERABLE 0x00000000\r
-#define EFI_GENERIC_ERROR_FATAL 0x00000001\r
-#define EFI_GENERIC_ERROR_CORRECTED 0x00000002\r
-#define EFI_GENERIC_ERROR_INFO 0x00000003\r
+#define EFI_GENERIC_ERROR_RECOVERABLE 0x00000000\r
+#define EFI_GENERIC_ERROR_FATAL 0x00000001\r
+#define EFI_GENERIC_ERROR_CORRECTED 0x00000002\r
+#define EFI_GENERIC_ERROR_INFO 0x00000003\r
///@}\r
\r
///\r
/// The validation bit mask indicates the validity of the following fields\r
/// in Error Record Header.\r
///@{\r
-#define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0\r
-#define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1\r
-#define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2\r
+#define EFI_ERROR_RECORD_HEADER_PLATFORM_ID_VALID BIT0\r
+#define EFI_ERROR_RECORD_HEADER_TIME_STAMP_VALID BIT1\r
+#define EFI_ERROR_RECORD_HEADER_PARTITION_ID_VALID BIT2\r
///@}\r
\r
///\r
/// Timestamp is precise if this bit is set and correlates to the time of the\r
/// error event.\r
///\r
-#define EFI_ERROR_TIME_STAMP_PRECISE BIT0\r
+#define EFI_ERROR_TIME_STAMP_PRECISE BIT0\r
\r
///\r
/// The timestamp correlates to the time when the error information was collected\r
/// event. The timestamp contains the local time in BCD format.\r
///\r
typedef struct {\r
- UINT8 Seconds;\r
- UINT8 Minutes;\r
- UINT8 Hours;\r
- UINT8 Flag;\r
- UINT8 Day;\r
- UINT8 Month;\r
- UINT8 Year;\r
- UINT8 Century;\r
+ UINT8 Seconds;\r
+ UINT8 Minutes;\r
+ UINT8 Hours;\r
+ UINT8 Flag;\r
+ UINT8 Day;\r
+ UINT8 Month;\r
+ UINT8 Year;\r
+ UINT8 Century;\r
} EFI_ERROR_TIME_STAMP;\r
\r
///\r
///\r
/// Error Record Header Flags\r
///@{\r
-#define EFI_HW_ERROR_FLAGS_RECOVERED 0x00000001\r
-#define EFI_HW_ERROR_FLAGS_PREVERR 0x00000002\r
-#define EFI_HW_ERROR_FLAGS_SIMULATED 0x00000004\r
+#define EFI_HW_ERROR_FLAGS_RECOVERED 0x00000001\r
+#define EFI_HW_ERROR_FLAGS_PREVERR 0x00000002\r
+#define EFI_HW_ERROR_FLAGS_SIMULATED 0x00000004\r
///@}\r
\r
///\r
/// Common error record header\r
///\r
typedef struct {\r
- UINT32 SignatureStart;\r
- UINT16 Revision;\r
- UINT32 SignatureEnd;\r
- UINT16 SectionCount;\r
- UINT32 ErrorSeverity;\r
- UINT32 ValidationBits;\r
- UINT32 RecordLength;\r
- EFI_ERROR_TIME_STAMP TimeStamp;\r
- EFI_GUID PlatformID;\r
- EFI_GUID PartitionID;\r
- EFI_GUID CreatorID;\r
- EFI_GUID NotificationType;\r
- UINT64 RecordID;\r
- UINT32 Flags;\r
- UINT64 PersistenceInfo;\r
- UINT8 Resv1[12];\r
+ UINT32 SignatureStart;\r
+ UINT16 Revision;\r
+ UINT32 SignatureEnd;\r
+ UINT16 SectionCount;\r
+ UINT32 ErrorSeverity;\r
+ UINT32 ValidationBits;\r
+ UINT32 RecordLength;\r
+ EFI_ERROR_TIME_STAMP TimeStamp;\r
+ EFI_GUID PlatformID;\r
+ EFI_GUID PartitionID;\r
+ EFI_GUID CreatorID;\r
+ EFI_GUID NotificationType;\r
+ UINT64 RecordID;\r
+ UINT32 Flags;\r
+ UINT64 PersistenceInfo;\r
+ UINT8 Resv1[12];\r
///\r
/// An array of SectionCount descriptors for the associated\r
/// sections. The number of valid sections is equivalent to the\r
///\r
/// Validity Fields in Error Section Descriptor.\r
///\r
-#define EFI_ERROR_SECTION_FRU_ID_VALID BIT0\r
-#define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1\r
+#define EFI_ERROR_SECTION_FRU_ID_VALID BIT0\r
+#define EFI_ERROR_SECTION_FRU_STRING_VALID BIT1\r
\r
///\r
/// Flag field contains information that describes the error section\r
/// in Error Section Descriptor.\r
///\r
-#define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0\r
-#define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1\r
-#define EFI_ERROR_SECTION_FLAGS_RESET BIT2\r
-#define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3\r
-#define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE BIT4\r
-#define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR BIT5\r
+#define EFI_ERROR_SECTION_FLAGS_PRIMARY BIT0\r
+#define EFI_ERROR_SECTION_FLAGS_CONTAINMENT_WARNING BIT1\r
+#define EFI_ERROR_SECTION_FLAGS_RESET BIT2\r
+#define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3\r
+#define EFI_ERROR_SECTION_FLAGS_RESOURCE_NOT_ACCESSIBLE BIT4\r
+#define EFI_ERROR_SECTION_FLAGS_LATENT_ERROR BIT5\r
\r
///\r
/// Error Sectition Type GUIDs in Error Section Descriptor\r
/// Error Section Descriptor\r
///\r
typedef struct {\r
- UINT32 SectionOffset;\r
- UINT32 SectionLength;\r
- UINT16 Revision;\r
- UINT8 SecValidMask;\r
- UINT8 Resv1;\r
- UINT32 SectionFlags;\r
- EFI_GUID SectionType;\r
- EFI_GUID FruId;\r
- UINT32 Severity;\r
- CHAR8 FruString[20];\r
+ UINT32 SectionOffset;\r
+ UINT32 SectionLength;\r
+ UINT16 Revision;\r
+ UINT8 SecValidMask;\r
+ UINT8 Resv1;\r
+ UINT32 SectionFlags;\r
+ EFI_GUID SectionType;\r
+ EFI_GUID FruId;\r
+ UINT32 Severity;\r
+ CHAR8 FruString[20];\r
} EFI_ERROR_SECTION_DESCRIPTOR;\r
\r
///\r
/// The validation bit mask indicates whether or not each of the following fields are\r
/// valid in Proessor Generic Error section.\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0\r
-#define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID BIT2\r
-#define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3\r
-#define EFI_GENERIC_ERROR_PROC_FLAGS_VALID BIT4\r
-#define EFI_GENERIC_ERROR_PROC_LEVEL_VALID BIT5\r
-#define EFI_GENERIC_ERROR_PROC_VERSION_VALID BIT6\r
-#define EFI_GENERIC_ERROR_PROC_BRAND_VALID BIT7\r
-#define EFI_GENERIC_ERROR_PROC_ID_VALID BIT8\r
-#define EFI_GENERIC_ERROR_PROC_TARGET_ADDR_VALID BIT9\r
-#define EFI_GENERIC_ERROR_PROC_REQUESTER_ID_VALID BIT10\r
-#define EFI_GENERIC_ERROR_PROC_RESPONDER_ID_VALID BIT11\r
-#define EFI_GENERIC_ERROR_PROC_INST_IP_VALID BIT12\r
+#define EFI_GENERIC_ERROR_PROC_TYPE_VALID BIT0\r
+#define EFI_GENERIC_ERROR_PROC_ISA_VALID BIT1\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_VALID BIT2\r
+#define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3\r
+#define EFI_GENERIC_ERROR_PROC_FLAGS_VALID BIT4\r
+#define EFI_GENERIC_ERROR_PROC_LEVEL_VALID BIT5\r
+#define EFI_GENERIC_ERROR_PROC_VERSION_VALID BIT6\r
+#define EFI_GENERIC_ERROR_PROC_BRAND_VALID BIT7\r
+#define EFI_GENERIC_ERROR_PROC_ID_VALID BIT8\r
+#define EFI_GENERIC_ERROR_PROC_TARGET_ADDR_VALID BIT9\r
+#define EFI_GENERIC_ERROR_PROC_REQUESTER_ID_VALID BIT10\r
+#define EFI_GENERIC_ERROR_PROC_RESPONDER_ID_VALID BIT11\r
+#define EFI_GENERIC_ERROR_PROC_INST_IP_VALID BIT12\r
///@}\r
\r
///\r
/// The type of the processor architecture in Proessor Generic Error section.\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00\r
-#define EFI_GENERIC_ERROR_PROC_TYPE_IA64 0x01\r
-#define EFI_GENERIC_ERROR_PROC_TYPE_ARM 0x02\r
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64 0x00\r
+#define EFI_GENERIC_ERROR_PROC_TYPE_IA64 0x01\r
+#define EFI_GENERIC_ERROR_PROC_TYPE_ARM 0x02\r
///@}\r
\r
///\r
/// The type of the instruction set executing when the error occurred in Proessor\r
/// Generic Error section.\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00\r
-#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01\r
-#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02\r
-#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03\r
-#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04\r
+#define EFI_GENERIC_ERROR_PROC_ISA_IA32 0x00\r
+#define EFI_GENERIC_ERROR_PROC_ISA_IA64 0x01\r
+#define EFI_GENERIC_ERROR_PROC_ISA_X64 0x02\r
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32 0x03\r
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64 0x04\r
///@}\r
\r
///\r
/// The type of error that occurred in Proessor Generic Error section.\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_UNKNOWN 0x00\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_CACHE 0x01\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_TLB 0x02\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_BUS 0x04\r
-#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_MICRO_ARCH 0x08\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_UNKNOWN 0x00\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_CACHE 0x01\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_TLB 0x02\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_BUS 0x04\r
+#define EFI_GENERIC_ERROR_PROC_ERROR_TYPE_MICRO_ARCH 0x08\r
///@}\r
\r
///\r
/// The type of operation in Proessor Generic Error section.\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_OPERATION_GENERIC 0x00\r
-#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_READ 0x01\r
-#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_WRITE 0x02\r
-#define EFI_GENERIC_ERROR_PROC_OPERATION_INSTRUCTION_EXEC 0x03\r
+#define EFI_GENERIC_ERROR_PROC_OPERATION_GENERIC 0x00\r
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_READ 0x01\r
+#define EFI_GENERIC_ERROR_PROC_OPERATION_DATA_WRITE 0x02\r
+#define EFI_GENERIC_ERROR_PROC_OPERATION_INSTRUCTION_EXEC 0x03\r
///@}\r
\r
///\r
/// Flags bit mask indicates additional information about the error in Proessor Generic\r
/// Error section\r
///@{\r
-#define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0\r
-#define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1\r
-#define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW BIT2\r
-#define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3\r
+#define EFI_GENERIC_ERROR_PROC_FLAGS_RESTARTABLE BIT0\r
+#define EFI_GENERIC_ERROR_PROC_FLAGS_PRECISE_IP BIT1\r
+#define EFI_GENERIC_ERROR_PROC_FLAGS_OVERFLOW BIT2\r
+#define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3\r
///@}\r
\r
///\r
/// describes processor reported hardware errors for logical processors in the system.\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- UINT8 Type;\r
- UINT8 Isa;\r
- UINT8 ErrorType;\r
- UINT8 Operation;\r
- UINT8 Flags;\r
- UINT8 Level;\r
- UINT16 Resv1;\r
- UINT64 VersionInfo;\r
- CHAR8 BrandString[128];\r
- UINT64 ApicId;\r
- UINT64 TargetAddr;\r
- UINT64 RequestorId;\r
- UINT64 ResponderId;\r
- UINT64 InstructionIP;\r
+ UINT64 ValidFields;\r
+ UINT8 Type;\r
+ UINT8 Isa;\r
+ UINT8 ErrorType;\r
+ UINT8 Operation;\r
+ UINT8 Flags;\r
+ UINT8 Level;\r
+ UINT16 Resv1;\r
+ UINT64 VersionInfo;\r
+ CHAR8 BrandString[128];\r
+ UINT64 ApicId;\r
+ UINT64 TargetAddr;\r
+ UINT64 RequestorId;\r
+ UINT64 ResponderId;\r
+ UINT64 InstructionIP;\r
} EFI_PROCESSOR_GENERIC_ERROR_DATA;\r
\r
-\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
/// IA32 and x64 Specific definitions.\r
/// The validation bit mask indicates which fields in the IA32/X64 Processor\r
/// Error Record structure are valid.\r
///@{\r
-#define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID BIT0\r
-#define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1\r
+#define EFI_IA32_X64_PROCESSOR_ERROR_APIC_ID_VALID BIT0\r
+#define EFI_IA32_X64_PROCESSOR_ERROR_CPU_ID_INFO_VALID BIT1\r
///@}\r
\r
///\r
/// IA32/X64 Processor Error Record\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- UINT64 ApicId;\r
- UINT8 CpuIdInfo[48];\r
+ UINT64 ValidFields;\r
+ UINT64 ApicId;\r
+ UINT8 CpuIdInfo[48];\r
} EFI_IA32_X64_PROCESSOR_ERROR_RECORD;\r
\r
///\r
/// The validation bit mask indicates which fields in the Cache Check structure\r
/// are valid.\r
///@{\r
-#define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0\r
-#define EFI_CACHE_CHECK_OPERATION_VALID BIT1\r
-#define EFI_CACHE_CHECK_LEVEL_VALID BIT2\r
-#define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
-#define EFI_CACHE_CHECK_UNCORRECTED_VALID BIT4\r
-#define EFI_CACHE_CHECK_PRECISE_IP_VALID BIT5\r
-#define EFI_CACHE_CHECK_RESTARTABLE_VALID BIT6\r
-#define EFI_CACHE_CHECK_OVERFLOW_VALID BIT7\r
+#define EFI_CACHE_CHECK_TRANSACTION_TYPE_VALID BIT0\r
+#define EFI_CACHE_CHECK_OPERATION_VALID BIT1\r
+#define EFI_CACHE_CHECK_LEVEL_VALID BIT2\r
+#define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
+#define EFI_CACHE_CHECK_UNCORRECTED_VALID BIT4\r
+#define EFI_CACHE_CHECK_PRECISE_IP_VALID BIT5\r
+#define EFI_CACHE_CHECK_RESTARTABLE_VALID BIT6\r
+#define EFI_CACHE_CHECK_OVERFLOW_VALID BIT7\r
///@}\r
\r
///\r
/// Type of cache error in the Cache Check structure\r
///@{\r
-#define EFI_CACHE_CHECK_ERROR_TYPE_INSTRUCTION 0\r
-#define EFI_CACHE_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
-#define EFI_CACHE_CHECK_ERROR_TYPE_GENERIC 2\r
+#define EFI_CACHE_CHECK_ERROR_TYPE_INSTRUCTION 0\r
+#define EFI_CACHE_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
+#define EFI_CACHE_CHECK_ERROR_TYPE_GENERIC 2\r
///@}\r
\r
///\r
/// Type of cache operation that caused the error in the Cache\r
/// Check structure\r
///@{\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC 0\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_READ 3\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_INSTRUCTION_FETCH 5\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_PREFETCH 6\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_EVICTION 7\r
-#define EFI_CACHE_CHECK_OPERATION_TYPE_SNOOP 8\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC 0\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_READ 3\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_INSTRUCTION_FETCH 5\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_PREFETCH 6\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_EVICTION 7\r
+#define EFI_CACHE_CHECK_OPERATION_TYPE_SNOOP 8\r
///@}\r
\r
///\r
/// IA32/X64 Cache Check Structure\r
///\r
typedef struct {\r
- UINT64 ValidFields:16;\r
- UINT64 TransactionType:2;\r
- UINT64 Operation:4;\r
- UINT64 Level:3;\r
- UINT64 ContextCorrupt:1;\r
- UINT64 ErrorUncorrected:1;\r
- UINT64 PreciseIp:1;\r
- UINT64 RestartableIp:1;\r
- UINT64 Overflow:1;\r
- UINT64 Resv1:34;\r
+ UINT64 ValidFields : 16;\r
+ UINT64 TransactionType : 2;\r
+ UINT64 Operation : 4;\r
+ UINT64 Level : 3;\r
+ UINT64 ContextCorrupt : 1;\r
+ UINT64 ErrorUncorrected : 1;\r
+ UINT64 PreciseIp : 1;\r
+ UINT64 RestartableIp : 1;\r
+ UINT64 Overflow : 1;\r
+ UINT64 Resv1 : 34;\r
} EFI_IA32_X64_CACHE_CHECK_INFO;\r
\r
///\r
/// The validation bit mask indicates which fields in the TLB Check structure\r
/// are valid.\r
///@{\r
-#define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0\r
-#define EFI_TLB_CHECK_OPERATION_VALID BIT1\r
-#define EFI_TLB_CHECK_LEVEL_VALID BIT2\r
-#define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
-#define EFI_TLB_CHECK_UNCORRECTED_VALID BIT4\r
-#define EFI_TLB_CHECK_PRECISE_IP_VALID BIT5\r
-#define EFI_TLB_CHECK_RESTARTABLE_VALID BIT6\r
-#define EFI_TLB_CHECK_OVERFLOW_VALID BIT7\r
+#define EFI_TLB_CHECK_TRANSACTION_TYPE_VALID BIT0\r
+#define EFI_TLB_CHECK_OPERATION_VALID BIT1\r
+#define EFI_TLB_CHECK_LEVEL_VALID BIT2\r
+#define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
+#define EFI_TLB_CHECK_UNCORRECTED_VALID BIT4\r
+#define EFI_TLB_CHECK_PRECISE_IP_VALID BIT5\r
+#define EFI_TLB_CHECK_RESTARTABLE_VALID BIT6\r
+#define EFI_TLB_CHECK_OVERFLOW_VALID BIT7\r
///@}\r
\r
///\r
/// Type of cache error in the TLB Check structure\r
///@{\r
-#define EFI_TLB_CHECK_ERROR_TYPE_INSTRUCTION 0\r
-#define EFI_TLB_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
-#define EFI_TLB_CHECK_ERROR_TYPE_GENERIC 2\r
+#define EFI_TLB_CHECK_ERROR_TYPE_INSTRUCTION 0\r
+#define EFI_TLB_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
+#define EFI_TLB_CHECK_ERROR_TYPE_GENERIC 2\r
///@}\r
\r
///\r
/// Type of cache operation that caused the error in the TLB\r
/// Check structure\r
///@{\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC 0\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_READ 3\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_INST_FETCH 5\r
-#define EFI_TLB_CHECK_OPERATION_TYPE_PREFETCH 6\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC 0\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_READ 3\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_INST_FETCH 5\r
+#define EFI_TLB_CHECK_OPERATION_TYPE_PREFETCH 6\r
///@}\r
\r
///\r
/// IA32/X64 TLB Check Structure\r
///\r
typedef struct {\r
- UINT64 ValidFields:16;\r
- UINT64 TransactionType:2;\r
- UINT64 Operation:4;\r
- UINT64 Level:3;\r
- UINT64 ContextCorrupt:1;\r
- UINT64 ErrorUncorrected:1;\r
- UINT64 PreciseIp:1;\r
- UINT64 RestartableIp:1;\r
- UINT64 Overflow:1;\r
- UINT64 Resv1:34;\r
+ UINT64 ValidFields : 16;\r
+ UINT64 TransactionType : 2;\r
+ UINT64 Operation : 4;\r
+ UINT64 Level : 3;\r
+ UINT64 ContextCorrupt : 1;\r
+ UINT64 ErrorUncorrected : 1;\r
+ UINT64 PreciseIp : 1;\r
+ UINT64 RestartableIp : 1;\r
+ UINT64 Overflow : 1;\r
+ UINT64 Resv1 : 34;\r
} EFI_IA32_X64_TLB_CHECK_INFO;\r
\r
///\r
/// The validation bit mask indicates which fields in the MS Check structure\r
/// are valid.\r
///@{\r
-#define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0\r
-#define EFI_BUS_CHECK_OPERATION_VALID BIT1\r
-#define EFI_BUS_CHECK_LEVEL_VALID BIT2\r
-#define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
-#define EFI_BUS_CHECK_UNCORRECTED_VALID BIT4\r
-#define EFI_BUS_CHECK_PRECISE_IP_VALID BIT5\r
-#define EFI_BUS_CHECK_RESTARTABLE_VALID BIT6\r
-#define EFI_BUS_CHECK_OVERFLOW_VALID BIT7\r
-#define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8\r
-#define EFI_BUS_CHECK_TIME_OUT_VALID BIT9\r
-#define EFI_BUS_CHECK_ADDRESS_SPACE_VALID BIT10\r
+#define EFI_BUS_CHECK_TRANSACTION_TYPE_VALID BIT0\r
+#define EFI_BUS_CHECK_OPERATION_VALID BIT1\r
+#define EFI_BUS_CHECK_LEVEL_VALID BIT2\r
+#define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3\r
+#define EFI_BUS_CHECK_UNCORRECTED_VALID BIT4\r
+#define EFI_BUS_CHECK_PRECISE_IP_VALID BIT5\r
+#define EFI_BUS_CHECK_RESTARTABLE_VALID BIT6\r
+#define EFI_BUS_CHECK_OVERFLOW_VALID BIT7\r
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_VALID BIT8\r
+#define EFI_BUS_CHECK_TIME_OUT_VALID BIT9\r
+#define EFI_BUS_CHECK_ADDRESS_SPACE_VALID BIT10\r
///@}\r
\r
///\r
/// Type of cache error in the Bus Check structure\r
///@{\r
-#define EFI_BUS_CHECK_ERROR_TYPE_INSTRUCTION 0\r
-#define EFI_BUS_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
-#define EFI_BUS_CHECK_ERROR_TYPE_GENERIC 2\r
+#define EFI_BUS_CHECK_ERROR_TYPE_INSTRUCTION 0\r
+#define EFI_BUS_CHECK_ERROR_TYPE_DATA_ACCESS 1\r
+#define EFI_BUS_CHECK_ERROR_TYPE_GENERIC 2\r
///@}\r
\r
///\r
/// Type of cache operation that caused the error in the Bus\r
/// Check structure\r
///@{\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC 0\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_READ 3\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_INST_FETCH 5\r
-#define EFI_BUS_CHECK_OPERATION_TYPE_PREFETCH 6\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC 0\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_READ 1\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_GENERIC_WRITE 2\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_READ 3\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_DATA_WRITE 4\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_INST_FETCH 5\r
+#define EFI_BUS_CHECK_OPERATION_TYPE_PREFETCH 6\r
///@}\r
\r
///\r
/// Type of Participation\r
///@{\r
-#define EFI_BUS_CHECK_PARTICIPATION_TYPE_REQUEST 0\r
-#define EFI_BUS_CHECK_PARTICIPATION_TYPE_RESPONDED 1\r
-#define EFI_BUS_CHECK_PARTICIPATION_TYPE_OBSERVED 2\r
-#define EFI_BUS_CHECK_PARTICIPATION_TYPE_GENERIC 3\r
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_REQUEST 0\r
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_RESPONDED 1\r
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_OBSERVED 2\r
+#define EFI_BUS_CHECK_PARTICIPATION_TYPE_GENERIC 3\r
///@}\r
\r
///\r
/// Type of Address Space\r
///@{\r
-#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_MEMORY 0\r
-#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_RESERVED 1\r
-#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_IO 2\r
-#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_OTHER 3\r
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_MEMORY 0\r
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_RESERVED 1\r
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_IO 2\r
+#define EFI_BUS_CHECK_ADDRESS_SPACE_TYPE_OTHER 3\r
///@}\r
\r
///\r
/// IA32/X64 Bus Check Structure\r
///\r
typedef struct {\r
- UINT64 ValidFields:16;\r
- UINT64 TransactionType:2;\r
- UINT64 Operation:4;\r
- UINT64 Level:3;\r
- UINT64 ContextCorrupt:1;\r
- UINT64 ErrorUncorrected:1;\r
- UINT64 PreciseIp:1;\r
- UINT64 RestartableIp:1;\r
- UINT64 Overflow:1;\r
- UINT64 ParticipationType:2;\r
- UINT64 TimeOut:1;\r
- UINT64 AddressSpace:2;\r
- UINT64 Resv1:29;\r
+ UINT64 ValidFields : 16;\r
+ UINT64 TransactionType : 2;\r
+ UINT64 Operation : 4;\r
+ UINT64 Level : 3;\r
+ UINT64 ContextCorrupt : 1;\r
+ UINT64 ErrorUncorrected : 1;\r
+ UINT64 PreciseIp : 1;\r
+ UINT64 RestartableIp : 1;\r
+ UINT64 Overflow : 1;\r
+ UINT64 ParticipationType : 2;\r
+ UINT64 TimeOut : 1;\r
+ UINT64 AddressSpace : 2;\r
+ UINT64 Resv1 : 29;\r
} EFI_IA32_X64_BUS_CHECK_INFO;\r
\r
///\r
/// The validation bit mask indicates which fields in the MS Check structure\r
/// are valid.\r
///@{\r
-#define EFI_MS_CHECK_ERROR_TYPE_VALID BIT0\r
-#define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1\r
-#define EFI_MS_CHECK_UNCORRECTED_VALID BIT2\r
-#define EFI_MS_CHECK_PRECISE_IP_VALID BIT3\r
-#define EFI_MS_CHECK_RESTARTABLE_VALID BIT4\r
-#define EFI_MS_CHECK_OVERFLOW_VALID BIT5\r
+#define EFI_MS_CHECK_ERROR_TYPE_VALID BIT0\r
+#define EFI_MS_CHECK_CONTEXT_CORRUPT_VALID BIT1\r
+#define EFI_MS_CHECK_UNCORRECTED_VALID BIT2\r
+#define EFI_MS_CHECK_PRECISE_IP_VALID BIT3\r
+#define EFI_MS_CHECK_RESTARTABLE_VALID BIT4\r
+#define EFI_MS_CHECK_OVERFLOW_VALID BIT5\r
///@}\r
\r
///\r
/// Error type identifies the operation that caused the error.\r
///@{\r
-#define EFI_MS_CHECK_ERROR_TYPE_NO 0\r
-#define EFI_MS_CHECK_ERROR_TYPE_UNCLASSIFIED 1\r
-#define EFI_MS_CHECK_ERROR_TYPE_MICROCODE_PARITY 2\r
-#define EFI_MS_CHECK_ERROR_TYPE_EXTERNAL 3\r
-#define EFI_MS_CHECK_ERROR_TYPE_FRC 4\r
-#define EFI_MS_CHECK_ERROR_TYPE_INTERNAL_UNCLASSIFIED 5\r
+#define EFI_MS_CHECK_ERROR_TYPE_NO 0\r
+#define EFI_MS_CHECK_ERROR_TYPE_UNCLASSIFIED 1\r
+#define EFI_MS_CHECK_ERROR_TYPE_MICROCODE_PARITY 2\r
+#define EFI_MS_CHECK_ERROR_TYPE_EXTERNAL 3\r
+#define EFI_MS_CHECK_ERROR_TYPE_FRC 4\r
+#define EFI_MS_CHECK_ERROR_TYPE_INTERNAL_UNCLASSIFIED 5\r
///@}\r
\r
///\r
/// IA32/X64 MS Check Field Description\r
///\r
typedef struct {\r
- UINT64 ValidFields:16;\r
- UINT64 ErrorType:3;\r
- UINT64 ContextCorrupt:1;\r
- UINT64 ErrorUncorrected:1;\r
- UINT64 PreciseIp:1;\r
- UINT64 RestartableIp:1;\r
- UINT64 Overflow:1;\r
- UINT64 Resv1:40;\r
+ UINT64 ValidFields : 16;\r
+ UINT64 ErrorType : 3;\r
+ UINT64 ContextCorrupt : 1;\r
+ UINT64 ErrorUncorrected : 1;\r
+ UINT64 PreciseIp : 1;\r
+ UINT64 RestartableIp : 1;\r
+ UINT64 Overflow : 1;\r
+ UINT64 Resv1 : 40;\r
} EFI_IA32_X64_MS_CHECK_INFO;\r
\r
///\r
/// IA32/X64 Check Information Item\r
///\r
typedef union {\r
- EFI_IA32_X64_CACHE_CHECK_INFO CacheCheck;\r
- EFI_IA32_X64_TLB_CHECK_INFO TlbCheck;\r
- EFI_IA32_X64_BUS_CHECK_INFO BusCheck;\r
- EFI_IA32_X64_MS_CHECK_INFO MsCheck;\r
- UINT64 Data64;\r
+ EFI_IA32_X64_CACHE_CHECK_INFO CacheCheck;\r
+ EFI_IA32_X64_TLB_CHECK_INFO TlbCheck;\r
+ EFI_IA32_X64_BUS_CHECK_INFO BusCheck;\r
+ EFI_IA32_X64_MS_CHECK_INFO MsCheck;\r
+ UINT64 Data64;\r
} EFI_IA32_X64_CHECK_INFO_ITEM;\r
\r
///\r
/// The validation bit mask indicates which fields in the IA32/X64 Processor Error\r
/// Information Structure are valid.\r
///@{\r
-#define EFI_IA32_X64_ERROR_PROC_CHECK_INFO_VALID BIT0\r
-#define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID BIT1\r
-#define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2\r
-#define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3\r
-#define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID BIT4\r
+#define EFI_IA32_X64_ERROR_PROC_CHECK_INFO_VALID BIT0\r
+#define EFI_IA32_X64_ERROR_PROC_TARGET_ADDR_VALID BIT1\r
+#define EFI_IA32_X64_ERROR_PROC_REQUESTER_ID_VALID BIT2\r
+#define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3\r
+#define EFI_IA32_X64_ERROR_PROC_INST_IP_VALID BIT4\r
///@}\r
\r
///\r
/// IA32/X64 Processor Error Information Structure\r
///\r
typedef struct {\r
- EFI_GUID ErrorType;\r
- UINT64 ValidFields;\r
- EFI_IA32_X64_CHECK_INFO_ITEM CheckInfo;\r
- UINT64 TargetId;\r
- UINT64 RequestorId;\r
- UINT64 ResponderId;\r
- UINT64 InstructionIP;\r
+ EFI_GUID ErrorType;\r
+ UINT64 ValidFields;\r
+ EFI_IA32_X64_CHECK_INFO_ITEM CheckInfo;\r
+ UINT64 TargetId;\r
+ UINT64 RequestorId;\r
+ UINT64 ResponderId;\r
+ UINT64 InstructionIP;\r
} EFI_IA32_X64_PROCESS_ERROR_INFO;\r
\r
///\r
/// IA32/X64 Processor Context Information Structure\r
///\r
typedef struct {\r
- UINT16 RegisterType;\r
- UINT16 ArraySize;\r
- UINT32 MsrAddress;\r
- UINT64 MmRegisterAddress;\r
+ UINT16 RegisterType;\r
+ UINT16 ArraySize;\r
+ UINT32 MsrAddress;\r
+ UINT64 MmRegisterAddress;\r
//\r
// This field will provide the contents of the actual registers or raw data.\r
// The number of Registers or size of the raw data reported is determined\r
///\r
/// Register Context Type\r
///@{\r
-#define EFI_REG_CONTEXT_TYPE_UNCLASSIFIED 0x0000\r
-#define EFI_REG_CONTEXT_TYPE_MSR 0x0001\r
-#define EFI_REG_CONTEXT_TYPE_IA32 0x0002\r
-#define EFI_REG_CONTEXT_TYPE_X64 0x0003\r
-#define EFI_REG_CONTEXT_TYPE_FXSAVE 0x0004\r
-#define EFI_REG_CONTEXT_TYPE_DR_IA32 0x0005\r
-#define EFI_REG_CONTEXT_TYPE_DR_X64 0x0006\r
-#define EFI_REG_CONTEXT_TYPE_MEM_MAP 0x0007\r
+#define EFI_REG_CONTEXT_TYPE_UNCLASSIFIED 0x0000\r
+#define EFI_REG_CONTEXT_TYPE_MSR 0x0001\r
+#define EFI_REG_CONTEXT_TYPE_IA32 0x0002\r
+#define EFI_REG_CONTEXT_TYPE_X64 0x0003\r
+#define EFI_REG_CONTEXT_TYPE_FXSAVE 0x0004\r
+#define EFI_REG_CONTEXT_TYPE_DR_IA32 0x0005\r
+#define EFI_REG_CONTEXT_TYPE_DR_X64 0x0006\r
+#define EFI_REG_CONTEXT_TYPE_MEM_MAP 0x0007\r
///@}\r
\r
///\r
/// IA32 Register State\r
///\r
typedef struct {\r
- UINT32 Eax;\r
- UINT32 Ebx;\r
- UINT32 Ecx;\r
- UINT32 Edx;\r
- UINT32 Esi;\r
- UINT32 Edi;\r
- UINT32 Ebp;\r
- UINT32 Esp;\r
- UINT16 Cs;\r
- UINT16 Ds;\r
- UINT16 Ss;\r
- UINT16 Es;\r
- UINT16 Fs;\r
- UINT16 Gs;\r
- UINT32 Eflags;\r
- UINT32 Eip;\r
- UINT32 Cr0;\r
- UINT32 Cr1;\r
- UINT32 Cr2;\r
- UINT32 Cr3;\r
- UINT32 Cr4;\r
- UINT32 Gdtr[2];\r
- UINT32 Idtr[2];\r
- UINT16 Ldtr;\r
- UINT16 Tr;\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+ UINT32 Esi;\r
+ UINT32 Edi;\r
+ UINT32 Ebp;\r
+ UINT32 Esp;\r
+ UINT16 Cs;\r
+ UINT16 Ds;\r
+ UINT16 Ss;\r
+ UINT16 Es;\r
+ UINT16 Fs;\r
+ UINT16 Gs;\r
+ UINT32 Eflags;\r
+ UINT32 Eip;\r
+ UINT32 Cr0;\r
+ UINT32 Cr1;\r
+ UINT32 Cr2;\r
+ UINT32 Cr3;\r
+ UINT32 Cr4;\r
+ UINT32 Gdtr[2];\r
+ UINT32 Idtr[2];\r
+ UINT16 Ldtr;\r
+ UINT16 Tr;\r
} EFI_CONTEXT_IA32_REGISTER_STATE;\r
\r
///\r
/// X64 Register State\r
///\r
typedef struct {\r
- UINT64 Rax;\r
- UINT64 Rbx;\r
- UINT64 Rcx;\r
- UINT64 Rdx;\r
- UINT64 Rsi;\r
- UINT64 Rdi;\r
- UINT64 Rbp;\r
- UINT64 Rsp;\r
- UINT64 R8;\r
- UINT64 R9;\r
- UINT64 R10;\r
- UINT64 R11;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
- UINT16 Cs;\r
- UINT16 Ds;\r
- UINT16 Ss;\r
- UINT16 Es;\r
- UINT16 Fs;\r
- UINT16 Gs;\r
- UINT32 Resv1;\r
- UINT64 Rflags;\r
- UINT64 Rip;\r
- UINT64 Cr0;\r
- UINT64 Cr1;\r
- UINT64 Cr2;\r
- UINT64 Cr3;\r
- UINT64 Cr4;\r
- UINT64 Gdtr[2];\r
- UINT64 Idtr[2];\r
- UINT16 Ldtr;\r
- UINT16 Tr;\r
+ UINT64 Rax;\r
+ UINT64 Rbx;\r
+ UINT64 Rcx;\r
+ UINT64 Rdx;\r
+ UINT64 Rsi;\r
+ UINT64 Rdi;\r
+ UINT64 Rbp;\r
+ UINT64 Rsp;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+ UINT16 Cs;\r
+ UINT16 Ds;\r
+ UINT16 Ss;\r
+ UINT16 Es;\r
+ UINT16 Fs;\r
+ UINT16 Gs;\r
+ UINT32 Resv1;\r
+ UINT64 Rflags;\r
+ UINT64 Rip;\r
+ UINT64 Cr0;\r
+ UINT64 Cr1;\r
+ UINT64 Cr2;\r
+ UINT64 Cr3;\r
+ UINT64 Cr4;\r
+ UINT64 Gdtr[2];\r
+ UINT64 Idtr[2];\r
+ UINT16 Ldtr;\r
+ UINT16 Tr;\r
} EFI_CONTEXT_X64_REGISTER_STATE;\r
\r
///\r
/// Processor Error Section.\r
///\r
typedef struct {\r
- UINT64 ApicIdValid:1;\r
- UINT64 CpuIdInforValid:1;\r
- UINT64 ErrorInfoNum:6;\r
- UINT64 ContextNum:6;\r
- UINT64 Resv1:50;\r
+ UINT64 ApicIdValid : 1;\r
+ UINT64 CpuIdInforValid : 1;\r
+ UINT64 ErrorInfoNum : 6;\r
+ UINT64 ContextNum : 6;\r
+ UINT64 Resv1 : 50;\r
} EFI_IA32_X64_VALID_BITS;\r
\r
#endif\r
/// Error Status Fields\r
///\r
typedef struct {\r
- UINT64 Resv1:8;\r
- UINT64 Type:8;\r
- UINT64 AddressSignal:1; ///< Error in Address signals or in Address portion of transaction\r
- UINT64 ControlSignal:1; ///< Error in Control signals or in Control portion of transaction\r
- UINT64 DataSignal:1; ///< Error in Data signals or in Data portion of transaction\r
- UINT64 DetectedByResponder:1; ///< Error detected by responder\r
- UINT64 DetectedByRequester:1; ///< Error detected by requestor\r
- UINT64 FirstError:1; ///< First Error in the sequence - option field\r
- UINT64 OverflowNotLogged:1; ///< Additional errors were not logged due to lack of resources\r
- UINT64 Resv2:41;\r
+ UINT64 Resv1 : 8;\r
+ UINT64 Type : 8;\r
+ UINT64 AddressSignal : 1; ///< Error in Address signals or in Address portion of transaction\r
+ UINT64 ControlSignal : 1; ///< Error in Control signals or in Control portion of transaction\r
+ UINT64 DataSignal : 1; ///< Error in Data signals or in Data portion of transaction\r
+ UINT64 DetectedByResponder : 1; ///< Error detected by responder\r
+ UINT64 DetectedByRequester : 1; ///< Error detected by requestor\r
+ UINT64 FirstError : 1; ///< First Error in the sequence - option field\r
+ UINT64 OverflowNotLogged : 1; ///< Additional errors were not logged due to lack of resources\r
+ UINT64 Resv2 : 41;\r
} EFI_GENERIC_ERROR_STATUS;\r
\r
///\r
///\r
/// General Internal errors\r
///\r
- ErrorInternal = 1,\r
- ErrorBus = 16,\r
+ ErrorInternal = 1,\r
+ ErrorBus = 16,\r
///\r
/// Component Internal errors\r
///\r
///\r
/// Bus internal errors\r
///\r
- ErrorVirtualMap = 17,\r
- ErrorAccessInvalid = 18, // Improper access\r
- ErrorUnimplAccess = 19, // Unimplemented memory access\r
- ErrorLossOfLockstep = 20,\r
- ErrorResponseInvalid= 21, // Response not associated with request\r
- ErrorParity = 22,\r
- ErrorProtocol = 23,\r
- ErrorPath = 24, // Detected path error\r
- ErrorTimeout = 25, // Bus timeout\r
- ErrorPoisoned = 26 // Read data poisoned\r
+ ErrorVirtualMap = 17,\r
+ ErrorAccessInvalid = 18, // Improper access\r
+ ErrorUnimplAccess = 19, // Unimplemented memory access\r
+ ErrorLossOfLockstep = 20,\r
+ ErrorResponseInvalid = 21, // Response not associated with request\r
+ ErrorParity = 22,\r
+ ErrorProtocol = 23,\r
+ ErrorPath = 24, // Detected path error\r
+ ErrorTimeout = 25, // Bus timeout\r
+ ErrorPoisoned = 26 // Read data poisoned\r
} EFI_GENERIC_ERROR_STATUS_ERROR_TYPE;\r
\r
///\r
/// Validation bit mask indicates which fields in the memory error record are valid\r
/// in Memory Error section\r
///@{\r
-#define EFI_PLATFORM_MEMORY_ERROR_STATUS_VALID BIT0\r
-#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID BIT1\r
-#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID BIT2\r
-#define EFI_PLATFORM_MEMORY_NODE_VALID BIT3\r
-#define EFI_PLATFORM_MEMORY_CARD_VALID BIT4\r
-#define EFI_PLATFORM_MEMORY_MODULE_VALID BIT5\r
-#define EFI_PLATFORM_MEMORY_BANK_VALID BIT6\r
-#define EFI_PLATFORM_MEMORY_DEVICE_VALID BIT7\r
-#define EFI_PLATFORM_MEMORY_ROW_VALID BIT8\r
-#define EFI_PLATFORM_MEMORY_COLUMN_VALID BIT9\r
-#define EFI_PLATFORM_MEMORY_BIT_POS_VALID BIT10\r
-#define EFI_PLATFORM_MEMORY_REQUESTOR_ID_VALID BIT11\r
-#define EFI_PLATFORM_MEMORY_RESPONDER_ID_VALID BIT12\r
-#define EFI_PLATFORM_MEMORY_TARGET_ID_VALID BIT13\r
-#define EFI_PLATFORM_MEMORY_ERROR_TYPE_VALID BIT14\r
-#define EFI_PLATFORM_MEMORY_ERROR_RANK_NUM_VALID BIT15\r
-#define EFI_PLATFORM_MEMORY_ERROR_CARD_HANDLE_VALID BIT16\r
-#define EFI_PLATFORM_MEMORY_ERROR_MODULE_HANDLE_VALID BIT17\r
-#define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18\r
-#define EFI_PLATFORM_MEMORY_ERROR_BANK_GROUP_VALID BIT19\r
-#define EFI_PLATFORM_MEMORY_ERROR_BANK_ADDRESS_VALID BIT20\r
-#define EFI_PLATFORM_MEMORY_ERROR_CHIP_IDENTIFICATION_VALID BIT21\r
+#define EFI_PLATFORM_MEMORY_ERROR_STATUS_VALID BIT0\r
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID BIT1\r
+#define EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID BIT2\r
+#define EFI_PLATFORM_MEMORY_NODE_VALID BIT3\r
+#define EFI_PLATFORM_MEMORY_CARD_VALID BIT4\r
+#define EFI_PLATFORM_MEMORY_MODULE_VALID BIT5\r
+#define EFI_PLATFORM_MEMORY_BANK_VALID BIT6\r
+#define EFI_PLATFORM_MEMORY_DEVICE_VALID BIT7\r
+#define EFI_PLATFORM_MEMORY_ROW_VALID BIT8\r
+#define EFI_PLATFORM_MEMORY_COLUMN_VALID BIT9\r
+#define EFI_PLATFORM_MEMORY_BIT_POS_VALID BIT10\r
+#define EFI_PLATFORM_MEMORY_REQUESTOR_ID_VALID BIT11\r
+#define EFI_PLATFORM_MEMORY_RESPONDER_ID_VALID BIT12\r
+#define EFI_PLATFORM_MEMORY_TARGET_ID_VALID BIT13\r
+#define EFI_PLATFORM_MEMORY_ERROR_TYPE_VALID BIT14\r
+#define EFI_PLATFORM_MEMORY_ERROR_RANK_NUM_VALID BIT15\r
+#define EFI_PLATFORM_MEMORY_ERROR_CARD_HANDLE_VALID BIT16\r
+#define EFI_PLATFORM_MEMORY_ERROR_MODULE_HANDLE_VALID BIT17\r
+#define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18\r
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_GROUP_VALID BIT19\r
+#define EFI_PLATFORM_MEMORY_ERROR_BANK_ADDRESS_VALID BIT20\r
+#define EFI_PLATFORM_MEMORY_ERROR_CHIP_IDENTIFICATION_VALID BIT21\r
///@}\r
\r
///\r
/// Memory Error Type identifies the type of error that occurred in Memory\r
/// Error section\r
///@{\r
-#define EFI_PLATFORM_MEMORY_ERROR_UNKNOWN 0x00\r
-#define EFI_PLATFORM_MEMORY_ERROR_NONE 0x01\r
-#define EFI_PLATFORM_MEMORY_ERROR_SINGLEBIT_ECC 0x02\r
-#define EFI_PLATFORM_MEMORY_ERROR_MLTIBIT_ECC 0x03\r
-#define EFI_PLATFORM_MEMORY_ERROR_SINGLESYMBOLS_CHIPKILL 0x04\r
-#define EFI_PLATFORM_MEMORY_ERROR_MULTISYMBOL_CHIPKILL 0x05\r
-#define EFI_PLATFORM_MEMORY_ERROR_MATER_ABORT 0x06\r
-#define EFI_PLATFORM_MEMORY_ERROR_TARGET_ABORT 0x07\r
-#define EFI_PLATFORM_MEMORY_ERROR_PARITY 0x08\r
-#define EFI_PLATFORM_MEMORY_ERROR_WDT 0x09\r
-#define EFI_PLATFORM_MEMORY_ERROR_INVALID_ADDRESS 0x0A\r
-#define EFI_PLATFORM_MEMORY_ERROR_MIRROR_FAILED 0x0B\r
-#define EFI_PLATFORM_MEMORY_ERROR_SPARING 0x0C\r
-#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_CORRECTED 0x0D\r
-#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_UNCORRECTED 0x0E\r
-#define EFI_PLATFORM_MEMORY_ERROR_MEMORY_MAP_EVENT 0x0F\r
+#define EFI_PLATFORM_MEMORY_ERROR_UNKNOWN 0x00\r
+#define EFI_PLATFORM_MEMORY_ERROR_NONE 0x01\r
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLEBIT_ECC 0x02\r
+#define EFI_PLATFORM_MEMORY_ERROR_MLTIBIT_ECC 0x03\r
+#define EFI_PLATFORM_MEMORY_ERROR_SINGLESYMBOLS_CHIPKILL 0x04\r
+#define EFI_PLATFORM_MEMORY_ERROR_MULTISYMBOL_CHIPKILL 0x05\r
+#define EFI_PLATFORM_MEMORY_ERROR_MATER_ABORT 0x06\r
+#define EFI_PLATFORM_MEMORY_ERROR_TARGET_ABORT 0x07\r
+#define EFI_PLATFORM_MEMORY_ERROR_PARITY 0x08\r
+#define EFI_PLATFORM_MEMORY_ERROR_WDT 0x09\r
+#define EFI_PLATFORM_MEMORY_ERROR_INVALID_ADDRESS 0x0A\r
+#define EFI_PLATFORM_MEMORY_ERROR_MIRROR_FAILED 0x0B\r
+#define EFI_PLATFORM_MEMORY_ERROR_SPARING 0x0C\r
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_CORRECTED 0x0D\r
+#define EFI_PLATFORM_MEMORY_ERROR_SCRUB_UNCORRECTED 0x0E\r
+#define EFI_PLATFORM_MEMORY_ERROR_MEMORY_MAP_EVENT 0x0F\r
///@}\r
\r
///\r
/// Memory Error Section\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
- UINT64 PhysicalAddress; // Error physical address\r
- UINT64 PhysicalAddressMask; // Grnaularity\r
- UINT16 Node; // Node #\r
- UINT16 Card;\r
- UINT16 ModuleRank; // Module or Rank#\r
- UINT16 Bank;\r
- UINT16 Device;\r
- UINT16 Row;\r
- UINT16 Column;\r
- UINT16 BitPosition;\r
- UINT64 RequestorId;\r
- UINT64 ResponderId;\r
- UINT64 TargetId;\r
- UINT8 ErrorType;\r
- UINT8 Extended;\r
- UINT16 RankNum;\r
- UINT16 CardHandle;\r
- UINT16 ModuleHandle;\r
+ UINT64 ValidFields;\r
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
+ UINT64 PhysicalAddress; // Error physical address\r
+ UINT64 PhysicalAddressMask; // Grnaularity\r
+ UINT16 Node; // Node #\r
+ UINT16 Card;\r
+ UINT16 ModuleRank; // Module or Rank#\r
+ UINT16 Bank;\r
+ UINT16 Device;\r
+ UINT16 Row;\r
+ UINT16 Column;\r
+ UINT16 BitPosition;\r
+ UINT64 RequestorId;\r
+ UINT64 ResponderId;\r
+ UINT64 TargetId;\r
+ UINT8 ErrorType;\r
+ UINT8 Extended;\r
+ UINT16 RankNum;\r
+ UINT16 CardHandle;\r
+ UINT16 ModuleHandle;\r
} EFI_PLATFORM_MEMORY_ERROR_DATA;\r
\r
///\r
/// Validation bit mask indicates which fields in the memory error record 2 are valid\r
/// in Memory Error section 2\r
///@{\r
-#define EFI_PLATFORM_MEMORY2_ERROR_STATUS_VALID BIT0\r
-#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_VALID BIT1\r
-#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_MASK_VALID BIT2\r
-#define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3\r
-#define EFI_PLATFORM_MEMORY2_CARD_VALID BIT4\r
-#define EFI_PLATFORM_MEMORY2_MODULE_VALID BIT5\r
-#define EFI_PLATFORM_MEMORY2_BANK_VALID BIT6\r
-#define EFI_PLATFORM_MEMORY2_DEVICE_VALID BIT7\r
-#define EFI_PLATFORM_MEMORY2_ROW_VALID BIT8\r
-#define EFI_PLATFORM_MEMORY2_COLUMN_VALID BIT9\r
-#define EFI_PLATFORM_MEMORY2_RANK_VALID BIT10\r
-#define EFI_PLATFORM_MEMORY2_BIT_POS_VALID BIT11\r
-#define EFI_PLATFORM_MEMORY2_CHIP_ID_VALID BIT12\r
-#define EFI_PLATFORM_MEMORY2_MEMORY_ERROR_TYPE_VALID BIT13\r
-#define EFI_PLATFORM_MEMORY2_STATUS_VALID BIT14\r
-#define EFI_PLATFORM_MEMORY2_REQUESTOR_ID_VALID BIT15\r
-#define EFI_PLATFORM_MEMORY2_RESPONDER_ID_VALID BIT16\r
-#define EFI_PLATFORM_MEMORY2_TARGET_ID_VALID BIT17\r
-#define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID BIT18\r
-#define EFI_PLATFORM_MEMORY2_MODULE_HANDLE_VALID BIT19\r
-#define EFI_PLATFORM_MEMORY2_BANK_GROUP_VALID BIT20\r
-#define EFI_PLATFORM_MEMORY2_BANK_ADDRESS_VALID BIT21\r
+#define EFI_PLATFORM_MEMORY2_ERROR_STATUS_VALID BIT0\r
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_VALID BIT1\r
+#define EFI_PLATFORM_MEMORY2_PHY_ADDRESS_MASK_VALID BIT2\r
+#define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3\r
+#define EFI_PLATFORM_MEMORY2_CARD_VALID BIT4\r
+#define EFI_PLATFORM_MEMORY2_MODULE_VALID BIT5\r
+#define EFI_PLATFORM_MEMORY2_BANK_VALID BIT6\r
+#define EFI_PLATFORM_MEMORY2_DEVICE_VALID BIT7\r
+#define EFI_PLATFORM_MEMORY2_ROW_VALID BIT8\r
+#define EFI_PLATFORM_MEMORY2_COLUMN_VALID BIT9\r
+#define EFI_PLATFORM_MEMORY2_RANK_VALID BIT10\r
+#define EFI_PLATFORM_MEMORY2_BIT_POS_VALID BIT11\r
+#define EFI_PLATFORM_MEMORY2_CHIP_ID_VALID BIT12\r
+#define EFI_PLATFORM_MEMORY2_MEMORY_ERROR_TYPE_VALID BIT13\r
+#define EFI_PLATFORM_MEMORY2_STATUS_VALID BIT14\r
+#define EFI_PLATFORM_MEMORY2_REQUESTOR_ID_VALID BIT15\r
+#define EFI_PLATFORM_MEMORY2_RESPONDER_ID_VALID BIT16\r
+#define EFI_PLATFORM_MEMORY2_TARGET_ID_VALID BIT17\r
+#define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID BIT18\r
+#define EFI_PLATFORM_MEMORY2_MODULE_HANDLE_VALID BIT19\r
+#define EFI_PLATFORM_MEMORY2_BANK_GROUP_VALID BIT20\r
+#define EFI_PLATFORM_MEMORY2_BANK_ADDRESS_VALID BIT21\r
///@}\r
\r
///\r
/// Memory Error Type identifies the type of error that occurred in Memory\r
/// Error section 2\r
///@{\r
-#define EFI_PLATFORM_MEMORY2_ERROR_UNKNOWN 0x00\r
-#define EFI_PLATFORM_MEMORY2_ERROR_NONE 0x01\r
-#define EFI_PLATFORM_MEMORY2_ERROR_SINGLEBIT_ECC 0x02\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MLTIBIT_ECC 0x03\r
-#define EFI_PLATFORM_MEMORY2_ERROR_SINGLESYMBOL_CHIPKILL 0x04\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MULTISYMBOL_CHIPKILL 0x05\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MASTER_ABORT 0x06\r
-#define EFI_PLATFORM_MEMORY2_ERROR_TARGET_ABORT 0x07\r
-#define EFI_PLATFORM_MEMORY2_ERROR_PARITY 0x08\r
-#define EFI_PLATFORM_MEMORY2_ERROR_WDT 0x09\r
-#define EFI_PLATFORM_MEMORY2_ERROR_INVALID_ADDRESS 0x0A\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MIRROR_BROKEN 0x0B\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_SPARING 0x0C\r
-#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_CORRECTED 0x0D\r
-#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_UNCORRECTED 0x0E\r
-#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_MAP_EVENT 0x0F\r
+#define EFI_PLATFORM_MEMORY2_ERROR_UNKNOWN 0x00\r
+#define EFI_PLATFORM_MEMORY2_ERROR_NONE 0x01\r
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLEBIT_ECC 0x02\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MLTIBIT_ECC 0x03\r
+#define EFI_PLATFORM_MEMORY2_ERROR_SINGLESYMBOL_CHIPKILL 0x04\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MULTISYMBOL_CHIPKILL 0x05\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MASTER_ABORT 0x06\r
+#define EFI_PLATFORM_MEMORY2_ERROR_TARGET_ABORT 0x07\r
+#define EFI_PLATFORM_MEMORY2_ERROR_PARITY 0x08\r
+#define EFI_PLATFORM_MEMORY2_ERROR_WDT 0x09\r
+#define EFI_PLATFORM_MEMORY2_ERROR_INVALID_ADDRESS 0x0A\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MIRROR_BROKEN 0x0B\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_SPARING 0x0C\r
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_CORRECTED 0x0D\r
+#define EFI_PLATFORM_MEMORY2_ERROR_SCRUB_UNCORRECTED 0x0E\r
+#define EFI_PLATFORM_MEMORY2_ERROR_MEMORY_MAP_EVENT 0x0F\r
///@}\r
\r
///\r
/// Memory Error Section 2\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
- UINT64 PhysicalAddress; // Error physical address\r
- UINT64 PhysicalAddressMask; // Grnaularity\r
- UINT16 Node; // Node #\r
- UINT16 Card;\r
- UINT16 Module; // Module or Rank#\r
- UINT16 Bank;\r
- UINT32 Device;\r
- UINT32 Row;\r
- UINT32 Column;\r
- UINT32 Rank;\r
- UINT32 BitPosition;\r
- UINT8 ChipId;\r
- UINT8 MemErrorType;\r
- UINT8 Status;\r
- UINT8 Reserved;\r
- UINT64 RequestorId;\r
- UINT64 ResponderId;\r
- UINT64 TargetId;\r
- UINT32 CardHandle;\r
- UINT32 ModuleHandle;\r
+ UINT64 ValidFields;\r
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
+ UINT64 PhysicalAddress; // Error physical address\r
+ UINT64 PhysicalAddressMask; // Grnaularity\r
+ UINT16 Node; // Node #\r
+ UINT16 Card;\r
+ UINT16 Module; // Module or Rank#\r
+ UINT16 Bank;\r
+ UINT32 Device;\r
+ UINT32 Row;\r
+ UINT32 Column;\r
+ UINT32 Rank;\r
+ UINT32 BitPosition;\r
+ UINT8 ChipId;\r
+ UINT8 MemErrorType;\r
+ UINT8 Status;\r
+ UINT8 Reserved;\r
+ UINT64 RequestorId;\r
+ UINT64 ResponderId;\r
+ UINT64 TargetId;\r
+ UINT32 CardHandle;\r
+ UINT32 ModuleHandle;\r
} EFI_PLATFORM_MEMORY2_ERROR_DATA;\r
\r
///\r
/// Validation bits mask indicates which of the following fields is valid\r
/// in PCI Express Error Record.\r
///@{\r
-#define EFI_PCIE_ERROR_PORT_TYPE_VALID BIT0\r
-#define EFI_PCIE_ERROR_VERSION_VALID BIT1\r
-#define EFI_PCIE_ERROR_COMMAND_STATUS_VALID BIT2\r
-#define EFI_PCIE_ERROR_DEVICE_ID_VALID BIT3\r
-#define EFI_PCIE_ERROR_SERIAL_NO_VALID BIT4\r
-#define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID BIT5\r
-#define EFI_PCIE_ERROR_CAPABILITY_INFO_VALID BIT6\r
-#define EFI_PCIE_ERROR_AER_INFO_VALID BIT7\r
+#define EFI_PCIE_ERROR_PORT_TYPE_VALID BIT0\r
+#define EFI_PCIE_ERROR_VERSION_VALID BIT1\r
+#define EFI_PCIE_ERROR_COMMAND_STATUS_VALID BIT2\r
+#define EFI_PCIE_ERROR_DEVICE_ID_VALID BIT3\r
+#define EFI_PCIE_ERROR_SERIAL_NO_VALID BIT4\r
+#define EFI_PCIE_ERROR_BRIDGE_CRL_STS_VALID BIT5\r
+#define EFI_PCIE_ERROR_CAPABILITY_INFO_VALID BIT6\r
+#define EFI_PCIE_ERROR_AER_INFO_VALID BIT7\r
///@}\r
\r
///\r
/// PCIe Device/Port Type as defined in the PCI Express capabilities register\r
///@{\r
-#define EFI_PCIE_ERROR_PORT_PCIE_ENDPOINT 0x00000000\r
-#define EFI_PCIE_ERROR_PORT_PCI_ENDPOINT 0x00000001\r
-#define EFI_PCIE_ERROR_PORT_ROOT_PORT 0x00000004\r
-#define EFI_PCIE_ERROR_PORT_UPSWITCH_PORT 0x00000005\r
-#define EFI_PCIE_ERROR_PORT_DOWNSWITCH_PORT 0x00000006\r
-#define EFI_PCIE_ERROR_PORT_PCIE_TO_PCI_BRIDGE 0x00000007\r
-#define EFI_PCIE_ERROR_PORT_PCI_TO_PCIE_BRIDGE 0x00000008\r
-#define EFI_PCIE_ERROR_PORT_ROOT_INT_ENDPOINT 0x00000009\r
-#define EFI_PCIE_ERROR_PORT_ROOT_EVENT_COLLECTOR 0x0000000A\r
+#define EFI_PCIE_ERROR_PORT_PCIE_ENDPOINT 0x00000000\r
+#define EFI_PCIE_ERROR_PORT_PCI_ENDPOINT 0x00000001\r
+#define EFI_PCIE_ERROR_PORT_ROOT_PORT 0x00000004\r
+#define EFI_PCIE_ERROR_PORT_UPSWITCH_PORT 0x00000005\r
+#define EFI_PCIE_ERROR_PORT_DOWNSWITCH_PORT 0x00000006\r
+#define EFI_PCIE_ERROR_PORT_PCIE_TO_PCI_BRIDGE 0x00000007\r
+#define EFI_PCIE_ERROR_PORT_PCI_TO_PCIE_BRIDGE 0x00000008\r
+#define EFI_PCIE_ERROR_PORT_ROOT_INT_ENDPOINT 0x00000009\r
+#define EFI_PCIE_ERROR_PORT_ROOT_EVENT_COLLECTOR 0x0000000A\r
///@}\r
\r
///\r
/// PCI Slot number\r
///\r
typedef struct {\r
- UINT16 Resv1:3;\r
- UINT16 Number:13;\r
+ UINT16 Resv1 : 3;\r
+ UINT16 Number : 13;\r
} EFI_GENERIC_ERROR_PCI_SLOT;\r
\r
///\r
/// bridge. Default values for both the bus numbers is zero.\r
///\r
typedef struct {\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT8 ClassCode[3];\r
- UINT8 Function;\r
- UINT8 Device;\r
- UINT16 Segment;\r
- UINT8 PrimaryOrDeviceBus;\r
- UINT8 SecondaryBus;\r
- EFI_GENERIC_ERROR_PCI_SLOT Slot;\r
- UINT8 Resv1;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT8 ClassCode[3];\r
+ UINT8 Function;\r
+ UINT8 Device;\r
+ UINT16 Segment;\r
+ UINT8 PrimaryOrDeviceBus;\r
+ UINT8 SecondaryBus;\r
+ EFI_GENERIC_ERROR_PCI_SLOT Slot;\r
+ UINT8 Resv1;\r
} EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID;\r
\r
///\r
/// PCIe Capability Structure\r
///\r
typedef struct {\r
- UINT8 PcieCap[60];\r
+ UINT8 PcieCap[60];\r
} EFI_PCIE_ERROR_DATA_CAPABILITY;\r
\r
///\r
/// PCIe Advanced Error Reporting Extended Capability Structure.\r
///\r
typedef struct {\r
- UINT8 PcieAer[96];\r
+ UINT8 PcieAer[96];\r
} EFI_PCIE_ERROR_DATA_AER;\r
\r
///\r
/// PCI Express Error Record\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- UINT32 PortType;\r
- UINT32 Version;\r
- UINT32 CommandStatus;\r
- UINT32 Resv2;\r
- EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID DevBridge;\r
- UINT64 SerialNo;\r
- UINT32 BridgeControlStatus;\r
- EFI_PCIE_ERROR_DATA_CAPABILITY Capability;\r
- EFI_PCIE_ERROR_DATA_AER AerInfo;\r
+ UINT64 ValidFields;\r
+ UINT32 PortType;\r
+ UINT32 Version;\r
+ UINT32 CommandStatus;\r
+ UINT32 Resv2;\r
+ EFI_GENERIC_ERROR_PCIE_DEV_BRIDGE_ID DevBridge;\r
+ UINT64 SerialNo;\r
+ UINT32 BridgeControlStatus;\r
+ EFI_PCIE_ERROR_DATA_CAPABILITY Capability;\r
+ EFI_PCIE_ERROR_DATA_AER AerInfo;\r
} EFI_PCIE_ERROR_DATA;\r
\r
///\r
/// Validation bits Indicates which of the following fields is valid\r
/// in PCI/PCI-X Bus Error Section.\r
///@{\r
-#define EFI_PCI_PCIX_BUS_ERROR_STATUS_VALID BIT0\r
-#define EFI_PCI_PCIX_BUS_ERROR_TYPE_VALID BIT1\r
-#define EFI_PCI_PCIX_BUS_ERROR_BUS_ID_VALID BIT2\r
-#define EFI_PCI_PCIX_BUS_ERROR_BUS_ADDRESS_VALID BIT3\r
-#define EFI_PCI_PCIX_BUS_ERROR_BUS_DATA_VALID BIT4\r
-#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID BIT5\r
-#define EFI_PCI_PCIX_BUS_ERROR_REQUESTOR_ID_VALID BIT6\r
-#define EFI_PCI_PCIX_BUS_ERROR_COMPLETER_ID_VALID BIT7\r
-#define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID BIT8\r
+#define EFI_PCI_PCIX_BUS_ERROR_STATUS_VALID BIT0\r
+#define EFI_PCI_PCIX_BUS_ERROR_TYPE_VALID BIT1\r
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ID_VALID BIT2\r
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_ADDRESS_VALID BIT3\r
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_DATA_VALID BIT4\r
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_VALID BIT5\r
+#define EFI_PCI_PCIX_BUS_ERROR_REQUESTOR_ID_VALID BIT6\r
+#define EFI_PCI_PCIX_BUS_ERROR_COMPLETER_ID_VALID BIT7\r
+#define EFI_PCI_PCIX_BUS_ERROR_TARGET_ID_VALID BIT8\r
///@}\r
\r
///\r
/// PCI Bus Error Type in PCI/PCI-X Bus Error Section\r
///@{\r
-#define EFI_PCI_PCIX_BUS_ERROR_UNKNOWN 0x0000\r
-#define EFI_PCI_PCIX_BUS_ERROR_DATA_PARITY 0x0001\r
-#define EFI_PCI_PCIX_BUS_ERROR_SYSTEM 0x0002\r
-#define EFI_PCI_PCIX_BUS_ERROR_MASTER_ABORT 0x0003\r
-#define EFI_PCI_PCIX_BUS_ERROR_BUS_TIMEOUT 0x0004\r
-#define EFI_PCI_PCIX_BUS_ERROR_MASTER_DATA_PARITY 0x0005\r
-#define EFI_PCI_PCIX_BUS_ERROR_ADDRESS_PARITY 0x0006\r
-#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_PARITY 0x0007\r
+#define EFI_PCI_PCIX_BUS_ERROR_UNKNOWN 0x0000\r
+#define EFI_PCI_PCIX_BUS_ERROR_DATA_PARITY 0x0001\r
+#define EFI_PCI_PCIX_BUS_ERROR_SYSTEM 0x0002\r
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_ABORT 0x0003\r
+#define EFI_PCI_PCIX_BUS_ERROR_BUS_TIMEOUT 0x0004\r
+#define EFI_PCI_PCIX_BUS_ERROR_MASTER_DATA_PARITY 0x0005\r
+#define EFI_PCI_PCIX_BUS_ERROR_ADDRESS_PARITY 0x0006\r
+#define EFI_PCI_PCIX_BUS_ERROR_COMMAND_PARITY 0x0007\r
///@}\r
\r
///\r
/// PCI/PCI-X Bus Error Section\r
///\r
typedef struct {\r
- UINT64 ValidFields;\r
- EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
- UINT16 Type;\r
- UINT16 BusId;\r
- UINT32 Resv2;\r
- UINT64 BusAddress;\r
- UINT64 BusData;\r
- UINT64 BusCommand;\r
- UINT64 RequestorId;\r
- UINT64 ResponderId;\r
- UINT64 TargetId;\r
+ UINT64 ValidFields;\r
+ EFI_GENERIC_ERROR_STATUS ErrorStatus;\r
+ UINT16 Type;\r
+ UINT16 BusId;\r
+ UINT32 Resv2;\r
+ UINT64 BusAddress;\r
+ UINT64 BusData;\r
+ UINT64 BusCommand;\r
+ UINT64 RequestorId;\r
+ UINT64 ResponderId;\r
+ UINT64 TargetId;\r
} EFI_PCI_PCIX_BUS_ERROR_DATA;\r
\r
///\r
/// Validation bits Indicates which of the following fields is valid\r
/// in PCI/PCI-X Component Error Section.\r
///@{\r
-#define EFI_PCI_PCIX_DEVICE_ERROR_STATUS_VALID BIT0\r
-#define EFI_PCI_PCIX_DEVICE_ERROR_ID_INFO_VALID BIT1\r
-#define EFI_PCI_PCIX_DEVICE_ERROR_MEM_NUM_VALID BIT2\r
-#define EFI_PCI_PCIX_DEVICE_ERROR_IO_NUM_VALID BIT3\r
-#define EFI_PCI_PCIX_DEVICE_ERROR_REG_DATA_PAIR_VALID BIT4\r
+#define EFI_PCI_PCIX_DEVICE_ERROR_STATUS_VALID BIT0\r
+#define EFI_PCI_PCIX_DEVICE_ERROR_ID_INFO_VALID BIT1\r
+#define EFI_PCI_PCIX_DEVICE_ERROR_MEM_NUM_VALID BIT2\r
+#define EFI_PCI_PCIX_DEVICE_ERROR_IO_NUM_VALID BIT3\r
+#define EFI_PCI_PCIX_DEVICE_ERROR_REG_DATA_PAIR_VALID BIT4\r
///@}\r
\r
///\r
/// PCI/PCI-X Device Identification Information\r
///\r
typedef struct {\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT8 ClassCode[3];\r
- UINT8 Function;\r
- UINT8 Device;\r
- UINT8 Bus;\r
- UINT8 Segment;\r
- UINT8 Resv1;\r
- UINT32 Resv2;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT8 ClassCode[3];\r
+ UINT8 Function;\r
+ UINT8 Device;\r
+ UINT8 Bus;\r
+ UINT8 Segment;\r
+ UINT8 Resv1;\r
+ UINT32 Resv2;\r
} EFI_GENERIC_ERROR_PCI_DEVICE_ID;\r
\r
///\r
/// Identifies the type of firmware error record\r
///@{\r
-#define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL 0x00\r
-#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1 0x01\r
-#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2 0x02\r
+#define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL 0x00\r
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1 0x01\r
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2 0x02\r
///@}\r
\r
///\r
///\r
/// Fault Reason in DMAr Generic Error Section\r
///@{\r
-#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_NOT_PRESENT 0x01\r
-#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_INVALID 0x02\r
-#define EFI_DMA_FAULT_REASON_ACCESS_MAPPING_TABLE_ERROR 0x03\r
-#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_MAPPING_TABLE 0x04\r
-#define EFI_DMA_FAULT_REASON_ACCESS_ADDR_OUT_OF_SPACE 0x05\r
-#define EFI_DMA_FAULT_REASON_INVALID_ACCESS 0x06\r
-#define EFI_DMA_FAULT_REASON_INVALID_REQUEST 0x07\r
-#define EFI_DMA_FAULT_REASON_ACCESS_TRANSLATE_TABLE_ERROR 0x08\r
-#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_TRANSLATE_TABLE 0x09\r
-#define EFI_DMA_FAULT_REASON_INVALID_COMMAOND 0x0A\r
-#define EFI_DMA_FAULT_REASON_ACCESS_COMMAND_BUFFER_ERROR 0x0B\r
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_NOT_PRESENT 0x01\r
+#define EFI_DMA_FAULT_REASON_TABLE_ENTRY_INVALID 0x02\r
+#define EFI_DMA_FAULT_REASON_ACCESS_MAPPING_TABLE_ERROR 0x03\r
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_MAPPING_TABLE 0x04\r
+#define EFI_DMA_FAULT_REASON_ACCESS_ADDR_OUT_OF_SPACE 0x05\r
+#define EFI_DMA_FAULT_REASON_INVALID_ACCESS 0x06\r
+#define EFI_DMA_FAULT_REASON_INVALID_REQUEST 0x07\r
+#define EFI_DMA_FAULT_REASON_ACCESS_TRANSLATE_TABLE_ERROR 0x08\r
+#define EFI_DMA_FAULT_REASON_RESV_BIT_ERROR_IN_TRANSLATE_TABLE 0x09\r
+#define EFI_DMA_FAULT_REASON_INVALID_COMMAOND 0x0A\r
+#define EFI_DMA_FAULT_REASON_ACCESS_COMMAND_BUFFER_ERROR 0x0B\r
///@}\r
\r
///\r
/// DMA access type in DMAr Generic Error Section\r
///@{\r
-#define EFI_DMA_ACCESS_TYPE_READ 0x00\r
-#define EFI_DMA_ACCESS_TYPE_WRITE 0x01\r
+#define EFI_DMA_ACCESS_TYPE_READ 0x00\r
+#define EFI_DMA_ACCESS_TYPE_WRITE 0x01\r
///@}\r
\r
///\r
/// DMA address type in DMAr Generic Error Section\r
///@{\r
-#define EFI_DMA_ADDRESS_UNTRANSLATED 0x00\r
-#define EFI_DMA_ADDRESS_TRANSLATION 0x01\r
+#define EFI_DMA_ADDRESS_UNTRANSLATED 0x00\r
+#define EFI_DMA_ADDRESS_TRANSLATION 0x01\r
///@}\r
\r
///\r
/// Architecture type in DMAr Generic Error Section\r
///@{\r
-#define EFI_DMA_ARCH_TYPE_VT 0x01\r
-#define EFI_DMA_ARCH_TYPE_IOMMU 0x02\r
+#define EFI_DMA_ARCH_TYPE_VT 0x01\r
+#define EFI_DMA_ARCH_TYPE_IOMMU 0x02\r
///@}\r
\r
///\r
/// DMAr Generic Error Section\r
///\r
typedef struct {\r
- UINT16 RequesterId;\r
- UINT16 SegmentNumber;\r
- UINT8 FaultReason;\r
- UINT8 AccessType;\r
- UINT8 AddressType;\r
- UINT8 ArchType;\r
- UINT64 DeviceAddr;\r
- UINT8 Resv1[16];\r
+ UINT16 RequesterId;\r
+ UINT16 SegmentNumber;\r
+ UINT8 FaultReason;\r
+ UINT8 AccessType;\r
+ UINT8 AddressType;\r
+ UINT8 ArchType;\r
+ UINT64 DeviceAddr;\r
+ UINT8 Resv1[16];\r
} EFI_DMAR_GENERIC_ERROR_DATA;\r
\r
///\r
/// Intel VT for Directed I/O specific DMAr Errors\r
///\r
typedef struct {\r
- UINT8 Version;\r
- UINT8 Revision;\r
- UINT8 OemId[6];\r
- UINT64 Capability;\r
- UINT64 CapabilityEx;\r
- UINT32 GlobalCommand;\r
- UINT32 GlobalStatus;\r
- UINT32 FaultStatus;\r
- UINT8 Resv1[12];\r
- UINT64 FaultRecord[2];\r
- UINT64 RootEntry[2];\r
- UINT64 ContextEntry[2];\r
- UINT64 PteL6;\r
- UINT64 PteL5;\r
- UINT64 PteL4;\r
- UINT64 PteL3;\r
- UINT64 PteL2;\r
- UINT64 PteL1;\r
+ UINT8 Version;\r
+ UINT8 Revision;\r
+ UINT8 OemId[6];\r
+ UINT64 Capability;\r
+ UINT64 CapabilityEx;\r
+ UINT32 GlobalCommand;\r
+ UINT32 GlobalStatus;\r
+ UINT32 FaultStatus;\r
+ UINT8 Resv1[12];\r
+ UINT64 FaultRecord[2];\r
+ UINT64 RootEntry[2];\r
+ UINT64 ContextEntry[2];\r
+ UINT64 PteL6;\r
+ UINT64 PteL5;\r
+ UINT64 PteL4;\r
+ UINT64 PteL3;\r
+ UINT64 PteL2;\r
+ UINT64 PteL1;\r
} EFI_DIRECTED_IO_DMAR_ERROR_DATA;\r
\r
///\r
/// IOMMU specific DMAr Errors\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Resv1[7];\r
- UINT64 Control;\r
- UINT64 Status;\r
- UINT8 Resv2[8];\r
- UINT64 EventLogEntry[2];\r
- UINT8 Resv3[16];\r
- UINT64 DeviceTableEntry[4];\r
- UINT64 PteL6;\r
- UINT64 PteL5;\r
- UINT64 PteL4;\r
- UINT64 PteL3;\r
- UINT64 PteL2;\r
- UINT64 PteL1;\r
+ UINT8 Revision;\r
+ UINT8 Resv1[7];\r
+ UINT64 Control;\r
+ UINT64 Status;\r
+ UINT8 Resv2[8];\r
+ UINT64 EventLogEntry[2];\r
+ UINT8 Resv3[16];\r
+ UINT64 DeviceTableEntry[4];\r
+ UINT64 PteL6;\r
+ UINT64 PteL5;\r
+ UINT64 PteL4;\r
+ UINT64 PteL3;\r
+ UINT64 PteL2;\r
+ UINT64 PteL1;\r
} EFI_IOMMU_DMAR_ERROR_DATA;\r
\r
#pragma pack()\r
\r
-extern EFI_GUID gEfiEventNotificationTypeCmcGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeCpeGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeMceGuid;\r
-extern EFI_GUID gEfiEventNotificationTypePcieGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeInitGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeNmiGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeBootGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeDmarGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeSeaGuid;\r
-extern EFI_GUID gEfiEventNotificationTypeSeiGuid;\r
-extern EFI_GUID gEfiEventNotificationTypePeiGuid;\r
-\r
-extern EFI_GUID gEfiProcessorGenericErrorSectionGuid;\r
-extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid;\r
-extern EFI_GUID gEfiIa32X64ProcessorErrorSectionGuid;\r
-extern EFI_GUID gEfiArmProcessorErrorSectionGuid ;\r
-extern EFI_GUID gEfiPlatformMemoryErrorSectionGuid;\r
-extern EFI_GUID gEfiPlatformMemory2ErrorSectionGuid;\r
-extern EFI_GUID gEfiPcieErrorSectionGuid;\r
-extern EFI_GUID gEfiFirmwareErrorSectionGuid;\r
-extern EFI_GUID gEfiPciBusErrorSectionGuid;\r
-extern EFI_GUID gEfiPciDevErrorSectionGuid;\r
-extern EFI_GUID gEfiDMArGenericErrorSectionGuid;\r
-extern EFI_GUID gEfiDirectedIoDMArErrorSectionGuid;\r
-extern EFI_GUID gEfiIommuDMArErrorSectionGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeCmcGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeCpeGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeMceGuid;\r
+extern EFI_GUID gEfiEventNotificationTypePcieGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeInitGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeNmiGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeBootGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeDmarGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeSeaGuid;\r
+extern EFI_GUID gEfiEventNotificationTypeSeiGuid;\r
+extern EFI_GUID gEfiEventNotificationTypePeiGuid;\r
+\r
+extern EFI_GUID gEfiProcessorGenericErrorSectionGuid;\r
+extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid;\r
+extern EFI_GUID gEfiIa32X64ProcessorErrorSectionGuid;\r
+extern EFI_GUID gEfiArmProcessorErrorSectionGuid;\r
+extern EFI_GUID gEfiPlatformMemoryErrorSectionGuid;\r
+extern EFI_GUID gEfiPlatformMemory2ErrorSectionGuid;\r
+extern EFI_GUID gEfiPcieErrorSectionGuid;\r
+extern EFI_GUID gEfiFirmwareErrorSectionGuid;\r
+extern EFI_GUID gEfiPciBusErrorSectionGuid;\r
+extern EFI_GUID gEfiPciDevErrorSectionGuid;\r
+extern EFI_GUID gEfiDMArGenericErrorSectionGuid;\r
+extern EFI_GUID gEfiDirectedIoDMArErrorSectionGuid;\r
+extern EFI_GUID gEfiIommuDMArErrorSectionGuid;\r
\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
/// IA32 and x64 Specific definitions.\r
///\r
\r
-extern EFI_GUID gEfiIa32X64ErrorTypeCacheCheckGuid;\r
-extern EFI_GUID gEfiIa32X64ErrorTypeTlbCheckGuid;\r
-extern EFI_GUID gEfiIa32X64ErrorTypeBusCheckGuid;\r
-extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid;\r
+extern EFI_GUID gEfiIa32X64ErrorTypeCacheCheckGuid;\r
+extern EFI_GUID gEfiIa32X64ErrorTypeTlbCheckGuid;\r
+extern EFI_GUID gEfiIa32X64ErrorTypeBusCheckGuid;\r
+extern EFI_GUID gEfiIa32X64ErrorTypeMsCheckGuid;\r
\r
#endif\r
\r
0x49152e77, 0x1ada, 0x4764, {0xb7, 0xa2, 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b } \\r
}\r
\r
-#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01\r
-#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02\r
+#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01\r
+#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02\r
\r
-#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01\r
+#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01\r
\r
typedef struct {\r
- UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE\r
- EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table.\r
- UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.\r
+ UINT64 Signature; ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE\r
+ EFI_PHYSICAL_ADDRESS EfiSystemTableBase; ///< The physical address of the EFI system table.\r
+ UINT32 Crc32; ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.\r
} EFI_SYSTEM_TABLE_POINTER;\r
\r
typedef struct {\r
/// Indicates the type of image info structure. For PE32 EFI images,\r
/// this is set to EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL.\r
///\r
- UINT32 ImageInfoType;\r
+ UINT32 ImageInfoType;\r
///\r
/// A pointer to an instance of the loaded image protocol for the associated image.\r
///\r
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImageProtocolInstance;\r
///\r
/// Indicates the image handle of the associated image.\r
///\r
- EFI_HANDLE ImageHandle;\r
+ EFI_HANDLE ImageHandle;\r
} EFI_DEBUG_IMAGE_INFO_NORMAL;\r
\r
typedef union {\r
- UINT32 *ImageInfoType;\r
- EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;\r
+ UINT32 *ImageInfoType;\r
+ EFI_DEBUG_IMAGE_INFO_NORMAL *NormalImage;\r
} EFI_DEBUG_IMAGE_INFO;\r
\r
typedef struct {\r
///\r
/// UpdateStatus is used by the system to indicate the state of the debug image info table.\r
///\r
- volatile UINT32 UpdateStatus;\r
+ volatile UINT32 UpdateStatus;\r
///\r
/// The number of EFI_DEBUG_IMAGE_INFO elements in the array pointed to by EfiDebugImageInfoTable.\r
///\r
- UINT32 TableSize;\r
+ UINT32 TableSize;\r
///\r
/// A pointer to the first element of an array of EFI_DEBUG_IMAGE_INFO structures.\r
///\r
- EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;\r
+ EFI_DEBUG_IMAGE_INFO *EfiDebugImageInfoTable;\r
} EFI_DEBUG_IMAGE_INFO_TABLE_HEADER;\r
\r
-extern EFI_GUID gEfiDebugImageInfoTableGuid;\r
+extern EFI_GUID gEfiDebugImageInfoTableGuid;\r
\r
#endif\r
0x5ad34ba, 0x6f02, 0x4214, {0x95, 0x2e, 0x4d, 0xa0, 0x39, 0x8e, 0x2b, 0xb9 } \\r
}\r
\r
-extern EFI_GUID gEfiDxeServicesTableGuid;\r
+extern EFI_GUID gEfiDxeServicesTableGuid;\r
\r
#endif\r
#ifndef __EVENT_GROUP_GUID__\r
#define __EVENT_GROUP_GUID__\r
\r
-\r
#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \\r
{ 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }\r
\r
-extern EFI_GUID gEfiEventExitBootServicesGuid;\r
-\r
+extern EFI_GUID gEfiEventExitBootServicesGuid;\r
\r
#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \\r
{ 0x13fa7698, 0xc831, 0x49c7, { 0x87, 0xea, 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96 } }\r
\r
-extern EFI_GUID gEfiEventVirtualAddressChangeGuid;\r
-\r
+extern EFI_GUID gEfiEventVirtualAddressChangeGuid;\r
\r
#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \\r
{ 0x78bee926, 0x692f, 0x48fd, { 0x9e, 0xdb, 0x1, 0x42, 0x2e, 0xf0, 0xd7, 0xab } }\r
\r
-extern EFI_GUID gEfiEventMemoryMapChangeGuid;\r
-\r
+extern EFI_GUID gEfiEventMemoryMapChangeGuid;\r
\r
#define EFI_EVENT_GROUP_READY_TO_BOOT \\r
{ 0x7ce88fb3, 0x4bd7, 0x4679, { 0x87, 0xa8, 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b } }\r
\r
-extern EFI_GUID gEfiEventReadyToBootGuid;\r
+extern EFI_GUID gEfiEventReadyToBootGuid;\r
\r
#define EFI_EVENT_GROUP_DXE_DISPATCH_GUID \\r
{ 0x7081e22f, 0xcac6, 0x4053, { 0x94, 0x68, 0x67, 0x57, 0x82, 0xcf, 0x88, 0xe5 }}\r
\r
-extern EFI_GUID gEfiEventDxeDispatchGuid;\r
+extern EFI_GUID gEfiEventDxeDispatchGuid;\r
\r
#define EFI_END_OF_DXE_EVENT_GROUP_GUID \\r
{ 0x2ce967a, 0xdd7e, 0x4ffc, { 0x9e, 0xe7, 0x81, 0xc, 0xf0, 0x47, 0x8, 0x80 } }\r
\r
-extern EFI_GUID gEfiEndOfDxeEventGroupGuid;\r
+extern EFI_GUID gEfiEndOfDxeEventGroupGuid;\r
\r
#endif\r
#define EFI_EVENT_LEGACY_BOOT_GUID \\r
{ 0x2a571201, 0x4966, 0x47f6, {0x8b, 0x86, 0xf3, 0x1e, 0x41, 0xf3, 0x2f, 0x10 } }\r
\r
-extern EFI_GUID gEfiEventLegacyBootGuid;\r
+extern EFI_GUID gEfiEventLegacyBootGuid;\r
\r
#endif\r
///\r
/// The size of the EFI_FILE_INFO structure, including the Null-terminated FileName string.\r
///\r
- UINT64 Size;\r
+ UINT64 Size;\r
///\r
/// The size of the file in bytes.\r
///\r
- UINT64 FileSize;\r
+ UINT64 FileSize;\r
///\r
/// PhysicalSize The amount of physical space the file consumes on the file system volume.\r
///\r
- UINT64 PhysicalSize;\r
+ UINT64 PhysicalSize;\r
///\r
/// The time the file was created.\r
///\r
- EFI_TIME CreateTime;\r
+ EFI_TIME CreateTime;\r
///\r
/// The time when the file was last accessed.\r
///\r
- EFI_TIME LastAccessTime;\r
+ EFI_TIME LastAccessTime;\r
///\r
/// The time when the file's contents were last modified.\r
///\r
- EFI_TIME ModificationTime;\r
+ EFI_TIME ModificationTime;\r
///\r
/// The attribute bits for the file.\r
///\r
- UINT64 Attribute;\r
+ UINT64 Attribute;\r
///\r
/// The Null-terminated name of the file.\r
///\r
- CHAR16 FileName[1];\r
+ CHAR16 FileName[1];\r
} EFI_FILE_INFO;\r
\r
///\r
/// computes this size correctly no matter how big the FileName array is declared.\r
/// This is required to make the EFI_FILE_INFO data structure ANSI compilant.\r
///\r
-#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName)\r
+#define SIZE_OF_EFI_FILE_INFO OFFSET_OF (EFI_FILE_INFO, FileName)\r
\r
-extern EFI_GUID gEfiFileInfoGuid;\r
+extern EFI_GUID gEfiFileInfoGuid;\r
\r
#endif\r
///\r
/// The size of the EFI_FILE_SYSTEM_INFO structure, including the Null-terminated VolumeLabel string.\r
///\r
- UINT64 Size;\r
+ UINT64 Size;\r
///\r
/// TRUE if the volume only supports read access.\r
///\r
- BOOLEAN ReadOnly;\r
+ BOOLEAN ReadOnly;\r
///\r
/// The number of bytes managed by the file system.\r
///\r
- UINT64 VolumeSize;\r
+ UINT64 VolumeSize;\r
///\r
/// The number of available bytes for use by the file system.\r
///\r
- UINT64 FreeSpace;\r
+ UINT64 FreeSpace;\r
///\r
/// The nominal block size by which files are typically grown.\r
///\r
- UINT32 BlockSize;\r
+ UINT32 BlockSize;\r
///\r
/// The Null-terminated string that is the volume's label.\r
///\r
- CHAR16 VolumeLabel[1];\r
+ CHAR16 VolumeLabel[1];\r
} EFI_FILE_SYSTEM_INFO;\r
\r
///\r
///\r
#define SIZE_OF_EFI_FILE_SYSTEM_INFO OFFSET_OF (EFI_FILE_SYSTEM_INFO, VolumeLabel)\r
\r
-extern EFI_GUID gEfiFileSystemInfoGuid;\r
+extern EFI_GUID gEfiFileSystemInfoGuid;\r
\r
#endif\r
///\r
/// The Null-terminated string that is the volume's label.\r
///\r
- CHAR16 VolumeLabel[1];\r
+ CHAR16 VolumeLabel[1];\r
} EFI_FILE_SYSTEM_VOLUME_LABEL;\r
\r
#define SIZE_OF_EFI_FILE_SYSTEM_VOLUME_LABEL \\r
OFFSET_OF (EFI_FILE_SYSTEM_VOLUME_LABEL, VolumeLabel)\r
\r
-extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid;\r
+extern EFI_GUID gEfiFileSystemVolumeLabelInfoIdGuid;\r
\r
#endif\r
#define EFI_FIRMWARE_CONTENTS_SIGNED_GUID \\r
{ 0xf9d89e8, 0x9259, 0x4f76, {0xa5, 0xaf, 0xc, 0x89, 0xe3, 0x40, 0x23, 0xdf } }\r
\r
-extern EFI_GUID gEfiFirmwareContentsSignedGuid;\r
+extern EFI_GUID gEfiFirmwareContentsSignedGuid;\r
\r
#endif\r
#define EFI_FFS_VOLUME_TOP_FILE_GUID \\r
{ 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }\r
\r
-\r
-extern EFI_GUID gEfiFirmwareFileSystem2Guid;\r
-extern EFI_GUID gEfiFirmwareVolumeTopFileGuid;\r
+extern EFI_GUID gEfiFirmwareFileSystem2Guid;\r
+extern EFI_GUID gEfiFirmwareVolumeTopFileGuid;\r
\r
#endif\r
#define EFI_FIRMWARE_FILE_SYSTEM3_GUID \\r
{ 0x5473c07a, 0x3dcb, 0x4dca, { 0xbd, 0x6f, 0x1e, 0x96, 0x89, 0xe7, 0x34, 0x9a }}\r
\r
-extern EFI_GUID gEfiFirmwareFileSystem3Guid;\r
+extern EFI_GUID gEfiFirmwareFileSystem3Guid;\r
\r
#endif // __FIRMWARE_FILE_SYSTEM3_GUID_H__\r
\r
**/\r
\r
-\r
#ifndef _FMP_CAPSULE_GUID_H__\r
#define _FMP_CAPSULE_GUID_H__\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT32 Version;\r
+ UINT32 Version;\r
\r
///\r
/// The number of drivers included in the capsule and the number of corresponding\r
/// offsets stored in ItemOffsetList array.\r
///\r
- UINT16 EmbeddedDriverCount;\r
+ UINT16 EmbeddedDriverCount;\r
\r
///\r
/// The number of payload items included in the capsule and the number of\r
/// corresponding offsets stored in the ItemOffsetList array.\r
///\r
- UINT16 PayloadItemCount;\r
+ UINT16 PayloadItemCount;\r
\r
///\r
/// Variable length array of dimension [EmbeddedDriverCount + PayloadItemCount]\r
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER;\r
\r
typedef struct {\r
- UINT32 Version;\r
+ UINT32 Version;\r
\r
///\r
/// Used to identify device firmware targeted by this update. This guid is matched by\r
/// system firmware against ImageTypeId field within a EFI_FIRMWARE_IMAGE_DESCRIPTOR\r
///\r
- EFI_GUID UpdateImageTypeId;\r
+ EFI_GUID UpdateImageTypeId;\r
\r
///\r
/// Passed as ImageIndex in call to EFI_FIRMWARE_MANAGEMENT_PROTOCOL.SetImage()\r
///\r
- UINT8 UpdateImageIndex;\r
- UINT8 reserved_bytes[3];\r
+ UINT8 UpdateImageIndex;\r
+ UINT8 reserved_bytes[3];\r
\r
///\r
/// Size of the binary update image which immediately follows this structure\r
///\r
- UINT32 UpdateImageSize;\r
+ UINT32 UpdateImageSize;\r
\r
///\r
/// Size of the VendorCode bytes which optionally immediately follow binary update image in the capsule\r
///\r
- UINT32 UpdateVendorCodeSize;\r
+ UINT32 UpdateVendorCodeSize;\r
\r
///\r
/// The HardwareInstance to target with this update. If value is zero it means match all\r
/// This header is outside the signed data of the Authentication Info structure and\r
/// therefore can be modified without changing the Auth data.\r
///\r
- UINT64 UpdateHardwareInstance;\r
+ UINT64 UpdateHardwareInstance;\r
\r
///\r
/// A 64-bit bitmask that determines what sections are added to the payload.\r
/// #define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001\r
/// #define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002\r
///\r
- UINT64 ImageCapsuleSupport;\r
+ UINT64 ImageCapsuleSupport;\r
} EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;\r
\r
#pragma pack()\r
\r
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001\r
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003\r
+#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001\r
+#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002\r
\r
-#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION 0x00000001\r
-#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003\r
-#define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001\r
-#define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002\r
-\r
-extern EFI_GUID gEfiFmpCapsuleGuid;\r
+extern EFI_GUID gEfiFmpCapsuleGuid;\r
\r
#endif\r
0x8BE4DF61, 0x93CA, 0x11d2, {0xAA, 0x0D, 0x00, 0xE0, 0x98, 0x03, 0x2B, 0x8C } \\r
}\r
\r
-extern EFI_GUID gEfiGlobalVariableGuid;\r
+extern EFI_GUID gEfiGlobalVariableGuid;\r
\r
//\r
// Follow UEFI 2.4 spec:\r
/// The language codes that the firmware supports. This value is deprecated.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes"\r
+#define EFI_LANG_CODES_VARIABLE_NAME L"LangCodes"\r
///\r
/// The language code that the system is configured for. This value is deprecated.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_LANG_VARIABLE_NAME L"Lang"\r
+#define EFI_LANG_VARIABLE_NAME L"Lang"\r
///\r
/// The firmware's boot managers timeout, in seconds, before initiating the default boot selection.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout"\r
+#define EFI_TIME_OUT_VARIABLE_NAME L"Timeout"\r
///\r
/// The language codes that the firmware supports.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes"\r
+#define EFI_PLATFORM_LANG_CODES_VARIABLE_NAME L"PlatformLangCodes"\r
///\r
/// The language code that the system is configured for.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang"\r
+#define EFI_PLATFORM_LANG_VARIABLE_NAME L"PlatformLang"\r
///\r
/// The device path of the default input/output/error output console.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_CON_IN_VARIABLE_NAME L"ConIn"\r
-#define EFI_CON_OUT_VARIABLE_NAME L"ConOut"\r
-#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut"\r
+#define EFI_CON_IN_VARIABLE_NAME L"ConIn"\r
+#define EFI_CON_OUT_VARIABLE_NAME L"ConOut"\r
+#define EFI_ERR_OUT_VARIABLE_NAME L"ErrOut"\r
///\r
/// The device path of all possible input/output/error output devices.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev"\r
-#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev"\r
-#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev"\r
+#define EFI_CON_IN_DEV_VARIABLE_NAME L"ConInDev"\r
+#define EFI_CON_OUT_DEV_VARIABLE_NAME L"ConOutDev"\r
+#define EFI_ERR_OUT_DEV_VARIABLE_NAME L"ErrOutDev"\r
///\r
/// The ordered boot option load list.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder"\r
+#define EFI_BOOT_ORDER_VARIABLE_NAME L"BootOrder"\r
///\r
/// The boot option for the next boot only.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext"\r
+#define EFI_BOOT_NEXT_VARIABLE_NAME L"BootNext"\r
///\r
/// The boot option that was selected for the current boot.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent"\r
+#define EFI_BOOT_CURRENT_VARIABLE_NAME L"BootCurrent"\r
///\r
/// The types of boot options supported by the boot manager. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport"\r
+#define EFI_BOOT_OPTION_SUPPORT_VARIABLE_NAME L"BootOptionSupport"\r
///\r
/// The ordered driver load option list.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder"\r
+#define EFI_DRIVER_ORDER_VARIABLE_NAME L"DriverOrder"\r
///\r
/// The ordered System Prep Application load option list.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder"\r
+#define EFI_SYS_PREP_ORDER_VARIABLE_NAME L"SysPrepOrder"\r
///\r
/// Identifies the level of hardware error record persistence\r
/// support implemented by the platform. This variable is\r
/// only modified by firmware and is read-only to the OS.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport"\r
+#define EFI_HW_ERR_REC_SUPPORT_VARIABLE_NAME L"HwErrRecSupport"\r
///\r
/// Whether the system is operating in setup mode (1) or not (0).\r
/// All other values are reserved. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_SETUP_MODE_NAME L"SetupMode"\r
+#define EFI_SETUP_MODE_NAME L"SetupMode"\r
///\r
/// The Key Exchange Key Signature Database.\r
/// Its attribute is NV+BS+RT+AT.\r
///\r
-#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK"\r
+#define EFI_KEY_EXCHANGE_KEY_NAME L"KEK"\r
///\r
/// The public Platform Key.\r
/// Its attribute is NV+BS+RT+AT.\r
///\r
-#define EFI_PLATFORM_KEY_NAME L"PK"\r
+#define EFI_PLATFORM_KEY_NAME L"PK"\r
///\r
/// Array of GUIDs representing the type of signatures supported\r
/// by the platform firmware. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport"\r
+#define EFI_SIGNATURE_SUPPORT_NAME L"SignatureSupport"\r
///\r
/// Whether the platform firmware is operating in Secure boot mode (1) or not (0).\r
/// All other values are reserved. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"\r
+#define EFI_SECURE_BOOT_MODE_NAME L"SecureBoot"\r
///\r
/// The OEM's default Key Exchange Key Signature Database. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault"\r
+#define EFI_KEK_DEFAULT_VARIABLE_NAME L"KEKDefault"\r
///\r
/// The OEM's default public Platform Key. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault"\r
+#define EFI_PK_DEFAULT_VARIABLE_NAME L"PKDefault"\r
///\r
/// The OEM's default secure boot signature store. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault"\r
+#define EFI_DB_DEFAULT_VARIABLE_NAME L"dbDefault"\r
///\r
/// The OEM's default secure boot blacklist signature store. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault"\r
+#define EFI_DBX_DEFAULT_VARIABLE_NAME L"dbxDefault"\r
///\r
/// The OEM's default secure boot timestamp signature store. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault"\r
+#define EFI_DBT_DEFAULT_VARIABLE_NAME L"dbtDefault"\r
///\r
/// Allows the firmware to indicate supported features and actions to the OS.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported"\r
+#define EFI_OS_INDICATIONS_SUPPORT_VARIABLE_NAME L"OsIndicationsSupported"\r
///\r
/// Allows the OS to request the firmware to enable certain features and to take certain actions.\r
/// Its attribute is NV+BS+RT.\r
///\r
-#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications"\r
+#define EFI_OS_INDICATIONS_VARIABLE_NAME L"OsIndications"\r
///\r
/// Whether the system is configured to use only vendor provided\r
/// keys or not. Should be treated as read-only.\r
/// Its attribute is BS+RT.\r
///\r
-#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys"\r
+#define EFI_VENDOR_KEYS_VARIABLE_NAME L"VendorKeys"\r
\r
#endif\r
0x024dee41, 0x33e7, 0x11d3, {0x9d, 0x69, 0x00, 0x08, 0xc7, 0x81, 0xf3, 0x9f } \\r
}\r
\r
-extern EFI_GUID gEfiPartTypeUnusedGuid;\r
-extern EFI_GUID gEfiPartTypeSystemPartGuid;\r
-extern EFI_GUID gEfiPartTypeLegacyMbrGuid;\r
+extern EFI_GUID gEfiPartTypeUnusedGuid;\r
+extern EFI_GUID gEfiPartTypeSystemPartGuid;\r
+extern EFI_GUID gEfiPartTypeLegacyMbrGuid;\r
\r
#endif\r
}\r
\r
typedef struct {\r
- EFI_PHYSICAL_ADDRESS FrameBufferBase;\r
- UINT32 FrameBufferSize;\r
- EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;\r
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;\r
+ UINT32 FrameBufferSize;\r
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION GraphicsMode;\r
} EFI_PEI_GRAPHICS_INFO_HOB;\r
\r
typedef struct {\r
- UINT16 VendorId; ///< Ignore if the value is 0xFFFF.\r
- UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.\r
- UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.\r
- UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.\r
- UINT8 RevisionId; ///< Ignore if the value is 0xFF.\r
- UINT8 BarIndex; ///< Ignore if the value is 0xFF.\r
+ UINT16 VendorId; ///< Ignore if the value is 0xFFFF.\r
+ UINT16 DeviceId; ///< Ignore if the value is 0xFFFF.\r
+ UINT16 SubsystemVendorId; ///< Ignore if the value is 0xFFFF.\r
+ UINT16 SubsystemId; ///< Ignore if the value is 0xFFFF.\r
+ UINT8 RevisionId; ///< Ignore if the value is 0xFF.\r
+ UINT8 BarIndex; ///< Ignore if the value is 0xFF.\r
} EFI_PEI_GRAPHICS_DEVICE_INFO_HOB;\r
\r
-extern EFI_GUID gEfiGraphicsInfoHobGuid;\r
-extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;\r
+extern EFI_GUID gEfiGraphicsInfoHobGuid;\r
+extern EFI_GUID gEfiGraphicsDeviceInfoHobGuid;\r
\r
#endif\r
0x414E6BDD, 0xE47B, 0x47cc, {0xB2, 0x44, 0xBB, 0x61, 0x02, 0x0C, 0xF5, 0x16} \\r
}\r
\r
-extern EFI_GUID gEfiHardwareErrorVariableGuid;\r
+extern EFI_GUID gEfiHardwareErrorVariableGuid;\r
\r
#endif\r
#define EFI_HII_STANDARD_FORM_GUID \\r
{ 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } }\r
\r
-extern EFI_GUID gEfiHiiStandardFormGuid;\r
+extern EFI_GUID gEfiHiiStandardFormGuid;\r
\r
#endif\r
#define EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID \\r
{ 0x14982a4f, 0xb0ed, 0x45b8, { 0xa8, 0x11, 0x5a, 0x7a, 0x9b, 0xc2, 0x32, 0xdf }}\r
\r
-extern EFI_GUID gEfiHiiKeyBoardLayoutGuid;\r
+extern EFI_GUID gEfiHiiKeyBoardLayoutGuid;\r
\r
#endif\r
#define EFI_HII_REST_STYLE_FORMSET_GUID \\r
{ 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } }\r
\r
-extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;\r
-extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;\r
-extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;\r
-extern EFI_GUID gEfiHiiRestStyleFormsetGuid;\r
+extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;\r
+extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;\r
+extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;\r
+extern EFI_GUID gEfiHiiRestStyleFormsetGuid;\r
\r
#endif\r
0x7739f24c, 0x93d7, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-extern EFI_GUID gEfiHobListGuid;\r
+extern EFI_GUID gEfiHobListGuid;\r
\r
#endif\r
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID\r
/// for the authorized signature database.\r
///\r
-#define EFI_IMAGE_SECURITY_DATABASE L"db"\r
+#define EFI_IMAGE_SECURITY_DATABASE L"db"\r
///\r
/// Varialbe name with guid EFI_IMAGE_SECURITY_DATABASE_GUID\r
/// for the forbidden signature database.\r
///\r
-#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"\r
+#define EFI_IMAGE_SECURITY_DATABASE1 L"dbx"\r
///\r
/// Variable name with guid EFI_IMAGE_SECURITY_DATABASE_GUID\r
/// for the timestamp signature database.\r
///\r
-#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"\r
+#define EFI_IMAGE_SECURITY_DATABASE2 L"dbt"\r
\r
-#define SECURE_BOOT_MODE_ENABLE 1\r
-#define SECURE_BOOT_MODE_DISABLE 0\r
+#define SECURE_BOOT_MODE_ENABLE 1\r
+#define SECURE_BOOT_MODE_DISABLE 0\r
\r
-#define SETUP_MODE 1\r
-#define USER_MODE 0\r
+#define SETUP_MODE 1\r
+#define USER_MODE 0\r
\r
-//***********************************************************************\r
+// ***********************************************************************\r
// Signature Database\r
-//***********************************************************************\r
+// ***********************************************************************\r
///\r
/// The format of a signature database.\r
///\r
///\r
/// An identifier which identifies the agent which added the signature to the list.\r
///\r
- EFI_GUID SignatureOwner;\r
+ EFI_GUID SignatureOwner;\r
///\r
/// The format of the signature is defined by the SignatureType.\r
///\r
- UINT8 SignatureData[1];\r
+ UINT8 SignatureData[1];\r
} EFI_SIGNATURE_DATA;\r
\r
typedef struct {\r
///\r
/// Type of the signature. GUID signature types are defined in below.\r
///\r
- EFI_GUID SignatureType;\r
+ EFI_GUID SignatureType;\r
///\r
/// Total size of the signature list, including this header.\r
///\r
- UINT32 SignatureListSize;\r
+ UINT32 SignatureListSize;\r
///\r
/// Size of the signature header which precedes the array of signatures.\r
///\r
- UINT32 SignatureHeaderSize;\r
+ UINT32 SignatureHeaderSize;\r
///\r
/// Size of each signature.\r
///\r
- UINT32 SignatureSize;\r
+ UINT32 SignatureSize;\r
///\r
/// Header before the array of signatures. The format of this header is specified\r
/// by the SignatureType.\r
///\r
/// The SHA256 hash of an X.509 certificate's To-Be-Signed contents.\r
///\r
- EFI_SHA256_HASH ToBeSignedHash;\r
+ EFI_SHA256_HASH ToBeSignedHash;\r
///\r
/// The time that the certificate shall be considered to be revoked.\r
///\r
- EFI_TIME TimeOfRevocation;\r
+ EFI_TIME TimeOfRevocation;\r
} EFI_CERT_X509_SHA256;\r
\r
typedef struct {\r
///\r
/// The SHA384 hash of an X.509 certificate's To-Be-Signed contents.\r
///\r
- EFI_SHA384_HASH ToBeSignedHash;\r
+ EFI_SHA384_HASH ToBeSignedHash;\r
///\r
/// The time that the certificate shall be considered to be revoked.\r
///\r
- EFI_TIME TimeOfRevocation;\r
+ EFI_TIME TimeOfRevocation;\r
} EFI_CERT_X509_SHA384;\r
\r
typedef struct {\r
///\r
/// The SHA512 hash of an X.509 certificate's To-Be-Signed contents.\r
///\r
- EFI_SHA512_HASH ToBeSignedHash;\r
+ EFI_SHA512_HASH ToBeSignedHash;\r
///\r
/// The time that the certificate shall be considered to be revoked.\r
///\r
- EFI_TIME TimeOfRevocation;\r
+ EFI_TIME TimeOfRevocation;\r
} EFI_CERT_X509_SHA512;\r
\r
#pragma pack()\r
0x4aafd29d, 0x68df, 0x49ee, {0x8a, 0xa9, 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7} \\r
}\r
\r
-//***********************************************************************\r
+// ***********************************************************************\r
// Image Execution Information Table Definition\r
-//***********************************************************************\r
+// ***********************************************************************\r
typedef UINT32 EFI_IMAGE_EXECUTION_ACTION;\r
\r
#define EFI_IMAGE_EXECUTION_AUTHENTICATION 0x00000007\r
///\r
} EFI_IMAGE_EXECUTION_INFO;\r
\r
-\r
typedef struct {\r
///\r
/// Number of EFI_IMAGE_EXECUTION_INFO structures.\r
///\r
- UINTN NumberOfImages;\r
+ UINTN NumberOfImages;\r
///\r
/// Number of image instances of EFI_IMAGE_EXECUTION_INFO structures.\r
///\r
// EFI_IMAGE_EXECUTION_INFO InformationInfo[]\r
} EFI_IMAGE_EXECUTION_INFO_TABLE;\r
\r
-extern EFI_GUID gEfiImageSecurityDatabaseGuid;\r
-extern EFI_GUID gEfiCertSha256Guid;\r
-extern EFI_GUID gEfiCertRsa2048Guid;\r
-extern EFI_GUID gEfiCertRsa2048Sha256Guid;\r
-extern EFI_GUID gEfiCertSha1Guid;\r
-extern EFI_GUID gEfiCertRsa2048Sha1Guid;\r
-extern EFI_GUID gEfiCertX509Guid;\r
-extern EFI_GUID gEfiCertSha224Guid;\r
-extern EFI_GUID gEfiCertSha384Guid;\r
-extern EFI_GUID gEfiCertSha512Guid;\r
-extern EFI_GUID gEfiCertX509Sha256Guid;\r
-extern EFI_GUID gEfiCertX509Sha384Guid;\r
-extern EFI_GUID gEfiCertX509Sha512Guid;\r
-extern EFI_GUID gEfiCertPkcs7Guid;\r
+extern EFI_GUID gEfiImageSecurityDatabaseGuid;\r
+extern EFI_GUID gEfiCertSha256Guid;\r
+extern EFI_GUID gEfiCertRsa2048Guid;\r
+extern EFI_GUID gEfiCertRsa2048Sha256Guid;\r
+extern EFI_GUID gEfiCertSha1Guid;\r
+extern EFI_GUID gEfiCertRsa2048Sha1Guid;\r
+extern EFI_GUID gEfiCertX509Guid;\r
+extern EFI_GUID gEfiCertSha224Guid;\r
+extern EFI_GUID gEfiCertSha384Guid;\r
+extern EFI_GUID gEfiCertSha512Guid;\r
+extern EFI_GUID gEfiCertX509Sha256Guid;\r
+extern EFI_GUID gEfiCertX509Sha384Guid;\r
+extern EFI_GUID gEfiCertX509Sha512Guid;\r
+extern EFI_GUID gEfiCertPkcs7Guid;\r
\r
#endif\r
{0x67d6f4cd, 0xd6b8, 0x4573, \\r
{0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}\r
\r
-\r
#pragma pack(1)\r
\r
typedef struct {\r
///\r
/// Version of the structure, initially 0x00000001.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
\r
///\r
/// The unique identifier of this capsule.\r
///\r
- UINT32 CapsuleId;\r
+ UINT32 CapsuleId;\r
\r
///\r
/// The length of the JSON payload immediately following this header, in bytes.\r
///\r
- UINT32 PayloadLength;\r
+ UINT32 PayloadLength;\r
\r
///\r
/// Variable length buffer containing the JSON payload that should be parsed and applied to the system. The\r
/// definition of the JSON schema used in the payload is beyond the scope of this specification.\r
///\r
- UINT8 Payload[];\r
+ UINT8 Payload[];\r
} EFI_JSON_CAPSULE_HEADER;\r
\r
typedef struct {\r
///\r
/// The length of the following ConfigData, in bytes.\r
///\r
- UINT32 ConfigDataLength;\r
+ UINT32 ConfigDataLength;\r
\r
///\r
/// Variable length buffer containing the JSON payload that describes one group of configuration data within\r
/// current system. The definition of the JSON schema used in this payload is beyond the scope of this specification.\r
///\r
- UINT8 ConfigData[];\r
+ UINT8 ConfigData[];\r
} EFI_JSON_CONFIG_DATA_ITEM;\r
\r
typedef struct {\r
///\r
/// Version of the structure, initially 0x00000001.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
\r
///\r
////The total length of EFI_JSON_CAPSULE_CONFIG_DATA, in bytes.\r
///\r
- UINT32 TotalLength;\r
+ UINT32 TotalLength;\r
\r
///\r
/// Array of configuration data groups.\r
///\r
- EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];\r
+ EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];\r
} EFI_JSON_CAPSULE_CONFIG_DATA;\r
\r
#pragma pack()\r
\r
-extern EFI_GUID gEfiJsonConfigDataTableGuid;\r
-extern EFI_GUID gEfiJsonCapsuleDataTableGuid;\r
-extern EFI_GUID gEfiJsonCapsuleResultTableGuid;\r
-extern EFI_GUID gEfiJsonCapsuleIdGuid;\r
-\r
+extern EFI_GUID gEfiJsonConfigDataTableGuid;\r
+extern EFI_GUID gEfiJsonCapsuleDataTableGuid;\r
+extern EFI_GUID gEfiJsonCapsuleResultTableGuid;\r
+extern EFI_GUID gEfiJsonCapsuleIdGuid;\r
\r
#endif\r
#define LINUX_EFI_INITRD_MEDIA_GUID \\r
{0x5568e427, 0x68fc, 0x4f3d, {0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68}}\r
\r
-extern EFI_GUID gLinuxEfiInitrdMediaGuid;\r
+extern EFI_GUID gLinuxEfiInitrdMediaGuid;\r
\r
#endif\r
0x914AEBE7, 0x4635, 0x459b, { 0xAA, 0x1C, 0x11, 0xE2, 0x19, 0xB0, 0x3A, 0x10 } \\r
}\r
\r
-extern EFI_GUID gEfiMdePkgTokenSpaceGuid;\r
+extern EFI_GUID gEfiMdePkgTokenSpaceGuid;\r
\r
#endif\r
#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \\r
{0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} }\r
\r
-extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid;\r
-extern EFI_GUID gEfiHobMemoryAllocStackGuid;\r
-extern EFI_GUID gEfiHobMemoryAllocModuleGuid;\r
+extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid;\r
+extern EFI_GUID gEfiHobMemoryAllocStackGuid;\r
+extern EFI_GUID gEfiHobMemoryAllocModuleGuid;\r
\r
#endif\r
#ifndef __UEFI_MEMORY_ATTRIBUTES_TABLE_H__\r
#define __UEFI_MEMORY_ATTRIBUTES_TABLE_H__\r
\r
-#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\\r
+#define EFI_MEMORY_ATTRIBUTES_TABLE_GUID {\\r
0xdcfa911d, 0x26eb, 0x469f, {0xa2, 0x20, 0x38, 0xb7, 0xdc, 0x46, 0x12, 0x20} \\r
}\r
\r
typedef struct {\r
- UINT32 Version;\r
- UINT32 NumberOfEntries;\r
- UINT32 DescriptorSize;\r
- UINT32 Reserved;\r
-//EFI_MEMORY_DESCRIPTOR Entry[1];\r
+ UINT32 Version;\r
+ UINT32 NumberOfEntries;\r
+ UINT32 DescriptorSize;\r
+ UINT32 Reserved;\r
+ // EFI_MEMORY_DESCRIPTOR Entry[1];\r
} EFI_MEMORY_ATTRIBUTES_TABLE;\r
\r
#define EFI_MEMORY_ATTRIBUTES_TABLE_VERSION 0x00000001\r
\r
-extern EFI_GUID gEfiMemoryAttributesTableGuid;\r
+extern EFI_GUID gEfiMemoryAttributesTableGuid;\r
\r
#endif\r
/// EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
/// EFI_VARIABLE_RUNTIME_ACCESS\r
///\r
-#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"\r
+#define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"\r
\r
///\r
/// 0 = Firmware MUST clear the MOR bit\r
/// 1 = Firmware MUST set the MOR bit\r
///\r
-#define MOR_CLEAR_MEMORY_BIT_MASK 0x01\r
+#define MOR_CLEAR_MEMORY_BIT_MASK 0x01\r
\r
///\r
/// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.\r
/// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.\r
///\r
-#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10\r
+#define MOR_DISABLEAUTODETECT_BIT_MASK 0x10\r
\r
///\r
/// MOR field bit offset\r
///\r
-#define MOR_CLEAR_MEMORY_BIT_OFFSET 0\r
-#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4\r
+#define MOR_CLEAR_MEMORY_BIT_OFFSET 0\r
+#define MOR_DISABLEAUTODETECT_BIT_OFFSET 4\r
\r
/**\r
Return the ClearMemory bit value 0 or 1.\r
\r
@return ClearMemory bit value\r
**/\r
-#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)\r
+#define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)\r
\r
/**\r
Return the DisableAutoDetect bit value 0 or 1.\r
\r
@return DisableAutoDetect bit value\r
**/\r
-#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)\r
+#define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)\r
\r
-extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;\r
+extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;\r
\r
#endif\r
//\r
// GUID name defined in spec.\r
//\r
-#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID\r
+#define MPS_TABLE_GUID EFI_MPS_TABLE_GUID\r
\r
-extern EFI_GUID gEfiMpsTableGuid;\r
+extern EFI_GUID gEfiMpsTableGuid;\r
\r
#endif\r
0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \\r
}\r
\r
-extern EFI_GUID gEfiPcAnsiGuid;\r
-extern EFI_GUID gEfiVT100Guid;\r
-extern EFI_GUID gEfiVT100PlusGuid;\r
-extern EFI_GUID gEfiVTUTF8Guid;\r
-extern EFI_GUID gEfiUartDevicePathGuid;\r
-extern EFI_GUID gEfiSasDevicePathGuid;\r
+extern EFI_GUID gEfiPcAnsiGuid;\r
+extern EFI_GUID gEfiVT100Guid;\r
+extern EFI_GUID gEfiVT100PlusGuid;\r
+extern EFI_GUID gEfiVTUTF8Guid;\r
+extern EFI_GUID gEfiUartDevicePathGuid;\r
+extern EFI_GUID gEfiSasDevicePathGuid;\r
\r
#endif\r
{ 0xeb66918a, 0x7eef, 0x402a, \\r
{ 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}\r
\r
-\r
-\r
-\r
#pragma pack(1)\r
\r
typedef struct {\r
///\r
/// Version of the structure, must be 0x1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
\r
///\r
/// Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8.\r
///\r
- UINT16 Length;\r
+ UINT16 Length;\r
\r
///\r
/// Bitmask of which calls are or are not supported, where a bit set to 1 indicates\r
/// that the call is supported, and 0 indicates that it is not.\r
///\r
- UINT32 RuntimeServicesSupported;\r
+ UINT32 RuntimeServicesSupported;\r
} EFI_RT_PROPERTIES_TABLE;\r
\r
#pragma pack()\r
\r
-#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1\r
+#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1\r
\r
#define EFI_RT_SUPPORTED_GET_TIME 0x0001\r
#define EFI_RT_SUPPORTED_SET_TIME 0x0002\r
#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES 0x1000\r
#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO 0x2000\r
\r
-extern EFI_GUID gEfiRtPropertiesTableGuid;\r
+extern EFI_GUID gEfiRtPropertiesTableGuid;\r
\r
#endif\r
0xf2fd1544, 0x9794, 0x4a2c, {0x99, 0x2e, 0xe5, 0xbb, 0xcf, 0x20, 0xe3, 0x94 } \\r
}\r
\r
-extern EFI_GUID gEfiSmbiosTableGuid;\r
-extern EFI_GUID gEfiSmbios3TableGuid;\r
+extern EFI_GUID gEfiSmbiosTableGuid;\r
+extern EFI_GUID gEfiSmbios3TableGuid;\r
\r
#endif\r
/// Designates the number of possible regions in the system\r
/// that can be usable for SMRAM.\r
///\r
- UINT32 NumberOfSmmReservedRegions;\r
+ UINT32 NumberOfSmmReservedRegions;\r
///\r
/// Used throughout this protocol to describe the candidate\r
/// regions for SMRAM that are supported by this platform.\r
///\r
- EFI_SMRAM_DESCRIPTOR Descriptor[1];\r
+ EFI_SMRAM_DESCRIPTOR Descriptor[1];\r
} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;\r
\r
-extern EFI_GUID gEfiSmmSmramMemoryGuid;\r
+extern EFI_GUID gEfiSmmSmramMemoryGuid;\r
\r
#endif\r
-\r
/// not be the same for different boots. Type EFI_HII_HANDLE is defined in\r
/// EFI_HII_DATABASE_PROTOCOL.NewPackageList() in the UEFI Specification.\r
///\r
- EFI_HII_HANDLE Handle;\r
+ EFI_HII_HANDLE Handle;\r
///\r
/// When combined with Handle, the string token can be used to retrieve the string.\r
/// Type EFI_STRING_ID is defined in EFI_IFR_OP_HEADER in the UEFI Specification.\r
///\r
- EFI_STRING_ID Token;\r
+ EFI_STRING_ID Token;\r
} EFI_STATUS_CODE_STRING_TOKEN;\r
\r
typedef union {\r
///\r
/// ASCII formatted string.\r
///\r
- CHAR8 *Ascii;\r
+ CHAR8 *Ascii;\r
///\r
/// Unicode formatted string.\r
///\r
- CHAR16 *Unicode;\r
+ CHAR16 *Unicode;\r
///\r
/// HII handle/token pair.\r
///\r
- EFI_STATUS_CODE_STRING_TOKEN Hii;\r
+ EFI_STATUS_CODE_STRING_TOKEN Hii;\r
} EFI_STATUS_CODE_STRING;\r
\r
///\r
/// DataHeader.Type should be\r
/// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// Specifies the format of the data in String.\r
///\r
- EFI_STRING_TYPE StringType;\r
+ EFI_STRING_TYPE StringType;\r
///\r
/// A pointer to the extended data. The data follows the format specified by\r
/// StringType.\r
///\r
- EFI_STATUS_CODE_STRING String;\r
+ EFI_STATUS_CODE_STRING String;\r
} EFI_STATUS_CODE_STRING_DATA;\r
\r
-extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;\r
+extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;\r
\r
///\r
/// Global ID for the following structures:\r
/// device that does not have a device path. DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The device path to the controller or the hardware device. Note that this parameter is a\r
/// variable-length device path structure and not a pointer to such a structure. This structure is\r
/// sizeof (EFI_DEVICE_HANDLE_EXTENDED_DATA) - HeaderSize, and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The device handle.\r
///\r
- EFI_HANDLE Handle;\r
+ EFI_HANDLE Handle;\r
} EFI_DEVICE_HANDLE_EXTENDED_DATA;\r
\r
///\r
/// sizeof(UINT32) + 3 * sizeof (UINT16) ), and DataHeader.Type\r
/// should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The PCI BAR. Applicable only for PCI devices. Ignored for all other devices.\r
///\r
- UINT32 Bar;\r
+ UINT32 Bar;\r
///\r
/// DevicePathSize should be zero if it is a virtual device that is not associated with\r
/// a device path. Otherwise, this parameter is the length of the variable-length\r
/// DevicePath.\r
///\r
- UINT16 DevicePathSize;\r
+ UINT16 DevicePathSize;\r
///\r
/// Represents the size the ReqRes parameter. ReqResSize should be zero if the\r
/// requested resources are not provided as a part of extended data.\r
///\r
- UINT16 ReqResSize;\r
+ UINT16 ReqResSize;\r
///\r
/// Represents the size the AllocRes parameter. AllocResSize should be zero if the\r
/// allocated resources are not provided as a part of extended data.\r
///\r
- UINT16 AllocResSize;\r
+ UINT16 AllocResSize;\r
///\r
/// The device path to the controller or the hardware device that did not get the requested\r
/// resources. Note that this parameter is the variable-length device path structure and not\r
///\r
/// The INT16 number by which to multiply the base-2 representation.\r
///\r
- INT16 Value;\r
+ INT16 Value;\r
///\r
/// The INT16 number by which to raise the base-2 calculation.\r
///\r
- INT16 Exponent;\r
+ INT16 Exponent;\r
} EFI_EXP_BASE10_DATA;\r
\r
///\r
/// HeaderSize, and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The voltage value at the time of the error.\r
///\r
- EFI_EXP_BASE10_DATA Voltage;\r
+ EFI_EXP_BASE10_DATA Voltage;\r
///\r
/// The voltage threshold.\r
///\r
- EFI_EXP_BASE10_DATA Threshold;\r
+ EFI_EXP_BASE10_DATA Threshold;\r
} EFI_COMPUTING_UNIT_VOLTAGE_ERROR_DATA;\r
\r
///\r
/// HeaderSize, and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The version of the microcode update from the header.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
} EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA;\r
\r
///\r
/// HeaderSize, and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The number of seconds that the computing unit timer was configured to expire.\r
///\r
- EFI_EXP_BASE10_DATA TimerLimit;\r
+ EFI_EXP_BASE10_DATA TimerLimit;\r
} EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA;\r
\r
///\r
/// HeaderSize , and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The unit number of the computing unit that does not match.\r
///\r
- UINT32 Instance;\r
+ UINT32 Instance;\r
///\r
/// The attributes describing the failure.\r
///\r
- UINT16 Attributes;\r
+ UINT16 Attributes;\r
} EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;\r
\r
///\r
/// HeaderSize , and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The thermal value at the time of the error.\r
///\r
- EFI_EXP_BASE10_DATA Temperature;\r
+ EFI_EXP_BASE10_DATA Temperature;\r
///\r
/// The thermal threshold.\r
///\r
- EFI_EXP_BASE10_DATA Threshold;\r
+ EFI_EXP_BASE10_DATA Threshold;\r
} EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA;\r
\r
///\r
/// sizeof (EFI_CACHE_INIT_DATA) - HeaderSize , and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The cache level. Starts with 1 for level 1 cache.\r
///\r
- UINT32 Level;\r
+ UINT32 Level;\r
///\r
/// The type of cache.\r
///\r
- EFI_INIT_CACHE_TYPE Type;\r
+ EFI_INIT_CACHE_TYPE Type;\r
} EFI_CACHE_INIT_DATA;\r
\r
///\r
///\r
///\r
-typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;\r
+typedef UINT32 EFI_CPU_STATE_CHANGE_CAUSE;\r
\r
///\r
/// The reasons that the processor is disabled.\r
/// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.\r
///\r
///@{\r
-#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001\r
-#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002\r
-#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004\r
-#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008\r
-#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010\r
-#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020\r
-#define EFI_CPU_CAUSE_USER_SELECTION 0x0080\r
-#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100\r
-#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000\r
+#define EFI_CPU_CAUSE_INTERNAL_ERROR 0x0001\r
+#define EFI_CPU_CAUSE_THERMAL_ERROR 0x0002\r
+#define EFI_CPU_CAUSE_SELFTEST_FAILURE 0x0004\r
+#define EFI_CPU_CAUSE_PREBOOT_TIMEOUT 0x0008\r
+#define EFI_CPU_CAUSE_FAILED_TO_START 0x0010\r
+#define EFI_CPU_CAUSE_CONFIG_ERROR 0x0020\r
+#define EFI_CPU_CAUSE_USER_SELECTION 0x0080\r
+#define EFI_CPU_CAUSE_BY_ASSOCIATION 0x0100\r
+#define EFI_CPU_CAUSE_UNSPECIFIED 0x8000\r
///@}\r
\r
///\r
/// HeaderSize, and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The reason for disabling the processor.\r
///\r
- UINT32 Cause;\r
+ UINT32 Cause;\r
///\r
/// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.\r
/// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware\r
/// disabled, which means it is invisible to software and will not respond to IPIs.\r
///\r
- BOOLEAN SoftwareDisabled;\r
+ BOOLEAN SoftwareDisabled;\r
} EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA;\r
\r
///\r
/// Memory Error Operations. Used to fill in EFI_MEMORY_EXTENDED_ERROR_DATA.Operation.\r
///\r
///@{\r
-#define EFI_MEMORY_OPERATION_OTHER 0x01\r
-#define EFI_MEMORY_OPERATION_UNKNOWN 0x02\r
-#define EFI_MEMORY_OPERATION_READ 0x03\r
-#define EFI_MEMORY_OPERATION_WRITE 0x04\r
-#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05\r
+#define EFI_MEMORY_OPERATION_OTHER 0x01\r
+#define EFI_MEMORY_OPERATION_UNKNOWN 0x02\r
+#define EFI_MEMORY_OPERATION_READ 0x03\r
+#define EFI_MEMORY_OPERATION_WRITE 0x04\r
+#define EFI_MEMORY_OPERATION_PARTIAL_WRITE 0x05\r
///@}\r
\r
///\r
/// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The error granularity type.\r
///\r
- EFI_MEMORY_ERROR_GRANULARITY Granularity;\r
+ EFI_MEMORY_ERROR_GRANULARITY Granularity;\r
///\r
/// The operation that resulted in the error being detected.\r
///\r
- EFI_MEMORY_ERROR_OPERATION Operation;\r
+ EFI_MEMORY_ERROR_OPERATION Operation;\r
///\r
/// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with\r
/// the error. If unknown, should be initialized to 0.\r
/// Inconsistent with specification here:\r
/// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.\r
///\r
- UINTN Syndrome;\r
+ UINTN Syndrome;\r
///\r
/// The physical address of the error.\r
///\r
- EFI_PHYSICAL_ADDRESS Address;\r
+ EFI_PHYSICAL_ADDRESS Address;\r
///\r
/// The range, in bytes, within which the error address can be determined.\r
///\r
- UINTN Resolution;\r
+ UINTN Resolution;\r
} EFI_MEMORY_EXTENDED_ERROR_DATA;\r
\r
///\r
/// A definition to describe that the operation is performed on multiple devices within the array.\r
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.\r
///\r
-#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe\r
+#define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe\r
\r
///\r
/// A definition to describe that the operation is performed on all devices within the array.\r
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.\r
///\r
-#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff\r
+#define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff\r
\r
///\r
/// A definition to describe that the operation is performed on multiple arrays.\r
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.\r
///\r
-#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe\r
+#define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe\r
\r
///\r
/// A definition to describe that the operation is performed on all the arrays.\r
/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.\r
///\r
-#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff\r
+#define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff\r
\r
///\r
/// This extended data provides some context that consumers can use to locate a DIMM within the\r
/// sizeof (EFI_STATUS_CODE_DIMM_NUMBER) - HeaderSize, and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The memory array number.\r
///\r
- UINT16 Array;\r
+ UINT16 Array;\r
///\r
/// The device number within that Array.\r
///\r
- UINT16 Device;\r
+ UINT16 Device;\r
} EFI_STATUS_CODE_DIMM_NUMBER;\r
\r
///\r
/// HeaderSize, and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The instance number of the memory module that does not match.\r
///\r
- EFI_STATUS_CODE_DIMM_NUMBER Instance;\r
+ EFI_STATUS_CODE_DIMM_NUMBER Instance;\r
} EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;\r
\r
///\r
/// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The starting address of the memory range.\r
///\r
- EFI_PHYSICAL_ADDRESS Start;\r
+ EFI_PHYSICAL_ADDRESS Start;\r
///\r
/// The length in bytes of the memory range.\r
///\r
- EFI_PHYSICAL_ADDRESS Length;\r
+ EFI_PHYSICAL_ADDRESS Length;\r
} EFI_MEMORY_RANGE_EXTENDED_DATA;\r
\r
///\r
/// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The line number of the source file where the fault was generated.\r
///\r
- UINT32 LineNumber;\r
+ UINT32 LineNumber;\r
///\r
/// The size in bytes of FileName.\r
///\r
- UINT32 FileNameSize;\r
+ UINT32 FileNameSize;\r
///\r
/// A pointer to a NULL-terminated ASCII or Unicode string that represents\r
/// the file name of the source file where the fault was generated.\r
///\r
- EFI_STATUS_CODE_STRING_DATA *FileName;\r
+ EFI_STATUS_CODE_STRING_DATA *FileName;\r
} EFI_DEBUG_ASSERT_DATA;\r
\r
///\r
/// EFI_SYSTEM_CONTEXT_EBC is defined in EFI_DEBUG_SUPPORT_PROTOCOL\r
/// in the UEFI Specification.\r
///\r
- EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;\r
+ EFI_SYSTEM_CONTEXT_EBC SystemContextEbc;\r
///\r
/// The context of the IA-32 processor when the exception was generated. Type\r
/// EFI_SYSTEM_CONTEXT_IA32 is defined in the\r
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.\r
///\r
- EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;\r
+ EFI_SYSTEM_CONTEXT_IA32 SystemContextIa32;\r
///\r
/// The context of the Itanium(R) processor when the exception was generated. Type\r
/// EFI_SYSTEM_CONTEXT_IPF is defined in the\r
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.\r
///\r
- EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;\r
+ EFI_SYSTEM_CONTEXT_IPF SystemContextIpf;\r
///\r
/// The context of the X64 processor when the exception was generated. Type\r
/// EFI_SYSTEM_CONTEXT_X64 is defined in the\r
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.\r
///\r
- EFI_SYSTEM_CONTEXT_X64 SystemContextX64;\r
+ EFI_SYSTEM_CONTEXT_X64 SystemContextX64;\r
///\r
/// The context of the ARM processor when the exception was generated. Type\r
/// EFI_SYSTEM_CONTEXT_ARM is defined in the\r
/// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.\r
///\r
- EFI_SYSTEM_CONTEXT_ARM SystemContextArm;\r
+ EFI_SYSTEM_CONTEXT_ARM SystemContextArm;\r
} EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT;\r
\r
///\r
/// and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The system context.\r
///\r
- EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;\r
+ EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT Context;\r
} EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;\r
\r
///\r
/// and DataHeader.Type should be\r
/// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The controller handle.\r
///\r
- EFI_HANDLE ControllerHandle;\r
+ EFI_HANDLE ControllerHandle;\r
///\r
/// The driver binding handle.\r
///\r
- EFI_HANDLE DriverBindingHandle;\r
+ EFI_HANDLE DriverBindingHandle;\r
///\r
/// The size of the RemainingDevicePath. It is zero if the Start() function is\r
/// called with RemainingDevicePath = NULL. The UEFI Specification allows\r
/// that the Start() function of bus drivers can be called in this way.\r
///\r
- UINT16 DevicePathSize;\r
+ UINT16 DevicePathSize;\r
///\r
/// Matches the RemainingDevicePath parameter being passed to the Start() function.\r
/// Note that this parameter is the variable-length device path and not a pointer\r
/// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The handle corresponding to the device that this legacy option ROM is being invoked.\r
///\r
- EFI_HANDLE DeviceHandle;\r
+ EFI_HANDLE DeviceHandle;\r
///\r
/// The base address of the shadowed legacy ROM image. May or may not point to the shadow RAM area.\r
///\r
- EFI_PHYSICAL_ADDRESS RomImageBase;\r
+ EFI_PHYSICAL_ADDRESS RomImageBase;\r
} EFI_LEGACY_OPROM_EXTENDED_DATA;\r
\r
///\r
/// DataHeader.Size should be sizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize,\r
/// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.\r
///\r
- EFI_STATUS_CODE_DATA DataHeader;\r
+ EFI_STATUS_CODE_DATA DataHeader;\r
///\r
/// The EFI_STATUS return value of the service or function whose failure triggered the\r
/// reporting of the status code (generally an error code or a debug code).\r
///\r
- EFI_STATUS ReturnStatus;\r
+ EFI_STATUS ReturnStatus;\r
} EFI_RETURN_STATUS_EXTENDED_DATA;\r
\r
-extern EFI_GUID gEfiStatusCodeSpecificDataGuid;\r
+extern EFI_GUID gEfiStatusCodeSpecificDataGuid;\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _SYSTEM_RESOURCE_TABLE_H__\r
#define _SYSTEM_RESOURCE_TABLE_H__\r
\r
/// When the UEFI Specification is updated, this comment block can be\r
/// removed.\r
///\r
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000\r
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF\r
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN 0x00001000\r
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX 0x00003FFF\r
\r
typedef struct {\r
///\r
/// that can be updated via UpdateCapsule(). This GUID must be unique within all\r
/// entries of the ESRT.\r
///\r
- EFI_GUID FwClass;\r
+ EFI_GUID FwClass;\r
///\r
/// Identifies the type of firmware resource.\r
///\r
- UINT32 FwType;\r
+ UINT32 FwType;\r
///\r
/// The firmware version field represents the current version of the firmware\r
/// resource, value must always increase as a larger number represents a newer\r
/// version.\r
///\r
- UINT32 FwVersion;\r
+ UINT32 FwVersion;\r
///\r
/// The lowest firmware resource version to which a firmware resource can be\r
/// rolled back for the given system/device. Generally this is used to protect\r
/// against known and fixed security issues.\r
///\r
- UINT32 LowestSupportedFwVersion;\r
+ UINT32 LowestSupportedFwVersion;\r
///\r
/// The capsule flags field contains the CapsuleGuid flags (bits 0- 15) as defined\r
/// in the EFI_CAPSULE_HEADER that will be set in the capsule header.\r
///\r
- UINT32 CapsuleFlags;\r
+ UINT32 CapsuleFlags;\r
///\r
/// The last attempt version field describes the last firmware version for which\r
/// an update was attempted (uses the same format as Firmware Version).\r
/// in the case of a removable device, this value is set to 0 in cases where the\r
/// device has not been updated since being added to the system.\r
///\r
- UINT32 LastAttemptVersion;\r
+ UINT32 LastAttemptVersion;\r
///\r
/// The last attempt status field describes the result of the last firmware update\r
/// attempt for the firmware resource entry.\r
/// If a firmware update has never been attempted or is unknown, for example after\r
/// fresh insertion of a removable device, LastAttemptStatus must be set to Success.\r
///\r
- UINT32 LastAttemptStatus;\r
+ UINT32 LastAttemptStatus;\r
} EFI_SYSTEM_RESOURCE_ENTRY;\r
\r
typedef struct {\r
///\r
/// The number of firmware resources in the table, must not be zero.\r
///\r
- UINT32 FwResourceCount;\r
+ UINT32 FwResourceCount;\r
///\r
/// The maximum number of resource array entries that can be within the table\r
/// without reallocating the table, must not be zero.\r
///\r
- UINT32 FwResourceCountMax;\r
+ UINT32 FwResourceCountMax;\r
///\r
/// The version of the EFI_SYSTEM_RESOURCE_ENTRY entities used in this table.\r
/// This field should be set to 1.\r
///\r
- UINT64 FwResourceVersion;\r
+ UINT64 FwResourceVersion;\r
///\r
/// Array of EFI_SYSTEM_RESOURCE_ENTRY\r
///\r
- //EFI_SYSTEM_RESOURCE_ENTRY Entries[];\r
+ // EFI_SYSTEM_RESOURCE_ENTRY Entries[];\r
} EFI_SYSTEM_RESOURCE_TABLE;\r
\r
-extern EFI_GUID gEfiSystemResourceTableGuid;\r
+extern EFI_GUID gEfiSystemResourceTableGuid;\r
\r
#endif\r
#define EFI_VECTOR_HANDOF_TABLE_GUID \\r
{ 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}\r
\r
-extern EFI_GUID gEfiVectorHandoffTableGuid;\r
+extern EFI_GUID gEfiVectorHandoffTableGuid;\r
\r
#endif\r
//\r
// _WIN_CERTIFICATE.wCertificateType\r
//\r
-#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002\r
-#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0\r
-#define WIN_CERT_TYPE_EFI_GUID 0x0EF1\r
+#define WIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002\r
+#define WIN_CERT_TYPE_EFI_PKCS115 0x0EF0\r
+#define WIN_CERT_TYPE_EFI_GUID 0x0EF1\r
\r
///\r
/// The WIN_CERTIFICATE structure is part of the PE/COFF specification.\r
/// The length of the entire certificate,\r
/// including the length of the header, in bytes.\r
///\r
- UINT32 dwLength;\r
+ UINT32 dwLength;\r
///\r
/// The revision level of the WIN_CERTIFICATE\r
/// structure. The current revision level is 0x0200.\r
///\r
- UINT16 wRevision;\r
+ UINT16 wRevision;\r
///\r
/// The certificate type. See WIN_CERT_TYPE_xxx for the UEFI\r
/// certificate types. The UEFI specification reserves the range of\r
/// certificate type values from 0x0EF0 to 0x0EFF.\r
///\r
- UINT16 wCertificateType;\r
+ UINT16 wCertificateType;\r
///\r
/// The following is the actual certificate. The format of\r
/// the certificate depends on wCertificateType.\r
/// WIN_CERTIFICATE_UEFI_GUID.CertData\r
///\r
typedef struct {\r
- EFI_GUID HashType;\r
- UINT8 PublicKey[256];\r
- UINT8 Signature[256];\r
+ EFI_GUID HashType;\r
+ UINT8 PublicKey[256];\r
+ UINT8 Signature[256];\r
} EFI_CERT_BLOCK_RSA_2048_SHA256;\r
\r
-\r
///\r
/// Certificate which encapsulates a GUID-specific digital signature\r
///\r
/// This is the standard WIN_CERTIFICATE header, where\r
/// wCertificateType is set to WIN_CERT_TYPE_EFI_GUID.\r
///\r
- WIN_CERTIFICATE Hdr;\r
+ WIN_CERTIFICATE Hdr;\r
///\r
/// This is the unique id which determines the\r
/// format of the CertData. .\r
///\r
- EFI_GUID CertType;\r
+ EFI_GUID CertType;\r
///\r
/// The following is the certificate data. The format of\r
/// the data is determined by the CertType.\r
/// If CertType is EFI_CERT_TYPE_RSA2048_SHA256_GUID,\r
/// the CertData will be EFI_CERT_BLOCK_RSA_2048_SHA256 structure.\r
///\r
- UINT8 CertData[1];\r
+ UINT8 CertData[1];\r
} WIN_CERTIFICATE_UEFI_GUID;\r
\r
-\r
///\r
/// Certificate which encapsulates the RSASSA_PKCS1-v1_5 digital signature.\r
///\r
/// This is the standard WIN_CERTIFICATE header, where\r
/// wCertificateType is set to WIN_CERT_TYPE_UEFI_PKCS1_15.\r
///\r
- WIN_CERTIFICATE Hdr;\r
+ WIN_CERTIFICATE Hdr;\r
///\r
/// This is the hashing algorithm which was performed on the\r
/// UEFI executable when creating the digital signature.\r
///\r
- EFI_GUID HashAlgorithm;\r
+ EFI_GUID HashAlgorithm;\r
///\r
/// The following is the actual digital signature. The\r
/// size of the signature is the same size as the key\r
///\r
} WIN_CERTIFICATE_EFI_PKCS1_15;\r
\r
-extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;\r
+extern EFI_GUID gEfiCertTypeRsa2048Sha256Guid;\r
\r
#endif\r
//\r
// Make sure we are using the correct packing rules per EFI specification\r
//\r
-#if !defined(__GNUC__)\r
-#pragma pack()\r
+#if !defined (__GNUC__)\r
+ #pragma pack()\r
#endif\r
\r
-#if defined(__INTEL_COMPILER)\r
+#if defined (__INTEL_COMPILER)\r
//\r
// Disable ICC's remark #869: "Parameter" was never referenced warning.\r
// This is legal ANSI C code so we disable the remark that is turned on with -Wall\r
//\r
-#pragma warning ( disable : 869 )\r
+ #pragma warning ( disable : 869 )\r
\r
//\r
// Disable ICC's remark #1418: external function definition with no prior declaration.\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 1418 )\r
+ #pragma warning ( disable : 1418 )\r
\r
//\r
// Disable ICC's remark #1419: external declaration in primary source file\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 1419 )\r
+ #pragma warning ( disable : 1419 )\r
\r
//\r
// Disable ICC's remark #593: "Variable" was set but never used.\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 593 )\r
+ #pragma warning ( disable : 593 )\r
\r
#endif\r
\r
-\r
-#if defined(_MSC_EXTENSIONS)\r
+#if defined (_MSC_EXTENSIONS)\r
\r
//\r
// Disable warning that make it impossible to compile at /W4\r
//\r
// Disabling bitfield type checking warnings.\r
//\r
-#pragma warning ( disable : 4214 )\r
+ #pragma warning ( disable : 4214 )\r
\r
//\r
// Disabling the unreferenced formal parameter warnings.\r
//\r
-#pragma warning ( disable : 4100 )\r
+ #pragma warning ( disable : 4100 )\r
\r
//\r
// Disable slightly different base types warning as CHAR8 * can not be set\r
// to a constant string.\r
//\r
-#pragma warning ( disable : 4057 )\r
+ #pragma warning ( disable : 4057 )\r
\r
//\r
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning\r
//\r
-#pragma warning ( disable : 4127 )\r
+ #pragma warning ( disable : 4127 )\r
\r
//\r
// This warning is caused by functions defined but not used. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4505 )\r
+ #pragma warning ( disable : 4505 )\r
\r
//\r
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4206 )\r
+ #pragma warning ( disable : 4206 )\r
\r
-#if defined(_MSC_VER) && _MSC_VER >= 1800\r
+ #if defined (_MSC_VER) && _MSC_VER >= 1800\r
\r
//\r
// Disable these warnings for VS2013.\r
// This warning is for potentially uninitialized local variable, and it may cause false\r
// positive issues in VS2013 and VS2015 build\r
//\r
-#pragma warning ( disable : 4701 )\r
+ #pragma warning ( disable : 4701 )\r
\r
//\r
// This warning is for potentially uninitialized local pointer variable, and it may cause\r
// false positive issues in VS2013 and VS2015 build\r
//\r
-#pragma warning ( disable : 4703 )\r
+ #pragma warning ( disable : 4703 )\r
\r
-#endif\r
+ #endif\r
\r
#endif\r
\r
+#if defined (_MSC_EXTENSIONS)\r
+\r
+//\r
+// use Microsoft C compiler dependent integer width types\r
+//\r
\r
-#if defined(_MSC_EXTENSIONS)\r
-\r
- //\r
- // use Microsoft C compiler dependent integer width types\r
- //\r
-\r
- ///\r
- /// 8-byte unsigned value.\r
- ///\r
- typedef unsigned __int64 UINT64;\r
- ///\r
- /// 8-byte signed value.\r
- ///\r
- typedef __int64 INT64;\r
- ///\r
- /// 4-byte unsigned value.\r
- ///\r
- typedef unsigned __int32 UINT32;\r
- ///\r
- /// 4-byte signed value.\r
- ///\r
- typedef __int32 INT32;\r
- ///\r
- /// 2-byte unsigned value.\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value.\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value.\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character.\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value.\r
- ///\r
- typedef signed char INT8;\r
+///\r
+/// 8-byte unsigned value.\r
+///\r
+typedef unsigned __int64 UINT64;\r
+///\r
+/// 8-byte signed value.\r
+///\r
+typedef __int64 INT64;\r
+///\r
+/// 4-byte unsigned value.\r
+///\r
+typedef unsigned __int32 UINT32;\r
+///\r
+/// 4-byte signed value.\r
+///\r
+typedef __int32 INT32;\r
+///\r
+/// 2-byte unsigned value.\r
+///\r
+typedef unsigned short UINT16;\r
+///\r
+/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
+///\r
+typedef unsigned short CHAR16;\r
+///\r
+/// 2-byte signed value.\r
+///\r
+typedef short INT16;\r
+///\r
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
+/// values are undefined.\r
+///\r
+typedef unsigned char BOOLEAN;\r
+///\r
+/// 1-byte unsigned value.\r
+///\r
+typedef unsigned char UINT8;\r
+///\r
+/// 1-byte Character.\r
+///\r
+typedef char CHAR8;\r
+///\r
+/// 1-byte signed value.\r
+///\r
+typedef signed char INT8;\r
#else\r
- ///\r
- /// 8-byte unsigned value.\r
- ///\r
- typedef unsigned long long UINT64;\r
- ///\r
- /// 8-byte signed value.\r
- ///\r
- typedef long long INT64;\r
- ///\r
- /// 4-byte unsigned value.\r
- ///\r
- typedef unsigned int UINT32;\r
- ///\r
- /// 4-byte signed value.\r
- ///\r
- typedef int INT32;\r
- ///\r
- /// 2-byte unsigned value.\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value.\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value.\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value\r
- ///\r
- typedef signed char INT8;\r
+///\r
+/// 8-byte unsigned value.\r
+///\r
+typedef unsigned long long UINT64;\r
+///\r
+/// 8-byte signed value.\r
+///\r
+typedef long long INT64;\r
+///\r
+/// 4-byte unsigned value.\r
+///\r
+typedef unsigned int UINT32;\r
+///\r
+/// 4-byte signed value.\r
+///\r
+typedef int INT32;\r
+///\r
+/// 2-byte unsigned value.\r
+///\r
+typedef unsigned short UINT16;\r
+///\r
+/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
+///\r
+typedef unsigned short CHAR16;\r
+///\r
+/// 2-byte signed value.\r
+///\r
+typedef short INT16;\r
+///\r
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
+/// values are undefined.\r
+///\r
+typedef unsigned char BOOLEAN;\r
+///\r
+/// 1-byte unsigned value.\r
+///\r
+typedef unsigned char UINT8;\r
+///\r
+/// 1-byte Character\r
+///\r
+typedef char CHAR8;\r
+///\r
+/// 1-byte signed value\r
+///\r
+typedef signed char INT8;\r
#endif\r
\r
///\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;\r
/// 8 bytes on supported 64-bit processor instructions.)\r
///\r
-typedef UINT32 UINTN;\r
+typedef UINT32 UINTN;\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;\r
/// 8 bytes on supported 64-bit processor instructions.)\r
///\r
-typedef INT32 INTN;\r
+typedef INT32 INTN;\r
\r
//\r
// Processor specific defines\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x80000000\r
+#define MAX_BIT 0x80000000\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
///\r
/// Maximum legal IA-32 address.\r
///\r
-#define MAX_ADDRESS 0xFFFFFFFF\r
+#define MAX_ADDRESS 0xFFFFFFFF\r
\r
///\r
/// Maximum usable address at boot time\r
///\r
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
\r
///\r
/// Maximum legal IA-32 INTN and UINTN values.\r
///\r
/// Minimum legal IA-32 INTN value.\r
///\r
-#define MIN_INTN (((INTN)-2147483647) - 1)\r
+#define MIN_INTN (((INTN)-2147483647) - 1)\r
\r
///\r
/// The stack alignment required for IA-32.\r
///\r
-#define CPU_STACK_ALIGNMENT sizeof(UINTN)\r
+#define CPU_STACK_ALIGNMENT sizeof(UINTN)\r
\r
///\r
/// Page allocation granularity for IA-32.\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
\r
//\r
// Modifier to ensure that all protocol member functions and EFI intrinsics\r
// EFI intrinsics are required to modify their member functions with EFIAPI.\r
//\r
#ifdef EFIAPI\r
- ///\r
- /// If EFIAPI is already defined, then we use that definition.\r
- ///\r
-#elif defined(_MSC_EXTENSIONS)\r
- ///\r
- /// Microsoft* compiler specific method for EFIAPI calling convention.\r
- ///\r
- #define EFIAPI __cdecl\r
-#elif defined(__GNUC__) || defined(__clang__)\r
- ///\r
- /// GCC specific method for EFIAPI calling convention.\r
- ///\r
- #define EFIAPI __attribute__((cdecl))\r
+///\r
+/// If EFIAPI is already defined, then we use that definition.\r
+///\r
+#elif defined (_MSC_EXTENSIONS)\r
+///\r
+/// Microsoft* compiler specific method for EFIAPI calling convention.\r
+///\r
+#define EFIAPI __cdecl\r
+#elif defined (__GNUC__) || defined (__clang__)\r
+///\r
+/// GCC specific method for EFIAPI calling convention.\r
+///\r
+#define EFIAPI __attribute__((cdecl))\r
#else\r
- ///\r
- /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
- /// is the standard.\r
- ///\r
- #define EFIAPI\r
+///\r
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
+/// is the standard.\r
+///\r
+#define EFIAPI\r
#endif\r
\r
-#if defined(__GNUC__) || defined(__clang__)\r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
+#if defined (__GNUC__) || defined (__clang__)\r
+///\r
+/// For GNU assembly code, .global or .globl can declare global symbols.\r
+/// Define this macro to unify the usage.\r
+///\r
+#define ASM_GLOBAL .globl\r
#endif\r
\r
/**\r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
-#define __USER_LABEL_PREFIX__ _\r
+#define __USER_LABEL_PREFIX__ _\r
#endif\r
\r
#endif\r
-\r
/// excluding the RSD PTR structure.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_COMMON_HEADER;\r
\r
#pragma pack(1)\r
/// The common ACPI description table header. This structure prefaces most ACPI tables.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT8 Revision;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT64 OemTableId;\r
- UINT32 OemRevision;\r
- UINT32 CreatorId;\r
- UINT32 CreatorRevision;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT8 Revision;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT64 OemTableId;\r
+ UINT32 OemRevision;\r
+ UINT32 CreatorId;\r
+ UINT32 CreatorRevision;\r
} EFI_ACPI_DESCRIPTION_HEADER;\r
#pragma pack()\r
\r
//\r
// Define for Descriptor\r
//\r
-#define ACPI_SMALL_ITEM_FLAG 0x00\r
-#define ACPI_LARGE_ITEM_FLAG 0x01\r
+#define ACPI_SMALL_ITEM_FLAG 0x00\r
+#define ACPI_LARGE_ITEM_FLAG 0x01\r
\r
//\r
// Small Item Descriptor Name\r
//\r
-#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04\r
-#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05\r
-#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06\r
-#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07\r
-#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08\r
-#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09\r
-#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E\r
-#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F\r
+#define ACPI_SMALL_IRQ_DESCRIPTOR_NAME 0x04\r
+#define ACPI_SMALL_DMA_DESCRIPTOR_NAME 0x05\r
+#define ACPI_SMALL_START_DEPENDENT_DESCRIPTOR_NAME 0x06\r
+#define ACPI_SMALL_END_DEPENDENT_DESCRIPTOR_NAME 0x07\r
+#define ACPI_SMALL_IO_PORT_DESCRIPTOR_NAME 0x08\r
+#define ACPI_SMALL_FIXED_IO_PORT_DESCRIPTOR_NAME 0x09\r
+#define ACPI_SMALL_VENDOR_DEFINED_DESCRIPTOR_NAME 0x0E\r
+#define ACPI_SMALL_END_TAG_DESCRIPTOR_NAME 0x0F\r
\r
//\r
// Large Item Descriptor Name\r
//\r
-#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01\r
-#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04\r
-#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05\r
-#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06\r
-#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07\r
-#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08\r
-#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09\r
-#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A\r
+#define ACPI_LARGE_24_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x01\r
+#define ACPI_LARGE_VENDOR_DEFINED_DESCRIPTOR_NAME 0x04\r
+#define ACPI_LARGE_32_BIT_MEMORY_RANGE_DESCRIPTOR_NAME 0x05\r
+#define ACPI_LARGE_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR_NAME 0x06\r
+#define ACPI_LARGE_DWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x07\r
+#define ACPI_LARGE_WORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x08\r
+#define ACPI_LARGE_EXTENDED_IRQ_DESCRIPTOR_NAME 0x09\r
+#define ACPI_LARGE_QWORD_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0A\r
\r
//\r
// Small Item Descriptor Value\r
//\r
-#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22\r
-#define ACPI_IRQ_DESCRIPTOR 0x23\r
-#define ACPI_DMA_DESCRIPTOR 0x2A\r
-#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30\r
-#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31\r
-#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38\r
-#define ACPI_IO_PORT_DESCRIPTOR 0x47\r
-#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B\r
-#define ACPI_END_TAG_DESCRIPTOR 0x79\r
+#define ACPI_IRQ_NOFLAG_DESCRIPTOR 0x22\r
+#define ACPI_IRQ_DESCRIPTOR 0x23\r
+#define ACPI_DMA_DESCRIPTOR 0x2A\r
+#define ACPI_START_DEPENDENT_DESCRIPTOR 0x30\r
+#define ACPI_START_DEPENDENT_EX_DESCRIPTOR 0x31\r
+#define ACPI_END_DEPENDENT_DESCRIPTOR 0x38\r
+#define ACPI_IO_PORT_DESCRIPTOR 0x47\r
+#define ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR 0x4B\r
+#define ACPI_END_TAG_DESCRIPTOR 0x79\r
\r
//\r
// Large Item Descriptor Value\r
//\r
-#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81\r
-#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85\r
-#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86\r
-#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87\r
-#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88\r
-#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89\r
-#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A\r
-#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A\r
+#define ACPI_24_BIT_MEMORY_RANGE_DESCRIPTOR 0x81\r
+#define ACPI_32_BIT_MEMORY_RANGE_DESCRIPTOR 0x85\r
+#define ACPI_32_BIT_FIXED_MEMORY_RANGE_DESCRIPTOR 0x86\r
+#define ACPI_DWORD_ADDRESS_SPACE_DESCRIPTOR 0x87\r
+#define ACPI_WORD_ADDRESS_SPACE_DESCRIPTOR 0x88\r
+#define ACPI_EXTENDED_INTERRUPT_DESCRIPTOR 0x89\r
+#define ACPI_QWORD_ADDRESS_SPACE_DESCRIPTOR 0x8A\r
+#define ACPI_ADDRESS_SPACE_DESCRIPTOR 0x8A\r
\r
//\r
// Resource Type\r
//\r
-#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00\r
-#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01\r
-#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02\r
+#define ACPI_ADDRESS_SPACE_TYPE_MEM 0x00\r
+#define ACPI_ADDRESS_SPACE_TYPE_IO 0x01\r
+#define ACPI_ADDRESS_SPACE_TYPE_BUS 0x02\r
\r
///\r
/// Power Management Timer frequency is fixed at 3.579545MHz.\r
///\r
-#define ACPI_TIMER_FREQUENCY 3579545\r
+#define ACPI_TIMER_FREQUENCY 3579545\r
\r
//\r
// Ensure proper structure formats\r
/// Address Space Descriptors.\r
///\r
typedef PACKED struct {\r
- UINT8 Desc;\r
- UINT16 Len;\r
- UINT8 ResType;\r
- UINT8 GenFlag;\r
- UINT8 SpecificFlag;\r
- UINT64 AddrSpaceGranularity;\r
- UINT64 AddrRangeMin;\r
- UINT64 AddrRangeMax;\r
- UINT64 AddrTranslationOffset;\r
- UINT64 AddrLen;\r
+ UINT8 Desc;\r
+ UINT16 Len;\r
+ UINT8 ResType;\r
+ UINT8 GenFlag;\r
+ UINT8 SpecificFlag;\r
+ UINT64 AddrSpaceGranularity;\r
+ UINT64 AddrRangeMin;\r
+ UINT64 AddrRangeMax;\r
+ UINT64 AddrTranslationOffset;\r
+ UINT64 AddrLen;\r
} EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
\r
typedef PACKED union {\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
PACKED struct {\r
- UINT8 Length : 3;\r
- UINT8 Name : 4;\r
- UINT8 Type : 1;\r
+ UINT8 Length : 3;\r
+ UINT8 Name : 4;\r
+ UINT8 Type : 1;\r
} Bits;\r
} ACPI_SMALL_RESOURCE_HEADER;\r
\r
typedef PACKED struct {\r
PACKED union {\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
PACKED struct {\r
- UINT8 Name : 7;\r
- UINT8 Type : 1;\r
- }Bits;\r
+ UINT8 Name : 7;\r
+ UINT8 Type : 1;\r
+ } Bits;\r
} Header;\r
- UINT16 Length;\r
+ UINT16 Length;\r
} ACPI_LARGE_RESOURCE_HEADER;\r
\r
///\r
/// IRQ Descriptor.\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT16 Mask;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT16 Mask;\r
} EFI_ACPI_IRQ_NOFLAG_DESCRIPTOR;\r
\r
///\r
/// IRQ Descriptor.\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT16 Mask;\r
- UINT8 Information;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT16 Mask;\r
+ UINT8 Information;\r
} EFI_ACPI_IRQ_DESCRIPTOR;\r
\r
///\r
/// DMA Descriptor.\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT8 ChannelMask;\r
- UINT8 Information;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT8 ChannelMask;\r
+ UINT8 Information;\r
} EFI_ACPI_DMA_DESCRIPTOR;\r
\r
///\r
/// I/O Port Descriptor\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT8 Information;\r
- UINT16 BaseAddressMin;\r
- UINT16 BaseAddressMax;\r
- UINT8 Alignment;\r
- UINT8 Length;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT8 Information;\r
+ UINT16 BaseAddressMin;\r
+ UINT16 BaseAddressMax;\r
+ UINT8 Alignment;\r
+ UINT8 Length;\r
} EFI_ACPI_IO_PORT_DESCRIPTOR;\r
\r
///\r
/// Fixed Location I/O Port Descriptor.\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT16 BaseAddress;\r
- UINT8 Length;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT16 BaseAddress;\r
+ UINT8 Length;\r
} EFI_ACPI_FIXED_LOCATION_IO_PORT_DESCRIPTOR;\r
\r
///\r
/// The End tag identifies an end of resource data.\r
///\r
typedef struct {\r
- UINT8 Desc;\r
- UINT8 Checksum;\r
+ UINT8 Desc;\r
+ UINT8 Checksum;\r
} EFI_ACPI_END_TAG_DESCRIPTOR;\r
\r
//\r
// General use definitions\r
//\r
-#define EFI_ACPI_RESERVED_BYTE 0x00\r
-#define EFI_ACPI_RESERVED_WORD 0x0000\r
-#define EFI_ACPI_RESERVED_DWORD 0x00000000\r
-#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000\r
+#define EFI_ACPI_RESERVED_BYTE 0x00\r
+#define EFI_ACPI_RESERVED_WORD 0x0000\r
+#define EFI_ACPI_RESERVED_DWORD 0x00000000\r
+#define EFI_ACPI_RESERVED_QWORD 0x0000000000000000\r
\r
//\r
// Resource Type Specific Flags\r
//\r
// Bit [0] : Write Status, _RW\r
//\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_WRITE (1 << 0)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_READ_ONLY (0 << 0)\r
//\r
// Bit [2:1] : Memory Attributes, _MEM\r
//\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE (0 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE (1 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_WRITE_COMBINING (2 << 1)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE (3 << 1)\r
//\r
// Bit [4:3] : Memory Attributes, _MTP\r
//\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)\r
-#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_MEMORY (0 << 3)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_RESERVED (1 << 3)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_ACPI (2 << 3)\r
+#define EFI_APCI_MEMORY_RESOURCE_SPECIFIC_FLAG_ADDRESS_RANGE_NVS (3 << 3)\r
//\r
// Bit [5] : Memory to I/O Translation, _TTP\r
//\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)\r
-#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)\r
+#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)\r
\r
//\r
// IRQ Information\r
// Ref ACPI specification 6.4.2.1\r
//\r
-#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10\r
-#define EFI_ACPI_IRQ_SHARABLE 0x10\r
+#define EFI_ACPI_IRQ_SHARABLE_MASK 0x10\r
+#define EFI_ACPI_IRQ_SHARABLE 0x10\r
\r
-#define EFI_ACPI_IRQ_POLARITY_MASK 0x08\r
-#define EFI_ACPI_IRQ_HIGH_TRUE 0x00\r
-#define EFI_ACPI_IRQ_LOW_FALSE 0x08\r
+#define EFI_ACPI_IRQ_POLARITY_MASK 0x08\r
+#define EFI_ACPI_IRQ_HIGH_TRUE 0x00\r
+#define EFI_ACPI_IRQ_LOW_FALSE 0x08\r
\r
-#define EFI_ACPI_IRQ_MODE 0x01\r
-#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00\r
-#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01\r
+#define EFI_ACPI_IRQ_MODE 0x01\r
+#define EFI_ACPI_IRQ_LEVEL_TRIGGERED 0x00\r
+#define EFI_ACPI_IRQ_EDGE_TRIGGERED 0x01\r
\r
//\r
// DMA Information\r
// Ref ACPI specification 6.4.2.2\r
//\r
-#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60\r
-#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00\r
-#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20\r
-#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40\r
-#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60\r
+#define EFI_ACPI_DMA_SPEED_TYPE_MASK 0x60\r
+#define EFI_ACPI_DMA_SPEED_TYPE_COMPATIBILITY 0x00\r
+#define EFI_ACPI_DMA_SPEED_TYPE_A 0x20\r
+#define EFI_ACPI_DMA_SPEED_TYPE_B 0x40\r
+#define EFI_ACPI_DMA_SPEED_TYPE_F 0x60\r
\r
-#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04\r
-#define EFI_ACPI_DMA_BUS_MASTER 0x04\r
+#define EFI_ACPI_DMA_BUS_MASTER_MASK 0x04\r
+#define EFI_ACPI_DMA_BUS_MASTER 0x04\r
\r
-#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03\r
-#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00\r
-#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01\r
-#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02\r
+#define EFI_ACPI_DMA_TRANSFER_TYPE_MASK 0x03\r
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT 0x00\r
+#define EFI_ACPI_DMA_TRANSFER_TYPE_8_BIT_AND_16_BIT 0x01\r
+#define EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT 0x02\r
\r
//\r
// IO Information\r
// Ref ACPI specification 6.4.2.5\r
//\r
-#define EFI_ACPI_IO_DECODE_MASK 0x01\r
-#define EFI_ACPI_IO_DECODE_16_BIT 0x01\r
-#define EFI_ACPI_IO_DECODE_10_BIT 0x00\r
+#define EFI_ACPI_IO_DECODE_MASK 0x01\r
+#define EFI_ACPI_IO_DECODE_16_BIT 0x01\r
+#define EFI_ACPI_IO_DECODE_10_BIT 0x00\r
\r
//\r
// Memory Information\r
// Ref ACPI specification 6.4.3.4\r
//\r
-#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01\r
-#define EFI_ACPI_MEMORY_WRITABLE 0x01\r
-#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00\r
+#define EFI_ACPI_MEMORY_WRITE_STATUS_MASK 0x01\r
+#define EFI_ACPI_MEMORY_WRITABLE 0x01\r
+#define EFI_ACPI_MEMORY_NON_WRITABLE 0x00\r
\r
//\r
// Interrupt Vector Flags definitions for Extended Interrupt Descriptor\r
// Ref ACPI specification 6.4.3.6\r
//\r
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0\r
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1\r
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2\r
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3\r
-#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4\r
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_PRODUCER_CONSUMER_MASK BIT0\r
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_MODE_MASK BIT1\r
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_POLARITY_MASK BIT2\r
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_SHARABLE_MASK BIT3\r
+#define EFI_ACPI_EXTENDED_INTERRUPT_FLAG_WAKE_CAPABLITY_MASK BIT4\r
\r
//\r
// Ensure proper structure formats\r
/// Root System Description Pointer Structure.\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Reserved;\r
- UINT32 RsdtAddress;\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Reserved;\r
+ UINT32 RsdtAddress;\r
} EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 1.0b specification).\r
///\r
-#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT).\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 IntModel;\r
- UINT8 Reserved1;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 Reserved2;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 Reserved3;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT8 Reserved4;\r
- UINT8 Reserved5;\r
- UINT8 Reserved6;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 IntModel;\r
+ UINT8 Reserved1;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 Reserved2;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 Reserved3;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT8 Reserved4;\r
+ UINT8 Reserved5;\r
+ UINT8 Reserved6;\r
+ UINT32 Flags;\r
} EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
///\r
#define EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x01\r
\r
-#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0\r
-#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1\r
+#define EFI_ACPI_1_0_INT_MODE_DUAL_PIC 0\r
+#define EFI_ACPI_1_0_INT_MODE_MULTIPLE_APIC 1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_1_0_WBINVD BIT0\r
-#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_1_0_PROC_C1 BIT2\r
-#define EFI_ACPI_1_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_1_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_1_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_1_0_FIX_RTC BIT6\r
-#define EFI_ACPI_1_0_RTC_S4 BIT7\r
-#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_1_0_DCK_CAP BIT9\r
+#define EFI_ACPI_1_0_WBINVD BIT0\r
+#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_1_0_PROC_C1 BIT2\r
+#define EFI_ACPI_1_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_1_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_1_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_1_0_FIX_RTC BIT6\r
+#define EFI_ACPI_1_0_RTC_S4 BIT7\r
+#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_1_0_DCK_CAP BIT9\r
\r
///\r
/// Firmware ACPI Control Structure.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT8 Reserved[40];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT8 Reserved[40];\r
} EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_1_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_1_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform-specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 1.0b specification).\r
///\r
-#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_1_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_1_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 SystemVectorBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 SystemVectorBase;\r
} EFI_ACPI_1_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterruptVector;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterruptVector;\r
+ UINT16 Flags;\r
} EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Non-Maskable Interrupt Source Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterruptVector;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterruptVector;\r
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicInti;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicInti;\r
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
//\r
//\r
// Define for Descriptor\r
//\r
-#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\r
+#define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME 0x02\r
\r
-#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82\r
+#define ACPI_GENERIC_REGISTER_DESCRIPTOR 0x82\r
\r
//\r
// Ensure proper structure formats\r
/// ACPI 2.0 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 Reserved;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 Reserved;\r
+ UINT64 Address;\r
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 2.0 spec.)\r
///\r
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02\r
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_2_0_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 2.0 spec.)\r
///\r
-#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 2.0 spec.)\r
///\r
-#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_2_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT8 Reserved2[3];\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT8 Reserved2[3];\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
} EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
//\r
// Fixed ACPI Description Table Preferred Power Management Profile\r
//\r
-#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0\r
-#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1\r
-#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2\r
-#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3\r
-#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4\r
-#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5\r
-#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6\r
+#define EFI_ACPI_2_0_PM_PROFILE_UNSPECIFIED 0\r
+#define EFI_ACPI_2_0_PM_PROFILE_DESKTOP 1\r
+#define EFI_ACPI_2_0_PM_PROFILE_MOBILE 2\r
+#define EFI_ACPI_2_0_PM_PROFILE_WORKSTATION 3\r
+#define EFI_ACPI_2_0_PM_PROFILE_ENTERPRISE_SERVER 4\r
+#define EFI_ACPI_2_0_PM_PROFILE_SOHO_SERVER 5\r
+#define EFI_ACPI_2_0_PM_PROFILE_APPLIANCE_PC 6\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_2_0_8042 BIT1\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_2_0_8042 BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_WBINVD BIT0\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_2_0_PROC_C1 BIT2\r
-#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_2_0_FIX_RTC BIT6\r
-#define EFI_ACPI_2_0_RTC_S4 BIT7\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_2_0_DCK_CAP BIT9\r
-#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_2_0_HEADLESS BIT12\r
-#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_2_0_WBINVD BIT0\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_2_0_PROC_C1 BIT2\r
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_2_0_FIX_RTC BIT6\r
+#define EFI_ACPI_2_0_RTC_S4 BIT7\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_2_0_DCK_CAP BIT9\r
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_2_0_HEADLESS BIT12\r
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved[31];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 2.0 spec.)\r
///\r
-#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_2_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_2_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// Local SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
} EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 Reserved;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 Reserved;\r
} EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 2.0 spec.)\r
///\r
-#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
//\r
// Define for Descriptor\r
//\r
-#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B\r
+#define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME 0x0B\r
\r
-#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B\r
+#define ACPI_EXTENDED_ADDRESS_SPACE_DESCRIPTOR 0x8B\r
\r
//\r
// Ensure proper structure formats\r
//\r
// Memory Type Specific Flags\r
//\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010\r
-#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UC 0x0000000000000001\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WC 0x0000000000000002\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WT 0x0000000000000004\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_WB 0x0000000000000008\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_UCE 0x0000000000000010\r
+#define EFI_ACPI_MEMORY_TYPE_SPECIFIC_ATTRIBUTES_NV 0x0000000000008000\r
\r
//\r
// Ensure proper structure formats\r
/// ACPI 3.0 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 3.0b spec.)\r
///\r
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2\r
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 3.0b) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_3_0_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 3.0 spec.)\r
///\r
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 3.0 spec.)\r
///\r
-#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT8 Reserved2[3];\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT8 Reserved2[3];\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
} EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_3_0_8042 BIT1\r
-#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_3_0_8042 BIT1\r
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_3_0_WBINVD BIT0\r
-#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_3_0_PROC_C1 BIT2\r
-#define EFI_ACPI_3_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_3_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_3_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_3_0_FIX_RTC BIT6\r
-#define EFI_ACPI_3_0_RTC_S4 BIT7\r
-#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_3_0_DCK_CAP BIT9\r
-#define EFI_ACPI_3_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_3_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_3_0_HEADLESS BIT12\r
-#define EFI_ACPI_3_0_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_3_0_WBINVD BIT0\r
+#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_3_0_PROC_C1 BIT2\r
+#define EFI_ACPI_3_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_3_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_3_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_3_0_FIX_RTC BIT6\r
+#define EFI_ACPI_3_0_RTC_S4 BIT7\r
+#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_3_0_DCK_CAP BIT9\r
+#define EFI_ACPI_3_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_3_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_3_0_HEADLESS BIT12\r
+#define EFI_ACPI_3_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved[31];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_3_0_S4BIOS_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 3.0 spec.)\r
///\r
-#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_3_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_3_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_3_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 3.0 spec.)\r
///\r
-#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT8 Reserved[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_3_0_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_3_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_3_0_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// ACPI 4.0 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 4.0b spec.)\r
///\r
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2\r
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 4.0a) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_4_0_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT8 Reserved2[3];\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT8 Reserved2[3];\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
} EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_4_0_8042 BIT1\r
-#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_4_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_4_0_8042 BIT1\r
+#define EFI_ACPI_4_0_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_4_0_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_4_0_PCIE_ASPM_CONTROLS BIT4\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_4_0_WBINVD BIT0\r
-#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_4_0_PROC_C1 BIT2\r
-#define EFI_ACPI_4_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_4_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_4_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_4_0_FIX_RTC BIT6\r
-#define EFI_ACPI_4_0_RTC_S4 BIT7\r
-#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_4_0_DCK_CAP BIT9\r
-#define EFI_ACPI_4_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_4_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_4_0_HEADLESS BIT12\r
-#define EFI_ACPI_4_0_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_4_0_WBINVD BIT0\r
+#define EFI_ACPI_4_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_4_0_PROC_C1 BIT2\r
+#define EFI_ACPI_4_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_4_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_4_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_4_0_FIX_RTC BIT6\r
+#define EFI_ACPI_4_0_RTC_S4 BIT7\r
+#define EFI_ACPI_4_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_4_0_DCK_CAP BIT9\r
+#define EFI_ACPI_4_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_4_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_4_0_HEADLESS BIT12\r
+#define EFI_ACPI_4_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_4_0_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_4_0_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_4_0_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_4_0_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_4_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_4_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_4_0_S4BIOS_F BIT0\r
-#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_4_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0\r
+#define EFI_ACPI_4_0_OSPM_64BIT_WAKE__F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_4_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_4_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
+#define EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_4_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_4_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_4_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_4_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_4_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_4_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_4_0_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_4_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_4_0_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_4_0_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
} EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_4_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_4_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_4_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_4_0_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_4_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_4_0_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_4_0_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_4_0_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_4_0_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_4_0_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_4_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_4_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_4_0_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_4_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_4_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03\r
-#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_4_0_EINJ_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_4_0_EINJ_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_4_0_EINJ_STATUS_FAILED 0x03\r
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_4_0_EINJ_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_4_0_ERST_NOOP 0x04\r
-#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_4_0_ERST_ADD 0x08\r
-#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_4_0_ERST_STALL 0x0C\r
-#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_4_0_ERST_GOTO 0x0F\r
-#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_4_0_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_4_0_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_4_0_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_4_0_ERST_NOOP 0x04\r
+#define EFI_ACPI_4_0_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_4_0_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_4_0_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_4_0_ERST_ADD 0x08\r
+#define EFI_ACPI_4_0_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_4_0_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_4_0_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_4_0_ERST_STALL 0x0C\r
+#define EFI_ACPI_4_0_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_4_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_4_0_ERST_GOTO 0x0F\r
+#define EFI_ACPI_4_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_4_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_4_0_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_4_0_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 4.0 spec.)\r
///\r
-#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_4_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_4_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_4_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_4_0_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_4_0_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_4_0_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_4_0_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_4_0_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_4_0_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_4_0_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_4_0_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_4_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_4_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_4_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_4_0_EINJ_NOOP 0x04\r
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_4_0_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_4_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_4_0_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_4_0_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE;\r
\r
//\r
//\r
// Define for Descriptor\r
//\r
-#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A\r
-#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C\r
-#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E\r
+#define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME 0x0A\r
+#define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME 0x0C\r
+#define ACPI_LARGE_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR_NAME 0x0E\r
\r
-#define ACPI_FIXED_DMA_DESCRIPTOR 0x55\r
-#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C\r
-#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E\r
+#define ACPI_FIXED_DMA_DESCRIPTOR 0x55\r
+#define ACPI_GPIO_CONNECTION_DESCRIPTOR 0x8C\r
+#define ACPI_GENERIC_SERIAL_BUS_CONNECTION_DESCRIPTOR 0x8E\r
\r
#pragma pack(1)\r
\r
/// Generic DMA Descriptor.\r
///\r
typedef PACKED struct {\r
- ACPI_SMALL_RESOURCE_HEADER Header;\r
- UINT16 DmaRequestLine;\r
- UINT16 DmaChannel;\r
- UINT8 DmaTransferWidth;\r
+ ACPI_SMALL_RESOURCE_HEADER Header;\r
+ UINT16 DmaRequestLine;\r
+ UINT16 DmaChannel;\r
+ UINT8 DmaTransferWidth;\r
} EFI_ACPI_FIXED_DMA_DESCRIPTOR;\r
\r
///\r
UINT16 VendorDataLength;\r
} EFI_ACPI_GPIO_CONNECTION_DESCRIPTOR;\r
\r
-#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0\r
-#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1\r
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_INTERRUPT 0x0\r
+#define EFI_ACPI_GPIO_CONNECTION_TYPE_IO 0x1\r
\r
///\r
/// Serial Bus Resource Descriptor (Generic)\r
UINT16 TypeSpecificFlags;\r
UINT8 TypeSpecificRevisionId;\r
UINT16 TypeDataLength;\r
-// Type specific data\r
+ // Type specific data\r
} EFI_ACPI_SERIAL_BUS_RESOURCE_DESCRIPTOR;\r
\r
#define EFI_ACPI_SERIAL_BUS_RESOURCE_TYPE_I2C 0x1\r
/// ACPI 5.0 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_5_0_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_5_0_SYSTEM_IO 1\r
-#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_5_0_SMBUS 4\r
+#define EFI_ACPI_5_0_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_5_0_SYSTEM_IO 1\r
+#define EFI_ACPI_5_0_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_5_0_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_5_0_SMBUS 4\r
#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_5_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2\r
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.0) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_5_0_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT8 Reserved2[3];\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT8 Reserved2[3];\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
} EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_5_0_8042 BIT1\r
-#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_5_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_5_0_8042 BIT1\r
+#define EFI_ACPI_5_0_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_5_0_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_5_0_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_5_0_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_5_0_WBINVD BIT0\r
-#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_5_0_PROC_C1 BIT2\r
-#define EFI_ACPI_5_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_5_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_5_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_5_0_FIX_RTC BIT6\r
-#define EFI_ACPI_5_0_RTC_S4 BIT7\r
-#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_5_0_DCK_CAP BIT9\r
-#define EFI_ACPI_5_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_5_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_5_0_HEADLESS BIT12\r
-#define EFI_ACPI_5_0_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_5_0_WBINVD BIT0\r
+#define EFI_ACPI_5_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_5_0_PROC_C1 BIT2\r
+#define EFI_ACPI_5_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_5_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_5_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_5_0_FIX_RTC BIT6\r
+#define EFI_ACPI_5_0_RTC_S4 BIT7\r
+#define EFI_ACPI_5_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_5_0_DCK_CAP BIT9\r
+#define EFI_ACPI_5_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_5_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_5_0_HEADLESS BIT12\r
+#define EFI_ACPI_5_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_5_0_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_5_0_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_5_0_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_5_0_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_5_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_5_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_5_0_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_0_S4BIOS_F BIT0\r
-#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_5_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_5_0_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_5_0_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_5_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_5_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
+#define EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_5_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_5_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_5_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_5_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_5_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicId;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicId;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
} EFI_ACPI_5_0_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_0_GIC_ENABLED BIT0\r
-#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_5_0_GIC_ENABLED BIT0\r
+#define EFI_ACPI_5_0_PERFORMANCE_INTERRUPT_MODEL BIT1\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_5_0_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_5_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_5_0_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_5_0_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_5_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_5_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_5_0_BGRT_VERSION 0x01\r
+#define EFI_ACPI_5_0_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01\r
-#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED\r
-#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED\r
+#define EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_5_0_BGRT_STATUS_INVALID EFI_ACPI_5_0_BGRT_STATUS_NOT_DISPLAYED\r
+#define EFI_ACPI_5_0_BGRT_STATUS_VALID EFI_ACPI_5_0_BGRT_STATUS_DISPLAYED\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_5_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_5_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_5_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 PhysicalAddress;\r
- UINT32 GlobalFlags;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 PhysicalAddress;\r
+ UINT32 GlobalFlags;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
} EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Global Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0\r
-#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1\r
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT BIT0\r
+#define EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE BIT1\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_5_0_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
} EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_5_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_5_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_5_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_5_0_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_5_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_5_0_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_5_0_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_5_0_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_5_0_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_5_0_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_5_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_5_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_5_0_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_5_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_5_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_5_0_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_5_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_5_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_5_0_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_5_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_5_0_ERST_NOOP 0x04\r
-#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_5_0_ERST_ADD 0x08\r
-#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_5_0_ERST_STALL 0x0C\r
-#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_5_0_ERST_GOTO 0x0F\r
-#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_5_0_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_5_0_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_5_0_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_5_0_ERST_NOOP 0x04\r
+#define EFI_ACPI_5_0_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_5_0_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_5_0_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_5_0_ERST_ADD 0x08\r
+#define EFI_ACPI_5_0_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_5_0_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_5_0_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_5_0_ERST_STALL 0x0C\r
+#define EFI_ACPI_5_0_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_5_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_5_0_ERST_GOTO 0x0F\r
+#define EFI_ACPI_5_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_5_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_5_0_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_5_0_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_5_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_5_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_5_0_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_5_0_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_5_0_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_5_0_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_5_0_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_5_0_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_5_0_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_5_0_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_5_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_5_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_5_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_5_0_EINJ_NOOP 0x04\r
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_5_0_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_5_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_5_0_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_5_0_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 5.0 spec.)\r
///\r
-#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
\r
///\r
/// PCCT Global Flags\r
///\r
-#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0\r
+#define EFI_ACPI_5_0_PCCT_FLAGS_SCI_DOORBELL BIT0\r
\r
//\r
// PCCT Subspace type\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 GenerateSci:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 GenerateSci : 1;\r
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 SciDoorbell:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 SciDoorbell : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
/// "WAET" Windows ACPI Emulated Devices Table\r
///\r
#define EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE SIGNATURE_32('W', 'A', 'E', 'T')\r
-#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE\r
+#define EFI_ACPI_5_0_WINDOWS_ACPI_ENLIGHTENMENT_TABLE_SIGNATURE EFI_ACPI_5_0_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE\r
\r
///\r
/// "WDAT" Watchdog Action Table\r
/// ACPI 5.1 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_5_1_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_5_1_SYSTEM_IO 1\r
-#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_5_1_SMBUS 4\r
+#define EFI_ACPI_5_1_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_5_1_SYSTEM_IO 1\r
+#define EFI_ACPI_5_1_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_5_1_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_5_1_SMBUS 4\r
#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_5_1_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2\r
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 5.1) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_5_1_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
} EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05\r
+#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x05\r
#define EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_5_1_8042 BIT1\r
-#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_5_1_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_5_1_8042 BIT1\r
+#define EFI_ACPI_5_1_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_5_1_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_5_1_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_5_1_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_5_1_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_5_1_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_5_1_WBINVD BIT0\r
-#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_5_1_PROC_C1 BIT2\r
-#define EFI_ACPI_5_1_P_LVL2_UP BIT3\r
-#define EFI_ACPI_5_1_PWR_BUTTON BIT4\r
-#define EFI_ACPI_5_1_SLP_BUTTON BIT5\r
-#define EFI_ACPI_5_1_FIX_RTC BIT6\r
-#define EFI_ACPI_5_1_RTC_S4 BIT7\r
-#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_5_1_DCK_CAP BIT9\r
-#define EFI_ACPI_5_1_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_5_1_SEALED_CASE BIT11\r
-#define EFI_ACPI_5_1_HEADLESS BIT12\r
-#define EFI_ACPI_5_1_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_5_1_WBINVD BIT0\r
+#define EFI_ACPI_5_1_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_5_1_PROC_C1 BIT2\r
+#define EFI_ACPI_5_1_P_LVL2_UP BIT3\r
+#define EFI_ACPI_5_1_PWR_BUTTON BIT4\r
+#define EFI_ACPI_5_1_SLP_BUTTON BIT5\r
+#define EFI_ACPI_5_1_FIX_RTC BIT6\r
+#define EFI_ACPI_5_1_RTC_S4 BIT7\r
+#define EFI_ACPI_5_1_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_5_1_DCK_CAP BIT9\r
+#define EFI_ACPI_5_1_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_5_1_SEALED_CASE BIT11\r
+#define EFI_ACPI_5_1_HEADLESS BIT12\r
+#define EFI_ACPI_5_1_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_5_1_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_5_1_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_5_1_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_5_1_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_5_1_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_5_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_5_1_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_5_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_1_S4BIOS_F BIT0\r
-#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_5_1_S4BIOS_F BIT0\r
+#define EFI_ACPI_5_1_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_5_1_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_5_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_5_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
+#define EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x03\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_1_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_5_1_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_5_1_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_5_1_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_5_1_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_5_1_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
} EFI_ACPI_5_1_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GIC_ENABLED BIT0\r
-#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_5_1_GIC_ENABLED BIT0\r
+#define EFI_ACPI_5_1_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_5_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_5_1_GIC_V1 0x01\r
-#define EFI_ACPI_5_1_GIC_V2 0x02\r
-#define EFI_ACPI_5_1_GIC_V3 0x03\r
-#define EFI_ACPI_5_1_GIC_V4 0x04\r
+#define EFI_ACPI_5_1_GIC_V1 0x01\r
+#define EFI_ACPI_5_1_GIC_V2 0x02\r
+#define EFI_ACPI_5_1_GIC_V3 0x03\r
+#define EFI_ACPI_5_1_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_5_1_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_5_1_GICR_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_5_1_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_5_1_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_5_1_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_5_1_GICC_ENABLED (1 << 0)\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_5_1_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_5_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_5_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_5_1_BGRT_VERSION 0x01\r
+#define EFI_ACPI_5_1_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_5_1_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_5_1_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_5_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_5_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_5_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_5_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_5_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_5_1_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
} EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_5_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_5_1_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_5_1_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_5_1_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_5_1_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_5_1_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_5_1_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_5_1_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_5_1_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_5_1_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_5_1_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_5_1_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_5_1_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_5_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_5_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_5_1_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_5_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_5_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_5_1_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_5_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_5_1_ERST_NOOP 0x04\r
-#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_5_1_ERST_ADD 0x08\r
-#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_5_1_ERST_STALL 0x0C\r
-#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_5_1_ERST_GOTO 0x0F\r
-#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_5_1_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_5_1_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_5_1_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_5_1_ERST_NOOP 0x04\r
+#define EFI_ACPI_5_1_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_5_1_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_5_1_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_5_1_ERST_ADD 0x08\r
+#define EFI_ACPI_5_1_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_5_1_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_5_1_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_5_1_ERST_STALL 0x0C\r
+#define EFI_ACPI_5_1_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_5_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_5_1_ERST_GOTO 0x0F\r
+#define EFI_ACPI_5_1_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_5_1_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_5_1_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_5_1_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_5_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_5_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_5_1_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_5_1_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_5_1_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_5_1_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_5_1_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_5_1_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_5_1_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_5_1_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_5_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_5_1_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_5_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_5_1_EINJ_NOOP 0x04\r
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_5_1_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_5_1_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_5_1_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_5_1_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 5.1 spec.)\r
///\r
-#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
\r
///\r
/// PCCT Global Flags\r
///\r
-#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0\r
+#define EFI_ACPI_5_1_PCCT_FLAGS_SCI_DOORBELL BIT0\r
\r
//\r
// PCCT Subspace type\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 GenerateSci:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 GenerateSci : 1;\r
} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 SciDoorbell:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 SciDoorbell : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
/// ACPI 6.0 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_6_0_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_6_0_SYSTEM_IO 1\r
-#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_6_0_SMBUS 4\r
+#define EFI_ACPI_6_0_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_6_0_SYSTEM_IO 1\r
+#define EFI_ACPI_6_0_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_6_0_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_6_0_SMBUS 4\r
#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_6_0_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2\r
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.0) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_0_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x00\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_0_8042 BIT1\r
-#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_0_8042 BIT1\r
+#define EFI_ACPI_6_0_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_0_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_0_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_0_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_0_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_0_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_0_WBINVD BIT0\r
-#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_0_PROC_C1 BIT2\r
-#define EFI_ACPI_6_0_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_0_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_0_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_0_FIX_RTC BIT6\r
-#define EFI_ACPI_6_0_RTC_S4 BIT7\r
-#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_0_DCK_CAP BIT9\r
-#define EFI_ACPI_6_0_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_0_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_0_HEADLESS BIT12\r
-#define EFI_ACPI_6_0_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_0_WBINVD BIT0\r
+#define EFI_ACPI_6_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_0_PROC_C1 BIT2\r
+#define EFI_ACPI_6_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_0_FIX_RTC BIT6\r
+#define EFI_ACPI_6_0_RTC_S4 BIT7\r
+#define EFI_ACPI_6_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_0_DCK_CAP BIT9\r
+#define EFI_ACPI_6_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_0_HEADLESS BIT12\r
+#define EFI_ACPI_6_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_0_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_0_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_0_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_0_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_0_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_0_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_0_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_0_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_0_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.0 Errata A spec.)\r
///\r
-#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
+#define EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_0_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_6_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_0_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_0_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_0_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_0_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_0_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_0_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_0_GIC_V1 0x01\r
-#define EFI_ACPI_6_0_GIC_V2 0x02\r
-#define EFI_ACPI_6_0_GIC_V3 0x03\r
-#define EFI_ACPI_6_0_GIC_V4 0x04\r
+#define EFI_ACPI_6_0_GIC_V1 0x01\r
+#define EFI_ACPI_6_0_GIC_V2 0x02\r
+#define EFI_ACPI_6_0_GIC_V3 0x03\r
+#define EFI_ACPI_6_0_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_0_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_0_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_0_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_0_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_0_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_0_GICC_ENABLED (1 << 0)\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_0_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_0_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_0_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_0_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_0_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_0_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_0_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_0_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_0_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_0_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.0 spec.)\r
//\r
-#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_0_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
} EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_0_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF BIT4\r
#define EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 MemoryDevicePhysicalID;\r
- UINT16 MemoryDeviceRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 MemoryDeviceRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 MemoryDevicePhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 MemoryDeviceStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 MemoryDevicePhysicalID;\r
+ UINT16 MemoryDeviceRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 MemoryDeviceRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 MemoryDevicePhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 MemoryDeviceStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 Reserved_18[6];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 Reserved_18[6];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_0_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_0_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
} EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_0_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_0_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_0_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_0_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_0_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_0_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_0_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_0_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_0_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_0_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_0_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_0_ERST_ADD 0x08\r
-#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_0_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_0_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_0_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_0_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_0_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_0_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_0_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_0_ERST_ADD 0x08\r
+#define EFI_ACPI_6_0_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_0_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_0_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_0_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_0_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_0_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_0_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_0_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_0_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_0_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_0_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_0_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_0_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_0_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_0_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_0_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_0_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_0_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_0_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.0 spec.)\r
///\r
-#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
\r
///\r
/// PCCT Global Flags\r
///\r
-#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0\r
+#define EFI_ACPI_6_0_PCCT_FLAGS_SCI_DOORBELL BIT0\r
\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 GenerateSci:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 GenerateSci : 1;\r
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 SciDoorbell:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 SciDoorbell : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 DoorbellInterrupt;\r
- UINT8 DoorbellInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 DoorbellInterrupt;\r
+ UINT8 DoorbellInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 DoorbellInterrupt;\r
- UINT8 DoorbellInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\r
- UINT64 DoorbellAckPreserve;\r
- UINT64 DoorbellAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 DoorbellInterrupt;\r
+ UINT8 DoorbellInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\r
+ UINT64 DoorbellAckPreserve;\r
+ UINT64 DoorbellAckWrite;\r
} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
//\r
/// ACPI 6.1 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_6_1_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_6_1_SYSTEM_IO 1\r
-#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_6_1_SMBUS 4\r
+#define EFI_ACPI_6_1_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_6_1_SYSTEM_IO 1\r
+#define EFI_ACPI_6_1_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_6_1_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_6_1_SMBUS 4\r
#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_6_1_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2\r
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.1) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_1_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x01\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_1_8042 BIT1\r
-#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_1_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_1_8042 BIT1\r
+#define EFI_ACPI_6_1_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_1_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_1_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_1_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_1_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_1_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_1_WBINVD BIT0\r
-#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_1_PROC_C1 BIT2\r
-#define EFI_ACPI_6_1_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_1_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_1_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_1_FIX_RTC BIT6\r
-#define EFI_ACPI_6_1_RTC_S4 BIT7\r
-#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_1_DCK_CAP BIT9\r
-#define EFI_ACPI_6_1_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_1_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_1_HEADLESS BIT12\r
-#define EFI_ACPI_6_1_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_1_WBINVD BIT0\r
+#define EFI_ACPI_6_1_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_1_PROC_C1 BIT2\r
+#define EFI_ACPI_6_1_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_1_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_1_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_1_FIX_RTC BIT6\r
+#define EFI_ACPI_6_1_RTC_S4 BIT7\r
+#define EFI_ACPI_6_1_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_1_DCK_CAP BIT9\r
+#define EFI_ACPI_6_1_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_1_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_1_HEADLESS BIT12\r
+#define EFI_ACPI_6_1_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_1_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_1_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_1_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_1_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_1_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_1_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_1_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_1_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_1_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_1_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_1_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_1_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_1_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
+#define EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_1_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_1_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_6_1_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_1_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_1_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_1_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_1_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_1_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_1_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_1_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_1_GIC_V1 0x01\r
-#define EFI_ACPI_6_1_GIC_V2 0x02\r
-#define EFI_ACPI_6_1_GIC_V3 0x03\r
-#define EFI_ACPI_6_1_GIC_V4 0x04\r
+#define EFI_ACPI_6_1_GIC_V1 0x01\r
+#define EFI_ACPI_6_1_GIC_V2 0x02\r
+#define EFI_ACPI_6_1_GIC_V3 0x03\r
+#define EFI_ACPI_6_1_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_1_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_1_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_1_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_1_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_1_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_1_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_1_GICC_ENABLED (1 << 0)\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_1_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_1_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_1_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_1_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_1_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_1_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_1_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_1_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_1_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_1_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.1 spec.)\r
//\r
-#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
//\r
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
-#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
-#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
-#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
-#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
-#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
+#define EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
+#define EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
+#define EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
+#define EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
+#define EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
\r
//\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_1_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
} EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_1_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\r
#define EFI_ACPI_6_1_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NVDIMMPhysicalID;\r
- UINT16 NVDIMMRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 NVDIMMRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 NVDIMMPhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 NVDIMMStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NVDIMMPhysicalID;\r
+ UINT16 NVDIMMRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 NVDIMMRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 NVDIMMPhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 NVDIMMStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
-\r
-#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 ValidFields;\r
- UINT8 ManufacturingLocation;\r
- UINT16 ManufacturingDate;\r
- UINT8 Reserved_22[2];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
+\r
+#define EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 ValidFields;\r
+ UINT8 ManufacturingLocation;\r
+ UINT16 ManufacturingDate;\r
+ UINT8 Reserved_22[2];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_1_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_1_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
- UINT8 Timestamp[8];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
+ UINT8 Timestamp[8];\r
} EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_1_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
-#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
+#define EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Version 2 Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
- UINT64 ReadAckPreserve;\r
- UINT64 ReadAckWrite;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
+ UINT64 ReadAckPreserve;\r
+ UINT64 ReadAckWrite;\r
} EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_1_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
-#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
+#define EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_1_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_1_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_1_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_1_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_1_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_1_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_1_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_1_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_1_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_1_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_1_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_1_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_1_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_1_ERST_ADD 0x08\r
-#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_1_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_1_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_1_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_1_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_1_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_1_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_1_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_1_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_1_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_1_ERST_ADD 0x08\r
+#define EFI_ACPI_6_1_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_1_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_1_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_1_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_1_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_1_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_1_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_1_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_1_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_1_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_1_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_1_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_1_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_1_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_1_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_1_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_1_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_1_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_1_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_1_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_1_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_1_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_1_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_1_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_1_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_1_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_1_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_1_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_1_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.1 spec.)\r
///\r
-#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x01\r
\r
///\r
/// PCCT Global Flags\r
///\r
-#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0\r
+#define EFI_ACPI_6_1_PCCT_FLAGS_SCI_DOORBELL BIT0\r
\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 GenerateSci:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 GenerateSci : 1;\r
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 SciDoorbell:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 SciDoorbell : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 DoorbellInterrupt;\r
- UINT8 DoorbellInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 DoorbellInterrupt;\r
+ UINT8 DoorbellInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 DoorbellInterrupt;\r
- UINT8 DoorbellInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\r
- UINT64 DoorbellAckPreserve;\r
- UINT64 DoorbellAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 DoorbellInterrupt;\r
+ UINT8 DoorbellInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE DoorbellAckRegister;\r
+ UINT64 DoorbellAckPreserve;\r
+ UINT64 DoorbellAckWrite;\r
} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
//\r
//\r
// Large Item Descriptor Name\r
//\r
-#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D\r
-#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F\r
-#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10\r
-#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11\r
-#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12\r
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME 0x0D\r
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME 0x0F\r
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME 0x10\r
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME 0x11\r
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME 0x12\r
\r
//\r
// Large Item Descriptor Value\r
//\r
-#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D\r
-#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F\r
-#define ACPI_PIN_GROUP_DESCRIPTOR 0x90\r
-#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91\r
-#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92\r
+#define ACPI_PIN_FUNCTION_DESCRIPTOR 0x8D\r
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR 0x8F\r
+#define ACPI_PIN_GROUP_DESCRIPTOR 0x90\r
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR 0x91\r
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR 0x92\r
\r
#pragma pack(1)\r
\r
/// ACPI 6.2 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
// Generic Address Space Address IDs\r
//\r
-#define EFI_ACPI_6_2_SYSTEM_MEMORY 0\r
-#define EFI_ACPI_6_2_SYSTEM_IO 1\r
-#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2\r
-#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3\r
-#define EFI_ACPI_6_2_SMBUS 4\r
+#define EFI_ACPI_6_2_SYSTEM_MEMORY 0\r
+#define EFI_ACPI_6_2_SYSTEM_IO 1\r
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE 2\r
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER 3\r
+#define EFI_ACPI_6_2_SMBUS 4\r
#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL 0x0A\r
#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE 0x7F\r
\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2\r
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.2) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x02\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_2_8042 BIT1\r
-#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_2_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_2_8042 BIT1\r
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_2_WBINVD BIT0\r
-#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_2_PROC_C1 BIT2\r
-#define EFI_ACPI_6_2_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_2_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_2_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_2_FIX_RTC BIT6\r
-#define EFI_ACPI_6_2_RTC_S4 BIT7\r
-#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_2_DCK_CAP BIT9\r
-#define EFI_ACPI_6_2_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_2_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_2_HEADLESS BIT12\r
-#define EFI_ACPI_6_2_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_2_WBINVD BIT0\r
+#define EFI_ACPI_6_2_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_2_PROC_C1 BIT2\r
+#define EFI_ACPI_6_2_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_2_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_2_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_2_FIX_RTC BIT6\r
+#define EFI_ACPI_6_2_RTC_S4 BIT7\r
+#define EFI_ACPI_6_2_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_2_DCK_CAP BIT9\r
+#define EFI_ACPI_6_2_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_2_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_2_HEADLESS BIT12\r
+#define EFI_ACPI_6_2_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_2_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_2_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_2_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0\r
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_2_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_2_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_2_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_2_GIC_V1 0x01\r
-#define EFI_ACPI_6_2_GIC_V2 0x02\r
-#define EFI_ACPI_6_2_GIC_V3 0x03\r
-#define EFI_ACPI_6_2_GIC_V4 0x04\r
+#define EFI_ACPI_6_2_GIC_V1 0x01\r
+#define EFI_ACPI_6_2_GIC_V2 0x02\r
+#define EFI_ACPI_6_2_GIC_V3 0x03\r
+#define EFI_ACPI_6_2_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_2_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_2_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)\r
\r
///\r
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT8 Reserved[2];\r
- UINT32 ItsId;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT8 Reserved[2];\r
+ UINT32 ItsId;\r
} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;\r
\r
///\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_2_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI RASF Platform RAS Capabilities\r
///\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
-#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_2_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_2_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior to when the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.2 spec.)\r
//\r
-#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
//\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
-#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
-#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
-#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
\r
//\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\r
#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NVDIMMPhysicalID;\r
- UINT16 NVDIMMRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 NVDIMMRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 NVDIMMPhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 NVDIMMStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NVDIMMPhysicalID;\r
+ UINT16 NVDIMMRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 NVDIMMRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 NVDIMMPhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 NVDIMMStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
-\r
-#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 ValidFields;\r
- UINT8 ManufacturingLocation;\r
- UINT16 ManufacturingDate;\r
- UINT8 Reserved_22[2];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
+\r
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 ValidFields;\r
+ UINT8 ManufacturingLocation;\r
+ UINT16 ManufacturingDate;\r
+ UINT8 Reserved_22[2];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_2_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Secure DEVices Table (SDEV)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;\r
\r
///\r
/// SDEV Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION 0x01\r
\r
///\r
/// Secure Device types\r
///\r
-#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
-#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
\r
///\r
/// Secure Device flags\r
///\r
-#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
\r
///\r
/// SDEV Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;\r
\r
///\r
/// PCIe Endpoint Device based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 PciSegmentNumber;\r
- UINT16 StartBusNumber;\r
- UINT16 PciPathOffset;\r
- UINT16 PciPathLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 PciSegmentNumber;\r
+ UINT16 StartBusNumber;\r
+ UINT16 PciPathOffset;\r
+ UINT16 PciPathLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\r
\r
///\r
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 DeviceIdentifierOffset;\r
- UINT16 DeviceIdentifierLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 DeviceIdentifierOffset;\r
+ UINT16 DeviceIdentifierLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
- UINT8 Timestamp[8];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
+ UINT8 Timestamp[8];\r
} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
-#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
-#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Version 2 Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
- UINT64 ReadAckPreserve;\r
- UINT64 ReadAckWrite;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
+ UINT64 ReadAckPreserve;\r
+ UINT64 ReadAckWrite;\r
} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_2_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
UINT8 NumberOfHardwareBanks;\r
UINT8 Reserved1[3];\r
-} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;\r
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// HMAT - Heterogeneous Memory Attribute Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[4];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\r
\r
///\r
/// HMAT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01\r
\r
///\r
/// HMAT types\r
///\r
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00\r
-#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
-#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE 0x00\r
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
\r
///\r
/// HMAT Structure Header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;\r
\r
///\r
/// Memory Subsystem Address Range Structure flags\r
///\r
typedef struct {\r
- UINT16 ProcessorProximityDomainValid:1;\r
- UINT16 MemoryProximityDomainValid:1;\r
- UINT16 ReservationHint:1;\r
- UINT16 Reserved:13;\r
+ UINT16 ProcessorProximityDomainValid : 1;\r
+ UINT16 MemoryProximityDomainValid : 1;\r
+ UINT16 ReservationHint : 1;\r
+ UINT16 Reserved : 13;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;\r
\r
///\r
/// Memory Subsystem Address Range Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;\r
- UINT8 Reserved1[2];\r
- UINT32 ProcessorProximityDomain;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved2[4];\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS Flags;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProcessorProximityDomain;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved2[4];\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure flags\r
///\r
typedef struct {\r
- UINT8 MemoryHierarchy:5;\r
- UINT8 Reserved:3;\r
+ UINT8 MemoryHierarchy : 5;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
- UINT8 DataType;\r
- UINT8 Reserved1[2];\r
- UINT32 NumberOfInitiatorProximityDomains;\r
- UINT32 NumberOfTargetProximityDomains;\r
- UINT8 Reserved2[4];\r
- UINT64 EntryBaseUnit;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
+ UINT8 DataType;\r
+ UINT8 Reserved1[2];\r
+ UINT32 NumberOfInitiatorProximityDomains;\r
+ UINT32 NumberOfTargetProximityDomains;\r
+ UINT8 Reserved2[4];\r
+ UINT64 EntryBaseUnit;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\r
\r
///\r
/// Memory Side Cache Information Structure cache attributes\r
///\r
typedef struct {\r
- UINT32 TotalCacheLevels:4;\r
- UINT32 CacheLevel:4;\r
- UINT32 CacheAssociativity:4;\r
- UINT32 WritePolicy:4;\r
- UINT32 CacheLineSize:16;\r
+ UINT32 TotalCacheLevels : 4;\r
+ UINT32 CacheLevel : 4;\r
+ UINT32 CacheAssociativity : 4;\r
+ UINT32 WritePolicy : 4;\r
+ UINT32 CacheLineSize : 16;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\r
\r
///\r
/// Memory Side Cache Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved1[4];\r
- UINT64 MemorySideCacheSize;\r
- EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
- UINT8 Reserved2[2];\r
- UINT16 NumberOfSmbiosHandles;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved1[4];\r
+ UINT64 MemorySideCacheSize;\r
+ EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
+ UINT8 Reserved2[2];\r
+ UINT16 NumberOfSmbiosHandles;\r
} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
-#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_2_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_2_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_2_ERST_ADD 0x08\r
-#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_2_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_2_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_2_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_2_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_2_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_2_ERST_ADD 0x08\r
+#define EFI_ACPI_6_2_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_2_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_2_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_2_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_2_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_2_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_2_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_2_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
\r
///\r
/// PCCT Global Flags\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 NotifyOnCompletion:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 NotifyOnCompletion : 1;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 PlatformInterrupt:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 PlatformInterrupt : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckWrite;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 3 Extended PCC Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT32 AddressLength;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT32 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckSet;\r
- UINT8 Reserved1[8];\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
- UINT64 CommandCompleteCheckMask;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
- UINT64 CommandCompleteUpdatePreserve;\r
- UINT64 CommandCompleteUpdateSet;\r
- EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
- UINT64 ErrorStatusMask;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT32 AddressLength;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT32 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckSet;\r
+ UINT8 Reserved1[8];\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
+ UINT64 CommandCompleteCheckMask;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
+ UINT64 CommandCompleteUpdatePreserve;\r
+ UINT64 CommandCompleteUpdateSet;\r
+ EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
+ UINT64 ErrorStatusMask;\r
} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;\r
\r
///\r
///\r
typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;\r
\r
-#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Flags;\r
- UINT32 Length;\r
- UINT32 Command;\r
+ UINT32 Signature;\r
+ UINT32 Flags;\r
+ UINT32 Length;\r
+ UINT32 Command;\r
} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\r
\r
///\r
/// Platform Debug Trigger Table (PDTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 TriggerCount;\r
- UINT8 Reserved[3];\r
- UINT32 TriggerIdentifierArrayOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 TriggerCount;\r
+ UINT8 Reserved[3];\r
+ UINT32 TriggerIdentifierArrayOffset;\r
} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\r
\r
///\r
/// PDTT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
\r
///\r
/// PDTT Platform Communication Channel Identifier Structure\r
///\r
typedef struct {\r
- UINT16 SubChannelIdentifer:8;\r
- UINT16 Runtime:1;\r
- UINT16 WaitForCompletion:1;\r
- UINT16 Reserved:6;\r
+ UINT16 SubChannelIdentifer : 8;\r
+ UINT16 Runtime : 1;\r
+ UINT16 WaitForCompletion : 1;\r
+ UINT16 Reserved : 6;\r
} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;\r
\r
///\r
/// PCC Commands Codes used by Platform Debug Trigger Table\r
///\r
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
-#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
\r
///\r
/// PPTT Platform Communication Channel\r
/// Processor Properties Topology Table (PPTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\r
\r
///\r
/// PPTT Revision (as defined in ACPI 6.2 spec.)\r
///\r
-#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// PPTT types\r
///\r
-#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00\r
-#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01\r
-#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02\r
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR 0x00\r
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE 0x01\r
+#define EFI_ACPI_6_2_PPTT_TYPE_ID 0x02\r
\r
///\r
/// PPTT Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;\r
\r
///\r
/// For PPTT struct processor flags\r
///\r
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0\r
-#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1\r
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0\r
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1\r
\r
///\r
/// Processor hierarchy node structure flags\r
///\r
typedef struct {\r
- UINT32 PhysicalPackage:1;\r
- UINT32 AcpiProcessorIdValid:1;\r
- UINT32 Reserved:30;\r
+ UINT32 PhysicalPackage : 1;\r
+ UINT32 AcpiProcessorIdValid : 1;\r
+ UINT32 Reserved : 30;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;\r
\r
///\r
/// Processor hierarchy node structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
- UINT32 Parent;\r
- UINT32 AcpiProcessorId;\r
- UINT32 NumberOfPrivateResources;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
+ UINT32 Parent;\r
+ UINT32 AcpiProcessorId;\r
+ UINT32 NumberOfPrivateResources;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;\r
\r
///\r
/// Cache Type Structure flags\r
///\r
typedef struct {\r
- UINT32 SizePropertyValid:1;\r
- UINT32 NumberOfSetsValid:1;\r
- UINT32 AssociativityValid:1;\r
- UINT32 AllocationTypeValid:1;\r
- UINT32 CacheTypeValid:1;\r
- UINT32 WritePolicyValid:1;\r
- UINT32 LineSizeValid:1;\r
- UINT32 Reserved:25;\r
+ UINT32 SizePropertyValid : 1;\r
+ UINT32 NumberOfSetsValid : 1;\r
+ UINT32 AssociativityValid : 1;\r
+ UINT32 AllocationTypeValid : 1;\r
+ UINT32 CacheTypeValid : 1;\r
+ UINT32 WritePolicyValid : 1;\r
+ UINT32 LineSizeValid : 1;\r
+ UINT32 Reserved : 25;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;\r
\r
///\r
/// For cache attributes\r
///\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
-#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
\r
///\r
/// Cache Type Structure cache attributes\r
///\r
typedef struct {\r
- UINT8 AllocationType:2;\r
- UINT8 CacheType:2;\r
- UINT8 WritePolicy:1;\r
- UINT8 Reserved:3;\r
+ UINT8 AllocationType : 2;\r
+ UINT8 CacheType : 2;\r
+ UINT8 WritePolicy : 1;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\r
\r
///\r
/// Cache Type Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
- UINT32 NextLevelOfCache;\r
- UINT32 Size;\r
- UINT32 NumberOfSets;\r
- UINT8 Associativity;\r
- EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
- UINT16 LineSize;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
+ UINT32 NextLevelOfCache;\r
+ UINT32 Size;\r
+ UINT32 NumberOfSets;\r
+ UINT8 Associativity;\r
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
+ UINT16 LineSize;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;\r
\r
///\r
/// ID structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 VendorId;\r
- UINT64 Level1Id;\r
- UINT64 Level2Id;\r
- UINT16 MajorRev;\r
- UINT16 MinorRev;\r
- UINT16 SpinRev;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 VendorId;\r
+ UINT64 Level1Id;\r
+ UINT64 Level2Id;\r
+ UINT16 MajorRev;\r
+ UINT16 MinorRev;\r
+ UINT16 SpinRev;\r
} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;\r
\r
//\r
/// ACPI 6.3 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2\r
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.3) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_3_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x03\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_3_8042 BIT1\r
-#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_3_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_3_8042 BIT1\r
+#define EFI_ACPI_6_3_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_3_WBINVD BIT0\r
-#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_3_PROC_C1 BIT2\r
-#define EFI_ACPI_6_3_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_3_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_3_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_3_FIX_RTC BIT6\r
-#define EFI_ACPI_6_3_RTC_S4 BIT7\r
-#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_3_DCK_CAP BIT9\r
-#define EFI_ACPI_6_3_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_3_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_3_HEADLESS BIT12\r
-#define EFI_ACPI_6_3_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_3_WBINVD BIT0\r
+#define EFI_ACPI_6_3_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_3_PROC_C1 BIT2\r
+#define EFI_ACPI_6_3_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_3_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_3_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_3_FIX_RTC BIT6\r
+#define EFI_ACPI_6_3_RTC_S4 BIT7\r
+#define EFI_ACPI_6_3_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_3_DCK_CAP BIT9\r
+#define EFI_ACPI_6_3_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_3_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_3_HEADLESS BIT12\r
+#define EFI_ACPI_6_3_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_3_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_3_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_3_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_3_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_3_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\r
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_3_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_3_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_3_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2;\r
- UINT16 SpeOverflowInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2;\r
+ UINT16 SpeOverflowInterrupt;\r
} EFI_ACPI_6_3_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_3_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_3_GIC_V1 0x01\r
-#define EFI_ACPI_6_3_GIC_V2 0x02\r
-#define EFI_ACPI_6_3_GIC_V3 0x03\r
-#define EFI_ACPI_6_3_GIC_V4 0x04\r
+#define EFI_ACPI_6_3_GIC_V1 0x01\r
+#define EFI_ACPI_6_3_GIC_V2 0x02\r
+#define EFI_ACPI_6_3_GIC_V3 0x03\r
+#define EFI_ACPI_6_3_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_3_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_3_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_3_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)\r
\r
///\r
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT8 Reserved[2];\r
- UINT32 ItsId;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT8 Reserved[2];\r
+ UINT32 ItsId;\r
} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;\r
\r
//\r
// All other values between 0x02 an 0xFF are reserved and\r
// will be ignored by OSPM.\r
//\r
-#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00\r
-#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01\r
+#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE 0x00\r
+#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE 0x01\r
\r
///\r
/// Device Handle - ACPI\r
///\r
typedef struct {\r
- UINT64 AcpiHid;\r
- UINT32 AcpiUid;\r
- UINT8 Reserved[4];\r
+ UINT64 AcpiHid;\r
+ UINT32 AcpiUid;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;\r
\r
///\r
/// Device Handle - PCI\r
///\r
typedef struct {\r
- UINT16 PciSegment;\r
- UINT16 PciBdfNumber;\r
- UINT8 Reserved[12];\r
+ UINT16 PciSegment;\r
+ UINT16 PciBdfNumber;\r
+ UINT8 Reserved[12];\r
} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;\r
\r
///\r
/// Generic Initiator Affinity Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1;\r
- UINT8 DeviceHandleType;\r
- UINT32 ProximityDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1;\r
+ UINT8 DeviceHandleType;\r
+ UINT32 ProximityDomain;\r
\r
union {\r
- EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;\r
- EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;\r
+ EFI_ACPI_6_3_DEVICE_HANDLE_ACPI Acpi;\r
+ EFI_ACPI_6_3_DEVICE_HANDLE_PCI Pci;\r
} DeviceHandle;\r
\r
- UINT32 Flags;\r
- UINT8 Reserved2[4];\r
+ UINT32 Flags;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;\r
\r
///\r
/// Generic Initiator Affinity Structure Flags. All other bits are reserved\r
/// and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)\r
\r
///\r
/// System Locality Distance Information Table (SLIT).\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_3_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI RASF Platform RAS Capabilities\r
///\r
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
-#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01\r
\r
///\r
/// Common Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Memory Aggregator Device Type\r
///\r
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM 0x2\r
\r
///\r
/// Socket Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE MemoryController[];\r
} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// MemoryController Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT32 ReadLatency;\r
- UINT32 WriteLatency;\r
- UINT32 ReadBandwidth;\r
- UINT32 WriteBandwidth;\r
- UINT16 OptimalAccessUnit;\r
- UINT16 OptimalAccessAlignment;\r
- UINT16 Reserved;\r
- UINT16 NumberOfProximityDomains;\r
-//UINT32 ProximityDomain[NumberOfProximityDomains];\r
-//EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT32 ReadLatency;\r
+ UINT32 WriteLatency;\r
+ UINT32 ReadBandwidth;\r
+ UINT32 WriteBandwidth;\r
+ UINT16 OptimalAccessUnit;\r
+ UINT16 OptimalAccessAlignment;\r
+ UINT16 Reserved;\r
+ UINT16 NumberOfProximityDomains;\r
+ // UINT32 ProximityDomain[NumberOfProximityDomains];\r
+ // EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE PhysicalComponent[];\r
} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// DIMM Memory Aggregator Device Structure.\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
- UINT16 PhysicalComponentIdentifier;\r
- UINT16 Reserved;\r
- UINT32 SizeOfDimm;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE Header;\r
+ UINT16 PhysicalComponentIdentifier;\r
+ UINT16 Reserved;\r
+ UINT32 SizeOfDimm;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:1] = Reserved (must be zero)\r
/// Bit [0] = Valid. A one indicates the boot image graphic is valid.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_3_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_3_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior towhen the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
- UINT32 VirtualPL2TimerGSIV;\r
- UINT32 VirtualPL2TimerFlags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
+ UINT32 VirtualPL2TimerGSIV;\r
+ UINT32 VirtualPL2TimerFlags;\r
} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\r
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// SBSA Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// SBSA Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.3 spec.)\r
//\r
-#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
//\r
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
-#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
-#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
-#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
-#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
-#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
+#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
+#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
+#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
+#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
+#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
\r
//\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS BIT5\r
#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NVDIMMPhysicalID;\r
- UINT16 NVDIMMRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 NVDIMMRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 NVDIMMPhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 NVDIMMStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NVDIMMPhysicalID;\r
+ UINT16 NVDIMMRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 NVDIMMRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 NVDIMMPhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 NVDIMMStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
-\r
-#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 ValidFields;\r
- UINT8 ManufacturingLocation;\r
- UINT16 ManufacturingDate;\r
- UINT8 Reserved_22[2];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
+\r
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 ValidFields;\r
+ UINT8 ManufacturingLocation;\r
+ UINT16 ManufacturingDate;\r
+ UINT8 Reserved_22[2];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_3_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Secure DEVices Table (SDEV)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;\r
\r
///\r
/// SDEV Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION 0x01\r
\r
///\r
/// Secure Devcice types\r
///\r
-#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
-#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
+#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
+#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
\r
///\r
/// Secure Devcice flags\r
///\r
-#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
+#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
\r
///\r
/// SDEV Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;\r
\r
///\r
/// PCIe Endpoint Device based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 PciSegmentNumber;\r
- UINT16 StartBusNumber;\r
- UINT16 PciPathOffset;\r
- UINT16 PciPathLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 PciSegmentNumber;\r
+ UINT16 StartBusNumber;\r
+ UINT16 PciPathOffset;\r
+ UINT16 PciPathLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\r
\r
///\r
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
- UINT16 DeviceIdentifierOffset;\r
- UINT16 DeviceIdentifierLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
+ UINT16 DeviceIdentifierOffset;\r
+ UINT16 DeviceIdentifierLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
- UINT8 Timestamp[8];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
+ UINT8 Timestamp[8];\r
} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
-#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
-#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Version 2 Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
- UINT64 ReadAckPreserve;\r
- UINT64 ReadAckWrite;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
+ UINT64 ReadAckPreserve;\r
+ UINT64 ReadAckWrite;\r
} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_3_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
UINT8 NumberOfHardwareBanks;\r
UINT8 Reserved1[3];\r
-} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;\r
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// HMAT - Heterogeneous Memory Attribute Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[4];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\r
\r
///\r
/// HMAT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\r
\r
///\r
/// HMAT types\r
///\r
-#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\r
-#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
-#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\r
+#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
\r
///\r
/// HMAT Structure Header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;\r
\r
///\r
/// Memory Proximity Domain Attributes Structure flags\r
///\r
typedef struct {\r
- UINT16 InitiatorProximityDomainValid:1;\r
- UINT16 Reserved:15;\r
+ UINT16 InitiatorProximityDomainValid : 1;\r
+ UINT16 Reserved : 15;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;\r
\r
///\r
/// Memory Proximity Domain Attributes Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\r
- UINT8 Reserved1[2];\r
- UINT32 InitiatorProximityDomain;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved2[20];\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\r
+ UINT8 Reserved1[2];\r
+ UINT32 InitiatorProximityDomain;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved2[20];\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure flags\r
///\r
typedef struct {\r
- UINT8 MemoryHierarchy:4;\r
- UINT8 Reserved:4;\r
+ UINT8 MemoryHierarchy : 4;\r
+ UINT8 Reserved : 4;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
- UINT8 DataType;\r
- UINT8 Reserved1[2];\r
- UINT32 NumberOfInitiatorProximityDomains;\r
- UINT32 NumberOfTargetProximityDomains;\r
- UINT8 Reserved2[4];\r
- UINT64 EntryBaseUnit;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
+ UINT8 DataType;\r
+ UINT8 Reserved1[2];\r
+ UINT32 NumberOfInitiatorProximityDomains;\r
+ UINT32 NumberOfTargetProximityDomains;\r
+ UINT8 Reserved2[4];\r
+ UINT64 EntryBaseUnit;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\r
\r
///\r
/// Memory Side Cache Information Structure cache attributes\r
///\r
typedef struct {\r
- UINT32 TotalCacheLevels:4;\r
- UINT32 CacheLevel:4;\r
- UINT32 CacheAssociativity:4;\r
- UINT32 WritePolicy:4;\r
- UINT32 CacheLineSize:16;\r
+ UINT32 TotalCacheLevels : 4;\r
+ UINT32 CacheLevel : 4;\r
+ UINT32 CacheAssociativity : 4;\r
+ UINT32 WritePolicy : 4;\r
+ UINT32 CacheLineSize : 16;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\r
\r
///\r
/// Memory Side Cache Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved1[4];\r
- UINT64 MemorySideCacheSize;\r
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
- UINT8 Reserved2[2];\r
- UINT16 NumberOfSmbiosHandles;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved1[4];\r
+ UINT64 MemorySideCacheSize;\r
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
+ UINT8 Reserved2[2];\r
+ UINT16 NumberOfSmbiosHandles;\r
} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
-#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
+#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_3_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_3_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_3_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_3_ERST_ADD 0x08\r
-#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_3_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_3_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_3_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_3_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_3_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_3_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_3_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_3_ERST_ADD 0x08\r
+#define EFI_ACPI_6_3_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_3_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_3_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_3_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_3_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_3_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_3_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_3_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
\r
///\r
/// PCCT Global Flags\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 NotifyOnCompletion:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 NotifyOnCompletion : 1;\r
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 PlatformInterrupt:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 PlatformInterrupt : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckWrite;\r
} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 3 Extended PCC Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT32 AddressLength;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT32 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckSet;\r
- UINT8 Reserved1[8];\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
- UINT64 CommandCompleteCheckMask;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
- UINT64 CommandCompleteUpdatePreserve;\r
- UINT64 CommandCompleteUpdateSet;\r
- EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
- UINT64 ErrorStatusMask;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT32 AddressLength;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT32 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckSet;\r
+ UINT8 Reserved1[8];\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
+ UINT64 CommandCompleteCheckMask;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
+ UINT64 CommandCompleteUpdatePreserve;\r
+ UINT64 CommandCompleteUpdateSet;\r
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
+ UINT64 ErrorStatusMask;\r
} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;\r
\r
///\r
///\r
typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;\r
\r
-#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
+#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Flags;\r
- UINT32 Length;\r
- UINT32 Command;\r
+ UINT32 Signature;\r
+ UINT32 Flags;\r
+ UINT32 Length;\r
+ UINT32 Command;\r
} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\r
\r
///\r
/// Platform Debug Trigger Table (PDTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 TriggerCount;\r
- UINT8 Reserved[3];\r
- UINT32 TriggerIdentifierArrayOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 TriggerCount;\r
+ UINT8 Reserved[3];\r
+ UINT32 TriggerIdentifierArrayOffset;\r
} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\r
\r
///\r
/// PDTT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
\r
///\r
/// PDTT Platform Communication Channel Identifier Structure\r
///\r
typedef struct {\r
- UINT16 SubChannelIdentifer:8;\r
- UINT16 Runtime:1;\r
- UINT16 WaitForCompletion:1;\r
- UINT16 TriggerOrder:1;\r
- UINT16 Reserved:5;\r
+ UINT16 SubChannelIdentifer : 8;\r
+ UINT16 Runtime : 1;\r
+ UINT16 WaitForCompletion : 1;\r
+ UINT16 TriggerOrder : 1;\r
+ UINT16 Reserved : 5;\r
} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;\r
\r
///\r
/// PCC Commands Codes used by Platform Debug Trigger Table\r
///\r
-#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
-#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
\r
///\r
/// PPTT Platform Communication Channel\r
/// Processor Properties Topology Table (PPTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\r
\r
///\r
/// PPTT Revision (as defined in ACPI 6.3 spec.)\r
///\r
-#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02\r
\r
///\r
/// PPTT types\r
///\r
-#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00\r
-#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01\r
-#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02\r
+#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR 0x00\r
+#define EFI_ACPI_6_3_PPTT_TYPE_CACHE 0x01\r
+#define EFI_ACPI_6_3_PPTT_TYPE_ID 0x02\r
\r
///\r
/// PPTT Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;\r
\r
///\r
/// Processor hierarchy node structure flags\r
///\r
typedef struct {\r
- UINT32 PhysicalPackage:1;\r
- UINT32 AcpiProcessorIdValid:1;\r
- UINT32 ProcessorIsAThread:1;\r
- UINT32 NodeIsALeaf:1;\r
- UINT32 IdenticalImplementation:1;\r
- UINT32 Reserved:27;\r
+ UINT32 PhysicalPackage : 1;\r
+ UINT32 AcpiProcessorIdValid : 1;\r
+ UINT32 ProcessorIsAThread : 1;\r
+ UINT32 NodeIsALeaf : 1;\r
+ UINT32 IdenticalImplementation : 1;\r
+ UINT32 Reserved : 27;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;\r
\r
///\r
/// Processor hierarchy node structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
- UINT32 Parent;\r
- UINT32 AcpiProcessorId;\r
- UINT32 NumberOfPrivateResources;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
+ UINT32 Parent;\r
+ UINT32 AcpiProcessorId;\r
+ UINT32 NumberOfPrivateResources;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;\r
\r
///\r
/// For PPTT struct cache flags\r
///\r
-#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1\r
-#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0\r
-#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID 0x1\r
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID 0x0\r
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID 0x1\r
\r
///\r
/// Cache Type Structure flags\r
///\r
typedef struct {\r
- UINT32 SizePropertyValid:1;\r
- UINT32 NumberOfSetsValid:1;\r
- UINT32 AssociativityValid:1;\r
- UINT32 AllocationTypeValid:1;\r
- UINT32 CacheTypeValid:1;\r
- UINT32 WritePolicyValid:1;\r
- UINT32 LineSizeValid:1;\r
- UINT32 Reserved:25;\r
+ UINT32 SizePropertyValid : 1;\r
+ UINT32 NumberOfSetsValid : 1;\r
+ UINT32 AssociativityValid : 1;\r
+ UINT32 AllocationTypeValid : 1;\r
+ UINT32 CacheTypeValid : 1;\r
+ UINT32 WritePolicyValid : 1;\r
+ UINT32 LineSizeValid : 1;\r
+ UINT32 Reserved : 25;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;\r
\r
///\r
/// For cache attributes\r
///\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
-#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
\r
///\r
/// Cache Type Structure cache attributes\r
///\r
typedef struct {\r
- UINT8 AllocationType:2;\r
- UINT8 CacheType:2;\r
- UINT8 WritePolicy:1;\r
- UINT8 Reserved:3;\r
+ UINT8 AllocationType : 2;\r
+ UINT8 CacheType : 2;\r
+ UINT8 WritePolicy : 1;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\r
\r
///\r
/// Cache Type Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
- UINT32 NextLevelOfCache;\r
- UINT32 Size;\r
- UINT32 NumberOfSets;\r
- UINT8 Associativity;\r
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
- UINT16 LineSize;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
+ UINT32 NextLevelOfCache;\r
+ UINT32 Size;\r
+ UINT32 NumberOfSets;\r
+ UINT8 Associativity;\r
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
+ UINT16 LineSize;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;\r
\r
///\r
/// ID structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 VendorId;\r
- UINT64 Level1Id;\r
- UINT64 Level2Id;\r
- UINT16 MajorRev;\r
- UINT16 MinorRev;\r
- UINT16 SpinRev;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 VendorId;\r
+ UINT64 Level1Id;\r
+ UINT64 Level2Id;\r
+ UINT16 MajorRev;\r
+ UINT16 MinorRev;\r
+ UINT16 SpinRev;\r
} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;\r
\r
//\r
/// ACPI 6.4 Generic Address Space definition\r
///\r
typedef struct {\r
- UINT8 AddressSpaceId;\r
- UINT8 RegisterBitWidth;\r
- UINT8 RegisterBitOffset;\r
- UINT8 AccessSize;\r
- UINT64 Address;\r
+ UINT8 AddressSpaceId;\r
+ UINT8 RegisterBitWidth;\r
+ UINT8 RegisterBitOffset;\r
+ UINT8 AccessSize;\r
+ UINT64 Address;\r
} EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE;\r
\r
//\r
/// Root System Description Pointer Structure\r
///\r
typedef struct {\r
- UINT64 Signature;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT8 Revision;\r
- UINT32 RsdtAddress;\r
- UINT32 Length;\r
- UINT64 XsdtAddress;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved[3];\r
+ UINT64 Signature;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT8 Revision;\r
+ UINT32 RsdtAddress;\r
+ UINT32 Length;\r
+ UINT64 XsdtAddress;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER;\r
\r
///\r
/// RSD_PTR Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2\r
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02 ///< ACPISpec (Revision 6.4) says current value is 2\r
\r
///\r
/// Common table header, this prefaces all ACPI tables, including FACS, but\r
/// excluding the RSD PTR structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_4_COMMON_HEADER;\r
\r
//\r
///\r
/// RSDT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
//\r
// Extended System Description Table\r
///\r
/// XSDT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Fixed ACPI Description Table Structure (FADT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 FirmwareCtrl;\r
- UINT32 Dsdt;\r
- UINT8 Reserved0;\r
- UINT8 PreferredPmProfile;\r
- UINT16 SciInt;\r
- UINT32 SmiCmd;\r
- UINT8 AcpiEnable;\r
- UINT8 AcpiDisable;\r
- UINT8 S4BiosReq;\r
- UINT8 PstateCnt;\r
- UINT32 Pm1aEvtBlk;\r
- UINT32 Pm1bEvtBlk;\r
- UINT32 Pm1aCntBlk;\r
- UINT32 Pm1bCntBlk;\r
- UINT32 Pm2CntBlk;\r
- UINT32 PmTmrBlk;\r
- UINT32 Gpe0Blk;\r
- UINT32 Gpe1Blk;\r
- UINT8 Pm1EvtLen;\r
- UINT8 Pm1CntLen;\r
- UINT8 Pm2CntLen;\r
- UINT8 PmTmrLen;\r
- UINT8 Gpe0BlkLen;\r
- UINT8 Gpe1BlkLen;\r
- UINT8 Gpe1Base;\r
- UINT8 CstCnt;\r
- UINT16 PLvl2Lat;\r
- UINT16 PLvl3Lat;\r
- UINT16 FlushSize;\r
- UINT16 FlushStride;\r
- UINT8 DutyOffset;\r
- UINT8 DutyWidth;\r
- UINT8 DayAlrm;\r
- UINT8 MonAlrm;\r
- UINT8 Century;\r
- UINT16 IaPcBootArch;\r
- UINT8 Reserved1;\r
- UINT32 Flags;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
- UINT8 ResetValue;\r
- UINT16 ArmBootArch;\r
- UINT8 MinorVersion;\r
- UINT64 XFirmwareCtrl;\r
- UINT64 XDsdt;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
- UINT64 HypervisorVendorIdentity;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 FirmwareCtrl;\r
+ UINT32 Dsdt;\r
+ UINT8 Reserved0;\r
+ UINT8 PreferredPmProfile;\r
+ UINT16 SciInt;\r
+ UINT32 SmiCmd;\r
+ UINT8 AcpiEnable;\r
+ UINT8 AcpiDisable;\r
+ UINT8 S4BiosReq;\r
+ UINT8 PstateCnt;\r
+ UINT32 Pm1aEvtBlk;\r
+ UINT32 Pm1bEvtBlk;\r
+ UINT32 Pm1aCntBlk;\r
+ UINT32 Pm1bCntBlk;\r
+ UINT32 Pm2CntBlk;\r
+ UINT32 PmTmrBlk;\r
+ UINT32 Gpe0Blk;\r
+ UINT32 Gpe1Blk;\r
+ UINT8 Pm1EvtLen;\r
+ UINT8 Pm1CntLen;\r
+ UINT8 Pm2CntLen;\r
+ UINT8 PmTmrLen;\r
+ UINT8 Gpe0BlkLen;\r
+ UINT8 Gpe1BlkLen;\r
+ UINT8 Gpe1Base;\r
+ UINT8 CstCnt;\r
+ UINT16 PLvl2Lat;\r
+ UINT16 PLvl3Lat;\r
+ UINT16 FlushSize;\r
+ UINT16 FlushStride;\r
+ UINT8 DutyOffset;\r
+ UINT8 DutyWidth;\r
+ UINT8 DayAlrm;\r
+ UINT8 MonAlrm;\r
+ UINT8 Century;\r
+ UINT16 IaPcBootArch;\r
+ UINT8 Reserved1;\r
+ UINT32 Flags;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ResetReg;\r
+ UINT8 ResetValue;\r
+ UINT16 ArmBootArch;\r
+ UINT8 MinorVersion;\r
+ UINT64 XFirmwareCtrl;\r
+ UINT64 XDsdt;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe0Blk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE XGpe1Blk;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepControlReg;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE SleepStatusReg;\r
+ UINT64 HypervisorVendorIdentity;\r
} EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE;\r
\r
///\r
/// FADT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
+#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x06\r
#define EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION 0x04\r
\r
//\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0\r
-#define EFI_ACPI_6_4_8042 BIT1\r
-#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2\r
-#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3\r
-#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4\r
-#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5\r
+#define EFI_ACPI_6_4_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_6_4_8042 BIT1\r
+#define EFI_ACPI_6_4_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_6_4_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_6_4_PCIE_ASPM_CONTROLS BIT4\r
+#define EFI_ACPI_6_4_CMOS_RTC_NOT_PRESENT BIT5\r
\r
//\r
// Fixed ACPI Description Table Arm Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0\r
-#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1\r
+#define EFI_ACPI_6_4_ARM_PSCI_COMPLIANT BIT0\r
+#define EFI_ACPI_6_4_ARM_PSCI_USE_HVC BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_6_4_WBINVD BIT0\r
-#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1\r
-#define EFI_ACPI_6_4_PROC_C1 BIT2\r
-#define EFI_ACPI_6_4_P_LVL2_UP BIT3\r
-#define EFI_ACPI_6_4_PWR_BUTTON BIT4\r
-#define EFI_ACPI_6_4_SLP_BUTTON BIT5\r
-#define EFI_ACPI_6_4_FIX_RTC BIT6\r
-#define EFI_ACPI_6_4_RTC_S4 BIT7\r
-#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8\r
-#define EFI_ACPI_6_4_DCK_CAP BIT9\r
-#define EFI_ACPI_6_4_RESET_REG_SUP BIT10\r
-#define EFI_ACPI_6_4_SEALED_CASE BIT11\r
-#define EFI_ACPI_6_4_HEADLESS BIT12\r
-#define EFI_ACPI_6_4_CPU_SW_SLP BIT13\r
-#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14\r
-#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15\r
-#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16\r
-#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17\r
-#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18\r
-#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
-#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20\r
-#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
+#define EFI_ACPI_6_4_WBINVD BIT0\r
+#define EFI_ACPI_6_4_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_6_4_PROC_C1 BIT2\r
+#define EFI_ACPI_6_4_P_LVL2_UP BIT3\r
+#define EFI_ACPI_6_4_PWR_BUTTON BIT4\r
+#define EFI_ACPI_6_4_SLP_BUTTON BIT5\r
+#define EFI_ACPI_6_4_FIX_RTC BIT6\r
+#define EFI_ACPI_6_4_RTC_S4 BIT7\r
+#define EFI_ACPI_6_4_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_6_4_DCK_CAP BIT9\r
+#define EFI_ACPI_6_4_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_6_4_SEALED_CASE BIT11\r
+#define EFI_ACPI_6_4_HEADLESS BIT12\r
+#define EFI_ACPI_6_4_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_6_4_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_6_4_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_6_4_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_6_4_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_6_4_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_6_4_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
+#define EFI_ACPI_6_4_HW_REDUCED_ACPI BIT20\r
+#define EFI_ACPI_6_4_LOW_POWER_S0_IDLE_CAPABLE BIT21\r
\r
///\r
/// Firmware ACPI Control Structure\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT32 HardwareSignature;\r
- UINT32 FirmwareWakingVector;\r
- UINT32 GlobalLock;\r
- UINT32 Flags;\r
- UINT64 XFirmwareWakingVector;\r
- UINT8 Version;\r
- UINT8 Reserved0[3];\r
- UINT32 OspmFlags;\r
- UINT8 Reserved1[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT32 HardwareSignature;\r
+ UINT32 FirmwareWakingVector;\r
+ UINT32 GlobalLock;\r
+ UINT32 Flags;\r
+ UINT64 XFirmwareWakingVector;\r
+ UINT8 Version;\r
+ UINT8 Reserved0[3];\r
+ UINT32 OspmFlags;\r
+ UINT8 Reserved1[24];\r
} EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE;\r
\r
///\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_4_S4BIOS_F BIT0\r
-#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1\r
+#define EFI_ACPI_6_4_S4BIOS_F BIT0\r
+#define EFI_ACPI_6_4_64BIT_WAKE_SUPPORTED_F BIT1\r
\r
///\r
/// OSPM Enabled Firmware Control Structure Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0\r
+#define EFI_ACPI_6_4_OSPM_64BIT_WAKE_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
// no definition needed as they are common description table header, the same with\r
// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.\r
//\r
-#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
-#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_4_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_4_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION 0x02\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 LocalApicAddress;\r
- UINT32 Flags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 LocalApicAddress;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;\r
\r
///\r
/// MADT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\r
+#define EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05\r
\r
///\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_4_PCAT_COMPAT BIT0\r
+#define EFI_ACPI_6_4_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
/// Processor Local APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE;\r
\r
///\r
/// IO APIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 IoApicAddress;\r
- UINT32 GlobalSystemInterruptBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalSystemInterruptBase;\r
} EFI_ACPI_6_4_IO_APIC_STRUCTURE;\r
\r
///\r
/// Interrupt Source Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Bus;\r
- UINT8 Source;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT16 Flags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Bus;\r
+ UINT8 Source;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT16 Flags;\r
} EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
- UINT8 CpeiProcessorOverride;\r
- UINT8 Reserved[31];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 CpeiProcessorOverride;\r
+ UINT8 Reserved[31];\r
} EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE;\r
\r
//\r
/// Non-Maskable Interrupt Source Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
///\r
/// Local APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorUid;\r
- UINT16 Flags;\r
- UINT8 LocalApicLint;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorUid;\r
+ UINT16 Flags;\r
+ UINT8 LocalApicLint;\r
} EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE;\r
\r
///\r
/// Local APIC Address Override Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 LocalApicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 LocalApicAddress;\r
} EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
///\r
/// IO SAPIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 IoApicId;\r
- UINT8 Reserved;\r
- UINT32 GlobalSystemInterruptBase;\r
- UINT64 IoSapicAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 IoApicId;\r
+ UINT8 Reserved;\r
+ UINT32 GlobalSystemInterruptBase;\r
+ UINT64 IoSapicAddress;\r
} EFI_ACPI_6_4_IO_SAPIC_STRUCTURE;\r
\r
///\r
/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 AcpiProcessorId;\r
- UINT8 LocalSapicId;\r
- UINT8 LocalSapicEid;\r
- UINT8 Reserved[3];\r
- UINT32 Flags;\r
- UINT32 ACPIProcessorUIDValue;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 AcpiProcessorId;\r
+ UINT8 LocalSapicId;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 Reserved[3];\r
+ UINT32 Flags;\r
+ UINT32 ACPIProcessorUIDValue;\r
} EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Sources Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT8 InterruptType;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT8 IoSapicVector;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT32 PlatformInterruptSourceFlags;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT8 InterruptType;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT8 IoSapicVector;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT32 PlatformInterruptSourceFlags;\r
} EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;\r
\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0\r
+#define EFI_ACPI_6_4_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Processor Local x2APIC Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 AcpiProcessorUid;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 AcpiProcessorUid;\r
} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE;\r
\r
///\r
/// Local x2APIC NMI Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Flags;\r
- UINT32 AcpiProcessorUid;\r
- UINT8 LocalX2ApicLint;\r
- UINT8 Reserved[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Flags;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT8 LocalX2ApicLint;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE;\r
\r
///\r
/// GIC Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 CPUInterfaceNumber;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ParkingProtocolVersion;\r
- UINT32 PerformanceInterruptGsiv;\r
- UINT64 ParkedAddress;\r
- UINT64 PhysicalBaseAddress;\r
- UINT64 GICV;\r
- UINT64 GICH;\r
- UINT32 VGICMaintenanceInterrupt;\r
- UINT64 GICRBaseAddress;\r
- UINT64 MPIDR;\r
- UINT8 ProcessorPowerEfficiencyClass;\r
- UINT8 Reserved2;\r
- UINT16 SpeOverflowInterrupt;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 CPUInterfaceNumber;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ParkingProtocolVersion;\r
+ UINT32 PerformanceInterruptGsiv;\r
+ UINT64 ParkedAddress;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT64 GICV;\r
+ UINT64 GICH;\r
+ UINT32 VGICMaintenanceInterrupt;\r
+ UINT64 GICRBaseAddress;\r
+ UINT64 MPIDR;\r
+ UINT8 ProcessorPowerEfficiencyClass;\r
+ UINT8 Reserved2;\r
+ UINT16 SpeOverflowInterrupt;\r
} EFI_ACPI_6_4_GIC_STRUCTURE;\r
\r
///\r
/// GIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GIC_ENABLED BIT0\r
-#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1\r
-#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
+#define EFI_ACPI_6_4_GIC_ENABLED BIT0\r
+#define EFI_ACPI_6_4_PERFORMANCE_INTERRUPT_MODEL BIT1\r
+#define EFI_ACPI_6_4_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS BIT2\r
\r
///\r
/// GIC Distributor Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 SystemVectorBase;\r
- UINT8 GicVersion;\r
- UINT8 Reserved2[3];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 SystemVectorBase;\r
+ UINT8 GicVersion;\r
+ UINT8 Reserved2[3];\r
} EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE;\r
\r
///\r
/// GIC Version\r
///\r
-#define EFI_ACPI_6_4_GIC_V1 0x01\r
-#define EFI_ACPI_6_4_GIC_V2 0x02\r
-#define EFI_ACPI_6_4_GIC_V3 0x03\r
-#define EFI_ACPI_6_4_GIC_V4 0x04\r
+#define EFI_ACPI_6_4_GIC_V1 0x01\r
+#define EFI_ACPI_6_4_GIC_V2 0x02\r
+#define EFI_ACPI_6_4_GIC_V3 0x03\r
+#define EFI_ACPI_6_4_GIC_V4 0x04\r
\r
///\r
/// GIC MSI Frame Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved1;\r
- UINT32 GicMsiFrameId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Flags;\r
- UINT16 SPICount;\r
- UINT16 SPIBase;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved1;\r
+ UINT32 GicMsiFrameId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Flags;\r
+ UINT16 SPICount;\r
+ UINT16 SPIBase;\r
} EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE;\r
\r
///\r
/// GIC MSI Frame Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0\r
+#define EFI_ACPI_6_4_SPI_COUNT_BASE_SELECT BIT0\r
\r
///\r
/// GICR Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT64 DiscoveryRangeBaseAddress;\r
- UINT32 DiscoveryRangeLength;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT64 DiscoveryRangeBaseAddress;\r
+ UINT32 DiscoveryRangeLength;\r
} EFI_ACPI_6_4_GICR_STRUCTURE;\r
\r
///\r
/// GIC Interrupt Translation Service Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved;\r
- UINT32 GicItsId;\r
- UINT64 PhysicalBaseAddress;\r
- UINT32 Reserved2;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved;\r
+ UINT32 GicItsId;\r
+ UINT64 PhysicalBaseAddress;\r
+ UINT32 Reserved2;\r
} EFI_ACPI_6_4_GIC_ITS_STRUCTURE;\r
\r
///\r
/// Multiprocessor Wakeup Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 MailBoxVersion;\r
- UINT32 Reserved;\r
- UINT64 MailBoxAddress;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 MailBoxVersion;\r
+ UINT32 Reserved;\r
+ UINT64 MailBoxAddress;\r
} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE;\r
\r
///\r
/// Multiprocessor Wakeup Mailbox Structure\r
///\r
typedef struct {\r
- UINT16 Command;\r
- UINT16 Reserved;\r
- UINT32 AcpiId;\r
- UINT64 WakeupVector;\r
- UINT8 ReservedForOs[2032];\r
- UINT8 ReservedForFirmware[2048];\r
+ UINT16 Command;\r
+ UINT16 Reserved;\r
+ UINT32 AcpiId;\r
+ UINT64 WakeupVector;\r
+ UINT8 ReservedForOs[2032];\r
+ UINT8 ReservedForFirmware[2048];\r
} EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE;\r
\r
-#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000\r
-#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001\r
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_NOOP 0x0000\r
+#define EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_COMMAND_WAKEUP 0x0001\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WarningEnergyLevel;\r
- UINT32 LowEnergyLevel;\r
- UINT32 CriticalEnergyLevel;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WarningEnergyLevel;\r
+ UINT32 LowEnergyLevel;\r
+ UINT32 CriticalEnergyLevel;\r
} EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE;\r
\r
///\r
/// SBST Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01\r
\r
///\r
/// Embedded Controller Boot Resources Table (ECDT)\r
/// a fully qualified reference to the name space object.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;\r
- UINT32 Uid;\r
- UINT8 GpeBit;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcControl;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EcData;\r
+ UINT32 Uid;\r
+ UINT8 GpeBit;\r
} EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; ///< Must be set to 1\r
- UINT64 Reserved2;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Reserved1; ///< Must be set to 1\r
+ UINT64 Reserved2;\r
} EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
/// Processor Local APIC/SAPIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProximityDomain7To0;\r
- UINT8 ApicId;\r
- UINT32 Flags;\r
- UINT8 LocalSapicEid;\r
- UINT8 ProximityDomain31To8[3];\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProximityDomain7To0;\r
+ UINT8 ApicId;\r
+ UINT32 Flags;\r
+ UINT8 LocalSapicEid;\r
+ UINT8 ProximityDomain31To8[3];\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// Local APIC/SAPIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
///\r
/// Memory Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT16 Reserved1;\r
- UINT32 AddressBaseLow;\r
- UINT32 AddressBaseHigh;\r
- UINT32 LengthLow;\r
- UINT32 LengthHigh;\r
- UINT32 Reserved2;\r
- UINT32 Flags;\r
- UINT64 Reserved3;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT16 Reserved1;\r
+ UINT32 AddressBaseLow;\r
+ UINT32 AddressBaseHigh;\r
+ UINT32 LengthLow;\r
+ UINT32 LengthHigh;\r
+ UINT32 Reserved2;\r
+ UINT32 Flags;\r
+ UINT64 Reserved3;\r
} EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE;\r
\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
-#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)\r
-#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)\r
-#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)\r
+#define EFI_ACPI_6_4_MEMORY_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_4_MEMORY_HOT_PLUGGABLE (1 << 1)\r
+#define EFI_ACPI_6_4_MEMORY_NONVOLATILE (1 << 2)\r
\r
///\r
/// Processor Local x2APIC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1[2];\r
- UINT32 ProximityDomain;\r
- UINT32 X2ApicId;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1[2];\r
+ UINT32 ProximityDomain;\r
+ UINT32 X2ApicId;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT32 AcpiProcessorUid;\r
- UINT32 Flags;\r
- UINT32 ClockDomain;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT32 AcpiProcessorUid;\r
+ UINT32 Flags;\r
+ UINT32 ClockDomain;\r
} EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE;\r
\r
///\r
/// GICC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)\r
+#define EFI_ACPI_6_4_GICC_ENABLED (1 << 0)\r
\r
///\r
/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 ProximityDomain;\r
- UINT8 Reserved[2];\r
- UINT32 ItsId;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomain;\r
+ UINT8 Reserved[2];\r
+ UINT32 ItsId;\r
} EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE;\r
\r
//\r
// All other values between 0x02 an 0xFF are reserved and\r
// will be ignored by OSPM.\r
//\r
-#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00\r
-#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01\r
+#define EFI_ACPI_6_4_ACPI_DEVICE_HANDLE 0x00\r
+#define EFI_ACPI_6_4_PCI_DEVICE_HANDLE 0x01\r
\r
///\r
/// Device Handle - ACPI\r
///\r
typedef struct {\r
- UINT64 AcpiHid;\r
- UINT32 AcpiUid;\r
- UINT8 Reserved[4];\r
+ UINT64 AcpiHid;\r
+ UINT32 AcpiUid;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_4_DEVICE_HANDLE_ACPI;\r
\r
///\r
/// Device Handle - PCI\r
///\r
typedef struct {\r
- UINT16 PciSegment;\r
- UINT16 PciBdfNumber;\r
- UINT8 Reserved[12];\r
+ UINT16 PciSegment;\r
+ UINT16 PciBdfNumber;\r
+ UINT8 Reserved[12];\r
} EFI_ACPI_6_4_DEVICE_HANDLE_PCI;\r
\r
///\r
/// Device Handle\r
///\r
typedef union {\r
- EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;\r
- EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;\r
+ EFI_ACPI_6_4_DEVICE_HANDLE_ACPI Acpi;\r
+ EFI_ACPI_6_4_DEVICE_HANDLE_PCI Pci;\r
} EFI_ACPI_6_4_DEVICE_HANDLE;\r
\r
///\r
/// Generic Initiator Affinity Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved1;\r
- UINT8 DeviceHandleType;\r
- UINT32 ProximityDomain;\r
- EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;\r
- UINT32 Flags;\r
- UINT8 Reserved2[4];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved1;\r
+ UINT8 DeviceHandleType;\r
+ UINT32 ProximityDomain;\r
+ EFI_ACPI_6_4_DEVICE_HANDLE DeviceHandle;\r
+ UINT32 Flags;\r
+ UINT8 Reserved2[4];\r
} EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE;\r
\r
///\r
/// The rest of the table is a matrix.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 NumberOfSystemLocalities;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 NumberOfSystemLocalities;\r
} EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;\r
\r
///\r
/// Corrected Platform Error Polling Table (CPEP)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[8];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[8];\r
} EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;\r
\r
///\r
/// CPEP Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01\r
\r
//\r
// CPEP processor structure types.\r
/// Corrected Platform Error Polling Processor Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 ProcessorId;\r
- UINT8 ProcessorEid;\r
- UINT32 PollingInterval;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 ProcessorId;\r
+ UINT8 ProcessorEid;\r
+ UINT32 PollingInterval;\r
} EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;\r
\r
///\r
/// Maximum System Characteristics Table (MSCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetProxDomInfo;\r
- UINT32 MaximumNumberOfProximityDomains;\r
- UINT32 MaximumNumberOfClockDomains;\r
- UINT64 MaximumPhysicalAddress;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetProxDomInfo;\r
+ UINT32 MaximumNumberOfProximityDomains;\r
+ UINT32 MaximumNumberOfClockDomains;\r
+ UINT64 MaximumPhysicalAddress;\r
} EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;\r
\r
///\r
/// MSCT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01\r
\r
///\r
/// Maximum Proximity Domain Information Structure Definition\r
///\r
typedef struct {\r
- UINT8 Revision;\r
- UINT8 Length;\r
- UINT32 ProximityDomainRangeLow;\r
- UINT32 ProximityDomainRangeHigh;\r
- UINT32 MaximumProcessorCapacity;\r
- UINT64 MaximumMemoryCapacity;\r
+ UINT8 Revision;\r
+ UINT8 Length;\r
+ UINT32 ProximityDomainRangeLow;\r
+ UINT32 ProximityDomainRangeHigh;\r
+ UINT32 MaximumProcessorCapacity;\r
+ UINT64 MaximumMemoryCapacity;\r
} EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;\r
\r
///\r
/// ACPI RAS Feature Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier[12];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier[12];\r
} EFI_ACPI_6_4_RAS_FEATURE_TABLE;\r
\r
///\r
/// RASF Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_RAS_FEATURE_TABLE_REVISION 0x01\r
\r
///\r
/// ACPI RASF Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT16 Version;\r
- UINT8 RASCapabilities[16];\r
- UINT8 SetRASCapabilities[16];\r
- UINT16 NumberOfRASFParameterBlocks;\r
- UINT32 SetRASCapabilitiesStatus;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 Version;\r
+ UINT8 RASCapabilities[16];\r
+ UINT8 SetRASCapabilities[16];\r
+ UINT16 NumberOfRASFParameterBlocks;\r
+ UINT32 SetRASCapabilitiesStatus;\r
} EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI RASF Platform RAS Capabilities\r
///\r
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
-#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED BIT0\r
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1\r
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT2\r
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS BIT3\r
+#define EFI_ACPI_6_4_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING BIT4\r
\r
///\r
/// ACPI RASF Parameter Block structure for PATROL_SCRUB\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 PatrolScrubCommand;\r
- UINT64 RequestedAddressRange[2];\r
- UINT64 ActualAddressRange[2];\r
- UINT16 Flags;\r
- UINT8 RequestedSpeed;\r
+ UINT16 Type;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 PatrolScrubCommand;\r
+ UINT64 RequestedAddressRange[2];\r
+ UINT64 ActualAddressRange[2];\r
+ UINT16 Flags;\r
+ UINT8 RequestedSpeed;\r
} EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;\r
\r
///\r
/// ACPI RASF Patrol Scrub command\r
///\r
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
-#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS 0x01\r
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER 0x02\r
+#define EFI_ACPI_6_4_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER 0x03\r
\r
///\r
/// Memory Power State Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 PlatformCommunicationChannelIdentifier;\r
- UINT8 Reserved[3];\r
-// Memory Power Node Structure\r
-// Memory Power State Characteristics\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 PlatformCommunicationChannelIdentifier;\r
+ UINT8 Reserved[3];\r
+ // Memory Power Node Structure\r
+ // Memory Power State Characteristics\r
} EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE;\r
\r
///\r
/// MPST Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_MEMORY_POWER_STATE_TABLE_REVISION 0x01\r
\r
///\r
/// MPST Platform Communication Channel Shared Memory Region definition.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT32 MemoryPowerCommandRegister;\r
- UINT32 MemoryPowerStatusRegister;\r
- UINT32 PowerStateId;\r
- UINT32 MemoryPowerNodeId;\r
- UINT64 MemoryEnergyConsumed;\r
- UINT64 ExpectedAveragePowerComsuned;\r
+ UINT32 Signature;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT32 MemoryPowerCommandRegister;\r
+ UINT32 MemoryPowerStatusRegister;\r
+ UINT32 PowerStateId;\r
+ UINT32 MemoryPowerNodeId;\r
+ UINT64 MemoryEnergyConsumed;\r
+ UINT64 ExpectedAveragePowerComsuned;\r
} EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;\r
\r
///\r
///\r
/// ACPI MPST Memory Power command\r
///\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE 0x01\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE 0x02\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED 0x03\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED 0x04\r
\r
///\r
/// MPST Memory Power Node Table\r
///\r
typedef struct {\r
- UINT8 PowerStateValue;\r
- UINT8 PowerStateInformationIndex;\r
+ UINT8 PowerStateValue;\r
+ UINT8 PowerStateInformationIndex;\r
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE;\r
\r
typedef struct {\r
- UINT8 Flag;\r
- UINT8 Reserved;\r
- UINT16 MemoryPowerNodeId;\r
- UINT32 Length;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
- UINT32 NumberOfPowerStates;\r
- UINT32 NumberOfPhysicalComponents;\r
-//EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
-//UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
+ UINT8 Flag;\r
+ UINT8 Reserved;\r
+ UINT16 MemoryPowerNodeId;\r
+ UINT32 Length;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
+ UINT32 NumberOfPowerStates;\r
+ UINT32 NumberOfPhysicalComponents;\r
+ // EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE MemoryPowerState[NumberOfPowerStates];\r
+ // UINT16 PhysicalComponentIdentifier[NumberOfPhysicalComponents];\r
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE;\r
\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE 0x01\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED 0x02\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerNodeCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerNodeCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE;\r
\r
///\r
/// MPST Memory Power State Characteristics Table\r
///\r
typedef struct {\r
- UINT8 PowerStateStructureID;\r
- UINT8 Flag;\r
- UINT16 Reserved;\r
- UINT32 AveragePowerConsumedInMPS0;\r
- UINT32 RelativePowerSavingToMPS0;\r
- UINT64 ExitLatencyToMPS0;\r
+ UINT8 PowerStateStructureID;\r
+ UINT8 Flag;\r
+ UINT16 Reserved;\r
+ UINT32 AveragePowerConsumedInMPS0;\r
+ UINT32 RelativePowerSavingToMPS0;\r
+ UINT64 ExitLatencyToMPS0;\r
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;\r
\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
-#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED 0x01\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY 0x02\r
+#define EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT 0x04\r
\r
typedef struct {\r
- UINT16 MemoryPowerStateCharacteristicsCount;\r
- UINT8 Reserved[2];\r
+ UINT16 MemoryPowerStateCharacteristicsCount;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;\r
\r
///\r
/// Platform Memory Topology Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 NumberOfMemoryDevices;\r
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 NumberOfMemoryDevices;\r
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\r
} EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE;\r
\r
///\r
/// PMTT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_4_MEMORY_TOPOLOGY_TABLE_REVISION 0x02\r
\r
///\r
/// Common Memory Device.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 Length;\r
- UINT16 Flags;\r
- UINT16 Reserved1;\r
- UINT32 NumberOfMemoryDevices;\r
-//UINT8 TypeSpecificData[];\r
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 Length;\r
+ UINT16 Flags;\r
+ UINT16 Reserved1;\r
+ UINT32 NumberOfMemoryDevices;\r
+ // UINT8 TypeSpecificData[];\r
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[NumberOfMemoryDevices];\r
} EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE;\r
\r
///\r
/// Memory Device Type.\r
///\r
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0\r
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2\r
-#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF\r
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_SOCKET 0x0\r
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_MEMORY_CONTROLLER 0x1\r
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_DIMM 0x2\r
+#define EFI_ACPI_6_4_PMTT_MEMORY_DEVICE_TYPE_VENDOR_SPECIFIC_TYPE 0xFF\r
\r
///\r
/// Socket Type Data.\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
- UINT16 SocketIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
+ UINT16 SocketIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
} EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA;\r
\r
///\r
/// Memory Controller Type Data.\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
- UINT16 MemoryControllerIdentifier;\r
- UINT16 Reserved;\r
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
+ UINT16 MemoryControllerIdentifier;\r
+ UINT16 Reserved;\r
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
} EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA;\r
\r
///\r
/// DIMM Type Specific Data.\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
- UINT32 SmbiosHandle;\r
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
+ UINT32 SmbiosHandle;\r
} EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA;\r
\r
///\r
/// Vendor Specific Type Data.\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
- UINT8 TypeUuid[16];\r
-//EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];\r
-//EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
+ EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE CommonMemoryDeviceHeader;\r
+ UINT8 TypeUuid[16];\r
+ // EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA VendorSpecificData[];\r
+ // EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE MemoryDeviceStructure[];\r
} EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA;\r
\r
///\r
/// Boot Graphics Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// 2-bytes (16 bit) version ID. This value must be 1.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// 1-byte status field indicating current status about the table.\r
/// Bits[7:3] = Reserved (must be zero)\r
/// Bit [0] = Displayed. A one indicates the boot image graphic is\r
/// displayed.\r
///\r
- UINT8 Status;\r
+ UINT8 Status;\r
///\r
/// 1-byte enumerated type field indicating format of the image.\r
/// 0 = Bitmap\r
/// 1 - 255 Reserved (for future use)\r
///\r
- UINT8 ImageType;\r
+ UINT8 ImageType;\r
///\r
/// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy\r
/// of the image bitmap.\r
///\r
- UINT64 ImageAddress;\r
+ UINT64 ImageAddress;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetX;\r
+ UINT32 ImageOffsetX;\r
///\r
/// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.\r
/// (X, Y) display offset of the top left corner of the boot image.\r
/// The top left corner of the display is at offset (0, 0).\r
///\r
- UINT32 ImageOffsetY;\r
+ UINT32 ImageOffsetY;\r
} EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE;\r
\r
///\r
/// BGRT Revision\r
///\r
-#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
+#define EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1\r
\r
///\r
/// BGRT Version\r
///\r
-#define EFI_ACPI_6_4_BGRT_VERSION 0x01\r
+#define EFI_ACPI_6_4_BGRT_VERSION 0x01\r
\r
///\r
/// BGRT Status\r
///\r
-#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00\r
-#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01\r
+#define EFI_ACPI_6_4_BGRT_STATUS_NOT_DISPLAYED 0x00\r
+#define EFI_ACPI_6_4_BGRT_STATUS_DISPLAYED 0x01\r
\r
///\r
/// BGRT Image Type\r
///\r
/// FPDT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01\r
\r
///\r
/// FPDT Performance Record Types\r
///\r
-#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
-#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER 0x0000\r
+#define EFI_ACPI_6_4_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER 0x0001\r
\r
///\r
/// FPDT Performance Record Revision\r
///\r
-#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
-#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER 0x01\r
+#define EFI_ACPI_6_4_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01\r
\r
///\r
/// FPDT Runtime Performance Record Types\r
///\r
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
-#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME 0x0000\r
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND 0x0001\r
+#define EFI_ACPI_6_4_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT 0x0002\r
\r
///\r
/// FPDT Runtime Performance Record Revision\r
/// FPDT Performance Record header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Length;\r
- UINT8 Revision;\r
+ UINT16 Type;\r
+ UINT8 Length;\r
+ UINT8 Revision;\r
} EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER;\r
\r
///\r
/// FPDT Performance Table header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
} EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the Basic Boot Performance Table.\r
///\r
- UINT64 BootPerformanceTablePointer;\r
+ UINT64 BootPerformanceTablePointer;\r
} EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT S3 Performance Table Pointer Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// 64-bit processor-relative physical address of the S3 Performance Table.\r
///\r
- UINT64 S3PerformanceTablePointer;\r
+ UINT64 S3PerformanceTablePointer;\r
} EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;\r
\r
///\r
/// FPDT Firmware Basic Boot Performance Record Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
- UINT32 Reserved;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ UINT32 Reserved;\r
///\r
/// Timer value logged at the beginning of firmware image execution.\r
/// This may not always be zero or near zero.\r
///\r
- UINT64 ResetEnd;\r
+ UINT64 ResetEnd;\r
///\r
/// Timer value logged just prior to loading the OS boot loader into memory.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 OsLoaderLoadImageStart;\r
+ UINT64 OsLoaderLoadImageStart;\r
///\r
/// Timer value logged just prior to launching the previously loaded OS boot loader image.\r
/// For non-UEFI compatible boots, the timer value logged will be just prior\r
/// to the INT 19h handler invocation.\r
///\r
- UINT64 OsLoaderStartImageStart;\r
+ UINT64 OsLoaderStartImageStart;\r
///\r
/// Timer value logged at the point when the OS loader calls the\r
/// ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesEntry;\r
+ UINT64 ExitBootServicesEntry;\r
///\r
/// Timer value logged at the point just prior towhen the OS loader gaining\r
/// control back from calls the ExitBootServices function for UEFI compatible firmware.\r
/// For non-UEFI compatible boots, this field must be zero.\r
///\r
- UINT64 ExitBootServicesExit;\r
+ UINT64 ExitBootServicesExit;\r
} EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD;\r
\r
///\r
// FPDT Firmware Basic Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
// FPDT Firmware S3 Boot Performance Table\r
//\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER Header;\r
//\r
// one or more Performance Records.\r
//\r
/// FPDT Basic S3 Resume Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// A count of the number of S3 resume cycles since the last full boot sequence.\r
///\r
- UINT32 ResumeCount;\r
+ UINT32 ResumeCount;\r
///\r
/// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the\r
/// OS waking vector. Only the most recent resume cycle's time is retained.\r
///\r
- UINT64 FullResume;\r
+ UINT64 FullResume;\r
///\r
/// Average timer value of all resume cycles logged since the last full boot\r
/// sequence, including the most recent resume. Note that the entire log of\r
/// timer values does not need to be retained in order to calculate this average.\r
///\r
- UINT64 AverageResume;\r
+ UINT64 AverageResume;\r
} EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD;\r
\r
///\r
/// FPDT Basic S3 Suspend Performance Record\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
+ EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER Header;\r
///\r
/// Timer value recorded at the OS write to SLP_TYP upon entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendStart;\r
+ UINT64 SuspendStart;\r
///\r
/// Timer value recorded at the final firmware write to SLP_TYP (or other\r
/// mechanism) used to trigger hardware entry to S3.\r
/// Only the most recent suspend cycle's timer value is retained.\r
///\r
- UINT64 SuspendEnd;\r
+ UINT64 SuspendEnd;\r
} EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD;\r
\r
///\r
/// Firmware Performance Record Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE;\r
\r
///\r
/// Generic Timer Description Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 CntControlBasePhysicalAddress;\r
- UINT32 Reserved;\r
- UINT32 SecurePL1TimerGSIV;\r
- UINT32 SecurePL1TimerFlags;\r
- UINT32 NonSecurePL1TimerGSIV;\r
- UINT32 NonSecurePL1TimerFlags;\r
- UINT32 VirtualTimerGSIV;\r
- UINT32 VirtualTimerFlags;\r
- UINT32 NonSecurePL2TimerGSIV;\r
- UINT32 NonSecurePL2TimerFlags;\r
- UINT64 CntReadBasePhysicalAddress;\r
- UINT32 PlatformTimerCount;\r
- UINT32 PlatformTimerOffset;\r
- UINT32 VirtualPL2TimerGSIV;\r
- UINT32 VirtualPL2TimerFlags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 CntControlBasePhysicalAddress;\r
+ UINT32 Reserved;\r
+ UINT32 SecurePL1TimerGSIV;\r
+ UINT32 SecurePL1TimerFlags;\r
+ UINT32 NonSecurePL1TimerGSIV;\r
+ UINT32 NonSecurePL1TimerFlags;\r
+ UINT32 VirtualTimerGSIV;\r
+ UINT32 VirtualTimerFlags;\r
+ UINT32 NonSecurePL2TimerGSIV;\r
+ UINT32 NonSecurePL2TimerFlags;\r
+ UINT64 CntReadBasePhysicalAddress;\r
+ UINT32 PlatformTimerCount;\r
+ UINT32 PlatformTimerOffset;\r
+ UINT32 VirtualPL2TimerGSIV;\r
+ UINT32 VirtualPL2TimerFlags;\r
} EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE;\r
\r
///\r
/// GTDT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\r
+#define EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03\r
\r
///\r
/// Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_4_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY BIT2\r
\r
///\r
/// Platform Timer Type\r
///\r
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0\r
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1\r
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK 0\r
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG 1\r
\r
///\r
/// GT Block Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 CntCtlBase;\r
- UINT32 GTBlockTimerCount;\r
- UINT32 GTBlockTimerOffset;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 CntCtlBase;\r
+ UINT32 GTBlockTimerCount;\r
+ UINT32 GTBlockTimerOffset;\r
} EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE;\r
\r
///\r
/// GT Block Timer Structure\r
///\r
typedef struct {\r
- UINT8 GTFrameNumber;\r
- UINT8 Reserved[3];\r
- UINT64 CntBaseX;\r
- UINT64 CntEL0BaseX;\r
- UINT32 GTxPhysicalTimerGSIV;\r
- UINT32 GTxPhysicalTimerFlags;\r
- UINT32 GTxVirtualTimerGSIV;\r
- UINT32 GTxVirtualTimerFlags;\r
- UINT32 GTxCommonFlags;\r
+ UINT8 GTFrameNumber;\r
+ UINT8 Reserved[3];\r
+ UINT64 CntBaseX;\r
+ UINT64 CntEL0BaseX;\r
+ UINT32 GTxPhysicalTimerGSIV;\r
+ UINT32 GTxPhysicalTimerFlags;\r
+ UINT32 GTxVirtualTimerGSIV;\r
+ UINT32 GTxVirtualTimerFlags;\r
+ UINT32 GTxCommonFlags;\r
} EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE;\r
\r
///\r
/// GT Block Physical Timers and Virtual Timers Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
\r
///\r
/// Common Flags Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
-#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER BIT0\r
+#define EFI_ACPI_6_4_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY BIT1\r
\r
///\r
/// Arm Generic Watchdog Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Reserved;\r
- UINT64 RefreshFramePhysicalAddress;\r
- UINT64 WatchdogControlFramePhysicalAddress;\r
- UINT32 WatchdogTimerGSIV;\r
- UINT32 WatchdogTimerFlags;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Reserved;\r
+ UINT64 RefreshFramePhysicalAddress;\r
+ UINT64 WatchdogControlFramePhysicalAddress;\r
+ UINT32 WatchdogTimerGSIV;\r
+ UINT32 WatchdogTimerFlags;\r
} EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE;\r
\r
///\r
/// Arm Generic Watchdog Timer Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
-#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE BIT0\r
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY BIT1\r
+#define EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_FLAG_SECURE_TIMER BIT2\r
\r
//\r
// NVDIMM Firmware Interface Table definition.\r
//\r
// NFIT Version (as defined in ACPI 6.4 spec.)\r
//\r
-#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
+#define EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1\r
\r
//\r
// Definition for NFIT Table Structure Types\r
//\r
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
-#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
-#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
-#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
-#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
-#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE 0\r
+#define EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE 1\r
+#define EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE_TYPE 2\r
+#define EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE 3\r
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE 4\r
+#define EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE 5\r
+#define EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE 6\r
\r
//\r
// Definition for NFIT Structure Header\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER;\r
\r
//\r
// Definition for System Physical Address Range Structure\r
//\r
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
-#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2\r
-\r
-#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
-#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
-\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 SPARangeStructureIndex;\r
- UINT16 Flags;\r
- UINT32 Reserved_8;\r
- UINT32 ProximityDomain;\r
- GUID AddressRangeTypeGUID;\r
- UINT64 SystemPhysicalAddressRangeBase;\r
- UINT64 SystemPhysicalAddressRangeLength;\r
- UINT64 AddressRangeMemoryMappingAttribute;\r
- UINT64 SPALocationCookie;\r
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT BIT0\r
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID BIT1\r
+#define EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_SPA_LOCATION_COOKIE_VALID BIT2\r
+\r
+#define EFI_ACPI_6_4_NFIT_GUID_VOLATILE_MEMORY_REGION { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_CONTROL_REGION { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}\r
+#define EFI_ACPI_6_4_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}\r
+\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 Flags;\r
+ UINT32 Reserved_8;\r
+ UINT32 ProximityDomain;\r
+ GUID AddressRangeTypeGUID;\r
+ UINT64 SystemPhysicalAddressRangeBase;\r
+ UINT64 SystemPhysicalAddressRangeLength;\r
+ UINT64 AddressRangeMemoryMappingAttribute;\r
+ UINT64 SPALocationCookie;\r
} EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;\r
\r
//\r
// Definition for Memory Device to System Physical Address Range Mapping Structure\r
//\r
typedef struct {\r
- UINT32 DIMMNumber:4;\r
- UINT32 MemoryChannelNumber:4;\r
- UINT32 MemoryControllerID:4;\r
- UINT32 SocketID:4;\r
- UINT32 NodeControllerID:12;\r
- UINT32 Reserved_28:4;\r
+ UINT32 DIMMNumber : 4;\r
+ UINT32 MemoryChannelNumber : 4;\r
+ UINT32 MemoryControllerID : 4;\r
+ UINT32 SocketID : 4;\r
+ UINT32 NodeControllerID : 12;\r
+ UINT32 Reserved_28 : 4;\r
} EFI_ACPI_6_4_NFIT_DEVICE_HANDLE;\r
\r
#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL BIT0\r
#define EFI_ACPI_6_4_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA BIT6\r
\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NVDIMMPhysicalID;\r
- UINT16 NVDIMMRegionID;\r
- UINT16 SPARangeStructureIndex ;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT64 NVDIMMRegionSize;\r
- UINT64 RegionOffset;\r
- UINT64 NVDIMMPhysicalAddressRegionBase;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 InterleaveWays;\r
- UINT16 NVDIMMStateFlags;\r
- UINT16 Reserved_46;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NVDIMMPhysicalID;\r
+ UINT16 NVDIMMRegionID;\r
+ UINT16 SPARangeStructureIndex;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT64 NVDIMMRegionSize;\r
+ UINT64 RegionOffset;\r
+ UINT64 NVDIMMPhysicalAddressRegionBase;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 InterleaveWays;\r
+ UINT16 NVDIMMStateFlags;\r
+ UINT16 Reserved_46;\r
} EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;\r
\r
//\r
// Definition for Interleave Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 InterleaveStructureIndex;\r
- UINT16 Reserved_6;\r
- UINT32 NumberOfLines;\r
- UINT32 LineSize;\r
-//UINT32 LineOffset[NumberOfLines];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 InterleaveStructureIndex;\r
+ UINT16 Reserved_6;\r
+ UINT32 NumberOfLines;\r
+ UINT32 LineSize;\r
+ // UINT32 LineOffset[NumberOfLines];\r
} EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE;\r
\r
//\r
// Definition for SMBIOS Management Information Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT32 Reserved_4;\r
-//UINT8 Data[];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT32 Reserved_4;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Control Region Structure\r
//\r
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
-\r
-#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
-\r
-typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 VendorID;\r
- UINT16 DeviceID;\r
- UINT16 RevisionID;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemDeviceID;\r
- UINT16 SubsystemRevisionID;\r
- UINT8 ValidFields;\r
- UINT8 ManufacturingLocation;\r
- UINT16 ManufacturingDate;\r
- UINT8 Reserved_22[2];\r
- UINT32 SerialNumber;\r
- UINT16 RegionFormatInterfaceCode;\r
- UINT16 NumberOfBlockControlWindows;\r
- UINT64 SizeOfBlockControlWindow;\r
- UINT64 CommandRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
- UINT64 StatusRegisterOffsetInBlockControlWindow;\r
- UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
- UINT16 NVDIMMControlRegionFlag;\r
- UINT8 Reserved_74[6];\r
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING BIT0\r
+\r
+#define EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED BIT0\r
+\r
+typedef struct {\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevisionID;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemDeviceID;\r
+ UINT16 SubsystemRevisionID;\r
+ UINT8 ValidFields;\r
+ UINT8 ManufacturingLocation;\r
+ UINT16 ManufacturingDate;\r
+ UINT8 Reserved_22[2];\r
+ UINT32 SerialNumber;\r
+ UINT16 RegionFormatInterfaceCode;\r
+ UINT16 NumberOfBlockControlWindows;\r
+ UINT64 SizeOfBlockControlWindow;\r
+ UINT64 CommandRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfCommandRegisterInBlockControlWindows;\r
+ UINT64 StatusRegisterOffsetInBlockControlWindow;\r
+ UINT64 SizeOfStatusRegisterInBlockControlWindows;\r
+ UINT16 NVDIMMControlRegionFlag;\r
+ UINT8 Reserved_74[6];\r
} EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;\r
\r
//\r
// Definition for NVDIMM Block Data Window Region Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- UINT16 NVDIMMControlRegionStructureIndex;\r
- UINT16 NumberOfBlockDataWindows;\r
- UINT64 BlockDataWindowStartOffset;\r
- UINT64 SizeOfBlockDataWindow;\r
- UINT64 BlockAccessibleMemoryCapacity;\r
- UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ UINT16 NVDIMMControlRegionStructureIndex;\r
+ UINT16 NumberOfBlockDataWindows;\r
+ UINT64 BlockDataWindowStartOffset;\r
+ UINT64 SizeOfBlockDataWindow;\r
+ UINT64 BlockAccessibleMemoryCapacity;\r
+ UINT64 BeginningAddressOfFirstBlockInBlockAccessibleMemory;\r
} EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;\r
\r
//\r
// Definition for Flush Hint Address Structure\r
//\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
- EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
- UINT16 NumberOfFlushHintAddresses;\r
- UINT8 Reserved_10[6];\r
-//UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
+ UINT16 Type;\r
+ UINT16 Length;\r
+ EFI_ACPI_6_4_NFIT_DEVICE_HANDLE NFITDeviceHandle;\r
+ UINT16 NumberOfFlushHintAddresses;\r
+ UINT8 Reserved_10[6];\r
+ // UINT64 FlushHintAddress[NumberOfFlushHintAddresses];\r
} EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;\r
\r
///\r
/// Secure DEVices Table (SDEV)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER;\r
\r
///\r
/// SDEV Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_SECURE_DEVICES_TABLE_REVISION 0x01\r
\r
///\r
/// Secure Device types\r
///\r
-#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
-#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
+#define EFI_ACPI_6_4_SDEV_TYPE_ACPI_NAMESPACE_DEVICE 0x00\r
+#define EFI_ACPI_6_4_SDEV_TYPE_PCIE_ENDPOINT_DEVICE 0x01\r
\r
///\r
/// Secure Device flags\r
///\r
-#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
-#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1\r
+#define EFI_ACPI_6_4_SDEV_FLAG_ALLOW_HANDOFF BIT0\r
+#define EFI_ACPI_6_4_SDEV_FLAG_SECURE_ACCESS_COMPONENTS_PRESENT BIT1\r
\r
///\r
/// SDEV Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Flags;\r
- UINT16 Length;\r
+ UINT8 Type;\r
+ UINT8 Flags;\r
+ UINT16 Length;\r
} EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER;\r
\r
///\r
/// ACPI_NAMESPACE_DEVICE based Secure Device Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
- UINT16 DeviceIdentifierOffset;\r
- UINT16 DeviceIdentifierLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
- UINT16 SecureAccessComponentsOffset;\r
- UINT16 SecureAccessComponentsLength;\r
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
+ UINT16 DeviceIdentifierOffset;\r
+ UINT16 DeviceIdentifierLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
+ UINT16 SecureAccessComponentsOffset;\r
+ UINT16 SecureAccessComponentsLength;\r
} EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;\r
\r
///\r
/// Secure Access Component Types\r
///\r
-#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00\r
-#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01\r
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_IDENTIFICATION 0x00\r
+#define EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_TYPE_MEMORY 0x01\r
\r
///\r
/// Identification Based Secure Access Component\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
- UINT16 HardwareIdentifierOffset;\r
- UINT16 HardwareIdentifierLength;\r
- UINT16 SubsystemIdentifierOffset;\r
- UINT16 SubsystemIdentifierLength;\r
- UINT16 HardwareRevision;\r
- UINT8 HardwareRevisionPresent;\r
- UINT8 ClassCodePresent;\r
- UINT8 PciCompatibleBaseClass;\r
- UINT8 PciCompatibleSubClass;\r
- UINT8 PciCompatibleProgrammingInterface;\r
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
+ UINT16 HardwareIdentifierOffset;\r
+ UINT16 HardwareIdentifierLength;\r
+ UINT16 SubsystemIdentifierOffset;\r
+ UINT16 SubsystemIdentifierLength;\r
+ UINT16 HardwareRevision;\r
+ UINT8 HardwareRevisionPresent;\r
+ UINT8 ClassCodePresent;\r
+ UINT8 PciCompatibleBaseClass;\r
+ UINT8 PciCompatibleSubClass;\r
+ UINT8 PciCompatibleProgrammingInterface;\r
} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE;\r
\r
///\r
/// Memory-based Secure Access Component\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
- UINT32 Reserved;\r
- UINT64 MemoryAddressBase;\r
- UINT64 MemoryLength;\r
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
+ UINT32 Reserved;\r
+ UINT64 MemoryAddressBase;\r
+ UINT64 MemoryLength;\r
} EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE;\r
\r
///\r
/// PCIe Endpoint Device based Secure Device Structure\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
- UINT16 PciSegmentNumber;\r
- UINT16 StartBusNumber;\r
- UINT16 PciPathOffset;\r
- UINT16 PciPathLength;\r
- UINT16 VendorSpecificDataOffset;\r
- UINT16 VendorSpecificDataLength;\r
+ EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER Header;\r
+ UINT16 PciSegmentNumber;\r
+ UINT16 StartBusNumber;\r
+ UINT16 PciPathOffset;\r
+ UINT16 PciPathLength;\r
+ UINT16 VendorSpecificDataOffset;\r
+ UINT16 VendorSpecificDataLength;\r
} EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;\r
\r
///\r
/// Boot Error Record Table (BERT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 BootErrorRegionLength;\r
- UINT64 BootErrorRegion;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 BootErrorRegionLength;\r
+ UINT64 BootErrorRegion;\r
} EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER;\r
\r
///\r
/// BERT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_REVISION 0x01\r
\r
///\r
/// Boot Error Region Block Status Definition\r
///\r
typedef struct {\r
- UINT32 UncorrectableErrorValid:1;\r
- UINT32 CorrectableErrorValid:1;\r
- UINT32 MultipleUncorrectableErrors:1;\r
- UINT32 MultipleCorrectableErrors:1;\r
- UINT32 ErrorDataEntryCount:10;\r
- UINT32 Reserved:18;\r
+ UINT32 UncorrectableErrorValid : 1;\r
+ UINT32 CorrectableErrorValid : 1;\r
+ UINT32 MultipleUncorrectableErrors : 1;\r
+ UINT32 MultipleCorrectableErrors : 1;\r
+ UINT32 ErrorDataEntryCount : 10;\r
+ UINT32 Reserved : 18;\r
} EFI_ACPI_6_4_ERROR_BLOCK_STATUS;\r
\r
///\r
/// Boot Error Region Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE;\r
\r
//\r
/// Generic Error Data Entry Definition\r
///\r
typedef struct {\r
- UINT8 SectionType[16];\r
- UINT32 ErrorSeverity;\r
- UINT16 Revision;\r
- UINT8 ValidationBits;\r
- UINT8 Flags;\r
- UINT32 ErrorDataLength;\r
- UINT8 FruId[16];\r
- UINT8 FruText[20];\r
- UINT8 Timestamp[8];\r
+ UINT8 SectionType[16];\r
+ UINT32 ErrorSeverity;\r
+ UINT16 Revision;\r
+ UINT8 ValidationBits;\r
+ UINT8 Flags;\r
+ UINT32 ErrorDataLength;\r
+ UINT8 FruId[16];\r
+ UINT8 FruText[20];\r
+ UINT8 Timestamp[8];\r
} EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;\r
\r
///\r
/// HEST - Hardware Error Source Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ErrorSourceCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ErrorSourceCount;\r
} EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER;\r
\r
///\r
/// HEST Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01\r
\r
//\r
// Error Source structure types.\r
//\r
// Error Source structure flags.\r
//\r
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
-#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_FIRMWARE_FIRST (1 << 0)\r
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GLOBAL (1 << 1)\r
+#define EFI_ACPI_6_4_ERROR_SOURCE_FLAG_GHES_ASSIST (1 << 2)\r
\r
///\r
/// IA-32 Architecture Machine Check Exception Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT64 GlobalCapabilityInitData;\r
- UINT64 GlobalControlInitData;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[7];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT64 GlobalCapabilityInitData;\r
+ UINT64 GlobalControlInitData;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[7];\r
} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure Definition\r
///\r
typedef struct {\r
- UINT8 BankNumber;\r
- UINT8 ClearStatusOnInitialization;\r
- UINT8 StatusDataFormat;\r
- UINT8 Reserved0;\r
- UINT32 ControlRegisterMsrAddress;\r
- UINT64 ControlInitData;\r
- UINT32 StatusRegisterMsrAddress;\r
- UINT32 AddressRegisterMsrAddress;\r
- UINT32 MiscRegisterMsrAddress;\r
+ UINT8 BankNumber;\r
+ UINT8 ClearStatusOnInitialization;\r
+ UINT8 StatusDataFormat;\r
+ UINT8 Reserved0;\r
+ UINT32 ControlRegisterMsrAddress;\r
+ UINT64 ControlInitData;\r
+ UINT32 StatusRegisterMsrAddress;\r
+ UINT32 AddressRegisterMsrAddress;\r
+ UINT32 MiscRegisterMsrAddress;\r
} EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Machine Check Bank Structure MCA data format\r
///\r
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
-#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32 0x00\r
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64 0x01\r
+#define EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64 0x02\r
\r
//\r
// Hardware Error Notification types. All other values are reserved\r
//\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
-#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_POLLED 0x00\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT 0x01\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT 0x02\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SCI 0x03\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_NMI 0x04\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CMCI 0x05\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_MCE 0x06\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL 0x07\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA 0x08\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI 0x09\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_GSIV 0x0A\r
+#define EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION 0x0B\r
\r
///\r
/// Hardware Error Notification Configuration Write Enable Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type:1;\r
- UINT16 PollInterval:1;\r
- UINT16 SwitchToPollingThresholdValue:1;\r
- UINT16 SwitchToPollingThresholdWindow:1;\r
- UINT16 ErrorThresholdValue:1;\r
- UINT16 ErrorThresholdWindow:1;\r
- UINT16 Reserved:10;\r
+ UINT16 Type : 1;\r
+ UINT16 PollInterval : 1;\r
+ UINT16 SwitchToPollingThresholdValue : 1;\r
+ UINT16 SwitchToPollingThresholdWindow : 1;\r
+ UINT16 ErrorThresholdValue : 1;\r
+ UINT16 ErrorThresholdWindow : 1;\r
+ UINT16 Reserved : 10;\r
} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;\r
\r
///\r
/// Hardware Error Notification Structure Definition\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
- UINT32 PollInterval;\r
- UINT32 Vector;\r
- UINT32 SwitchToPollingThresholdValue;\r
- UINT32 SwitchToPollingThresholdWindow;\r
- UINT32 ErrorThresholdValue;\r
- UINT32 ErrorThresholdWindow;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE ConfigurationWriteEnable;\r
+ UINT32 PollInterval;\r
+ UINT32 Vector;\r
+ UINT32 SwitchToPollingThresholdValue;\r
+ UINT32 SwitchToPollingThresholdWindow;\r
+ UINT32 ErrorThresholdValue;\r
+ UINT32 ErrorThresholdWindow;\r
} EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture Corrected Machine Check Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT8 NumberOfHardwareBanks;\r
- UINT8 Reserved1[3];\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT8 NumberOfHardwareBanks;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// IA-32 Architecture NMI Error Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
} EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;\r
\r
///\r
/// PCI Express Root Port AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 RootErrorCommand;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 RootErrorCommand;\r
} EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Device AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE;\r
\r
///\r
/// PCI Express Bridge AER Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT8 Reserved0[2];\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 Bus;\r
- UINT16 Device;\r
- UINT16 Function;\r
- UINT16 DeviceControl;\r
- UINT8 Reserved1[2];\r
- UINT32 UncorrectableErrorMask;\r
- UINT32 UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 SecondaryUncorrectableErrorMask;\r
- UINT32 SecondaryUncorrectableErrorSeverity;\r
- UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT8 Reserved0[2];\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 Bus;\r
+ UINT16 Device;\r
+ UINT16 Function;\r
+ UINT16 DeviceControl;\r
+ UINT8 Reserved1[2];\r
+ UINT32 UncorrectableErrorMask;\r
+ UINT32 UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 SecondaryUncorrectableErrorMask;\r
+ UINT32 SecondaryUncorrectableErrorSeverity;\r
+ UINT32 SecondaryAdvancedErrorCapabilitiesAndControl;\r
} EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;\r
\r
///\r
/// Generic Hardware Error Source Version 2 Structure Definition\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 SourceId;\r
- UINT16 RelatedSourceId;\r
- UINT8 Flags;\r
- UINT8 Enabled;\r
- UINT32 NumberOfRecordsToPreAllocate;\r
- UINT32 MaxSectionsPerRecord;\r
- UINT32 MaxRawDataLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
- EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
- UINT32 ErrorStatusBlockLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
- UINT64 ReadAckPreserve;\r
- UINT64 ReadAckWrite;\r
+ UINT16 Type;\r
+ UINT16 SourceId;\r
+ UINT16 RelatedSourceId;\r
+ UINT8 Flags;\r
+ UINT8 Enabled;\r
+ UINT32 NumberOfRecordsToPreAllocate;\r
+ UINT32 MaxSectionsPerRecord;\r
+ UINT32 MaxRawDataLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusAddress;\r
+ EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
+ UINT32 ErrorStatusBlockLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReadAckRegister;\r
+ UINT64 ReadAckPreserve;\r
+ UINT64 ReadAckWrite;\r
} EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;\r
\r
///\r
/// Generic Error Status Definition\r
///\r
typedef struct {\r
- EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\r
- UINT32 RawDataOffset;\r
- UINT32 RawDataLength;\r
- UINT32 DataLength;\r
- UINT32 ErrorSeverity;\r
+ EFI_ACPI_6_4_ERROR_BLOCK_STATUS BlockStatus;\r
+ UINT32 RawDataOffset;\r
+ UINT32 RawDataLength;\r
+ UINT32 DataLength;\r
+ UINT32 ErrorSeverity;\r
} EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE;\r
\r
///\r
EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE NotificationStructure;\r
UINT8 NumberOfHardwareBanks;\r
UINT8 Reserved1[3];\r
-} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;\r
+} EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;\r
\r
///\r
/// HMAT - Heterogeneous Memory Attribute Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 Reserved[4];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 Reserved[4];\r
} EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;\r
\r
///\r
/// HMAT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02\r
\r
///\r
/// HMAT types\r
///\r
-#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\r
-#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
-#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES 0x00\r
+#define EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO 0x01\r
+#define EFI_ACPI_6_4_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO 0x02\r
\r
///\r
/// HMAT Structure Header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER;\r
\r
///\r
/// Memory Proximity Domain Attributes Structure flags\r
///\r
typedef struct {\r
- UINT16 InitiatorProximityDomainValid:1;\r
- UINT16 Reserved:15;\r
+ UINT16 InitiatorProximityDomainValid : 1;\r
+ UINT16 Reserved : 15;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;\r
\r
///\r
/// Memory Proximity Domain Attributes Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\r
- UINT8 Reserved1[2];\r
- UINT32 InitiatorProximityDomain;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved2[20];\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS Flags;\r
+ UINT8 Reserved1[2];\r
+ UINT32 InitiatorProximityDomain;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved2[20];\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure flags\r
///\r
typedef struct {\r
- UINT8 MemoryHierarchy:4;\r
- UINT8 AccessAttributes:2;\r
- UINT8 Reserved:2;\r
+ UINT8 MemoryHierarchy : 4;\r
+ UINT8 AccessAttributes : 2;\r
+ UINT8 Reserved : 2;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;\r
\r
///\r
/// System Locality Latency and Bandwidth Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
- UINT8 DataType;\r
- UINT8 MinTransferSize;\r
- UINT8 Reserved1;\r
- UINT32 NumberOfInitiatorProximityDomains;\r
- UINT32 NumberOfTargetProximityDomains;\r
- UINT8 Reserved2[4];\r
- UINT64 EntryBaseUnit;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS Flags;\r
+ UINT8 DataType;\r
+ UINT8 MinTransferSize;\r
+ UINT8 Reserved1;\r
+ UINT32 NumberOfInitiatorProximityDomains;\r
+ UINT32 NumberOfTargetProximityDomains;\r
+ UINT8 Reserved2[4];\r
+ UINT64 EntryBaseUnit;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;\r
\r
///\r
/// Memory Side Cache Information Structure cache attributes\r
///\r
typedef struct {\r
- UINT32 TotalCacheLevels:4;\r
- UINT32 CacheLevel:4;\r
- UINT32 CacheAssociativity:4;\r
- UINT32 WritePolicy:4;\r
- UINT32 CacheLineSize:16;\r
+ UINT32 TotalCacheLevels : 4;\r
+ UINT32 CacheLevel : 4;\r
+ UINT32 CacheAssociativity : 4;\r
+ UINT32 WritePolicy : 4;\r
+ UINT32 CacheLineSize : 16;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;\r
\r
///\r
/// Memory Side Cache Information Structure\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT8 Reserved[2];\r
- UINT32 Length;\r
- UINT32 MemoryProximityDomain;\r
- UINT8 Reserved1[4];\r
- UINT64 MemorySideCacheSize;\r
- EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
- UINT8 Reserved2[2];\r
- UINT16 NumberOfSmbiosHandles;\r
+ UINT16 Type;\r
+ UINT8 Reserved[2];\r
+ UINT32 Length;\r
+ UINT32 MemoryProximityDomain;\r
+ UINT8 Reserved1[4];\r
+ UINT64 MemorySideCacheSize;\r
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES CacheAttributes;\r
+ UINT8 Reserved2[2];\r
+ UINT16 NumberOfSmbiosHandles;\r
} EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;\r
\r
///\r
/// ERST - Error Record Serialization Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 SerializationHeaderSize;\r
- UINT8 Reserved0[4];\r
- UINT32 InstructionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 SerializationHeaderSize;\r
+ UINT8 Reserved0[4];\r
+ UINT32 InstructionEntryCount;\r
} EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;\r
\r
///\r
/// ERST Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01\r
\r
///\r
/// ERST Serialization Actions\r
///\r
-#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00\r
-#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01\r
-#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02\r
-#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03\r
-#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04\r
-#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08\r
-#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09\r
-#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A\r
-#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
-#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
-#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
+#define EFI_ACPI_6_4_ERST_BEGIN_WRITE_OPERATION 0x00\r
+#define EFI_ACPI_6_4_ERST_BEGIN_READ_OPERATION 0x01\r
+#define EFI_ACPI_6_4_ERST_BEGIN_CLEAR_OPERATION 0x02\r
+#define EFI_ACPI_6_4_ERST_END_OPERATION 0x03\r
+#define EFI_ACPI_6_4_ERST_SET_RECORD_OFFSET 0x04\r
+#define EFI_ACPI_6_4_ERST_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_4_ERST_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_4_ERST_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_4_ERST_GET_RECORD_IDENTIFIER 0x08\r
+#define EFI_ACPI_6_4_ERST_SET_RECORD_IDENTIFIER 0x09\r
+#define EFI_ACPI_6_4_ERST_GET_RECORD_COUNT 0x0A\r
+#define EFI_ACPI_6_4_ERST_BEGIN_DUMMY_WRITE_OPERATION 0x0B\r
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE 0x0D\r
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH 0x0E\r
+#define EFI_ACPI_6_4_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES 0x0F\r
+#define EFI_ACPI_6_4_ERST_GET_EXECUTE_OPERATION_TIMINGS 0x10\r
\r
///\r
/// ERST Action Command Status\r
///\r
-#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
-#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
-#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03\r
-#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
-#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
+#define EFI_ACPI_6_4_ERST_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_4_ERST_STATUS_NOT_ENOUGH_SPACE 0x01\r
+#define EFI_ACPI_6_4_ERST_STATUS_HARDWARE_NOT_AVAILABLE 0x02\r
+#define EFI_ACPI_6_4_ERST_STATUS_FAILED 0x03\r
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_STORE_EMPTY 0x04\r
+#define EFI_ACPI_6_4_ERST_STATUS_RECORD_NOT_FOUND 0x05\r
\r
///\r
/// ERST Serialization Instructions\r
///\r
-#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_4_ERST_NOOP 0x04\r
-#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05\r
-#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06\r
-#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07\r
-#define EFI_ACPI_6_4_ERST_ADD 0x08\r
-#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09\r
-#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A\r
-#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B\r
-#define EFI_ACPI_6_4_ERST_STALL 0x0C\r
-#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D\r
-#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
-#define EFI_ACPI_6_4_ERST_GOTO 0x0F\r
-#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10\r
-#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11\r
-#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12\r
+#define EFI_ACPI_6_4_ERST_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_4_ERST_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_4_ERST_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_4_ERST_NOOP 0x04\r
+#define EFI_ACPI_6_4_ERST_LOAD_VAR1 0x05\r
+#define EFI_ACPI_6_4_ERST_LOAD_VAR2 0x06\r
+#define EFI_ACPI_6_4_ERST_STORE_VAR1 0x07\r
+#define EFI_ACPI_6_4_ERST_ADD 0x08\r
+#define EFI_ACPI_6_4_ERST_SUBTRACT 0x09\r
+#define EFI_ACPI_6_4_ERST_ADD_VALUE 0x0A\r
+#define EFI_ACPI_6_4_ERST_SUBTRACT_VALUE 0x0B\r
+#define EFI_ACPI_6_4_ERST_STALL 0x0C\r
+#define EFI_ACPI_6_4_ERST_STALL_WHILE_TRUE 0x0D\r
+#define EFI_ACPI_6_4_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE 0x0E\r
+#define EFI_ACPI_6_4_ERST_GOTO 0x0F\r
+#define EFI_ACPI_6_4_ERST_SET_SRC_ADDRESS_BASE 0x10\r
+#define EFI_ACPI_6_4_ERST_SET_DST_ADDRESS_BASE 0x11\r
+#define EFI_ACPI_6_4_ERST_MOVE_DATA 0x12\r
\r
///\r
/// ERST Instruction Flags\r
///\r
-#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_4_ERST_PRESERVE_REGISTER 0x01\r
\r
///\r
/// ERST Serialization Instruction Entry\r
///\r
typedef struct {\r
- UINT8 SerializationAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 SerializationAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ - Error Injection Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 InjectionHeaderSize;\r
- UINT8 InjectionFlags;\r
- UINT8 Reserved0[3];\r
- UINT32 InjectionEntryCount;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 InjectionHeaderSize;\r
+ UINT8 InjectionFlags;\r
+ UINT8 Reserved0[3];\r
+ UINT32 InjectionEntryCount;\r
} EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER;\r
\r
///\r
/// EINJ Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_ERROR_INJECTION_TABLE_REVISION 0x01\r
\r
///\r
/// EINJ Error Injection Actions\r
///\r
-#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
-#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
-#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02\r
-#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03\r
-#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04\r
-#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05\r
-#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06\r
-#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07\r
-#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF\r
+#define EFI_ACPI_6_4_EINJ_BEGIN_INJECTION_OPERATION 0x00\r
+#define EFI_ACPI_6_4_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE 0x01\r
+#define EFI_ACPI_6_4_EINJ_SET_ERROR_TYPE 0x02\r
+#define EFI_ACPI_6_4_EINJ_GET_ERROR_TYPE 0x03\r
+#define EFI_ACPI_6_4_EINJ_END_OPERATION 0x04\r
+#define EFI_ACPI_6_4_EINJ_EXECUTE_OPERATION 0x05\r
+#define EFI_ACPI_6_4_EINJ_CHECK_BUSY_STATUS 0x06\r
+#define EFI_ACPI_6_4_EINJ_GET_COMMAND_STATUS 0x07\r
+#define EFI_ACPI_6_4_EINJ_TRIGGER_ERROR 0xFF\r
\r
///\r
/// EINJ Action Command Status\r
///\r
-#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00\r
-#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
-#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02\r
+#define EFI_ACPI_6_4_EINJ_STATUS_SUCCESS 0x00\r
+#define EFI_ACPI_6_4_EINJ_STATUS_UNKNOWN_FAILURE 0x01\r
+#define EFI_ACPI_6_4_EINJ_STATUS_INVALID_ACCESS 0x02\r
\r
///\r
/// EINJ Error Type Definition\r
///\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
-#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_CORRECTABLE (1 << 0)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL (1 << 1)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL (1 << 2)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_CORRECTABLE (1 << 3)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL (1 << 4)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL (1 << 5)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE (1 << 6)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL (1 << 7)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL (1 << 8)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_CORRECTABLE (1 << 9)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL (1 << 10)\r
+#define EFI_ACPI_6_4_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL (1 << 11)\r
\r
///\r
/// EINJ Injection Instructions\r
///\r
-#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00\r
-#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01\r
-#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02\r
-#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03\r
-#define EFI_ACPI_6_4_EINJ_NOOP 0x04\r
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER 0x00\r
+#define EFI_ACPI_6_4_EINJ_READ_REGISTER_VALUE 0x01\r
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER 0x02\r
+#define EFI_ACPI_6_4_EINJ_WRITE_REGISTER_VALUE 0x03\r
+#define EFI_ACPI_6_4_EINJ_NOOP 0x04\r
\r
///\r
/// EINJ Instruction Flags\r
///\r
-#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01\r
+#define EFI_ACPI_6_4_EINJ_PRESERVE_REGISTER 0x01\r
\r
///\r
/// EINJ Injection Instruction Entry\r
///\r
typedef struct {\r
- UINT8 InjectionAction;\r
- UINT8 Instruction;\r
- UINT8 Flags;\r
- UINT8 Reserved0;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT64 Value;\r
- UINT64 Mask;\r
+ UINT8 InjectionAction;\r
+ UINT8 Instruction;\r
+ UINT8 Flags;\r
+ UINT8 Reserved0;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT64 Value;\r
+ UINT64 Mask;\r
} EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY;\r
\r
///\r
/// EINJ Trigger Action Table\r
///\r
typedef struct {\r
- UINT32 HeaderSize;\r
- UINT32 Revision;\r
- UINT32 TableSize;\r
- UINT32 EntryCount;\r
+ UINT32 HeaderSize;\r
+ UINT32 Revision;\r
+ UINT32 TableSize;\r
+ UINT32 EntryCount;\r
} EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE;\r
\r
///\r
/// Platform Communications Channel Table (PCCT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Flags;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 Flags;\r
+ UINT64 Reserved;\r
} EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;\r
\r
///\r
/// PCCT Version (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
+#define EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02\r
\r
///\r
/// PCCT Global Flags\r
//\r
// PCCT Subspace type\r
//\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_GENERIC 0x00\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS 0x01\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS 0x02\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC 0x03\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC 0x04\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_TYPE_5_HW_REGISTERS_COMMUNICATIONS 0x05\r
\r
///\r
/// PCC Subspace Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER;\r
\r
///\r
/// Generic Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[6];\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[6];\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC;\r
\r
///\r
///\r
\r
typedef struct {\r
- UINT8 Command;\r
- UINT8 Reserved:7;\r
- UINT8 NotifyOnCompletion:1;\r
+ UINT8 Command;\r
+ UINT8 Reserved : 7;\r
+ UINT8 NotifyOnCompletion : 1;\r
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;\r
\r
typedef struct {\r
- UINT8 CommandComplete:1;\r
- UINT8 PlatformInterrupt:1;\r
- UINT8 Error:1;\r
- UINT8 PlatformNotification:1;\r
- UINT8 Reserved:4;\r
- UINT8 Reserved1;\r
+ UINT8 CommandComplete : 1;\r
+ UINT8 PlatformInterrupt : 1;\r
+ UINT8 Error : 1;\r
+ UINT8 PlatformNotification : 1;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Reserved1;\r
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;\r
\r
typedef struct {\r
EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS Status;\r
} EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;\r
\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
-#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY BIT0\r
+#define EFI_ACPI_6_4_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE BIT1\r
\r
///\r
/// Type 1 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 2 HW-Reduced Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT64 AddressLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT16 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckWrite;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT64 AddressLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT16 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckWrite;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;\r
\r
///\r
/// Type 3 Extended PCC Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT32 PlatformInterrupt;\r
- UINT8 PlatformInterruptFlags;\r
- UINT8 Reserved;\r
- UINT64 BaseAddress;\r
- UINT32 AddressLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- UINT32 NominalLatency;\r
- UINT32 MaximumPeriodicAccessRate;\r
- UINT32 MinimumRequestTurnaroundTime;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
- UINT64 PlatformInterruptAckPreserve;\r
- UINT64 PlatformInterruptAckSet;\r
- UINT8 Reserved1[8];\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
- UINT64 CommandCompleteCheckMask;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
- UINT64 CommandCompleteUpdatePreserve;\r
- UINT64 CommandCompleteUpdateSet;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
- UINT64 ErrorStatusMask;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT32 PlatformInterrupt;\r
+ UINT8 PlatformInterruptFlags;\r
+ UINT8 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT32 AddressLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ UINT32 NominalLatency;\r
+ UINT32 MaximumPeriodicAccessRate;\r
+ UINT32 MinimumRequestTurnaroundTime;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PlatformInterruptAckRegister;\r
+ UINT64 PlatformInterruptAckPreserve;\r
+ UINT64 PlatformInterruptAckSet;\r
+ UINT8 Reserved1[8];\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
+ UINT64 CommandCompleteCheckMask;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteUpdateRegister;\r
+ UINT64 CommandCompleteUpdatePreserve;\r
+ UINT64 CommandCompleteUpdateSet;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
+ UINT64 ErrorStatusMask;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC;\r
\r
///\r
///\r
typedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBSPACE_4_EXTENDED_PCC;\r
\r
-#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
+#define EFI_ACPI_6_4_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Flags;\r
- UINT32 Length;\r
- UINT32 Command;\r
+ UINT32 Signature;\r
+ UINT32 Flags;\r
+ UINT32 Length;\r
+ UINT32 Command;\r
} EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;\r
\r
///\r
/// Type 5 HW Registers based Communications Subspace Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Version;\r
- UINT64 BaseAddress;\r
- UINT64 SharedMemoryRangeLength;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
- UINT64 DoorbellPreserve;\r
- UINT64 DoorbellWrite;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
- UINT64 CommandCompleteCheckMask;\r
- EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
- UINT64 ErrorStatusMask;\r
- UINT32 NominalLatency;\r
- UINT32 MinimumRequestTurnaroundTime;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Version;\r
+ UINT64 BaseAddress;\r
+ UINT64 SharedMemoryRangeLength;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DoorbellRegister;\r
+ UINT64 DoorbellPreserve;\r
+ UINT64 DoorbellWrite;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CommandCompleteCheckRegister;\r
+ UINT64 CommandCompleteCheckMask;\r
+ EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ErrorStatusRegister;\r
+ UINT64 ErrorStatusMask;\r
+ UINT32 NominalLatency;\r
+ UINT32 MinimumRequestTurnaroundTime;\r
} EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS;\r
\r
///\r
/// Reduced PCC Subspace Shared Memory Region\r
///\r
typedef struct {\r
- UINT32 Signature;\r
-//UINT8 CommunicationSubspace[];\r
+ UINT32 Signature;\r
+ // UINT8 CommunicationSubspace[];\r
} EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION;\r
\r
///\r
/// Platform Debug Trigger Table (PDTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 TriggerCount;\r
- UINT8 Reserved[3];\r
- UINT32 TriggerIdentifierArrayOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 TriggerCount;\r
+ UINT8 Reserved[3];\r
+ UINT32 TriggerIdentifierArrayOffset;\r
} EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;\r
\r
///\r
/// PDTT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
+#define EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00\r
\r
///\r
/// PDTT Platform Communication Channel Identifier Structure\r
///\r
typedef struct {\r
- UINT16 SubChannelIdentifer:8;\r
- UINT16 Runtime:1;\r
- UINT16 WaitForCompletion:1;\r
- UINT16 TriggerOrder:1;\r
- UINT16 Reserved:5;\r
+ UINT16 SubChannelIdentifer : 8;\r
+ UINT16 Runtime : 1;\r
+ UINT16 WaitForCompletion : 1;\r
+ UINT16 TriggerOrder : 1;\r
+ UINT16 Reserved : 5;\r
} EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER;\r
\r
///\r
/// PCC Commands Codes used by Platform Debug Trigger Table\r
///\r
-#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
-#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_DOORBELL_ONLY 0x00\r
+#define EFI_ACPI_6_4_PDTT_PCC_COMMAND_VENDOR_SPECIFIC 0x01\r
\r
///\r
/// PDTT Platform Communication Channel\r
/// Processor Properties Topology Table (PPTT)\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;\r
\r
///\r
/// PPTT Revision (as defined in ACPI 6.4 spec.)\r
///\r
-#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03\r
+#define EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x03\r
\r
///\r
/// PPTT types\r
///\r
-#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00\r
-#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01\r
-#define EFI_ACPI_6_4_PPTT_TYPE_ID 0x02\r
+#define EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR 0x00\r
+#define EFI_ACPI_6_4_PPTT_TYPE_CACHE 0x01\r
+#define EFI_ACPI_6_4_PPTT_TYPE_ID 0x02\r
\r
///\r
/// PPTT Structure Header\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER;\r
\r
///\r
/// Processor hierarchy node structure flags\r
///\r
typedef struct {\r
- UINT32 PhysicalPackage:1;\r
- UINT32 AcpiProcessorIdValid:1;\r
- UINT32 ProcessorIsAThread:1;\r
- UINT32 NodeIsALeaf:1;\r
- UINT32 IdenticalImplementation:1;\r
- UINT32 Reserved:27;\r
+ UINT32 PhysicalPackage : 1;\r
+ UINT32 AcpiProcessorIdValid : 1;\r
+ UINT32 ProcessorIsAThread : 1;\r
+ UINT32 NodeIsALeaf : 1;\r
+ UINT32 IdenticalImplementation : 1;\r
+ UINT32 Reserved : 27;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS;\r
\r
///\r
/// Processor hierarchy node structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
- UINT32 Parent;\r
- UINT32 AcpiProcessorId;\r
- UINT32 NumberOfPrivateResources;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS Flags;\r
+ UINT32 Parent;\r
+ UINT32 AcpiProcessorId;\r
+ UINT32 NumberOfPrivateResources;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR;\r
\r
///\r
/// For PPTT struct cache flags\r
///\r
-#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1\r
-#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0\r
-#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_CACHE_SIZE_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_CACHE_TYPE_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1\r
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0\r
+#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1\r
\r
///\r
/// Cache Type Structure flags\r
///\r
typedef struct {\r
- UINT32 SizePropertyValid:1;\r
- UINT32 NumberOfSetsValid:1;\r
- UINT32 AssociativityValid:1;\r
- UINT32 AllocationTypeValid:1;\r
- UINT32 CacheTypeValid:1;\r
- UINT32 WritePolicyValid:1;\r
- UINT32 LineSizeValid:1;\r
- UINT32 CacheIdValid:1;\r
- UINT32 Reserved:24;\r
+ UINT32 SizePropertyValid : 1;\r
+ UINT32 NumberOfSetsValid : 1;\r
+ UINT32 AssociativityValid : 1;\r
+ UINT32 AllocationTypeValid : 1;\r
+ UINT32 CacheTypeValid : 1;\r
+ UINT32 WritePolicyValid : 1;\r
+ UINT32 LineSizeValid : 1;\r
+ UINT32 CacheIdValid : 1;\r
+ UINT32 Reserved : 24;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS;\r
\r
///\r
/// For cache attributes\r
///\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
-#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ 0x0\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_WRITE 0x1\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE 0x2\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_DATA 0x0\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION 0x1\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED 0x2\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK 0x0\r
+#define EFI_ACPI_6_4_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1\r
\r
///\r
/// Cache Type Structure cache attributes\r
///\r
typedef struct {\r
- UINT8 AllocationType:2;\r
- UINT8 CacheType:2;\r
- UINT8 WritePolicy:1;\r
- UINT8 Reserved:3;\r
+ UINT8 AllocationType : 2;\r
+ UINT8 CacheType : 2;\r
+ UINT8 WritePolicy : 1;\r
+ UINT8 Reserved : 3;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES;\r
\r
///\r
/// Cache Type Structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
- UINT32 NextLevelOfCache;\r
- UINT32 Size;\r
- UINT32 NumberOfSets;\r
- UINT8 Associativity;\r
- EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
- UINT16 LineSize;\r
- UINT32 CacheId;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS Flags;\r
+ UINT32 NextLevelOfCache;\r
+ UINT32 Size;\r
+ UINT32 NumberOfSets;\r
+ UINT8 Associativity;\r
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES Attributes;\r
+ UINT16 LineSize;\r
+ UINT32 CacheId;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE;\r
\r
///\r
/// ID structure\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT8 Reserved[2];\r
- UINT32 VendorId;\r
- UINT64 Level1Id;\r
- UINT64 Level2Id;\r
- UINT16 MajorRev;\r
- UINT16 MinorRev;\r
- UINT16 SpinRev;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT8 Reserved[2];\r
+ UINT32 VendorId;\r
+ UINT64 Level1Id;\r
+ UINT64 Level2Id;\r
+ UINT16 MajorRev;\r
+ UINT16 MinorRev;\r
+ UINT16 SpinRev;\r
} EFI_ACPI_6_4_PPTT_STRUCTURE_ID;\r
\r
///\r
/// Platform Health Assessment Table (PHAT) Format\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
-//UINT8 PlatformTelemetryRecords[];\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ // UINT8 PlatformTelemetryRecords[];\r
} EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE;\r
\r
-#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01\r
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_REVISION 0x01\r
\r
///\r
/// PHAT Record Format\r
///\r
typedef struct {\r
- UINT16 PlatformHealthAssessmentRecordType;\r
- UINT16 RecordLength;\r
- UINT8 Revision;\r
-//UINT8 Data[];\r
+ UINT16 PlatformHealthAssessmentRecordType;\r
+ UINT16 RecordLength;\r
+ UINT8 Revision;\r
+ // UINT8 Data[];\r
} EFI_ACPI_6_4_PHAT_RECORD;\r
\r
///\r
/// PHAT Version Element\r
///\r
typedef struct {\r
- GUID ComponentId;\r
- UINT64 VersionValue;\r
- UINT32 ProducerId;\r
+ GUID ComponentId;\r
+ UINT64 VersionValue;\r
+ UINT32 ProducerId;\r
} EFI_ACPI_6_4_PHAT_VERSION_ELEMENT;\r
\r
///\r
/// PHAT Firmware Version Data Record\r
///\r
typedef struct {\r
- UINT16 PlatformRecordType;\r
- UINT16 RecordLength;\r
- UINT8 Revision;\r
- UINT8 Reserved[3];\r
- UINT32 RecordCount;\r
-//UINT8 PhatVersionElement[];\r
+ UINT16 PlatformRecordType;\r
+ UINT16 RecordLength;\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
+ UINT32 RecordCount;\r
+ // UINT8 PhatVersionElement[];\r
} EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD;\r
\r
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01\r
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_VERSION_DATA_RECORD_REVISION 0x01\r
\r
///\r
/// Firmware Health Data Record Structure\r
///\r
typedef struct {\r
- UINT16 PlatformRecordType;\r
- UINT16 RecordLength;\r
- UINT8 Revision;\r
- UINT16 Reserved;\r
- UINT8 AmHealthy;\r
- GUID DeviceSignature;\r
- UINT32 DeviceSpecificDataOffset;\r
-//UINT8 DevicePath[];\r
-//UINT8 DeviceSpecificData[];\r
+ UINT16 PlatformRecordType;\r
+ UINT16 RecordLength;\r
+ UINT8 Revision;\r
+ UINT16 Reserved;\r
+ UINT8 AmHealthy;\r
+ GUID DeviceSignature;\r
+ UINT32 DeviceSpecificDataOffset;\r
+ // UINT8 DevicePath[];\r
+ // UINT8 DeviceSpecificData[];\r
} EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE;\r
\r
#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_REVISION 0x01\r
///\r
/// Firmware Health Data Record device health state\r
///\r
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00\r
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01\r
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02\r
-#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03\r
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ERRORS_FOUND 0x00\r
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_NO_ERRORS_FOUND 0x01\r
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_UNKNOWN 0x02\r
+#define EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_ADVISORY 0x03\r
\r
//\r
// Known table signatures\r
///\r
/// "PHAT" Platform Health Assessment Table\r
///\r
-#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')\r
+#define EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE_SIGNATURE SIGNATURE_32('P', 'H', 'A', 'T')\r
\r
///\r
/// "SDEI" Software Delegated Exceptions Interface Table\r
//\r
// Primary OpCode\r
//\r
-#define AML_ZERO_OP 0x00\r
-#define AML_ONE_OP 0x01\r
-#define AML_ALIAS_OP 0x06\r
-#define AML_NAME_OP 0x08\r
-#define AML_BYTE_PREFIX 0x0a\r
-#define AML_WORD_PREFIX 0x0b\r
-#define AML_DWORD_PREFIX 0x0c\r
-#define AML_STRING_PREFIX 0x0d\r
-#define AML_QWORD_PREFIX 0x0e\r
-#define AML_SCOPE_OP 0x10\r
-#define AML_BUFFER_OP 0x11\r
-#define AML_PACKAGE_OP 0x12\r
-#define AML_VAR_PACKAGE_OP 0x13\r
-#define AML_METHOD_OP 0x14\r
-#define AML_EXTERNAL_OP 0x15\r
-#define AML_DUAL_NAME_PREFIX 0x2e\r
-#define AML_MULTI_NAME_PREFIX 0x2f\r
-#define AML_NAME_CHAR_A 0x41\r
-#define AML_NAME_CHAR_B 0x42\r
-#define AML_NAME_CHAR_C 0x43\r
-#define AML_NAME_CHAR_D 0x44\r
-#define AML_NAME_CHAR_E 0x45\r
-#define AML_NAME_CHAR_F 0x46\r
-#define AML_NAME_CHAR_G 0x47\r
-#define AML_NAME_CHAR_H 0x48\r
-#define AML_NAME_CHAR_I 0x49\r
-#define AML_NAME_CHAR_J 0x4a\r
-#define AML_NAME_CHAR_K 0x4b\r
-#define AML_NAME_CHAR_L 0x4c\r
-#define AML_NAME_CHAR_M 0x4d\r
-#define AML_NAME_CHAR_N 0x4e\r
-#define AML_NAME_CHAR_O 0x4f\r
-#define AML_NAME_CHAR_P 0x50\r
-#define AML_NAME_CHAR_Q 0x51\r
-#define AML_NAME_CHAR_R 0x52\r
-#define AML_NAME_CHAR_S 0x53\r
-#define AML_NAME_CHAR_T 0x54\r
-#define AML_NAME_CHAR_U 0x55\r
-#define AML_NAME_CHAR_V 0x56\r
-#define AML_NAME_CHAR_W 0x57\r
-#define AML_NAME_CHAR_X 0x58\r
-#define AML_NAME_CHAR_Y 0x59\r
-#define AML_NAME_CHAR_Z 0x5a\r
-#define AML_ROOT_CHAR 0x5c\r
-#define AML_PARENT_PREFIX_CHAR 0x5e\r
-#define AML_NAME_CHAR__ 0x5f\r
-#define AML_LOCAL0 0x60\r
-#define AML_LOCAL1 0x61\r
-#define AML_LOCAL2 0x62\r
-#define AML_LOCAL3 0x63\r
-#define AML_LOCAL4 0x64\r
-#define AML_LOCAL5 0x65\r
-#define AML_LOCAL6 0x66\r
-#define AML_LOCAL7 0x67\r
-#define AML_ARG0 0x68\r
-#define AML_ARG1 0x69\r
-#define AML_ARG2 0x6a\r
-#define AML_ARG3 0x6b\r
-#define AML_ARG4 0x6c\r
-#define AML_ARG5 0x6d\r
-#define AML_ARG6 0x6e\r
-#define AML_STORE_OP 0x70\r
-#define AML_REF_OF_OP 0x71\r
-#define AML_ADD_OP 0x72\r
-#define AML_CONCAT_OP 0x73\r
-#define AML_SUBTRACT_OP 0x74\r
-#define AML_INCREMENT_OP 0x75\r
-#define AML_DECREMENT_OP 0x76\r
-#define AML_MULTIPLY_OP 0x77\r
-#define AML_DIVIDE_OP 0x78\r
-#define AML_SHIFT_LEFT_OP 0x79\r
-#define AML_SHIFT_RIGHT_OP 0x7a\r
-#define AML_AND_OP 0x7b\r
-#define AML_NAND_OP 0x7c\r
-#define AML_OR_OP 0x7d\r
-#define AML_NOR_OP 0x7e\r
-#define AML_XOR_OP 0x7f\r
-#define AML_NOT_OP 0x80\r
-#define AML_FIND_SET_LEFT_BIT_OP 0x81\r
-#define AML_FIND_SET_RIGHT_BIT_OP 0x82\r
-#define AML_DEREF_OF_OP 0x83\r
-#define AML_CONCAT_RES_OP 0x84\r
-#define AML_MOD_OP 0x85\r
-#define AML_NOTIFY_OP 0x86\r
-#define AML_SIZE_OF_OP 0x87\r
-#define AML_INDEX_OP 0x88\r
-#define AML_MATCH_OP 0x89\r
-#define AML_CREATE_DWORD_FIELD_OP 0x8a\r
-#define AML_CREATE_WORD_FIELD_OP 0x8b\r
-#define AML_CREATE_BYTE_FIELD_OP 0x8c\r
-#define AML_CREATE_BIT_FIELD_OP 0x8d\r
-#define AML_OBJECT_TYPE_OP 0x8e\r
-#define AML_CREATE_QWORD_FIELD_OP 0x8f\r
-#define AML_LAND_OP 0x90\r
-#define AML_LOR_OP 0x91\r
-#define AML_LNOT_OP 0x92\r
-#define AML_LEQUAL_OP 0x93\r
-#define AML_LGREATER_OP 0x94\r
-#define AML_LLESS_OP 0x95\r
-#define AML_TO_BUFFER_OP 0x96\r
-#define AML_TO_DEC_STRING_OP 0x97\r
-#define AML_TO_HEX_STRING_OP 0x98\r
-#define AML_TO_INTEGER_OP 0x99\r
-#define AML_TO_STRING_OP 0x9c\r
-#define AML_COPY_OBJECT_OP 0x9d\r
-#define AML_MID_OP 0x9e\r
-#define AML_CONTINUE_OP 0x9f\r
-#define AML_IF_OP 0xa0\r
-#define AML_ELSE_OP 0xa1\r
-#define AML_WHILE_OP 0xa2\r
-#define AML_NOOP_OP 0xa3\r
-#define AML_RETURN_OP 0xa4\r
-#define AML_BREAK_OP 0xa5\r
-#define AML_BREAK_POINT_OP 0xcc\r
-#define AML_ONES_OP 0xff\r
+#define AML_ZERO_OP 0x00\r
+#define AML_ONE_OP 0x01\r
+#define AML_ALIAS_OP 0x06\r
+#define AML_NAME_OP 0x08\r
+#define AML_BYTE_PREFIX 0x0a\r
+#define AML_WORD_PREFIX 0x0b\r
+#define AML_DWORD_PREFIX 0x0c\r
+#define AML_STRING_PREFIX 0x0d\r
+#define AML_QWORD_PREFIX 0x0e\r
+#define AML_SCOPE_OP 0x10\r
+#define AML_BUFFER_OP 0x11\r
+#define AML_PACKAGE_OP 0x12\r
+#define AML_VAR_PACKAGE_OP 0x13\r
+#define AML_METHOD_OP 0x14\r
+#define AML_EXTERNAL_OP 0x15\r
+#define AML_DUAL_NAME_PREFIX 0x2e\r
+#define AML_MULTI_NAME_PREFIX 0x2f\r
+#define AML_NAME_CHAR_A 0x41\r
+#define AML_NAME_CHAR_B 0x42\r
+#define AML_NAME_CHAR_C 0x43\r
+#define AML_NAME_CHAR_D 0x44\r
+#define AML_NAME_CHAR_E 0x45\r
+#define AML_NAME_CHAR_F 0x46\r
+#define AML_NAME_CHAR_G 0x47\r
+#define AML_NAME_CHAR_H 0x48\r
+#define AML_NAME_CHAR_I 0x49\r
+#define AML_NAME_CHAR_J 0x4a\r
+#define AML_NAME_CHAR_K 0x4b\r
+#define AML_NAME_CHAR_L 0x4c\r
+#define AML_NAME_CHAR_M 0x4d\r
+#define AML_NAME_CHAR_N 0x4e\r
+#define AML_NAME_CHAR_O 0x4f\r
+#define AML_NAME_CHAR_P 0x50\r
+#define AML_NAME_CHAR_Q 0x51\r
+#define AML_NAME_CHAR_R 0x52\r
+#define AML_NAME_CHAR_S 0x53\r
+#define AML_NAME_CHAR_T 0x54\r
+#define AML_NAME_CHAR_U 0x55\r
+#define AML_NAME_CHAR_V 0x56\r
+#define AML_NAME_CHAR_W 0x57\r
+#define AML_NAME_CHAR_X 0x58\r
+#define AML_NAME_CHAR_Y 0x59\r
+#define AML_NAME_CHAR_Z 0x5a\r
+#define AML_ROOT_CHAR 0x5c\r
+#define AML_PARENT_PREFIX_CHAR 0x5e\r
+#define AML_NAME_CHAR__ 0x5f\r
+#define AML_LOCAL0 0x60\r
+#define AML_LOCAL1 0x61\r
+#define AML_LOCAL2 0x62\r
+#define AML_LOCAL3 0x63\r
+#define AML_LOCAL4 0x64\r
+#define AML_LOCAL5 0x65\r
+#define AML_LOCAL6 0x66\r
+#define AML_LOCAL7 0x67\r
+#define AML_ARG0 0x68\r
+#define AML_ARG1 0x69\r
+#define AML_ARG2 0x6a\r
+#define AML_ARG3 0x6b\r
+#define AML_ARG4 0x6c\r
+#define AML_ARG5 0x6d\r
+#define AML_ARG6 0x6e\r
+#define AML_STORE_OP 0x70\r
+#define AML_REF_OF_OP 0x71\r
+#define AML_ADD_OP 0x72\r
+#define AML_CONCAT_OP 0x73\r
+#define AML_SUBTRACT_OP 0x74\r
+#define AML_INCREMENT_OP 0x75\r
+#define AML_DECREMENT_OP 0x76\r
+#define AML_MULTIPLY_OP 0x77\r
+#define AML_DIVIDE_OP 0x78\r
+#define AML_SHIFT_LEFT_OP 0x79\r
+#define AML_SHIFT_RIGHT_OP 0x7a\r
+#define AML_AND_OP 0x7b\r
+#define AML_NAND_OP 0x7c\r
+#define AML_OR_OP 0x7d\r
+#define AML_NOR_OP 0x7e\r
+#define AML_XOR_OP 0x7f\r
+#define AML_NOT_OP 0x80\r
+#define AML_FIND_SET_LEFT_BIT_OP 0x81\r
+#define AML_FIND_SET_RIGHT_BIT_OP 0x82\r
+#define AML_DEREF_OF_OP 0x83\r
+#define AML_CONCAT_RES_OP 0x84\r
+#define AML_MOD_OP 0x85\r
+#define AML_NOTIFY_OP 0x86\r
+#define AML_SIZE_OF_OP 0x87\r
+#define AML_INDEX_OP 0x88\r
+#define AML_MATCH_OP 0x89\r
+#define AML_CREATE_DWORD_FIELD_OP 0x8a\r
+#define AML_CREATE_WORD_FIELD_OP 0x8b\r
+#define AML_CREATE_BYTE_FIELD_OP 0x8c\r
+#define AML_CREATE_BIT_FIELD_OP 0x8d\r
+#define AML_OBJECT_TYPE_OP 0x8e\r
+#define AML_CREATE_QWORD_FIELD_OP 0x8f\r
+#define AML_LAND_OP 0x90\r
+#define AML_LOR_OP 0x91\r
+#define AML_LNOT_OP 0x92\r
+#define AML_LEQUAL_OP 0x93\r
+#define AML_LGREATER_OP 0x94\r
+#define AML_LLESS_OP 0x95\r
+#define AML_TO_BUFFER_OP 0x96\r
+#define AML_TO_DEC_STRING_OP 0x97\r
+#define AML_TO_HEX_STRING_OP 0x98\r
+#define AML_TO_INTEGER_OP 0x99\r
+#define AML_TO_STRING_OP 0x9c\r
+#define AML_COPY_OBJECT_OP 0x9d\r
+#define AML_MID_OP 0x9e\r
+#define AML_CONTINUE_OP 0x9f\r
+#define AML_IF_OP 0xa0\r
+#define AML_ELSE_OP 0xa1\r
+#define AML_WHILE_OP 0xa2\r
+#define AML_NOOP_OP 0xa3\r
+#define AML_RETURN_OP 0xa4\r
+#define AML_BREAK_OP 0xa5\r
+#define AML_BREAK_POINT_OP 0xcc\r
+#define AML_ONES_OP 0xff\r
\r
//\r
// Extended OpCode\r
//\r
-#define AML_EXT_OP 0x5b\r
+#define AML_EXT_OP 0x5b\r
\r
-#define AML_EXT_MUTEX_OP 0x01\r
-#define AML_EXT_EVENT_OP 0x02\r
-#define AML_EXT_COND_REF_OF_OP 0x12\r
-#define AML_EXT_CREATE_FIELD_OP 0x13\r
-#define AML_EXT_LOAD_TABLE_OP 0x1f\r
-#define AML_EXT_LOAD_OP 0x20\r
-#define AML_EXT_STALL_OP 0x21\r
-#define AML_EXT_SLEEP_OP 0x22\r
-#define AML_EXT_ACQUIRE_OP 0x23\r
-#define AML_EXT_SIGNAL_OP 0x24\r
-#define AML_EXT_WAIT_OP 0x25\r
-#define AML_EXT_RESET_OP 0x26\r
-#define AML_EXT_RELEASE_OP 0x27\r
-#define AML_EXT_FROM_BCD_OP 0x28\r
-#define AML_EXT_TO_BCD_OP 0x29\r
-#define AML_EXT_UNLOAD_OP 0x2a\r
-#define AML_EXT_REVISION_OP 0x30\r
-#define AML_EXT_DEBUG_OP 0x31\r
-#define AML_EXT_FATAL_OP 0x32\r
-#define AML_EXT_TIMER_OP 0x33\r
-#define AML_EXT_REGION_OP 0x80\r
-#define AML_EXT_FIELD_OP 0x81\r
-#define AML_EXT_DEVICE_OP 0x82\r
-#define AML_EXT_PROCESSOR_OP 0x83\r
-#define AML_EXT_POWER_RES_OP 0x84\r
-#define AML_EXT_THERMAL_ZONE_OP 0x85\r
-#define AML_EXT_INDEX_FIELD_OP 0x86\r
-#define AML_EXT_BANK_FIELD_OP 0x87\r
-#define AML_EXT_DATA_REGION_OP 0x88\r
+#define AML_EXT_MUTEX_OP 0x01\r
+#define AML_EXT_EVENT_OP 0x02\r
+#define AML_EXT_COND_REF_OF_OP 0x12\r
+#define AML_EXT_CREATE_FIELD_OP 0x13\r
+#define AML_EXT_LOAD_TABLE_OP 0x1f\r
+#define AML_EXT_LOAD_OP 0x20\r
+#define AML_EXT_STALL_OP 0x21\r
+#define AML_EXT_SLEEP_OP 0x22\r
+#define AML_EXT_ACQUIRE_OP 0x23\r
+#define AML_EXT_SIGNAL_OP 0x24\r
+#define AML_EXT_WAIT_OP 0x25\r
+#define AML_EXT_RESET_OP 0x26\r
+#define AML_EXT_RELEASE_OP 0x27\r
+#define AML_EXT_FROM_BCD_OP 0x28\r
+#define AML_EXT_TO_BCD_OP 0x29\r
+#define AML_EXT_UNLOAD_OP 0x2a\r
+#define AML_EXT_REVISION_OP 0x30\r
+#define AML_EXT_DEBUG_OP 0x31\r
+#define AML_EXT_FATAL_OP 0x32\r
+#define AML_EXT_TIMER_OP 0x33\r
+#define AML_EXT_REGION_OP 0x80\r
+#define AML_EXT_FIELD_OP 0x81\r
+#define AML_EXT_DEVICE_OP 0x82\r
+#define AML_EXT_PROCESSOR_OP 0x83\r
+#define AML_EXT_POWER_RES_OP 0x84\r
+#define AML_EXT_THERMAL_ZONE_OP 0x85\r
+#define AML_EXT_INDEX_FIELD_OP 0x86\r
+#define AML_EXT_BANK_FIELD_OP 0x87\r
+#define AML_EXT_DATA_REGION_OP 0x88\r
\r
//\r
// FieldElement OpCode\r
//\r
-#define AML_FIELD_RESERVED_OP 0x00\r
-#define AML_FIELD_ACCESS_OP 0x01\r
-#define AML_FIELD_CONNECTION_OP 0x02\r
-#define AML_FIELD_EXT_ACCESS_OP 0x03\r
+#define AML_FIELD_RESERVED_OP 0x00\r
+#define AML_FIELD_ACCESS_OP 0x01\r
+#define AML_FIELD_CONNECTION_OP 0x02\r
+#define AML_FIELD_EXT_ACCESS_OP 0x03\r
\r
//\r
// AML Name segment definitions\r
//\r
-#define AML_NAME_SEG_SIZE 4\r
+#define AML_NAME_SEG_SIZE 4\r
\r
#endif\r
/// Information Record header that appears at the beginning of each record\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Reserved;\r
- UINT16 RecordLength;\r
+ UINT8 Type;\r
+ UINT8 Reserved;\r
+ UINT16 RecordLength;\r
} EFI_ACPI_ASF_RECORD_HEADER;\r
\r
///\r
/// and configuration\r
///\r
typedef struct {\r
- EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
- UINT8 MinWatchDogResetValue;\r
- UINT8 MinPollingInterval;\r
- UINT16 SystemID;\r
- UINT32 IANAManufactureID;\r
- UINT8 FeatureFlags;\r
- UINT8 Reserved[3];\r
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
+ UINT8 MinWatchDogResetValue;\r
+ UINT8 MinPollingInterval;\r
+ UINT16 SystemID;\r
+ UINT32 IANAManufactureID;\r
+ UINT8 FeatureFlags;\r
+ UINT8 Reserved[3];\r
} EFI_ACPI_ASF_INFO;\r
\r
///\r
/// ASF Alert Data\r
///\r
typedef struct {\r
- UINT8 DeviceAddress;\r
- UINT8 Command;\r
- UINT8 DataMask;\r
- UINT8 CompareValue;\r
- UINT8 EventSenseType;\r
- UINT8 EventType;\r
- UINT8 EventOffset;\r
- UINT8 EventSourceType;\r
- UINT8 EventSeverity;\r
- UINT8 SensorNumber;\r
- UINT8 Entity;\r
- UINT8 EntityInstance;\r
+ UINT8 DeviceAddress;\r
+ UINT8 Command;\r
+ UINT8 DataMask;\r
+ UINT8 CompareValue;\r
+ UINT8 EventSenseType;\r
+ UINT8 EventType;\r
+ UINT8 EventOffset;\r
+ UINT8 EventSourceType;\r
+ UINT8 EventSeverity;\r
+ UINT8 SensorNumber;\r
+ UINT8 Entity;\r
+ UINT8 EntityInstance;\r
} EFI_ACPI_ASF_ALERTDATA;\r
\r
///\r
/// Alert sensors definition\r
///\r
typedef struct {\r
- EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
- UINT8 AssertionEventBitMask;\r
- UINT8 DeassertionEventBitMask;\r
- UINT8 NumberOfAlerts;\r
- UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C\r
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
+ UINT8 AssertionEventBitMask;\r
+ UINT8 DeassertionEventBitMask;\r
+ UINT8 NumberOfAlerts;\r
+ UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x0C\r
///\r
/// EFI_ACPI_ASF_ALERTDATA DeviceArray[ANYSIZE_ARRAY];\r
///\r
/// Alert Control Data\r
///\r
typedef struct {\r
- UINT8 Function;\r
- UINT8 DeviceAddress;\r
- UINT8 Command;\r
- UINT8 DataValue;\r
+ UINT8 Function;\r
+ UINT8 DeviceAddress;\r
+ UINT8 Command;\r
+ UINT8 DataValue;\r
} EFI_ACPI_ASF_CONTROLDATA;\r
\r
///\r
/// Alert Remote Control System Actions\r
///\r
typedef struct {\r
- EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
- UINT8 NumberOfControls;\r
- UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4\r
- UINT16 RctlReserved;\r
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
+ UINT8 NumberOfControls;\r
+ UINT8 ArrayElementLength; ///< For ASF version 1.0 and later, this filed is set to 0x4\r
+ UINT16 RctlReserved;\r
///\r
/// EFI_ACPI_ASF_CONTROLDATA; DeviceArray[ANYSIZE_ARRAY];\r
///\r
} EFI_ACPI_ASF_RCTL;\r
\r
-\r
///\r
/// Remote Control Capabilities\r
///\r
typedef struct {\r
- EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
- UINT8 RemoteControlCapabilities[7];\r
- UINT8 RMCPCompletionCode;\r
- UINT32 RMCPIANA;\r
- UINT8 RMCPSpecialCommand;\r
- UINT8 RMCPSpecialCommandParameter[2];\r
- UINT8 RMCPBootOptions[2];\r
- UINT8 RMCPOEMParameters[2];\r
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
+ UINT8 RemoteControlCapabilities[7];\r
+ UINT8 RMCPCompletionCode;\r
+ UINT32 RMCPIANA;\r
+ UINT8 RMCPSpecialCommand;\r
+ UINT8 RMCPSpecialCommandParameter[2];\r
+ UINT8 RMCPBootOptions[2];\r
+ UINT8 RMCPOEMParameters[2];\r
} EFI_ACPI_ASF_RMCP;\r
\r
///\r
/// SMBus Devices with fixed addresses\r
///\r
typedef struct {\r
- EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
- UINT8 SEEPROMAddress;\r
- UINT8 NumberOfDevices;\r
+ EFI_ACPI_ASF_RECORD_HEADER RecordHeader;\r
+ UINT8 SEEPROMAddress;\r
+ UINT8 NumberOfDevices;\r
///\r
/// UINT8 FixedSmbusAddresses[ANYSIZE_ARRAY];\r
///\r
///\r
/// The revision stored in ASF! DESCRIPTION TABLE as BCD value\r
///\r
-#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20\r
+#define EFI_ACPI_2_0_ASF_DESCRIPTION_TABLE_REVISION 0x20\r
\r
///\r
/// "ASF!" ASF Description Table Signature\r
/// Arm Error Source Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
} EFI_ACPI_ARM_ERROR_SOURCE_TABLE;\r
\r
///\r
/// 0x02 - SMMU error node\r
/// 0x03 - Vendor-defined error node\r
/// 0x04 - GIC error node\r
- UINT8 Type;\r
+ UINT8 Type;\r
\r
/// Length of structure in bytes.\r
- UINT16 Length;\r
+ UINT16 Length;\r
\r
/// Reserved - Must be zero.\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
\r
/// Offset from the start of the node to node-specific data.\r
- UINT32 DataOffset;\r
+ UINT32 DataOffset;\r
\r
/// Offset from the start of the node to the node interface structure.\r
- UINT32 InterfaceOffset;\r
+ UINT32 InterfaceOffset;\r
\r
/// Offset from the start of the node to node interrupt array.\r
- UINT32 InterruptArrayOffset;\r
+ UINT32 InterruptArrayOffset;\r
\r
/// Number of entries in the interrupt array.\r
- UINT32 InterruptArrayCount;\r
+ UINT32 InterruptArrayCount;\r
\r
// Generic node data\r
\r
/// The timestamp frequency of the counter in Hz.\r
- UINT64 TimestampRate;\r
+ UINT64 TimestampRate;\r
\r
/// Reserved - Must be zero.\r
- UINT64 Reserved1;\r
+ UINT64 Reserved1;\r
\r
/// The rate in Hz at which the Error Generation Counter decrements.\r
- UINT64 ErrorInjectionCountdownRate;\r
+ UINT64 ErrorInjectionCountdownRate;\r
} EFI_ACPI_AEST_NODE_STRUCT;\r
\r
// AEST Node type definitions\r
/// Interface type:\r
/// 0x0 - System register (SR)\r
/// 0x1 - Memory mapped (MMIO)\r
- UINT8 Type;\r
+ UINT8 Type;\r
\r
/// Reserved - Must be zero.\r
- UINT8 Reserved[3];\r
+ UINT8 Reserved[3];\r
\r
/// AEST node interface flags.\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
/// Base address of error group that contains the error node.\r
- UINT64 BaseAddress;\r
+ UINT64 BaseAddress;\r
\r
/// Zero-based index of the first standard error record that\r
/// belongs to this node.\r
- UINT32 StartErrorRecordIndex;\r
+ UINT32 StartErrorRecordIndex;\r
\r
/// Number of error records in this node including both\r
/// implemented and unimplemented records.\r
- UINT32 NumberErrorRecords;\r
+ UINT32 NumberErrorRecords;\r
\r
/// A bitmap indicating the error records within this\r
/// node that are implemented in the current system.\r
- UINT64 ErrorRecordImplemented;\r
+ UINT64 ErrorRecordImplemented;\r
\r
/// A bitmap indicating the error records within this node that\r
/// support error status reporting through the ERRGSR register.\r
- UINT64 ErrorRecordStatusReportingSupported;\r
+ UINT64 ErrorRecordStatusReportingSupported;\r
\r
/// A bitmap indicating the addressing mode used by each error\r
/// record within this node to populate the ERR<n>_ADDR register.\r
- UINT64 AddressingMode;\r
+ UINT64 AddressingMode;\r
} EFI_ACPI_AEST_INTERFACE_STRUCT;\r
\r
// AEST Interface node type definitions.\r
-#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0\r
-#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1\r
+#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0\r
+#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1\r
\r
// AEST node interface flag definitions.\r
-#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0\r
-#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0\r
-#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1\r
+#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0\r
+#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0\r
+#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1\r
\r
///\r
/// AEST Node Interrupt structure.\r
/// Interrupt type:\r
/// 0x0 - Fault Handling Interrupt\r
/// 0x1 - Error Recovery Interrupt\r
- UINT8 InterruptType;\r
+ UINT8 InterruptType;\r
\r
/// Reserved - Must be zero.\r
- UINT8 Reserved[2];\r
+ UINT8 Reserved[2];\r
\r
/// Interrupt flags\r
/// Bits [31:1]: Must be zero.\r
/// Bit 0:\r
/// 0b - Interrupt is edge-triggered\r
/// 1b - Interrupt is level-triggered\r
- UINT8 InterruptFlags;\r
+ UINT8 InterruptFlags;\r
\r
/// GSIV of interrupt, if interrupt is an SPI or a PPI.\r
- UINT32 InterruptGsiv;\r
+ UINT32 InterruptGsiv;\r
\r
/// If MSI is supported, then this field must be set to the\r
/// Identifier field of the IORT ITS Group node.\r
- UINT8 ItsGroupRefId;\r
+ UINT8 ItsGroupRefId;\r
\r
/// Reserved - must be zero.\r
- UINT8 Reserved1[3];\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_AEST_INTERRUPT_STRUCT;\r
\r
// AEST Interrupt node - interrupt type defintions.\r
-#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0\r
-#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1\r
+#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0\r
+#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1\r
\r
// AEST Interrupt node - interrupt flag defintions.\r
-#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0\r
-#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0\r
+#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0\r
+#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0\r
\r
///\r
/// Cache Processor Resource structure.\r
///\r
typedef struct {\r
/// Reference to the cache structure in the PPTT table.\r
- UINT32 CacheRefId;\r
+ UINT32 CacheRefId;\r
\r
/// Reserved\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;\r
\r
///\r
///\r
typedef struct {\r
/// TLB level from perspective of current processor.\r
- UINT32 TlbRefId;\r
+ UINT32 TlbRefId;\r
\r
/// Reserved\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;\r
\r
///\r
///\r
typedef struct {\r
/// Vendor-defined supplementary data.\r
- UINT32 Data;\r
+ UINT32 Data;\r
} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;\r
\r
///\r
///\r
typedef union {\r
/// Processor Cache resource.\r
- EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache;\r
+ EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache;\r
\r
/// Processor TLB resource.\r
- EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb;\r
+ EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb;\r
\r
/// Processor Generic resource.\r
- EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic;\r
+ EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic;\r
} EFI_ACPI_AEST_PROCESSOR_RESOURCE;\r
\r
///\r
///\r
typedef struct {\r
/// AEST Node header\r
- EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
\r
/// Processor ID of node.\r
- UINT32 AcpiProcessorId;\r
+ UINT32 AcpiProcessorId;\r
\r
/// Resource type of the processor node.\r
/// 0x0 - Cache\r
/// 0x1 - TLB\r
/// 0x2 - Generic\r
- UINT8 ResourceType;\r
+ UINT8 ResourceType;\r
\r
/// Reserved - must be zero.\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
\r
/// Processor structure flags.\r
- UINT8 Flags;\r
+ UINT8 Flags;\r
\r
/// Processor structure revision.\r
- UINT8 Revision;\r
+ UINT8 Revision;\r
\r
/// Processor affinity descriptor for the resource that this\r
/// error node pertains to.\r
- UINT64 ProcessorAffinityLevelIndicator;\r
+ UINT64 ProcessorAffinityLevelIndicator;\r
\r
/// Processor resource\r
- EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource;\r
+ EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource;\r
\r
// Node Interface\r
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r
} EFI_ACPI_AEST_PROCESSOR_STRUCT;\r
\r
// AEST Processor resource type definitions.\r
-#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0\r
-#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1\r
-#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2\r
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0\r
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1\r
+#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2\r
\r
// AEST Processor flag definitions.\r
-#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0\r
-#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1\r
+#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0\r
+#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1\r
\r
///\r
/// Memory Controller structure.\r
///\r
typedef struct {\r
/// AEST Node header\r
- EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
\r
/// SRAT proximity domain.\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
\r
// Node Interface\r
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r
///\r
typedef struct {\r
/// AEST Node header\r
- EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
\r
/// Reference to the IORT table node that describes this SMMU.\r
- UINT32 SmmuRefId;\r
+ UINT32 SmmuRefId;\r
\r
/// Reference to the IORT table node that is associated with the\r
/// sub-component within this SMMU.\r
- UINT32 SubComponentRefId;\r
+ UINT32 SubComponentRefId;\r
\r
// Node Interface\r
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r
///\r
typedef struct {\r
/// AEST Node header\r
- EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
\r
/// ACPI HID of the component.\r
- UINT32 HardwareId;\r
+ UINT32 HardwareId;\r
\r
/// The ACPI Unique identifier of the component.\r
- UINT32 UniqueId;\r
+ UINT32 UniqueId;\r
\r
/// Vendor-specific data, for example to identify this error source.\r
- UINT8 VendorData[16];\r
+ UINT8 VendorData[16];\r
\r
// Node Interface\r
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r
///\r
typedef struct {\r
/// AEST Node header\r
- EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
+ EFI_ACPI_AEST_NODE_STRUCT NodeHeader;\r
\r
/// Type of GIC interface that is associated with this error node.\r
/// 0x0 - GIC CPU (GICC)\r
/// 0x1 - GIC Distributor (GICD)\r
/// 0x2 - GIC Resistributor (GICR)\r
/// 0x3 - GIC ITS (GITS)\r
- UINT32 InterfaceType;\r
+ UINT32 InterfaceType;\r
\r
/// Identifier for the interface instance.\r
- UINT32 GicInterfaceRefId;\r
+ UINT32 GicInterfaceRefId;\r
\r
// Node Interface\r
// EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface;\r
} EFI_ACPI_AEST_GIC_STRUCT;\r
\r
// AEST GIC interface type definitions.\r
-#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0\r
-#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1\r
-#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2\r
-#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3\r
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0\r
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1\r
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2\r
+#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3\r
\r
#pragma pack()\r
\r
/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)\r
///\r
typedef struct {\r
- UINT16 config; ///< General Configuration.\r
- UINT16 cylinders; ///< Number of Cylinders.\r
- UINT16 reserved_2;\r
- UINT16 heads; ///< Number of logical heads.\r
- UINT16 vendor_data1;\r
- UINT16 vendor_data2;\r
- UINT16 sectors_per_track;\r
- UINT16 vendor_specific_7_9[3];\r
- CHAR8 SerialNo[20]; ///< ASCII\r
- UINT16 vendor_specific_20_21[2];\r
- UINT16 ecc_bytes_available;\r
- CHAR8 FirmwareVer[8]; ///< ASCII\r
- CHAR8 ModelName[40]; ///< ASCII\r
- UINT16 multi_sector_cmd_max_sct_cnt;\r
- UINT16 reserved_48;\r
- UINT16 capabilities;\r
- UINT16 reserved_50;\r
- UINT16 pio_cycle_timing;\r
- UINT16 reserved_52;\r
- UINT16 field_validity;\r
- UINT16 current_cylinders;\r
- UINT16 current_heads;\r
- UINT16 current_sectors;\r
- UINT16 CurrentCapacityLsb;\r
- UINT16 CurrentCapacityMsb;\r
- UINT16 reserved_59;\r
- UINT16 user_addressable_sectors_lo;\r
- UINT16 user_addressable_sectors_hi;\r
- UINT16 reserved_62;\r
- UINT16 multi_word_dma_mode;\r
- UINT16 advanced_pio_modes;\r
- UINT16 min_multi_word_dma_cycle_time;\r
- UINT16 rec_multi_word_dma_cycle_time;\r
- UINT16 min_pio_cycle_time_without_flow_control;\r
- UINT16 min_pio_cycle_time_with_flow_control;\r
- UINT16 reserved_69_79[11];\r
- UINT16 major_version_no;\r
- UINT16 minor_version_no;\r
- UINT16 command_set_supported_82; ///< word 82\r
- UINT16 command_set_supported_83; ///< word 83\r
- UINT16 command_set_feature_extn; ///< word 84\r
- UINT16 command_set_feature_enb_85; ///< word 85\r
- UINT16 command_set_feature_enb_86; ///< word 86\r
- UINT16 command_set_feature_default; ///< word 87\r
- UINT16 ultra_dma_mode; ///< word 88\r
- UINT16 reserved_89_127[39];\r
- UINT16 security_status;\r
- UINT16 vendor_data_129_159[31];\r
- UINT16 reserved_160_255[96];\r
+ UINT16 config; ///< General Configuration.\r
+ UINT16 cylinders; ///< Number of Cylinders.\r
+ UINT16 reserved_2;\r
+ UINT16 heads; ///< Number of logical heads.\r
+ UINT16 vendor_data1;\r
+ UINT16 vendor_data2;\r
+ UINT16 sectors_per_track;\r
+ UINT16 vendor_specific_7_9[3];\r
+ CHAR8 SerialNo[20]; ///< ASCII\r
+ UINT16 vendor_specific_20_21[2];\r
+ UINT16 ecc_bytes_available;\r
+ CHAR8 FirmwareVer[8]; ///< ASCII\r
+ CHAR8 ModelName[40]; ///< ASCII\r
+ UINT16 multi_sector_cmd_max_sct_cnt;\r
+ UINT16 reserved_48;\r
+ UINT16 capabilities;\r
+ UINT16 reserved_50;\r
+ UINT16 pio_cycle_timing;\r
+ UINT16 reserved_52;\r
+ UINT16 field_validity;\r
+ UINT16 current_cylinders;\r
+ UINT16 current_heads;\r
+ UINT16 current_sectors;\r
+ UINT16 CurrentCapacityLsb;\r
+ UINT16 CurrentCapacityMsb;\r
+ UINT16 reserved_59;\r
+ UINT16 user_addressable_sectors_lo;\r
+ UINT16 user_addressable_sectors_hi;\r
+ UINT16 reserved_62;\r
+ UINT16 multi_word_dma_mode;\r
+ UINT16 advanced_pio_modes;\r
+ UINT16 min_multi_word_dma_cycle_time;\r
+ UINT16 rec_multi_word_dma_cycle_time;\r
+ UINT16 min_pio_cycle_time_without_flow_control;\r
+ UINT16 min_pio_cycle_time_with_flow_control;\r
+ UINT16 reserved_69_79[11];\r
+ UINT16 major_version_no;\r
+ UINT16 minor_version_no;\r
+ UINT16 command_set_supported_82; ///< word 82\r
+ UINT16 command_set_supported_83; ///< word 83\r
+ UINT16 command_set_feature_extn; ///< word 84\r
+ UINT16 command_set_feature_enb_85; ///< word 85\r
+ UINT16 command_set_feature_enb_86; ///< word 86\r
+ UINT16 command_set_feature_default; ///< word 87\r
+ UINT16 ultra_dma_mode; ///< word 88\r
+ UINT16 reserved_89_127[39];\r
+ UINT16 security_status;\r
+ UINT16 vendor_data_129_159[31];\r
+ UINT16 reserved_160_255[96];\r
} ATA5_IDENTIFY_DATA;\r
\r
///\r
/// completion of the ATA IDENTIFY_DEVICE command.\r
///\r
typedef struct {\r
- UINT16 config; ///< General Configuration.\r
- UINT16 obsolete_1;\r
- UINT16 specific_config; ///< Specific Configuration.\r
- UINT16 obsolete_3;\r
- UINT16 retired_4_5[2];\r
- UINT16 obsolete_6;\r
- UINT16 cfa_reserved_7_8[2];\r
- UINT16 retired_9;\r
- CHAR8 SerialNo[20]; ///< word 10~19\r
- UINT16 retired_20_21[2];\r
- UINT16 obsolete_22;\r
- CHAR8 FirmwareVer[8]; ///< word 23~26\r
- CHAR8 ModelName[40]; ///< word 27~46\r
- UINT16 multi_sector_cmd_max_sct_cnt;\r
- UINT16 trusted_computing_support;\r
- UINT16 capabilities_49;\r
- UINT16 capabilities_50;\r
- UINT16 obsolete_51_52[2];\r
- UINT16 field_validity;\r
- UINT16 obsolete_54_58[5];\r
- UINT16 multi_sector_setting;\r
- UINT16 user_addressable_sectors_lo;\r
- UINT16 user_addressable_sectors_hi;\r
- UINT16 obsolete_62;\r
- UINT16 multi_word_dma_mode;\r
- UINT16 advanced_pio_modes;\r
- UINT16 min_multi_word_dma_cycle_time;\r
- UINT16 rec_multi_word_dma_cycle_time;\r
- UINT16 min_pio_cycle_time_without_flow_control;\r
- UINT16 min_pio_cycle_time_with_flow_control;\r
- UINT16 additional_supported; ///< word 69\r
- UINT16 reserved_70;\r
- UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.\r
- UINT16 queue_depth;\r
- UINT16 serial_ata_capabilities;\r
- UINT16 reserved_77; ///< Reserved for Serial ATA\r
- UINT16 serial_ata_features_supported;\r
- UINT16 serial_ata_features_enabled;\r
- UINT16 major_version_no;\r
- UINT16 minor_version_no;\r
- UINT16 command_set_supported_82; ///< word 82\r
- UINT16 command_set_supported_83; ///< word 83\r
- UINT16 command_set_feature_extn; ///< word 84\r
- UINT16 command_set_feature_enb_85; ///< word 85\r
- UINT16 command_set_feature_enb_86; ///< word 86\r
- UINT16 command_set_feature_default; ///< word 87\r
- UINT16 ultra_dma_mode; ///< word 88\r
- UINT16 time_for_security_erase_unit;\r
- UINT16 time_for_enhanced_security_erase_unit;\r
- UINT16 advanced_power_management_level;\r
- UINT16 master_password_identifier;\r
- UINT16 hardware_configuration_test_result;\r
- UINT16 obsolete_94;\r
- UINT16 stream_minimum_request_size;\r
- UINT16 streaming_transfer_time_for_dma;\r
- UINT16 streaming_access_latency_for_dma_and_pio;\r
- UINT16 streaming_performance_granularity[2]; ///< word 98~99\r
- UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103\r
- UINT16 streaming_transfer_time_for_pio;\r
- UINT16 max_no_of_512byte_blocks_per_data_set_cmd;\r
- UINT16 phy_logic_sector_support; ///< word 106\r
- UINT16 interseek_delay_for_iso7779;\r
- UINT16 world_wide_name[4]; ///< word 108~111\r
- UINT16 reserved_for_128bit_wwn_112_115[4];\r
- UINT16 reserved_for_technical_report;\r
- UINT16 logic_sector_size_lo; ///< word 117\r
- UINT16 logic_sector_size_hi; ///< word 118\r
- UINT16 features_and_command_sets_supported_ext; ///< word 119\r
- UINT16 features_and_command_sets_enabled_ext; ///< word 120\r
- UINT16 reserved_121_126[6];\r
- UINT16 obsolete_127;\r
- UINT16 security_status; ///< word 128\r
- UINT16 vendor_specific_129_159[31];\r
- UINT16 cfa_power_mode; ///< word 160\r
- UINT16 reserved_for_compactflash_161_167[7];\r
- UINT16 device_nominal_form_factor;\r
- UINT16 is_data_set_cmd_supported;\r
- CHAR8 additional_product_identifier[8];\r
- UINT16 reserved_174_175[2];\r
- CHAR8 media_serial_number[60]; ///< word 176~205\r
- UINT16 sct_command_transport; ///< word 206\r
- UINT16 reserved_207_208[2];\r
- UINT16 alignment_logic_in_phy_blocks; ///< word 209\r
- UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211\r
- UINT16 verify_sector_count_mode2[2];\r
- UINT16 nv_cache_capabilities;\r
- UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215\r
- UINT16 nv_cache_size_in_logical_block_msw; ///< word 216\r
- UINT16 nominal_media_rotation_rate;\r
- UINT16 reserved_218;\r
- UINT16 nv_cache_options; ///< word 219\r
- UINT16 write_read_verify_mode; ///< word 220\r
- UINT16 reserved_221;\r
- UINT16 transport_major_revision_number;\r
- UINT16 transport_minor_revision_number;\r
- UINT16 reserved_224_229[6];\r
- UINT64 extended_no_of_addressable_sectors;\r
- UINT16 min_number_per_download_microcode_mode3; ///< word 234\r
- UINT16 max_number_per_download_microcode_mode3; ///< word 235\r
- UINT16 reserved_236_254[19];\r
- UINT16 integrity_word;\r
+ UINT16 config; ///< General Configuration.\r
+ UINT16 obsolete_1;\r
+ UINT16 specific_config; ///< Specific Configuration.\r
+ UINT16 obsolete_3;\r
+ UINT16 retired_4_5[2];\r
+ UINT16 obsolete_6;\r
+ UINT16 cfa_reserved_7_8[2];\r
+ UINT16 retired_9;\r
+ CHAR8 SerialNo[20]; ///< word 10~19\r
+ UINT16 retired_20_21[2];\r
+ UINT16 obsolete_22;\r
+ CHAR8 FirmwareVer[8]; ///< word 23~26\r
+ CHAR8 ModelName[40]; ///< word 27~46\r
+ UINT16 multi_sector_cmd_max_sct_cnt;\r
+ UINT16 trusted_computing_support;\r
+ UINT16 capabilities_49;\r
+ UINT16 capabilities_50;\r
+ UINT16 obsolete_51_52[2];\r
+ UINT16 field_validity;\r
+ UINT16 obsolete_54_58[5];\r
+ UINT16 multi_sector_setting;\r
+ UINT16 user_addressable_sectors_lo;\r
+ UINT16 user_addressable_sectors_hi;\r
+ UINT16 obsolete_62;\r
+ UINT16 multi_word_dma_mode;\r
+ UINT16 advanced_pio_modes;\r
+ UINT16 min_multi_word_dma_cycle_time;\r
+ UINT16 rec_multi_word_dma_cycle_time;\r
+ UINT16 min_pio_cycle_time_without_flow_control;\r
+ UINT16 min_pio_cycle_time_with_flow_control;\r
+ UINT16 additional_supported; ///< word 69\r
+ UINT16 reserved_70;\r
+ UINT16 reserved_71_74[4]; ///< Reserved for IDENTIFY PACKET DEVICE cmd.\r
+ UINT16 queue_depth;\r
+ UINT16 serial_ata_capabilities;\r
+ UINT16 reserved_77; ///< Reserved for Serial ATA\r
+ UINT16 serial_ata_features_supported;\r
+ UINT16 serial_ata_features_enabled;\r
+ UINT16 major_version_no;\r
+ UINT16 minor_version_no;\r
+ UINT16 command_set_supported_82; ///< word 82\r
+ UINT16 command_set_supported_83; ///< word 83\r
+ UINT16 command_set_feature_extn; ///< word 84\r
+ UINT16 command_set_feature_enb_85; ///< word 85\r
+ UINT16 command_set_feature_enb_86; ///< word 86\r
+ UINT16 command_set_feature_default; ///< word 87\r
+ UINT16 ultra_dma_mode; ///< word 88\r
+ UINT16 time_for_security_erase_unit;\r
+ UINT16 time_for_enhanced_security_erase_unit;\r
+ UINT16 advanced_power_management_level;\r
+ UINT16 master_password_identifier;\r
+ UINT16 hardware_configuration_test_result;\r
+ UINT16 obsolete_94;\r
+ UINT16 stream_minimum_request_size;\r
+ UINT16 streaming_transfer_time_for_dma;\r
+ UINT16 streaming_access_latency_for_dma_and_pio;\r
+ UINT16 streaming_performance_granularity[2]; ///< word 98~99\r
+ UINT16 maximum_lba_for_48bit_addressing[4]; ///< word 100~103\r
+ UINT16 streaming_transfer_time_for_pio;\r
+ UINT16 max_no_of_512byte_blocks_per_data_set_cmd;\r
+ UINT16 phy_logic_sector_support; ///< word 106\r
+ UINT16 interseek_delay_for_iso7779;\r
+ UINT16 world_wide_name[4]; ///< word 108~111\r
+ UINT16 reserved_for_128bit_wwn_112_115[4];\r
+ UINT16 reserved_for_technical_report;\r
+ UINT16 logic_sector_size_lo; ///< word 117\r
+ UINT16 logic_sector_size_hi; ///< word 118\r
+ UINT16 features_and_command_sets_supported_ext; ///< word 119\r
+ UINT16 features_and_command_sets_enabled_ext; ///< word 120\r
+ UINT16 reserved_121_126[6];\r
+ UINT16 obsolete_127;\r
+ UINT16 security_status; ///< word 128\r
+ UINT16 vendor_specific_129_159[31];\r
+ UINT16 cfa_power_mode; ///< word 160\r
+ UINT16 reserved_for_compactflash_161_167[7];\r
+ UINT16 device_nominal_form_factor;\r
+ UINT16 is_data_set_cmd_supported;\r
+ CHAR8 additional_product_identifier[8];\r
+ UINT16 reserved_174_175[2];\r
+ CHAR8 media_serial_number[60]; ///< word 176~205\r
+ UINT16 sct_command_transport; ///< word 206\r
+ UINT16 reserved_207_208[2];\r
+ UINT16 alignment_logic_in_phy_blocks; ///< word 209\r
+ UINT16 write_read_verify_sector_count_mode3[2]; ///< word 210~211\r
+ UINT16 verify_sector_count_mode2[2];\r
+ UINT16 nv_cache_capabilities;\r
+ UINT16 nv_cache_size_in_logical_block_lsw; ///< word 215\r
+ UINT16 nv_cache_size_in_logical_block_msw; ///< word 216\r
+ UINT16 nominal_media_rotation_rate;\r
+ UINT16 reserved_218;\r
+ UINT16 nv_cache_options; ///< word 219\r
+ UINT16 write_read_verify_mode; ///< word 220\r
+ UINT16 reserved_221;\r
+ UINT16 transport_major_revision_number;\r
+ UINT16 transport_minor_revision_number;\r
+ UINT16 reserved_224_229[6];\r
+ UINT64 extended_no_of_addressable_sectors;\r
+ UINT16 min_number_per_download_microcode_mode3; ///< word 234\r
+ UINT16 max_number_per_download_microcode_mode3; ///< word 235\r
+ UINT16 reserved_236_254[19];\r
+ UINT16 integrity_word;\r
} ATA_IDENTIFY_DATA;\r
\r
///\r
/// completion of the ATA IDENTIFY_PACKET_DEVICE command.\r
///\r
typedef struct {\r
- UINT16 config; ///< General Configuration.\r
- UINT16 reserved_1;\r
- UINT16 specific_config; ///< Specific Configuration.\r
- UINT16 reserved_3_9[7];\r
- CHAR8 SerialNo[20]; ///< word 10~19\r
- UINT16 reserved_20_22[3];\r
- CHAR8 FirmwareVer[8]; ///< word 23~26\r
- CHAR8 ModelName[40]; ///< word 27~46\r
- UINT16 reserved_47_48[2];\r
- UINT16 capabilities_49;\r
- UINT16 capabilities_50;\r
- UINT16 obsolete_51;\r
- UINT16 reserved_52;\r
- UINT16 field_validity; ///< word 53\r
- UINT16 reserved_54_61[8];\r
- UINT16 dma_dir;\r
- UINT16 multi_word_dma_mode; ///< word 63\r
- UINT16 advanced_pio_modes; ///< word 64\r
- UINT16 min_multi_word_dma_cycle_time;\r
- UINT16 rec_multi_word_dma_cycle_time;\r
- UINT16 min_pio_cycle_time_without_flow_control;\r
- UINT16 min_pio_cycle_time_with_flow_control;\r
- UINT16 reserved_69_70[2];\r
- UINT16 obsolete_71_72[2];\r
- UINT16 reserved_73_74[2];\r
- UINT16 obsolete_75;\r
- UINT16 serial_ata_capabilities;\r
- UINT16 reserved_77; ///< Reserved for Serial ATA\r
- UINT16 serial_ata_features_supported;\r
- UINT16 serial_ata_features_enabled;\r
- UINT16 major_version_no; ///< word 80\r
- UINT16 minor_version_no; ///< word 81\r
- UINT16 cmd_set_support_82;\r
- UINT16 cmd_set_support_83;\r
- UINT16 cmd_feature_support;\r
- UINT16 cmd_feature_enable_85;\r
- UINT16 cmd_feature_enable_86;\r
- UINT16 cmd_feature_default;\r
- UINT16 ultra_dma_select;\r
- UINT16 time_required_for_sec_erase; ///< word 89\r
- UINT16 time_required_for_enhanced_sec_erase; ///< word 90\r
- UINT16 advanced_power_management_level;\r
- UINT16 master_pwd_revison_code;\r
- UINT16 hardware_reset_result; ///< word 93\r
- UINT16 obsolete_94;\r
- UINT16 reserved_95_107[13];\r
- UINT16 world_wide_name[4]; ///< word 108~111\r
- UINT16 reserved_for_128bit_wwn_112_115[4];\r
- UINT16 reserved_116_118[3];\r
- UINT16 command_and_feature_sets_supported; ///< word 119\r
- UINT16 command_and_feature_sets_supported_enabled;\r
- UINT16 reserved_121_124[4];\r
- UINT16 atapi_byte_count_0_behavior; ///< word 125\r
- UINT16 obsolete_126_127[2];\r
- UINT16 security_status;\r
- UINT16 reserved_129_159[31];\r
- UINT16 cfa_reserved_160_175[16];\r
- UINT16 reserved_176_221[46];\r
- UINT16 transport_major_version;\r
- UINT16 transport_minor_version;\r
- UINT16 reserved_224_254[31];\r
- UINT16 integrity_word;\r
+ UINT16 config; ///< General Configuration.\r
+ UINT16 reserved_1;\r
+ UINT16 specific_config; ///< Specific Configuration.\r
+ UINT16 reserved_3_9[7];\r
+ CHAR8 SerialNo[20]; ///< word 10~19\r
+ UINT16 reserved_20_22[3];\r
+ CHAR8 FirmwareVer[8]; ///< word 23~26\r
+ CHAR8 ModelName[40]; ///< word 27~46\r
+ UINT16 reserved_47_48[2];\r
+ UINT16 capabilities_49;\r
+ UINT16 capabilities_50;\r
+ UINT16 obsolete_51;\r
+ UINT16 reserved_52;\r
+ UINT16 field_validity; ///< word 53\r
+ UINT16 reserved_54_61[8];\r
+ UINT16 dma_dir;\r
+ UINT16 multi_word_dma_mode; ///< word 63\r
+ UINT16 advanced_pio_modes; ///< word 64\r
+ UINT16 min_multi_word_dma_cycle_time;\r
+ UINT16 rec_multi_word_dma_cycle_time;\r
+ UINT16 min_pio_cycle_time_without_flow_control;\r
+ UINT16 min_pio_cycle_time_with_flow_control;\r
+ UINT16 reserved_69_70[2];\r
+ UINT16 obsolete_71_72[2];\r
+ UINT16 reserved_73_74[2];\r
+ UINT16 obsolete_75;\r
+ UINT16 serial_ata_capabilities;\r
+ UINT16 reserved_77; ///< Reserved for Serial ATA\r
+ UINT16 serial_ata_features_supported;\r
+ UINT16 serial_ata_features_enabled;\r
+ UINT16 major_version_no; ///< word 80\r
+ UINT16 minor_version_no; ///< word 81\r
+ UINT16 cmd_set_support_82;\r
+ UINT16 cmd_set_support_83;\r
+ UINT16 cmd_feature_support;\r
+ UINT16 cmd_feature_enable_85;\r
+ UINT16 cmd_feature_enable_86;\r
+ UINT16 cmd_feature_default;\r
+ UINT16 ultra_dma_select;\r
+ UINT16 time_required_for_sec_erase; ///< word 89\r
+ UINT16 time_required_for_enhanced_sec_erase; ///< word 90\r
+ UINT16 advanced_power_management_level;\r
+ UINT16 master_pwd_revison_code;\r
+ UINT16 hardware_reset_result; ///< word 93\r
+ UINT16 obsolete_94;\r
+ UINT16 reserved_95_107[13];\r
+ UINT16 world_wide_name[4]; ///< word 108~111\r
+ UINT16 reserved_for_128bit_wwn_112_115[4];\r
+ UINT16 reserved_116_118[3];\r
+ UINT16 command_and_feature_sets_supported; ///< word 119\r
+ UINT16 command_and_feature_sets_supported_enabled;\r
+ UINT16 reserved_121_124[4];\r
+ UINT16 atapi_byte_count_0_behavior; ///< word 125\r
+ UINT16 obsolete_126_127[2];\r
+ UINT16 security_status;\r
+ UINT16 reserved_129_159[31];\r
+ UINT16 cfa_reserved_160_175[16];\r
+ UINT16 reserved_176_221[46];\r
+ UINT16 transport_major_version;\r
+ UINT16 transport_minor_version;\r
+ UINT16 reserved_224_254[31];\r
+ UINT16 integrity_word;\r
} ATAPI_IDENTIFY_DATA;\r
\r
-\r
///\r
/// Standard Quiry Data format, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 peripheral_type;\r
- UINT8 RMB;\r
- UINT8 version;\r
- UINT8 response_data_format;\r
- UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 vendor_info[8];\r
- UINT8 product_id[16];\r
- UINT8 product_revision_level[4];\r
- UINT8 vendor_specific_36_55[55 - 36 + 1];\r
- UINT8 reserved_56_95[95 - 56 + 1];\r
+ UINT8 peripheral_type;\r
+ UINT8 RMB;\r
+ UINT8 version;\r
+ UINT8 response_data_format;\r
+ UINT8 addnl_length; ///< n - 4, Numbers of bytes following this one.\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 reserved_7;\r
+ UINT8 vendor_info[8];\r
+ UINT8 product_id[16];\r
+ UINT8 product_revision_level[4];\r
+ UINT8 vendor_specific_36_55[55 - 36 + 1];\r
+ UINT8 reserved_56_95[95 - 56 + 1];\r
///\r
/// Vendor-specific parameters fields. The sizeof (ATAPI_INQUIRY_DATA) is 254\r
/// since allocation_length is one byte in ATAPI_INQUIRY_CMD.\r
///\r
- UINT8 vendor_specific_96_253[253 - 96 + 1];\r
+ UINT8 vendor_specific_96_253[253 - 96 + 1];\r
} ATAPI_INQUIRY_DATA;\r
\r
///\r
/// Request Sense Standard Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 error_code : 7;\r
- UINT8 valid : 1;\r
- UINT8 reserved_1;\r
- UINT8 sense_key : 4;\r
- UINT8 reserved_2 : 1;\r
- UINT8 Vendor_specifc_1 : 3;\r
- UINT8 vendor_specific_3;\r
- UINT8 vendor_specific_4;\r
- UINT8 vendor_specific_5;\r
- UINT8 vendor_specific_6;\r
- UINT8 addnl_sense_length; ///< n - 7\r
- UINT8 vendor_specific_8;\r
- UINT8 vendor_specific_9;\r
- UINT8 vendor_specific_10;\r
- UINT8 vendor_specific_11;\r
- UINT8 addnl_sense_code; ///< mandatory\r
- UINT8 addnl_sense_code_qualifier; ///< mandatory\r
- UINT8 field_replaceable_unit_code; ///< optional\r
- UINT8 sense_key_specific_15 : 7;\r
- UINT8 SKSV : 1;\r
- UINT8 sense_key_specific_16;\r
- UINT8 sense_key_specific_17;\r
+ UINT8 error_code : 7;\r
+ UINT8 valid : 1;\r
+ UINT8 reserved_1;\r
+ UINT8 sense_key : 4;\r
+ UINT8 reserved_2 : 1;\r
+ UINT8 Vendor_specifc_1 : 3;\r
+ UINT8 vendor_specific_3;\r
+ UINT8 vendor_specific_4;\r
+ UINT8 vendor_specific_5;\r
+ UINT8 vendor_specific_6;\r
+ UINT8 addnl_sense_length; ///< n - 7\r
+ UINT8 vendor_specific_8;\r
+ UINT8 vendor_specific_9;\r
+ UINT8 vendor_specific_10;\r
+ UINT8 vendor_specific_11;\r
+ UINT8 addnl_sense_code; ///< mandatory\r
+ UINT8 addnl_sense_code_qualifier; ///< mandatory\r
+ UINT8 field_replaceable_unit_code; ///< optional\r
+ UINT8 sense_key_specific_15 : 7;\r
+ UINT8 SKSV : 1;\r
+ UINT8 sense_key_specific_16;\r
+ UINT8 sense_key_specific_17;\r
} ATAPI_REQUEST_SENSE_DATA;\r
\r
///\r
/// READ CAPACITY Data, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 BlockSize3;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
+ UINT8 LastLba3;\r
+ UINT8 LastLba2;\r
+ UINT8 LastLba1;\r
+ UINT8 LastLba0;\r
+ UINT8 BlockSize3;\r
+ UINT8 BlockSize2;\r
+ UINT8 BlockSize1;\r
+ UINT8 BlockSize0;\r
} ATAPI_READ_CAPACITY_DATA;\r
\r
///\r
/// defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 reserved_0;\r
- UINT8 reserved_1;\r
- UINT8 reserved_2;\r
- UINT8 Capacity_Length;\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 DesCode : 2;\r
- UINT8 reserved_9 : 6;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
+ UINT8 reserved_0;\r
+ UINT8 reserved_1;\r
+ UINT8 reserved_2;\r
+ UINT8 Capacity_Length;\r
+ UINT8 LastLba3;\r
+ UINT8 LastLba2;\r
+ UINT8 LastLba1;\r
+ UINT8 LastLba0;\r
+ UINT8 DesCode : 2;\r
+ UINT8 reserved_9 : 6;\r
+ UINT8 BlockSize2;\r
+ UINT8 BlockSize1;\r
+ UINT8 BlockSize0;\r
} ATAPI_READ_FORMAT_CAPACITY_DATA;\r
\r
///\r
/// Test Unit Ready Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1;\r
+ UINT8 reserved_2;\r
+ UINT8 reserved_3;\r
+ UINT8 reserved_4;\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 reserved_7;\r
+ UINT8 reserved_8;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_TEST_UNIT_READY_CMD;\r
\r
///\r
/// INQUIRY Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 page_code; ///< defined in SFF8090i, V6\r
- UINT8 reserved_3;\r
- UINT8 allocation_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1 : 5;\r
+ UINT8 lun : 3;\r
+ UINT8 page_code; ///< defined in SFF8090i, V6\r
+ UINT8 reserved_3;\r
+ UINT8 allocation_length;\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 reserved_7;\r
+ UINT8 reserved_8;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_INQUIRY_CMD;\r
\r
///\r
/// REQUEST SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 allocation_length;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 reserved_7;\r
- UINT8 reserved_8;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1 : 5;\r
+ UINT8 lun : 3;\r
+ UINT8 reserved_2;\r
+ UINT8 reserved_3;\r
+ UINT8 allocation_length;\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 reserved_7;\r
+ UINT8 reserved_8;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_REQUEST_SENSE_CMD;\r
\r
///\r
/// READ (10) Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 Lba0;\r
- UINT8 Lba1;\r
- UINT8 Lba2;\r
- UINT8 Lba3;\r
- UINT8 reserved_6;\r
- UINT8 TranLen0;\r
- UINT8 TranLen1;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1 : 5;\r
+ UINT8 lun : 3;\r
+ UINT8 Lba0;\r
+ UINT8 Lba1;\r
+ UINT8 Lba2;\r
+ UINT8 Lba3;\r
+ UINT8 reserved_6;\r
+ UINT8 TranLen0;\r
+ UINT8 TranLen1;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_READ10_CMD;\r
\r
///\r
/// READ Format Capacity Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 reserved_2;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 allocation_length_hi;\r
- UINT8 allocation_length_lo;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1 : 5;\r
+ UINT8 lun : 3;\r
+ UINT8 reserved_2;\r
+ UINT8 reserved_3;\r
+ UINT8 reserved_4;\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 allocation_length_hi;\r
+ UINT8 allocation_length_lo;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_READ_FORMAT_CAP_CMD;\r
\r
///\r
/// MODE SENSE Command, defined in SFF-8070i(ATAPI Removable Rewritable Specification).\r
///\r
typedef struct {\r
- UINT8 opcode;\r
- UINT8 reserved_1 : 5;\r
- UINT8 lun : 3;\r
- UINT8 page_code : 6;\r
- UINT8 page_control : 2;\r
- UINT8 reserved_3;\r
- UINT8 reserved_4;\r
- UINT8 reserved_5;\r
- UINT8 reserved_6;\r
- UINT8 parameter_list_length_hi;\r
- UINT8 parameter_list_length_lo;\r
- UINT8 reserved_9;\r
- UINT8 reserved_10;\r
- UINT8 reserved_11;\r
+ UINT8 opcode;\r
+ UINT8 reserved_1 : 5;\r
+ UINT8 lun : 3;\r
+ UINT8 page_code : 6;\r
+ UINT8 page_control : 2;\r
+ UINT8 reserved_3;\r
+ UINT8 reserved_4;\r
+ UINT8 reserved_5;\r
+ UINT8 reserved_6;\r
+ UINT8 parameter_list_length_hi;\r
+ UINT8 parameter_list_length_lo;\r
+ UINT8 reserved_9;\r
+ UINT8 reserved_10;\r
+ UINT8 reserved_11;\r
} ATAPI_MODE_SENSE_CMD;\r
\r
///\r
/// We add it here for the convenience of ATA/ATAPI module writers.\r
///\r
typedef union {\r
- UINT16 Data16[6];\r
- ATAPI_TEST_UNIT_READY_CMD TestUnitReady;\r
- ATAPI_READ10_CMD Read10;\r
- ATAPI_REQUEST_SENSE_CMD RequestSence;\r
- ATAPI_INQUIRY_CMD Inquiry;\r
- ATAPI_MODE_SENSE_CMD ModeSense;\r
- ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
+ UINT16 Data16[6];\r
+ ATAPI_TEST_UNIT_READY_CMD TestUnitReady;\r
+ ATAPI_READ10_CMD Read10;\r
+ ATAPI_REQUEST_SENSE_CMD RequestSence;\r
+ ATAPI_INQUIRY_CMD Inquiry;\r
+ ATAPI_MODE_SENSE_CMD ModeSense;\r
+ ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
} ATAPI_PACKET_COMMAND;\r
\r
#pragma pack()\r
\r
-\r
-#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000\r
-#define ATAPI_MAX_DMA_CMD_SECTORS 0x100\r
+#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000\r
+#define ATAPI_MAX_DMA_CMD_SECTORS 0x100\r
\r
// ATA/ATAPI Signature equates\r
-#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3\r
-#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3\r
-#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3\r
+#define ATA_SIGNATURE 0x0101 ///< defined in ACS-3\r
+#define ATAPI_SIGNATURE 0xeb14 ///< defined in ACS-3\r
+#define ATAPI_SIGNATURE_32 0xeb140101 ///< defined in ACS-3\r
\r
// Spin Up Configuration definitions\r
-#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3\r
-#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3\r
-#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3\r
-#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3\r
+#define ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE 0x37c8 ///< defined in ACS-3\r
+#define ATA_SPINUP_CFG_REQUIRED_IDD_COMPLETE 0x738c ///< defined in ACS-3\r
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE 0x8c73 ///< defined in ACS-3\r
+#define ATA_SPINUP_CFG_NOT_REQUIRED_IDD_COMPLETE 0xc837 ///< defined in ACS-3\r
\r
//\r
// ATA Packet Command Code\r
//\r
-#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3\r
-#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3\r
-#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3\r
-#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3\r
-#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1\r
-#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4\r
-#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices\r
-#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices\r
-\r
-#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices\r
- #define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices\r
- #define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices\r
- #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
- #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices\r
- #define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices\r
-\r
-#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices\r
-\r
- #define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices\r
- #define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_CMD_FORMAT_UNIT 0x04 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_SOFT_RESET 0x08 ///< defined from ATA-3\r
+#define ATA_CMD_PACKET 0xA0 ///< defined from ATA-3\r
+#define ATA_CMD_IDENTIFY_DEVICE 0xA1 ///< defined from ATA-3\r
+#define ATA_CMD_SERVICE 0xA2 ///< defined from ATA-3\r
+#define ATA_CMD_TEST_UNIT_READY 0x00 ///< defined from ATA-1\r
+#define ATA_CMD_REQUEST_SENSE 0x03 ///< defined from ATA-4\r
+#define ATA_CMD_INQUIRY 0x12 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_FORMAT_CAPACITY 0x23 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_CAPACITY 0x25 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_10 0x28 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_10 0x2A ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_ATAPI_SEEK 0x2B ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_AND_VERIFY 0x2E ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_VERIFY 0x2F ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_READ_12 0xA8 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_WRITE_12 0xAA ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_START_STOP_UNIT 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL 0x1E ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_CMD_MODE_SELECT 0x55 ///< defined in ATAPI Removable Rewritable Media Devices\r
+\r
+#define ATA_CMD_MODE_SENSE 0x5A ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_PAGE_CODE_READ_WRITE_ERROR 0x01 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_PAGE_CODE_CACHING_PAGE 0x08 ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES 0x1B ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_PAGE_CODE_TIMER_PROTECT_PAGE 0x1C ///< defined in ATAPI Removable Rewritable Media Devices\r
+#define ATA_PAGE_CODE_RETURN_ALL_PAGES 0x3F ///< defined in ATAPI Removable Rewritable Media Devices\r
+\r
+#define ATA_CMD_GET_CONFIGURATION 0x46 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_GCCD_RT_FIELD_VALUE_ALL 0x00 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_GCCD_RT_FIELD_VALUE_CURRENT 0x01 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_GCCD_RT_FIELD_VALUE_SINGLE 0x02 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_GCCD_RT_FIELD_VALUE_RESERVED 0x03 ///< defined in ATAPI Multimedia Devices\r
+\r
+#define ATA_FEATURE_LIST_PROFILE_LIST 0x0000 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_FEATURE_LIST_CORE 0x0001 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_FEATURE_LIST_MORPHING 0x0002 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM 0x0003 ///< defined in ATAPI Multimedia Devices\r
+#define ATA_FEATURE_LIST_WRITE_PROTECT 0x0004 ///< defined in ATAPI Multimedia Devices\r
\r
///\r
/// Start/Stop and Eject Operations\r
///\r
///@{\r
-#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc\r
-#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type\r
-#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible\r
-#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)\r
+#define ATA_CMD_SUBOP_STOP_DISC 0x00 ///< Stop the Disc\r
+#define ATA_CMD_SUBOP_START_DISC 0x01 ///< Start the Disc and acquire the format type\r
+#define ATA_CMD_SUBOP_EJECT_DISC 0x02 ///< Eject the Disc if possible\r
+#define ATA_CMD_SUBOP_CLOSE_TRAY 0x03 ///< Load the Disc (Close Tray)\r
///@}\r
\r
//\r
//\r
// Class 1: PIO Data-In Commands\r
//\r
-#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3\r
-#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1\r
-#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1\r
-#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6\r
-#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3\r
-#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3\r
-#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3\r
+#define ATA_CMD_IDENTIFY_DRIVE 0xec ///< defined from ATA-3\r
+#define ATA_CMD_READ_BUFFER 0xe4 ///< defined from ATA-1\r
+#define ATA_CMD_READ_SECTORS 0x20 ///< defined from ATA-1\r
+#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_READ_LONG 0x22 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined from ATA-6\r
+#define ATA_CMD_READ_MULTIPLE 0xc4 ///< defined in ACS-3\r
+#define ATA_CMD_READ_MULTIPLE_EXT 0x29 ///< defined in ACS-3\r
+#define ATA_CMD_READ_LOG_EXT 0x2f ///< defined in ACS-3\r
\r
//\r
// Class 2: PIO Data-Out Commands\r
//\r
-#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1\r
-#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1\r
-#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6\r
-#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3\r
-#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3\r
+#define ATA_CMD_FORMAT_TRACK 0x50 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_WRITE_BUFFER 0xe8 ///< defined from ATA-1\r
+#define ATA_CMD_WRITE_SECTORS 0x30 ///< defined from ATA-1\r
+#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_WRITE_LONG 0x32 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_WRITE_VERIFY 0x3c ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_WRITE_SECTORS_EXT 0x34 ///< defined from ATA-6\r
+#define ATA_CMD_WRITE_MULTIPLE 0xc5 ///< defined in ACS-3\r
+#define ATA_CMD_WRITE_MULTIPLE_EXT 0x39 ///< defined in ACS-3\r
\r
//\r
// Class 3 No Data Command\r
//\r
-#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3\r
-#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3\r
-#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1\r
-#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1\r
-#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1\r
-#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1\r
-#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1\r
-#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1\r
-#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6\r
-#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3\r
-#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2\r
-#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1\r
-#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1\r
-#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1\r
-#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1\r
-#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1\r
-#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3\r
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6\r
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6\r
+#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_BOOT_POST_BOOT 0xdc ///< defined from ATA-1, obsoleted from ATA-3\r
+#define ATA_CMD_BOOT_PRE_BOOT 0xdd ///< defined from ATA-1, obsoleted from ATA-3\r
+#define ATA_CMD_CHECK_POWER_MODE 0x98 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5 ///< defined from ATA-1\r
+#define ATA_CMD_DOOR_LOCK 0xde ///< defined from ATA-1\r
+#define ATA_CMD_DOOR_UNLOCK 0xdf ///< defined from ATA-1\r
+#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ///< defined from ATA-1\r
+#define ATA_CMD_IDLE_ALIAS 0x97 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_IDLE 0xe3 ///< defined from ATA-1\r
+#define ATA_CMD_IDLE_IMMEDIATE 0x95 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1 ///< defined from ATA-1\r
+#define ATA_CMD_INIT_DRIVE_PARAM 0x91 ///< defined from ATA-1, obsoleted from ATA-6\r
+#define ATA_CMD_RECALIBRATE 0x10 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_READ_DRIVE_STATE 0xe9 ///< defined from ATA-1, obsoleted from ATA-3\r
+#define ATA_CMD_SET_MULTIPLE_MODE 0xC6 ///< defined from ATA-2\r
+#define ATA_CMD_READ_VERIFY 0x40 ///< defined from ATA-1\r
+#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_SEEK 0x70 ///< defined from ATA-1\r
+#define ATA_CMD_SET_FEATURES 0xef ///< defined from ATA-1\r
+#define ATA_CMD_STANDBY 0x96 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_STANDBY_ALIAS 0xe2 ///< defined from ATA-1\r
+#define ATA_CMD_STANDBY_IMMEDIATE 0x94 ///< defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0 ///< defined from ATA-1\r
+#define ATA_CMD_SLEEP 0xe6 ///< defined in ACS-3\r
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xf8 ///< defined in ATA-6\r
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27 ///< defined in ATA-6\r
\r
//\r
// Set Features Sub Command\r
//\r
-#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3\r
-#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3\r
-#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE 0x02 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_SET_TRANSFER_MODE 0x03 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_APM 0x05 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_PUIS 0x06 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP 0x07 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY 0x0b ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE 0x10 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION 0x31 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL 0x41 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE 0x42 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES 0x43 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS 0x4a ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD 0x55 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE 0x63 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS 0x66 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE 0x82 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_APM 0x85 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_PUIS 0x86 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY 0x8b ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE 0x90 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION 0x95 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD 0xaa ///< defined in ACS-3\r
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL 0xc1 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE 0xc2 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING 0xc3 ///< defined in ACS-3\r
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS 0xcc ///< defined in ACS-3\r
\r
//\r
// S.M.A.R.T\r
//\r
-#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3\r
-#define ATA_CONSTANT_C2 0xc2 ///< reserved\r
-#define ATA_CONSTANT_4F 0x4f ///< reserved\r
-\r
-#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3\r
-\r
-#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3\r
- #define ATA_AUTOSAVE_DISABLE_ATTR 0x00\r
- #define ATA_AUTOSAVE_ENABLE_ATTR 0xf1\r
-\r
-#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3\r
- #define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3\r
- #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3\r
-\r
-#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3\r
-#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3\r
-#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved\r
-#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3\r
-#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3\r
-\r
-#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3\r
-#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3\r
+#define ATA_CMD_SMART 0xb0 ///< defined from ATA-3\r
+#define ATA_CONSTANT_C2 0xc2 ///< reserved\r
+#define ATA_CONSTANT_4F 0x4f ///< reserved\r
+\r
+#define ATA_SMART_READ_DATA 0xd0 ///< defined in ACS-3\r
+\r
+#define ATA_SMART_AUTOSAVE 0xd2 ///< defined in ACS-3\r
+#define ATA_AUTOSAVE_DISABLE_ATTR 0x00\r
+#define ATA_AUTOSAVE_ENABLE_ATTR 0xf1\r
+\r
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE 0xd4 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_OFFLINE_ROUTINE 0x00 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST 0x01 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST 0x02 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_OFFLINE_CONVEYANCE_SELFTEST 0x03 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_OFFLINE_SELECTIVE_SELFTEST 0x04 ///< defined in ACS-3\r
+#define ATA_SMART_ABORT_SELF_TEST_SUBROUTINE 0x7f ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_CAPTIVE_SHORT_SELFTEST 0x81 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_CAPTIVE_EXTENDED_SELFTEST 0x82 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST 0x83 ///< defined in ACS-3\r
+#define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST 0x84 ///< defined in ACS-3\r
+\r
+#define ATA_SMART_READLOG 0xd5 ///< defined in ACS-3\r
+#define ATA_SMART_WRITELOG 0xd6 ///< defined in ACS-3\r
+#define ATA_SMART_ENABLE_OPERATION 0xd8 ///< reserved\r
+#define ATA_SMART_DISABLE_OPERATION 0xd9 ///< defined in ACS-3\r
+#define ATA_SMART_RETURN_STATUS 0xda ///< defined from ATA-3\r
+\r
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE 0xc24f ///< defined in ACS-3\r
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE 0x2cf4 ///< defined in ACS-3\r
\r
// SMART Log Definitions\r
-#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3\r
-#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3\r
-#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3\r
-#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3\r
-#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3\r
-#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3\r
-#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3\r
-#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3\r
-#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3\r
+#define ATA_SMART_LOG_DIRECTORY 0x00 ///< defined in ACS-3\r
+#define ATA_SMART_SUM_SMART_ERROR_LOG 0x01 ///< defined in ACS-3\r
+#define ATA_SMART_COMP_SMART_ERROR_LOG 0x02 ///< defined in ACS-3\r
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG 0x03 ///< defined in ACS-3\r
+#define ATA_SMART_SMART_SELFTEST_LOG 0x06 ///< defined in ACS-3\r
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG 0x07 ///< defined in ACS-3\r
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG 0x09 ///< defined in ACS-3\r
+#define ATA_SMART_HOST_VENDOR_SPECIFIC 0x80 ///< defined in ACS-3\r
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC 0xa0 ///< defined in ACS-3\r
\r
//\r
// Class 4: DMA Command\r
//\r
-#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1\r
-#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5\r
-#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6\r
-#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1\r
-#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-\r
-#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6\r
+#define ATA_CMD_READ_DMA 0xc8 ///< defined from ATA-1\r
+#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9 ///< defined from ATA-1, obsoleted from ATA-5\r
+#define ATA_CMD_READ_DMA_EXT 0x25 ///< defined from ATA-6\r
+#define ATA_CMD_WRITE_DMA 0xca ///< defined from ATA-1\r
+#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined from ATA-1, obsoleted from ATA-\r
+#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined from ATA-6\r
\r
//\r
// ATA Security commands\r
//\r
-#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3\r
-#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3\r
-#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3\r
-#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3\r
-#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3\r
-#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_SET_PASSWORD 0xf1 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_UNLOCK 0xf2 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_ERASE_PREPARE 0xf3 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_ERASE_UNIT 0xf4 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_FREEZE_LOCK 0xf5 ///< defined in ACS-3\r
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD 0xf6 ///< defined in ACS-3\r
\r
-#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3\r
+#define ATA_SECURITY_BUFFER_LENGTH 512 ///< defined in ACS-3\r
\r
//\r
// ATA Device Config Overlay\r
//\r
-#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6\r
- #define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6\r
- #define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6\r
- #define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6\r
- #define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6\r
+#define ATA_CMD_DEV_CONFIG_OVERLAY 0xb1 ///< defined from ATA-6\r
+#define ATA_CMD_DEV_CONFIG_RESTORE_FEATURE 0xc0 ///< defined from ATA-6\r
+#define ATA_CMD_DEV_CONFIG_FREEZELOCK_FEATURE 0xc1 ///< defined from ATA-6\r
+#define ATA_CMD_DEV_CONFIG_IDENTIFY_FEATURE 0xc2 ///< defined from ATA-6\r
+#define ATA_CMD_DEV_CONFIG_SET_FEATURE 0xc3 ///< defined from ATA-6\r
\r
//\r
// ATA Trusted Computing Feature Set Commands\r
//\r
-#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3\r
-#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3\r
-#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3\r
-#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3\r
-#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3\r
+#define ATA_CMD_TRUSTED_NON_DATA 0x5b ///< defined in ACS-3\r
+#define ATA_CMD_TRUSTED_RECEIVE 0x5c ///< defined in ACS-3\r
+#define ATA_CMD_TRUSTED_RECEIVE_DMA 0x5d ///< defined in ACS-3\r
+#define ATA_CMD_TRUSTED_SEND 0x5e ///< defined in ACS-3\r
+#define ATA_CMD_TRUSTED_SEND_DMA 0x5f ///< defined in ACS-3\r
\r
//\r
// ATA Trusted Receive Fields\r
//\r
-#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3\r
-#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3\r
-#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3\r
-#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3\r
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION 0x00 ///< defined in ACS-3\r
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED 0xec ///< defined in ACS-3\r
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED 0xed ///< defined in ACS-3\r
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED 0xee ///< defined in ACS-3\r
\r
//\r
// Equates used for Acoustic Flags\r
//\r
-#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6\r
-#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6\r
-#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6\r
+#define ATA_ACOUSTIC_LEVEL_BYPASS 0xff ///< defined from ATA-6\r
+#define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE 0xfe ///< defined from ATA-6\r
+#define ATA_ACOUSTIC_LEVEL_QUIET 0x80 ///< defined from ATA-6\r
\r
//\r
// Equates used for DiPM Support\r
//\r
-#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions\r
- #define ATA_DIPM_ENABLE 0x10 // defined in ACS-3\r
- #define ATA_DIPM_DISABLE 0x90 // defined in ACS-3\r
+#define ATA_CMD_DIPM_SUB 0x03 // defined in ACS-3 : Count value in SetFeature identification : 03h Device-initiated interface power state transitions\r
+#define ATA_DIPM_ENABLE 0x10 // defined in ACS-3\r
+#define ATA_DIPM_DISABLE 0x90 // defined in ACS-3\r
\r
//\r
// Equates used for DevSleep Support\r
//\r
-#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep\r
- #define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec\r
- #define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec\r
+#define ATA_CMD_DEVSLEEP_SUB 0x09 // defined in SATA 3.2 Gold Spec : Count value in SetFeature identification : 09h Device Sleep\r
+#define ATA_DEVSLEEP_ENABLE 0x10 // defined in SATA 3.2 Gold Spec\r
+#define ATA_DEVSLEEP_DISABLE 0x90 // defined in SATA 3.2 Gold Spec\r
\r
-#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms\r
-#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us\r
-#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms\r
+#define ATA_DEVSLP_EXIT_TIMEOUT 20 // MDAT - 20 ms\r
+#define ATA_DEVSLP_MINIMUM_DETECTION_TIME 10 // DMDT - 10 us\r
+#define ATA_DEVSLP_MINIMUM_ASSERTION_TIME 10 // DETO - 10 ms\r
\r
//\r
// Set MAX Commands\r
//\r
-#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6\r
-#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6\r
- #define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6\r
- #define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6\r
- #define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6\r
- #define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6\r
+#define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37 ///< defined from ATA-6\r
+#define ATA_CMD_SET_MAX_ADDRESS 0xf9 ///< defined from ATA-6\r
+#define ATA_SET_MAX_SET_PASSWORD 0x01 ///< defined from ATA-6\r
+#define ATA_SET_MAX_LOCK 0x02 ///< defined from ATA-6\r
+#define ATA_SET_MAX_UNLOCK 0x03 ///< defined from ATA-6\r
+#define ATA_SET_MAX_FREEZE_LOCK 0x04 ///< defined from ATA-6\r
\r
///\r
/// Default content of device control register, disable INT,\r
/// Bit3 is set to 1 according ATA-1\r
///\r
-#define ATA_DEFAULT_CTL (0x0a)\r
+#define ATA_DEFAULT_CTL (0x0a)\r
///\r
/// Default context of Device/Head Register,\r
/// Bit7 and Bit5 are set to 1 for back-compatibilities.\r
///\r
-#define ATA_DEFAULT_CMD (0xa0)\r
+#define ATA_DEFAULT_CMD (0xa0)\r
\r
-#define ATAPI_MAX_BYTE_COUNT (0xfffe)\r
+#define ATAPI_MAX_BYTE_COUNT (0xfffe)\r
\r
-#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i\r
+#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i\r
\r
//\r
// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier\r
//\r
// Sense Key\r
//\r
-#define ATA_SK_NO_SENSE (0x0)\r
-#define ATA_SK_RECOVERY_ERROR (0x1)\r
-#define ATA_SK_NOT_READY (0x2)\r
-#define ATA_SK_MEDIUM_ERROR (0x3)\r
-#define ATA_SK_HARDWARE_ERROR (0x4)\r
-#define ATA_SK_ILLEGAL_REQUEST (0x5)\r
-#define ATA_SK_UNIT_ATTENTION (0x6)\r
-#define ATA_SK_DATA_PROTECT (0x7)\r
-#define ATA_SK_BLANK_CHECK (0x8)\r
-#define ATA_SK_VENDOR_SPECIFIC (0x9)\r
-#define ATA_SK_RESERVED_A (0xA)\r
-#define ATA_SK_ABORT (0xB)\r
-#define ATA_SK_RESERVED_C (0xC)\r
-#define ATA_SK_OVERFLOW (0xD)\r
-#define ATA_SK_MISCOMPARE (0xE)\r
-#define ATA_SK_RESERVED_F (0xF)\r
+#define ATA_SK_NO_SENSE (0x0)\r
+#define ATA_SK_RECOVERY_ERROR (0x1)\r
+#define ATA_SK_NOT_READY (0x2)\r
+#define ATA_SK_MEDIUM_ERROR (0x3)\r
+#define ATA_SK_HARDWARE_ERROR (0x4)\r
+#define ATA_SK_ILLEGAL_REQUEST (0x5)\r
+#define ATA_SK_UNIT_ATTENTION (0x6)\r
+#define ATA_SK_DATA_PROTECT (0x7)\r
+#define ATA_SK_BLANK_CHECK (0x8)\r
+#define ATA_SK_VENDOR_SPECIFIC (0x9)\r
+#define ATA_SK_RESERVED_A (0xA)\r
+#define ATA_SK_ABORT (0xB)\r
+#define ATA_SK_RESERVED_C (0xC)\r
+#define ATA_SK_OVERFLOW (0xD)\r
+#define ATA_SK_MISCOMPARE (0xE)\r
+#define ATA_SK_RESERVED_F (0xF)\r
\r
//\r
// Additional Sense Codes\r
//\r
-#define ATA_ASC_NOT_READY (0x04)\r
-#define ATA_ASC_MEDIA_ERR1 (0x10)\r
-#define ATA_ASC_MEDIA_ERR2 (0x11)\r
-#define ATA_ASC_MEDIA_ERR3 (0x14)\r
-#define ATA_ASC_MEDIA_ERR4 (0x30)\r
-#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)\r
-#define ATA_ASC_INVALID_CMD (0x20)\r
-#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)\r
-#define ATA_ASC_INVALID_FIELD (0x24)\r
-#define ATA_ASC_WRITE_PROTECTED (0x27)\r
-#define ATA_ASC_MEDIA_CHANGE (0x28)\r
-#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.\r
-#define ATA_ASC_ILLEGAL_FIELD (0x26)\r
-#define ATA_ASC_NO_MEDIA (0x3A)\r
-#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
+#define ATA_ASC_NOT_READY (0x04)\r
+#define ATA_ASC_MEDIA_ERR1 (0x10)\r
+#define ATA_ASC_MEDIA_ERR2 (0x11)\r
+#define ATA_ASC_MEDIA_ERR3 (0x14)\r
+#define ATA_ASC_MEDIA_ERR4 (0x30)\r
+#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)\r
+#define ATA_ASC_INVALID_CMD (0x20)\r
+#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)\r
+#define ATA_ASC_INVALID_FIELD (0x24)\r
+#define ATA_ASC_WRITE_PROTECTED (0x27)\r
+#define ATA_ASC_MEDIA_CHANGE (0x28)\r
+#define ATA_ASC_RESET (0x29) ///< Power On Reset or Bus Reset occurred.\r
+#define ATA_ASC_ILLEGAL_FIELD (0x26)\r
+#define ATA_ASC_NO_MEDIA (0x3A)\r
+#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
\r
//\r
// Additional Sense Code Qualifier\r
//\r
-#define ATA_ASCQ_IN_PROGRESS (0x01)\r
+#define ATA_ASCQ_IN_PROGRESS (0x01)\r
\r
//\r
// Error Register\r
//\r
-#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2\r
-#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1\r
-#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined from ATA-1, obsoleted from ATA-2\r
+#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_MC BIT5 ///< Media Change defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_IDNF BIT4 ///< ID Not Found defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_MCR BIT3 ///< Media Change Requested defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_ABRT BIT2 ///< Aborted Command defined from ATA-1\r
+#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined from ATA-1, obsoleted from ATA-4\r
\r
//\r
// Status Register\r
//\r
-#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1\r
-#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1\r
-#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6\r
-#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1\r
-#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4\r
-#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1\r
+#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined from ATA-1\r
+#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined from ATA-1\r
+#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_STSREG_DF BIT5 ///< Drive Fault defined from ATA-6\r
+#define ATA_STSREG_DSC BIT4 ///< Disk Seek Complete defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_STSREG_DRQ BIT3 ///< Data Request defined from ATA-1\r
+#define ATA_STSREG_CORR BIT2 ///< Corrected Data defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_STSREG_IDX BIT1 ///< Index defined from ATA-1, obsoleted from ATA-4\r
+#define ATA_STSREG_ERR BIT0 ///< Error defined from ATA-1\r
\r
//\r
// Device Control Register\r
//\r
-#define ATA_CTLREG_SRST BIT2 ///< Software Reset.\r
-#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.\r
+#define ATA_CTLREG_SRST BIT2 ///< Software Reset.\r
+#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #.\r
\r
#endif\r
///\r
/// 48bit Bluetooth device address.\r
///\r
- UINT8 Address[6];\r
+ UINT8 Address[6];\r
} BLUETOOTH_ADDRESS;\r
\r
///\r
/// BLUETOOTH_CLASS_OF_DEVICE. See Bluetooth specification for detail.\r
///\r
typedef struct {\r
- UINT8 FormatType:2;\r
- UINT8 MinorDeviceClass: 6;\r
- UINT16 MajorDeviceClass: 5;\r
- UINT16 MajorServiceClass:11;\r
+ UINT8 FormatType : 2;\r
+ UINT8 MinorDeviceClass : 6;\r
+ UINT16 MajorDeviceClass : 5;\r
+ UINT16 MajorServiceClass : 11;\r
} BLUETOOTH_CLASS_OF_DEVICE;\r
\r
///\r
///\r
/// 48-bit Bluetooth device address\r
///\r
- UINT8 Address[6];\r
+ UINT8 Address[6];\r
///\r
/// 0x00 - Public Device Address\r
/// 0x01 - Random Device Address\r
///\r
- UINT8 Type;\r
+ UINT8 Type;\r
} BLUETOOTH_LE_ADDRESS;\r
\r
#pragma pack()\r
\r
-#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248\r
+#define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE 248\r
\r
-#define BLUETOOTH_HCI_LINK_KEY_SIZE 16\r
+#define BLUETOOTH_HCI_LINK_KEY_SIZE 16\r
\r
#endif\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT8 Blue;\r
- UINT8 Green;\r
- UINT8 Red;\r
- UINT8 Reserved;\r
+ UINT8 Blue;\r
+ UINT8 Green;\r
+ UINT8 Red;\r
+ UINT8 Reserved;\r
} BMP_COLOR_MAP;\r
\r
typedef struct {\r
- CHAR8 CharB;\r
- CHAR8 CharM;\r
- UINT32 Size;\r
- UINT16 Reserved[2];\r
- UINT32 ImageOffset;\r
- UINT32 HeaderSize;\r
- UINT32 PixelWidth;\r
- UINT32 PixelHeight;\r
- UINT16 Planes; ///< Must be 1\r
- UINT16 BitPerPixel; ///< 1, 4, 8, or 24\r
- UINT32 CompressionType;\r
- UINT32 ImageSize; ///< Compressed image size in bytes\r
- UINT32 XPixelsPerMeter;\r
- UINT32 YPixelsPerMeter;\r
- UINT32 NumberOfColors;\r
- UINT32 ImportantColors;\r
+ CHAR8 CharB;\r
+ CHAR8 CharM;\r
+ UINT32 Size;\r
+ UINT16 Reserved[2];\r
+ UINT32 ImageOffset;\r
+ UINT32 HeaderSize;\r
+ UINT32 PixelWidth;\r
+ UINT32 PixelHeight;\r
+ UINT16 Planes; ///< Must be 1\r
+ UINT16 BitPerPixel; ///< 1, 4, 8, or 24\r
+ UINT32 CompressionType;\r
+ UINT32 ImageSize; ///< Compressed image size in bytes\r
+ UINT32 XPixelsPerMeter;\r
+ UINT32 YPixelsPerMeter;\r
+ UINT32 NumberOfColors;\r
+ UINT32 ImportantColors;\r
} BMP_IMAGE_HEADER;\r
\r
#pragma pack()\r
//\r
// CXL assigned new Vendor ID\r
//\r
-#define CXL_DVSEC_VENDOR_ID 0x1E98\r
+#define CXL_DVSEC_VENDOR_ID 0x1E98\r
\r
#endif\r
-\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58\r
// (subject to change as per CXL assigned Vendor ID)\r
//\r
-#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
+#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
\r
//\r
// CXL Flex Bus Device default device and function number\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1\r
//\r
-#define CXL_DEV_DEV 0\r
-#define CXL_DEV_FUNC 0\r
+#define CXL_DEV_DEV 0\r
+#define CXL_DEV_FUNC 0\r
\r
//\r
// Ensure proper structure formats\r
///@{\r
typedef union {\r
struct {\r
- UINT16 CacheCapable : 1; // bit 0\r
- UINT16 IoCapable : 1; // bit 1\r
- UINT16 MemCapable : 1; // bit 2\r
- UINT16 MemHwInitMode : 1; // bit 3\r
- UINT16 HdmCount : 2; // bit 4..5\r
- UINT16 Reserved1 : 8; // bit 6..13\r
- UINT16 ViralCapable : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 CacheCapable : 1; // bit 0\r
+ UINT16 IoCapable : 1; // bit 1\r
+ UINT16 MemCapable : 1; // bit 2\r
+ UINT16 MemHwInitMode : 1; // bit 3\r
+ UINT16 HdmCount : 2; // bit 4..5\r
+ UINT16 Reserved1 : 8; // bit 6..13\r
+ UINT16 ViralCapable : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CacheSfCoverage : 5; // bit 3..7\r
- UINT16 CacheSfGranularity : 3; // bit 8..10\r
- UINT16 CacheCleanEviction : 1; // bit 11\r
- UINT16 Reserved1 : 2; // bit 12..13\r
- UINT16 ViralEnable : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CacheSfCoverage : 5; // bit 3..7\r
+ UINT16 CacheSfGranularity : 3; // bit 8..10\r
+ UINT16 CacheCleanEviction : 1; // bit 11\r
+ UINT16 Reserved1 : 2; // bit 12..13\r
+ UINT16 ViralEnable : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 14; // bit 0..13\r
- UINT16 ViralStatus : 1; // bit 14\r
- UINT16 Reserved2 : 1; // bit 15\r
+ UINT16 Reserved1 : 14; // bit 0..13\r
+ UINT16 ViralStatus : 1; // bit 14\r
+ UINT16 Reserved2 : 1; // bit 15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 1; // bit 0\r
- UINT16 Reserved2 : 1; // bit 1\r
- UINT16 Reserved3 : 1; // bit 2\r
- UINT16 Reserved4 : 13; // bit 3..15\r
+ UINT16 Reserved1 : 1; // bit 0\r
+ UINT16 Reserved2 : 1; // bit 1\r
+ UINT16 Reserved3 : 1; // bit 2\r
+ UINT16 Reserved4 : 13; // bit 3..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;\r
\r
typedef union {\r
struct {\r
- UINT16 Reserved1 : 1; // bit 0\r
- UINT16 Reserved2 : 1; // bit 1\r
- UINT16 Reserved3 : 14; // bit 2..15\r
+ UINT16 Reserved1 : 1; // bit 0\r
+ UINT16 Reserved2 : 1; // bit 1\r
+ UINT16 Reserved3 : 14; // bit 2..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;\r
\r
typedef union {\r
struct {\r
- UINT16 ConfigLock : 1; // bit 0\r
- UINT16 Reserved1 : 15; // bit 1..15\r
+ UINT16 ConfigLock : 1; // bit 0\r
+ UINT16 Reserved1 : 15; // bit 1..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;\r
\r
typedef union {\r
struct {\r
- UINT32 MemorySizeHigh : 32; // bit 0..31\r
+ UINT32 MemorySizeHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryInfoValid : 1; // bit 0\r
- UINT32 MemoryActive : 1; // bit 1\r
- UINT32 MediaType : 3; // bit 2..4\r
- UINT32 MemoryClass : 3; // bit 5..7\r
- UINT32 DesiredInterleave : 3; // bit 8..10\r
- UINT32 Reserved : 17; // bit 11..27\r
- UINT32 MemorySizeLow : 4; // bit 28..31\r
+ UINT32 MemoryInfoValid : 1; // bit 0\r
+ UINT32 MemoryActive : 1; // bit 1\r
+ UINT32 MediaType : 3; // bit 2..4\r
+ UINT32 MemoryClass : 3; // bit 5..7\r
+ UINT32 DesiredInterleave : 3; // bit 8..10\r
+ UINT32 Reserved : 17; // bit 11..27\r
+ UINT32 MemorySizeLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryBaseHigh : 32; // bit 0..31\r
+ UINT32 MemoryBaseHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 28; // bit 0..27\r
- UINT32 MemoryBaseLow : 4; // bit 28..31\r
+ UINT32 Reserved : 28; // bit 0..27\r
+ UINT32 MemoryBaseLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;\r
\r
-\r
typedef union {\r
struct {\r
- UINT32 MemorySizeHigh : 32; // bit 0..31\r
+ UINT32 MemorySizeHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryInfoValid : 1; // bit 0\r
- UINT32 MemoryActive : 1; // bit 1\r
- UINT32 MediaType : 3; // bit 2..4\r
- UINT32 MemoryClass : 3; // bit 5..7\r
- UINT32 DesiredInterleave : 3; // bit 8..10\r
- UINT32 Reserved : 17; // bit 11..27\r
- UINT32 MemorySizeLow : 4; // bit 28..31\r
+ UINT32 MemoryInfoValid : 1; // bit 0\r
+ UINT32 MemoryActive : 1; // bit 1\r
+ UINT32 MediaType : 3; // bit 2..4\r
+ UINT32 MemoryClass : 3; // bit 5..7\r
+ UINT32 DesiredInterleave : 3; // bit 8..10\r
+ UINT32 Reserved : 17; // bit 11..27\r
+ UINT32 MemorySizeLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;\r
\r
typedef union {\r
struct {\r
- UINT32 MemoryBaseHigh : 32; // bit 0..31\r
+ UINT32 MemoryBaseHigh : 32; // bit 0..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 28; // bit 0..27\r
- UINT32 MemoryBaseLow : 4; // bit 28..31\r
+ UINT32 Reserved : 28; // bit 0..27\r
+ UINT32 MemoryBaseLow : 4; // bit 28..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;\r
\r
//\r
// Flex Bus Device DVSEC ID\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58\r
//\r
-#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
+#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
\r
//\r
// PCIe DVSEC for Flex Bus Device\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95\r
//\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
- CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
- CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
- CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
- CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
- CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
- CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
- UINT16 Reserved; // offset 22\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
- CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
+ CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
+ UINT16 Reserved; // offset 22\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
+ CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38);\r
///@}\r
\r
///\r
///@{\r
typedef union {\r
struct {\r
- UINT16 CacheCapable : 1; // bit 0\r
- UINT16 IoCapable : 1; // bit 1\r
- UINT16 MemCapable : 1; // bit 2\r
- UINT16 Reserved : 13; // bit 3..15\r
+ UINT16 CacheCapable : 1; // bit 0\r
+ UINT16 IoCapable : 1; // bit 1\r
+ UINT16 MemCapable : 1; // bit 2\r
+ UINT16 Reserved : 13; // bit 3..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CxlSyncBypassEnable : 1; // bit 3\r
- UINT16 DriftBufferEnable : 1; // bit 4\r
- UINT16 Reserved : 3; // bit 5..7\r
- UINT16 Retimer1Present : 1; // bit 8\r
- UINT16 Retimer2Present : 1; // bit 9\r
- UINT16 Reserved2 : 6; // bit 10..15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CxlSyncBypassEnable : 1; // bit 3\r
+ UINT16 DriftBufferEnable : 1; // bit 4\r
+ UINT16 Reserved : 3; // bit 5..7\r
+ UINT16 Retimer1Present : 1; // bit 8\r
+ UINT16 Retimer2Present : 1; // bit 9\r
+ UINT16 Reserved2 : 6; // bit 10..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CacheEnable : 1; // bit 0\r
- UINT16 IoEnable : 1; // bit 1\r
- UINT16 MemEnable : 1; // bit 2\r
- UINT16 CxlSyncBypassEnable : 1; // bit 3\r
- UINT16 DriftBufferEnable : 1; // bit 4\r
- UINT16 Reserved : 3; // bit 5..7\r
- UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
- UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
- UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
- UINT16 Reserved2 : 5; // bit 11..15\r
+ UINT16 CacheEnable : 1; // bit 0\r
+ UINT16 IoEnable : 1; // bit 1\r
+ UINT16 MemEnable : 1; // bit 2\r
+ UINT16 CxlSyncBypassEnable : 1; // bit 3\r
+ UINT16 DriftBufferEnable : 1; // bit 4\r
+ UINT16 Reserved : 3; // bit 5..7\r
+ UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
+ UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
+ UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
+ UINT16 Reserved2 : 5; // bit 11..15\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;\r
\r
//\r
// Flex Bus Port DVSEC ID\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62\r
//\r
-#define FLEX_BUS_PORT_DVSEC_ID 7\r
+#define FLEX_BUS_PORT_DVSEC_ID 7\r
\r
//\r
// PCIe DVSEC for Flex Bus Port\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99\r
//\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
- CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
+ CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
} CXL_1_1_DVSEC_FLEX_BUS_PORT;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10);\r
///@}\r
\r
///\r
/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1\r
///@{\r
\r
-#define CXL_CAPABILITY_HEADER_OFFSET 0\r
+#define CXL_CAPABILITY_HEADER_OFFSET 0\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
- UINT32 ArraySize : 8; // bit 24..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
+ UINT32 ArraySize : 8; // bit 24..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CAPABILITY_HEADER;\r
\r
-#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
+#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_RAS_CAPABILITY_HEADER;\r
\r
-#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
+#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_SECURITY_CAPABILITY_HEADER;\r
\r
-#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
+#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
typedef union {\r
struct {\r
- UINT32 CxlCapabilityId : 16; // bit 0..15\r
- UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
- UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
+ UINT32 CxlCapabilityId : 16; // bit 0..15\r
+ UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
+ UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_LINK_CAPABILITY_HEADER;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParity : 1; // bit 0..0\r
- UINT32 CacheAddressParity : 1; // bit 1..1\r
- UINT32 CacheByteEnableParity : 1; // bit 2..2\r
- UINT32 CacheDataEcc : 1; // bit 3..3\r
- UINT32 MemDataParity : 1; // bit 4..4\r
- UINT32 MemAddressParity : 1; // bit 5..5\r
- UINT32 MemByteEnableParity : 1; // bit 6..6\r
- UINT32 MemDataEcc : 1; // bit 7..7\r
- UINT32 ReInitThreshold : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
- UINT32 PoisonReceived : 1; // bit 10..10\r
- UINT32 ReceiverOverflow : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParity : 1; // bit 0..0\r
+ UINT32 CacheAddressParity : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParity : 1; // bit 2..2\r
+ UINT32 CacheDataEcc : 1; // bit 3..3\r
+ UINT32 MemDataParity : 1; // bit 4..4\r
+ UINT32 MemAddressParity : 1; // bit 5..5\r
+ UINT32 MemByteEnableParity : 1; // bit 6..6\r
+ UINT32 MemDataEcc : 1; // bit 7..7\r
+ UINT32 ReInitThreshold : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
+ UINT32 PoisonReceived : 1; // bit 10..10\r
+ UINT32 ReceiverOverflow : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParityMask : 1; // bit 0..0\r
- UINT32 CacheAddressParityMask : 1; // bit 1..1\r
- UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
- UINT32 CacheDataEccMask : 1; // bit 3..3\r
- UINT32 MemDataParityMask : 1; // bit 4..4\r
- UINT32 MemAddressParityMask : 1; // bit 5..5\r
- UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
- UINT32 MemDataEccMask : 1; // bit 7..7\r
- UINT32 ReInitThresholdMask : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
- UINT32 PoisonReceivedMask : 1; // bit 10..10\r
- UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParityMask : 1; // bit 0..0\r
+ UINT32 CacheAddressParityMask : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
+ UINT32 CacheDataEccMask : 1; // bit 3..3\r
+ UINT32 MemDataParityMask : 1; // bit 4..4\r
+ UINT32 MemAddressParityMask : 1; // bit 5..5\r
+ UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
+ UINT32 MemDataEccMask : 1; // bit 7..7\r
+ UINT32 ReInitThresholdMask : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
+ UINT32 PoisonReceivedMask : 1; // bit 10..10\r
+ UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_MASK;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
- UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
- UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
- UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
- UINT32 MemDataParitySeverity : 1; // bit 4..4\r
- UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
- UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
- UINT32 MemDataEccSeverity : 1; // bit 7..7\r
- UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
- UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
- UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
- UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
- UINT32 Reserved : 20; // bit 12..31\r
+ UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
+ UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
+ UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
+ UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
+ UINT32 MemDataParitySeverity : 1; // bit 4..4\r
+ UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
+ UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
+ UINT32 MemDataEccSeverity : 1; // bit 7..7\r
+ UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
+ UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
+ UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
+ UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
+ UINT32 Reserved : 20; // bit 12..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataEcc : 1; // bit 0..0\r
- UINT32 MemoryDataEcc : 1; // bit 1..1\r
- UINT32 CrcThreshold : 1; // bit 2..2\r
- UINT32 RetryThreshold : 1; // bit 3..3\r
- UINT32 CachePoisonReceived : 1; // bit 4..4\r
- UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
- UINT32 PhysicalLayerError : 1; // bit 6..6\r
- UINT32 Reserved : 25; // bit 7..31\r
+ UINT32 CacheDataEcc : 1; // bit 0..0\r
+ UINT32 MemoryDataEcc : 1; // bit 1..1\r
+ UINT32 CrcThreshold : 1; // bit 2..2\r
+ UINT32 RetryThreshold : 1; // bit 3..3\r
+ UINT32 CachePoisonReceived : 1; // bit 4..4\r
+ UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
+ UINT32 PhysicalLayerError : 1; // bit 6..6\r
+ UINT32 Reserved : 25; // bit 7..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CORRECTABLE_ERROR_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CacheDataEccMask : 1; // bit 0..0\r
- UINT32 MemoryDataEccMask : 1; // bit 1..1\r
- UINT32 CrcThresholdMask : 1; // bit 2..2\r
- UINT32 RetryThresholdMask : 1; // bit 3..3\r
- UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
- UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
- UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
- UINT32 Reserved : 25; // bit 7..31\r
+ UINT32 CacheDataEccMask : 1; // bit 0..0\r
+ UINT32 MemoryDataEccMask : 1; // bit 1..1\r
+ UINT32 CrcThresholdMask : 1; // bit 2..2\r
+ UINT32 RetryThresholdMask : 1; // bit 3..3\r
+ UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
+ UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
+ UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
+ UINT32 Reserved : 25; // bit 7..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CORRECTABLE_ERROR_MASK;\r
\r
typedef union {\r
struct {\r
- UINT32 FirstErrorPointer : 4; // bit 0..3\r
- UINT32 Reserved1 : 5; // bit 4..8\r
- UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
- UINT32 Reserved2 : 3; // bit 10..12\r
- UINT32 PoisonEnabled : 1; // bit 13..13\r
- UINT32 Reserved3 : 18; // bit 14..31\r
+ UINT32 FirstErrorPointer : 4; // bit 0..3\r
+ UINT32 Reserved1 : 5; // bit 4..8\r
+ UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
+ UINT32 Reserved2 : 3; // bit 10..12\r
+ UINT32 PoisonEnabled : 1; // bit 13..13\r
+ UINT32 Reserved3 : 18; // bit 14..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_ERROR_CAPABILITIES_AND_CONTROL;\r
\r
typedef struct {\r
- CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
- CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
- CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
- CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
- CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
- CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
- UINT32 HeaderLog[16];\r
+ CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
+ CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
+ CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
+ CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
+ CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
+ CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
+ UINT32 HeaderLog[16];\r
} CXL_1_1_RAS_CAPABILITY_STRUCTURE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58);\r
\r
typedef union {\r
struct {\r
- UINT32 DeviceTrustLevel : 2; // bit 0..1\r
- UINT32 Reserved : 30; // bit 2..31\r
+ UINT32 DeviceTrustLevel : 2; // bit 0..1\r
+ UINT32 Reserved : 30; // bit 2..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_1_1_SECURITY_POLICY;\r
\r
typedef struct {\r
- CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
+ CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;\r
\r
CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
\r
typedef union {\r
struct {\r
- UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
- UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
- UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
- UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
- UINT64 NumRetryReceived : 5; // bit 24..28\r
- UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
- UINT64 WrPtrReceived : 8; // bit 34..41\r
- UINT64 EchoEseqReceived : 8; // bit 42..49\r
- UINT64 NumFreeBufReceived : 8; // bit 50..57\r
- UINT64 Reserved : 6; // bit 58..63\r
+ UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
+ UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
+ UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
+ UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
+ UINT64 NumRetryReceived : 5; // bit 24..28\r
+ UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
+ UINT64 WrPtrReceived : 8; // bit 34..41\r
+ UINT64 EchoEseqReceived : 8; // bit 42..49\r
+ UINT64 NumFreeBufReceived : 8; // bit 50..57\r
+ UINT64 Reserved : 6; // bit 58..63\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 LlReset : 1; // bit 0..0\r
- UINT16 LlInitStall : 1; // bit 1..1\r
- UINT16 LlCrdStall : 1; // bit 2..2\r
- UINT16 InitState : 2; // bit 3..4\r
- UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
- UINT16 Reserved : 3; // bit 13..15\r
+ UINT16 LlReset : 1; // bit 0..0\r
+ UINT16 LlInitStall : 1; // bit 1..1\r
+ UINT16 LlCrdStall : 1; // bit 2..2\r
+ UINT16 InitState : 2; // bit 3..4\r
+ UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
+ UINT16 Reserved : 3; // bit 13..15\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_CONTROL_AND_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_RX_CREDIT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT64 CacheReqCredits : 10; // bit 0..9\r
- UINT64 CacheRspCredits : 10; // bit 10..19\r
- UINT64 CacheDataCredits : 10; // bit 20..29\r
- UINT64 MemReqRspCredits : 10; // bit 30..39\r
- UINT64 MemDataCredits : 10; // bit 40..49\r
+ UINT64 CacheReqCredits : 10; // bit 0..9\r
+ UINT64 CacheRspCredits : 10; // bit 10..19\r
+ UINT64 CacheDataCredits : 10; // bit 20..29\r
+ UINT64 MemReqRspCredits : 10; // bit 30..39\r
+ UINT64 MemDataCredits : 10; // bit 40..49\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_TX_CREDIT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 AckForceThreshold : 8; // bit 0..7\r
- UINT32 AckFLushRetimer : 10; // bit 8..17\r
+ UINT32 AckForceThreshold : 8; // bit 0..7\r
+ UINT32 AckFLushRetimer : 10; // bit 8..17\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_ACK_TIMER_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT32 MdhDisable : 1; // bit 0..0\r
- UINT32 Reserved : 31; // bit 1..31\r
+ UINT32 MdhDisable : 1; // bit 0..0\r
+ UINT32 Reserved : 31; // bit 1..31\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_LINK_LAYER_DEFEATURE;\r
\r
typedef struct {\r
- CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
- CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
- CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
- CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
- CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
- CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
- CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
+ CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
+ CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
+ CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
+ CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
+ CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
+ CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
+ CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
} CXL_1_1_LINK_CAPABILITY_STRUCTURE;\r
\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10);\r
CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);\r
-CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);\r
-CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28);\r
+CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30);\r
+CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38);\r
\r
-#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
+#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
typedef union {\r
struct {\r
- UINT32 Reserved1 : 4; // bit 0..3\r
- UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
- UINT32 Reserved2 : 24; // bit 8..31\r
+ UINT32 Reserved1 : 4; // bit 0..3\r
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
+ UINT32 Reserved2 : 24; // bit 8..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_IO_ARBITRATION_CONTROL;\r
\r
CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);\r
\r
-#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
+#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
typedef union {\r
struct {\r
- UINT32 Reserved1 : 4; // bit 0..3\r
- UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
- UINT32 Reserved2 : 24; // bit 8..31\r
+ UINT32 Reserved1 : 4; // bit 0..3\r
+ UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
+ UINT32 Reserved2 : 24; // bit 8..31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;\r
\r
CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);\r
///@{\r
typedef union {\r
struct {\r
- UINT64 RcrbEnable : 1; // bit 0..0\r
- UINT64 Reserved : 12; // bit 1..12\r
- UINT64 RcrbBaseAddress : 51; // bit 13..63\r
+ UINT64 RcrbEnable : 1; // bit 0..0\r
+ UINT64 Reserved : 12; // bit 1..12\r
+ UINT64 RcrbBaseAddress : 51; // bit 13..63\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} CXL_RCRB_BASE;\r
\r
CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);\r
// CXL Downstream / Upstream Port RCRB space register offsets\r
// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97\r
//\r
-#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
-#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
-#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
+#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
+#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
+#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _DEBUG_PORT_2_TABLE_H_\r
#define _DEBUG_PORT_2_TABLE_H_\r
\r
// Debug Device Information structure.\r
//\r
typedef struct {\r
- UINT8 Revision;\r
- UINT16 Length;\r
- UINT8 NumberofGenericAddressRegisters;\r
- UINT16 NameSpaceStringLength;\r
- UINT16 NameSpaceStringOffset;\r
- UINT16 OemDataLength;\r
- UINT16 OemDataOffset;\r
- UINT16 PortType;\r
- UINT16 PortSubtype;\r
- UINT8 Reserved[2];\r
- UINT16 BaseAddressRegisterOffset;\r
- UINT16 AddressSizeOffset;\r
+ UINT8 Revision;\r
+ UINT16 Length;\r
+ UINT8 NumberofGenericAddressRegisters;\r
+ UINT16 NameSpaceStringLength;\r
+ UINT16 NameSpaceStringOffset;\r
+ UINT16 OemDataLength;\r
+ UINT16 OemDataOffset;\r
+ UINT16 PortType;\r
+ UINT16 PortSubtype;\r
+ UINT8 Reserved[2];\r
+ UINT16 BaseAddressRegisterOffset;\r
+ UINT16 AddressSizeOffset;\r
} EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT;\r
\r
-#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00\r
+#define EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION 0x00\r
\r
#define EFI_ACPI_DBG2_PORT_TYPE_SERIAL 0x8000\r
#define EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_FULL_16550 0x0000\r
// Debug Port 2 Table definition.\r
//\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 OffsetDbgDeviceInfo;\r
- UINT32 NumberDbgDeviceInfo;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 OffsetDbgDeviceInfo;\r
+ UINT32 NumberDbgDeviceInfo;\r
} EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE;\r
\r
#pragma pack()\r
//\r
// DBG2 Revision (defined in spec)\r
//\r
-#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00\r
+#define EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION 0x00\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _DEBUG_PORT_TABLE_H_\r
#define _DEBUG_PORT_TABLE_H_\r
\r
//\r
// DBGP Revision (defined in spec)\r
//\r
-#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01\r
+#define EFI_ACPI_DEBUG_PORT_TABLE_REVISION 0x01\r
\r
//\r
// Interface Type\r
///\r
/// Dhcpv4 Options, definitions from RFC 2132\r
///\r
-#define DHCP4_TAG_PAD 0 /// Pad Option\r
-#define DHCP4_TAG_EOP 255 /// End Option\r
-#define DHCP4_TAG_NETMASK 1 /// Subnet Mask\r
-#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC\r
-#define DHCP4_TAG_ROUTER 3 /// Router option,\r
-#define DHCP4_TAG_TIME_SERVER 4 /// Time Server\r
-#define DHCP4_TAG_NAME_SERVER 5 /// Name Server\r
-#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server\r
-#define DHCP4_TAG_LOG_SERVER 7 /// Log Server\r
-#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server\r
-#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server\r
-#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server\r
-#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server\r
-#define DHCP4_TAG_HOSTNAME 12 /// Host Name\r
-#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size\r
-#define DHCP4_TAG_DUMP 14 /// Merit Dump File\r
-#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name\r
-#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server\r
-#define DHCP4_TAG_ROOTPATH 17 /// Root path\r
-#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path\r
-#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable\r
-#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable\r
-#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter\r
-#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size\r
-#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live\r
-#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout\r
-#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table\r
-#define DHCP4_TAG_IFMTU 26 /// Interface MTU\r
-#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local\r
-#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address\r
-#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery\r
-#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier\r
-#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery\r
-#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address\r
-#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route\r
-#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation\r
-#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout\r
-#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation\r
-#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL\r
-#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval\r
-#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage\r
-#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain\r
-#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers\r
-#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers\r
-#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information\r
-#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server\r
-#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server\r
-#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type\r
-#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope\r
-#define DHCP4_TAG_XFONT 48 /// X Window System Font Server\r
-#define DHCP4_TAG_XDM 49 /// X Window System Display Manager\r
-#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address\r
-#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time\r
-#define DHCP4_TAG_OVERLOAD 52 /// Option Overload\r
-#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type\r
-#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier\r
-#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List\r
-#define DHCP4_TAG_MESSAGE 56 /// Message\r
-#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size\r
-#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value\r
-#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value\r
-#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier\r
-#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier\r
-#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain\r
-#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers\r
-#define DHCP4_TAG_TFTP 66 /// TFTP server name\r
-#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name\r
-#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent\r
-#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server\r
-#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server\r
-#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server\r
-#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server\r
-#define DHCP4_TAG_FINGER 73 /// Default Finger Server\r
-#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server\r
-#define DHCP4_TAG_STTALK 75 /// StreetTalk Server\r
-#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server\r
-#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier\r
-#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578\r
-#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578\r
-#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578\r
-#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route\r
-\r
+#define DHCP4_TAG_PAD 0 /// Pad Option\r
+#define DHCP4_TAG_EOP 255 /// End Option\r
+#define DHCP4_TAG_NETMASK 1 /// Subnet Mask\r
+#define DHCP4_TAG_TIME_OFFSET 2 /// Time Offset from UTC\r
+#define DHCP4_TAG_ROUTER 3 /// Router option,\r
+#define DHCP4_TAG_TIME_SERVER 4 /// Time Server\r
+#define DHCP4_TAG_NAME_SERVER 5 /// Name Server\r
+#define DHCP4_TAG_DNS_SERVER 6 /// Domain Name Server\r
+#define DHCP4_TAG_LOG_SERVER 7 /// Log Server\r
+#define DHCP4_TAG_COOKIE_SERVER 8 /// Cookie Server\r
+#define DHCP4_TAG_LPR_SERVER 9 /// LPR Print Server\r
+#define DHCP4_TAG_IMPRESS_SERVER 10 /// Impress Server\r
+#define DHCP4_TAG_RL_SERVER 11 /// Resource Location Server\r
+#define DHCP4_TAG_HOSTNAME 12 /// Host Name\r
+#define DHCP4_TAG_BOOTFILE_LEN 13 /// Boot File Size\r
+#define DHCP4_TAG_DUMP 14 /// Merit Dump File\r
+#define DHCP4_TAG_DOMAINNAME 15 /// Domain Name\r
+#define DHCP4_TAG_SWAP_SERVER 16 /// Swap Server\r
+#define DHCP4_TAG_ROOTPATH 17 /// Root path\r
+#define DHCP4_TAG_EXTEND_PATH 18 /// Extensions Path\r
+#define DHCP4_TAG_IPFORWARD 19 /// IP Forwarding Enable/Disable\r
+#define DHCP4_TAG_NONLOCAL_SRR 20 /// on-Local Source Routing Enable/Disable\r
+#define DHCP4_TAG_POLICY_SRR 21 /// Policy Filter\r
+#define DHCP4_TAG_EMTU 22 /// Maximum Datagram Reassembly Size\r
+#define DHCP4_TAG_TTL 23 /// Default IP Time-to-live\r
+#define DHCP4_TAG_PATHMTU_AGE 24 /// Path MTU Aging Timeout\r
+#define DHCP4_TAG_PATHMTU_PLATEAU 25 /// Path MTU Plateau Table\r
+#define DHCP4_TAG_IFMTU 26 /// Interface MTU\r
+#define DHCP4_TAG_SUBNET_LOCAL 27 /// All Subnets are Local\r
+#define DHCP4_TAG_BROADCAST 28 /// Broadcast Address\r
+#define DHCP4_TAG_DISCOVER_MASK 29 /// Perform Mask Discovery\r
+#define DHCP4_TAG_SUPPLY_MASK 30 /// Mask Supplier\r
+#define DHCP4_TAG_DISCOVER_ROUTE 31 /// Perform Router Discovery\r
+#define DHCP4_TAG_ROUTER_SOLICIT 32 /// Router Solicitation Address\r
+#define DHCP4_TAG_STATIC_ROUTE 33 /// Static Route\r
+#define DHCP4_TAG_TRAILER 34 /// Trailer Encapsulation\r
+#define DHCP4_TAG_ARPAGE 35 /// ARP Cache Timeout\r
+#define DHCP4_TAG_ETHER_ENCAP 36 /// Ethernet Encapsulation\r
+#define DHCP4_TAG_TCP_TTL 37 /// TCP Default TTL\r
+#define DHCP4_TAG_KEEP_INTERVAL 38 /// TCP Keepalive Interval\r
+#define DHCP4_TAG_KEEP_GARBAGE 39 /// TCP Keepalive Garbage\r
+#define DHCP4_TAG_NIS_DOMAIN 40 /// Network Information Service Domain\r
+#define DHCP4_TAG_NIS_SERVER 41 /// Network Information Servers\r
+#define DHCP4_TAG_NTP_SERVER 42 /// Network Time Protocol Servers\r
+#define DHCP4_TAG_VENDOR 43 /// Vendor Specific Information\r
+#define DHCP4_TAG_NBNS 44 /// NetBIOS over TCP/IP Name Server\r
+#define DHCP4_TAG_NBDD 45 /// NetBIOS Datagram Distribution Server\r
+#define DHCP4_TAG_NBTYPE 46 /// NetBIOS over TCP/IP Node Type\r
+#define DHCP4_TAG_NBSCOPE 47 /// NetBIOS over TCP/IP Scope\r
+#define DHCP4_TAG_XFONT 48 /// X Window System Font Server\r
+#define DHCP4_TAG_XDM 49 /// X Window System Display Manager\r
+#define DHCP4_TAG_REQUEST_IP 50 /// Requested IP Address\r
+#define DHCP4_TAG_LEASE 51 /// IP Address Lease Time\r
+#define DHCP4_TAG_OVERLOAD 52 /// Option Overload\r
+#define DHCP4_TAG_MSG_TYPE 53 /// DHCP Message Type\r
+#define DHCP4_TAG_SERVER_ID 54 /// Server Identifier\r
+#define DHCP4_TAG_PARA_LIST 55 /// Parameter Request List\r
+#define DHCP4_TAG_MESSAGE 56 /// Message\r
+#define DHCP4_TAG_MAXMSG 57 /// Maximum DHCP Message Size\r
+#define DHCP4_TAG_T1 58 /// Renewal (T1) Time Value\r
+#define DHCP4_TAG_T2 59 /// Rebinding (T2) Time Value\r
+#define DHCP4_TAG_VENDOR_CLASS_ID 60 /// Vendor class identifier\r
+#define DHCP4_TAG_CLIENT_ID 61 /// Client-identifier\r
+#define DHCP4_TAG_NISPLUS 64 /// Network Information Service+ Domain\r
+#define DHCP4_TAG_NISPLUS_SERVER 65 /// Network Information Service+ Servers\r
+#define DHCP4_TAG_TFTP 66 /// TFTP server name\r
+#define DHCP4_TAG_BOOTFILE 67 /// Bootfile name\r
+#define DHCP4_TAG_MOBILEIP 68 /// Mobile IP Home Agent\r
+#define DHCP4_TAG_SMTP 69 /// Simple Mail Transport Protocol Server\r
+#define DHCP4_TAG_POP3 70 /// Post Office Protocol (POP3) Server\r
+#define DHCP4_TAG_NNTP 71 /// Network News Transport Protocol Server\r
+#define DHCP4_TAG_WWW 72 /// Default World Wide Web (WWW) Server\r
+#define DHCP4_TAG_FINGER 73 /// Default Finger Server\r
+#define DHCP4_TAG_IRC 74 /// Default Internet Relay Chat (IRC) Server\r
+#define DHCP4_TAG_STTALK 75 /// StreetTalk Server\r
+#define DHCP4_TAG_STDA 76 /// StreetTalk Directory Assistance Server\r
+#define DHCP4_TAG_USER_CLASS_ID 77 /// User class identifier\r
+#define DHCP4_TAG_ARCH 93 /// Client System Architecture Type, RFC 4578\r
+#define DHCP4_TAG_UNDI 94 /// Client Network Interface Identifier, RFC 4578\r
+#define DHCP4_TAG_UUID 97 /// Client Machine Identifier, RFC 4578\r
+#define DHCP4_TAG_CLASSLESS_ROUTE 121 /// Classless Route\r
\r
///\r
/// Dynamic Host Configuration Protocol for IPv6 (DHCPv6)\r
/// Enumeration of Dhcp6 message type, refers to section-5.3 of rfc-3315.\r
///\r
typedef enum {\r
- Dhcp6MsgSolicit = 1,\r
- Dhcp6MsgAdvertise = 2,\r
- Dhcp6MsgRequest = 3,\r
- Dhcp6MsgConfirm = 4,\r
- Dhcp6MsgRenew = 5,\r
- Dhcp6MsgRebind = 6,\r
- Dhcp6MsgReply = 7,\r
- Dhcp6MsgRelease = 8,\r
- Dhcp6MsgDecline = 9,\r
- Dhcp6MsgReconfigure = 10,\r
- Dhcp6MsgInfoRequest = 11\r
+ Dhcp6MsgSolicit = 1,\r
+ Dhcp6MsgAdvertise = 2,\r
+ Dhcp6MsgRequest = 3,\r
+ Dhcp6MsgConfirm = 4,\r
+ Dhcp6MsgRenew = 5,\r
+ Dhcp6MsgRebind = 6,\r
+ Dhcp6MsgReply = 7,\r
+ Dhcp6MsgRelease = 8,\r
+ Dhcp6MsgDecline = 9,\r
+ Dhcp6MsgReconfigure = 10,\r
+ Dhcp6MsgInfoRequest = 11\r
} DHCP6_MSG_TYPE;\r
\r
///\r
/// Enumeration of option code in Dhcp6 packet, refers to section-24.3 of rfc-3315.\r
///\r
typedef enum {\r
- Dhcp6OptClientId = 1,\r
- Dhcp6OptServerId = 2,\r
- Dhcp6OptIana = 3,\r
- Dhcp6OptIata = 4,\r
- Dhcp6OptIaAddr = 5,\r
- Dhcp6OptRequestOption = 6,\r
- Dhcp6OptPreference = 7,\r
- Dhcp6OptElapsedTime = 8,\r
- Dhcp6OptReplayMessage = 9,\r
- Dhcp6OptAuthentication = 11,\r
- Dhcp6OptServerUnicast = 12,\r
- Dhcp6OptStatusCode = 13,\r
- Dhcp6OptRapidCommit = 14,\r
- Dhcp6OptUserClass = 15,\r
- Dhcp6OptVendorClass = 16,\r
- Dhcp6OptVendorInfo = 17,\r
- Dhcp6OptInterfaceId = 18,\r
- Dhcp6OptReconfigMessage = 19,\r
- Dhcp6OptReconfigureAccept = 20\r
+ Dhcp6OptClientId = 1,\r
+ Dhcp6OptServerId = 2,\r
+ Dhcp6OptIana = 3,\r
+ Dhcp6OptIata = 4,\r
+ Dhcp6OptIaAddr = 5,\r
+ Dhcp6OptRequestOption = 6,\r
+ Dhcp6OptPreference = 7,\r
+ Dhcp6OptElapsedTime = 8,\r
+ Dhcp6OptReplayMessage = 9,\r
+ Dhcp6OptAuthentication = 11,\r
+ Dhcp6OptServerUnicast = 12,\r
+ Dhcp6OptStatusCode = 13,\r
+ Dhcp6OptRapidCommit = 14,\r
+ Dhcp6OptUserClass = 15,\r
+ Dhcp6OptVendorClass = 16,\r
+ Dhcp6OptVendorInfo = 17,\r
+ Dhcp6OptInterfaceId = 18,\r
+ Dhcp6OptReconfigMessage = 19,\r
+ Dhcp6OptReconfigureAccept = 20\r
} DHCP6_OPT_CODE;\r
\r
///\r
/// Enumeration of status code recorded by IANA, refers to section-24.4 of rfc-3315.\r
///\r
typedef enum {\r
- Dhcp6StsSuccess = 0,\r
- Dhcp6StsUnspecFail = 1,\r
- Dhcp6StsNoAddrsAvail = 2,\r
- Dhcp6StsNoBinding = 3,\r
- Dhcp6StsNotOnLink = 4,\r
- Dhcp6StsUseMulticast = 5\r
+ Dhcp6StsSuccess = 0,\r
+ Dhcp6StsUnspecFail = 1,\r
+ Dhcp6StsNoAddrsAvail = 2,\r
+ Dhcp6StsNoBinding = 3,\r
+ Dhcp6StsNotOnLink = 4,\r
+ Dhcp6StsUseMulticast = 5\r
} DHCP6_STS_CODE;\r
\r
///\r
/// Enumeration of Duid type recorded by IANA, refers to section-24.5 of rfc-3315.\r
///\r
typedef enum {\r
- Dhcp6DuidTypeLlt = 1,\r
- Dhcp6DuidTypeEn = 2,\r
- Dhcp6DuidTypeLl = 3,\r
- Dhcp6DuidTypeUuid = 4\r
+ Dhcp6DuidTypeLlt = 1,\r
+ Dhcp6DuidTypeEn = 2,\r
+ Dhcp6DuidTypeLl = 3,\r
+ Dhcp6DuidTypeUuid = 4\r
} DHCP6_DUID_TYPE;\r
\r
/// Transmission and Retransmission Parameters\r
///\r
/// Transmit parameters of solicit message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_SOL_MAX_DELAY 1\r
-#define DHCP6_SOL_IRT 1\r
-#define DHCP6_SOL_MRC 0\r
-#define DHCP6_SOL_MRT 120\r
-#define DHCP6_SOL_MRD 0\r
+#define DHCP6_SOL_MAX_DELAY 1\r
+#define DHCP6_SOL_IRT 1\r
+#define DHCP6_SOL_MRC 0\r
+#define DHCP6_SOL_MRT 120\r
+#define DHCP6_SOL_MRD 0\r
///\r
/// Transmit parameters of request message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_REQ_IRT 1\r
-#define DHCP6_REQ_MRC 10\r
-#define DHCP6_REQ_MRT 30\r
-#define DHCP6_REQ_MRD 0\r
+#define DHCP6_REQ_IRT 1\r
+#define DHCP6_REQ_MRC 10\r
+#define DHCP6_REQ_MRT 30\r
+#define DHCP6_REQ_MRD 0\r
///\r
/// Transmit parameters of confirm message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_CNF_MAX_DELAY 1\r
-#define DHCP6_CNF_IRT 1\r
-#define DHCP6_CNF_MRC 0\r
-#define DHCP6_CNF_MRT 4\r
-#define DHCP6_CNF_MRD 10\r
+#define DHCP6_CNF_MAX_DELAY 1\r
+#define DHCP6_CNF_IRT 1\r
+#define DHCP6_CNF_MRC 0\r
+#define DHCP6_CNF_MRT 4\r
+#define DHCP6_CNF_MRD 10\r
///\r
/// Transmit parameters of renew message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_REN_IRT 10\r
-#define DHCP6_REN_MRC 0\r
-#define DHCP6_REN_MRT 600\r
-#define DHCP6_REN_MRD 0\r
+#define DHCP6_REN_IRT 10\r
+#define DHCP6_REN_MRC 0\r
+#define DHCP6_REN_MRT 600\r
+#define DHCP6_REN_MRD 0\r
///\r
/// Transmit parameters of rebind message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_REB_IRT 10\r
-#define DHCP6_REB_MRC 0\r
-#define DHCP6_REB_MRT 600\r
-#define DHCP6_REB_MRD 0\r
+#define DHCP6_REB_IRT 10\r
+#define DHCP6_REB_MRC 0\r
+#define DHCP6_REB_MRT 600\r
+#define DHCP6_REB_MRD 0\r
///\r
/// Transmit parameters of information request message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_INF_MAX_DELAY 1\r
-#define DHCP6_INF_IRT 1\r
-#define DHCP6_INF_MRC 0\r
-#define DHCP6_INF_MRT 120\r
-#define DHCP6_INF_MRD 0\r
+#define DHCP6_INF_MAX_DELAY 1\r
+#define DHCP6_INF_IRT 1\r
+#define DHCP6_INF_MRC 0\r
+#define DHCP6_INF_MRT 120\r
+#define DHCP6_INF_MRD 0\r
///\r
/// Transmit parameters of release message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_REL_IRT 1\r
-#define DHCP6_REL_MRC 5\r
-#define DHCP6_REL_MRT 0\r
-#define DHCP6_REL_MRD 0\r
+#define DHCP6_REL_IRT 1\r
+#define DHCP6_REL_MRC 5\r
+#define DHCP6_REL_MRT 0\r
+#define DHCP6_REL_MRD 0\r
///\r
/// Transmit parameters of decline message, refers to section-5.5 of rfc-3315.\r
///\r
-#define DHCP6_DEC_IRT 1\r
-#define DHCP6_DEC_MRC 5\r
-#define DHCP6_DEC_MRT 0\r
-#define DHCP6_DEC_MRD 0\r
+#define DHCP6_DEC_IRT 1\r
+#define DHCP6_DEC_MRC 5\r
+#define DHCP6_DEC_MRT 0\r
+#define DHCP6_DEC_MRD 0\r
\r
////\r
//// DHCPv6 Options, definitions from RFC 3315,RFC 5970 and RFC 3646.\r
////\r
-#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option\r
-#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option\r
-#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option\r
-#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses\r
-#define DHCP6_OPT_IAADDR 5 /// IA Address option\r
-#define DHCP6_OPT_ORO 6 /// Request option\r
-#define DHCP6_OPT_PREFERENCE 7 /// Preference option\r
-#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option\r
-#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option\r
-#define DHCP6_OPT_AUTH 11 /// Authentication option\r
-#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option\r
-#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option\r
-#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option\r
-#define DHCP6_OPT_USER_CLASS 15 /// User Class option\r
-#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option\r
-#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option\r
-#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option\r
-#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option\r
-#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option\r
-#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646\r
-#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970\r
-#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970\r
-#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970\r
-#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970\r
+#define DHCP6_OPT_CLIENT_ID 1 /// Client Identifier Option\r
+#define DHCP6_OPT_SERVER_ID 2 /// Server Identifier Option\r
+#define DHCP6_OPT_IA_NA 3 /// The Identity Association for Non-temporary Addresses option\r
+#define DHCP6_OPT_IA_TA 4 /// The Identity Association for the Temporary Addresses\r
+#define DHCP6_OPT_IAADDR 5 /// IA Address option\r
+#define DHCP6_OPT_ORO 6 /// Request option\r
+#define DHCP6_OPT_PREFERENCE 7 /// Preference option\r
+#define DHCP6_OPT_ELAPSED_TIME 8 /// Elapsed Time Option\r
+#define DHCP6_OPT_REPLAY_MSG 9 /// Relay Message option\r
+#define DHCP6_OPT_AUTH 11 /// Authentication option\r
+#define DHCP6_OPT_UNICAST 12 /// Server Unicast Option\r
+#define DHCP6_OPT_STATUS_CODE 13 /// Status Code Option\r
+#define DHCP6_OPT_RAPID_COMMIT 14 /// Rapid Commit option\r
+#define DHCP6_OPT_USER_CLASS 15 /// User Class option\r
+#define DHCP6_OPT_VENDOR_CLASS 16 /// Vendor Class Option\r
+#define DHCP6_OPT_VENDOR_OPTS 17 /// Vendor-specific Information Option\r
+#define DHCP6_OPT_INTERFACE_ID 18 /// Interface-Id Option\r
+#define DHCP6_OPT_RECONFIG_MSG 19 /// Reconfigure Message Option\r
+#define DHCP6_OPT_RECONFIG_ACCEPT 20 /// Reconfigure Accept Option\r
+#define DHCP6_OPT_DNS_SERVERS 23 /// DNS Configuration options, RFC 3646\r
+#define DHCP6_OPT_BOOT_FILE_URL 59 /// Assigned by IANA, RFC 5970\r
+#define DHCP6_OPT_BOOT_FILE_PARAM 60 /// Assigned by IANA, RFC 5970\r
+#define DHCP6_OPT_ARCH 61 /// Assigned by IANA, RFC 5970\r
+#define DHCP6_OPT_UNDI 62 /// Assigned by IANA, RFC 5970\r
\r
///\r
/// Processor Architecture Types\r
/// These identifiers are defined by IETF:\r
/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml\r
///\r
-#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE\r
-#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE\r
-#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE\r
-#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE\r
-#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE\r
-#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE\r
-#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE\r
+#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE\r
+#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE\r
+#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE\r
+#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE\r
+#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE\r
+#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE\r
+#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE\r
\r
-#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http\r
-#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http\r
-#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http\r
-#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http\r
-#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http\r
+#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http\r
+#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http\r
+#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http\r
+#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http\r
+#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http\r
\r
#endif\r
- HPET - High Precision Event Timer\r
- NUMA - Non-uniform Memory Access\r
**/\r
+\r
#ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r
#define _DMA_REMAPPING_REPORTING_TABLE_H_\r
\r
///\r
/// DMA-Remapping Reporting Structure definitions from section 8.1\r
///@{\r
-#define EFI_ACPI_DMAR_REVISION 0x01\r
+#define EFI_ACPI_DMAR_REVISION 0x01\r
\r
#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0\r
#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1\r
///\r
/// Remapping Structure Types definitions from section 8.2\r
///@{\r
-#define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r
-#define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r
-#define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r
-#define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r
-#define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r
-#define EFI_ACPI_DMAR_TYPE_SATC 0x05\r
+#define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r
+#define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r
+#define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r
+#define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r
+#define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r
+#define EFI_ACPI_DMAR_TYPE_SATC 0x05\r
///@}\r
\r
///\r
///\r
/// Root Port ATS Capability Reporting Structure definitions from section 8.5\r
///\r
-#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r
+#define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r
\r
///\r
/// Definition for DMA Remapping Structure Header\r
///\r
typedef struct {\r
- UINT16 Type;\r
- UINT16 Length;\r
+ UINT16 Type;\r
+ UINT16 Length;\r
} EFI_ACPI_DMAR_STRUCTURE_HEADER;\r
\r
///\r
/// Definition for DMA-Remapping PCI Path\r
///\r
typedef struct {\r
- UINT8 Device;\r
- UINT8 Function;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
} EFI_ACPI_DMAR_PCI_PATH;\r
\r
///\r
/// Device Scope Structure is defined in section 8.3.1\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Length;\r
- UINT16 Reserved2;\r
- UINT8 EnumerationId;\r
- UINT8 StartBusNumber;\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ UINT16 Reserved2;\r
+ UINT8 EnumerationId;\r
+ UINT8 StartBusNumber;\r
} EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r
\r
/**\r
for each PCI segment in the platform.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+\r
/**\r
- Bit[0]: INCLUDE_PCI_ALL\r
- If Set, this remapping hardware unit has under its scope all\r
through the DeviceScope field.\r
- Bits[7:1] Reserved.\r
**/\r
- UINT8 Flags;\r
- UINT8 Reserved;\r
+ UINT8 Flags;\r
+ UINT8 Reserved;\r
///\r
/// The PCI Segment associated with this unit.\r
///\r
- UINT16 SegmentNumber;\r
+ UINT16 SegmentNumber;\r
///\r
/// Base address of remapping hardware register-set for this unit.\r
///\r
- UINT64 RegisterBaseAddress;\r
+ UINT64 RegisterBaseAddress;\r
} EFI_ACPI_DMAR_DRHD_HEADER;\r
\r
/**\r
reserved memory region.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
- UINT8 Reserved[2];\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[2];\r
///\r
/// PCI Segment Number associated with devices identified through\r
/// the Device Scope field.\r
///\r
- UINT16 SegmentNumber;\r
+ UINT16 SegmentNumber;\r
///\r
/// Base address of 4KB-aligned reserved memory region\r
///\r
- UINT64 ReservedMemoryRegionBaseAddress;\r
+ UINT64 ReservedMemoryRegionBaseAddress;\r
+\r
/**\r
Last address of the reserved memory region. Value in this field must be\r
greater than the value in Reserved Memory Region Base Address field.\r
The reserved memory region size (Limit - Base + 1) must be an integer\r
multiple of 4KB.\r
**/\r
- UINT64 ReservedMemoryRegionLimitAddress;\r
+ UINT64 ReservedMemoryRegionLimitAddress;\r
} EFI_ACPI_DMAR_RMRR_HEADER;\r
\r
/**\r
ATS transactions.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+\r
/**\r
- Bit[0]: ALL_PORTS:\r
- If Set, indicates all PCI Express Root Ports in the specified\r
Root Ports identified through the Device Scope field.\r
- Bits[7:1] Reserved.\r
**/\r
- UINT8 Flags;\r
- UINT8 Reserved;\r
+ UINT8 Flags;\r
+ UINT8 Reserved;\r
///\r
/// The PCI Segment associated with this ATSR structure\r
///\r
- UINT16 SegmentNumber;\r
+ UINT16 SegmentNumber;\r
} EFI_ACPI_DMAR_ATSR_HEADER;\r
\r
/**\r
reported through DRHD structure.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
- UINT8 Reserved[4];\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[4];\r
///\r
/// Register Base Address of this Remap hardware unit reported in the\r
/// corresponding DRHD structure.\r
///\r
- UINT64 RegisterBaseAddress;\r
+ UINT64 RegisterBaseAddress;\r
///\r
/// Proximity Domain to which the Remap hardware unit identified by the\r
/// Register Base Address field belongs.\r
///\r
- UINT32 ProximityDomain;\r
+ UINT32 ProximityDomain;\r
} EFI_ACPI_DMAR_RHSA_HEADER;\r
\r
/**\r
with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
- UINT8 Reserved[3];\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ UINT8 Reserved[3];\r
+\r
/**\r
Each ACPI device enumerated through an ANDD structure must have a unique\r
value for this field. To report an ACPI device with ACPI Device Number\r
The Start Bus Number and Path fields in the Device-Scope together\r
provides the 16-bit source-id allocated by platform for the ACPI device.\r
**/\r
- UINT8 AcpiDeviceNumber;\r
+ UINT8 AcpiDeviceNumber;\r
} EFI_ACPI_DMAR_ANDD_HEADER;\r
\r
/**\r
defined in section 8.8.\r
**/\r
typedef struct {\r
- EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+ EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r
+\r
/**\r
- Bit[0]: ATC_REQUIRED:\r
- If Set, indicates that every SoC integrated device enumerated\r
performance or functionality).\r
- Bits[7:1] Reserved.\r
**/\r
- UINT8 Flags;\r
- UINT8 Reserved;\r
+ UINT8 Flags;\r
+ UINT8 Reserved;\r
///\r
/// The PCI Segment associated with this SATC structure. All SoC integrated\r
/// devices within a PCI segment with same value for Flags field must be\r
/// enumerated in the same SATC structure.\r
///\r
- UINT16 SegmentNumber;\r
+ UINT16 SegmentNumber;\r
} EFI_ACPI_DMAR_SATC_HEADER;\r
\r
/**\r
structures of type 1 (RMRR), and so forth.\r
**/\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+\r
/**\r
This field indicates the maximum DMA physical addressability supported by\r
this platform. The system address map reported by the BIOS indicates what\r
For example, for a platform supporting 40 bits of physical addressability,\r
the value of 100111b is reported in this field.\r
**/\r
- UINT8 HostAddressWidth;\r
+ UINT8 HostAddressWidth;\r
+\r
/**\r
- Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt\r
remapping. If Set, the platform supports interrupt remapping.\r
such as on ExitBootServices().\r
- Bits[7:3] Reserved.\r
**/\r
- UINT8 Flags;\r
- UINT8 Reserved[10];\r
+ UINT8 Flags;\r
+ UINT8 Reserved[10];\r
} EFI_ACPI_DMAR_HEADER;\r
\r
#pragma pack()\r
//\r
// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660\r
//\r
-#define CDVOL_TYPE_STANDARD 0x0\r
-#define CDVOL_TYPE_CODED 0x1\r
-#define CDVOL_TYPE_END 0xFF\r
+#define CDVOL_TYPE_STANDARD 0x0\r
+#define CDVOL_TYPE_CODED 0x1\r
+#define CDVOL_TYPE_END 0xFF\r
\r
///\r
/// CDROM_VOLUME_DESCRIPTOR.Id\r
///\r
/// CDROM_VOLUME_DESCRIPTOR.SystemId\r
///\r
-#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"\r
+#define CDVOL_ELTORITO_ID "EL TORITO SPECIFICATION"\r
\r
//\r
// Indicator types\r
//\r
// ELTORITO_CATALOG.Boot.MediaTypes\r
//\r
-#define ELTORITO_NO_EMULATION 0x00\r
-#define ELTORITO_12_DISKETTE 0x01\r
-#define ELTORITO_14_DISKETTE 0x02\r
-#define ELTORITO_28_DISKETTE 0x03\r
-#define ELTORITO_HARD_DISK 0x04\r
-\r
+#define ELTORITO_NO_EMULATION 0x00\r
+#define ELTORITO_12_DISKETTE 0x01\r
+#define ELTORITO_14_DISKETTE 0x02\r
+#define ELTORITO_28_DISKETTE 0x03\r
+#define ELTORITO_HARD_DISK 0x04\r
\r
#pragma pack(1)\r
\r
///\r
typedef union {\r
struct {\r
- UINT8 Type;\r
- CHAR8 Id[5]; ///< "CD001"\r
- CHAR8 Reserved[82];\r
+ UINT8 Type;\r
+ CHAR8 Id[5]; ///< "CD001"\r
+ CHAR8 Reserved[82];\r
} Unknown;\r
\r
///\r
/// Boot Record Volume Descriptor, defined in "El Torito" Specification.\r
///\r
struct {\r
- UINT8 Type; ///< Must be 0\r
- CHAR8 Id[5]; ///< "CD001"\r
- UINT8 Version; ///< Must be 1\r
- CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"\r
- CHAR8 Unused[32]; ///< Must be 0\r
- UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog\r
- CHAR8 Unused2[13]; ///< Must be 0\r
+ UINT8 Type; ///< Must be 0\r
+ CHAR8 Id[5]; ///< "CD001"\r
+ UINT8 Version; ///< Must be 1\r
+ CHAR8 SystemId[32]; ///< "EL TORITO SPECIFICATION"\r
+ CHAR8 Unused[32]; ///< Must be 0\r
+ UINT8 EltCatalog[4]; ///< Absolute pointer to first sector of Boot Catalog\r
+ CHAR8 Unused2[13]; ///< Must be 0\r
} BootRecordVolume;\r
\r
///\r
/// Primary Volume Descriptor, defined in ISO 9660.\r
///\r
struct {\r
- UINT8 Type;\r
- CHAR8 Id[5]; ///< "CD001"\r
- UINT8 Version;\r
- UINT8 Unused; ///< Must be 0\r
- CHAR8 SystemId[32];\r
- CHAR8 VolumeId[32];\r
- UINT8 Unused2[8]; ///< Must be 0\r
- UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks\r
+ UINT8 Type;\r
+ CHAR8 Id[5]; ///< "CD001"\r
+ UINT8 Version;\r
+ UINT8 Unused; ///< Must be 0\r
+ CHAR8 SystemId[32];\r
+ CHAR8 VolumeId[32];\r
+ UINT8 Unused2[8]; ///< Must be 0\r
+ UINT32 VolSpaceSize[2]; ///< the number of Logical Blocks\r
} PrimaryVolume;\r
-\r
} CDROM_VOLUME_DESCRIPTOR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- CHAR8 Reserved[0x20];\r
+ CHAR8 Reserved[0x20];\r
} Unknown;\r
\r
///\r
/// Catalog validation entry (Catalog header)\r
///\r
struct {\r
- UINT8 Indicator; ///< Must be 01\r
- UINT8 PlatformId;\r
- UINT16 Reserved;\r
- CHAR8 ManufacId[24];\r
- UINT16 Checksum;\r
- UINT16 Id55AA;\r
+ UINT8 Indicator; ///< Must be 01\r
+ UINT8 PlatformId;\r
+ UINT16 Reserved;\r
+ CHAR8 ManufacId[24];\r
+ UINT16 Checksum;\r
+ UINT16 Id55AA;\r
} Catalog;\r
\r
///\r
/// Initial/Default Entry or Section Entry\r
///\r
struct {\r
- UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable\r
- UINT8 MediaType : 4;\r
- UINT8 Reserved1 : 4; ///< Must be 0\r
- UINT16 LoadSegment;\r
- UINT8 SystemType;\r
- UINT8 Reserved2; ///< Must be 0\r
- UINT16 SectorCount;\r
- UINT32 Lba;\r
+ UINT8 Indicator; ///< 88 = Bootable, 00 = Not Bootable\r
+ UINT8 MediaType : 4;\r
+ UINT8 Reserved1 : 4; ///< Must be 0\r
+ UINT16 LoadSegment;\r
+ UINT8 SystemType;\r
+ UINT8 Reserved2; ///< Must be 0\r
+ UINT16 SectorCount;\r
+ UINT32 Lba;\r
} Boot;\r
\r
///\r
/// Section Header Entry\r
///\r
struct {\r
- UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header\r
- UINT8 PlatformId;\r
- UINT16 SectionEntries; ///< Number of section entries following this header\r
- CHAR8 Id[28];\r
+ UINT8 Indicator; ///< 90 - Header, more header follw, 91 - Final Header\r
+ UINT8 PlatformId;\r
+ UINT16 SectionEntries; ///< Number of section entries following this header\r
+ CHAR8 Id[28];\r
} Section;\r
-\r
} ELTORITO_CATALOG;\r
\r
#pragma pack()\r
//\r
// EMMC command index\r
//\r
-#define EMMC_GO_IDLE_STATE 0\r
-#define EMMC_SEND_OP_COND 1\r
-#define EMMC_ALL_SEND_CID 2\r
-#define EMMC_SET_RELATIVE_ADDR 3\r
-#define EMMC_SET_DSR 4\r
-#define EMMC_SLEEP_AWAKE 5\r
-#define EMMC_SWITCH 6\r
-#define EMMC_SELECT_DESELECT_CARD 7\r
-#define EMMC_SEND_EXT_CSD 8\r
-#define EMMC_SEND_CSD 9\r
-#define EMMC_SEND_CID 10\r
-#define EMMC_STOP_TRANSMISSION 12\r
-#define EMMC_SEND_STATUS 13\r
-#define EMMC_BUSTEST_R 14\r
-#define EMMC_GO_INACTIVE_STATE 15\r
-#define EMMC_SET_BLOCKLEN 16\r
-#define EMMC_READ_SINGLE_BLOCK 17\r
-#define EMMC_READ_MULTIPLE_BLOCK 18\r
-#define EMMC_BUSTEST_W 19\r
-#define EMMC_SEND_TUNING_BLOCK 21\r
-#define EMMC_SET_BLOCK_COUNT 23\r
-#define EMMC_WRITE_BLOCK 24\r
-#define EMMC_WRITE_MULTIPLE_BLOCK 25\r
-#define EMMC_PROGRAM_CID 26\r
-#define EMMC_PROGRAM_CSD 27\r
-#define EMMC_SET_WRITE_PROT 28\r
-#define EMMC_CLR_WRITE_PROT 29\r
-#define EMMC_SEND_WRITE_PROT 30\r
-#define EMMC_SEND_WRITE_PROT_TYPE 31\r
-#define EMMC_ERASE_GROUP_START 35\r
-#define EMMC_ERASE_GROUP_END 36\r
-#define EMMC_ERASE 38\r
-#define EMMC_FAST_IO 39\r
-#define EMMC_GO_IRQ_STATE 40\r
-#define EMMC_LOCK_UNLOCK 42\r
-#define EMMC_SET_TIME 49\r
-#define EMMC_PROTOCOL_RD 53\r
-#define EMMC_PROTOCOL_WR 54\r
-#define EMMC_APP_CMD 55\r
-#define EMMC_GEN_CMD 56\r
+#define EMMC_GO_IDLE_STATE 0\r
+#define EMMC_SEND_OP_COND 1\r
+#define EMMC_ALL_SEND_CID 2\r
+#define EMMC_SET_RELATIVE_ADDR 3\r
+#define EMMC_SET_DSR 4\r
+#define EMMC_SLEEP_AWAKE 5\r
+#define EMMC_SWITCH 6\r
+#define EMMC_SELECT_DESELECT_CARD 7\r
+#define EMMC_SEND_EXT_CSD 8\r
+#define EMMC_SEND_CSD 9\r
+#define EMMC_SEND_CID 10\r
+#define EMMC_STOP_TRANSMISSION 12\r
+#define EMMC_SEND_STATUS 13\r
+#define EMMC_BUSTEST_R 14\r
+#define EMMC_GO_INACTIVE_STATE 15\r
+#define EMMC_SET_BLOCKLEN 16\r
+#define EMMC_READ_SINGLE_BLOCK 17\r
+#define EMMC_READ_MULTIPLE_BLOCK 18\r
+#define EMMC_BUSTEST_W 19\r
+#define EMMC_SEND_TUNING_BLOCK 21\r
+#define EMMC_SET_BLOCK_COUNT 23\r
+#define EMMC_WRITE_BLOCK 24\r
+#define EMMC_WRITE_MULTIPLE_BLOCK 25\r
+#define EMMC_PROGRAM_CID 26\r
+#define EMMC_PROGRAM_CSD 27\r
+#define EMMC_SET_WRITE_PROT 28\r
+#define EMMC_CLR_WRITE_PROT 29\r
+#define EMMC_SEND_WRITE_PROT 30\r
+#define EMMC_SEND_WRITE_PROT_TYPE 31\r
+#define EMMC_ERASE_GROUP_START 35\r
+#define EMMC_ERASE_GROUP_END 36\r
+#define EMMC_ERASE 38\r
+#define EMMC_FAST_IO 39\r
+#define EMMC_GO_IRQ_STATE 40\r
+#define EMMC_LOCK_UNLOCK 42\r
+#define EMMC_SET_TIME 49\r
+#define EMMC_PROTOCOL_RD 53\r
+#define EMMC_PROTOCOL_WR 54\r
+#define EMMC_APP_CMD 55\r
+#define EMMC_GEN_CMD 56\r
\r
typedef enum {\r
- EmmcPartitionUserData = 0,\r
- EmmcPartitionBoot1 = 1,\r
- EmmcPartitionBoot2 = 2,\r
- EmmcPartitionRPMB = 3,\r
- EmmcPartitionGP1 = 4,\r
- EmmcPartitionGP2 = 5,\r
- EmmcPartitionGP3 = 6,\r
- EmmcPartitionGP4 = 7,\r
+ EmmcPartitionUserData = 0,\r
+ EmmcPartitionBoot1 = 1,\r
+ EmmcPartitionBoot2 = 2,\r
+ EmmcPartitionRPMB = 3,\r
+ EmmcPartitionGP1 = 4,\r
+ EmmcPartitionGP2 = 5,\r
+ EmmcPartitionGP3 = 6,\r
+ EmmcPartitionGP4 = 7,\r
EmmcPartitionUnknown\r
} EMMC_PARTITION_TYPE;\r
\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 NotUsed:1; // Not used [0:0]\r
- UINT8 Crc:7; // CRC [7:1]\r
- UINT8 ManufacturingDate; // Manufacturing date [15:8]\r
- UINT8 ProductSerialNumber[4]; // Product serial number [47:16]\r
- UINT8 ProductRevision; // Product revision [55:48]\r
- UINT8 ProductName[6]; // Product name [103:56]\r
- UINT8 OemId; // OEM/Application ID [111:104]\r
- UINT8 DeviceType:2; // Device/BGA [113:112]\r
- UINT8 Reserved:6; // Reserved [119:114]\r
- UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
+ UINT8 NotUsed : 1; // Not used [0:0]\r
+ UINT8 Crc : 7; // CRC [7:1]\r
+ UINT8 ManufacturingDate; // Manufacturing date [15:8]\r
+ UINT8 ProductSerialNumber[4]; // Product serial number [47:16]\r
+ UINT8 ProductRevision; // Product revision [55:48]\r
+ UINT8 ProductName[6]; // Product name [103:56]\r
+ UINT8 OemId; // OEM/Application ID [111:104]\r
+ UINT8 DeviceType : 2; // Device/BGA [113:112]\r
+ UINT8 Reserved : 6; // Reserved [119:114]\r
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
} EMMC_CID;\r
\r
typedef struct {\r
- UINT32 NotUsed:1; // Not used [0:0]\r
- UINT32 Crc:7; // CRC [7:1]\r
- UINT32 Ecc:2; // ECC code [9:8]\r
- UINT32 FileFormat:2; // File format [11:10]\r
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
- UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
- UINT32 FileFormatGrp:1; // File format group [15:15]\r
- UINT32 ContentProtApp:1; // Content protection application [16:16]\r
- UINT32 Reserved:4; // Reserved [20:17]\r
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
- UINT32 R2WFactor:3; // Write speed factor [28:26]\r
- UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]\r
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
+ UINT32 NotUsed : 1; // Not used [0:0]\r
+ UINT32 Crc : 7; // CRC [7:1]\r
+ UINT32 Ecc : 2; // ECC code [9:8]\r
+ UINT32 FileFormat : 2; // File format [11:10]\r
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]\r
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp : 1; // File format group [15:15]\r
+ UINT32 ContentProtApp : 1; // Content protection application [16:16]\r
+ UINT32 Reserved : 4; // Reserved [20:17]\r
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]\r
+ UINT32 DefaultEcc : 2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]\r
\r
- UINT32 WpGrpSize:5; // Write protect group size [36:32]\r
- UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]\r
- UINT32 EraseGrpSize:5; // Erase group size [46:42]\r
- UINT32 CSizeMult:3; // Device size multiplier [49:47]\r
- UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]\r
- UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]\r
- UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]\r
- UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]\r
- UINT32 CSizeLow:2; // Device size low two bits [63:62]\r
+ UINT32 WpGrpSize : 5; // Write protect group size [36:32]\r
+ UINT32 EraseGrpMult : 5; // Erase group size multiplier [41:37]\r
+ UINT32 EraseGrpSize : 5; // Erase group size [46:42]\r
+ UINT32 CSizeMult : 3; // Device size multiplier [49:47]\r
+ UINT32 VddWCurrMax : 3; // Max. write current @ VDD max [52:50]\r
+ UINT32 VddWCurrMin : 3; // Max. write current @ VDD min [55:53]\r
+ UINT32 VddRCurrMax : 3; // Max. read current @ VDD max [58:56]\r
+ UINT32 VddRCurrMin : 3; // Max. read current @ VDD min [61:59]\r
+ UINT32 CSizeLow : 2; // Device size low two bits [63:62]\r
\r
- UINT32 CSizeHigh:10; // Device size high eight bits [73:64]\r
- UINT32 Reserved1:2; // Reserved [75:74]\r
- UINT32 DsrImp:1; // DSR implemented [76:76]\r
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
- UINT32 Ccc:12; // Device command classes [95:84]\r
+ UINT32 CSizeHigh : 10; // Device size high eight bits [73:64]\r
+ UINT32 Reserved1 : 2; // Reserved [75:74]\r
+ UINT32 DsrImp : 1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]\r
+ UINT32 Ccc : 12; // Device command classes [95:84]\r
\r
- UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]\r
- UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
- UINT32 Taac:8; // Data read access-time 1 [119:112]\r
- UINT32 Reserved2:2; // Reserved [121:120]\r
- UINT32 SpecVers:4; // System specification version [125:122]\r
- UINT32 CsdStructure:2; // CSD structure [127:126]\r
+ UINT32 TranSpeed : 8; // Max. bus clock frequency [103:96]\r
+ UINT32 Nsac : 8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac : 8; // Data read access-time 1 [119:112]\r
+ UINT32 Reserved2 : 2; // Reserved [121:120]\r
+ UINT32 SpecVers : 4; // System specification version [125:122]\r
+ UINT32 CsdStructure : 2; // CSD structure [127:126]\r
} EMMC_CSD;\r
\r
typedef struct {\r
//\r
// Modes Segment\r
//\r
- UINT8 Reserved[16]; // Reserved [15:0]\r
- UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]\r
- UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]\r
- UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]\r
- UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]\r
- UINT8 FfuStatus; // FFU status R [26]\r
- UINT8 Reserved1[2]; // Reserved [28:27]\r
- UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]\r
- UINT8 ModeConfig; // Mode config R/W/EP [30]\r
- UINT8 Reserved2; // Reserved [31]\r
- UINT8 FlushCache; // Flushing of the cache W/EP [32]\r
- UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]\r
- UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]\r
- UINT8 PackedFailureIndex; // Packed command failure index R [35]\r
- UINT8 PackedCommandStatus; // Packed command status R [36]\r
- UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]\r
- UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]\r
- UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]\r
- UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]\r
- UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]\r
- UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]\r
- UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]\r
- UINT8 DataSectorSize; // Sector size R [61]\r
- UINT8 UseNativeSector; // Sector size emulation R/W [62]\r
- UINT8 NativeSectorSize; // Native sector size R [63]\r
- UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]\r
- UINT8 Reserved3[2]; // Reserved [129:128]\r
- UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]\r
- UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]\r
- UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]\r
- UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]\r
- UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]\r
- UINT8 Reserved4; // Reserved [135]\r
- UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]\r
- UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]\r
- UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]\r
- UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]\r
- UINT8 PartitionsAttribute; // Partitions attribute R/W [156]\r
- UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]\r
- UINT8 PartitioningSupport; // Partitioning Support R [160]\r
- UINT8 HpiMgmt; // HPI management R/W/EP [161]\r
- UINT8 RstFunction; // H/W reset function R/W [162]\r
- UINT8 BkopsEn; // Enable background operations handshake R/W [163]\r
- UINT8 BkopsStart; // Manually start background operations W/EP [164]\r
- UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]\r
- UINT8 WrRelParam; // Write reliability parameter register R [166]\r
- UINT8 WrRelSet; // Write reliability setting register R/W [167]\r
- UINT8 RpmbSizeMult; // RPMB Size R [168]\r
- UINT8 FwConfig; // FW configuration R/W [169]\r
- UINT8 Reserved5; // Reserved [170]\r
- UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]\r
- UINT8 Reserved6; // Reserved [172]\r
- UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]\r
- UINT8 BootWpStatus; // Boot write protection status registers R [174]\r
- UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]\r
- UINT8 Reserved7; // Reserved [176]\r
- UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]\r
- UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]\r
- UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]\r
- UINT8 Reserved8; // Reserved [180]\r
- UINT8 ErasedMemCont; // Erased memory content R [181]\r
- UINT8 Reserved9; // Reserved [182]\r
- UINT8 BusWidth; // Bus width mode W/EP [183]\r
- UINT8 Reserved10; // Reserved [184]\r
- UINT8 HsTiming; // High-speed interface timing R/W/EP [185]\r
- UINT8 Reserved11; // Reserved [186]\r
- UINT8 PowerClass; // Power class R/W/EP [187]\r
- UINT8 Reserved12; // Reserved [188]\r
- UINT8 CmdSetRev; // Command set revision R [189]\r
- UINT8 Reserved13; // Reserved [190]\r
- UINT8 CmdSet; // Command set R/W/EP [191]\r
+ UINT8 Reserved[16]; // Reserved [15:0]\r
+ UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]\r
+ UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]\r
+ UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]\r
+ UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]\r
+ UINT8 FfuStatus; // FFU status R [26]\r
+ UINT8 Reserved1[2]; // Reserved [28:27]\r
+ UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]\r
+ UINT8 ModeConfig; // Mode config R/W/EP [30]\r
+ UINT8 Reserved2; // Reserved [31]\r
+ UINT8 FlushCache; // Flushing of the cache W/EP [32]\r
+ UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]\r
+ UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]\r
+ UINT8 PackedFailureIndex; // Packed command failure index R [35]\r
+ UINT8 PackedCommandStatus; // Packed command status R [36]\r
+ UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]\r
+ UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]\r
+ UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]\r
+ UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]\r
+ UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]\r
+ UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]\r
+ UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]\r
+ UINT8 DataSectorSize; // Sector size R [61]\r
+ UINT8 UseNativeSector; // Sector size emulation R/W [62]\r
+ UINT8 NativeSectorSize; // Native sector size R [63]\r
+ UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]\r
+ UINT8 Reserved3[2]; // Reserved [129:128]\r
+ UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]\r
+ UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]\r
+ UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]\r
+ UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]\r
+ UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]\r
+ UINT8 Reserved4; // Reserved [135]\r
+ UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]\r
+ UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]\r
+ UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]\r
+ UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]\r
+ UINT8 PartitionsAttribute; // Partitions attribute R/W [156]\r
+ UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]\r
+ UINT8 PartitioningSupport; // Partitioning Support R [160]\r
+ UINT8 HpiMgmt; // HPI management R/W/EP [161]\r
+ UINT8 RstFunction; // H/W reset function R/W [162]\r
+ UINT8 BkopsEn; // Enable background operations handshake R/W [163]\r
+ UINT8 BkopsStart; // Manually start background operations W/EP [164]\r
+ UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]\r
+ UINT8 WrRelParam; // Write reliability parameter register R [166]\r
+ UINT8 WrRelSet; // Write reliability setting register R/W [167]\r
+ UINT8 RpmbSizeMult; // RPMB Size R [168]\r
+ UINT8 FwConfig; // FW configuration R/W [169]\r
+ UINT8 Reserved5; // Reserved [170]\r
+ UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]\r
+ UINT8 Reserved6; // Reserved [172]\r
+ UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]\r
+ UINT8 BootWpStatus; // Boot write protection status registers R [174]\r
+ UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]\r
+ UINT8 Reserved7; // Reserved [176]\r
+ UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]\r
+ UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]\r
+ UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]\r
+ UINT8 Reserved8; // Reserved [180]\r
+ UINT8 ErasedMemCont; // Erased memory content R [181]\r
+ UINT8 Reserved9; // Reserved [182]\r
+ UINT8 BusWidth; // Bus width mode W/EP [183]\r
+ UINT8 Reserved10; // Reserved [184]\r
+ UINT8 HsTiming; // High-speed interface timing R/W/EP [185]\r
+ UINT8 Reserved11; // Reserved [186]\r
+ UINT8 PowerClass; // Power class R/W/EP [187]\r
+ UINT8 Reserved12; // Reserved [188]\r
+ UINT8 CmdSetRev; // Command set revision R [189]\r
+ UINT8 Reserved13; // Reserved [190]\r
+ UINT8 CmdSet; // Command set R/W/EP [191]\r
//\r
// Properties Segment\r
//\r
- UINT8 ExtCsdRev; // Extended CSD revision [192]\r
- UINT8 Reserved14; // Reserved [193]\r
- UINT8 CsdStructure; // CSD STRUCTURE [194]\r
- UINT8 Reserved15; // Reserved [195]\r
- UINT8 DeviceType; // Device type [196]\r
- UINT8 DriverStrength; // I/O Driver Strength [197]\r
- UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r
- UINT8 PartitionSwitchTime; // Partition switching timing [199]\r
- UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r
- UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r
- UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r
- UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r
- UINT8 Reserved16; // Reserved [204]\r
- UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r
- UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r
- UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r
- UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r
- UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r
- UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
- UINT8 Reserved17; // Reserved [211]\r
- UINT8 SecCount[4]; // Sector Count [215:212]\r
- UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]\r
- UINT8 SATimeout; // Sleep/awake timeout [217]\r
- UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
- UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
- UINT8 SCVcc; // Sleep current (VCC) [220]\r
- UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r
- UINT8 RelWrSecC; // Reliable write sector count [222]\r
- UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r
- UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r
- UINT8 AccSize; // Access size [225]\r
- UINT8 BootSizeMult; // Boot partition size [226]\r
- UINT8 Reserved18; // Reserved [227]\r
- UINT8 BootInfo; // Boot information [228]\r
- UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r
- UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r
- UINT8 SecFeatureSupport; // Secure Feature support [231]\r
- UINT8 TrimMult; // TRIM Multiplier [232]\r
- UINT8 Reserved19; // Reserved [233]\r
- UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r
- UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r
- UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r
- UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r
- UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r
- UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r
- UINT8 Reserved20; // Reserved [240]\r
- UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r
- UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r
- UINT8 BkopsStatus; // Background operations status [246]\r
- UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r
- UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r
- UINT8 CacheSize[4]; // Cache size [252:249]\r
- UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r
- UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r
- UINT8 DeviceVersion[2]; // Device version [263:262]\r
- UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r
- UINT8 OptimalWriteSize; // Optimal write size [265]\r
- UINT8 OptimalReadSize; // Optimal read size [266]\r
- UINT8 PreEolInfo; // Pre EOL information [267]\r
- UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r
- UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r
- UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r
- UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r
- UINT8 Reserved21[181]; // Reserved [486:306]\r
- UINT8 FfuArg[4]; // FFU Argument [490:487]\r
- UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r
- UINT8 FfuFeatures; // FFU features [492]\r
- UINT8 SupportedModes; // Supported modes [493]\r
- UINT8 ExtSupport; // Extended partitions attribute support [494]\r
- UINT8 LargeUnitSizeM1; // Large Unit size [495]\r
- UINT8 ContextCapabilities; // Context management capabilities [496]\r
- UINT8 TagResSize; // Tag Resources Size [497]\r
- UINT8 TagUnitSize; // Tag Unit Size [498]\r
- UINT8 DataTagSupport; // Data Tag Support [499]\r
- UINT8 MaxPackedWrites; // Max packed write commands [500]\r
- UINT8 MaxPackedReads; // Max packed read commands[501]\r
- UINT8 BkOpsSupport; // Background operations support [502]\r
- UINT8 HpiFeatures; // HPI features [503]\r
- UINT8 SupportedCmdSet; // Supported Command Sets [504]\r
- UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r
- UINT8 Reserved22[6]; // Reserved [511:506]\r
+ UINT8 ExtCsdRev; // Extended CSD revision [192]\r
+ UINT8 Reserved14; // Reserved [193]\r
+ UINT8 CsdStructure; // CSD STRUCTURE [194]\r
+ UINT8 Reserved15; // Reserved [195]\r
+ UINT8 DeviceType; // Device type [196]\r
+ UINT8 DriverStrength; // I/O Driver Strength [197]\r
+ UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r
+ UINT8 PartitionSwitchTime; // Partition switching timing [199]\r
+ UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r
+ UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r
+ UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r
+ UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r
+ UINT8 Reserved16; // Reserved [204]\r
+ UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r
+ UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r
+ UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r
+ UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r
+ UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r
+ UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
+ UINT8 Reserved17; // Reserved [211]\r
+ UINT8 SecCount[4]; // Sector Count [215:212]\r
+ UINT8 SleepNotificationTime; // Sleep Notification Timeout [216]\r
+ UINT8 SATimeout; // Sleep/awake timeout [217]\r
+ UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
+ UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
+ UINT8 SCVcc; // Sleep current (VCC) [220]\r
+ UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r
+ UINT8 RelWrSecC; // Reliable write sector count [222]\r
+ UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r
+ UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r
+ UINT8 AccSize; // Access size [225]\r
+ UINT8 BootSizeMult; // Boot partition size [226]\r
+ UINT8 Reserved18; // Reserved [227]\r
+ UINT8 BootInfo; // Boot information [228]\r
+ UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r
+ UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r
+ UINT8 SecFeatureSupport; // Secure Feature support [231]\r
+ UINT8 TrimMult; // TRIM Multiplier [232]\r
+ UINT8 Reserved19; // Reserved [233]\r
+ UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r
+ UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r
+ UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r
+ UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r
+ UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r
+ UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r
+ UINT8 Reserved20; // Reserved [240]\r
+ UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r
+ UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r
+ UINT8 BkopsStatus; // Background operations status [246]\r
+ UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r
+ UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r
+ UINT8 CacheSize[4]; // Cache size [252:249]\r
+ UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r
+ UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r
+ UINT8 DeviceVersion[2]; // Device version [263:262]\r
+ UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r
+ UINT8 OptimalWriteSize; // Optimal write size [265]\r
+ UINT8 OptimalReadSize; // Optimal read size [266]\r
+ UINT8 PreEolInfo; // Pre EOL information [267]\r
+ UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r
+ UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r
+ UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r
+ UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r
+ UINT8 Reserved21[181]; // Reserved [486:306]\r
+ UINT8 FfuArg[4]; // FFU Argument [490:487]\r
+ UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r
+ UINT8 FfuFeatures; // FFU features [492]\r
+ UINT8 SupportedModes; // Supported modes [493]\r
+ UINT8 ExtSupport; // Extended partitions attribute support [494]\r
+ UINT8 LargeUnitSizeM1; // Large Unit size [495]\r
+ UINT8 ContextCapabilities; // Context management capabilities [496]\r
+ UINT8 TagResSize; // Tag Resources Size [497]\r
+ UINT8 TagUnitSize; // Tag Unit Size [498]\r
+ UINT8 DataTagSupport; // Data Tag Support [499]\r
+ UINT8 MaxPackedWrites; // Max packed write commands [500]\r
+ UINT8 MaxPackedReads; // Max packed read commands[501]\r
+ UINT8 BkOpsSupport; // Background operations support [502]\r
+ UINT8 HpiFeatures; // HPI features [503]\r
+ UINT8 SupportedCmdSet; // Supported Command Sets [504]\r
+ UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r
+ UINT8 Reserved22[6]; // Reserved [511:506]\r
} EMMC_EXT_CSD;\r
\r
#pragma pack()\r
///\r
typedef union {\r
struct {\r
- UINT32 Revision : 8;\r
- UINT32 NumberOfTimers : 5;\r
- UINT32 CounterSize : 1;\r
- UINT32 Reserved : 1;\r
- UINT32 LegacyRoute : 1;\r
- UINT32 VendorId : 16;\r
+ UINT32 Revision : 8;\r
+ UINT32 NumberOfTimers : 5;\r
+ UINT32 CounterSize : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 LegacyRoute : 1;\r
+ UINT32 VendorId : 16;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;\r
\r
-\r
///\r
/// High Precision Event Timer Table header definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 EventTimerBlockId;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;\r
- UINT8 HpetNumber;\r
- UINT16 MainCounterMinimumClockTickInPeriodicMode;\r
- UINT8 PageProtectionAndOemAttribute;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 EventTimerBlockId;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddressLower32Bit;\r
+ UINT8 HpetNumber;\r
+ UINT16 MainCounterMinimumClockTickInPeriodicMode;\r
+ UINT8 PageProtectionAndOemAttribute;\r
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;\r
\r
///\r
// Page protection setting\r
// Values 3 through 15 are reserved for use by the specification\r
//\r
-#define EFI_ACPI_NO_PAGE_PROTECTION 0\r
-#define EFI_ACPI_4KB_PAGE_PROTECTION 1\r
-#define EFI_ACPI_64KB_PAGE_PROTECTION 2\r
+#define EFI_ACPI_NO_PAGE_PROTECTION 0\r
+#define EFI_ACPI_4KB_PAGE_PROTECTION 1\r
+#define EFI_ACPI_64KB_PAGE_PROTECTION 2\r
\r
#pragma pack()\r
\r
#define ADAPTER_INFO_PLATFORM_SECURITY_GUID \\r
{0x6be272c7, 0x1320, 0x4ccd, { 0x90, 0x17, 0xd4, 0x61, 0x2c, 0x01, 0x2b, 0x25 }}\r
\r
-#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003\r
+#define PLATFORM_SECURITY_VERSION_VNEXTCS 0x00000003\r
\r
-#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV\r
-#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002\r
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003\r
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004\r
+#define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001 // IHV\r
+#define PLATFORM_SECURITY_ROLE_PLATFORM_IBV 0x00000002\r
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM 0x00000003\r
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM 0x00000004\r
\r
typedef struct {\r
//\r
// Return PLATFORM_SECURITY_VERSION_VNEXTCS\r
//\r
- UINT32 Version;\r
+ UINT32 Version;\r
//\r
// The role of the publisher of this interface. Reference platform designers\r
// such as IHVs and IBVs are expected to return PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE\r
// security features, then the platform implementers, OEMs and ODMs, will\r
// need to publish this interface with a role of Implementer.\r
//\r
- UINT32 Role;\r
+ UINT32 Role;\r
//\r
// Human readable vendor, model, & version of this implementation.\r
//\r
- CHAR16 ImplementationID[256];\r
+ CHAR16 ImplementationID[256];\r
//\r
// The size in bytes of the SecurityFeaturesRequired and SecurityFeaturesEnabled arrays.\r
// The arrays must be the same size.\r
//\r
- UINT32 SecurityFeaturesSize;\r
+ UINT32 SecurityFeaturesSize;\r
//\r
// IHV-defined bitfield corresponding to all security features which must be\r
// implemented to meet the security requirements defined by PLATFORM_SECURITY_VERSION Version.\r
//\r
-//UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV\r
+ // UINT8 SecurityFeaturesRequired[]; //Ignored for non-IHV\r
//\r
// Publisher-defined bitfield corresponding to all security features which\r
// have implemented programmatic tests in this module.\r
//\r
-//UINT8 SecurityFeaturesImplemented[];\r
+ // UINT8 SecurityFeaturesImplemented[];\r
//\r
// Publisher-defined bitfield corresponding to all security features which\r
// have been verified implemented by this implementation.\r
//\r
-//UINT8 SecurityFeaturesVerified[];\r
+ // UINT8 SecurityFeaturesVerified[];\r
//\r
// A Null-terminated string, one failure per line (CR/LF terminated), with a\r
// unique identifier that the OEM/ODM can use to locate the documentation\r
// which will describe the steps to remediate the failure - a URL to the\r
// documentation is recommended.\r
//\r
-//CHAR16 ErrorString[];\r
+ // CHAR16 ErrorString[];\r
} ADAPTER_INFO_PLATFORM_SECURITY;\r
\r
#pragma pack()\r
\r
-extern EFI_GUID gAdapterInfoPlatformSecurityGuid;\r
+extern EFI_GUID gAdapterInfoPlatformSecurityGuid;\r
\r
#endif\r
/// The version of an HTTP message is indicated by an HTTP-Version field\r
/// in the first line of the message.\r
///\r
-#define HTTP_VERSION "HTTP/1.1"\r
+#define HTTP_VERSION "HTTP/1.1"\r
\r
///\r
/// HTTP Request Method definitions\r
/// The Method token indicates the method to be performed on the\r
/// resource identified by the Request-URI. The method is case-sensitive.\r
///\r
-#define HTTP_METHOD_OPTIONS "OPTIONS"\r
-#define HTTP_METHOD_GET "GET"\r
-#define HTTP_METHOD_HEAD "HEAD"\r
-#define HTTP_METHOD_POST "POST"\r
-#define HTTP_METHOD_PUT "PUT"\r
-#define HTTP_METHOD_DELETE "DELETE"\r
-#define HTTP_METHOD_TRACE "TRACE"\r
-#define HTTP_METHOD_CONNECT "CONNECT"\r
-#define HTTP_METHOD_PATCH "PATCH"\r
+#define HTTP_METHOD_OPTIONS "OPTIONS"\r
+#define HTTP_METHOD_GET "GET"\r
+#define HTTP_METHOD_HEAD "HEAD"\r
+#define HTTP_METHOD_POST "POST"\r
+#define HTTP_METHOD_PUT "PUT"\r
+#define HTTP_METHOD_DELETE "DELETE"\r
+#define HTTP_METHOD_TRACE "TRACE"\r
+#define HTTP_METHOD_CONNECT "CONNECT"\r
+#define HTTP_METHOD_PATCH "PATCH"\r
\r
///\r
/// Connect method has maximum length according to EFI_HTTP_METHOD defined in\r
/// is specifically limited to a small set of desired types, as in the case of a request\r
/// for an in-line image.\r
///\r
-#define HTTP_HEADER_ACCEPT "Accept"\r
-\r
+#define HTTP_HEADER_ACCEPT "Accept"\r
\r
///\r
/// Accept-Charset Request Header\r
/// more comprehensive or special-purpose character sets to signal that capability to a\r
/// server which is capable of representing documents in those character sets.\r
///\r
-#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"\r
+#define HTTP_HEADER_ACCEPT_CHARSET "Accept-Charset"\r
\r
///\r
/// Accept-Language Request Header\r
/// but restricts the set of natural languages that are preferred\r
/// as a response to the request.\r
///\r
-#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"\r
+#define HTTP_HEADER_ACCEPT_LANGUAGE "Accept-Language"\r
\r
///\r
/// Accept-Ranges Request Header\r
/// The Accept-Ranges response-header field allows the server to\r
/// indicate its acceptance of range requests for a resource:\r
///\r
-#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"\r
-\r
+#define HTTP_HEADER_ACCEPT_RANGES "Accept-Ranges"\r
\r
///\r
/// Accept-Encoding Request Header\r
/// The Accept-Encoding request-header field is similar to Accept,\r
/// but restricts the content-codings that are acceptable in the response.\r
///\r
-#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"\r
+#define HTTP_HEADER_ACCEPT_ENCODING "Accept-Encoding"\r
\r
///\r
/// Content-Encoding Header\r
/// is primarily used to allow a document to be compressed without losing the identity\r
/// of its underlying media type.\r
///\r
-#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"\r
+#define HTTP_HEADER_CONTENT_ENCODING "Content-Encoding"\r
\r
///\r
/// HTTP Content-Encoding Compression types\r
///\r
\r
-#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.\r
-#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).\r
-#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".\r
-#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"\r
+#define HTTP_CONTENT_ENCODING_IDENTITY "identity" /// No transformation is used. This is the default value for content coding.\r
+#define HTTP_CONTENT_ENCODING_GZIP "gzip" /// Content-Encoding: GNU zip format (described in RFC 1952).\r
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress" /// encoding format produced by the common UNIX file compression program "compress".\r
+#define HTTP_CONTENT_ENCODING_DEFLATE "deflate" /// The "zlib" format defined in RFC 1950 in combination with the "deflate"\r
/// compression mechanism described in RFC 1951.\r
\r
-\r
///\r
/// Content-Type Header\r
/// The Content-Type entity-header field indicates the media type of the entity-body sent to\r
/// the recipient or, in the case of the HEAD method, the media type that would have been sent\r
/// had the request been a GET.\r
///\r
-#define HTTP_HEADER_CONTENT_TYPE "Content-Type"\r
+#define HTTP_HEADER_CONTENT_TYPE "Content-Type"\r
//\r
// Common Media Types defined in http://www.iana.org/assignments/media-types/media-types.xhtml\r
//\r
#define HTTP_CONTENT_TYPE_APP_JSON "application/json"\r
#define HTTP_CONTENT_TYPE_APP_OCTET_STREAM "application/octet-stream"\r
\r
-#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"\r
-#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"\r
-#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"\r
-#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"\r
-\r
-#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"\r
-#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"\r
-#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"\r
-#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml"\r
+#define HTTP_CONTENT_TYPE_TEXT_HTML "text/html"\r
+#define HTTP_CONTENT_TYPE_TEXT_PLAIN "text/plain"\r
+#define HTTP_CONTENT_TYPE_TEXT_CSS "text/css"\r
+#define HTTP_CONTENT_TYPE_TEXT_XML "text/xml"\r
\r
+#define HTTP_CONTENT_TYPE_IMAGE_GIF "image/gif"\r
+#define HTTP_CONTENT_TYPE_IMAGE_JPEG "image/jpeg"\r
+#define HTTP_CONTENT_TYPE_IMAGE_PNG "image/png"\r
+#define HTTP_CONTENT_TYPE_IMAGE_SVG_XML "image/svg+xml"\r
\r
///\r
/// Content-Length Header\r
/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD\r
/// method, the size of the entity-body that would have been sent had the request been a GET.\r
///\r
-#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"\r
+#define HTTP_HEADER_CONTENT_LENGTH "Content-Length"\r
\r
///\r
/// Transfer-Encoding Header\r
/// and the recipient. This differs from the content-coding in that the transfer-coding\r
/// is a property of the message, not of the entity.\r
///\r
-#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"\r
-#define HTTP_HEADER_TRANSFER_ENCODING_CHUNKED "chunked"\r
-#define CHUNKED_TRANSFER_CODING_CR '\r'\r
-#define CHUNKED_TRANSFER_CODING_LF '\n'\r
-#define CHUNKED_TRANSFER_CODING_LAST_CHUNK '0'\r
-#define CHUNKED_TRANSFER_CODING_EXTENSION_SEPARATOR ';'\r
+#define HTTP_HEADER_TRANSFER_ENCODING "Transfer-Encoding"\r
+#define HTTP_HEADER_TRANSFER_ENCODING_CHUNKED "chunked"\r
+#define CHUNKED_TRANSFER_CODING_CR '\r'\r
+#define CHUNKED_TRANSFER_CODING_LF '\n'\r
+#define CHUNKED_TRANSFER_CODING_LAST_CHUNK '0'\r
+#define CHUNKED_TRANSFER_CODING_EXTENSION_SEPARATOR ';'\r
\r
///\r
/// User Agent Request Header\r
/// By convention, the product tokens are listed in order of their significance for\r
/// identifying the application.\r
///\r
-#define HTTP_HEADER_USER_AGENT "User-Agent"\r
+#define HTTP_HEADER_USER_AGENT "User-Agent"\r
\r
///\r
/// Host Request Header\r
/// The Host request-header field specifies the Internet host and port number of the resource\r
/// being requested, as obtained from the original URI given by the user or referring resource\r
///\r
-#define HTTP_HEADER_HOST "Host"\r
+#define HTTP_HEADER_HOST "Host"\r
\r
///\r
/// Location Response Header\r
/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for\r
/// automatic redirection to the resource. The field value consists of a single absolute URI.\r
///\r
-#define HTTP_HEADER_LOCATION "Location"\r
+#define HTTP_HEADER_LOCATION "Location"\r
\r
///\r
/// The If-Match request-header field is used with a method to make it conditional.\r
/// to prevent inadvertent modification of the wrong version of a resource.\r
/// As a special case, the value "*" matches any current entity of the resource.\r
///\r
-#define HTTP_HEADER_IF_MATCH "If-Match"\r
-\r
+#define HTTP_HEADER_IF_MATCH "If-Match"\r
\r
///\r
/// The If-None-Match request-header field is used with a method to make it conditional.\r
/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the\r
/// client believes that the resource does not exist.\r
///\r
-#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"\r
-\r
-\r
+#define HTTP_HEADER_IF_NONE_MATCH "If-None-Match"\r
\r
///\r
/// Authorization Request Header\r
/// containing the authentication information of the user agent for\r
/// the realm of the resource being requested.\r
///\r
-#define HTTP_HEADER_AUTHORIZATION "Authorization"\r
+#define HTTP_HEADER_AUTHORIZATION "Authorization"\r
\r
///\r
/// ETAG Response Header\r
/// The ETag response-header field provides the current value of the entity tag\r
/// for the requested variant.\r
///\r
-#define HTTP_HEADER_ETAG "ETag"\r
+#define HTTP_HEADER_ETAG "ETag"\r
\r
///\r
/// Custom header field checked by the iLO web server to\r
/// specify a client session key.\r
/// Example: X-Auth-Token: 24de6b1f8fa147ad59f6452def628798\r
///\r
-#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token"\r
+#define HTTP_HEADER_X_AUTH_TOKEN "X-Auth-Token"\r
\r
///\r
/// Expect Header\r
/// order to properly handle this request. The only such expectation\r
/// defined by this specification is 100-continue.\r
///\r
-#define HTTP_HEADER_EXPECT "Expect"\r
+#define HTTP_HEADER_EXPECT "Expect"\r
\r
///\r
/// Expect Header Value\r
///\r
-#define HTTP_EXPECT_100_CONTINUE "100-continue"\r
+#define HTTP_EXPECT_100_CONTINUE "100-continue"\r
\r
#pragma pack()\r
\r
#ifndef _ISCSI_BOOT_FIRMWARE_TABLE_H_\r
#define _ISCSI_BOOT_FIRMWARE_TABLE_H_\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_REVISION 0x01\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_ALIGNMENT 8\r
\r
///\r
/// Structure Type/ID\r
///\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_RESERVED_STRUCTURE_ID 0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_ID 1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_ID 2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_ID 3\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_ID 4\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_EXTERNSIONS_STRUCTURE_ID 5\r
\r
///\r
/// from the definition of IP_PREFIX_ORIGIN Enumeration in MSDN,\r
/// iBF Table Header\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 Length;\r
- UINT8 Revision;\r
- UINT8 Checksum;\r
- UINT8 OemId[6];\r
- UINT64 OemTableId;\r
- UINT8 Reserved[24];\r
+ UINT32 Signature;\r
+ UINT32 Length;\r
+ UINT8 Revision;\r
+ UINT8 Checksum;\r
+ UINT8 OemId[6];\r
+ UINT64 OemTableId;\r
+ UINT8 Reserved[24];\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;\r
\r
///\r
/// Common Header of Boot Firmware Table Structure\r
///\r
typedef struct {\r
- UINT8 StructureId;\r
- UINT8 Version;\r
- UINT16 Length;\r
- UINT8 Index;\r
- UINT8 Flags;\r
+ UINT8 StructureId;\r
+ UINT8 Version;\r
+ UINT16 Length;\r
+ UINT8 Index;\r
+ UINT8 Flags;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER;\r
\r
///\r
/// Control Structure\r
///\r
typedef struct {\r
- EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
- UINT16 Extensions;\r
- UINT16 InitiatorOffset;\r
- UINT16 NIC0Offset;\r
- UINT16 Target0Offset;\r
- UINT16 NIC1Offset;\r
- UINT16 Target1Offset;\r
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
+ UINT16 Extensions;\r
+ UINT16 InitiatorOffset;\r
+ UINT16 NIC0Offset;\r
+ UINT16 Target0Offset;\r
+ UINT16 NIC1Offset;\r
+ UINT16 Target1Offset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION 0x1\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_FLAG_BOOT_FAILOVER BIT0\r
\r
///\r
/// Initiator Structure\r
///\r
typedef struct {\r
- EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
- EFI_IPv6_ADDRESS ISnsServer;\r
- EFI_IPv6_ADDRESS SlpServer;\r
- EFI_IPv6_ADDRESS PrimaryRadiusServer;\r
- EFI_IPv6_ADDRESS SecondaryRadiusServer;\r
- UINT16 IScsiNameLength;\r
- UINT16 IScsiNameOffset;\r
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
+ EFI_IPv6_ADDRESS ISnsServer;\r
+ EFI_IPv6_ADDRESS SlpServer;\r
+ EFI_IPv6_ADDRESS PrimaryRadiusServer;\r
+ EFI_IPv6_ADDRESS SecondaryRadiusServer;\r
+ UINT16 IScsiNameLength;\r
+ UINT16 IScsiNameOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION 0x1\r
\r
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
/// NIC Structure\r
///\r
typedef struct {\r
- EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
- EFI_IPv6_ADDRESS Ip;\r
- UINT8 SubnetMaskPrefixLength;\r
- UINT8 Origin;\r
- EFI_IPv6_ADDRESS Gateway;\r
- EFI_IPv6_ADDRESS PrimaryDns;\r
- EFI_IPv6_ADDRESS SecondaryDns;\r
- EFI_IPv6_ADDRESS DhcpServer;\r
- UINT16 VLanTag;\r
- UINT8 Mac[6];\r
- UINT16 PciLocation;\r
- UINT16 HostNameLength;\r
- UINT16 HostNameOffset;\r
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
+ EFI_IPv6_ADDRESS Ip;\r
+ UINT8 SubnetMaskPrefixLength;\r
+ UINT8 Origin;\r
+ EFI_IPv6_ADDRESS Gateway;\r
+ EFI_IPv6_ADDRESS PrimaryDns;\r
+ EFI_IPv6_ADDRESS SecondaryDns;\r
+ EFI_IPv6_ADDRESS DhcpServer;\r
+ UINT16 VLanTag;\r
+ UINT8 Mac[6];\r
+ UINT16 PciLocation;\r
+ UINT16 HostNameLength;\r
+ UINT16 HostNameOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_VERSION 0x1\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_NIC_STRUCTURE_FLAG_GLOBAL BIT2\r
\r
///\r
/// Target Structure\r
///\r
typedef struct {\r
- EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
- EFI_IPv6_ADDRESS Ip;\r
- UINT16 Port;\r
- UINT8 BootLun[8];\r
- UINT8 CHAPType;\r
- UINT8 NicIndex;\r
- UINT16 IScsiNameLength;\r
- UINT16 IScsiNameOffset;\r
- UINT16 CHAPNameLength;\r
- UINT16 CHAPNameOffset;\r
- UINT16 CHAPSecretLength;\r
- UINT16 CHAPSecretOffset;\r
- UINT16 ReverseCHAPNameLength;\r
- UINT16 ReverseCHAPNameOffset;\r
- UINT16 ReverseCHAPSecretLength;\r
- UINT16 ReverseCHAPSecretOffset;\r
+ EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_STRUCTURE_HEADER Header;\r
+ EFI_IPv6_ADDRESS Ip;\r
+ UINT16 Port;\r
+ UINT8 BootLun[8];\r
+ UINT8 CHAPType;\r
+ UINT8 NicIndex;\r
+ UINT16 IScsiNameLength;\r
+ UINT16 IScsiNameOffset;\r
+ UINT16 CHAPNameLength;\r
+ UINT16 CHAPNameOffset;\r
+ UINT16 CHAPSecretLength;\r
+ UINT16 CHAPSecretOffset;\r
+ UINT16 ReverseCHAPNameLength;\r
+ UINT16 ReverseCHAPNameOffset;\r
+ UINT16 ReverseCHAPSecretLength;\r
+ UINT16 ReverseCHAPSecretOffset;\r
} EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE;\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_VERSION 0x1\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BLOCK_VALID BIT0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_BOOT_SELECTED BIT1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_CHAP BIT2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_FLAG_RADIUS_RCHAP BIT3\r
\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1\r
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_NO_CHAP 0\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_CHAP 1\r
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_TARGET_STRUCTURE_CHAP_TYPE_MUTUAL_CHAP 2\r
\r
#pragma pack()\r
\r
#endif\r
-\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
-#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0\r
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0\r
\r
-#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r
-#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r
-#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r
-#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r
-#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r
-#define EFI_ACPI_IORT_TYPE_PMCG 0x5\r
+#define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r
+#define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r
+#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r
+#define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r
+#define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r
+#define EFI_ACPI_IORT_TYPE_PMCG 0x5\r
\r
-#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r
\r
-#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r
-#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r
-#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r
-#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r
\r
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r
-#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r
\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r
#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r
\r
-#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r
-#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r
\r
-#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r
-#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r
\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r
#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3\r
\r
-#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r
-#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r
-#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r
+#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r
\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r
#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1\r
\r
-#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r
+#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r
\r
#pragma pack(1)\r
\r
/// Table header\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 NumNodes;\r
- UINT32 NodeOffset;\r
- UINT32 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 NumNodes;\r
+ UINT32 NodeOffset;\r
+ UINT32 Reserved;\r
} EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r
\r
///\r
/// Definition for ID mapping table shared by all node types\r
///\r
typedef struct {\r
- UINT32 InputBase;\r
- UINT32 NumIds;\r
- UINT32 OutputBase;\r
- UINT32 OutputReference;\r
- UINT32 Flags;\r
+ UINT32 InputBase;\r
+ UINT32 NumIds;\r
+ UINT32 OutputBase;\r
+ UINT32 OutputReference;\r
+ UINT32 Flags;\r
} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r
\r
///\r
/// Node header definition shared by all node types\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT16 Length;\r
- UINT8 Revision;\r
- UINT32 Reserved;\r
- UINT32 NumIdMappings;\r
- UINT32 IdReference;\r
+ UINT8 Type;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT32 Reserved;\r
+ UINT32 NumIdMappings;\r
+ UINT32 IdReference;\r
} EFI_ACPI_6_0_IO_REMAPPING_NODE;\r
\r
///\r
/// Node type 0: ITS node\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
\r
- UINT32 NumItsIdentifiers;\r
-//UINT32 ItsIdentifiers[NumItsIdentifiers];\r
+ UINT32 NumItsIdentifiers;\r
+ // UINT32 ItsIdentifiers[NumItsIdentifiers];\r
} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r
\r
///\r
/// Node type 1: root complex node\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
\r
- UINT32 CacheCoherent;\r
- UINT8 AllocationHints;\r
- UINT16 Reserved;\r
- UINT8 MemoryAccessFlags;\r
+ UINT32 CacheCoherent;\r
+ UINT8 AllocationHints;\r
+ UINT16 Reserved;\r
+ UINT8 MemoryAccessFlags;\r
\r
- UINT32 AtsAttribute;\r
- UINT32 PciSegmentNumber;\r
- UINT8 MemoryAddressSize;\r
- UINT8 Reserved1[3];\r
+ UINT32 AtsAttribute;\r
+ UINT32 PciSegmentNumber;\r
+ UINT8 MemoryAddressSize;\r
+ UINT8 Reserved1[3];\r
} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r
\r
///\r
/// Node type 2: named component node\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
-\r
- UINT32 Flags;\r
- UINT32 CacheCoherent;\r
- UINT8 AllocationHints;\r
- UINT16 Reserved;\r
- UINT8 MemoryAccessFlags;\r
- UINT8 AddressSizeLimit;\r
-//UINT8 ObjectName[];\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+\r
+ UINT32 Flags;\r
+ UINT32 CacheCoherent;\r
+ UINT8 AllocationHints;\r
+ UINT16 Reserved;\r
+ UINT8 MemoryAccessFlags;\r
+ UINT8 AddressSizeLimit;\r
+ // UINT8 ObjectName[];\r
} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r
\r
///\r
/// Node type 3: SMMUv1 or SMMUv2 node\r
///\r
typedef struct {\r
- UINT32 Interrupt;\r
- UINT32 InterruptFlags;\r
+ UINT32 Interrupt;\r
+ UINT32 InterruptFlags;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r
\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
-\r
- UINT64 Base;\r
- UINT64 Span;\r
- UINT32 Model;\r
- UINT32 Flags;\r
- UINT32 GlobalInterruptArrayRef;\r
- UINT32 NumContextInterrupts;\r
- UINT32 ContextInterruptArrayRef;\r
- UINT32 NumPmuInterrupts;\r
- UINT32 PmuInterruptArrayRef;\r
-\r
- UINT32 SMMU_NSgIrpt;\r
- UINT32 SMMU_NSgIrptFlags;\r
- UINT32 SMMU_NSgCfgIrpt;\r
- UINT32 SMMU_NSgCfgIrptFlags;\r
-\r
-//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r
-//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+\r
+ UINT64 Base;\r
+ UINT64 Span;\r
+ UINT32 Model;\r
+ UINT32 Flags;\r
+ UINT32 GlobalInterruptArrayRef;\r
+ UINT32 NumContextInterrupts;\r
+ UINT32 ContextInterruptArrayRef;\r
+ UINT32 NumPmuInterrupts;\r
+ UINT32 PmuInterruptArrayRef;\r
+\r
+ UINT32 SMMU_NSgIrpt;\r
+ UINT32 SMMU_NSgIrptFlags;\r
+ UINT32 SMMU_NSgCfgIrpt;\r
+ UINT32 SMMU_NSgCfgIrptFlags;\r
+\r
+ // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r
+ // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r
\r
///\r
/// Node type 4: SMMUv3 node\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
-\r
- UINT64 Base;\r
- UINT32 Flags;\r
- UINT32 Reserved;\r
- UINT64 VatosAddress;\r
- UINT32 Model;\r
- UINT32 Event;\r
- UINT32 Pri;\r
- UINT32 Gerr;\r
- UINT32 Sync;\r
- UINT32 ProximityDomain;\r
- UINT32 DeviceIdMappingIndex;\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+\r
+ UINT64 Base;\r
+ UINT32 Flags;\r
+ UINT32 Reserved;\r
+ UINT64 VatosAddress;\r
+ UINT32 Model;\r
+ UINT32 Event;\r
+ UINT32 Pri;\r
+ UINT32 Gerr;\r
+ UINT32 Sync;\r
+ UINT32 ProximityDomain;\r
+ UINT32 DeviceIdMappingIndex;\r
} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r
\r
///\r
/// Node type 5: PMCG node\r
///\r
typedef struct {\r
- EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
+ EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r
\r
- UINT64 Base;\r
- UINT32 OverflowInterruptGsiv;\r
- UINT32 NodeReference;\r
- UINT64 Page1Base;\r
-//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r
+ UINT64 Base;\r
+ UINT32 OverflowInterruptGsiv;\r
+ UINT32 NodeReference;\r
+ UINT64 Page1Base;\r
+ // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r
} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r
\r
#pragma pack()\r
/// Individual bit fields\r
///\r
struct {\r
- UINT8 FormatVersionNumber:4;\r
- UINT8 Reserved:4;\r
+ UINT8 FormatVersionNumber : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 8-bit value\r
///\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION;\r
\r
typedef struct {\r
- IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion;\r
- UINT8 InternalUseStartingOffset;\r
- UINT8 ChassisInfoStartingOffset;\r
- UINT8 BoardAreaStartingOffset;\r
- UINT8 ProductInfoStartingOffset;\r
- UINT8 MultiRecInfoStartingOffset;\r
- UINT8 Pad;\r
- UINT8 Checksum;\r
+ IPMI_FRU_COMMON_HEADER_FORMAT_VERSION FormatVersion;\r
+ UINT8 InternalUseStartingOffset;\r
+ UINT8 ChassisInfoStartingOffset;\r
+ UINT8 BoardAreaStartingOffset;\r
+ UINT8 ProductInfoStartingOffset;\r
+ UINT8 MultiRecInfoStartingOffset;\r
+ UINT8 Pad;\r
+ UINT8 Checksum;\r
} IPMI_FRU_COMMON_HEADER;\r
\r
//\r
/// Individual bit fields\r
///\r
struct {\r
- UINT8 RecordFormatVersion:4;\r
- UINT8 Reserved:3;\r
- UINT8 EndofList:1;\r
+ UINT8 RecordFormatVersion : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 EndofList : 1;\r
} Bits;\r
///\r
/// All bit fields as a 8-bit value\r
///\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION;\r
\r
typedef struct {\r
- UINT8 RecordTypeId;\r
- IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion;\r
- UINT8 RecordLength;\r
- UINT8 RecordChecksum;\r
- UINT8 HeaderChecksum;\r
+ UINT8 RecordTypeId;\r
+ IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION FormatVersion;\r
+ UINT8 RecordLength;\r
+ UINT8 RecordChecksum;\r
+ UINT8 HeaderChecksum;\r
} IPMI_FRU_MULTI_RECORD_HEADER;\r
\r
//\r
//\r
// Definitions for Get Device ID command\r
//\r
-#define IPMI_APP_GET_DEVICE_ID 0x1\r
+#define IPMI_APP_GET_DEVICE_ID 0x1\r
\r
//\r
// Constants and Structure definitions for "Get Device ID" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 DeviceRevision : 4;\r
- UINT8 Reserved : 3;\r
- UINT8 DeviceSdr : 1;\r
+ UINT8 DeviceRevision : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 DeviceSdr : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_DEVICE_ID_DEVICE_REV;\r
\r
typedef union {\r
struct {\r
- UINT8 MajorFirmwareRev : 7;\r
- UINT8 UpdateMode : 1;\r
+ UINT8 MajorFirmwareRev : 7;\r
+ UINT8 UpdateMode : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_DEVICE_ID_FIRMWARE_REV_1;\r
\r
typedef union {\r
struct {\r
- UINT8 SensorDeviceSupport : 1;\r
- UINT8 SdrRepositorySupport : 1;\r
- UINT8 SelDeviceSupport : 1;\r
- UINT8 FruInventorySupport : 1;\r
- UINT8 IpmbMessageReceiver : 1;\r
- UINT8 IpmbMessageGenerator : 1;\r
- UINT8 BridgeSupport : 1;\r
- UINT8 ChassisSupport : 1;\r
+ UINT8 SensorDeviceSupport : 1;\r
+ UINT8 SdrRepositorySupport : 1;\r
+ UINT8 SelDeviceSupport : 1;\r
+ UINT8 FruInventorySupport : 1;\r
+ UINT8 IpmbMessageReceiver : 1;\r
+ UINT8 IpmbMessageGenerator : 1;\r
+ UINT8 BridgeSupport : 1;\r
+ UINT8 ChassisSupport : 1;\r
} Bits;\r
UINT8 Uint8;\r
} IPMI_GET_DEVICE_ID_DEVICE_SUPPORT;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 DeviceId;\r
- IPMI_GET_DEVICE_ID_DEVICE_REV DeviceRevision;\r
- IPMI_GET_DEVICE_ID_FIRMWARE_REV_1 FirmwareRev1;\r
- UINT8 MinorFirmwareRev;\r
- UINT8 SpecificationVersion;\r
- IPMI_GET_DEVICE_ID_DEVICE_SUPPORT DeviceSupport;\r
- UINT8 ManufacturerId[3];\r
- UINT16 ProductId;\r
- UINT32 AuxFirmwareRevInfo;\r
+ UINT8 CompletionCode;\r
+ UINT8 DeviceId;\r
+ IPMI_GET_DEVICE_ID_DEVICE_REV DeviceRevision;\r
+ IPMI_GET_DEVICE_ID_FIRMWARE_REV_1 FirmwareRev1;\r
+ UINT8 MinorFirmwareRev;\r
+ UINT8 SpecificationVersion;\r
+ IPMI_GET_DEVICE_ID_DEVICE_SUPPORT DeviceSupport;\r
+ UINT8 ManufacturerId[3];\r
+ UINT16 ProductId;\r
+ UINT32 AuxFirmwareRevInfo;\r
} IPMI_GET_DEVICE_ID_RESPONSE;\r
\r
-\r
//\r
// Definitions for Cold Reset command\r
//\r
// Constants and Structure definitions for "Get Self Test Results" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 Result;\r
- UINT8 Param;\r
+ UINT8 CompletionCode;\r
+ UINT8 Result;\r
+ UINT8 Param;\r
} IPMI_SELF_TEST_RESULT_RESPONSE;\r
\r
-#define IPMI_APP_SELFTEST_NO_ERROR 0x55\r
-#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56\r
-#define IPMI_APP_SELFTEST_ERROR 0x57\r
-#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58\r
-#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL 0x80\r
-#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR 0x40\r
-#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU 0x20\r
-#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL 0x10\r
-#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08\r
-#define IPMI_APP_SELFTEST_FRU_CORRUPT 0x04\r
-#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02\r
-#define IPMI_APP_SELFTEST_FW_CORRUPT 0x01\r
+#define IPMI_APP_SELFTEST_NO_ERROR 0x55\r
+#define IPMI_APP_SELFTEST_NOT_IMPLEMENTED 0x56\r
+#define IPMI_APP_SELFTEST_ERROR 0x57\r
+#define IPMI_APP_SELFTEST_FATAL_HW_ERROR 0x58\r
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SEL 0x80\r
+#define IPMI_APP_SELFTEST_INACCESSIBLE_SDR 0x40\r
+#define IPMI_APP_SELFTEST_INACCESSIBLE_FRU 0x20\r
+#define IPMI_APP_SELFTEST_IPMB_SIGNAL_FAIL 0x10\r
+#define IPMI_APP_SELFTEST_SDR_REPOSITORY_EMPTY 0x08\r
+#define IPMI_APP_SELFTEST_FRU_CORRUPT 0x04\r
+#define IPMI_APP_SELFTEST_FW_BOOTBLOCK_CORRUPT 0x02\r
+#define IPMI_APP_SELFTEST_FW_CORRUPT 0x01\r
\r
//\r
// Definitions for Manufacturing Test ON command\r
//\r
-#define IPMI_APP_MANUFACTURING_TEST_ON 0x5\r
+#define IPMI_APP_MANUFACTURING_TEST_ON 0x5\r
\r
//\r
// Constants and Structure definitions for "Manufacturing Test ON" command to follow here\r
//\r
// Definitions for Set ACPI Power State command\r
//\r
-#define IPMI_APP_SET_ACPI_POWERSTATE 0x6\r
+#define IPMI_APP_SET_ACPI_POWERSTATE 0x6\r
\r
//\r
// Constants and Structure definitions for "Set ACPI Power State" command to follow here\r
// Definitions for System Power State\r
//\r
// Working\r
-#define IPMI_SYSTEM_POWER_STATE_S0_G0 0x0\r
-#define IPMI_SYSTEM_POWER_STATE_S1 0x1\r
-#define IPMI_SYSTEM_POWER_STATE_S2 0x2\r
-#define IPMI_SYSTEM_POWER_STATE_S3 0x3\r
-#define IPMI_SYSTEM_POWER_STATE_S4 0x4\r
+#define IPMI_SYSTEM_POWER_STATE_S0_G0 0x0\r
+#define IPMI_SYSTEM_POWER_STATE_S1 0x1\r
+#define IPMI_SYSTEM_POWER_STATE_S2 0x2\r
+#define IPMI_SYSTEM_POWER_STATE_S3 0x3\r
+#define IPMI_SYSTEM_POWER_STATE_S4 0x4\r
// Soft off\r
-#define IPMI_SYSTEM_POWER_STATE_S5_G2 0x5\r
+#define IPMI_SYSTEM_POWER_STATE_S5_G2 0x5\r
// Sent when message source cannot differentiate between S4 and S5\r
-#define IPMI_SYSTEM_POWER_STATE_S4_S5 0x6\r
+#define IPMI_SYSTEM_POWER_STATE_S4_S5 0x6\r
// Mechanical off\r
-#define IPMI_SYSTEM_POWER_STATE_G3 0x7\r
+#define IPMI_SYSTEM_POWER_STATE_G3 0x7\r
// Sleeping - cannot differentiate between S1-S3\r
-#define IPMI_SYSTEM_POWER_STATE_SLEEPING 0x8\r
+#define IPMI_SYSTEM_POWER_STATE_SLEEPING 0x8\r
// Sleeping - cannot differentiate between S1-S4\r
#define IPMI_SYSTEM_POWER_STATE_G1_SLEEPING 0x9\r
// S5 entered by override\r
-#define IPMI_SYSTEM_POWER_STATE_OVERRIDE 0xA\r
-#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON 0x20\r
-#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF 0x21\r
-#define IPMI_SYSTEM_POWER_STATE_UNKNOWN 0x2A\r
-#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE 0x7F\r
+#define IPMI_SYSTEM_POWER_STATE_OVERRIDE 0xA\r
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON 0x20\r
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF 0x21\r
+#define IPMI_SYSTEM_POWER_STATE_UNKNOWN 0x2A\r
+#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE 0x7F\r
\r
//\r
// Definitions for Device Power State\r
//\r
-#define IPMI_DEVICE_POWER_STATE_D0 0x0\r
-#define IPMI_DEVICE_POWER_STATE_D1 0x1\r
-#define IPMI_DEVICE_POWER_STATE_D2 0x2\r
-#define IPMI_DEVICE_POWER_STATE_D3 0x3\r
-#define IPMI_DEVICE_POWER_STATE_UNKNOWN 0x2A\r
-#define IPMI_DEVICE_POWER_STATE_NO_CHANGE 0x7F\r
+#define IPMI_DEVICE_POWER_STATE_D0 0x0\r
+#define IPMI_DEVICE_POWER_STATE_D1 0x1\r
+#define IPMI_DEVICE_POWER_STATE_D2 0x2\r
+#define IPMI_DEVICE_POWER_STATE_D3 0x3\r
+#define IPMI_DEVICE_POWER_STATE_UNKNOWN 0x2A\r
+#define IPMI_DEVICE_POWER_STATE_NO_CHANGE 0x7F\r
\r
typedef union {\r
struct {\r
- UINT8 PowerState : 7;\r
- UINT8 StateChange : 1;\r
+ UINT8 PowerState : 7;\r
+ UINT8 StateChange : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_ACPI_POWER_STATE;\r
\r
typedef struct {\r
- IPMI_ACPI_POWER_STATE SystemPowerState;\r
- IPMI_ACPI_POWER_STATE DevicePowerState;\r
+ IPMI_ACPI_POWER_STATE SystemPowerState;\r
+ IPMI_ACPI_POWER_STATE DevicePowerState;\r
} IPMI_SET_ACPI_POWER_STATE_REQUEST;\r
\r
//\r
// Definitions for Get ACPI Power State command\r
//\r
-#define IPMI_APP_GET_ACPI_POWERSTATE 0x7\r
+#define IPMI_APP_GET_ACPI_POWERSTATE 0x7\r
\r
//\r
// Constants and Structure definitions for "Get ACPI Power State" command to follow here\r
//\r
// Definitions for Get Device GUID command\r
//\r
-#define IPMI_APP_GET_DEVICE_GUID 0x8\r
+#define IPMI_APP_GET_DEVICE_GUID 0x8\r
\r
//\r
// Constants and Structure definitions for "Get Device GUID" command to follow here\r
// Message structure definition for "Get Device Guid" IPMI command\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 Guid[16];\r
+ UINT8 CompletionCode;\r
+ UINT8 Guid[16];\r
} IPMI_GET_DEVICE_GUID_RESPONSE;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 TimerUse : 3;\r
- UINT8 Reserved : 3;\r
- UINT8 TimerRunning : 1;\r
- UINT8 TimerUseExpirationFlagLog : 1;\r
+ UINT8 TimerUse : 3;\r
+ UINT8 Reserved : 3;\r
+ UINT8 TimerRunning : 1;\r
+ UINT8 TimerUseExpirationFlagLog : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_WATCHDOG_TIMER_USE;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 TimeoutAction : 3;\r
- UINT8 Reserved1 : 1;\r
- UINT8 PreTimeoutInterrupt : 3;\r
- UINT8 Reserved2 : 1;\r
+ UINT8 TimeoutAction : 3;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 PreTimeoutInterrupt : 3;\r
+ UINT8 Reserved2 : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_WATCHDOG_TIMER_ACTIONS;\r
\r
//\r
#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OEM BIT5\r
\r
typedef struct {\r
- IPMI_WATCHDOG_TIMER_USE TimerUse;\r
- IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;\r
- UINT8 PretimeoutInterval;\r
- UINT8 TimerUseExpirationFlagsClear;\r
- UINT16 InitialCountdownValue;\r
+ IPMI_WATCHDOG_TIMER_USE TimerUse;\r
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;\r
+ UINT8 PretimeoutInterval;\r
+ UINT8 TimerUseExpirationFlagsClear;\r
+ UINT16 InitialCountdownValue;\r
} IPMI_SET_WATCHDOG_TIMER_REQUEST;\r
\r
//\r
// Constants and Structure definitions for "Get WatchDog Timer" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_WATCHDOG_TIMER_USE TimerUse;\r
- IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;\r
- UINT8 PretimeoutInterval;\r
- UINT8 TimerUseExpirationFlagsClear;\r
- UINT16 InitialCountdownValue;\r
- UINT16 PresentCountdownValue;\r
+ UINT8 CompletionCode;\r
+ IPMI_WATCHDOG_TIMER_USE TimerUse;\r
+ IPMI_WATCHDOG_TIMER_ACTIONS TimerActions;\r
+ UINT8 PretimeoutInterval;\r
+ UINT8 TimerUseExpirationFlagsClear;\r
+ UINT16 InitialCountdownValue;\r
+ UINT16 PresentCountdownValue;\r
} IPMI_GET_WATCHDOG_TIMER_RESPONSE;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 ReceiveMessageQueueInterrupt : 1;\r
- UINT8 EventMessageBufferFullInterrupt : 1;\r
- UINT8 EventMessageBuffer : 1;\r
- UINT8 SystemEventLogging : 1;\r
- UINT8 Reserved : 1;\r
- UINT8 Oem0Enable : 1;\r
- UINT8 Oem1Enable : 1;\r
- UINT8 Oem2Enable : 1;\r
+ UINT8 ReceiveMessageQueueInterrupt : 1;\r
+ UINT8 EventMessageBufferFullInterrupt : 1;\r
+ UINT8 EventMessageBuffer : 1;\r
+ UINT8 SystemEventLogging : 1;\r
+ UINT8 Reserved : 1;\r
+ UINT8 Oem0Enable : 1;\r
+ UINT8 Oem1Enable : 1;\r
+ UINT8 Oem2Enable : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BMC_GLOBAL_ENABLES;\r
\r
typedef struct {\r
- IPMI_BMC_GLOBAL_ENABLES SetEnables;\r
+ IPMI_BMC_GLOBAL_ENABLES SetEnables;\r
} IPMI_SET_BMC_GLOBAL_ENABLES_REQUEST;\r
\r
//\r
// Constants and Structure definitions for "Get BMC Global Enables " command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_BMC_GLOBAL_ENABLES GetEnables;\r
+ UINT8 CompletionCode;\r
+ IPMI_BMC_GLOBAL_ENABLES GetEnables;\r
} IPMI_GET_BMC_GLOBAL_ENABLES_RESPONSE;\r
\r
//\r
// Definitions for Clear Message Flags command\r
//\r
-#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30\r
+#define IPMI_APP_CLEAR_MESSAGE_FLAGS 0x30\r
\r
//\r
// Constants and Structure definitions for "Clear Message Flags" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ReceiveMessageQueue : 1;\r
- UINT8 EventMessageBuffer : 1;\r
- UINT8 Reserved1 : 1;\r
- UINT8 WatchdogPerTimeoutInterrupt : 1;\r
- UINT8 Reserved2 : 1;\r
- UINT8 Oem0 : 1;\r
- UINT8 Oem1 : 1;\r
- UINT8 Oem2 : 1;\r
+ UINT8 ReceiveMessageQueue : 1;\r
+ UINT8 EventMessageBuffer : 1;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 WatchdogPerTimeoutInterrupt : 1;\r
+ UINT8 Reserved2 : 1;\r
+ UINT8 Oem0 : 1;\r
+ UINT8 Oem1 : 1;\r
+ UINT8 Oem2 : 1;\r
} Bits;\r
UINT8 Uint8;\r
} IPMI_MESSAGE_FLAGS;\r
\r
typedef struct {\r
- IPMI_MESSAGE_FLAGS ClearFlags;\r
+ IPMI_MESSAGE_FLAGS ClearFlags;\r
} IPMI_CLEAR_MESSAGE_FLAGS_REQUEST;\r
\r
//\r
// Definitions for Get Message Flags command\r
//\r
-#define IPMI_APP_GET_MESSAGE_FLAGS 0x31\r
+#define IPMI_APP_GET_MESSAGE_FLAGS 0x31\r
\r
//\r
// Constants and Structure definitions for "Get Message Flags" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_MESSAGE_FLAGS GetFlags;\r
+ UINT8 CompletionCode;\r
+ IPMI_MESSAGE_FLAGS GetFlags;\r
} IPMI_GET_MESSAGE_FLAGS_RESPONSE;\r
\r
//\r
//\r
// Definitions for Get Message command\r
//\r
-#define IPMI_APP_GET_MESSAGE 0x33\r
+#define IPMI_APP_GET_MESSAGE 0x33\r
\r
//\r
// Constants and Structure definitions for "Get Message" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ChannelNumber : 4;\r
- UINT8 InferredPrivilegeLevel : 4;\r
+ UINT8 ChannelNumber : 4;\r
+ UINT8 InferredPrivilegeLevel : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_MESSAGE_CHANNEL_NUMBER;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_GET_MESSAGE_CHANNEL_NUMBER ChannelNumber;\r
- UINT8 MessageData[0];\r
+ UINT8 CompletionCode;\r
+ IPMI_GET_MESSAGE_CHANNEL_NUMBER ChannelNumber;\r
+ UINT8 MessageData[0];\r
} IPMI_GET_MESSAGE_RESPONSE;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 ChannelNumber : 4;\r
- UINT8 Authentication : 1;\r
- UINT8 Encryption : 1;\r
- UINT8 Tracking : 2;\r
+ UINT8 ChannelNumber : 4;\r
+ UINT8 Authentication : 1;\r
+ UINT8 Encryption : 1;\r
+ UINT8 Tracking : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SEND_MESSAGE_CHANNEL_NUMBER;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_SEND_MESSAGE_CHANNEL_NUMBER ChannelNumber;\r
- UINT8 MessageData[0];\r
+ UINT8 CompletionCode;\r
+ IPMI_SEND_MESSAGE_CHANNEL_NUMBER ChannelNumber;\r
+ UINT8 MessageData[0];\r
} IPMI_SEND_MESSAGE_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ResponseData[0];\r
+ UINT8 CompletionCode;\r
+ UINT8 ResponseData[0];\r
} IPMI_SEND_MESSAGE_RESPONSE;\r
\r
//\r
// Definitions for Read Event Message Buffer command\r
//\r
-#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35\r
+#define IPMI_APP_READ_EVENT_MSG_BUFFER 0x35\r
\r
//\r
// Constants and Structure definitions for "Read Event Message Buffer" command to follow here\r
//\r
// Definitions for Get BT Interface Capabilities command\r
//\r
-#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36\r
+#define IPMI_APP_GET_BT_INTERFACE_CAPABILITY 0x36\r
\r
//\r
// Constants and Structure definitions for "Get BT Interface Capabilities" command to follow here\r
//\r
// Definitions for Get System GUID command\r
//\r
-#define IPMI_APP_GET_SYSTEM_GUID 0x37\r
+#define IPMI_APP_GET_SYSTEM_GUID 0x37\r
\r
//\r
// Constants and Structure definitions for "Get System GUID" command to follow here\r
//\r
// Definitions for Get Channel Authentication Capabilities command\r
//\r
-#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38\r
+#define IPMI_APP_GET_CHANNEL_AUTHENTICATION_CAPABILITIES 0x38\r
\r
//\r
// Constants and Structure definitions for "Get Channel Authentication Capabilities" command to follow here\r
//\r
// Definitions for Get Session Challenge command\r
//\r
-#define IPMI_APP_GET_SESSION_CHALLENGE 0x39\r
+#define IPMI_APP_GET_SESSION_CHALLENGE 0x39\r
\r
//\r
// Constants and Structure definitions for "Get Session Challenge" command to follow here\r
//\r
// Definitions for Set Session Privelege Level command\r
//\r
-#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B\r
+#define IPMI_APP_SET_SESSION_PRIVELEGE_LEVEL 0x3B\r
\r
//\r
// Constants and Structure definitions for "Set Session Privelege Level" command to follow here\r
//\r
// Definitions for Close Session command\r
//\r
-#define IPMI_APP_CLOSE_SESSION 0x3C\r
+#define IPMI_APP_CLOSE_SESSION 0x3C\r
\r
//\r
// Constants and Structure definitions for "Close Session" command to follow here\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 6;\r
- UINT8 MemoryType : 2;\r
+ UINT8 Reserved : 6;\r
+ UINT8 MemoryType : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_CHANNEL_ACCESS_TYPE;\r
\r
typedef struct {\r
- IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER ChannelNumber;\r
- IPMI_GET_CHANNEL_ACCESS_TYPE AccessType;\r
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER ChannelNumber;\r
+ IPMI_GET_CHANNEL_ACCESS_TYPE AccessType;\r
} IPMI_GET_CHANNEL_ACCESS_REQUEST;\r
\r
typedef union {\r
struct {\r
- UINT8 AccessMode : 3;\r
- UINT8 UserLevelAuthEnabled : 1;\r
- UINT8 MessageAuthEnable : 1;\r
- UINT8 Alert : 1;\r
- UINT8 Reserved : 2;\r
+ UINT8 AccessMode : 3;\r
+ UINT8 UserLevelAuthEnabled : 1;\r
+ UINT8 MessageAuthEnable : 1;\r
+ UINT8 Alert : 1;\r
+ UINT8 Reserved : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS;\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelPriviledgeLimit : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelPriviledgeLimit : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS ChannelAccess;\r
- IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT PrivilegeLimit;\r
+ UINT8 CompletionCode;\r
+ IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS ChannelAccess;\r
+ IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT PrivilegeLimit;\r
} IPMI_GET_CHANNEL_ACCESS_RESPONSE;\r
\r
//\r
// Definitions for channel media type\r
//\r
// IPMB (I2C)\r
-#define IPMI_CHANNEL_MEDIA_TYPE_IPMB 0x1\r
+#define IPMI_CHANNEL_MEDIA_TYPE_IPMB 0x1\r
// ICMB v1.0\r
-#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0 0x2\r
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0 0x2\r
// ICMB v0.9\r
-#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9 0x3\r
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9 0x3\r
// 802.3 LAN\r
-#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN 0x4\r
+#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN 0x4\r
// Asynch. Serial/Modem (RS-232)\r
-#define IPMI_CHANNEL_MEDIA_TYPE_RS_232 0x5\r
+#define IPMI_CHANNEL_MEDIA_TYPE_RS_232 0x5\r
// Other LAN\r
-#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN 0x6\r
+#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN 0x6\r
// PCI SMBus\r
-#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS 0x7\r
+#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS 0x7\r
// SMBus v1.0/1.1\r
-#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1 0x8\r
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1 0x8\r
// SMBus v2.0\r
-#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2 0x9\r
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2 0x9\r
// USB 1.x\r
-#define IPMI_CHANNEL_MEDIA_TYPE_USB1 0xA\r
+#define IPMI_CHANNEL_MEDIA_TYPE_USB1 0xA\r
// USB 2.x\r
-#define IPMI_CHANNEL_MEDIA_TYPE_USB2 0xB\r
+#define IPMI_CHANNEL_MEDIA_TYPE_USB2 0xB\r
// System Interface (KCS, SMIC, or BT)\r
#define IPMI_CHANNEL_MEDIA_TYPE_SYSTEM_INTERFACE 0xC\r
// OEM\r
-#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START 0x60\r
-#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END 0x7F\r
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START 0x60\r
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END 0x7F\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_INFO_CHANNEL_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelMediumType : 7;\r
- UINT8 Reserved : 1;\r
+ UINT8 ChannelMediumType : 7;\r
+ UINT8 Reserved : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_INFO_MEDIUM_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelProtocolType : 5;\r
- UINT8 Reserved : 3;\r
+ UINT8 ChannelProtocolType : 5;\r
+ UINT8 Reserved : 3;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_INFO_PROTOCOL_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 ActiveSessionCount : 6;\r
- UINT8 SessionSupport : 2;\r
+ UINT8 ActiveSessionCount : 6;\r
+ UINT8 SessionSupport : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_INFO_SESSION_SUPPORT;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber;\r
- IPMI_CHANNEL_INFO_MEDIUM_TYPE MediumType;\r
- IPMI_CHANNEL_INFO_PROTOCOL_TYPE ProtocolType;\r
- IPMI_CHANNEL_INFO_SESSION_SUPPORT SessionSupport;\r
- UINT8 VendorId[3];\r
- UINT16 AuxChannelInfo;\r
+ UINT8 CompletionCode;\r
+ IPMI_CHANNEL_INFO_CHANNEL_NUMBER ChannelNumber;\r
+ IPMI_CHANNEL_INFO_MEDIUM_TYPE MediumType;\r
+ IPMI_CHANNEL_INFO_PROTOCOL_TYPE ProtocolType;\r
+ IPMI_CHANNEL_INFO_SESSION_SUPPORT SessionSupport;\r
+ UINT8 VendorId[3];\r
+ UINT16 AuxChannelInfo;\r
} IPMI_GET_CHANNEL_INFO_RESPONSE;\r
\r
//\r
//\r
// Definitions for Set User Access command\r
//\r
-#define IPMI_APP_SET_USER_ACCESS 0x43\r
+#define IPMI_APP_SET_USER_ACCESS 0x43\r
\r
//\r
// Constants and Structure definitions for "Set User Access" command to follow here\r
//\r
// Definitions for Get User Access command\r
//\r
-#define IPMI_APP_GET_USER_ACCESS 0x44\r
+#define IPMI_APP_GET_USER_ACCESS 0x44\r
\r
//\r
// Constants and Structure definitions for "Get User Access" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_USER_ACCESS_CHANNEL_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 UserId : 6;\r
- UINT8 Reserved : 2;\r
+ UINT8 UserId : 6;\r
+ UINT8 Reserved : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_USER_ID;\r
\r
typedef struct {\r
- IPMI_GET_USER_ACCESS_CHANNEL_NUMBER ChannelNumber;\r
- IPMI_USER_ID UserId;\r
+ IPMI_GET_USER_ACCESS_CHANNEL_NUMBER ChannelNumber;\r
+ IPMI_USER_ID UserId;\r
} IPMI_GET_USER_ACCESS_REQUEST;\r
\r
typedef union {\r
struct {\r
- UINT8 MaxUserId : 6;\r
- UINT8 Reserved : 2;\r
+ UINT8 MaxUserId : 6;\r
+ UINT8 Reserved : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_USER_ACCESS_MAX_USER_ID;\r
\r
typedef union {\r
struct {\r
- UINT8 CurrentUserId : 6;\r
- UINT8 UserIdEnableStatus : 2;\r
+ UINT8 CurrentUserId : 6;\r
+ UINT8 UserIdEnableStatus : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_USER_ACCESS_CURRENT_USER;\r
\r
typedef union {\r
struct {\r
- UINT8 FixedUserId : 6;\r
- UINT8 Reserved : 2;\r
+ UINT8 FixedUserId : 6;\r
+ UINT8 Reserved : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_USER_ACCESS_FIXED_NAME_USER;\r
\r
typedef union {\r
struct {\r
- UINT8 UserPrivilegeLimit : 4;\r
- UINT8 EnableIpmiMessaging : 1;\r
- UINT8 EnableUserLinkAuthetication : 1;\r
- UINT8 UserAccessAvailable : 1;\r
- UINT8 Reserved : 1;\r
+ UINT8 UserPrivilegeLimit : 4;\r
+ UINT8 EnableIpmiMessaging : 1;\r
+ UINT8 EnableUserLinkAuthetication : 1;\r
+ UINT8 UserAccessAvailable : 1;\r
+ UINT8 Reserved : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_USER_ACCESS_CHANNEL_ACCESS;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_GET_USER_ACCESS_MAX_USER_ID MaxUserId;\r
- IPMI_GET_USER_ACCESS_CURRENT_USER CurrentUser;\r
- IPMI_GET_USER_ACCESS_FIXED_NAME_USER FixedNameUser;\r
- IPMI_GET_USER_ACCESS_CHANNEL_ACCESS ChannelAccess;\r
+ UINT8 CompletionCode;\r
+ IPMI_GET_USER_ACCESS_MAX_USER_ID MaxUserId;\r
+ IPMI_GET_USER_ACCESS_CURRENT_USER CurrentUser;\r
+ IPMI_GET_USER_ACCESS_FIXED_NAME_USER FixedNameUser;\r
+ IPMI_GET_USER_ACCESS_CHANNEL_ACCESS ChannelAccess;\r
} IPMI_GET_USER_ACCESS_RESPONSE;\r
\r
//\r
// Definitions for Set User Name command\r
//\r
-#define IPMI_APP_SET_USER_NAME 0x45\r
+#define IPMI_APP_SET_USER_NAME 0x45\r
\r
//\r
// Constants and Structure definitions for "Set User Name" command to follow here\r
//\r
typedef struct {\r
- IPMI_USER_ID UserId;\r
- UINT8 UserName[16];\r
+ IPMI_USER_ID UserId;\r
+ UINT8 UserName[16];\r
} IPMI_SET_USER_NAME_REQUEST;\r
\r
//\r
// Definitions for Get User Name command\r
//\r
-#define IPMI_APP_GET_USER_NAME 0x46\r
+#define IPMI_APP_GET_USER_NAME 0x46\r
\r
//\r
// Constants and Structure definitions for "Get User Name" command to follow here\r
//\r
typedef struct {\r
- IPMI_USER_ID UserId;\r
+ IPMI_USER_ID UserId;\r
} IPMI_GET_USER_NAME_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 UserName[16];\r
+ UINT8 CompletionCode;\r
+ UINT8 UserName[16];\r
} IPMI_GET_USER_NAME_RESPONSE;\r
\r
//\r
// Definitions for Set User Password command\r
//\r
-#define IPMI_APP_SET_USER_PASSWORD 0x47\r
+#define IPMI_APP_SET_USER_PASSWORD 0x47\r
\r
//\r
// Constants and Structure definitions for "Set User Password" command to follow here\r
\r
typedef union {\r
struct {\r
- UINT8 UserId : 6;\r
- UINT8 Reserved : 1;\r
- UINT8 PasswordSize : 1;\r
+ UINT8 UserId : 6;\r
+ UINT8 Reserved : 1;\r
+ UINT8 PasswordSize : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SET_USER_PASSWORD_USER_ID;\r
\r
typedef union {\r
struct {\r
- UINT8 Operation : 2;\r
- UINT8 Reserved : 6;\r
+ UINT8 Operation : 2;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SET_USER_PASSWORD_OPERATION;\r
\r
typedef struct {\r
- IPMI_SET_USER_PASSWORD_USER_ID UserId;\r
- IPMI_SET_USER_PASSWORD_OPERATION Operation;\r
- UINT8 PasswordData[0]; // 16 or 20 bytes, depending on the 'PasswordSize' field\r
+ IPMI_SET_USER_PASSWORD_USER_ID UserId;\r
+ IPMI_SET_USER_PASSWORD_OPERATION Operation;\r
+ UINT8 PasswordData[0]; // 16 or 20 bytes, depending on the 'PasswordSize' field\r
} IPMI_SET_USER_PASSWORD_REQUEST;\r
\r
//\r
//\r
// Definitions for Get Payload activation Status command\r
//\r
-#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a\r
+#define IPMI_APP_GET_PAYLOAD_ACTIVATION_STATUS 0x4a\r
\r
//\r
// Constants and Structure definitions for "Get Payload activation Status" command to follow here\r
//\r
// Definitions for Get Payload Instance Info command\r
//\r
-#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b\r
+#define IPMI_APP_GET_PAYLOAD_INSTANCE_INFO 0x4b\r
\r
//\r
// Constants and Structure definitions for "Get Payload Instance Info" command to follow here\r
//\r
// Definitions for Set User Payload Access command\r
//\r
-#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C\r
+#define IPMI_APP_SET_USER_PAYLOAD_ACCESS 0x4C\r
\r
//\r
// Constants and Structure definitions for "Set User Payload Access" command to follow here\r
//\r
// Definitions for Get User Payload Access command\r
//\r
-#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D\r
+#define IPMI_APP_GET_USER_PAYLOAD_ACCESS 0x4D\r
\r
//\r
// Constants and Structure definitions for "Get User Payload Access" command to follow here\r
//\r
// Definitions for Get Channel Payload Support command\r
//\r
-#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E\r
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_SUPPORT 0x4E\r
\r
//\r
// Constants and Structure definitions for "Get Channel Payload Support" command to follow here\r
//\r
// Definitions for Get Channel Payload Version command\r
//\r
-#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F\r
+#define IPMI_APP_GET_CHANNEL_PAYLOAD_VERSION 0x4F\r
\r
//\r
// Constants and Structure definitions for "Get Channel Payload Version" command to follow here\r
//\r
// Definitions for Master Write-Read command\r
//\r
-#define IPMI_APP_MASTER_WRITE_READ 0x52\r
+#define IPMI_APP_MASTER_WRITE_READ 0x52\r
\r
//\r
// Constants and Structure definitions for "Master Write Read" command to follow here\r
//\r
// Definitions for Get Channel Cipher Suites command\r
//\r
-#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54\r
+#define IPMI_APP_GET_CHANNEL_CIPHER_SUITES 0x54\r
\r
//\r
// Constants and Structure definitions for "Get Channel Cipher Suites" command to follow here\r
//\r
// Definitions for Suspend-Resume Payload Encryption command\r
//\r
-#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55\r
+#define IPMI_APP_SUSPEND_RESUME_PAYLOAD_ENCRYPTION 0x55\r
\r
//\r
// Constants and Structure definitions for "Suspend-Resume Payload Encryption" command to follow here\r
//\r
// Definitions for Set Channel Security Keys command\r
//\r
-#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56\r
+#define IPMI_APP_SET_CHANNEL_SECURITY_KEYS 0x56\r
\r
//\r
// Constants and Structure definitions for "Set Channel Security Keys" command to follow here\r
//\r
// Definitions for Get System Interface Capabilities command\r
//\r
-#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57\r
+#define IPMI_APP_GET_SYSTEM_INTERFACE_CAPABILITIES 0x57\r
\r
//\r
// Constants and Structure definitions for "Get System Interface Capabilities" command to follow here\r
//\r
// Net function definition for Bridge command\r
//\r
-#define IPMI_NETFN_BRIDGE 0x02\r
+#define IPMI_NETFN_BRIDGE 0x02\r
\r
//\r
// Definitions for Get Bridge State command\r
//\r
// Definitions for Get ICMB Address command\r
//\r
-#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02\r
+#define IPMI_BRIDGE_GET_ICMB_ADDRESS 0x02\r
\r
//\r
// Constants and Structure definitions for "Get ICMB Address" command to follow here\r
//\r
// Definitions for Set ICMB Address command\r
//\r
-#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03\r
+#define IPMI_BRIDGE_SET_ICMB_ADDRESS 0x03\r
\r
//\r
// Constants and Structure definitions for "Set ICMB Address" command to follow here\r
//\r
// Definitions for Clear Bridge Statistics command\r
//\r
-#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08\r
+#define IPMI_BRIDGE_CLEAR_STATISTICS 0x08\r
\r
//\r
// Constants and Structure definitions for "Clear Bridge Statistics" command to follow here\r
//\r
// Definitions for Get ICMB Connection ID command\r
//\r
-#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B\r
+#define IPMI_BRIDGE_GET_ICMB_CONNECTION_ID 0x0B\r
\r
//\r
// Constants and Structure definitions for "Get ICMB Connection ID" command to follow here\r
//\r
// Definitions for Set Discovered command\r
//\r
-#define IPMI_BRIDGE_SET_DISCOVERED 0x12\r
+#define IPMI_BRIDGE_SET_DISCOVERED 0x12\r
\r
//\r
// Constants and Structure definitions for "Set Discovered" command to follow here\r
//\r
// Definitions for Get Chassis Device ID command\r
//\r
-#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13\r
+#define IPMI_BRIDGE_GET_CHASSIS_DEVICEID 0x13\r
\r
//\r
// Constants and Structure definitions for "Get Chassis Device ID" command to follow here\r
//\r
// Definitions for Set Chassis Device ID command\r
//\r
-#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14\r
+#define IPMI_BRIDGE_SET_CHASSIS_DEVICEID 0x14\r
\r
//\r
// Constants and Structure definitions for "Set Chassis Device ID" command to follow here\r
// Constants and Structure definitions for "Get Chassis Capabilities" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 CapabilitiesFlags;\r
- UINT8 ChassisFruInfoDeviceAddress;\r
- UINT8 ChassisSDRDeviceAddress;\r
- UINT8 ChassisSELDeviceAddress;\r
- UINT8 ChassisSystemManagementDeviceAddress;\r
- UINT8 ChassisBridgeDeviceAddress;\r
+ UINT8 CompletionCode;\r
+ UINT8 CapabilitiesFlags;\r
+ UINT8 ChassisFruInfoDeviceAddress;\r
+ UINT8 ChassisSDRDeviceAddress;\r
+ UINT8 ChassisSELDeviceAddress;\r
+ UINT8 ChassisSystemManagementDeviceAddress;\r
+ UINT8 ChassisBridgeDeviceAddress;\r
} IPMI_GET_CHASSIS_CAPABILITIES_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Get Chassis Status" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 CurrentPowerState;\r
- UINT8 LastPowerEvent;\r
- UINT8 MiscChassisState;\r
- UINT8 FrontPanelButtonCapabilities;\r
+ UINT8 CompletionCode;\r
+ UINT8 CurrentPowerState;\r
+ UINT8 LastPowerEvent;\r
+ UINT8 MiscChassisState;\r
+ UINT8 FrontPanelButtonCapabilities;\r
} IPMI_GET_CHASSIS_STATUS_RESPONSE;\r
\r
//\r
// Definitions for Chassis Control command\r
//\r
-#define IPMI_CHASSIS_CONTROL 0x02\r
+#define IPMI_CHASSIS_CONTROL 0x02\r
\r
//\r
// Constants and Structure definitions for "Chassis Control" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ChassisControl:4;\r
- UINT8 Reserved:4;\r
+ UINT8 ChassisControl : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL;\r
\r
typedef struct {\r
- IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL ChassisControl;\r
+ IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL ChassisControl;\r
} IPMI_CHASSIS_CONTROL_REQUEST;\r
\r
//\r
// Definitions for Chassis Reset command\r
//\r
-#define IPMI_CHASSIS_RESET 0x03\r
+#define IPMI_CHASSIS_RESET 0x03\r
\r
//\r
// Constants and Structure definitions for "Chassis Reset" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 PowerRestorePolicy : 3;\r
- UINT8 Reserved : 5;\r
+ UINT8 PowerRestorePolicy : 3;\r
+ UINT8 Reserved : 5;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_POWER_RESTORE_POLICY;\r
\r
typedef struct {\r
- IPMI_POWER_RESTORE_POLICY PowerRestorePolicy;\r
+ IPMI_POWER_RESTORE_POLICY PowerRestorePolicy;\r
} IPMI_SET_POWER_RESTORE_POLICY_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 PowerRestorePolicySupport;\r
+ UINT8 CompletionCode;\r
+ UINT8 PowerRestorePolicySupport;\r
} IPMI_SET_POWER_RESTORE_POLICY_RESPONSE;\r
\r
//\r
\r
typedef union {\r
struct {\r
- UINT8 Cause:4;\r
- UINT8 Reserved:4;\r
+ UINT8 Cause : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SYSTEM_RESTART_CAUSE;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_SYSTEM_RESTART_CAUSE RestartCause;\r
- UINT8 ChannelNumber;\r
+ UINT8 CompletionCode;\r
+ IPMI_SYSTEM_RESTART_CAUSE RestartCause;\r
+ UINT8 ChannelNumber;\r
} IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;\r
\r
//\r
// Definitions for Set System BOOT options command\r
//\r
-#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08\r
+#define IPMI_CHASSIS_SET_SYSTEM_BOOT_OPTIONS 0x08\r
\r
//\r
// Constants and Structure definitions for "Set System boot options" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ParameterSelector:7;\r
- UINT8 MarkParameterInvalid:1;\r
+ UINT8 ParameterSelector : 7;\r
+ UINT8 MarkParameterInvalid : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID;\r
\r
typedef struct {\r
- IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;\r
- UINT8 ParameterData[0];\r
+ IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;\r
+ UINT8 ParameterData[0];\r
} IPMI_SET_BOOT_OPTIONS_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode:8;\r
+ UINT8 CompletionCode : 8;\r
} IPMI_SET_BOOT_OPTIONS_RESPONSE;\r
\r
//\r
// Definitions for Get System Boot options command\r
//\r
-#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09\r
+#define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09\r
\r
//\r
// Constants and Structure definitions for "Get System boot options" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ParameterSelector:7;\r
- UINT8 Reserved:1;\r
+ UINT8 ParameterSelector : 7;\r
+ UINT8 Reserved : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR;\r
\r
typedef struct {\r
- IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR ParameterSelector;\r
- UINT8 SetSelector;\r
- UINT8 BlockSelector;\r
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR ParameterSelector;\r
+ UINT8 SetSelector;\r
+ UINT8 BlockSelector;\r
} IPMI_GET_BOOT_OPTIONS_REQUEST;\r
\r
typedef struct {\r
- UINT8 Parameter;\r
- UINT8 Valid;\r
- UINT8 Data1;\r
- UINT8 Data2;\r
- UINT8 Data3;\r
- UINT8 Data4;\r
- UINT8 Data5;\r
+ UINT8 Parameter;\r
+ UINT8 Valid;\r
+ UINT8 Data1;\r
+ UINT8 Data2;\r
+ UINT8 Data3;\r
+ UINT8 Data4;\r
+ UINT8 Data5;\r
} IPMI_GET_THE_SYSTEM_BOOT_OPTIONS;\r
\r
typedef struct {\r
- UINT8 ParameterVersion;\r
- UINT8 ParameterValid;\r
- UINT8 ChannelNumber;\r
- UINT32 SessionId;\r
- UINT32 TimeStamp;\r
- UINT8 Reserved[3];\r
+ UINT8 ParameterVersion;\r
+ UINT8 ParameterValid;\r
+ UINT8 ChannelNumber;\r
+ UINT32 SessionId;\r
+ UINT32 TimeStamp;\r
+ UINT8 Reserved[3];\r
} IPMI_BOOT_INITIATOR;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 SetInProgress : 2;\r
- UINT8 Reserved : 6;\r
+ UINT8 SetInProgress : 2;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;\r
\r
typedef struct {\r
- UINT8 ServicePartitionSelector;\r
+ UINT8 ServicePartitionSelector;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;\r
\r
typedef union {\r
struct {\r
- UINT8 ServicePartitionDiscovered : 1;\r
- UINT8 ServicePartitionScanRequest : 1;\r
- UINT8 Reserved: 6;\r
+ UINT8 ServicePartitionDiscovered : 1;\r
+ UINT8 ServicePartitionScanRequest : 1;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;\r
\r
typedef union {\r
struct {\r
- UINT8 BmcBootFlagValid : 5;\r
- UINT8 Reserved : 3;\r
+ UINT8 BmcBootFlagValid : 5;\r
+ UINT8 Reserved : 3;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;\r
\r
typedef struct {\r
- UINT8 WriteMask;\r
- UINT8 BootInitiatorAcknowledgeData;\r
+ UINT8 WriteMask;\r
+ UINT8 BootInitiatorAcknowledgeData;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;\r
\r
//\r
#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_HARDDRIVE 0xB\r
#define IPMI_BOOT_DEVICE_SELECTOR_FLOPPY 0xF\r
\r
-#define BOOT_OPTION_HANDLED_BY_BIOS 0x01\r
+#define BOOT_OPTION_HANDLED_BY_BIOS 0x01\r
\r
//\r
// Constant definitions for the 'BIOS Mux Control Override' field of Boot Option Parameters #5\r
//\r
-#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING 0x00\r
-#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC 0x01\r
-#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM 0x02\r
+#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING 0x00\r
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC 0x01\r
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM 0x02\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved:5;\r
- UINT8 BiosBootType:1;\r
- UINT8 PersistentOptions:1;\r
- UINT8 BootFlagValid:1;\r
+ UINT8 Reserved : 5;\r
+ UINT8 BiosBootType : 1;\r
+ UINT8 PersistentOptions : 1;\r
+ UINT8 BootFlagValid : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1;\r
\r
typedef union {\r
struct {\r
- UINT8 LockReset:1;\r
- UINT8 ScreenBlank:1;\r
- UINT8 BootDeviceSelector:4;\r
- UINT8 LockKeyboard:1;\r
- UINT8 CmosClear:1;\r
+ UINT8 LockReset : 1;\r
+ UINT8 ScreenBlank : 1;\r
+ UINT8 BootDeviceSelector : 4;\r
+ UINT8 LockKeyboard : 1;\r
+ UINT8 CmosClear : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2;\r
\r
typedef union {\r
struct {\r
- UINT8 ConsoleRedirection:2;\r
- UINT8 LockSleep:1;\r
- UINT8 UserPasswordBypass:1;\r
- UINT8 ForceProgressEventTrap:1;\r
- UINT8 BiosVerbosity:2;\r
- UINT8 LockPower:1;\r
+ UINT8 ConsoleRedirection : 2;\r
+ UINT8 LockSleep : 1;\r
+ UINT8 UserPasswordBypass : 1;\r
+ UINT8 ForceProgressEventTrap : 1;\r
+ UINT8 BiosVerbosity : 2;\r
+ UINT8 LockPower : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3;\r
\r
typedef union {\r
struct {\r
- UINT8 BiosMuxControlOverride:3;\r
- UINT8 BiosSharedModeOverride:1;\r
- UINT8 Reserved:4;\r
+ UINT8 BiosMuxControlOverride : 3;\r
+ UINT8 BiosSharedModeOverride : 1;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4;\r
\r
typedef union {\r
struct {\r
- UINT8 DeviceInstanceSelector:5;\r
- UINT8 Reserved:3;\r
+ UINT8 DeviceInstanceSelector : 5;\r
+ UINT8 Reserved : 3;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5;\r
\r
typedef struct {\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1 Data1;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2 Data2;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3 Data3;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4 Data4;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5 Data5;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1 Data1;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2 Data2;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3 Data3;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4 Data4;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5 Data5;\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNumber:4;\r
- UINT8 Reserved:4;\r
+ UINT8 ChannelNumber : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_BOOT_OPTIONS_CHANNEL_NUMBER;\r
\r
typedef struct {\r
- IPMI_BOOT_OPTIONS_CHANNEL_NUMBER ChannelNumber;\r
- UINT8 SessionId[4];\r
- UINT8 BootInfoTimeStamp[4];\r
+ IPMI_BOOT_OPTIONS_CHANNEL_NUMBER ChannelNumber;\r
+ UINT8 SessionId[4];\r
+ UINT8 BootInfoTimeStamp[4];\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;\r
\r
typedef struct {\r
- UINT8 SetSelector;\r
- UINT8 BlockData[16];\r
+ UINT8 SetSelector;\r
+ UINT8 BlockData[16];\r
} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7;\r
\r
typedef union {\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0 Parm0;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1 Parm1;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2 Parm2;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3 Parm3;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4 Parm4;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 Parm5;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6 Parm6;\r
- IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0 Parm0;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1 Parm1;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2 Parm2;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3 Parm3;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4 Parm4;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5 Parm5;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6 Parm6;\r
+ IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7 Parm7;\r
} IPMI_BOOT_OPTIONS_PARAMETERS;\r
\r
typedef union {\r
struct {\r
- UINT8 ParameterVersion:4;\r
- UINT8 Reserved:4;\r
+ UINT8 ParameterVersion : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION;\r
\r
typedef union {\r
struct {\r
- UINT8 ParameterSelector:7;\r
- UINT8 ParameterValid:1;\r
+ UINT8 ParameterSelector : 7;\r
+ UINT8 ParameterValid : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION ParameterVersion;\r
- IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;\r
- UINT8 ParameterData[0];\r
+ UINT8 CompletionCode;\r
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION ParameterVersion;\r
+ IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID ParameterValid;\r
+ UINT8 ParameterData[0];\r
} IPMI_GET_BOOT_OPTIONS_RESPONSE;\r
\r
//\r
// Definitions for Set front panel button enables command\r
//\r
-#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A\r
+#define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A\r
\r
//\r
// Constants and Structure definitions for "Set front panel button enables" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 DisablePoweroffButton:1;\r
- UINT8 DisableResetButton:1;\r
- UINT8 DisableDiagnosticInterruptButton:1;\r
- UINT8 DisableStandbyButton:1;\r
- UINT8 Reserved:4;\r
+ UINT8 DisablePoweroffButton : 1;\r
+ UINT8 DisableResetButton : 1;\r
+ UINT8 DisableDiagnosticInterruptButton : 1;\r
+ UINT8 DisableStandbyButton : 1;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_FRONT_PANEL_BUTTON_ENABLES;\r
\r
typedef struct {\r
- IPMI_FRONT_PANEL_BUTTON_ENABLES FrontPanelButtonEnables;\r
+ IPMI_FRONT_PANEL_BUTTON_ENABLES FrontPanelButtonEnables;\r
} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;\r
\r
//\r
// Definitions for Set Power Cycle Interval command\r
//\r
-#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B\r
+#define IPMI_CHASSIS_SET_POWER_CYCLE_INTERVALS 0x0B\r
\r
//\r
// Constants and Structure definitions for "Set Power Cycle Interval" command to follow here\r
//\r
// Definitions for Get POH Counter command\r
//\r
-#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F\r
+#define IPMI_CHASSIS_GET_POH_COUNTER 0x0F\r
\r
//\r
// Constants and Structure definitions for "Get POH Counter" command to follow here\r
//\r
// Net function definition for Firmware command\r
//\r
-#define IPMI_NETFN_FIRMWARE 0x08\r
+#define IPMI_NETFN_FIRMWARE 0x08\r
\r
//\r
// All Firmware commands and their structure definitions to follow here\r
// Constants and Structure definitions for "Get Device ID" command to follow here\r
//\r
typedef struct {\r
- UINT8 CurrentExecutionContext;\r
- UINT8 PartitionPointer;\r
+ UINT8 CurrentExecutionContext;\r
+ UINT8 PartitionPointer;\r
} IPMI_MSG_GET_BMC_EXEC_RSP;\r
\r
//\r
//\r
// Net function definition for Sensor command\r
//\r
-#define IPMI_NETFN_SENSOR_EVENT 0x04\r
+#define IPMI_NETFN_SENSOR_EVENT 0x04\r
\r
//\r
// All Sensor commands and their structure definitions to follow here\r
//\r
// Definitions for Send Platform Event Message command\r
//\r
-#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE 0x02\r
+#define IPMI_SENSOR_PLATFORM_EVENT_MESSAGE 0x02\r
\r
typedef struct {\r
- UINT8 GeneratorId;\r
- UINT8 EvMRevision;\r
- UINT8 SensorType;\r
- UINT8 SensorNumber;\r
- UINT8 EventDirType;\r
- UINT8 OEMEvData1;\r
- UINT8 OEMEvData2;\r
- UINT8 OEMEvData3;\r
+ UINT8 GeneratorId;\r
+ UINT8 EvMRevision;\r
+ UINT8 SensorType;\r
+ UINT8 SensorNumber;\r
+ UINT8 EventDirType;\r
+ UINT8 OEMEvData1;\r
+ UINT8 OEMEvData2;\r
+ UINT8 OEMEvData3;\r
} IPMI_PLATFORM_EVENT_MESSAGE_DATA_REQUEST;\r
\r
#pragma pack()\r
// Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here\r
//\r
typedef struct {\r
- UINT8 DeviceId;\r
+ UINT8 DeviceId;\r
} IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT16 InventoryAreaSize;\r
- UINT8 AccessType;\r
+ UINT8 CompletionCode;\r
+ UINT16 InventoryAreaSize;\r
+ UINT8 AccessType;\r
} IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE;\r
\r
//\r
// Definitions for Read Fru Data command\r
//\r
-#define IPMI_STORAGE_READ_FRU_DATA 0x11\r
+#define IPMI_STORAGE_READ_FRU_DATA 0x11\r
\r
//\r
// Constants and Structure definitions for "Read Fru Data" command to follow here\r
//\r
typedef struct {\r
- UINT8 FruDeviceId;\r
- UINT16 FruOffset;\r
+ UINT8 FruDeviceId;\r
+ UINT16 FruOffset;\r
} IPMI_FRU_COMMON_DATA;\r
\r
typedef struct {\r
- IPMI_FRU_COMMON_DATA Data;\r
- UINT8 Count;\r
+ IPMI_FRU_COMMON_DATA Data;\r
+ UINT8 Count;\r
} IPMI_FRU_READ_COMMAND;\r
\r
typedef struct {\r
- UINT8 DeviceId;\r
- UINT16 InventoryOffset;\r
- UINT8 CountToRead;\r
+ UINT8 DeviceId;\r
+ UINT16 InventoryOffset;\r
+ UINT8 CountToRead;\r
} IPMI_READ_FRU_DATA_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 CountReturned;\r
- UINT8 Data[0];\r
+ UINT8 CompletionCode;\r
+ UINT8 CountReturned;\r
+ UINT8 Data[0];\r
} IPMI_READ_FRU_DATA_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Write Fru Data" command to follow here\r
//\r
typedef struct {\r
- IPMI_FRU_COMMON_DATA Data;\r
- UINT8 FruData[16];\r
+ IPMI_FRU_COMMON_DATA Data;\r
+ UINT8 FruData[16];\r
} IPMI_FRU_WRITE_COMMAND;\r
\r
typedef struct {\r
- UINT8 DeviceId;\r
- UINT16 InventoryOffset;\r
- UINT8 Data[0];\r
+ UINT8 DeviceId;\r
+ UINT16 InventoryOffset;\r
+ UINT8 Data[0];\r
} IPMI_WRITE_FRU_DATA_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 CountWritten;\r
+ UINT8 CompletionCode;\r
+ UINT8 CountWritten;\r
} IPMI_WRITE_FRU_DATA_RESPONSE;\r
\r
//\r
//\r
// Definitions for Get SDR Repository Info command\r
//\r
-#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20\r
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_INFO 0x20\r
\r
//\r
// Constants and Structure definitions for "Get SDR Repository Info" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 SdrRepAllocInfoCmd : 1;\r
- UINT8 SdrRepReserveCmd : 1;\r
- UINT8 PartialAddSdrCmd : 1;\r
- UINT8 DeleteSdrRepCmd : 1;\r
- UINT8 Reserved : 1;\r
- UINT8 SdrRepUpdateOp : 2;\r
- UINT8 Overflow : 1;\r
+ UINT8 SdrRepAllocInfoCmd : 1;\r
+ UINT8 SdrRepReserveCmd : 1;\r
+ UINT8 PartialAddSdrCmd : 1;\r
+ UINT8 DeleteSdrRepCmd : 1;\r
+ UINT8 Reserved : 1;\r
+ UINT8 SdrRepUpdateOp : 2;\r
+ UINT8 Overflow : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_OPERATION_SUPPORT;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 Version;\r
- UINT16 RecordCount;\r
- UINT16 FreeSpace;\r
- UINT32 RecentAdditionTimeStamp;\r
- UINT32 RecentEraseTimeStamp;\r
- IPMI_SDR_OPERATION_SUPPORT OperationSupport;\r
+ UINT8 CompletionCode;\r
+ UINT8 Version;\r
+ UINT16 RecordCount;\r
+ UINT16 FreeSpace;\r
+ UINT32 RecentAdditionTimeStamp;\r
+ UINT32 RecentEraseTimeStamp;\r
+ IPMI_SDR_OPERATION_SUPPORT OperationSupport;\r
} IPMI_GET_SDR_REPOSITORY_INFO_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Reserve SDR Repository" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ReservationId[2]; // Reservation ID. LS byte first.\r
+ UINT8 CompletionCode;\r
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.\r
} IPMI_RESERVE_SDR_REPOSITORY_RESPONSE;\r
\r
//\r
// Definitions for Get SDR command\r
//\r
-#define IPMI_STORAGE_GET_SDR 0x23\r
+#define IPMI_STORAGE_GET_SDR 0x23\r
\r
//\r
// Constants and Structure definitions for "Get SDR" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 EventScanningEnabled : 1;\r
- UINT8 EventScanningDisabled : 1;\r
- UINT8 InitSensorType : 1;\r
- UINT8 InitHysteresis : 1;\r
- UINT8 InitThresholds : 1;\r
- UINT8 InitEvent : 1;\r
- UINT8 InitScanning : 1;\r
- UINT8 SettableSensor : 1;\r
+ UINT8 EventScanningEnabled : 1;\r
+ UINT8 EventScanningDisabled : 1;\r
+ UINT8 InitSensorType : 1;\r
+ UINT8 InitHysteresis : 1;\r
+ UINT8 InitThresholds : 1;\r
+ UINT8 InitEvent : 1;\r
+ UINT8 InitScanning : 1;\r
+ UINT8 SettableSensor : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_SENSOR_INIT;\r
\r
typedef union {\r
struct {\r
- UINT8 EventMessageControl : 2;\r
- UINT8 ThresholdAccessSupport : 2;\r
- UINT8 HysteresisSupport : 2;\r
- UINT8 ReArmSupport : 1;\r
- UINT8 IgnoreSensor : 1;\r
+ UINT8 EventMessageControl : 2;\r
+ UINT8 ThresholdAccessSupport : 2;\r
+ UINT8 HysteresisSupport : 2;\r
+ UINT8 ReArmSupport : 1;\r
+ UINT8 IgnoreSensor : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_SENSOR_CAP;\r
\r
typedef union {\r
struct {\r
- UINT8 Linearization : 7;\r
- UINT8 Reserved : 1;\r
+ UINT8 Linearization : 7;\r
+ UINT8 Reserved : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_LINEARIZATION;\r
\r
typedef union {\r
struct {\r
- UINT8 Toleremce : 6;\r
- UINT8 MHi : 2;\r
+ UINT8 Toleremce : 6;\r
+ UINT8 MHi : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_M_TOLERANCE;\r
\r
typedef union {\r
struct {\r
- UINT8 AccuracyLow : 6;\r
- UINT8 BHi : 2;\r
+ UINT8 AccuracyLow : 6;\r
+ UINT8 BHi : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_B_ACCURACY;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 2;\r
- UINT8 AccuracyExp : 2;\r
- UINT8 AccuracyHi : 4;\r
+ UINT8 Reserved : 2;\r
+ UINT8 AccuracyExp : 2;\r
+ UINT8 AccuracyHi : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR;\r
\r
typedef union {\r
struct {\r
- UINT8 BExp : 4;\r
- UINT8 RExp : 4;\r
+ UINT8 BExp : 4;\r
+ UINT8 RExp : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_R_EXP_B_EXP;\r
\r
typedef union {\r
struct {\r
- UINT8 NominalReadingSpscified : 1;\r
- UINT8 NominalMaxSpscified : 1;\r
- UINT8 NominalMinSpscified : 1;\r
- UINT8 Reserved : 5;\r
+ UINT8 NominalReadingSpscified : 1;\r
+ UINT8 NominalMaxSpscified : 1;\r
+ UINT8 NominalMinSpscified : 1;\r
+ UINT8 Reserved : 5;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_ANALOG_FLAGS;\r
\r
typedef struct {\r
- UINT16 RecordId; // 1\r
- UINT8 Version; // 3\r
- UINT8 RecordType; // 4\r
- UINT8 RecordLength; // 5\r
- UINT8 OwnerId; // 6\r
- UINT8 OwnerLun; // 7\r
- UINT8 SensorNumber; // 8\r
- UINT8 EntityId; // 9\r
- UINT8 EntityInstance; // 10\r
- IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11\r
- IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12\r
- UINT8 SensorType; // 13\r
- UINT8 EventType; // 14\r
- UINT8 Reserved1[7]; // 15\r
- UINT8 UnitType; // 22\r
- UINT8 Reserved2; // 23\r
- IPMI_SDR_RECORD_LINEARIZATION Linearization; // 24\r
- UINT8 MLo; // 25\r
- IPMI_SDR_RECORD_M_TOLERANCE MHiTolerance; // 26\r
- UINT8 BLo; // 27\r
- IPMI_SDR_RECORD_B_ACCURACY BHiAccuracyLo; // 28\r
- IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR AccuracySensorDirection; // 29\r
- IPMI_SDR_RECORD_R_EXP_B_EXP RExpBExp; // 30\r
- IPMI_SDR_RECORD_ANALOG_FLAGS AnalogFlags; // 31\r
- UINT8 NominalReading; // 32\r
- UINT8 Reserved3[4]; // 33\r
- UINT8 UpperNonRecoverThreshold; // 37\r
- UINT8 UpperCriticalThreshold; // 38\r
- UINT8 UpperNonCriticalThreshold; // 39\r
- UINT8 LowerNonRecoverThreshold; // 40\r
- UINT8 LowerCriticalThreshold; // 41\r
- UINT8 LowerNonCriticalThreshold; // 42\r
- UINT8 Reserved4[5]; // 43\r
- UINT8 IdStringLength; // 48\r
- UINT8 AsciiIdString[16]; // 49 - 64\r
+ UINT16 RecordId; // 1\r
+ UINT8 Version; // 3\r
+ UINT8 RecordType; // 4\r
+ UINT8 RecordLength; // 5\r
+ UINT8 OwnerId; // 6\r
+ UINT8 OwnerLun; // 7\r
+ UINT8 SensorNumber; // 8\r
+ UINT8 EntityId; // 9\r
+ UINT8 EntityInstance; // 10\r
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11\r
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12\r
+ UINT8 SensorType; // 13\r
+ UINT8 EventType; // 14\r
+ UINT8 Reserved1[7]; // 15\r
+ UINT8 UnitType; // 22\r
+ UINT8 Reserved2; // 23\r
+ IPMI_SDR_RECORD_LINEARIZATION Linearization; // 24\r
+ UINT8 MLo; // 25\r
+ IPMI_SDR_RECORD_M_TOLERANCE MHiTolerance; // 26\r
+ UINT8 BLo; // 27\r
+ IPMI_SDR_RECORD_B_ACCURACY BHiAccuracyLo; // 28\r
+ IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR AccuracySensorDirection; // 29\r
+ IPMI_SDR_RECORD_R_EXP_B_EXP RExpBExp; // 30\r
+ IPMI_SDR_RECORD_ANALOG_FLAGS AnalogFlags; // 31\r
+ UINT8 NominalReading; // 32\r
+ UINT8 Reserved3[4]; // 33\r
+ UINT8 UpperNonRecoverThreshold; // 37\r
+ UINT8 UpperCriticalThreshold; // 38\r
+ UINT8 UpperNonCriticalThreshold; // 39\r
+ UINT8 LowerNonRecoverThreshold; // 40\r
+ UINT8 LowerCriticalThreshold; // 41\r
+ UINT8 LowerNonCriticalThreshold; // 42\r
+ UINT8 Reserved4[5]; // 43\r
+ UINT8 IdStringLength; // 48\r
+ UINT8 AsciiIdString[16]; // 49 - 64\r
} IPMI_SDR_RECORD_STRUCT_1;\r
\r
typedef struct {\r
- UINT16 RecordId; // 1\r
- UINT8 Version; // 3\r
- UINT8 RecordType; // 4\r
- UINT8 RecordLength; // 5\r
- UINT8 OwnerId; // 6\r
- UINT8 OwnerLun; // 7\r
- UINT8 SensorNumber; // 8\r
- UINT8 EntityId; // 9\r
- UINT8 EntityInstance; // 10\r
- IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11\r
- IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12\r
- UINT8 SensorType; // 13\r
- UINT8 EventType; // 14\r
- UINT8 Reserved1[7]; // 15\r
- UINT8 UnitType; // 22\r
- UINT8 Reserved2[9]; // 23\r
- UINT8 IdStringLength; // 32\r
- UINT8 AsciiIdString[16]; // 33 - 48\r
+ UINT16 RecordId; // 1\r
+ UINT8 Version; // 3\r
+ UINT8 RecordType; // 4\r
+ UINT8 RecordLength; // 5\r
+ UINT8 OwnerId; // 6\r
+ UINT8 OwnerLun; // 7\r
+ UINT8 SensorNumber; // 8\r
+ UINT8 EntityId; // 9\r
+ UINT8 EntityInstance; // 10\r
+ IPMI_SDR_RECORD_SENSOR_INIT SensorInitialization; // 11\r
+ IPMI_SDR_RECORD_SENSOR_CAP SensorCapabilities; // 12\r
+ UINT8 SensorType; // 13\r
+ UINT8 EventType; // 14\r
+ UINT8 Reserved1[7]; // 15\r
+ UINT8 UnitType; // 22\r
+ UINT8 Reserved2[9]; // 23\r
+ UINT8 IdStringLength; // 32\r
+ UINT8 AsciiIdString[16]; // 33 - 48\r
} IPMI_SDR_RECORD_STRUCT_2;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved1 : 1;\r
- UINT8 ControllerSlaveAddress : 7;\r
- UINT8 FruDeviceId;\r
- UINT8 BusId : 3;\r
- UINT8 Lun : 2;\r
- UINT8 Reserved2 : 2;\r
- UINT8 LogicalFruDevice : 1;\r
- UINT8 Reserved3 : 4;\r
- UINT8 ChannelNumber : 4;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 ControllerSlaveAddress : 7;\r
+ UINT8 FruDeviceId;\r
+ UINT8 BusId : 3;\r
+ UINT8 Lun : 2;\r
+ UINT8 Reserved2 : 2;\r
+ UINT8 LogicalFruDevice : 1;\r
+ UINT8 Reserved3 : 4;\r
+ UINT8 ChannelNumber : 4;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} IPMI_FRU_DATA_INFO;\r
\r
typedef union {\r
struct {\r
- UINT8 Length : 4;\r
- UINT8 Reserved : 1;\r
- UINT8 StringType : 3;\r
+ UINT8 Length : 4;\r
+ UINT8 Reserved : 1;\r
+ UINT8 StringType : 3;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH;\r
\r
typedef struct {\r
- UINT16 RecordId; // 1\r
- UINT8 Version; // 3\r
- UINT8 RecordType; // 4\r
- UINT8 RecordLength; // 5\r
- IPMI_FRU_DATA_INFO FruDeviceData; // 6\r
- UINT8 Reserved; // 10\r
- UINT8 DeviceType; // 11\r
- UINT8 DeviceTypeModifier; // 12\r
- UINT8 FruEntityId; // 13\r
- UINT8 FruEntityInstance; // 14\r
- UINT8 OemReserved; // 15\r
- IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH StringTypeLength; // 16\r
- UINT8 String[16]; // 17\r
+ UINT16 RecordId; // 1\r
+ UINT8 Version; // 3\r
+ UINT8 RecordType; // 4\r
+ UINT8 RecordLength; // 5\r
+ IPMI_FRU_DATA_INFO FruDeviceData; // 6\r
+ UINT8 Reserved; // 10\r
+ UINT8 DeviceType; // 11\r
+ UINT8 DeviceTypeModifier; // 12\r
+ UINT8 FruEntityId; // 13\r
+ UINT8 FruEntityInstance; // 14\r
+ UINT8 OemReserved; // 15\r
+ IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH StringTypeLength; // 16\r
+ UINT8 String[16]; // 17\r
} IPMI_SDR_RECORD_STRUCT_11;\r
\r
typedef struct {\r
- UINT16 RecordId; //1\r
- UINT8 Version; //3\r
- UINT8 RecordType; //4\r
- UINT8 RecordLength; //5\r
- UINT8 ManufacturerId[3]; //6\r
- UINT8 StringChars[20];\r
+ UINT16 RecordId; // 1\r
+ UINT8 Version; // 3\r
+ UINT8 RecordType; // 4\r
+ UINT8 RecordLength; // 5\r
+ UINT8 ManufacturerId[3]; // 6\r
+ UINT8 StringChars[20];\r
} IPMI_SDR_RECORD_STRUCT_C0;\r
\r
typedef struct {\r
- UINT16 RecordId; //1\r
- UINT8 Version; //3\r
- UINT8 RecordType; //4\r
- UINT8 RecordLength; //5\r
+ UINT16 RecordId; // 1\r
+ UINT8 Version; // 3\r
+ UINT8 RecordType; // 4\r
+ UINT8 RecordLength; // 5\r
} IPMI_SDR_RECORD_STRUCT_HEADER;\r
\r
typedef union {\r
- IPMI_SDR_RECORD_STRUCT_1 SensorType1;\r
- IPMI_SDR_RECORD_STRUCT_2 SensorType2;\r
- IPMI_SDR_RECORD_STRUCT_11 SensorType11;\r
- IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0;\r
- IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader;\r
+ IPMI_SDR_RECORD_STRUCT_1 SensorType1;\r
+ IPMI_SDR_RECORD_STRUCT_2 SensorType2;\r
+ IPMI_SDR_RECORD_STRUCT_11 SensorType11;\r
+ IPMI_SDR_RECORD_STRUCT_C0 SensorTypeC0;\r
+ IPMI_SDR_RECORD_STRUCT_HEADER SensorHeader;\r
} IPMI_SENSOR_RECORD_STRUCT;\r
\r
typedef struct {\r
- UINT16 ReservationId;\r
- UINT16 RecordId;\r
- UINT8 RecordOffset;\r
- UINT8 BytesToRead;\r
+ UINT16 ReservationId;\r
+ UINT16 RecordId;\r
+ UINT8 RecordOffset;\r
+ UINT8 BytesToRead;\r
} IPMI_GET_SDR_REQUEST;\r
\r
typedef struct {\r
//\r
// Definitions for Add SDR command\r
//\r
-#define IPMI_STORAGE_ADD_SDR 0x24\r
+#define IPMI_STORAGE_ADD_SDR 0x24\r
\r
//\r
// Constants and Structure definitions for "Add SDR" command to follow here\r
//\r
// Definitions for Partial Add SDR command\r
//\r
-#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25\r
+#define IPMI_STORAGE_PARTIAL_ADD_SDR 0x25\r
\r
//\r
// Constants and Structure definitions for "Partial Add SDR" command to follow here\r
//\r
// Definitions for Clear SDR Repository command\r
//\r
-#define IPMI_STORAGE_CLEAR_SDR 0x27\r
+#define IPMI_STORAGE_CLEAR_SDR 0x27\r
\r
//\r
// Constants and Structure definitions for "Clear SDR Repository" command to follow here\r
//\r
// Definitions for Get SDR Repository Time command\r
//\r
-#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28\r
+#define IPMI_STORAGE_GET_SDR_REPOSITORY_TIME 0x28\r
\r
//\r
// Constants and Structure definitions for "Get SDR Repository Time" command to follow here\r
//\r
// Definitions for Set SDR Repository Time command\r
//\r
-#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29\r
+#define IPMI_STORAGE_SET_SDR_REPOSITORY_TIME 0x29\r
\r
//\r
// Constants and Structure definitions for "Set SDR Repository Time" command to follow here\r
//\r
// Definitions for Enter SDR Repository Update Mode command\r
//\r
-#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A\r
+#define IPMI_STORAGE_ENTER_SDR_UPDATE_MODE 0x2A\r
\r
//\r
// Constants and Structure definitions for "Enter SDR Repository Update Mode" command to follow here\r
//\r
// Constants and Structure definitions for "Get SEL Info" command to follow here\r
//\r
-#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD BIT0\r
-#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD BIT1\r
-#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD BIT2\r
-#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD BIT3\r
-#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG BIT7\r
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD BIT0\r
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD BIT1\r
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD BIT2\r
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD BIT3\r
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG BIT7\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 Version; // Version of SEL\r
- UINT16 NoOfEntries; // No of Entries in the SEL\r
- UINT16 FreeSpace; // Free space in Bytes\r
- UINT32 RecentAddTimeStamp; // Most Recent Addition of Time Stamp\r
- UINT32 RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp\r
- UINT8 OperationSupport; // Operation Support\r
+ UINT8 CompletionCode;\r
+ UINT8 Version; // Version of SEL\r
+ UINT16 NoOfEntries; // No of Entries in the SEL\r
+ UINT16 FreeSpace; // Free space in Bytes\r
+ UINT32 RecentAddTimeStamp; // Most Recent Addition of Time Stamp\r
+ UINT32 RecentEraseTimeStamp; // Most Recent Erasure of Time Stamp\r
+ UINT8 OperationSupport; // Operation Support\r
} IPMI_GET_SEL_INFO_RESPONSE;\r
\r
//\r
// Definitions for Get SEL Allocation Info command\r
//\r
-#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41\r
+#define IPMI_STORAGE_GET_SEL_ALLOCATION_INFO 0x41\r
\r
//\r
// Constants and Structure definitions for "Get SEL Allocation Info" command to follow here\r
//\r
// Definitions for Reserve SEL command\r
//\r
-#define IPMI_STORAGE_RESERVE_SEL 0x42\r
+#define IPMI_STORAGE_RESERVE_SEL 0x42\r
\r
//\r
// Constants and Structure definitions for "Reserve SEL" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ReservationId[2]; // Reservation ID. LS byte first.\r
+ UINT8 CompletionCode;\r
+ UINT8 ReservationId[2]; // Reservation ID. LS byte first.\r
} IPMI_RESERVE_SEL_RESPONSE;\r
\r
//\r
// Definitions for Get SEL Entry command\r
//\r
-#define IPMI_STORAGE_GET_SEL_ENTRY 0x43\r
+#define IPMI_STORAGE_GET_SEL_ENTRY 0x43\r
\r
//\r
// Constants and Structure definitions for "Get SEL Entry" command to follow here\r
// Below is Definitions for SEL Record Formats (Chapter 32)\r
//\r
typedef struct {\r
- UINT16 RecordId;\r
- UINT8 RecordType;\r
- UINT32 TimeStamp;\r
- UINT16 GeneratorId;\r
- UINT8 EvMRevision;\r
- UINT8 SensorType;\r
- UINT8 SensorNumber;\r
- UINT8 EventDirType;\r
- UINT8 OEMEvData1;\r
- UINT8 OEMEvData2;\r
- UINT8 OEMEvData3;\r
+ UINT16 RecordId;\r
+ UINT8 RecordType;\r
+ UINT32 TimeStamp;\r
+ UINT16 GeneratorId;\r
+ UINT8 EvMRevision;\r
+ UINT8 SensorType;\r
+ UINT8 SensorNumber;\r
+ UINT8 EventDirType;\r
+ UINT8 OEMEvData1;\r
+ UINT8 OEMEvData2;\r
+ UINT8 OEMEvData3;\r
} IPMI_SEL_EVENT_RECORD_DATA;\r
\r
typedef struct {\r
- UINT16 RecordId;\r
- UINT8 RecordType; // C0h-DFh = OEM system event record\r
- UINT32 TimeStamp;\r
- UINT8 ManufacturerId[3];\r
- UINT8 OEMDefined[6];\r
+ UINT16 RecordId;\r
+ UINT8 RecordType; // C0h-DFh = OEM system event record\r
+ UINT32 TimeStamp;\r
+ UINT8 ManufacturerId[3];\r
+ UINT8 OEMDefined[6];\r
} IPMI_TIMESTAMPED_OEM_SEL_RECORD_DATA;\r
\r
typedef struct {\r
- UINT16 RecordId;\r
- UINT8 RecordType; // E0h-FFh = OEM system event record\r
- UINT8 OEMDefined[13];\r
+ UINT16 RecordId;\r
+ UINT8 RecordType; // E0h-FFh = OEM system event record\r
+ UINT8 OEMDefined[13];\r
} IPMI_NON_TIMESTAMPED_OEM_SEL_RECORD_DATA;\r
\r
typedef struct {\r
- UINT8 ReserveId[2]; // Reservation ID, LS Byte First\r
- UINT8 SelRecID[2]; // Sel Record ID, LS Byte First\r
- UINT8 Offset; // Offset Into Record\r
- UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record\r
+ UINT8 ReserveId[2]; // Reservation ID, LS Byte First\r
+ UINT8 SelRecID[2]; // Sel Record ID, LS Byte First\r
+ UINT8 Offset; // Offset Into Record\r
+ UINT8 BytesToRead; // Bytes to be Read, 0xFF for entire record\r
} IPMI_GET_SEL_ENTRY_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT16 NextSelRecordId; // Next SEL Record ID, LS Byte first\r
- IPMI_SEL_EVENT_RECORD_DATA RecordData;\r
+ UINT8 CompletionCode;\r
+ UINT16 NextSelRecordId; // Next SEL Record ID, LS Byte first\r
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;\r
} IPMI_GET_SEL_ENTRY_RESPONSE;\r
\r
//\r
// Definitions for Add SEL Entry command\r
//\r
-#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44\r
+#define IPMI_STORAGE_ADD_SEL_ENTRY 0x44\r
\r
//\r
// Constants and Structure definitions for "Add SEL Entry" command to follow here\r
//\r
typedef struct {\r
- IPMI_SEL_EVENT_RECORD_DATA RecordData;\r
+ IPMI_SEL_EVENT_RECORD_DATA RecordData;\r
} IPMI_ADD_SEL_ENTRY_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT16 RecordId; // Record ID for added record, LS Byte first\r
+ UINT8 CompletionCode;\r
+ UINT16 RecordId; // Record ID for added record, LS Byte first\r
} IPMI_ADD_SEL_ENTRY_RESPONSE;\r
\r
//\r
// Definitions for Partial Add SEL Entry command\r
//\r
-#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45\r
+#define IPMI_STORAGE_PARTIAL_ADD_SEL_ENTRY 0x45\r
\r
//\r
// Constants and Structure definitions for "Partial Add SEL Entry" command to follow here\r
//\r
typedef struct {\r
- UINT16 ReservationId;\r
- UINT16 RecordId;\r
- UINT8 OffsetIntoRecord;\r
- UINT8 InProgress;\r
- UINT8 RecordData[0];\r
+ UINT16 ReservationId;\r
+ UINT16 RecordId;\r
+ UINT8 OffsetIntoRecord;\r
+ UINT8 InProgress;\r
+ UINT8 RecordData[0];\r
} IPMI_PARTIAL_ADD_SEL_ENTRY_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT16 RecordId;\r
+ UINT8 CompletionCode;\r
+ UINT16 RecordId;\r
} IPMI_PARTIAL_ADD_SEL_ENTRY_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Delete SEL Entry" command to follow here\r
//\r
typedef struct {\r
- UINT8 ReserveId[2]; // Reservation ID, LS byte first\r
- UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First\r
+ UINT8 ReserveId[2]; // Reservation ID, LS byte first\r
+ UINT8 RecordToDelete[2]; // Record to Delete, LS Byte First\r
} IPMI_DELETE_SEL_ENTRY_REQUEST;\r
\r
-#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED 0x80\r
-#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS 0x81\r
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED 0x80\r
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS 0x81\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT16 RecordId; // Record ID added. LS byte first\r
+ UINT8 CompletionCode;\r
+ UINT16 RecordId; // Record ID added. LS byte first\r
} IPMI_DELETE_SEL_ENTRY_RESPONSE;\r
\r
//\r
// Definitions for Clear SEL command\r
//\r
-#define IPMI_STORAGE_CLEAR_SEL 0x47\r
+#define IPMI_STORAGE_CLEAR_SEL 0x47\r
\r
//\r
// Constants and Structure definitions for "Clear SEL" command to follow here\r
//\r
-#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII 0x43\r
-#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII 0x4C\r
-#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII 0x52\r
-#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE 0xAA\r
-#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS 0x00\r
+#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII 0x43\r
+#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII 0x4C\r
+#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII 0x52\r
+#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE 0xAA\r
+#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS 0x00\r
\r
typedef struct {\r
- UINT8 Reserve[2]; // Reserve ID, LSB first\r
- UINT8 AscC; // Ascii for 'C' (0x43)\r
- UINT8 AscL; // Ascii for 'L' (0x4c)\r
- UINT8 AscR; // Ascii for 'R' (0x52)\r
- UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status\r
+ UINT8 Reserve[2]; // Reserve ID, LSB first\r
+ UINT8 AscC; // Ascii for 'C' (0x43)\r
+ UINT8 AscL; // Ascii for 'L' (0x4c)\r
+ UINT8 AscR; // Ascii for 'R' (0x52)\r
+ UINT8 Erase; // 0xAA, Initiate Erase, 0x00 Get Erase Status\r
} IPMI_CLEAR_SEL_REQUEST;\r
\r
-#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS 0x00\r
-#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED 0x01\r
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS 0x00\r
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED 0x01\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ErasureProgress;\r
+ UINT8 CompletionCode;\r
+ UINT8 ErasureProgress;\r
} IPMI_CLEAR_SEL_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Get SEL Time" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT32 Timestamp; // Present Timestamp clock reading. LS byte first.\r
+ UINT8 CompletionCode;\r
+ UINT32 Timestamp; // Present Timestamp clock reading. LS byte first.\r
} IPMI_GET_SEL_TIME_RESPONSE;\r
\r
//\r
// Constants and Structure definitions for "Set SEL Time" command to follow here\r
//\r
typedef struct {\r
- UINT32 Timestamp;\r
+ UINT32 Timestamp;\r
} IPMI_SET_SEL_TIME_REQUEST;\r
\r
//\r
//\r
// Definitions for Get SEL Time UTC Offset command\r
//\r
-#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET 0x5C\r
+#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET 0x5C\r
\r
//\r
// Constants and Structure definitions for "Get SEL Time UTC Offset" command to follow here\r
//\r
typedef struct {\r
- UINT8 CompletionCode;\r
+ UINT8 CompletionCode;\r
//\r
// 16-bit, 2s-complement signed integer for the offset in minutes from UTC to SEL Time.\r
// LS-byte first. (ranges from -1440 to 1440)\r
//\r
- INT16 UtcOffset;\r
+ INT16 UtcOffset;\r
} IPMI_GET_SEL_TIME_UTC_OFFSET_RESPONSE;\r
\r
//\r
// Definitions for Set SEL Time UTC Offset command\r
//\r
-#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET 0x5D\r
+#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET 0x5D\r
\r
//\r
// Constants and Structure definitions for "Set SEL Time UTC Offset" command to follow here\r
//\r
\r
-#define IPMI_COMPLETE_SEL_RECORD 0xFF\r
+#define IPMI_COMPLETE_SEL_RECORD 0xFF\r
\r
-#define IPMI_SEL_SYSTEM_RECORD 0x02\r
-#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START 0xC0\r
-#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END 0xDF\r
-#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START 0xE0\r
-#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END 0xFF\r
+#define IPMI_SEL_SYSTEM_RECORD 0x02\r
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START 0xC0\r
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END 0xDF\r
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START 0xE0\r
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END 0xFF\r
\r
-#define IPMI_SEL_EVENT_DIR(EventDirType) (EventDirType >> 7)\r
-#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT 0x00\r
-#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT 0x01\r
+#define IPMI_SEL_EVENT_DIR(EventDirType) (EventDirType >> 7)\r
+#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT 0x00\r
+#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT 0x01\r
\r
-#define IPMI_SEL_EVENT_TYPE(EventDirType) (EventDirType & 0x7F)\r
+#define IPMI_SEL_EVENT_TYPE(EventDirType) (EventDirType & 0x7F)\r
//\r
// Event/Reading Type Code Ranges (Chapter 42)\r
//\r
-#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED 0x00\r
-#define IPMI_SEL_EVENT_TYPE_THRESHOLD 0x01\r
-#define IPMI_SEL_EVENT_TYPE_GENERIC_START 0x02\r
-#define IPMI_SEL_EVENT_TYPE_GENERIC_END 0x0C\r
-#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC 0x6F\r
-#define IPMI_SEL_EVENT_TYPE_OEM_START 0x70\r
-#define IPMI_SEL_EVENT_TYPE_OEM_END 0x7F\r
+#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED 0x00\r
+#define IPMI_SEL_EVENT_TYPE_THRESHOLD 0x01\r
+#define IPMI_SEL_EVENT_TYPE_GENERIC_START 0x02\r
+#define IPMI_SEL_EVENT_TYPE_GENERIC_END 0x0C\r
+#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC 0x6F\r
+#define IPMI_SEL_EVENT_TYPE_OEM_START 0x70\r
+#define IPMI_SEL_EVENT_TYPE_OEM_END 0x7F\r
\r
-#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)\r
+#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)\r
//\r
// System Software IDs definitions (Section 5.5)\r
//\r
-#define IPMI_SWID_BIOS_RANGE_START 0x00\r
-#define IPMI_SWID_BIOS_RANGE_END 0x0F\r
-#define IPMI_SWID_SMI_HANDLER_RANGE_START 0x10\r
-#define IPMI_SWID_SMI_HANDLER_RANGE_END 0x1F\r
-#define IPMI_SWID_SMS_RANGE_START 0x20\r
-#define IPMI_SWID_SMS_RANGE_END 0x2F\r
-#define IPMI_SWID_OEM_RANGE_START 0x30\r
-#define IPMI_SWID_OEM_RANGE_END 0x3F\r
-#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START 0x40\r
-#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END 0x46\r
-#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID 0x47\r
-\r
-#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)\r
-#define LUN_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 8) & 0x03)\r
-#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 12) & 0x0F)\r
-\r
-#define IPMI_EVM_REVISION 0x04\r
-#define IPMI_BIOS_ID 0x18\r
-#define IPMI_FORMAT_REV 0x00\r
-#define IPMI_FORMAT_REV1 0x01\r
-#define IPMI_SOFTWARE_ID 0x01\r
-#define IPMI_PLATFORM_VAL_ID 0x01\r
-#define IPMI_GENERATOR_ID(i,f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)\r
-\r
-#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F\r
-\r
-#define IPMI_OEM_SPECIFIC_DATA 0x02\r
-#define IPMI_SENSOR_SPECIFIC_DATA 0x03\r
+#define IPMI_SWID_BIOS_RANGE_START 0x00\r
+#define IPMI_SWID_BIOS_RANGE_END 0x0F\r
+#define IPMI_SWID_SMI_HANDLER_RANGE_START 0x10\r
+#define IPMI_SWID_SMI_HANDLER_RANGE_END 0x1F\r
+#define IPMI_SWID_SMS_RANGE_START 0x20\r
+#define IPMI_SWID_SMS_RANGE_END 0x2F\r
+#define IPMI_SWID_OEM_RANGE_START 0x30\r
+#define IPMI_SWID_OEM_RANGE_END 0x3F\r
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START 0x40\r
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END 0x46\r
+#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID 0x47\r
+\r
+#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId & 0xFF) >> 1)\r
+#define LUN_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 8) & 0x03)\r
+#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId) ((GeneratorId >> 12) & 0x0F)\r
+\r
+#define IPMI_EVM_REVISION 0x04\r
+#define IPMI_BIOS_ID 0x18\r
+#define IPMI_FORMAT_REV 0x00\r
+#define IPMI_FORMAT_REV1 0x01\r
+#define IPMI_SOFTWARE_ID 0x01\r
+#define IPMI_PLATFORM_VAL_ID 0x01\r
+#define IPMI_GENERATOR_ID(i, f) ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)\r
+\r
+#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE 0x6F\r
+\r
+#define IPMI_OEM_SPECIFIC_DATA 0x02\r
+#define IPMI_SENSOR_SPECIFIC_DATA 0x03\r
\r
#pragma pack()\r
#endif\r
//\r
// Definitions for Set Lan Configuration Parameters command\r
//\r
-#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01\r
+#define IPMI_TRANSPORT_SET_LAN_CONFIG_PARAMETERS 0x01\r
\r
//\r
// Constants and Structure definitions for "Set Lan Configuration Parameters" command to follow here\r
\r
typedef union {\r
struct {\r
- UINT8 NoAuth : 1;\r
- UINT8 MD2Auth : 1;\r
- UINT8 MD5Auth : 1;\r
- UINT8 Reserved1 : 1;\r
- UINT8 StraightPswd : 1;\r
- UINT8 OemType : 1;\r
- UINT8 Reserved2 : 2;\r
+ UINT8 NoAuth : 1;\r
+ UINT8 MD2Auth : 1;\r
+ UINT8 MD5Auth : 1;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 StraightPswd : 1;\r
+ UINT8 OemType : 1;\r
+ UINT8 Reserved2 : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_AUTH_TYPE;\r
\r
typedef struct {\r
- UINT8 IpAddress[4];\r
+ UINT8 IpAddress[4];\r
} IPMI_LAN_IP_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 AddressSrc : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 AddressSrc : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_IP_ADDRESS_SRC;\r
\r
typedef struct {\r
- UINT8 MacAddress[6];\r
+ UINT8 MacAddress[6];\r
} IPMI_LAN_MAC_ADDRESS;\r
\r
typedef struct {\r
- UINT8 IpAddress[4];\r
+ UINT8 IpAddress[4];\r
} IPMI_LAN_SUBNET_MASK;\r
\r
typedef union {\r
struct {\r
- UINT8 IpFlag : 3;\r
- UINT8 Reserved : 5;\r
+ UINT8 IpFlag : 3;\r
+ UINT8 Reserved : 5;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_IPV4_HDR_PARAM_DATA_2;\r
\r
typedef union {\r
struct {\r
- UINT8 Precedence : 3;\r
- UINT8 Reserved : 1;\r
- UINT8 ServiceType : 4;\r
+ UINT8 Precedence : 3;\r
+ UINT8 Reserved : 1;\r
+ UINT8 ServiceType : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_IPV4_HDR_PARAM_DATA_3;\r
\r
typedef struct {\r
- UINT8 TimeToLive;\r
- IPMI_LAN_IPV4_HDR_PARAM_DATA_2 Data2;\r
- IPMI_LAN_IPV4_HDR_PARAM_DATA_3 Data3;\r
+ UINT8 TimeToLive;\r
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_2 Data2;\r
+ IPMI_LAN_IPV4_HDR_PARAM_DATA_3 Data3;\r
} IPMI_LAN_IPV4_HDR_PARAM;\r
\r
typedef struct {\r
- UINT8 RcmpPortMsb;\r
- UINT8 RcmpPortLsb;\r
+ UINT8 RcmpPortMsb;\r
+ UINT8 RcmpPortLsb;\r
} IPMI_LAN_RCMP_PORT;\r
\r
typedef union {\r
struct {\r
- UINT8 EnableBmcArpResponse : 1;\r
- UINT8 EnableBmcGratuitousArp : 1;\r
- UINT8 Reserved : 6;\r
+ UINT8 EnableBmcArpResponse : 1;\r
+ UINT8 EnableBmcGratuitousArp : 1;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_BMC_GENERATED_ARP_CONTROL;\r
\r
typedef struct {\r
- UINT8 ArpInterval;\r
+ UINT8 ArpInterval;\r
} IPMI_LAN_ARP_INTERVAL;\r
\r
typedef struct {\r
- UINT8 Data[18];\r
+ UINT8 Data[18];\r
} IPMI_LAN_COMMUNITY_STRING;\r
\r
typedef union {\r
struct {\r
- UINT8 DestinationSelector : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 DestinationSelector : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_SET_SELECTOR;\r
\r
typedef union {\r
struct {\r
- UINT8 DestinationType : 3;\r
- UINT8 Reserved : 4;\r
- UINT8 AlertAcknowledged : 1;\r
+ UINT8 DestinationType : 3;\r
+ UINT8 Reserved : 4;\r
+ UINT8 AlertAcknowledged : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_DEST_TYPE_DESTINATION_TYPE;\r
\r
typedef struct {\r
- IPMI_LAN_SET_SELECTOR SetSelector;\r
- IPMI_LAN_DEST_TYPE_DESTINATION_TYPE DestinationType;\r
+ IPMI_LAN_SET_SELECTOR SetSelector;\r
+ IPMI_LAN_DEST_TYPE_DESTINATION_TYPE DestinationType;\r
} IPMI_LAN_DEST_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 AlertingIpAddressSelector : 4;\r
- UINT8 AddressFormat : 4;\r
+ UINT8 AlertingIpAddressSelector : 4;\r
+ UINT8 AddressFormat : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_ADDRESS_FORMAT;\r
\r
typedef union {\r
struct {\r
- UINT8 UseDefaultGateway : 1;\r
- UINT8 Reserved2 : 7;\r
+ UINT8 UseDefaultGateway : 1;\r
+ UINT8 Reserved2 : 7;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_GATEWAY_SELECTOR;\r
\r
typedef struct {\r
- IPMI_LAN_SET_SELECTOR SetSelector;\r
- IPMI_LAN_ADDRESS_FORMAT AddressFormat;\r
- IPMI_LAN_GATEWAY_SELECTOR GatewaySelector;\r
- IPMI_LAN_IP_ADDRESS AlertingIpAddress;\r
- IPMI_LAN_MAC_ADDRESS AlertingMacAddress;\r
+ IPMI_LAN_SET_SELECTOR SetSelector;\r
+ IPMI_LAN_ADDRESS_FORMAT AddressFormat;\r
+ IPMI_LAN_GATEWAY_SELECTOR GatewaySelector;\r
+ IPMI_LAN_IP_ADDRESS AlertingIpAddress;\r
+ IPMI_LAN_MAC_ADDRESS AlertingMacAddress;\r
} IPMI_LAN_DEST_ADDRESS;\r
\r
typedef union {\r
- IPMI_LAN_AUTH_TYPE IpmiLanAuthType;\r
- IPMI_LAN_IP_ADDRESS IpmiLanIpAddress;\r
- IPMI_LAN_IP_ADDRESS_SRC IpmiLanIpAddressSrc;\r
- IPMI_LAN_MAC_ADDRESS IpmiLanMacAddress;\r
- IPMI_LAN_SUBNET_MASK IpmiLanSubnetMask;\r
- IPMI_LAN_IPV4_HDR_PARAM IpmiLanIpv4HdrParam;\r
- IPMI_LAN_RCMP_PORT IpmiLanPrimaryRcmpPort;\r
- IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl;\r
- IPMI_LAN_ARP_INTERVAL IpmiLanArpInterval;\r
- IPMI_LAN_COMMUNITY_STRING IpmiLanCommunityString;\r
- IPMI_LAN_DEST_TYPE IpmiLanDestType;\r
- IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress;\r
+ IPMI_LAN_AUTH_TYPE IpmiLanAuthType;\r
+ IPMI_LAN_IP_ADDRESS IpmiLanIpAddress;\r
+ IPMI_LAN_IP_ADDRESS_SRC IpmiLanIpAddressSrc;\r
+ IPMI_LAN_MAC_ADDRESS IpmiLanMacAddress;\r
+ IPMI_LAN_SUBNET_MASK IpmiLanSubnetMask;\r
+ IPMI_LAN_IPV4_HDR_PARAM IpmiLanIpv4HdrParam;\r
+ IPMI_LAN_RCMP_PORT IpmiLanPrimaryRcmpPort;\r
+ IPMI_LAN_BMC_GENERATED_ARP_CONTROL IpmiLanArpControl;\r
+ IPMI_LAN_ARP_INTERVAL IpmiLanArpInterval;\r
+ IPMI_LAN_COMMUNITY_STRING IpmiLanCommunityString;\r
+ IPMI_LAN_DEST_TYPE IpmiLanDestType;\r
+ IPMI_LAN_DEST_ADDRESS IpmiLanDestAddress;\r
} IPMI_LAN_OPTIONS;\r
\r
typedef union {\r
struct {\r
- UINT8 AddressSourceType : 4;\r
- UINT8 Reserved : 3;\r
- UINT8 EnableStatus : 1;\r
+ UINT8 AddressSourceType : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 EnableStatus : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE;\r
\r
typedef struct {\r
- UINT8 SetSelector;\r
- IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE AddressSourceType;\r
- UINT8 Ipv6Address[16];\r
- UINT8 AddressPrefixLen;\r
- UINT8 AddressStatus;\r
+ UINT8 SetSelector;\r
+ IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE AddressSourceType;\r
+ UINT8 Ipv6Address[16];\r
+ UINT8 AddressPrefixLen;\r
+ UINT8 AddressStatus;\r
} IPMI_LAN_IPV6_STATIC_ADDRESS;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 SetInProgress:2;\r
- UINT8 Reserved:6;\r
+ UINT8 SetInProgress : 2;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_LAN_SET_IN_PROGRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SET_LAN_CONFIG_CHANNEL_NUM;\r
\r
typedef struct {\r
- IPMI_SET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;\r
- UINT8 ParameterSelector;\r
- UINT8 ParameterData[0];\r
+ IPMI_SET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;\r
+ UINT8 ParameterSelector;\r
+ UINT8 ParameterData[0];\r
} IPMI_SET_LAN_CONFIGURATION_PARAMETERS_COMMAND_REQUEST;\r
\r
//\r
// Definitions for Get Lan Configuration Parameters command\r
//\r
-#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02\r
+#define IPMI_TRANSPORT_GET_LAN_CONFIG_PARAMETERS 0x02\r
\r
//\r
// Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 3;\r
- UINT8 GetParameter : 1;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 GetParameter : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_LAN_CONFIG_CHANNEL_NUM;\r
\r
typedef struct {\r
- IPMI_GET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;\r
- UINT8 ParameterSelector;\r
- UINT8 SetSelector;\r
- UINT8 BlockSelector;\r
+ IPMI_GET_LAN_CONFIG_CHANNEL_NUM ChannelNumber;\r
+ UINT8 ParameterSelector;\r
+ UINT8 SetSelector;\r
+ UINT8 BlockSelector;\r
} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ParameterRevision;\r
- UINT8 ParameterData[0];\r
+ UINT8 CompletionCode;\r
+ UINT8 ParameterRevision;\r
+ UINT8 ParameterData[0];\r
} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_RESPONSE;\r
\r
//\r
//\r
// Definitions for Get IP-UDP-RMCP Statistics command\r
//\r
-#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04\r
+#define IPMI_TRANSPORT_GET_PACKET_STATISTICS 0x04\r
\r
//\r
// Constants and Structure definitions for "Get IP-UDP-RMCP Statistics" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 NoAuthentication : 1;\r
- UINT8 MD2Authentication : 1;\r
- UINT8 MD5Authentication : 1;\r
- UINT8 Reserved1 : 1;\r
- UINT8 StraightPassword : 1;\r
- UINT8 OemProprietary : 1;\r
- UINT8 Reservd2 : 2;\r
+ UINT8 NoAuthentication : 1;\r
+ UINT8 MD2Authentication : 1;\r
+ UINT8 MD5Authentication : 1;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 StraightPassword : 1;\r
+ UINT8 OemProprietary : 1;\r
+ UINT8 Reservd2 : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_AUTH_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 EnableBasicMode : 1;\r
- UINT8 EnablePPPMode : 1;\r
- UINT8 EnableTerminalMode : 1;\r
- UINT8 Reserved1 : 2;\r
- UINT8 SnoopOsPPPNegotiation : 1;\r
- UINT8 Reserved2 : 1;\r
- UINT8 DirectConnect : 1;\r
+ UINT8 EnableBasicMode : 1;\r
+ UINT8 EnablePPPMode : 1;\r
+ UINT8 EnableTerminalMode : 1;\r
+ UINT8 Reserved1 : 2;\r
+ UINT8 SnoopOsPPPNegotiation : 1;\r
+ UINT8 Reserved2 : 1;\r
+ UINT8 DirectConnect : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_CONNECTION_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 InactivityTimeout : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 InactivityTimeout : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_INACTIVITY_TIMEOUT;\r
\r
typedef union {\r
struct {\r
- UINT8 IpmiCallback : 1;\r
- UINT8 CBCPCallback : 1;\r
- UINT8 Reserved : 6;\r
+ UINT8 IpmiCallback : 1;\r
+ UINT8 CBCPCallback : 1;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE;\r
\r
typedef union {\r
struct {\r
- UINT8 CbcpEnableNoCallback : 1;\r
- UINT8 CbcpEnablePreSpecifiedNumber : 1;\r
- UINT8 CbcpEnableUserSpecifiedNumber : 1;\r
- UINT8 CbcpEnableCallbackFromList : 1;\r
- UINT8 Reserved : 4;\r
+ UINT8 CbcpEnableNoCallback : 1;\r
+ UINT8 CbcpEnablePreSpecifiedNumber : 1;\r
+ UINT8 CbcpEnableUserSpecifiedNumber : 1;\r
+ UINT8 CbcpEnableCallbackFromList : 1;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_CHANNEL_CALLBACK_CONTROL_CBCP;\r
\r
typedef struct {\r
- IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE CallbackEnable;\r
- IPMI_CHANNEL_CALLBACK_CONTROL_CBCP CBCPNegotiation;\r
- UINT8 CallbackDestination1;\r
- UINT8 CallbackDestination2;\r
- UINT8 CallbackDestination3;\r
+ IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE CallbackEnable;\r
+ IPMI_CHANNEL_CALLBACK_CONTROL_CBCP CBCPNegotiation;\r
+ UINT8 CallbackDestination1;\r
+ UINT8 CallbackDestination2;\r
+ UINT8 CallbackDestination3;\r
} IPMI_EMP_CHANNEL_CALLBACK_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT8 CloseSessionOnDCDLoss : 1;\r
- UINT8 EnableSessionInactivityTimeout : 1;\r
- UINT8 Reserved : 6;\r
+ UINT8 CloseSessionOnDCDLoss : 1;\r
+ UINT8 EnableSessionInactivityTimeout : 1;\r
+ UINT8 Reserved : 6;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_SESSION_TERMINATION;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved1 : 5;\r
- UINT8 EnableDtrHangup : 1;\r
- UINT8 FlowControl : 2;\r
- UINT8 BitRate : 4;\r
- UINT8 Reserved2 : 4;\r
- UINT8 SaveSetting : 1;\r
- UINT8 SetComPort : 1;\r
- UINT8 Reserved3 : 6;\r
+ UINT8 Reserved1 : 5;\r
+ UINT8 EnableDtrHangup : 1;\r
+ UINT8 FlowControl : 2;\r
+ UINT8 BitRate : 4;\r
+ UINT8 Reserved2 : 4;\r
+ UINT8 SaveSetting : 1;\r
+ UINT8 SetComPort : 1;\r
+ UINT8 Reserved3 : 6;\r
} Bits;\r
- UINT8 Uint8;\r
- UINT16 Uint16;\r
+ UINT8 Uint8;\r
+ UINT16 Uint16;\r
} IPMI_EMP_MESSAGING_COM_SETTING;\r
\r
typedef union {\r
struct {\r
- UINT8 RingDurationInterval : 6;\r
- UINT8 Reserved1 : 2;\r
- UINT8 RingDeadTime : 4;\r
- UINT8 Reserved2 : 4;\r
+ UINT8 RingDurationInterval : 6;\r
+ UINT8 Reserved1 : 2;\r
+ UINT8 RingDeadTime : 4;\r
+ UINT8 Reserved2 : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_MODEM_RING_TIME;\r
\r
typedef struct {\r
- UINT8 Reserved;\r
- UINT8 InitString[48];\r
+ UINT8 Reserved;\r
+ UINT8 InitString[48];\r
} IPMI_EMP_MODEM_INIT_STRING;\r
\r
typedef struct {\r
- UINT8 EscapeSequence[5];\r
+ UINT8 EscapeSequence[5];\r
} IPMI_EMP_MODEM_ESC_SEQUENCE;\r
\r
typedef struct {\r
- UINT8 HangupSequence[8];\r
+ UINT8 HangupSequence[8];\r
} IPMI_EMP_MODEM_HANGUP_SEQUENCE;\r
\r
typedef struct {\r
- UINT8 ModelDialCommend[8];\r
+ UINT8 ModelDialCommend[8];\r
} IPMI_MODEM_DIALUP_COMMAND;\r
\r
typedef struct {\r
- UINT8 PageBlackoutInterval;\r
+ UINT8 PageBlackoutInterval;\r
} IPMI_PAGE_BLACKOUT_INTERVAL;\r
\r
typedef struct {\r
- UINT8 CommunityString[18];\r
+ UINT8 CommunityString[18];\r
} IPMI_EMP_COMMUNITY_STRING;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 4;\r
- UINT8 DialStringSelector : 4;\r
+ UINT8 Reserved : 4;\r
+ UINT8 DialStringSelector : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_DIAL_PAGE_DESTINATION;\r
\r
typedef union {\r
struct {\r
- UINT8 TapAccountSelector : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 TapAccountSelector : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_TAP_PAGE_DESTINATION;\r
\r
typedef struct {\r
- UINT8 PPPAccountSetSelector;\r
- UINT8 DialStringSelector;\r
+ UINT8 PPPAccountSetSelector;\r
+ UINT8 DialStringSelector;\r
} IPMI_PPP_ALERT_DESTINATION;\r
\r
typedef union {\r
\r
typedef union {\r
struct {\r
- UINT8 DestinationSelector : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 DestinationSelector : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_DESTINATION_SELECTOR;\r
\r
typedef union {\r
struct {\r
- UINT8 DestinationType : 4;\r
- UINT8 Reserved : 3;\r
- UINT8 AlertAckRequired : 1;\r
+ UINT8 DestinationType : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 AlertAckRequired : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_DESTINATION_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 NumRetriesCall : 3;\r
- UINT8 Reserved1 : 1;\r
- UINT8 NumRetryAlert : 3;\r
- UINT8 Reserved2 : 1;\r
+ UINT8 NumRetriesCall : 3;\r
+ UINT8 Reserved1 : 1;\r
+ UINT8 NumRetryAlert : 3;\r
+ UINT8 Reserved2 : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_RETRIES;\r
\r
typedef struct {\r
- IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;\r
- IPMI_EMP_DESTINATION_TYPE DestinationType;\r
- UINT8 AlertAckTimeoutSeconds;\r
- IPMI_EMP_RETRIES Retries;\r
- IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;\r
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;\r
+ IPMI_EMP_DESTINATION_TYPE DestinationType;\r
+ UINT8 AlertAckTimeoutSeconds;\r
+ IPMI_EMP_RETRIES Retries;\r
+ IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;\r
} IPMI_EMP_DESTINATION_INFO;\r
\r
typedef union {\r
struct {\r
- UINT8 Parity : 3;\r
- UINT8 CharacterSize : 1;\r
- UINT8 StopBit : 1;\r
- UINT8 DtrHangup : 1;\r
- UINT8 FlowControl : 2;\r
+ UINT8 Parity : 3;\r
+ UINT8 CharacterSize : 1;\r
+ UINT8 StopBit : 1;\r
+ UINT8 DtrHangup : 1;\r
+ UINT8 FlowControl : 2;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_DESTINATION_COM_SETTING_DATA_2;\r
\r
typedef union {\r
struct {\r
- UINT8 BitRate : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 BitRate : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_EMP_BIT_RATE;\r
\r
typedef struct {\r
- IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;\r
- IPMI_EMP_DESTINATION_COM_SETTING_DATA_2 Data2;\r
- IPMI_EMP_BIT_RATE BitRate;\r
+ IPMI_EMP_DESTINATION_SELECTOR DestinationSelector;\r
+ IPMI_EMP_DESTINATION_COM_SETTING_DATA_2 Data2;\r
+ IPMI_EMP_BIT_RATE BitRate;\r
} IPMI_EMP_DESTINATION_COM_SETTING;\r
\r
typedef union {\r
struct {\r
- UINT8 DialStringSelector : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 DialStringSelector : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_DIAL_STRING_SELECTOR;\r
\r
typedef struct {\r
- IPMI_DIAL_STRING_SELECTOR DestinationSelector;\r
- UINT8 Reserved;\r
- UINT8 DialString[48];\r
+ IPMI_DIAL_STRING_SELECTOR DestinationSelector;\r
+ UINT8 Reserved;\r
+ UINT8 DialString[48];\r
} IPMI_DESTINATION_DIAL_STRING;\r
\r
typedef union {\r
- UINT32 IpAddressLong;\r
- UINT8 IpAddress[4];\r
+ UINT32 IpAddressLong;\r
+ UINT8 IpAddress[4];\r
} IPMI_PPP_IP_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 IpAddressSelector : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 IpAddressSelector : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_DESTINATION_IP_ADDRESS_SELECTOR;\r
\r
typedef struct {\r
- IPMI_DESTINATION_IP_ADDRESS_SELECTOR DestinationSelector;\r
- IPMI_PPP_IP_ADDRESS PppIpAddress;\r
+ IPMI_DESTINATION_IP_ADDRESS_SELECTOR DestinationSelector;\r
+ IPMI_PPP_IP_ADDRESS PppIpAddress;\r
} IPMI_DESTINATION_IP_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 TapServiceSelector : 4;\r
- UINT8 TapDialStringSelector : 4;\r
+ UINT8 TapServiceSelector : 4;\r
+ UINT8 TapDialStringSelector : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR;\r
\r
-\r
typedef struct {\r
- UINT8 TapSelector;\r
- IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR TapDialStringServiceSelector;\r
+ UINT8 TapSelector;\r
+ IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR TapDialStringServiceSelector;\r
} IPMI_DESTINATION_TAP_ACCOUNT;\r
\r
typedef struct {\r
- UINT8 TapSelector;\r
- UINT8 PagerIdString[16];\r
+ UINT8 TapSelector;\r
+ UINT8 PagerIdString[16];\r
} IPMI_TAP_PAGER_ID_STRING;\r
\r
typedef union {\r
- UINT8 OptionData;\r
- IPMI_EMP_AUTH_TYPE EmpAuthType;\r
- IPMI_EMP_CONNECTION_TYPE EmpConnectionType;\r
- IPMI_EMP_INACTIVITY_TIMEOUT EmpInactivityTimeout;\r
- IPMI_EMP_CHANNEL_CALLBACK_CONTROL EmpCallbackControl;\r
- IPMI_EMP_SESSION_TERMINATION EmpSessionTermination;\r
- IPMI_EMP_MESSAGING_COM_SETTING EmpMessagingComSetting;\r
- IPMI_EMP_MODEM_RING_TIME EmpModemRingTime;\r
- IPMI_EMP_MODEM_INIT_STRING EmpModemInitString;\r
- IPMI_EMP_MODEM_ESC_SEQUENCE EmpModemEscSequence;\r
- IPMI_EMP_MODEM_HANGUP_SEQUENCE EmpModemHangupSequence;\r
- IPMI_MODEM_DIALUP_COMMAND EmpModemDialupCommand;\r
- IPMI_PAGE_BLACKOUT_INTERVAL EmpPageBlackoutInterval;\r
- IPMI_EMP_COMMUNITY_STRING EmpCommunityString;\r
- IPMI_EMP_DESTINATION_INFO EmpDestinationInfo;\r
- IPMI_EMP_DESTINATION_COM_SETTING EmpDestinationComSetting;\r
- UINT8 CallRetryBusySignalInterval;\r
- IPMI_DESTINATION_DIAL_STRING DestinationDialString;\r
- IPMI_DESTINATION_IP_ADDRESS DestinationIpAddress;\r
- IPMI_DESTINATION_TAP_ACCOUNT DestinationTapAccount;\r
- IPMI_TAP_PAGER_ID_STRING TapPagerIdString;\r
+ UINT8 OptionData;\r
+ IPMI_EMP_AUTH_TYPE EmpAuthType;\r
+ IPMI_EMP_CONNECTION_TYPE EmpConnectionType;\r
+ IPMI_EMP_INACTIVITY_TIMEOUT EmpInactivityTimeout;\r
+ IPMI_EMP_CHANNEL_CALLBACK_CONTROL EmpCallbackControl;\r
+ IPMI_EMP_SESSION_TERMINATION EmpSessionTermination;\r
+ IPMI_EMP_MESSAGING_COM_SETTING EmpMessagingComSetting;\r
+ IPMI_EMP_MODEM_RING_TIME EmpModemRingTime;\r
+ IPMI_EMP_MODEM_INIT_STRING EmpModemInitString;\r
+ IPMI_EMP_MODEM_ESC_SEQUENCE EmpModemEscSequence;\r
+ IPMI_EMP_MODEM_HANGUP_SEQUENCE EmpModemHangupSequence;\r
+ IPMI_MODEM_DIALUP_COMMAND EmpModemDialupCommand;\r
+ IPMI_PAGE_BLACKOUT_INTERVAL EmpPageBlackoutInterval;\r
+ IPMI_EMP_COMMUNITY_STRING EmpCommunityString;\r
+ IPMI_EMP_DESTINATION_INFO EmpDestinationInfo;\r
+ IPMI_EMP_DESTINATION_COM_SETTING EmpDestinationComSetting;\r
+ UINT8 CallRetryBusySignalInterval;\r
+ IPMI_DESTINATION_DIAL_STRING DestinationDialString;\r
+ IPMI_DESTINATION_IP_ADDRESS DestinationIpAddress;\r
+ IPMI_DESTINATION_TAP_ACCOUNT DestinationTapAccount;\r
+ IPMI_TAP_PAGER_ID_STRING TapPagerIdString;\r
} IPMI_EMP_OPTIONS;\r
\r
//\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNo : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNo : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_MUX_CHANNEL_NUM;\r
\r
typedef union {\r
struct {\r
- UINT8 MuxSetting : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 MuxSetting : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_MUX_SETTING_REQUEST;\r
\r
typedef struct {\r
- IPMI_MUX_CHANNEL_NUM ChannelNumber;\r
- IPMI_MUX_SETTING_REQUEST MuxSetting;\r
+ IPMI_MUX_CHANNEL_NUM ChannelNumber;\r
+ IPMI_MUX_SETTING_REQUEST MuxSetting;\r
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;\r
\r
typedef union {\r
struct {\r
- UINT8 MuxSetToBmc : 1;\r
- UINT8 CommandStatus : 1;\r
- UINT8 MessagingSessionActive : 1;\r
- UINT8 AlertInProgress : 1;\r
- UINT8 Reserved : 2;\r
- UINT8 MuxToBmcAllowed : 1;\r
- UINT8 MuxToSystemBlocked : 1;\r
+ UINT8 MuxSetToBmc : 1;\r
+ UINT8 CommandStatus : 1;\r
+ UINT8 MessagingSessionActive : 1;\r
+ UINT8 AlertInProgress : 1;\r
+ UINT8 Reserved : 2;\r
+ UINT8 MuxToBmcAllowed : 1;\r
+ UINT8 MuxToSystemBlocked : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_MUX_SETTING_PRESENT_STATE;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- IPMI_MUX_SETTING_PRESENT_STATE MuxSetting;\r
+ UINT8 CompletionCode;\r
+ IPMI_MUX_SETTING_PRESENT_STATE MuxSetting;\r
} IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;\r
\r
//\r
// Definitions for Get TAP Response Code command\r
//\r
-#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13\r
+#define IPMI_TRANSPORT_GET_TAP_RESPONSE_CODE 0x13\r
\r
//\r
// Constants and Structure definitions for "Get TAP Response Code" command to follow here\r
//\r
// Definitions for Send PPP UDP Proxy Packet command\r
//\r
-#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16\r
+#define IPMI_TRANSPORT_SEND_PPP_UDP_PROXY_PACKET 0x16\r
\r
//\r
// Constants and Structure definitions for "Send PPP UDP Proxy Packet" command to follow here\r
//\r
// Definitions for Set user Callback Options command\r
//\r
-#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A\r
+#define IPMI_TRANSPORT_SET_USER_CALLBACK_OPTIONS 0x1A\r
\r
//\r
// Constants and Structure definitions for "Set user Callback Options" command to follow here\r
//\r
// Definitions for Get user Callback Options command\r
//\r
-#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B\r
+#define IPMI_TRANSPORT_GET_USER_CALLBACK_OPTIONS 0x1B\r
\r
//\r
// Constants and Structure definitions for "Get user Callback Options" command to follow here\r
//\r
typedef union {\r
struct {\r
- UINT8 SessionState : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 SessionState : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SOL_SESSION_STATE;\r
\r
typedef struct {\r
- IPMI_SOL_SESSION_STATE SessionState;\r
- UINT8 PayloadInstance;\r
- UINT8 FormatVersionMajor; // 1\r
- UINT8 FormatVersionMinor; // 0\r
+ IPMI_SOL_SESSION_STATE SessionState;\r
+ UINT8 PayloadInstance;\r
+ UINT8 FormatVersionMajor; // 1\r
+ UINT8 FormatVersionMinor; // 0\r
} IPMI_SOL_ACTIVATING_REQUEST;\r
\r
//\r
//\r
// SOL Configuration Parameters selector\r
//\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS 0\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE 1\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION 2\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM 3\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY 4\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE 5\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL 7\r
-#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT 8\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS 0\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE 1\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION 2\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM 3\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY 4\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE 5\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL 7\r
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT 8\r
\r
typedef union {\r
struct {\r
- UINT8 ChannelNumber : 4;\r
- UINT8 Reserved : 4;\r
+ UINT8 ChannelNumber : 4;\r
+ UINT8 Reserved : 4;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM;\r
\r
typedef struct {\r
- IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;\r
- UINT8 ParameterSelector;\r
- UINT8 ParameterData[0];\r
+ IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;\r
+ UINT8 ParameterSelector;\r
+ UINT8 ParameterData[0];\r
} IPMI_SET_SOL_CONFIGURATION_PARAMETERS_REQUEST;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT8 ChannelNumber : 4;\r
- UINT8 Reserved : 3;\r
- UINT8 GetParameter : 1;\r
+ UINT8 ChannelNumber : 4;\r
+ UINT8 Reserved : 3;\r
+ UINT8 GetParameter : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM;\r
\r
typedef struct {\r
- IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;\r
- UINT8 ParameterSelector;\r
- UINT8 SetSelector;\r
- UINT8 BlockSelector;\r
+ IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM ChannelNumber;\r
+ UINT8 ParameterSelector;\r
+ UINT8 SetSelector;\r
+ UINT8 BlockSelector;\r
} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_REQUEST;\r
\r
typedef struct {\r
- UINT8 CompletionCode;\r
- UINT8 ParameterRevision;\r
- UINT8 ParameterData[0];\r
+ UINT8 CompletionCode;\r
+ UINT8 ParameterRevision;\r
+ UINT8 ParameterData[0];\r
} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_RESPONSE;\r
\r
#pragma pack()\r
#ifndef _LEGACY_BIOS_MPTABLE_H_\r
#define _LEGACY_BIOS_MPTABLE_H_\r
\r
-#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04\r
+#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04\r
\r
//\r
// Define MP table structures. All are packed.\r
\r
#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_')\r
typedef struct {\r
- UINT32 Reserved1 : 6;\r
- UINT32 MutipleClk : 1;\r
- UINT32 Imcr : 1;\r
- UINT32 Reserved2 : 24;\r
+ UINT32 Reserved1 : 6;\r
+ UINT32 MutipleClk : 1;\r
+ UINT32 Imcr : 1;\r
+ UINT32 Reserved2 : 24;\r
} FEATUREBYTE2_5;\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 PhysicalAddress;\r
- UINT8 Length;\r
- UINT8 SpecRev;\r
- UINT8 Checksum;\r
- UINT8 FeatureByte1;\r
- FEATUREBYTE2_5 FeatureByte2_5;\r
+ UINT32 Signature;\r
+ UINT32 PhysicalAddress;\r
+ UINT8 Length;\r
+ UINT8 SpecRev;\r
+ UINT8 Checksum;\r
+ UINT8 FeatureByte1;\r
+ FEATUREBYTE2_5 FeatureByte2_5;\r
} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;\r
\r
#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P')\r
typedef struct {\r
- UINT32 Signature;\r
- UINT16 BaseTableLength;\r
- UINT8 SpecRev;\r
- UINT8 Checksum;\r
- CHAR8 OemId[8];\r
- CHAR8 OemProductId[12];\r
- UINT32 OemTablePointer;\r
- UINT16 OemTableSize;\r
- UINT16 EntryCount;\r
- UINT32 LocalApicAddress;\r
- UINT16 ExtendedTableLength;\r
- UINT8 ExtendedChecksum;\r
- UINT8 Reserved;\r
+ UINT32 Signature;\r
+ UINT16 BaseTableLength;\r
+ UINT8 SpecRev;\r
+ UINT8 Checksum;\r
+ CHAR8 OemId[8];\r
+ CHAR8 OemProductId[12];\r
+ UINT32 OemTablePointer;\r
+ UINT16 OemTableSize;\r
+ UINT16 EntryCount;\r
+ UINT32 LocalApicAddress;\r
+ UINT16 ExtendedTableLength;\r
+ UINT8 ExtendedChecksum;\r
+ UINT8 Reserved;\r
} EFI_LEGACY_MP_TABLE_HEADER;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
+ UINT8 EntryType;\r
} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;\r
\r
//\r
//\r
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00\r
typedef struct {\r
- UINT8 Enabled : 1;\r
- UINT8 Bsp : 1;\r
- UINT8 Reserved : 6;\r
+ UINT8 Enabled : 1;\r
+ UINT8 Bsp : 1;\r
+ UINT8 Reserved : 6;\r
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS;\r
\r
typedef struct {\r
- UINT32 Stepping : 4;\r
- UINT32 Model : 4;\r
- UINT32 Family : 4;\r
- UINT32 Reserved : 20;\r
+ UINT32 Stepping : 4;\r
+ UINT32 Model : 4;\r
+ UINT32 Family : 4;\r
+ UINT32 Reserved : 20;\r
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE;\r
\r
typedef struct {\r
- UINT32 Fpu : 1;\r
- UINT32 Reserved1 : 6;\r
- UINT32 Mce : 1;\r
- UINT32 Cx8 : 1;\r
- UINT32 Apic : 1;\r
- UINT32 Reserved2 : 22;\r
+ UINT32 Fpu : 1;\r
+ UINT32 Reserved1 : 6;\r
+ UINT32 Mce : 1;\r
+ UINT32 Cx8 : 1;\r
+ UINT32 Apic : 1;\r
+ UINT32 Reserved2 : 22;\r
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Id;\r
- UINT8 Ver;\r
- EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS Flags;\r
- EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature;\r
- EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES Features;\r
- UINT32 Reserved1;\r
- UINT32 Reserved2;\r
+ UINT8 EntryType;\r
+ UINT8 Id;\r
+ UINT8 Ver;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FLAGS Flags;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_SIGNATURE Signature;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR_FEATURES Features;\r
+ UINT32 Reserved1;\r
+ UINT32 Reserved2;\r
} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;\r
\r
//\r
//\r
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Id;\r
- CHAR8 TypeString[6];\r
+ UINT8 EntryType;\r
+ UINT8 Id;\r
+ CHAR8 TypeString[6];\r
} EFI_LEGACY_MP_TABLE_ENTRY_BUS;\r
\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus\r
//\r
// Entry Type 2: I/O APIC.\r
//\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02\r
typedef struct {\r
- UINT8 Enabled : 1;\r
- UINT8 Reserved : 7;\r
+ UINT8 Enabled : 1;\r
+ UINT8 Reserved : 7;\r
} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Id;\r
- UINT8 Ver;\r
- EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags;\r
- UINT32 Address;\r
+ UINT8 EntryType;\r
+ UINT8 Id;\r
+ UINT8 Ver;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC_FLAGS Flags;\r
+ UINT32 Address;\r
} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;\r
\r
//\r
// Entry Type 3: I/O Interrupt Assignment.\r
//\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03\r
typedef struct {\r
- UINT16 Polarity : 2;\r
- UINT16 Trigger : 2;\r
- UINT16 Reserved : 12;\r
+ UINT16 Polarity : 2;\r
+ UINT16 Trigger : 2;\r
+ UINT16 Reserved : 12;\r
} EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS;\r
\r
typedef struct {\r
- UINT8 IntNo : 2;\r
- UINT8 Dev : 5;\r
- UINT8 Reserved : 1;\r
+ UINT8 IntNo : 2;\r
+ UINT8 Dev : 5;\r
+ UINT8 Reserved : 1;\r
} EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS;\r
\r
typedef union {\r
- EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields;\r
- UINT8 byte;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FIELDS fields;\r
+ UINT8 byte;\r
} EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 IntType;\r
- EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;\r
- UINT8 SourceBusId;\r
- EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;\r
- UINT8 DestApicId;\r
- UINT8 DestApicIntIn;\r
+ UINT8 EntryType;\r
+ UINT8 IntType;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;\r
+ UINT8 SourceBusId;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;\r
+ UINT8 DestApicId;\r
+ UINT8 DestApicIntIn;\r
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;\r
\r
typedef enum {\r
- EfiLegacyMpTableEntryIoIntTypeInt = 0,\r
- EfiLegacyMpTableEntryIoIntTypeNmi = 1,\r
- EfiLegacyMpTableEntryIoIntTypeSmi = 2,\r
- EfiLegacyMpTableEntryIoIntTypeExtInt= 3,\r
+ EfiLegacyMpTableEntryIoIntTypeInt = 0,\r
+ EfiLegacyMpTableEntryIoIntTypeNmi = 1,\r
+ EfiLegacyMpTableEntryIoIntTypeSmi = 2,\r
+ EfiLegacyMpTableEntryIoIntTypeExtInt = 3,\r
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;\r
\r
typedef enum {\r
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;\r
\r
typedef enum {\r
- EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,\r
- EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,\r
- EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,\r
- EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,\r
+ EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,\r
+ EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,\r
+ EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,\r
+ EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,\r
} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;\r
\r
//\r
//\r
#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 IntType;\r
- EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;\r
- UINT8 SourceBusId;\r
- EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;\r
- UINT8 DestApicId;\r
- UINT8 DestApicIntIn;\r
+ UINT8 EntryType;\r
+ UINT8 IntType;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_FLAGS Flags;\r
+ UINT8 SourceBusId;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_INT_SOURCE_BUS_IRQ SourceBusIrq;\r
+ UINT8 DestApicId;\r
+ UINT8 DestApicIntIn;\r
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;\r
\r
typedef enum {\r
- EfiLegacyMpTableEntryLocalIntTypeInt = 0,\r
- EfiLegacyMpTableEntryLocalIntTypeNmi = 1,\r
- EfiLegacyMpTableEntryLocalIntTypeSmi = 2,\r
- EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,\r
+ EfiLegacyMpTableEntryLocalIntTypeInt = 0,\r
+ EfiLegacyMpTableEntryLocalIntTypeNmi = 1,\r
+ EfiLegacyMpTableEntryLocalIntTypeSmi = 2,\r
+ EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,\r
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;\r
\r
typedef enum {\r
- EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,\r
- EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,\r
- EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,\r
- EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,\r
+ EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,\r
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh = 0x1,\r
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,\r
+ EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,\r
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;\r
\r
typedef enum {\r
- EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,\r
- EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,\r
- EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,\r
- EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,\r
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,\r
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,\r
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,\r
+ EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,\r
} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;\r
\r
//\r
// Entry Type 128: System Address Space Mapping.\r
//\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Length;\r
- UINT8 BusId;\r
- UINT8 AddressType;\r
- UINT64 AddressBase;\r
- UINT64 AddressLength;\r
+ UINT8 EntryType;\r
+ UINT8 Length;\r
+ UINT8 BusId;\r
+ UINT8 AddressType;\r
+ UINT64 AddressBase;\r
+ UINT64 AddressLength;\r
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;\r
\r
typedef enum {\r
//\r
#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81\r
typedef struct {\r
- UINT8 SubtractiveDecode : 1;\r
- UINT8 Reserved : 7;\r
+ UINT8 SubtractiveDecode : 1;\r
+ UINT8 Reserved : 7;\r
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Length;\r
- UINT8 BusId;\r
- EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo;\r
- UINT8 ParentBus;\r
- UINT8 Reserved1;\r
- UINT8 Reserved2;\r
- UINT8 Reserved3;\r
+ UINT8 EntryType;\r
+ UINT8 Length;\r
+ UINT8 BusId;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY_BUSINFO BusInfo;\r
+ UINT8 ParentBus;\r
+ UINT8 Reserved1;\r
+ UINT8 Reserved2;\r
+ UINT8 Reserved3;\r
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;\r
\r
//\r
// Entry Type 130: Compatibility Bus Address Space Modifier.\r
//\r
-#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82\r
+#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82\r
typedef struct {\r
- UINT8 RangeMode : 1;\r
- UINT8 Reserved : 7;\r
+ UINT8 RangeMode : 1;\r
+ UINT8 Reserved : 7;\r
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE;\r
\r
typedef struct {\r
- UINT8 EntryType;\r
- UINT8 Length;\r
- UINT8 BusId;\r
- EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode;\r
- UINT32 PredefinedRangeList;\r
+ UINT8 EntryType;\r
+ UINT8 Length;\r
+ UINT8 BusId;\r
+ EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER_ADDR_MODE AddrMode;\r
+ UINT32 PredefinedRangeList;\r
} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;\r
\r
#pragma pack()\r
- GAS - Generic Address Structure\r
- LPI - Low Power Idle\r
**/\r
+\r
#ifndef _LOW_POWER_IDLE_TABLE_H_\r
#define _LOW_POWER_IDLE_TABLE_H_\r
\r
///\r
/// LPI Structure Types\r
///\r
-#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00\r
+#define ACPI_LPI_STRUCTURE_TYPE_NATIVE_CSTATE 0x00\r
\r
///\r
/// Low Power Idle (LPI) State Flags\r
///\r
typedef union {\r
struct {\r
- UINT32 Disabled : 1; ///< If set, LPI state is not used\r
+ UINT32 Disabled : 1; ///< If set, LPI state is not used\r
+\r
/**\r
If set, Residency counter is not available for this LPI state and\r
Residency Counter Frequency is invalid\r
**/\r
- UINT32 CounterUnavailable : 1;\r
- UINT32 Reserved : 30; ///< Reserved for future use. Must be zero\r
+ UINT32 CounterUnavailable : 1;\r
+ UINT32 Reserved : 30; ///< Reserved for future use. Must be zero\r
} Bits;\r
- UINT32 Data32;\r
+ UINT32 Data32;\r
} ACPI_LPI_STATE_FLAGS;\r
\r
///\r
/// Low Power Idle (LPI) structure with Native C-state instruction entry trigger descriptor\r
///\r
typedef struct {\r
- UINT32 Type; ///< LPI State descriptor Type 0\r
- UINT32 Length; ///< Length of LPI state Descriptor Structure\r
+ UINT32 Type; ///< LPI State descriptor Type 0\r
+ UINT32 Length; ///< Length of LPI state Descriptor Structure\r
///\r
/// Unique LPI state identifier: zero based, monotonically increasing identifier\r
///\r
- UINT16 UniqueId;\r
- UINT8 Reserved[2]; ///< Must be Zero\r
- ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags\r
+ UINT16 UniqueId;\r
+ UINT8 Reserved[2]; ///< Must be Zero\r
+ ACPI_LPI_STATE_FLAGS Flags; ///< LPI state flags\r
+\r
/**\r
The LPI entry trigger, matching an existing _CST.Register object, represented as a\r
Generic Address Structure. All processors must request this state or deeper to trigger.\r
**/\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;\r
- UINT32 Residency; ///< Minimum residency or break-even in uSec\r
- UINT32 Latency; ///< Worst case exit latency in uSec\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE EntryTrigger;\r
+ UINT32 Residency; ///< Minimum residency or break-even in uSec\r
+ UINT32 Latency; ///< Worst case exit latency in uSec\r
+\r
/**\r
[optional] Residency counter, represented as a Generic Address Structure.\r
If not present, Flags[1] bit should be set.\r
**/\r
- EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;\r
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResidencyCounter;\r
+\r
/**\r
[optional] Residency counter frequency in cycles per second. Value 0 indicates that\r
counter runs at TSC frequency. Valid only if Residency Counter is present.\r
**/\r
- UINT64 ResidencyCounterFrequency;\r
+ UINT64 ResidencyCounterFrequency;\r
} ACPI_LPI_NATIVE_CSTATE_DESCRIPTOR;\r
\r
#pragma pack()\r
#ifndef _MBR_H_\r
#define _MBR_H_\r
\r
-#define MBR_SIGNATURE 0xaa55\r
+#define MBR_SIGNATURE 0xaa55\r
\r
#define EXTENDED_DOS_PARTITION 0x05\r
#define EXTENDED_WINDOWS_PARTITION 0x0F\r
\r
-#define MAX_MBR_PARTITIONS 4\r
+#define MAX_MBR_PARTITIONS 4\r
\r
-#define PMBR_GPT_PARTITION 0xEE\r
-#define EFI_PARTITION 0xEF\r
+#define PMBR_GPT_PARTITION 0xEE\r
+#define EFI_PARTITION 0xEF\r
\r
-#define MBR_SIZE 512\r
+#define MBR_SIZE 512\r
\r
#pragma pack(1)\r
///\r
/// MBR Partition Entry\r
///\r
typedef struct {\r
- UINT8 BootIndicator;\r
- UINT8 StartHead;\r
- UINT8 StartSector;\r
- UINT8 StartTrack;\r
- UINT8 OSIndicator;\r
- UINT8 EndHead;\r
- UINT8 EndSector;\r
- UINT8 EndTrack;\r
- UINT8 StartingLBA[4];\r
- UINT8 SizeInLBA[4];\r
+ UINT8 BootIndicator;\r
+ UINT8 StartHead;\r
+ UINT8 StartSector;\r
+ UINT8 StartTrack;\r
+ UINT8 OSIndicator;\r
+ UINT8 EndHead;\r
+ UINT8 EndSector;\r
+ UINT8 EndTrack;\r
+ UINT8 StartingLBA[4];\r
+ UINT8 SizeInLBA[4];\r
} MBR_PARTITION_RECORD;\r
\r
///\r
/// MBR Partition Table\r
///\r
typedef struct {\r
- UINT8 BootStrapCode[440];\r
- UINT8 UniqueMbrSignature[4];\r
- UINT8 Unknown[2];\r
- MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];\r
- UINT16 Signature;\r
+ UINT8 BootStrapCode[440];\r
+ UINT8 UniqueMbrSignature[4];\r
+ UINT8 Unknown[2];\r
+ MBR_PARTITION_RECORD Partition[MAX_MBR_PARTITIONS];\r
+ UINT16 Signature;\r
} MASTER_BOOT_RECORD;\r
\r
#pragma pack()\r
/// a number of base address allocation structures.\r
///\r
typedef struct {\r
- UINT64 BaseAddress;\r
- UINT16 PciSegmentGroupNumber;\r
- UINT8 StartBusNumber;\r
- UINT8 EndBusNumber;\r
- UINT32 Reserved;\r
+ UINT64 BaseAddress;\r
+ UINT16 PciSegmentGroupNumber;\r
+ UINT8 StartBusNumber;\r
+ UINT8 EndBusNumber;\r
+ UINT32 Reserved;\r
} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;\r
\r
///\r
/// must be defined in a platform specific manner.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT64 Reserved;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 Reserved;\r
} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;\r
\r
///\r
0xBB983CCF, 0x151D, 0x40E1, {0xA0, 0x7B, 0x4A, 0x17, 0xBE, 0x16, 0x82, 0x92} \\r
}\r
\r
-#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock"\r
+#define MEMORY_OVERWRITE_REQUEST_CONTROL_LOCK_NAME L"MemoryOverwriteRequestControlLock"\r
\r
//\r
// VendorGuid: {BB983CCF-151D-40E1-A07B-4A17BE168292}\r
// Getting the variable returns the internal state and never exposes the key.\r
//\r
\r
-extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid;\r
+extern EFI_GUID gEfiMemoryOverwriteRequestControlLockGuid;\r
\r
#endif\r
//\r
// controller register offsets\r
//\r
-#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
-#define NVME_VER_OFFSET 0x0008 // Version\r
-#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
-#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
-#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
-#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
-#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
-#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
-#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
-#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
-#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
-#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
+#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities\r
+#define NVME_VER_OFFSET 0x0008 // Version\r
+#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set\r
+#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear\r
+#define NVME_CC_OFFSET 0x0014 // Controller Configuration\r
+#define NVME_CSTS_OFFSET 0x001c // Controller Status\r
+#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset\r
+#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes\r
+#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address\r
+#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address\r
+#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell\r
+#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell\r
\r
//\r
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))\r
// Get the doorbell stride bit shift value from the controller capabilities.\r
//\r
-#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
-#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
-\r
+#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell\r
+#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell\r
\r
#pragma pack(1)\r
\r
// 3.1.1 Offset 00h: CAP - Controller Capabilities\r
//\r
typedef struct {\r
- UINT16 Mqes; // Maximum Queue Entries Supported\r
- UINT8 Cqr:1; // Contiguous Queues Required\r
- UINT8 Ams:2; // Arbitration Mechanism Supported\r
- UINT8 Rsvd1:5;\r
- UINT8 To; // Timeout\r
- UINT16 Dstrd:4;\r
- UINT16 Nssrs:1; // NVM Subsystem Reset Supported NSSRS\r
- UINT16 Css:4; // Command Sets Supported - Bit 37\r
- UINT16 Rsvd3:7;\r
- UINT8 Mpsmin:4;\r
- UINT8 Mpsmax:4;\r
- UINT8 Rsvd4;\r
+ UINT16 Mqes; // Maximum Queue Entries Supported\r
+ UINT8 Cqr : 1; // Contiguous Queues Required\r
+ UINT8 Ams : 2; // Arbitration Mechanism Supported\r
+ UINT8 Rsvd1 : 5;\r
+ UINT8 To; // Timeout\r
+ UINT16 Dstrd : 4;\r
+ UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS\r
+ UINT16 Css : 4; // Command Sets Supported - Bit 37\r
+ UINT16 Rsvd3 : 7;\r
+ UINT8 Mpsmin : 4;\r
+ UINT8 Mpsmax : 4;\r
+ UINT8 Rsvd4;\r
} NVME_CAP;\r
\r
//\r
// 3.1.2 Offset 08h: VS - Version\r
//\r
typedef struct {\r
- UINT16 Mnr; // Minor version number\r
- UINT16 Mjr; // Major version number\r
+ UINT16 Mnr; // Minor version number\r
+ UINT16 Mjr; // Major version number\r
} NVME_VER;\r
\r
//\r
// 3.1.5 Offset 14h: CC - Controller Configuration\r
//\r
typedef struct {\r
- UINT16 En:1; // Enable\r
- UINT16 Rsvd1:3;\r
- UINT16 Css:3; // I/O Command Set Selected\r
- UINT16 Mps:4; // Memory Page Size\r
- UINT16 Ams:3; // Arbitration Mechanism Selected\r
- UINT16 Shn:2; // Shutdown Notification\r
- UINT8 Iosqes:4; // I/O Submission Queue Entry Size\r
- UINT8 Iocqes:4; // I/O Completion Queue Entry Size\r
- UINT8 Rsvd2;\r
+ UINT16 En : 1; // Enable\r
+ UINT16 Rsvd1 : 3;\r
+ UINT16 Css : 3; // I/O Command Set Selected\r
+ UINT16 Mps : 4; // Memory Page Size\r
+ UINT16 Ams : 3; // Arbitration Mechanism Selected\r
+ UINT16 Shn : 2; // Shutdown Notification\r
+ UINT8 Iosqes : 4; // I/O Submission Queue Entry Size\r
+ UINT8 Iocqes : 4; // I/O Completion Queue Entry Size\r
+ UINT8 Rsvd2;\r
} NVME_CC;\r
-#define NVME_CC_SHN_NORMAL_SHUTDOWN 1\r
-#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2\r
+#define NVME_CC_SHN_NORMAL_SHUTDOWN 1\r
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN 2\r
\r
//\r
// 3.1.6 Offset 1Ch: CSTS - Controller Status\r
//\r
typedef struct {\r
- UINT32 Rdy:1; // Ready\r
- UINT32 Cfs:1; // Controller Fatal Status\r
- UINT32 Shst:2; // Shutdown Status\r
- UINT32 Nssro:1; // NVM Subsystem Reset Occurred\r
- UINT32 Rsvd1:27;\r
+ UINT32 Rdy : 1; // Ready\r
+ UINT32 Cfs : 1; // Controller Fatal Status\r
+ UINT32 Shst : 2; // Shutdown Status\r
+ UINT32 Nssro : 1; // NVM Subsystem Reset Occurred\r
+ UINT32 Rsvd1 : 27;\r
} NVME_CSTS;\r
-#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1\r
-#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2\r
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1\r
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2\r
//\r
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes\r
//\r
typedef struct {\r
- UINT16 Asqs:12; // Submission Queue Size\r
- UINT16 Rsvd1:4;\r
- UINT16 Acqs:12; // Completion Queue Size\r
- UINT16 Rsvd2:4;\r
+ UINT16 Asqs : 12; // Submission Queue Size\r
+ UINT16 Rsvd1 : 4;\r
+ UINT16 Acqs : 12; // Completion Queue Size\r
+ UINT16 Rsvd2 : 4;\r
} NVME_AQA;\r
\r
//\r
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address\r
//\r
-#define NVME_ASQ UINT64\r
+#define NVME_ASQ UINT64\r
//\r
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address\r
//\r
-#define NVME_ACQ UINT64\r
+#define NVME_ACQ UINT64\r
\r
//\r
// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell\r
//\r
typedef struct {\r
- UINT16 Sqt;\r
- UINT16 Rsvd1;\r
+ UINT16 Sqt;\r
+ UINT16 Rsvd1;\r
} NVME_SQTDBL;\r
\r
//\r
// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell\r
//\r
typedef struct {\r
- UINT16 Cqh;\r
- UINT16 Rsvd1;\r
+ UINT16 Cqh;\r
+ UINT16 Rsvd1;\r
} NVME_CQHDBL;\r
\r
//\r
//\r
// CDW 10, 11\r
//\r
- UINT64 Slba; /* Starting Sector Address */\r
+ UINT64 Slba; /* Starting Sector Address */\r
//\r
// CDW 12\r
//\r
- UINT16 Nlb; /* Number of Sectors */\r
- UINT16 Rsvd1:10;\r
- UINT16 Prinfo:4; /* Protection Info Check */\r
- UINT16 Fua:1; /* Force Unit Access */\r
- UINT16 Lr:1; /* Limited Retry */\r
+ UINT16 Nlb; /* Number of Sectors */\r
+ UINT16 Rsvd1 : 10;\r
+ UINT16 Prinfo : 4; /* Protection Info Check */\r
+ UINT16 Fua : 1; /* Force Unit Access */\r
+ UINT16 Lr : 1; /* Limited Retry */\r
//\r
// CDW 13\r
//\r
- UINT32 Af:4; /* Access Frequency */\r
- UINT32 Al:2; /* Access Latency */\r
- UINT32 Sr:1; /* Sequential Request */\r
- UINT32 In:1; /* Incompressible */\r
- UINT32 Rsvd2:24;\r
+ UINT32 Af : 4; /* Access Frequency */\r
+ UINT32 Al : 2; /* Access Latency */\r
+ UINT32 Sr : 1; /* Sequential Request */\r
+ UINT32 In : 1; /* Incompressible */\r
+ UINT32 Rsvd2 : 24;\r
//\r
// CDW 14\r
//\r
- UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
//\r
// CDW 15\r
//\r
- UINT16 Elbat; /* Expected Logical Block Application Tag */\r
- UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
+ UINT16 Elbat; /* Expected Logical Block Application Tag */\r
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
} NVME_READ;\r
\r
//\r
//\r
// CDW 10, 11\r
//\r
- UINT64 Slba; /* Starting Sector Address */\r
+ UINT64 Slba; /* Starting Sector Address */\r
//\r
// CDW 12\r
//\r
- UINT16 Nlb; /* Number of Sectors */\r
- UINT16 Rsvd1:10;\r
- UINT16 Prinfo:4; /* Protection Info Check */\r
- UINT16 Fua:1; /* Force Unit Access */\r
- UINT16 Lr:1; /* Limited Retry */\r
+ UINT16 Nlb; /* Number of Sectors */\r
+ UINT16 Rsvd1 : 10;\r
+ UINT16 Prinfo : 4; /* Protection Info Check */\r
+ UINT16 Fua : 1; /* Force Unit Access */\r
+ UINT16 Lr : 1; /* Limited Retry */\r
//\r
// CDW 13\r
//\r
- UINT32 Af:4; /* Access Frequency */\r
- UINT32 Al:2; /* Access Latency */\r
- UINT32 Sr:1; /* Sequential Request */\r
- UINT32 In:1; /* Incompressible */\r
- UINT32 Rsvd2:24;\r
+ UINT32 Af : 4; /* Access Frequency */\r
+ UINT32 Al : 2; /* Access Latency */\r
+ UINT32 Sr : 1; /* Sequential Request */\r
+ UINT32 In : 1; /* Incompressible */\r
+ UINT32 Rsvd2 : 24;\r
//\r
// CDW 14\r
//\r
- UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
//\r
// CDW 15\r
//\r
- UINT16 Lbat; /* Logical Block Application Tag */\r
- UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
+ UINT16 Lbat; /* Logical Block Application Tag */\r
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
} NVME_WRITE;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Flush; /* Flush */\r
+ UINT32 Flush; /* Flush */\r
} NVME_FLUSH;\r
\r
//\r
//\r
// CDW 10, 11\r
//\r
- UINT64 Slba; /* Starting LBA */\r
+ UINT64 Slba; /* Starting LBA */\r
//\r
// CDW 12\r
//\r
- UINT32 Nlb:16; /* Number of Logical Blocks */\r
- UINT32 Rsvd1:16;\r
+ UINT32 Nlb : 16; /* Number of Logical Blocks */\r
+ UINT32 Rsvd1 : 16;\r
} NVME_WRITE_UNCORRECTABLE;\r
\r
//\r
//\r
// CDW 10, 11\r
//\r
- UINT64 Slba; /* Starting LBA */\r
+ UINT64 Slba; /* Starting LBA */\r
//\r
// CDW 12\r
//\r
- UINT16 Nlb; /* Number of Logical Blocks */\r
- UINT16 Rsvd1:10;\r
- UINT16 Prinfo:4; /* Protection Info Check */\r
- UINT16 Fua:1; /* Force Unit Access */\r
- UINT16 Lr:1; /* Limited Retry */\r
+ UINT16 Nlb; /* Number of Logical Blocks */\r
+ UINT16 Rsvd1 : 10;\r
+ UINT16 Prinfo : 4; /* Protection Info Check */\r
+ UINT16 Fua : 1; /* Force Unit Access */\r
+ UINT16 Lr : 1; /* Limited Retry */\r
//\r
// CDW 13\r
//\r
- UINT32 Rsvd2;\r
+ UINT32 Rsvd2;\r
//\r
// CDW 14\r
//\r
- UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
+ UINT32 Ilbrt; /* Initial Logical Block Reference Tag */\r
//\r
// CDW 15\r
//\r
- UINT16 Lbat; /* Logical Block Application Tag */\r
- UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
+ UINT16 Lbat; /* Logical Block Application Tag */\r
+ UINT16 Lbatm; /* Logical Block Application Tag Mask */\r
} NVME_WRITE_ZEROES;\r
\r
//\r
//\r
// CDW 10, 11\r
//\r
- UINT64 Slba; /* Starting LBA */\r
+ UINT64 Slba; /* Starting LBA */\r
//\r
// CDW 12\r
//\r
- UINT16 Nlb; /* Number of Logical Blocks */\r
- UINT16 Rsvd1:10;\r
- UINT16 Prinfo:4; /* Protection Info Check */\r
- UINT16 Fua:1; /* Force Unit Access */\r
- UINT16 Lr:1; /* Limited Retry */\r
+ UINT16 Nlb; /* Number of Logical Blocks */\r
+ UINT16 Rsvd1 : 10;\r
+ UINT16 Prinfo : 4; /* Protection Info Check */\r
+ UINT16 Fua : 1; /* Force Unit Access */\r
+ UINT16 Lr : 1; /* Limited Retry */\r
//\r
// CDW 13\r
//\r
- UINT32 Rsvd2;\r
+ UINT32 Rsvd2;\r
//\r
// CDW 14\r
//\r
- UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
+ UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */\r
//\r
// CDW 15\r
//\r
- UINT16 Elbat; /* Expected Logical Block Application Tag */\r
- UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
+ UINT16 Elbat; /* Expected Logical Block Application Tag */\r
+ UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */\r
} NVME_COMPARE;\r
\r
typedef union {\r
} NVME_CMD;\r
\r
typedef struct {\r
- UINT16 Mp; /* Maximum Power */\r
- UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Mps:1; /* Max Power Scale */\r
- UINT8 Nops:1; /* Non-Operational State */\r
- UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT32 Enlat; /* Entry Latency */\r
- UINT32 Exlat; /* Exit Latency */\r
- UINT8 Rrt:5; /* Relative Read Throughput */\r
- UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rrl:5; /* Relative Read Latency */\r
- UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rwt:5; /* Relative Write Throughput */\r
- UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rwl:5; /* Relative Write Latency */\r
- UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT16 Mp; /* Maximum Power */\r
+ UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Mps : 1; /* Max Power Scale */\r
+ UINT8 Nops : 1; /* Non-Operational State */\r
+ UINT8 Rsvd2 : 6; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Enlat; /* Entry Latency */\r
+ UINT32 Exlat; /* Exit Latency */\r
+ UINT8 Rrt : 5; /* Relative Read Throughput */\r
+ UINT8 Rsvd3 : 3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rrl : 5; /* Relative Read Latency */\r
+ UINT8 Rsvd4 : 3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rwt : 5; /* Relative Write Throughput */\r
+ UINT8 Rsvd5 : 3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rwl : 5; /* Relative Write Latency */\r
+ UINT8 Rsvd6 : 3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_PSDESCRIPTOR;\r
\r
//\r
//\r
// Controller Capabilities and Features 0-255\r
//\r
- UINT16 Vid; /* PCI Vendor ID */\r
- UINT16 Ssvid; /* PCI sub-system vendor ID */\r
- UINT8 Sn[20]; /* Product serial number */\r
+ UINT16 Vid; /* PCI Vendor ID */\r
+ UINT16 Ssvid; /* PCI sub-system vendor ID */\r
+ UINT8 Sn[20]; /* Product serial number */\r
\r
- UINT8 Mn[40]; /* Product model number */\r
- UINT8 Fr[8]; /* Firmware Revision */\r
- UINT8 Rab; /* Recommended Arbitration Burst */\r
- UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
- UINT8 Cmic; /* Multi-interface Capabilities */\r
- UINT8 Mdts; /* Maximum Data Transfer Size */\r
- UINT8 Cntlid[2]; /* Controller ID */\r
- UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Mn[40]; /* Product model number */\r
+ UINT8 Fr[8]; /* Firmware Revision */\r
+ UINT8 Rab; /* Recommended Arbitration Burst */\r
+ UINT8 Ieee_oui[3]; /* Organization Unique Identifier */\r
+ UINT8 Cmic; /* Multi-interface Capabilities */\r
+ UINT8 Mdts; /* Maximum Data Transfer Size */\r
+ UINT8 Cntlid[2]; /* Controller ID */\r
+ UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */\r
//\r
// Admin Command Set Attributes\r
//\r
- UINT16 Oacs; /* Optional Admin Command Support */\r
- #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3\r
- #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2\r
- #define FORMAT_NVM_SUPPORTED BIT1\r
- #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
- UINT8 Acl; /* Abort Command Limit */\r
- UINT8 Aerl; /* Async Event Request Limit */\r
- UINT8 Frmw; /* Firmware updates */\r
- UINT8 Lpa; /* Log Page Attributes */\r
- UINT8 Elpe; /* Error Log Page Entries */\r
- UINT8 Npss; /* Number of Power States Support */\r
- UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
- UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
+ UINT16 Oacs; /* Optional Admin Command Support */\r
+ #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3\r
+ #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2\r
+ #define FORMAT_NVM_SUPPORTED BIT1\r
+ #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0\r
+ UINT8 Acl; /* Abort Command Limit */\r
+ UINT8 Aerl; /* Async Event Request Limit */\r
+ UINT8 Frmw; /* Firmware updates */\r
+ UINT8 Lpa; /* Log Page Attributes */\r
+ UINT8 Elpe; /* Error Log Page Entries */\r
+ UINT8 Npss; /* Number of Power States Support */\r
+ UINT8 Avscc; /* Admin Vendor Specific Command Configuration */\r
+ UINT8 Apsta; /* Autonomous Power State Transition Attributes */\r
//\r
// Below fields before Rsvd2 are defined in NVM Express 1.3 Spec\r
//\r
- UINT16 Wctemp; /* Warning Composite Temperature Threshold */\r
- UINT16 Cctemp; /* Critical Composite Temperature Threshold */\r
- UINT16 Mtfa; /* Maximum Time for Firmware Activation */\r
- UINT32 Hmpre; /* Host Memory Buffer Preferred Size */\r
- UINT32 Hmmin; /* Host Memory Buffer Minimum Size */\r
- UINT8 Tnvmcap[16]; /* Total NVM Capacity */\r
- UINT8 Rsvd2[216]; /* Reserved as of NVM Express */\r
+ UINT16 Wctemp; /* Warning Composite Temperature Threshold */\r
+ UINT16 Cctemp; /* Critical Composite Temperature Threshold */\r
+ UINT16 Mtfa; /* Maximum Time for Firmware Activation */\r
+ UINT32 Hmpre; /* Host Memory Buffer Preferred Size */\r
+ UINT32 Hmmin; /* Host Memory Buffer Minimum Size */\r
+ UINT8 Tnvmcap[16]; /* Total NVM Capacity */\r
+ UINT8 Rsvd2[216]; /* Reserved as of NVM Express */\r
//\r
// NVM Command Set Attributes\r
//\r
- UINT8 Sqes; /* Submission Queue Entry Size */\r
- UINT8 Cqes; /* Completion Queue Entry Size */\r
- UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT32 Nn; /* Number of Namespaces */\r
- UINT16 Oncs; /* Optional NVM Command Support */\r
- UINT16 Fuses; /* Fused Operation Support */\r
- UINT8 Fna; /* Format NVM Attributes */\r
- UINT8 Vwc; /* Volatile Write Cache */\r
- UINT16 Awun; /* Atomic Write Unit Normal */\r
- UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
- UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
- UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT16 Acwu; /* Atomic Compare & Write Unit */\r
- UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT32 Sgls; /* SGL Support */\r
- UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Sqes; /* Submission Queue Entry Size */\r
+ UINT8 Cqes; /* Completion Queue Entry Size */\r
+ UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Nn; /* Number of Namespaces */\r
+ UINT16 Oncs; /* Optional NVM Command Support */\r
+ UINT16 Fuses; /* Fused Operation Support */\r
+ UINT8 Fna; /* Format NVM Attributes */\r
+ UINT8 Vwc; /* Volatile Write Cache */\r
+ UINT16 Awun; /* Atomic Write Unit Normal */\r
+ UINT16 Awupf; /* Atomic Write Unit Power Fail */\r
+ UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */\r
+ UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT16 Acwu; /* Atomic Compare & Write Unit */\r
+ UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Sgls; /* SGL Support */\r
+ UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */\r
//\r
// I/O Command set Attributes\r
//\r
- UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */\r
//\r
// Power State Descriptors\r
//\r
- NVME_PSDESCRIPTOR PsDescriptor[32];\r
+ NVME_PSDESCRIPTOR PsDescriptor[32];\r
\r
- UINT8 VendorData[1024]; /* Vendor specific data */\r
+ UINT8 VendorData[1024]; /* Vendor specific data */\r
} NVME_ADMIN_CONTROLLER_DATA;\r
\r
typedef struct {\r
- UINT16 Ms; /* Metadata Size */\r
- UINT8 Lbads; /* LBA Data Size */\r
- UINT8 Rp:2; /* Relative Performance */\r
- #define LBAF_RP_BEST 00b\r
- #define LBAF_RP_BETTER 01b\r
- #define LBAF_RP_GOOD 10b\r
- #define LBAF_RP_DEGRADED 11b\r
- UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT16 Ms; /* Metadata Size */\r
+ UINT8 Lbads; /* LBA Data Size */\r
+ UINT8 Rp : 2; /* Relative Performance */\r
+ #define LBAF_RP_BEST 00b\r
+ #define LBAF_RP_BETTER 01b\r
+ #define LBAF_RP_GOOD 10b\r
+ #define LBAF_RP_DEGRADED 11b\r
+ UINT8 Rsvd1 : 6; /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_LBAFORMAT;\r
\r
//\r
//\r
// NVM Command Set Specific\r
//\r
- UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
- UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
- UINT64 Nuse; /* Namespace Utilization */\r
- UINT8 Nsfeat; /* Namespace Features */\r
- UINT8 Nlbaf; /* Number of LBA Formats */\r
- UINT8 Flbas; /* Formatted LBA size */\r
- UINT8 Mc; /* Metadata Capabilities */\r
- UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
- UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
- UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
- UINT8 Rescap; /* Reservation Capabilities */\r
- UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
+ UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */\r
+ UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */\r
+ UINT64 Nuse; /* Namespace Utilization */\r
+ UINT8 Nsfeat; /* Namespace Features */\r
+ UINT8 Nlbaf; /* Number of LBA Formats */\r
+ UINT8 Flbas; /* Formatted LBA size */\r
+ UINT8 Mc; /* Metadata Capabilities */\r
+ UINT8 Dpc; /* End-to-end Data Protection capabilities */\r
+ UINT8 Dps; /* End-to-end Data Protection Type Settings */\r
+ UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */\r
+ UINT8 Rescap; /* Reservation Capabilities */\r
+ UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT64 Eui64; /* IEEE Extended Unique Identifier */\r
//\r
// LBA Format\r
//\r
- NVME_LBAFORMAT LbaFormat[16];\r
+ NVME_LBAFORMAT LbaFormat[16];\r
\r
- UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT8 VendorData[3712]; /* Vendor specific data */\r
+ UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT8 VendorData[3712]; /* Vendor specific data */\r
} NVME_ADMIN_NAMESPACE_DATA;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Cns:2;\r
- UINT32 Rsvd1:30;\r
+ UINT32 Cns : 2;\r
+ UINT32 Rsvd1 : 30;\r
} NVME_ADMIN_IDENTIFY;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Qid:16; /* Queue Identifier */\r
- UINT32 Qsize:16; /* Queue Size */\r
+ UINT32 Qid : 16; /* Queue Identifier */\r
+ UINT32 Qsize : 16; /* Queue Size */\r
\r
//\r
// CDW 11\r
//\r
- UINT32 Pc:1; /* Physically Contiguous */\r
- UINT32 Ien:1; /* Interrupts Enabled */\r
- UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */\r
- UINT32 Iv:16; /* Interrupt Vector for MSI-X or MSI*/\r
+ UINT32 Pc : 1; /* Physically Contiguous */\r
+ UINT32 Ien : 1; /* Interrupts Enabled */\r
+ UINT32 Rsvd1 : 14; /* reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Iv : 16; /* Interrupt Vector for MSI-X or MSI*/\r
} NVME_ADMIN_CRIOCQ;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Qid:16; /* Queue Identifier */\r
- UINT32 Qsize:16; /* Queue Size */\r
+ UINT32 Qid : 16; /* Queue Identifier */\r
+ UINT32 Qsize : 16; /* Queue Size */\r
\r
//\r
// CDW 11\r
//\r
- UINT32 Pc:1; /* Physically Contiguous */\r
- UINT32 Qprio:2; /* Queue Priority */\r
- UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */\r
- UINT32 Cqid:16; /* Completion Queue ID */\r
+ UINT32 Pc : 1; /* Physically Contiguous */\r
+ UINT32 Qprio : 2; /* Queue Priority */\r
+ UINT32 Rsvd1 : 13; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Cqid : 16; /* Completion Queue ID */\r
} NVME_ADMIN_CRIOSQ;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT16 Qid;\r
- UINT16 Rsvd1;\r
+ UINT16 Qid;\r
+ UINT16 Rsvd1;\r
} NVME_ADMIN_DEIOCQ;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT16 Qid;\r
- UINT16 Rsvd1;\r
+ UINT16 Qid;\r
+ UINT16 Rsvd1;\r
} NVME_ADMIN_DEIOSQ;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Sqid:16; /* Submission Queue identifier */\r
- UINT32 Cid:16; /* Command Identifier */\r
+ UINT32 Sqid : 16; /* Submission Queue identifier */\r
+ UINT32 Cid : 16; /* Command Identifier */\r
} NVME_ADMIN_ABORT;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Fs:3; /* Submission Queue identifier */\r
- UINT32 Aa:2; /* Command Identifier */\r
- UINT32 Rsvd1:27;\r
+ UINT32 Fs : 3; /* Submission Queue identifier */\r
+ UINT32 Aa : 2; /* Command Identifier */\r
+ UINT32 Rsvd1 : 27;\r
} NVME_ADMIN_FIRMWARE_ACTIVATE;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Numd; /* Number of Dwords */\r
+ UINT32 Numd; /* Number of Dwords */\r
//\r
// CDW 11\r
//\r
- UINT32 Ofst; /* Offset */\r
+ UINT32 Ofst; /* Offset */\r
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Fid:8; /* Feature Identifier */\r
- UINT32 Sel:3; /* Select */\r
- UINT32 Rsvd1:21;\r
+ UINT32 Fid : 8; /* Feature Identifier */\r
+ UINT32 Sel : 3; /* Select */\r
+ UINT32 Rsvd1 : 21;\r
} NVME_ADMIN_GET_FEATURES;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Lid:8; /* Log Page Identifier */\r
- #define LID_ERROR_INFO 0x1\r
- #define LID_SMART_INFO 0x2\r
- #define LID_FW_SLOT_INFO 0x3\r
- UINT32 Rsvd1:8;\r
- UINT32 Numd:12; /* Number of Dwords */\r
- UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */\r
+ UINT32 Lid : 8; /* Log Page Identifier */\r
+ #define LID_ERROR_INFO 0x1\r
+ #define LID_SMART_INFO 0x2\r
+ #define LID_FW_SLOT_INFO 0x3\r
+ UINT32 Rsvd1 : 8;\r
+ UINT32 Numd : 12; /* Number of Dwords */\r
+ UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */\r
} NVME_ADMIN_GET_LOG_PAGE;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Fid:8; /* Feature Identifier */\r
- UINT32 Rsvd1:23;\r
- UINT32 Sv:1; /* Save */\r
+ UINT32 Fid : 8; /* Feature Identifier */\r
+ UINT32 Rsvd1 : 23;\r
+ UINT32 Sv : 1; /* Save */\r
} NVME_ADMIN_SET_FEATURES;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Lbaf:4; /* LBA Format */\r
- UINT32 Ms:1; /* Metadata Settings */\r
- UINT32 Pi:3; /* Protection Information */\r
- UINT32 Pil:1; /* Protection Information Location */\r
- UINT32 Ses:3; /* Secure Erase Settings */\r
- UINT32 Rsvd1:20;\r
+ UINT32 Lbaf : 4; /* LBA Format */\r
+ UINT32 Ms : 1; /* Metadata Settings */\r
+ UINT32 Pi : 3; /* Protection Information */\r
+ UINT32 Pil : 1; /* Protection Information Location */\r
+ UINT32 Ses : 3; /* Secure Erase Settings */\r
+ UINT32 Rsvd1 : 20;\r
} NVME_ADMIN_FORMAT_NVM;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Rsvd1:8;\r
- UINT32 Spsp:16; /* SP Specific */\r
- UINT32 Secp:8; /* Security Protocol */\r
+ UINT32 Rsvd1 : 8;\r
+ UINT32 Spsp : 16; /* SP Specific */\r
+ UINT32 Secp : 8; /* Security Protocol */\r
//\r
// CDW 11\r
//\r
- UINT32 Al; /* Allocation Length */\r
+ UINT32 Al; /* Allocation Length */\r
} NVME_ADMIN_SECURITY_RECEIVE;\r
\r
//\r
//\r
// CDW 10\r
//\r
- UINT32 Rsvd1:8;\r
- UINT32 Spsp:16; /* SP Specific */\r
- UINT32 Secp:8; /* Security Protocol */\r
+ UINT32 Rsvd1 : 8;\r
+ UINT32 Spsp : 16; /* SP Specific */\r
+ UINT32 Secp : 8; /* Security Protocol */\r
//\r
// CDW 11\r
//\r
- UINT32 Tl; /* Transfer Length */\r
+ UINT32 Tl; /* Transfer Length */\r
} NVME_ADMIN_SECURITY_SEND;\r
\r
typedef union {\r
} NVME_ADMIN_CMD;\r
\r
typedef struct {\r
- UINT32 Cdw10;\r
- UINT32 Cdw11;\r
- UINT32 Cdw12;\r
- UINT32 Cdw13;\r
- UINT32 Cdw14;\r
- UINT32 Cdw15;\r
+ UINT32 Cdw10;\r
+ UINT32 Cdw11;\r
+ UINT32 Cdw12;\r
+ UINT32 Cdw13;\r
+ UINT32 Cdw14;\r
+ UINT32 Cdw15;\r
} NVME_RAW;\r
\r
typedef union {\r
- NVME_ADMIN_CMD Admin; // Union of Admin commands\r
- NVME_CMD Nvm; // Union of Nvm commands\r
- NVME_RAW Raw;\r
+ NVME_ADMIN_CMD Admin; // Union of Admin commands\r
+ NVME_CMD Nvm; // Union of Nvm commands\r
+ NVME_RAW Raw;\r
} NVME_PAYLOAD;\r
\r
//\r
//\r
// CDW 0, Common to all commands\r
//\r
- UINT8 Opc; // Opcode\r
- UINT8 Fuse:2; // Fused Operation\r
- UINT8 Rsvd1:5;\r
- UINT8 Psdt:1; // PRP or SGL for Data Transfer\r
- UINT16 Cid; // Command Identifier\r
+ UINT8 Opc; // Opcode\r
+ UINT8 Fuse : 2; // Fused Operation\r
+ UINT8 Rsvd1 : 5;\r
+ UINT8 Psdt : 1; // PRP or SGL for Data Transfer\r
+ UINT16 Cid; // Command Identifier\r
\r
//\r
// CDW 1\r
//\r
- UINT32 Nsid; // Namespace Identifier\r
+ UINT32 Nsid; // Namespace Identifier\r
\r
//\r
// CDW 2,3\r
//\r
- UINT64 Rsvd2;\r
+ UINT64 Rsvd2;\r
\r
//\r
// CDW 4,5\r
//\r
- UINT64 Mptr; // Metadata Pointer\r
+ UINT64 Mptr; // Metadata Pointer\r
\r
//\r
// CDW 6-9\r
//\r
- UINT64 Prp[2]; // First and second PRP entries\r
-\r
- NVME_PAYLOAD Payload;\r
+ UINT64 Prp[2]; // First and second PRP entries\r
\r
+ NVME_PAYLOAD Payload;\r
} NVME_SQ;\r
\r
//\r
//\r
// CDW 0\r
//\r
- UINT32 Dword0;\r
+ UINT32 Dword0;\r
//\r
// CDW 1\r
//\r
- UINT32 Rsvd1;\r
+ UINT32 Rsvd1;\r
//\r
// CDW 2\r
//\r
- UINT16 Sqhd; // Submission Queue Head Pointer\r
- UINT16 Sqid; // Submission Queue Identifier\r
+ UINT16 Sqhd; // Submission Queue Head Pointer\r
+ UINT16 Sqid; // Submission Queue Identifier\r
//\r
// CDW 3\r
//\r
- UINT16 Cid; // Command Identifier\r
- UINT16 Pt:1; // Phase Tag\r
- UINT16 Sc:8; // Status Code\r
- UINT16 Sct:3; // Status Code Type\r
- UINT16 Rsvd2:2;\r
- UINT16 Mo:1; // More\r
- UINT16 Dnr:1; // Do Not Retry\r
+ UINT16 Cid; // Command Identifier\r
+ UINT16 Pt : 1; // Phase Tag\r
+ UINT16 Sc : 8; // Status Code\r
+ UINT16 Sct : 3; // Status Code Type\r
+ UINT16 Rsvd2 : 2;\r
+ UINT16 Mo : 1; // More\r
+ UINT16 Dnr : 1; // Do Not Retry\r
} NVME_CQ;\r
\r
//\r
// Nvm Express Admin cmd opcodes\r
//\r
-#define NVME_ADMIN_DEIOSQ_CMD 0x00\r
-#define NVME_ADMIN_CRIOSQ_CMD 0x01\r
-#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02\r
-#define NVME_ADMIN_DEIOCQ_CMD 0x04\r
-#define NVME_ADMIN_CRIOCQ_CMD 0x05\r
-#define NVME_ADMIN_IDENTIFY_CMD 0x06\r
-#define NVME_ADMIN_ABORT_CMD 0x08\r
-#define NVME_ADMIN_SET_FEATURES_CMD 0x09\r
-#define NVME_ADMIN_GET_FEATURES_CMD 0x0A\r
-#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C\r
-#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D\r
-#define NVME_ADMIN_FW_COMMIT_CMD 0x10\r
-#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11\r
-#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15\r
-#define NVME_ADMIN_FORMAT_NVM_CMD 0x80\r
-#define NVME_ADMIN_SECURITY_SEND_CMD 0x81\r
-#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82\r
-\r
-#define NVME_IO_FLUSH_OPC 0\r
-#define NVME_IO_WRITE_OPC 1\r
-#define NVME_IO_READ_OPC 2\r
+#define NVME_ADMIN_DEIOSQ_CMD 0x00\r
+#define NVME_ADMIN_CRIOSQ_CMD 0x01\r
+#define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02\r
+#define NVME_ADMIN_DEIOCQ_CMD 0x04\r
+#define NVME_ADMIN_CRIOCQ_CMD 0x05\r
+#define NVME_ADMIN_IDENTIFY_CMD 0x06\r
+#define NVME_ADMIN_ABORT_CMD 0x08\r
+#define NVME_ADMIN_SET_FEATURES_CMD 0x09\r
+#define NVME_ADMIN_GET_FEATURES_CMD 0x0A\r
+#define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C\r
+#define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D\r
+#define NVME_ADMIN_FW_COMMIT_CMD 0x10\r
+#define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11\r
+#define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15\r
+#define NVME_ADMIN_FORMAT_NVM_CMD 0x80\r
+#define NVME_ADMIN_SECURITY_SEND_CMD 0x81\r
+#define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82\r
+\r
+#define NVME_IO_FLUSH_OPC 0\r
+#define NVME_IO_WRITE_OPC 1\r
+#define NVME_IO_READ_OPC 2\r
\r
typedef enum {\r
DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,\r
CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,\r
- GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,\r
+ GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,\r
DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,\r
CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,\r
- IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,\r
- AbortOpcode = NVME_ADMIN_ABORT_CMD,\r
- SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,\r
- GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,\r
- AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,\r
- NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,\r
- FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,\r
- FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,\r
- NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,\r
- FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,\r
- SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,\r
- SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD\r
+ IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,\r
+ AbortOpcode = NVME_ADMIN_ABORT_CMD,\r
+ SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,\r
+ GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,\r
+ AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,\r
+ NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,\r
+ FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,\r
+ FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,\r
+ NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,\r
+ FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,\r
+ SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,\r
+ SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD\r
} NVME_ADMIN_COMMAND_OPCODE;\r
\r
//\r
// (ref. spec. v1.1 figure 82).\r
//\r
typedef enum {\r
-IdentifyNamespaceCns = 0x0,\r
-IdentifyControllerCns = 0x1,\r
-IdentifyActiveNsListCns = 0x2\r
+ IdentifyNamespaceCns = 0x0,\r
+ IdentifyControllerCns = 0x1,\r
+ IdentifyActiveNsListCns = 0x2\r
} NVME_ADMIN_IDENTIFY_CNS;\r
\r
//\r
// (ref. spec. 1.1 figure 60).\r
//\r
typedef enum {\r
- ActivateActionReplace = 0x0,\r
+ ActivateActionReplace = 0x0,\r
ActivateActionReplaceActivate = 0x1,\r
- ActivateActionActivate = 0x2\r
+ ActivateActionActivate = 0x2\r
} NVME_FW_ACTIVATE_ACTION;\r
\r
//\r
//\r
typedef enum {\r
FirmwareSlotCtrlChooses = 0x0,\r
- FirmwareSlot1 = 0x1,\r
- FirmwareSlot2 = 0x2,\r
- FirmwareSlot3 = 0x3,\r
- FirmwareSlot4 = 0x4,\r
- FirmwareSlot5 = 0x5,\r
- FirmwareSlot6 = 0x6,\r
- FirmwareSlot7 = 0x7\r
+ FirmwareSlot1 = 0x1,\r
+ FirmwareSlot2 = 0x2,\r
+ FirmwareSlot3 = 0x3,\r
+ FirmwareSlot4 = 0x4,\r
+ FirmwareSlot5 = 0x5,\r
+ FirmwareSlot6 = 0x6,\r
+ FirmwareSlot7 = 0x7\r
} NVME_FW_ACTIVATE_SLOT;\r
\r
//\r
// (ref. spec. v1.1 Figure 73).\r
//\r
typedef enum {\r
- ErrorInfoLogID = LID_ERROR_INFO,\r
- SmartHealthInfoLogID = LID_SMART_INFO,\r
+ ErrorInfoLogID = LID_ERROR_INFO,\r
+ SmartHealthInfoLogID = LID_SMART_INFO,\r
FirmwareSlotInfoLogID = LID_FW_SLOT_INFO\r
} NVME_LOG_ID;\r
\r
//\r
// Indicates the firmware slot from which the actively running firmware revision was loaded.\r
//\r
- UINT8 ActivelyRunningFwSlot:3;\r
- UINT8 :1;\r
+ UINT8 ActivelyRunningFwSlot : 3;\r
+ UINT8 : 1;\r
//\r
// Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.\r
//\r
- UINT8 NextActiveFwSlot:3;\r
- UINT8 :1;\r
+ UINT8 NextActiveFwSlot : 3;\r
+ UINT8 : 1;\r
} NVME_ACTIVE_FW_INFO;\r
\r
//\r
typedef struct {\r
//\r
// Specifies information about the active firmware revision.\r
- //s\r
- NVME_ACTIVE_FW_INFO ActiveFwInfo;\r
- UINT8 Reserved1[7];\r
+ // s\r
+ NVME_ACTIVE_FW_INFO ActiveFwInfo;\r
+ UINT8 Reserved1[7];\r
//\r
// Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.\r
//\r
- CHAR8 FwRevisionSlot[7][8];\r
- UINT8 Reserved2[448];\r
+ CHAR8 FwRevisionSlot[7][8];\r
+ UINT8 Reserved2[448];\r
} NVME_FW_SLOT_INFO_LOG;\r
\r
//\r
//\r
// This field indicates critical warnings for the state of the controller.\r
//\r
- UINT8 CriticalWarningAvailableSpare:1;\r
- UINT8 CriticalWarningTemperature:1;\r
- UINT8 CriticalWarningReliability:1;\r
- UINT8 CriticalWarningMediaReadOnly:1;\r
- UINT8 CriticalWarningVolatileBackup:1;\r
- UINT8 CriticalWarningReserved:3;\r
+ UINT8 CriticalWarningAvailableSpare : 1;\r
+ UINT8 CriticalWarningTemperature : 1;\r
+ UINT8 CriticalWarningReliability : 1;\r
+ UINT8 CriticalWarningMediaReadOnly : 1;\r
+ UINT8 CriticalWarningVolatileBackup : 1;\r
+ UINT8 CriticalWarningReserved : 3;\r
//\r
// Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.\r
//\r
- UINT16 CompositeTemp;\r
+ UINT16 CompositeTemp;\r
//\r
// Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.\r
//\r
- UINT8 AvailableSpare;\r
+ UINT8 AvailableSpare;\r
//\r
// When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).\r
//\r
- UINT8 AvailableSpareThreshold;\r
+ UINT8 AvailableSpareThreshold;\r
//\r
// Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).\r
//\r
- UINT8 PercentageUsed;\r
- UINT8 Reserved1[26];\r
+ UINT8 PercentageUsed;\r
+ UINT8 Reserved1[26];\r
//\r
// Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.\r
//\r
- UINT8 DataUnitsRead[16];\r
+ UINT8 DataUnitsRead[16];\r
//\r
// Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.\r
//\r
- UINT8 DataUnitsWritten[16];\r
+ UINT8 DataUnitsWritten[16];\r
//\r
// Contains the number of read commands completed by the controller.\r
//\r
- UINT8 HostReadCommands[16];\r
+ UINT8 HostReadCommands[16];\r
//\r
// Contains the number of write commands completed by the controller.\r
//\r
- UINT8 HostWriteCommands[16];\r
+ UINT8 HostWriteCommands[16];\r
//\r
// Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.\r
//\r
- UINT8 ControllerBusyTime[16];\r
+ UINT8 ControllerBusyTime[16];\r
//\r
// Contains the number of power cycles.\r
//\r
- UINT8 PowerCycles[16];\r
+ UINT8 PowerCycles[16];\r
//\r
// Contains the number of power-on hours.\r
//\r
- UINT8 PowerOnHours[16];\r
+ UINT8 PowerOnHours[16];\r
//\r
// Contains the number of unsafe shutdowns.\r
//\r
- UINT8 UnsafeShutdowns[16];\r
+ UINT8 UnsafeShutdowns[16];\r
//\r
// Contains the number of occurrences where the controller detected an unrecovered data integrity error.\r
//\r
- UINT8 MediaAndDataIntegrityErrors[16];\r
+ UINT8 MediaAndDataIntegrityErrors[16];\r
//\r
// Contains the number of Error Information log entries over the life of the controller.\r
//\r
- UINT8 NumberErrorInformationLogEntries[16];\r
+ UINT8 NumberErrorInformationLogEntries[16];\r
//\r
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
//\r
- UINT32 WarningCompositeTemperatureTime;\r
+ UINT32 WarningCompositeTemperatureTime;\r
//\r
// Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.\r
//\r
- UINT32 CriticalCompositeTemperatureTime;\r
+ UINT32 CriticalCompositeTemperatureTime;\r
//\r
// Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.\r
//\r
- UINT16 TemperatureSensor[8];\r
- UINT8 Reserved2[296];\r
+ UINT16 TemperatureSensor[8];\r
+ UINT8 Reserved2[296];\r
} NVME_SMART_HEALTH_INFO_LOG;\r
\r
#pragma pack()\r
/// Section 6.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 Command;\r
- UINT16 Status;\r
- UINT8 RevisionID;\r
- UINT8 ClassCode[3];\r
- UINT8 CacheLineSize;\r
- UINT8 LatencyTimer;\r
- UINT8 HeaderType;\r
- UINT8 BIST;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT8 RevisionID;\r
+ UINT8 ClassCode[3];\r
+ UINT8 CacheLineSize;\r
+ UINT8 LatencyTimer;\r
+ UINT8 HeaderType;\r
+ UINT8 BIST;\r
} PCI_DEVICE_INDEPENDENT_REGION;\r
\r
///\r
/// Section 6.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- UINT32 Bar[6];\r
- UINT32 CISPtr;\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemID;\r
- UINT32 ExpansionRomBar;\r
- UINT8 CapabilityPtr;\r
- UINT8 Reserved1[3];\r
- UINT32 Reserved2;\r
- UINT8 InterruptLine;\r
- UINT8 InterruptPin;\r
- UINT8 MinGnt;\r
- UINT8 MaxLat;\r
+ UINT32 Bar[6];\r
+ UINT32 CISPtr;\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemID;\r
+ UINT32 ExpansionRomBar;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved1[3];\r
+ UINT32 Reserved2;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT8 MinGnt;\r
+ UINT8 MaxLat;\r
} PCI_DEVICE_HEADER_TYPE_REGION;\r
\r
///\r
/// Section 6.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
- PCI_DEVICE_HEADER_TYPE_REGION Device;\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_DEVICE_HEADER_TYPE_REGION Device;\r
} PCI_TYPE00;\r
\r
///\r
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
///\r
typedef struct {\r
- UINT32 Bar[2];\r
- UINT8 PrimaryBus;\r
- UINT8 SecondaryBus;\r
- UINT8 SubordinateBus;\r
- UINT8 SecondaryLatencyTimer;\r
- UINT8 IoBase;\r
- UINT8 IoLimit;\r
- UINT16 SecondaryStatus;\r
- UINT16 MemoryBase;\r
- UINT16 MemoryLimit;\r
- UINT16 PrefetchableMemoryBase;\r
- UINT16 PrefetchableMemoryLimit;\r
- UINT32 PrefetchableBaseUpper32;\r
- UINT32 PrefetchableLimitUpper32;\r
- UINT16 IoBaseUpper16;\r
- UINT16 IoLimitUpper16;\r
- UINT8 CapabilityPtr;\r
- UINT8 Reserved[3];\r
- UINT32 ExpansionRomBAR;\r
- UINT8 InterruptLine;\r
- UINT8 InterruptPin;\r
- UINT16 BridgeControl;\r
+ UINT32 Bar[2];\r
+ UINT8 PrimaryBus;\r
+ UINT8 SecondaryBus;\r
+ UINT8 SubordinateBus;\r
+ UINT8 SecondaryLatencyTimer;\r
+ UINT8 IoBase;\r
+ UINT8 IoLimit;\r
+ UINT16 SecondaryStatus;\r
+ UINT16 MemoryBase;\r
+ UINT16 MemoryLimit;\r
+ UINT16 PrefetchableMemoryBase;\r
+ UINT16 PrefetchableMemoryLimit;\r
+ UINT32 PrefetchableBaseUpper32;\r
+ UINT32 PrefetchableLimitUpper32;\r
+ UINT16 IoBaseUpper16;\r
+ UINT16 IoLimitUpper16;\r
+ UINT8 CapabilityPtr;\r
+ UINT8 Reserved[3];\r
+ UINT32 ExpansionRomBAR;\r
+ UINT8 InterruptLine;\r
+ UINT8 InterruptPin;\r
+ UINT16 BridgeControl;\r
} PCI_BRIDGE_CONTROL_REGISTER;\r
\r
///\r
/// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r
///\r
typedef struct {\r
- PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
- PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
+ PCI_DEVICE_INDEPENDENT_REGION Hdr;\r
+ PCI_BRIDGE_CONTROL_REGISTER Bridge;\r
} PCI_TYPE01;\r
\r
typedef union {\r
- PCI_TYPE00 Device;\r
- PCI_TYPE01 Bridge;\r
+ PCI_TYPE00 Device;\r
+ PCI_TYPE01 Bridge;\r
} PCI_TYPE_GENERIC;\r
\r
///\r
/// Section 4.5.1, PC Card Standard. 8.0\r
///\r
typedef struct {\r
- UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r
- UINT8 Cap_Ptr;\r
- UINT8 Reserved;\r
- UINT16 SecondaryStatus; ///< Secondary Status\r
- UINT8 PciBusNumber; ///< PCI Bus Number\r
- UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
- UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
- UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
- UINT32 MemoryBase0; ///< Memory Base Register 0\r
- UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
- UINT32 MemoryBase1;\r
- UINT32 MemoryLimit1;\r
- UINT32 IoBase0;\r
- UINT32 IoLimit0; ///< I/O Base Register 0\r
- UINT32 IoBase1; ///< I/O Limit Register 0\r
- UINT32 IoLimit1;\r
- UINT8 InterruptLine; ///< Interrupt Line\r
- UINT8 InterruptPin; ///< Interrupt Pin\r
- UINT16 BridgeControl; ///< Bridge Control\r
+ UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r
+ UINT8 Cap_Ptr;\r
+ UINT8 Reserved;\r
+ UINT16 SecondaryStatus; ///< Secondary Status\r
+ UINT8 PciBusNumber; ///< PCI Bus Number\r
+ UINT8 CardBusBusNumber; ///< CardBus Bus Number\r
+ UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r
+ UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r
+ UINT32 MemoryBase0; ///< Memory Base Register 0\r
+ UINT32 MemoryLimit0; ///< Memory Limit Register 0\r
+ UINT32 MemoryBase1;\r
+ UINT32 MemoryLimit1;\r
+ UINT32 IoBase0;\r
+ UINT32 IoLimit0; ///< I/O Base Register 0\r
+ UINT32 IoBase1; ///< I/O Limit Register 0\r
+ UINT32 IoLimit1;\r
+ UINT8 InterruptLine; ///< Interrupt Line\r
+ UINT8 InterruptPin; ///< Interrupt Pin\r
+ UINT16 BridgeControl; ///< Bridge Control\r
} PCI_CARDBUS_CONTROL_REGISTER;\r
\r
//\r
// Definitions of PCI class bytes and manipulation macros.\r
//\r
-#define PCI_CLASS_OLD 0x00\r
-#define PCI_CLASS_OLD_OTHER 0x00\r
-#define PCI_CLASS_OLD_VGA 0x01\r
-\r
-#define PCI_CLASS_MASS_STORAGE 0x01\r
-#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
-#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
-#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
-#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
-#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
-#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
-\r
-#define PCI_CLASS_NETWORK 0x02\r
-#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
-#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
-#define PCI_CLASS_NETWORK_FDDI 0x02\r
-#define PCI_CLASS_NETWORK_ATM 0x03\r
-#define PCI_CLASS_NETWORK_ISDN 0x04\r
-#define PCI_CLASS_NETWORK_OTHER 0x80\r
-\r
-#define PCI_CLASS_DISPLAY 0x03\r
-#define PCI_CLASS_DISPLAY_VGA 0x00\r
-#define PCI_IF_VGA_VGA 0x00\r
-#define PCI_IF_VGA_8514 0x01\r
-#define PCI_CLASS_DISPLAY_XGA 0x01\r
-#define PCI_CLASS_DISPLAY_3D 0x02\r
-#define PCI_CLASS_DISPLAY_OTHER 0x80\r
-\r
-#define PCI_CLASS_MEDIA 0x04\r
-#define PCI_CLASS_MEDIA_VIDEO 0x00\r
-#define PCI_CLASS_MEDIA_AUDIO 0x01\r
-#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
-#define PCI_CLASS_MEDIA_OTHER 0x80\r
-\r
-#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
-#define PCI_CLASS_MEMORY_RAM 0x00\r
-#define PCI_CLASS_MEMORY_FLASH 0x01\r
-#define PCI_CLASS_MEMORY_OTHER 0x80\r
-\r
-#define PCI_CLASS_BRIDGE 0x06\r
-#define PCI_CLASS_BRIDGE_HOST 0x00\r
-#define PCI_CLASS_BRIDGE_ISA 0x01\r
-#define PCI_CLASS_BRIDGE_EISA 0x02\r
-#define PCI_CLASS_BRIDGE_MCA 0x03\r
-#define PCI_CLASS_BRIDGE_P2P 0x04\r
-#define PCI_IF_BRIDGE_P2P 0x00\r
-#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
-#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
-#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
-#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
-#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
-#define PCI_CLASS_BRIDGE_OTHER 0x80\r
-#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
-\r
-#define PCI_CLASS_SCC 0x07 ///< Simple communications controllers\r
-#define PCI_SUBCLASS_SERIAL 0x00\r
-#define PCI_IF_GENERIC_XT 0x00\r
-#define PCI_IF_16450 0x01\r
-#define PCI_IF_16550 0x02\r
-#define PCI_IF_16650 0x03\r
-#define PCI_IF_16750 0x04\r
-#define PCI_IF_16850 0x05\r
-#define PCI_IF_16950 0x06\r
-#define PCI_SUBCLASS_PARALLEL 0x01\r
-#define PCI_IF_PARALLEL_PORT 0x00\r
-#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
-#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
-#define PCI_IF_1284_CONTROLLER 0x03\r
-#define PCI_IF_1284_DEVICE 0xFE\r
-#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
-#define PCI_SUBCLASS_MODEM 0x03\r
-#define PCI_IF_GENERIC_MODEM 0x00\r
-#define PCI_IF_16450_MODEM 0x01\r
-#define PCI_IF_16550_MODEM 0x02\r
-#define PCI_IF_16650_MODEM 0x03\r
-#define PCI_IF_16750_MODEM 0x04\r
-#define PCI_SUBCLASS_SCC_OTHER 0x80\r
-\r
-#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
-#define PCI_SUBCLASS_PIC 0x00\r
-#define PCI_IF_8259_PIC 0x00\r
-#define PCI_IF_ISA_PIC 0x01\r
-#define PCI_IF_EISA_PIC 0x02\r
-#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
-#define PCI_IF_APIC_CONTROLLER2 0x20\r
-#define PCI_SUBCLASS_DMA 0x01\r
-#define PCI_IF_8237_DMA 0x00\r
-#define PCI_IF_ISA_DMA 0x01\r
-#define PCI_IF_EISA_DMA 0x02\r
-#define PCI_SUBCLASS_TIMER 0x02\r
-#define PCI_IF_8254_TIMER 0x00\r
-#define PCI_IF_ISA_TIMER 0x01\r
-#define PCI_IF_EISA_TIMER 0x02\r
-#define PCI_SUBCLASS_RTC 0x03\r
-#define PCI_IF_GENERIC_RTC 0x00\r
-#define PCI_IF_ISA_RTC 0x01\r
-#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
-#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
-\r
-#define PCI_CLASS_INPUT_DEVICE 0x09\r
-#define PCI_SUBCLASS_KEYBOARD 0x00\r
-#define PCI_SUBCLASS_PEN 0x01\r
-#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
-#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
-#define PCI_SUBCLASS_GAMEPORT 0x04\r
-#define PCI_IF_GAMEPORT 0x00\r
-#define PCI_IF_GAMEPORT1 0x10\r
-#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
-\r
-#define PCI_CLASS_DOCKING_STATION 0x0A\r
+#define PCI_CLASS_OLD 0x00\r
+#define PCI_CLASS_OLD_OTHER 0x00\r
+#define PCI_CLASS_OLD_VGA 0x01\r
+\r
+#define PCI_CLASS_MASS_STORAGE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r
+#define PCI_CLASS_MASS_STORAGE_IDE 0x01\r
+#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r
+#define PCI_CLASS_MASS_STORAGE_IPI 0x03\r
+#define PCI_CLASS_MASS_STORAGE_RAID 0x04\r
+#define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r
+\r
+#define PCI_CLASS_NETWORK 0x02\r
+#define PCI_CLASS_NETWORK_ETHERNET 0x00\r
+#define PCI_CLASS_NETWORK_TOKENRING 0x01\r
+#define PCI_CLASS_NETWORK_FDDI 0x02\r
+#define PCI_CLASS_NETWORK_ATM 0x03\r
+#define PCI_CLASS_NETWORK_ISDN 0x04\r
+#define PCI_CLASS_NETWORK_OTHER 0x80\r
+\r
+#define PCI_CLASS_DISPLAY 0x03\r
+#define PCI_CLASS_DISPLAY_VGA 0x00\r
+#define PCI_IF_VGA_VGA 0x00\r
+#define PCI_IF_VGA_8514 0x01\r
+#define PCI_CLASS_DISPLAY_XGA 0x01\r
+#define PCI_CLASS_DISPLAY_3D 0x02\r
+#define PCI_CLASS_DISPLAY_OTHER 0x80\r
+\r
+#define PCI_CLASS_MEDIA 0x04\r
+#define PCI_CLASS_MEDIA_VIDEO 0x00\r
+#define PCI_CLASS_MEDIA_AUDIO 0x01\r
+#define PCI_CLASS_MEDIA_TELEPHONE 0x02\r
+#define PCI_CLASS_MEDIA_OTHER 0x80\r
+\r
+#define PCI_CLASS_MEMORY_CONTROLLER 0x05\r
+#define PCI_CLASS_MEMORY_RAM 0x00\r
+#define PCI_CLASS_MEMORY_FLASH 0x01\r
+#define PCI_CLASS_MEMORY_OTHER 0x80\r
+\r
+#define PCI_CLASS_BRIDGE 0x06\r
+#define PCI_CLASS_BRIDGE_HOST 0x00\r
+#define PCI_CLASS_BRIDGE_ISA 0x01\r
+#define PCI_CLASS_BRIDGE_EISA 0x02\r
+#define PCI_CLASS_BRIDGE_MCA 0x03\r
+#define PCI_CLASS_BRIDGE_P2P 0x04\r
+#define PCI_IF_BRIDGE_P2P 0x00\r
+#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r
+#define PCI_CLASS_BRIDGE_PCMCIA 0x05\r
+#define PCI_CLASS_BRIDGE_NUBUS 0x06\r
+#define PCI_CLASS_BRIDGE_CARDBUS 0x07\r
+#define PCI_CLASS_BRIDGE_RACEWAY 0x08\r
+#define PCI_CLASS_BRIDGE_OTHER 0x80\r
+#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r
+\r
+#define PCI_CLASS_SCC 0x07///< Simple communications controllers\r
+#define PCI_SUBCLASS_SERIAL 0x00\r
+#define PCI_IF_GENERIC_XT 0x00\r
+#define PCI_IF_16450 0x01\r
+#define PCI_IF_16550 0x02\r
+#define PCI_IF_16650 0x03\r
+#define PCI_IF_16750 0x04\r
+#define PCI_IF_16850 0x05\r
+#define PCI_IF_16950 0x06\r
+#define PCI_SUBCLASS_PARALLEL 0x01\r
+#define PCI_IF_PARALLEL_PORT 0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT 0x02\r
+#define PCI_IF_1284_CONTROLLER 0x03\r
+#define PCI_IF_1284_DEVICE 0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM 0x03\r
+#define PCI_IF_GENERIC_MODEM 0x00\r
+#define PCI_IF_16450_MODEM 0x01\r
+#define PCI_IF_16550_MODEM 0x02\r
+#define PCI_IF_16650_MODEM 0x03\r
+#define PCI_IF_16750_MODEM 0x04\r
+#define PCI_SUBCLASS_SCC_OTHER 0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r
+#define PCI_SUBCLASS_PIC 0x00\r
+#define PCI_IF_8259_PIC 0x00\r
+#define PCI_IF_ISA_PIC 0x01\r
+#define PCI_IF_EISA_PIC 0x02\r
+#define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r
+#define PCI_IF_APIC_CONTROLLER2 0x20\r
+#define PCI_SUBCLASS_DMA 0x01\r
+#define PCI_IF_8237_DMA 0x00\r
+#define PCI_IF_ISA_DMA 0x01\r
+#define PCI_IF_EISA_DMA 0x02\r
+#define PCI_SUBCLASS_TIMER 0x02\r
+#define PCI_IF_8254_TIMER 0x00\r
+#define PCI_IF_ISA_TIMER 0x01\r
+#define PCI_IF_EISA_TIMER 0x02\r
+#define PCI_SUBCLASS_RTC 0x03\r
+#define PCI_IF_GENERIC_RTC 0x00\r
+#define PCI_IF_ISA_RTC 0x01\r
+#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r
+#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r
+\r
+#define PCI_CLASS_INPUT_DEVICE 0x09\r
+#define PCI_SUBCLASS_KEYBOARD 0x00\r
+#define PCI_SUBCLASS_PEN 0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r
+#define PCI_SUBCLASS_GAMEPORT 0x04\r
+#define PCI_IF_GAMEPORT 0x00\r
+#define PCI_IF_GAMEPORT1 0x10\r
+#define PCI_SUBCLASS_INPUT_OTHER 0x80\r
+\r
+#define PCI_CLASS_DOCKING_STATION 0x0A\r
#define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r
#define PCI_SUBCLASS_DOCKING_OTHER 0x80\r
\r
-#define PCI_CLASS_PROCESSOR 0x0B\r
-#define PCI_SUBCLASS_PROC_386 0x00\r
-#define PCI_SUBCLASS_PROC_486 0x01\r
-#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
-#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
-#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
-#define PCI_SUBCLASS_PROC_MIPS 0x30\r
-#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
-\r
-#define PCI_CLASS_SERIAL 0x0C\r
-#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
-#define PCI_IF_1394 0x00\r
-#define PCI_IF_1394_OPEN_HCI 0x10\r
-#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
-#define PCI_CLASS_SERIAL_SSA 0x02\r
-#define PCI_CLASS_SERIAL_USB 0x03\r
-#define PCI_IF_UHCI 0x00\r
-#define PCI_IF_OHCI 0x10\r
-#define PCI_IF_USB_OTHER 0x80\r
-#define PCI_IF_USB_DEVICE 0xFE\r
-#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
-#define PCI_CLASS_SERIAL_SMB 0x05\r
-\r
-#define PCI_CLASS_WIRELESS 0x0D\r
-#define PCI_SUBCLASS_IRDA 0x00\r
-#define PCI_SUBCLASS_IR 0x01\r
-#define PCI_SUBCLASS_RF 0x10\r
-#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
-\r
-#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
-\r
-#define PCI_CLASS_SATELLITE 0x0F\r
-#define PCI_SUBCLASS_TV 0x01\r
-#define PCI_SUBCLASS_AUDIO 0x02\r
-#define PCI_SUBCLASS_VOICE 0x03\r
-#define PCI_SUBCLASS_DATA 0x04\r
-\r
-#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
-#define PCI_SUBCLASS_NET_COMPUT 0x00\r
-#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
-#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
-\r
-#define PCI_CLASS_DPIO 0x11\r
-#define PCI_SUBCLASS_DPIO 0x00\r
-#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
+#define PCI_CLASS_PROCESSOR 0x0B\r
+#define PCI_SUBCLASS_PROC_386 0x00\r
+#define PCI_SUBCLASS_PROC_486 0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM 0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA 0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC 0x20\r
+#define PCI_SUBCLASS_PROC_MIPS 0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r
+\r
+#define PCI_CLASS_SERIAL 0x0C\r
+#define PCI_CLASS_SERIAL_FIREWIRE 0x00\r
+#define PCI_IF_1394 0x00\r
+#define PCI_IF_1394_OPEN_HCI 0x10\r
+#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r
+#define PCI_CLASS_SERIAL_SSA 0x02\r
+#define PCI_CLASS_SERIAL_USB 0x03\r
+#define PCI_IF_UHCI 0x00\r
+#define PCI_IF_OHCI 0x10\r
+#define PCI_IF_USB_OTHER 0x80\r
+#define PCI_IF_USB_DEVICE 0xFE\r
+#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
+#define PCI_CLASS_SERIAL_SMB 0x05\r
+\r
+#define PCI_CLASS_WIRELESS 0x0D\r
+#define PCI_SUBCLASS_IRDA 0x00\r
+#define PCI_SUBCLASS_IR 0x01\r
+#define PCI_SUBCLASS_RF 0x10\r
+#define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO 0x0E\r
+\r
+#define PCI_CLASS_SATELLITE 0x0F\r
+#define PCI_SUBCLASS_TV 0x01\r
+#define PCI_SUBCLASS_AUDIO 0x02\r
+#define PCI_SUBCLASS_VOICE 0x03\r
+#define PCI_SUBCLASS_DATA 0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT 0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT 0x10\r
+#define PCI_SUBCLASS_SECURITY_OTHER 0x80\r
+\r
+#define PCI_CLASS_DPIO 0x11\r
+#define PCI_SUBCLASS_DPIO 0x00\r
+#define PCI_SUBCLASS_DPIO_OTHER 0x80\r
\r
/**\r
Macro that checks whether the Base Class code of device matched.\r
@retval FALSE Base Class code doesn't match the specified device.\r
\r
**/\r
-#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
+#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r
+\r
/**\r
Macro that checks whether the Base Class code and Sub-Class code of device matched.\r
\r
@retval FALSE Base Class code and Sub-Class code don't match the specified device.\r
\r
**/\r
-#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
+#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
+\r
/**\r
Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r
\r
@retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\r
\r
**/\r
-#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
+#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
\r
/**\r
Macro that checks whether device is a display controller.\r
@retval FALSE Device is not a display controller.\r
\r
**/\r
-#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
+#define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r
+\r
/**\r
Macro that checks whether device is a VGA-compatible controller.\r
\r
@retval FALSE Device is not a VGA-compatible controller.\r
\r
**/\r
-#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
+#define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r
+\r
/**\r
Macro that checks whether device is an 8514-compatible controller.\r
\r
@retval FALSE Device is not an 8514-compatible controller.\r
\r
**/\r
-#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
+#define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r
+\r
/**\r
Macro that checks whether device is built before the Class Code field was defined.\r
\r
@retval FALSE Device is not an old device.\r
\r
**/\r
-#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
+#define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r
+\r
/**\r
Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r
\r
@retval FALSE Device is not an old VGA-compatible device.\r
\r
**/\r
-#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
+#define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r
+\r
/**\r
Macro that checks whether device is an IDE controller.\r
\r
@retval FALSE Device is not an IDE controller.\r
\r
**/\r
-#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
+#define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r
+\r
/**\r
Macro that checks whether device is a SCSI bus controller.\r
\r
@retval FALSE Device is not a SCSI bus controller.\r
\r
**/\r
-#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
+#define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r
+\r
/**\r
Macro that checks whether device is a RAID controller.\r
\r
@retval FALSE Device is not a RAID controller.\r
\r
**/\r
-#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
+#define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r
+\r
/**\r
Macro that checks whether device is an ISA bridge.\r
\r
@retval FALSE Device is not an ISA bridge.\r
\r
**/\r
-#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
+#define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r
+\r
/**\r
Macro that checks whether device is a PCI-to-PCI bridge.\r
\r
@retval FALSE Device is not a PCI-to-PCI bridge.\r
\r
**/\r
-#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
+#define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r
+\r
/**\r
Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r
\r
@retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r
\r
**/\r
-#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
+#define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r
+\r
/**\r
Macro that checks whether device is a 16550-compatible serial controller.\r
\r
@retval FALSE Device is not a 16550-compatible serial controller.\r
\r
**/\r
-#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+#define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+\r
/**\r
Macro that checks whether device is a Universal Serial Bus controller.\r
\r
@retval FALSE Device is not a Universal Serial Bus controller.\r
\r
**/\r
-#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
+#define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r
\r
//\r
// the definition of Header Type\r
//\r
-#define HEADER_TYPE_DEVICE 0x00\r
-#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
-#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
-#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
+#define HEADER_TYPE_DEVICE 0x00\r
+#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r
+#define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r
+#define HEADER_TYPE_MULTI_FUNCTION 0x80\r
//\r
// Mask of Header type\r
//\r
-#define HEADER_LAYOUT_CODE 0x7f\r
+#define HEADER_LAYOUT_CODE 0x7f\r
+\r
/**\r
Macro that checks whether device is a PCI-PCI bridge.\r
\r
@retval FALSE Device is not a PCI-PCI bridge.\r
\r
**/\r
-#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
+#define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r
+\r
/**\r
Macro that checks whether device is a CardBus bridge.\r
\r
@retval FALSE Device is not a CardBus bridge.\r
\r
**/\r
-#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
+#define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r
+\r
/**\r
Macro that checks whether device is a multiple functions device.\r
\r
@retval FALSE Device is not a multiple functions device.\r
\r
**/\r
-#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
+#define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r
\r
///\r
/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r
///\r
-#define PCI_BRIDGE_ROMBAR 0x38\r
-\r
-#define PCI_MAX_BAR 0x0006\r
-#define PCI_MAX_CONFIG_OFFSET 0x0100\r
-\r
-#define PCI_VENDOR_ID_OFFSET 0x00\r
-#define PCI_DEVICE_ID_OFFSET 0x02\r
-#define PCI_COMMAND_OFFSET 0x04\r
-#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
-#define PCI_REVISION_ID_OFFSET 0x08\r
-#define PCI_CLASSCODE_OFFSET 0x09\r
-#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
-#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
-#define PCI_HEADER_TYPE_OFFSET 0x0E\r
-#define PCI_BIST_OFFSET 0x0F\r
-#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
-#define PCI_CARDBUS_CIS_OFFSET 0x28\r
-#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
-#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
-#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
-#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
-#define PCI_EXPANSION_ROM_BASE 0x30\r
-#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
-#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
-#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
-#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
-#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
+#define PCI_BRIDGE_ROMBAR 0x38\r
+\r
+#define PCI_MAX_BAR 0x0006\r
+#define PCI_MAX_CONFIG_OFFSET 0x0100\r
+\r
+#define PCI_VENDOR_ID_OFFSET 0x00\r
+#define PCI_DEVICE_ID_OFFSET 0x02\r
+#define PCI_COMMAND_OFFSET 0x04\r
+#define PCI_PRIMARY_STATUS_OFFSET 0x06\r
+#define PCI_REVISION_ID_OFFSET 0x08\r
+#define PCI_CLASSCODE_OFFSET 0x09\r
+#define PCI_CACHELINE_SIZE_OFFSET 0x0C\r
+#define PCI_LATENCY_TIMER_OFFSET 0x0D\r
+#define PCI_HEADER_TYPE_OFFSET 0x0E\r
+#define PCI_BIST_OFFSET 0x0F\r
+#define PCI_BASE_ADDRESSREG_OFFSET 0x10\r
+#define PCI_CARDBUS_CIS_OFFSET 0x28\r
+#define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r
+#define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r
+#define PCI_EXPANSION_ROM_BASE 0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET 0x34\r
+#define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r
+#define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r
\r
//\r
// defined in PCI-to-PCI Bridge Architecture Specification\r
///\r
/// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r
///\r
-#define PCI_INT_LINE_UNKNOWN 0xFF\r
+#define PCI_INT_LINE_UNKNOWN 0xFF\r
\r
///\r
/// PCI Access Data Format\r
///\r
typedef union {\r
struct {\r
- UINT32 Reg : 8;\r
- UINT32 Func : 3;\r
- UINT32 Dev : 5;\r
- UINT32 Bus : 8;\r
- UINT32 Reserved : 7;\r
- UINT32 Enable : 1;\r
+ UINT32 Reg : 8;\r
+ UINT32 Func : 3;\r
+ UINT32 Dev : 5;\r
+ UINT32 Bus : 8;\r
+ UINT32 Reserved : 7;\r
+ UINT32 Enable : 1;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_CONFIG_ACCESS_CF8;\r
\r
#pragma pack()\r
\r
-#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
-#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
-#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
-#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
-#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
-#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
-#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
-#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
-#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
-#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
+#define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r
+#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r
+#define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r
+#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r
+#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r
+#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r
+#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r
+#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r
+#define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r
+#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r
\r
//\r
// defined in PCI-to-PCI Bridge Architecture Specification\r
//\r
// Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r
//\r
-#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
-#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
-#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
+#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r
+#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r
+#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r
\r
//\r
// Following are the PCI status control bit\r
//\r
-#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
-#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
-#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
-#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
+#define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r
+#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r
+#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r
+#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r
\r
///\r
/// defined in PC Card Standard\r
///\r
-#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
+#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r
\r
#pragma pack(1)\r
//\r
// PCI Capability List IDs and records\r
//\r
-#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
-#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
-#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
-#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
-#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
-#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
-#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
+#define EFI_PCI_CAPABILITY_ID_PMI 0x01\r
+#define EFI_PCI_CAPABILITY_ID_AGP 0x02\r
+#define EFI_PCI_CAPABILITY_ID_VPD 0x03\r
+#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r
+#define EFI_PCI_CAPABILITY_ID_MSI 0x05\r
+#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r
+#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r
\r
///\r
/// Capabilities List Header\r
/// Section 6.7, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- UINT8 CapabilityID;\r
- UINT8 NextItemPtr;\r
+ UINT8 CapabilityID;\r
+ UINT8 NextItemPtr;\r
} EFI_PCI_CAPABILITY_HDR;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT16 Version : 3;\r
- UINT16 PmeClock : 1;\r
- UINT16 Reserved : 1;\r
- UINT16 DeviceSpecificInitialization : 1;\r
- UINT16 AuxCurrent : 3;\r
- UINT16 D1Support : 1;\r
- UINT16 D2Support : 1;\r
- UINT16 PmeSupport : 5;\r
+ UINT16 Version : 3;\r
+ UINT16 PmeClock : 1;\r
+ UINT16 Reserved : 1;\r
+ UINT16 DeviceSpecificInitialization : 1;\r
+ UINT16 AuxCurrent : 3;\r
+ UINT16 D1Support : 1;\r
+ UINT16 D2Support : 1;\r
+ UINT16 PmeSupport : 5;\r
} Bits;\r
- UINT16 Data;\r
+ UINT16 Data;\r
} EFI_PCI_PMC;\r
\r
-#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
+#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r
\r
///\r
/// PMCSR - Power Management Control/Status\r
///\r
typedef union {\r
struct {\r
- UINT16 PowerState : 2;\r
- UINT16 ReservedForPciExpress : 1;\r
- UINT16 NoSoftReset : 1;\r
- UINT16 Reserved : 4;\r
- UINT16 PmeEnable : 1;\r
- UINT16 DataSelect : 4;\r
- UINT16 DataScale : 2;\r
- UINT16 PmeStatus : 1;\r
+ UINT16 PowerState : 2;\r
+ UINT16 ReservedForPciExpress : 1;\r
+ UINT16 NoSoftReset : 1;\r
+ UINT16 Reserved : 4;\r
+ UINT16 PmeEnable : 1;\r
+ UINT16 DataSelect : 4;\r
+ UINT16 DataScale : 2;\r
+ UINT16 PmeStatus : 1;\r
} Bits;\r
- UINT16 Data;\r
+ UINT16 Data;\r
} EFI_PCI_PMCSR;\r
\r
-#define PCI_POWER_STATE_D0 0\r
-#define PCI_POWER_STATE_D1 1\r
-#define PCI_POWER_STATE_D2 2\r
-#define PCI_POWER_STATE_D3_HOT 3\r
+#define PCI_POWER_STATE_D0 0\r
+#define PCI_POWER_STATE_D1 1\r
+#define PCI_POWER_STATE_D2 2\r
+#define PCI_POWER_STATE_D3_HOT 3\r
\r
///\r
/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r
///\r
typedef union {\r
struct {\r
- UINT8 Reserved : 6;\r
- UINT8 B2B3 : 1;\r
- UINT8 BusPowerClockControl : 1;\r
+ UINT8 Reserved : 6;\r
+ UINT8 B2B3 : 1;\r
+ UINT8 BusPowerClockControl : 1;\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} EFI_PCI_PMCSR_BSE;\r
\r
///\r
/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- EFI_PCI_PMC PMC;\r
- EFI_PCI_PMCSR PMCSR;\r
- EFI_PCI_PMCSR_BSE BridgeExtention;\r
- UINT8 Data;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ EFI_PCI_PMC PMC;\r
+ EFI_PCI_PMCSR PMCSR;\r
+ EFI_PCI_PMCSR_BSE BridgeExtention;\r
+ UINT8 Data;\r
} EFI_PCI_CAPABILITY_PMI;\r
\r
///\r
/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT8 Rev;\r
- UINT8 Reserved;\r
- UINT32 Status;\r
- UINT32 Command;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 Rev;\r
+ UINT8 Reserved;\r
+ UINT32 Status;\r
+ UINT32 Command;\r
} EFI_PCI_CAPABILITY_AGP;\r
\r
///\r
/// Appendix I, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 AddrReg;\r
- UINT32 DataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 AddrReg;\r
+ UINT32 DataReg;\r
} EFI_PCI_CAPABILITY_VPD;\r
\r
///\r
/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT8 ExpnsSlotReg;\r
- UINT8 ChassisNo;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 ExpnsSlotReg;\r
+ UINT8 ChassisNo;\r
} EFI_PCI_CAPABILITY_SLOTID;\r
\r
///\r
/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 MsgCtrlReg;\r
- UINT32 MsgAddrReg;\r
- UINT16 MsgDataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrReg;\r
+ UINT16 MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI32;\r
\r
///\r
/// Section 6.8.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 MsgCtrlReg;\r
- UINT32 MsgAddrRegLsdw;\r
- UINT32 MsgAddrRegMsdw;\r
- UINT16 MsgDataReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 MsgCtrlReg;\r
+ UINT32 MsgAddrRegLsdw;\r
+ UINT32 MsgAddrRegMsdw;\r
+ UINT16 MsgDataReg;\r
} EFI_PCI_CAPABILITY_MSI64;\r
\r
///\r
/// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
///\r
/// not finished - fields need to go here\r
///\r
} EFI_PCI_CAPABILITY_HOTPLUG;\r
\r
-#define PCI_BAR_IDX0 0x00\r
-#define PCI_BAR_IDX1 0x01\r
-#define PCI_BAR_IDX2 0x02\r
-#define PCI_BAR_IDX3 0x03\r
-#define PCI_BAR_IDX4 0x04\r
-#define PCI_BAR_IDX5 0x05\r
+#define PCI_BAR_IDX0 0x00\r
+#define PCI_BAR_IDX1 0x01\r
+#define PCI_BAR_IDX2 0x02\r
+#define PCI_BAR_IDX3 0x03\r
+#define PCI_BAR_IDX4 0x04\r
+#define PCI_BAR_IDX5 0x05\r
\r
///\r
/// EFI PCI Option ROM definitions\r
///\r
-#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
+#define EFI_ROOT_BRIDGE_LIST 'eprb'\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r
\r
-#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
-#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
-#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
-#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
+#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r
+#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r
+#define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r
+#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r
\r
///\r
/// Standard PCI Expansion ROM Header\r
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
///\r
typedef struct {\r
- UINT16 Signature; ///< 0xaa55\r
- UINT8 Reserved[0x16];\r
- UINT16 PcirOffset;\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT8 Reserved[0x16];\r
+ UINT16 PcirOffset;\r
} PCI_EXPANSION_ROM_HEADER;\r
\r
///\r
/// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- UINT16 Signature; ///< 0xaa55\r
- UINT8 Size512;\r
- UINT8 InitEntryPoint[3];\r
- UINT8 Reserved[0x12];\r
- UINT16 PcirOffset;\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT8 Size512;\r
+ UINT8 InitEntryPoint[3];\r
+ UINT8 Reserved[0x12];\r
+ UINT16 PcirOffset;\r
} EFI_LEGACY_EXPANSION_ROM_HEADER;\r
\r
///\r
/// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r
///\r
typedef struct {\r
- UINT32 Signature; ///< "PCIR"\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 Reserved0;\r
- UINT16 Length;\r
- UINT8 Revision;\r
- UINT8 ClassCode[3];\r
- UINT16 ImageLength;\r
- UINT16 CodeRevision;\r
- UINT8 CodeType;\r
- UINT8 Indicator;\r
- UINT16 Reserved1;\r
+ UINT32 Signature; ///< "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 Reserved0;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 Reserved1;\r
} PCI_DATA_STRUCTURE;\r
\r
///\r
/// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r
///\r
typedef struct {\r
- UINT16 Signature; ///< 0xaa55\r
- UINT16 InitializationSize;\r
- UINT32 EfiSignature; ///< 0x0EF1\r
- UINT16 EfiSubsystem;\r
- UINT16 EfiMachineType;\r
- UINT16 CompressionType;\r
- UINT8 Reserved[8];\r
- UINT16 EfiImageHeaderOffset;\r
- UINT16 PcirOffset;\r
+ UINT16 Signature; ///< 0xaa55\r
+ UINT16 InitializationSize;\r
+ UINT32 EfiSignature; ///< 0x0EF1\r
+ UINT16 EfiSubsystem;\r
+ UINT16 EfiMachineType;\r
+ UINT16 CompressionType;\r
+ UINT8 Reserved[8];\r
+ UINT16 EfiImageHeaderOffset;\r
+ UINT16 PcirOffset;\r
} EFI_PCI_EXPANSION_ROM_HEADER;\r
\r
typedef union {\r
- UINT8 *Raw;\r
- PCI_EXPANSION_ROM_HEADER *Generic;\r
- EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
- EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
+ UINT8 *Raw;\r
+ PCI_EXPANSION_ROM_HEADER *Generic;\r
+ EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r
+ EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r
} EFI_PCI_ROM_HEADER;\r
\r
#pragma pack()\r
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
///\r
///@{\r
-#define PCI_CLASS_MASS_STORAGE_ATA 0x05\r
+#define PCI_CLASS_MASS_STORAGE_ATA 0x05\r
#define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20\r
#define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30\r
///@}\r
/// PCI_CLASS_NETWORK, Base Class 02h.\r
///\r
///@{\r
-#define PCI_CLASS_NETWORK_WORLDFIP 0x05\r
-#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\r
+#define PCI_CLASS_NETWORK_WORLDFIP 0x05\r
+#define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06\r
///@}\r
\r
///\r
/// PCI_CLASS_BRIDGE, Base Class 06h.\r
///\r
///@{\r
-#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\r
-#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\r
-#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\r
-#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\r
+#define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09\r
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40\r
+#define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80\r
+#define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A\r
///@}\r
\r
///\r
/// PCI_CLASS_SCC, Base Class 07h.\r
///\r
///@{\r
-#define PCI_SUBCLASS_GPIB 0x04\r
-#define PCI_SUBCLASS_SMART_CARD 0x05\r
+#define PCI_SUBCLASS_GPIB 0x04\r
+#define PCI_SUBCLASS_SMART_CARD 0x05\r
///@}\r
\r
///\r
/// PCI_CLASS_SERIAL, Base Class 0Ch.\r
///\r
///@{\r
-#define PCI_IF_EHCI 0x20\r
-#define PCI_CLASS_SERIAL_IB 0x06\r
-#define PCI_CLASS_SERIAL_IPMI 0x07\r
-#define PCI_IF_IPMI_SMIC 0x00\r
-#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\r
-#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\r
-#define PCI_CLASS_SERIAL_SERCOS 0x08\r
-#define PCI_CLASS_SERIAL_CANBUS 0x09\r
+#define PCI_IF_EHCI 0x20\r
+#define PCI_CLASS_SERIAL_IB 0x06\r
+#define PCI_CLASS_SERIAL_IPMI 0x07\r
+#define PCI_IF_IPMI_SMIC 0x00\r
+#define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style\r
+#define PCI_IF_IPMI_BT 0x02 ///< Block Transfer\r
+#define PCI_CLASS_SERIAL_SERCOS 0x08\r
+#define PCI_CLASS_SERIAL_CANBUS 0x09\r
///@}\r
\r
///\r
/// PCI_CLASS_WIRELESS, Base Class 0Dh.\r
///\r
///@{\r
-#define PCI_SUBCLASS_BLUETOOTH 0x11\r
-#define PCI_SUBCLASS_BROADBAND 0x12\r
+#define PCI_SUBCLASS_BLUETOOTH 0x11\r
+#define PCI_SUBCLASS_BROADBAND 0x12\r
///@}\r
\r
///\r
/// PCI_CLASS_DPIO, Base Class 11h.\r
///\r
///@{\r
-#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01\r
-#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10\r
-#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20\r
+#define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01\r
+#define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10\r
+#define PCI_SUBCLASS_MANAGEMENT_CARD 0x20\r
///@}\r
\r
///\r
/// defined in PCI Express Spec.\r
///\r
-#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r
+#define PCI_EXP_MAX_CONFIG_OFFSET 0x1000\r
\r
///\r
/// PCI Capability List IDs and records.\r
/// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 CommandReg;\r
- UINT32 StatusReg;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 CommandReg;\r
+ UINT32 StatusReg;\r
} EFI_PCI_CAPABILITY_PCIX;\r
\r
///\r
/// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT16 SecStatusReg;\r
- UINT32 StatusReg;\r
- UINT32 SplitTransCtrlRegUp;\r
- UINT32 SplitTransCtrlRegDn;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT16 SecStatusReg;\r
+ UINT32 StatusReg;\r
+ UINT32 SplitTransCtrlRegUp;\r
+ UINT32 SplitTransCtrlRegDn;\r
} EFI_PCI_CAPABILITY_PCIX_BRDG;\r
\r
///\r
/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3\r
///\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- UINT8 Length;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ UINT8 Length;\r
} EFI_PCI_CAPABILITY_VENDOR_HDR;\r
\r
#pragma pack()\r
\r
-#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
+#define PCI_CODE_TYPE_EFI_IMAGE 0x03\r
\r
#endif\r
#ifndef __PCI30_H__\r
#define __PCI30_H__\r
\r
-\r
#include <IndustryStandard/Pci23.h>\r
\r
///\r
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
///\r
///@{\r
-#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r
-#define PCI_IF_MASS_STORAGE_SATA 0x00\r
-#define PCI_IF_MASS_STORAGE_AHCI 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r
+#define PCI_IF_MASS_STORAGE_SATA 0x00\r
+#define PCI_IF_MASS_STORAGE_AHCI 0x01\r
///@}\r
\r
///\r
/// PCI_CLASS_WIRELESS, Base Class 0Dh.\r
///\r
///@{\r
-#define PCI_SUBCLASS_ETHERNET_80211A 0x20\r
-#define PCI_SUBCLASS_ETHERNET_80211B 0x21\r
+#define PCI_SUBCLASS_ETHERNET_80211A 0x20\r
+#define PCI_SUBCLASS_ETHERNET_80211B 0x21\r
///@}\r
\r
/**\r
@retval FALSE Device is not a SATA controller.\r
\r
**/\r
-#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r
+#define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r
\r
///\r
/// PCI Capability List IDs and records\r
/// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r
///\r
typedef struct {\r
- UINT32 Signature; ///< "PCIR"\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT16 DeviceListOffset;\r
- UINT16 Length;\r
- UINT8 Revision;\r
- UINT8 ClassCode[3];\r
- UINT16 ImageLength;\r
- UINT16 CodeRevision;\r
- UINT8 CodeType;\r
- UINT8 Indicator;\r
- UINT16 MaxRuntimeImageLength;\r
- UINT16 ConfigUtilityCodeHeaderOffset;\r
- UINT16 DMTFCLPEntryPointOffset;\r
+ UINT32 Signature; ///< "PCIR"\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 DeviceListOffset;\r
+ UINT16 Length;\r
+ UINT8 Revision;\r
+ UINT8 ClassCode[3];\r
+ UINT16 ImageLength;\r
+ UINT16 CodeRevision;\r
+ UINT8 CodeType;\r
+ UINT8 Indicator;\r
+ UINT16 MaxRuntimeImageLength;\r
+ UINT16 ConfigUtilityCodeHeaderOffset;\r
+ UINT16 DMTFCLPEntryPointOffset;\r
} PCI_3_0_DATA_STRUCTURE;\r
\r
#pragma pack()\r
#ifndef __PCI_CODE_ID_H__\r
#define __PCI_CODE_ID_H__\r
\r
-\r
///\r
/// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r
///\r
///@{\r
-#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00\r
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11\r
-#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12\r
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13\r
-#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21\r
-#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02\r
-#define PCI_CLASS_MASS_STORAGE_SAS 0x07\r
-#define PCI_IF_MASS_STORAGE_SAS 0x00\r
-#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01\r
-#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08\r
-#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00\r
-#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01\r
-#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02\r
+#define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00\r
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11\r
+#define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12\r
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13\r
+#define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21\r
+#define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02\r
+#define PCI_CLASS_MASS_STORAGE_SAS 0x07\r
+#define PCI_IF_MASS_STORAGE_SAS 0x00\r
+#define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01\r
+#define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08\r
+#define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00\r
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01\r
+#define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02\r
///@}\r
\r
///\r
/// PCI_CLASS_NETWORK, Base Class 02h.\r
///\r
///@{\r
-#define PCI_CLASS_NETWORK_INFINIBAND 0x07\r
+#define PCI_CLASS_NETWORK_INFINIBAND 0x07\r
///@}\r
\r
///\r
/// PCI_CLASS_MEDIA, Base Class 04h.\r
///\r
///@{\r
-#define PCI_CLASS_MEDIA_MIXED_MODE 0x03\r
+#define PCI_CLASS_MEDIA_MIXED_MODE 0x03\r
///@}\r
\r
///\r
/// PCI_CLASS_BRIDGE, Base Class 06h.\r
///\r
///@{\r
-#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B\r
-#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00\r
-#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01\r
+#define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B\r
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00\r
+#define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01\r
///@}\r
\r
///\r
/// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.\r
///\r
///@{\r
-#define PCI_IF_HPET 0x03\r
-#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r
-#define PCI_SUBCLASS_IOMMU 0x06\r
+#define PCI_IF_HPET 0x03\r
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r
+#define PCI_SUBCLASS_IOMMU 0x06\r
///@}\r
\r
///\r
/// PCI_CLASS_PROCESSOR, Base Class 0Bh.\r
///\r
///@{\r
-#define PCI_SUBCLASS_PROC_OTHER 0x80\r
+#define PCI_SUBCLASS_PROC_OTHER 0x80\r
///@}\r
\r
///\r
/// PCI_CLASS_SERIAL, Base Class 0Ch.\r
///\r
///@{\r
-#define PCI_IF_XHCI 0x30\r
+#define PCI_IF_XHCI 0x30\r
#define PCI_CLASS_SERIAL_OTHER 0x80\r
///@}\r
\r
/// PCI_CLASS_SATELLITE, Base Class 0Fh.\r
///\r
///@{\r
-#define PCI_SUBCLASS_SATELLITE_OTHER 0x80\r
+#define PCI_SUBCLASS_SATELLITE_OTHER 0x80\r
///@}\r
\r
///\r
@return The encode ECAM address.\r
\r
**/\r
-#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \\r
+#define PCI_ECAM_ADDRESS(Bus, Device, Function, Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
#pragma pack(1)\r
///\r
typedef union {\r
struct {\r
- UINT16 Version : 4;\r
- UINT16 DevicePortType : 4;\r
- UINT16 SlotImplemented : 1;\r
- UINT16 InterruptMessageNumber : 5;\r
- UINT16 Undefined : 1;\r
- UINT16 Reserved : 1;\r
+ UINT16 Version : 4;\r
+ UINT16 DevicePortType : 4;\r
+ UINT16 SlotImplemented : 1;\r
+ UINT16 InterruptMessageNumber : 5;\r
+ UINT16 Undefined : 1;\r
+ UINT16 Reserved : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_CAPABILITY;\r
\r
-#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
-#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
-#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
-#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
-#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
-#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
-#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r
+#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r
+#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r
+#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r
+#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r
+#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r
+#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r
\r
typedef union {\r
struct {\r
- UINT32 MaxPayloadSize : 3;\r
- UINT32 PhantomFunctions : 2;\r
- UINT32 ExtendedTagField : 1;\r
- UINT32 EndpointL0sAcceptableLatency : 3;\r
- UINT32 EndpointL1AcceptableLatency : 3;\r
- UINT32 Undefined : 3;\r
- UINT32 RoleBasedErrorReporting : 1;\r
- UINT32 Reserved : 2;\r
- UINT32 CapturedSlotPowerLimitValue : 8;\r
- UINT32 CapturedSlotPowerLimitScale : 2;\r
- UINT32 FunctionLevelReset : 1;\r
- UINT32 Reserved2 : 3;\r
+ UINT32 MaxPayloadSize : 3;\r
+ UINT32 PhantomFunctions : 2;\r
+ UINT32 ExtendedTagField : 1;\r
+ UINT32 EndpointL0sAcceptableLatency : 3;\r
+ UINT32 EndpointL1AcceptableLatency : 3;\r
+ UINT32 Undefined : 3;\r
+ UINT32 RoleBasedErrorReporting : 1;\r
+ UINT32 Reserved : 2;\r
+ UINT32 CapturedSlotPowerLimitValue : 8;\r
+ UINT32 CapturedSlotPowerLimitScale : 2;\r
+ UINT32 FunctionLevelReset : 1;\r
+ UINT32 Reserved2 : 3;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_DEVICE_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 CorrectableError : 1;\r
- UINT16 NonFatalError : 1;\r
- UINT16 FatalError : 1;\r
- UINT16 UnsupportedRequest : 1;\r
- UINT16 RelaxedOrdering : 1;\r
- UINT16 MaxPayloadSize : 3;\r
- UINT16 ExtendedTagField : 1;\r
- UINT16 PhantomFunctions : 1;\r
- UINT16 AuxPower : 1;\r
- UINT16 NoSnoop : 1;\r
- UINT16 MaxReadRequestSize : 3;\r
- UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 RelaxedOrdering : 1;\r
+ UINT16 MaxPayloadSize : 3;\r
+ UINT16 ExtendedTagField : 1;\r
+ UINT16 PhantomFunctions : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 NoSnoop : 1;\r
+ UINT16 MaxReadRequestSize : 3;\r
+ UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_CONTROL;\r
\r
#define PCIE_MAX_PAYLOAD_SIZE_128B 0\r
#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6\r
#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7\r
\r
-#define PCIE_MAX_READ_REQ_SIZE_128B 0\r
-#define PCIE_MAX_READ_REQ_SIZE_256B 1\r
-#define PCIE_MAX_READ_REQ_SIZE_512B 2\r
-#define PCIE_MAX_READ_REQ_SIZE_1024B 3\r
-#define PCIE_MAX_READ_REQ_SIZE_2048B 4\r
-#define PCIE_MAX_READ_REQ_SIZE_4096B 5\r
-#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\r
-#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\r
+#define PCIE_MAX_READ_REQ_SIZE_128B 0\r
+#define PCIE_MAX_READ_REQ_SIZE_256B 1\r
+#define PCIE_MAX_READ_REQ_SIZE_512B 2\r
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3\r
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4\r
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6\r
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7\r
\r
typedef union {\r
struct {\r
- UINT16 CorrectableError : 1;\r
- UINT16 NonFatalError : 1;\r
- UINT16 FatalError : 1;\r
- UINT16 UnsupportedRequest : 1;\r
- UINT16 AuxPower : 1;\r
- UINT16 TransactionsPending : 1;\r
- UINT16 Reserved : 10;\r
+ UINT16 CorrectableError : 1;\r
+ UINT16 NonFatalError : 1;\r
+ UINT16 FatalError : 1;\r
+ UINT16 UnsupportedRequest : 1;\r
+ UINT16 AuxPower : 1;\r
+ UINT16 TransactionsPending : 1;\r
+ UINT16 Reserved : 10;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 MaxLinkSpeed : 4;\r
- UINT32 MaxLinkWidth : 6;\r
- UINT32 Aspm : 2;\r
- UINT32 L0sExitLatency : 3;\r
- UINT32 L1ExitLatency : 3;\r
- UINT32 ClockPowerManagement : 1;\r
- UINT32 SurpriseDownError : 1;\r
- UINT32 DataLinkLayerLinkActive : 1;\r
- UINT32 LinkBandwidthNotification : 1;\r
- UINT32 AspmOptionalityCompliance : 1;\r
- UINT32 Reserved : 1;\r
- UINT32 PortNumber : 8;\r
+ UINT32 MaxLinkSpeed : 4;\r
+ UINT32 MaxLinkWidth : 6;\r
+ UINT32 Aspm : 2;\r
+ UINT32 L0sExitLatency : 3;\r
+ UINT32 L1ExitLatency : 3;\r
+ UINT32 ClockPowerManagement : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 DataLinkLayerLinkActive : 1;\r
+ UINT32 LinkBandwidthNotification : 1;\r
+ UINT32 AspmOptionalityCompliance : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 PortNumber : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_LINK_CAPABILITY;\r
\r
-#define PCIE_LINK_ASPM_L0S BIT0\r
-#define PCIE_LINK_ASPM_L1 BIT1\r
+#define PCIE_LINK_ASPM_L0S BIT0\r
+#define PCIE_LINK_ASPM_L1 BIT1\r
\r
typedef union {\r
struct {\r
- UINT16 AspmControl : 2;\r
- UINT16 Reserved : 1;\r
- UINT16 ReadCompletionBoundary : 1;\r
- UINT16 LinkDisable : 1;\r
- UINT16 RetrainLink : 1;\r
- UINT16 CommonClockConfiguration : 1;\r
- UINT16 ExtendedSynch : 1;\r
- UINT16 ClockPowerManagement : 1;\r
- UINT16 HardwareAutonomousWidthDisable : 1;\r
- UINT16 LinkBandwidthManagementInterrupt : 1;\r
- UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
+ UINT16 AspmControl : 2;\r
+ UINT16 Reserved : 1;\r
+ UINT16 ReadCompletionBoundary : 1;\r
+ UINT16 LinkDisable : 1;\r
+ UINT16 RetrainLink : 1;\r
+ UINT16 CommonClockConfiguration : 1;\r
+ UINT16 ExtendedSynch : 1;\r
+ UINT16 ClockPowerManagement : 1;\r
+ UINT16 HardwareAutonomousWidthDisable : 1;\r
+ UINT16 LinkBandwidthManagementInterrupt : 1;\r
+ UINT16 LinkAutonomousBandwidthInterrupt : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CurrentLinkSpeed : 4;\r
- UINT16 NegotiatedLinkWidth : 6;\r
- UINT16 Undefined : 1;\r
- UINT16 LinkTraining : 1;\r
- UINT16 SlotClockConfiguration : 1;\r
- UINT16 DataLinkLayerLinkActive : 1;\r
- UINT16 LinkBandwidthManagement : 1;\r
- UINT16 LinkAutonomousBandwidth : 1;\r
+ UINT16 CurrentLinkSpeed : 4;\r
+ UINT16 NegotiatedLinkWidth : 6;\r
+ UINT16 Undefined : 1;\r
+ UINT16 LinkTraining : 1;\r
+ UINT16 SlotClockConfiguration : 1;\r
+ UINT16 DataLinkLayerLinkActive : 1;\r
+ UINT16 LinkBandwidthManagement : 1;\r
+ UINT16 LinkAutonomousBandwidth : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 AttentionButton : 1;\r
- UINT32 PowerController : 1;\r
- UINT32 MrlSensor : 1;\r
- UINT32 AttentionIndicator : 1;\r
- UINT32 PowerIndicator : 1;\r
- UINT32 HotPlugSurprise : 1;\r
- UINT32 HotPlugCapable : 1;\r
- UINT32 SlotPowerLimitValue : 8;\r
- UINT32 SlotPowerLimitScale : 2;\r
- UINT32 ElectromechanicalInterlock : 1;\r
- UINT32 NoCommandCompleted : 1;\r
- UINT32 PhysicalSlotNumber : 13;\r
+ UINT32 AttentionButton : 1;\r
+ UINT32 PowerController : 1;\r
+ UINT32 MrlSensor : 1;\r
+ UINT32 AttentionIndicator : 1;\r
+ UINT32 PowerIndicator : 1;\r
+ UINT32 HotPlugSurprise : 1;\r
+ UINT32 HotPlugCapable : 1;\r
+ UINT32 SlotPowerLimitValue : 8;\r
+ UINT32 SlotPowerLimitScale : 2;\r
+ UINT32 ElectromechanicalInterlock : 1;\r
+ UINT32 NoCommandCompleted : 1;\r
+ UINT32 PhysicalSlotNumber : 13;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_SLOT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT16 AttentionButtonPressed : 1;\r
- UINT16 PowerFaultDetected : 1;\r
- UINT16 MrlSensorChanged : 1;\r
- UINT16 PresenceDetectChanged : 1;\r
- UINT16 CommandCompletedInterrupt : 1;\r
- UINT16 HotPlugInterrupt : 1;\r
- UINT16 AttentionIndicator : 2;\r
- UINT16 PowerIndicator : 2;\r
- UINT16 PowerController : 1;\r
- UINT16 ElectromechanicalInterlock : 1;\r
- UINT16 DataLinkLayerStateChanged : 1;\r
- UINT16 Reserved : 3;\r
+ UINT16 AttentionButtonPressed : 1;\r
+ UINT16 PowerFaultDetected : 1;\r
+ UINT16 MrlSensorChanged : 1;\r
+ UINT16 PresenceDetectChanged : 1;\r
+ UINT16 CommandCompletedInterrupt : 1;\r
+ UINT16 HotPlugInterrupt : 1;\r
+ UINT16 AttentionIndicator : 2;\r
+ UINT16 PowerIndicator : 2;\r
+ UINT16 PowerController : 1;\r
+ UINT16 ElectromechanicalInterlock : 1;\r
+ UINT16 DataLinkLayerStateChanged : 1;\r
+ UINT16 Reserved : 3;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_SLOT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 AttentionButtonPressed : 1;\r
- UINT16 PowerFaultDetected : 1;\r
- UINT16 MrlSensorChanged : 1;\r
- UINT16 PresenceDetectChanged : 1;\r
- UINT16 CommandCompleted : 1;\r
- UINT16 MrlSensor : 1;\r
- UINT16 PresenceDetect : 1;\r
- UINT16 ElectromechanicalInterlock : 1;\r
- UINT16 DataLinkLayerStateChanged : 1;\r
- UINT16 Reserved : 7;\r
+ UINT16 AttentionButtonPressed : 1;\r
+ UINT16 PowerFaultDetected : 1;\r
+ UINT16 MrlSensorChanged : 1;\r
+ UINT16 PresenceDetectChanged : 1;\r
+ UINT16 CommandCompleted : 1;\r
+ UINT16 MrlSensor : 1;\r
+ UINT16 PresenceDetect : 1;\r
+ UINT16 ElectromechanicalInterlock : 1;\r
+ UINT16 DataLinkLayerStateChanged : 1;\r
+ UINT16 Reserved : 7;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_SLOT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT16 SystemErrorOnCorrectableError : 1;\r
- UINT16 SystemErrorOnNonFatalError : 1;\r
- UINT16 SystemErrorOnFatalError : 1;\r
- UINT16 PmeInterrupt : 1;\r
- UINT16 CrsSoftwareVisibility : 1;\r
- UINT16 Reserved : 11;\r
+ UINT16 SystemErrorOnCorrectableError : 1;\r
+ UINT16 SystemErrorOnNonFatalError : 1;\r
+ UINT16 SystemErrorOnFatalError : 1;\r
+ UINT16 PmeInterrupt : 1;\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 11;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_ROOT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT16 CrsSoftwareVisibility : 1;\r
- UINT16 Reserved : 15;\r
+ UINT16 CrsSoftwareVisibility : 1;\r
+ UINT16 Reserved : 15;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_ROOT_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT32 PmeRequesterId : 16;\r
- UINT32 PmeStatus : 1;\r
- UINT32 PmePending : 1;\r
- UINT32 Reserved : 14;\r
+ UINT32 PmeRequesterId : 16;\r
+ UINT32 PmeStatus : 1;\r
+ UINT32 PmePending : 1;\r
+ UINT32 Reserved : 14;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_ROOT_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 CompletionTimeoutRanges : 4;\r
- UINT32 CompletionTimeoutDisable : 1;\r
- UINT32 AriForwarding : 1;\r
- UINT32 AtomicOpRouting : 1;\r
- UINT32 AtomicOp32Completer : 1;\r
- UINT32 AtomicOp64Completer : 1;\r
- UINT32 Cas128Completer : 1;\r
- UINT32 NoRoEnabledPrPrPassing : 1;\r
- UINT32 LtrMechanism : 1;\r
- UINT32 TphCompleter : 2;\r
- UINT32 LnSystemCLS : 2;\r
- UINT32 TenBitTagCompleterSupported : 1;\r
- UINT32 TenBitTagRequesterSupported : 1;\r
- UINT32 Obff : 2;\r
- UINT32 ExtendedFmtField : 1;\r
- UINT32 EndEndTlpPrefix : 1;\r
- UINT32 MaxEndEndTlpPrefixes : 2;\r
- UINT32 EmergencyPowerReductionSupported : 2;\r
- UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
- UINT32 Reserved3 : 4;\r
- UINT32 FrsSupported : 1;\r
+ UINT32 CompletionTimeoutRanges : 4;\r
+ UINT32 CompletionTimeoutDisable : 1;\r
+ UINT32 AriForwarding : 1;\r
+ UINT32 AtomicOpRouting : 1;\r
+ UINT32 AtomicOp32Completer : 1;\r
+ UINT32 AtomicOp64Completer : 1;\r
+ UINT32 Cas128Completer : 1;\r
+ UINT32 NoRoEnabledPrPrPassing : 1;\r
+ UINT32 LtrMechanism : 1;\r
+ UINT32 TphCompleter : 2;\r
+ UINT32 LnSystemCLS : 2;\r
+ UINT32 TenBitTagCompleterSupported : 1;\r
+ UINT32 TenBitTagRequesterSupported : 1;\r
+ UINT32 Obff : 2;\r
+ UINT32 ExtendedFmtField : 1;\r
+ UINT32 EndEndTlpPrefix : 1;\r
+ UINT32 MaxEndEndTlpPrefixes : 2;\r
+ UINT32 EmergencyPowerReductionSupported : 2;\r
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;\r
+ UINT32 Reserved3 : 4;\r
+ UINT32 FrsSupported : 1;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_DEVICE_CAPABILITY2;\r
\r
-#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\r
-#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14\r
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15\r
\r
-#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
-#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r
+#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r
\r
typedef union {\r
struct {\r
- UINT16 CompletionTimeoutValue : 4;\r
- UINT16 CompletionTimeoutDisable : 1;\r
- UINT16 AriForwarding : 1;\r
- UINT16 AtomicOpRequester : 1;\r
- UINT16 AtomicOpEgressBlocking : 1;\r
- UINT16 IdoRequest : 1;\r
- UINT16 IdoCompletion : 1;\r
- UINT16 LtrMechanism : 1;\r
- UINT16 EmergencyPowerReductionRequest : 1;\r
- UINT16 TenBitTagRequesterEnable : 1;\r
- UINT16 Obff : 2;\r
- UINT16 EndEndTlpPrefixBlocking : 1;\r
+ UINT16 CompletionTimeoutValue : 4;\r
+ UINT16 CompletionTimeoutDisable : 1;\r
+ UINT16 AriForwarding : 1;\r
+ UINT16 AtomicOpRequester : 1;\r
+ UINT16 AtomicOpEgressBlocking : 1;\r
+ UINT16 IdoRequest : 1;\r
+ UINT16 IdoCompletion : 1;\r
+ UINT16 LtrMechanism : 1;\r
+ UINT16 EmergencyPowerReductionRequest : 1;\r
+ UINT16 TenBitTagRequesterEnable : 1;\r
+ UINT16 Obff : 2;\r
+ UINT16 EndEndTlpPrefixBlocking : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_DEVICE_CONTROL2;\r
\r
-#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
-#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
-#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
-#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
-#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
-#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
-#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
-#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
-#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
-\r
-#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
-#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
-#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
+#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r
+#define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r
+#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r
+#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r
+#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r
+#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r
+#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r
+#define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r
+#define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r
+\r
+#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r
+#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r
+#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 1;\r
- UINT32 LinkSpeedsVector : 7;\r
- UINT32 Crosslink : 1;\r
- UINT32 Reserved2 : 23;\r
+ UINT32 Reserved : 1;\r
+ UINT32 LinkSpeedsVector : 7;\r
+ UINT32 Crosslink : 1;\r
+ UINT32 Reserved2 : 23;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_REG_PCIE_LINK_CAPABILITY2;\r
\r
typedef union {\r
struct {\r
- UINT16 TargetLinkSpeed : 4;\r
- UINT16 EnterCompliance : 1;\r
- UINT16 HardwareAutonomousSpeedDisable : 1;\r
- UINT16 SelectableDeemphasis : 1;\r
- UINT16 TransmitMargin : 3;\r
- UINT16 EnterModifiedCompliance : 1;\r
- UINT16 ComplianceSos : 1;\r
- UINT16 CompliancePresetDeemphasis : 4;\r
+ UINT16 TargetLinkSpeed : 4;\r
+ UINT16 EnterCompliance : 1;\r
+ UINT16 HardwareAutonomousSpeedDisable : 1;\r
+ UINT16 SelectableDeemphasis : 1;\r
+ UINT16 TransmitMargin : 3;\r
+ UINT16 EnterModifiedCompliance : 1;\r
+ UINT16 ComplianceSos : 1;\r
+ UINT16 CompliancePresetDeemphasis : 4;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_CONTROL2;\r
\r
typedef union {\r
struct {\r
- UINT16 CurrentDeemphasisLevel : 1;\r
- UINT16 EqualizationComplete : 1;\r
- UINT16 EqualizationPhase1Successful : 1;\r
- UINT16 EqualizationPhase2Successful : 1;\r
- UINT16 EqualizationPhase3Successful : 1;\r
- UINT16 LinkEqualizationRequest : 1;\r
- UINT16 Reserved : 10;\r
+ UINT16 CurrentDeemphasisLevel : 1;\r
+ UINT16 EqualizationComplete : 1;\r
+ UINT16 EqualizationPhase1Successful : 1;\r
+ UINT16 EqualizationPhase2Successful : 1;\r
+ UINT16 EqualizationPhase3Successful : 1;\r
+ UINT16 LinkEqualizationRequest : 1;\r
+ UINT16 Reserved : 10;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_REG_PCIE_LINK_STATUS2;\r
\r
typedef struct {\r
- EFI_PCI_CAPABILITY_HDR Hdr;\r
- PCI_REG_PCIE_CAPABILITY Capability;\r
- PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
- PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
- PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
- PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
- PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
- PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
- PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
- PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
- PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
- PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
- PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
- PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
- PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
- PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
- UINT16 DeviceStatus2;\r
- PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
- PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
- PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
- UINT32 SlotCapability2;\r
- UINT16 SlotControl2;\r
- UINT16 SlotStatus2;\r
+ EFI_PCI_CAPABILITY_HDR Hdr;\r
+ PCI_REG_PCIE_CAPABILITY Capability;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r
+ PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r
+ PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r
+ PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r
+ PCI_REG_PCIE_LINK_CONTROL LinkControl;\r
+ PCI_REG_PCIE_LINK_STATUS LinkStatus;\r
+ PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r
+ PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r
+ PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r
+ PCI_REG_PCIE_ROOT_CONTROL RootControl;\r
+ PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r
+ PCI_REG_PCIE_ROOT_STATUS RootStatus;\r
+ PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r
+ PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r
+ UINT16 DeviceStatus2;\r
+ PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r
+ PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r
+ PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r
+ UINT32 SlotCapability2;\r
+ UINT16 SlotControl2;\r
+ UINT16 SlotStatus2;\r
} PCI_CAPABILITY_PCIEXP;\r
\r
-#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
-#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
+#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r
+#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r
\r
//\r
// for SR-IOV\r
//\r
-#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
-#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
-#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
+#define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r
+#define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r
+#define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r
\r
typedef struct {\r
- UINT32 CapabilityHeader;\r
- UINT32 Capability;\r
- UINT16 Control;\r
- UINT16 Status;\r
- UINT16 InitialVFs;\r
- UINT16 TotalVFs;\r
- UINT16 NumVFs;\r
- UINT8 FunctionDependencyLink;\r
- UINT8 Reserved0;\r
- UINT16 FirstVFOffset;\r
- UINT16 VFStride;\r
- UINT16 Reserved1;\r
- UINT16 VFDeviceID;\r
- UINT32 SupportedPageSize;\r
- UINT32 SystemPageSize;\r
- UINT32 VFBar[6];\r
- UINT32 VFMigrationStateArrayOffset;\r
+ UINT32 CapabilityHeader;\r
+ UINT32 Capability;\r
+ UINT16 Control;\r
+ UINT16 Status;\r
+ UINT16 InitialVFs;\r
+ UINT16 TotalVFs;\r
+ UINT16 NumVFs;\r
+ UINT8 FunctionDependencyLink;\r
+ UINT8 Reserved0;\r
+ UINT16 FirstVFOffset;\r
+ UINT16 VFStride;\r
+ UINT16 Reserved1;\r
+ UINT16 VFDeviceID;\r
+ UINT32 SupportedPageSize;\r
+ UINT32 SystemPageSize;\r
+ UINT32 VFBar[6];\r
+ UINT32 VFMigrationStateArrayOffset;\r
} SR_IOV_CAPABILITY_REGISTER;\r
\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
-#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r
+#define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r
\r
typedef struct {\r
- UINT32 CapabilityId:16;\r
- UINT32 CapabilityVersion:4;\r
- UINT32 NextCapabilityOffset:12;\r
+ UINT32 CapabilityId : 16;\r
+ UINT32 CapabilityVersion : 4;\r
+ UINT32 NextCapabilityOffset : 12;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r
\r
-#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
+#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r
\r
typedef union {\r
struct {\r
- UINT32 Undefined : 1;\r
- UINT32 Reserved : 3;\r
- UINT32 DataLinkProtocolError : 1;\r
- UINT32 SurpriseDownError : 1;\r
- UINT32 Reserved2 : 6;\r
- UINT32 PoisonedTlp : 1;\r
- UINT32 FlowControlProtocolError : 1;\r
- UINT32 CompletionTimeout : 1;\r
- UINT32 CompleterAbort : 1;\r
- UINT32 UnexpectedCompletion : 1;\r
- UINT32 ReceiverOverflow : 1;\r
- UINT32 MalformedTlp : 1;\r
- UINT32 EcrcError : 1;\r
- UINT32 UnsupportedRequestError : 1;\r
- UINT32 AcsVoilation : 1;\r
- UINT32 UncorrectableInternalError : 1;\r
- UINT32 McBlockedTlp : 1;\r
- UINT32 AtomicOpEgressBlocked : 1;\r
- UINT32 TlpPrefixBlockedError : 1;\r
- UINT32 Reserved3 : 6;\r
+ UINT32 Undefined : 1;\r
+ UINT32 Reserved : 3;\r
+ UINT32 DataLinkProtocolError : 1;\r
+ UINT32 SurpriseDownError : 1;\r
+ UINT32 Reserved2 : 6;\r
+ UINT32 PoisonedTlp : 1;\r
+ UINT32 FlowControlProtocolError : 1;\r
+ UINT32 CompletionTimeout : 1;\r
+ UINT32 CompleterAbort : 1;\r
+ UINT32 UnexpectedCompletion : 1;\r
+ UINT32 ReceiverOverflow : 1;\r
+ UINT32 MalformedTlp : 1;\r
+ UINT32 EcrcError : 1;\r
+ UINT32 UnsupportedRequestError : 1;\r
+ UINT32 AcsVoilation : 1;\r
+ UINT32 UncorrectableInternalError : 1;\r
+ UINT32 McBlockedTlp : 1;\r
+ UINT32 AtomicOpEgressBlocked : 1;\r
+ UINT32 TlpPrefixBlockedError : 1;\r
+ UINT32 Reserved3 : 6;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
- PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
- UINT32 CorrectableErrorStatus;\r
- UINT32 CorrectableErrorMask;\r
- UINT32 AdvancedErrorCapabilitiesAndControl;\r
- UINT32 HeaderLog[4];\r
- UINT32 RootErrorCommand;\r
- UINT32 RootErrorStatus;\r
- UINT16 ErrorSourceIdentification;\r
- UINT16 CorrectableErrorSourceIdentification;\r
- UINT32 TlpPrefixLog[4];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r
+ PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r
+ UINT32 CorrectableErrorStatus;\r
+ UINT32 CorrectableErrorMask;\r
+ UINT32 AdvancedErrorCapabilitiesAndControl;\r
+ UINT32 HeaderLog[4];\r
+ UINT32 RootErrorCommand;\r
+ UINT32 RootErrorStatus;\r
+ UINT16 ErrorSourceIdentification;\r
+ UINT16 CorrectableErrorSourceIdentification;\r
+ UINT32 TlpPrefixLog[4];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r
\r
typedef struct {\r
- UINT32 VcResourceCapability:24;\r
- UINT32 PortArbTableOffset:8;\r
- UINT32 VcResourceControl;\r
- UINT16 Reserved1;\r
- UINT16 VcResourceStatus;\r
+ UINT32 VcResourceCapability : 24;\r
+ UINT32 PortArbTableOffset : 8;\r
+ UINT32 VcResourceControl;\r
+ UINT16 Reserved1;\r
+ UINT16 VcResourceStatus;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 ExtendedVcCount:3;\r
- UINT32 PortVcCapability1:29;\r
- UINT32 PortVcCapability2:24;\r
- UINT32 VcArbTableOffset:8;\r
- UINT16 PortVcControl;\r
- UINT16 PortVcStatus;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 ExtendedVcCount : 3;\r
+ UINT32 PortVcCapability1 : 29;\r
+ UINT32 PortVcCapability2 : 24;\r
+ UINT32 VcArbTableOffset : 8;\r
+ UINT16 PortVcControl;\r
+ UINT16 PortVcStatus;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT64 SerialNumber;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT64 SerialNumber;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 ElementSelfDescription;\r
- UINT32 Reserved;\r
- UINT32 LinkEntry[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 ElementSelfDescription;\r
+ UINT32 Reserved;\r
+ UINT32 LinkEntry[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 RootComplexLinkCapabilities;\r
- UINT16 RootComplexLinkControl;\r
- UINT16 RootComplexLinkStatus;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 RootComplexLinkCapabilities;\r
+ UINT16 RootComplexLinkControl;\r
+ UINT16 RootComplexLinkStatus;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 DataSelect:8;\r
- UINT32 Reserved:24;\r
- UINT32 Data;\r
- UINT32 PowerBudgetCapability:1;\r
- UINT32 Reserved2:7;\r
- UINT32 Reserved3:24;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 DataSelect : 8;\r
+ UINT32 Reserved : 24;\r
+ UINT32 Data;\r
+ UINT32 PowerBudgetCapability : 1;\r
+ UINT32 Reserved2 : 7;\r
+ UINT32 Reserved3 : 24;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 AcsCapability;\r
- UINT16 AcsControl;\r
- UINT8 EgressControlVectorArray[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 AcsCapability;\r
+ UINT16 AcsControl;\r
+ UINT8 EgressControlVectorArray[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 AssociationBitmap;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 AssociationBitmap;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r
\r
typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 VendorSpecificHeader;\r
- UINT8 VendorSpecific[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 VendorSpecificHeader;\r
+ UINT8 VendorSpecific[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT32 RcrbCapabilities;\r
- UINT32 RcrbControl;\r
- UINT32 Reserved;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT32 RcrbCapabilities;\r
+ UINT32 RcrbControl;\r
+ UINT32 Reserved;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 MultiCastCapability;\r
- UINT16 MulticastControl;\r
- UINT64 McBaseAddress;\r
- UINT64 McReceiveAddress;\r
- UINT64 McBlockAll;\r
- UINT64 McBlockUntranslated;\r
- UINT64 McOverlayBar;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 MultiCastCapability;\r
+ UINT16 MulticastControl;\r
+ UINT64 McBaseAddress;\r
+ UINT64 McReceiveAddress;\r
+ UINT64 McBlockAll;\r
+ UINT64 McBlockUntranslated;\r
+ UINT64 McOverlayBar;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved:4;\r
- UINT32 BarSizeCapability:28;\r
+ UINT32 Reserved : 4;\r
+ UINT32 BarSizeCapability : 28;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY;\r
\r
-\r
typedef union {\r
struct {\r
- UINT32 BarIndex:3;\r
- UINT32 Reserved:2;\r
- UINT32 ResizableBarNumber:3;\r
- UINT32 BarSize:6;\r
- UINT32 Reserved2:2;\r
- UINT32 BarSizeCapability:16;\r
+ UINT32 BarIndex : 3;\r
+ UINT32 Reserved : 2;\r
+ UINT32 ResizableBarNumber : 3;\r
+ UINT32 BarSize : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 BarSizeCapability : 16;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY ResizableBarCapability;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r
\r
-#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)\r
+#define GET_NUMBER_RESIZABLE_BARS(x) (x->Capability[0].ResizableBarControl.Bits.ResizableBarNumber)\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 AriCapability;\r
- UINT16 AriControl;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 AriCapability;\r
+ UINT16 AriControl;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 DpaCapability;\r
- UINT32 DpaLatencyIndicator;\r
- UINT16 DpaStatus;\r
- UINT16 DpaControl;\r
- UINT8 DpaPowerAllocationArray[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 DpaCapability;\r
+ UINT32 DpaLatencyIndicator;\r
+ UINT16 DpaStatus;\r
+ UINT16 DpaControl;\r
+ UINT8 DpaPowerAllocationArray[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r
\r
-#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
-\r
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT16 MaxSnoopLatency;\r
- UINT16 MaxNoSnoopLatency;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT16 MaxSnoopLatency;\r
+ UINT16 MaxNoSnoopLatency;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r
\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- UINT32 TphRequesterCapability;\r
- UINT32 TphRequesterControl;\r
- UINT16 TphStTable[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ UINT32 TphRequesterCapability;\r
+ UINT32 TphRequesterControl;\r
+ UINT16 TphStTable[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r
\r
-#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
+#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r
\r
#pragma pack()\r
\r
\r
typedef union {\r
struct {\r
- UINT32 PerformEqualization : 1;\r
- UINT32 LinkEqualizationRequestInterruptEnable : 1;\r
- UINT32 Reserved : 30;\r
+ UINT32 PerformEqualization : 1;\r
+ UINT32 LinkEqualizationRequestInterruptEnable : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_LINK_CONTROL3;\r
\r
typedef union {\r
struct {\r
- UINT16 DownstreamPortTransmitterPreset : 4;\r
- UINT16 DownstreamPortReceiverPresetHint : 3;\r
- UINT16 Reserved : 1;\r
- UINT16 UpstreamPortTransmitterPreset : 4;\r
- UINT16 UpstreamPortReceiverPresetHint : 3;\r
- UINT16 Reserved2 : 1;\r
+ UINT16 DownstreamPortTransmitterPreset : 4;\r
+ UINT16 DownstreamPortReceiverPresetHint : 3;\r
+ UINT16 Reserved : 1;\r
+ UINT16 UpstreamPortTransmitterPreset : 4;\r
+ UINT16 UpstreamPortReceiverPresetHint : 3;\r
+ UINT16 Reserved2 : 1;\r
} Bits;\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\r
- UINT32 LaneErrorStatus;\r
- PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\r
+ UINT32 LaneErrorStatus;\r
+ PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;\r
\r
#pragma pack()\r
\r
typedef union {\r
struct {\r
- UINT32 PciPmL12 : 1;\r
- UINT32 PciPmL11 : 1;\r
- UINT32 AspmL12 : 1;\r
- UINT32 AspmL11 : 1;\r
- UINT32 L1PmSubstates : 1;\r
- UINT32 Reserved : 3;\r
- UINT32 CommonModeRestoreTime : 8;\r
- UINT32 TPowerOnScale : 2;\r
- UINT32 Reserved2 : 1;\r
- UINT32 TPowerOnValue : 5;\r
- UINT32 Reserved3 : 8;\r
+ UINT32 PciPmL12 : 1;\r
+ UINT32 PciPmL11 : 1;\r
+ UINT32 AspmL12 : 1;\r
+ UINT32 AspmL11 : 1;\r
+ UINT32 L1PmSubstates : 1;\r
+ UINT32 Reserved : 3;\r
+ UINT32 CommonModeRestoreTime : 8;\r
+ UINT32 TPowerOnScale : 2;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 TPowerOnValue : 5;\r
+ UINT32 Reserved3 : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;\r
\r
typedef union {\r
struct {\r
- UINT32 PciPmL12 : 1;\r
- UINT32 PciPmL11 : 1;\r
- UINT32 AspmL12 : 1;\r
- UINT32 AspmL11 : 1;\r
- UINT32 Reserved : 4;\r
- UINT32 CommonModeRestoreTime : 8;\r
- UINT32 LtrL12ThresholdValue : 10;\r
- UINT32 Reserved2 : 3;\r
- UINT32 LtrL12ThresholdScale : 3;\r
+ UINT32 PciPmL12 : 1;\r
+ UINT32 PciPmL11 : 1;\r
+ UINT32 AspmL12 : 1;\r
+ UINT32 AspmL11 : 1;\r
+ UINT32 Reserved : 4;\r
+ UINT32 CommonModeRestoreTime : 8;\r
+ UINT32 LtrL12ThresholdValue : 10;\r
+ UINT32 Reserved2 : 3;\r
+ UINT32 LtrL12ThresholdScale : 3;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;\r
\r
typedef union {\r
struct {\r
- UINT32 TPowerOnScale : 2;\r
- UINT32 Reserved : 1;\r
- UINT32 TPowerOnValue : 5;\r
- UINT32 Reserved2 : 24;\r
+ UINT32 TPowerOnScale : 2;\r
+ UINT32 Reserved : 1;\r
+ UINT32 TPowerOnValue : 5;\r
+ UINT32 Reserved2 : 24;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\r
- PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;\r
+ PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;\r
\r
#pragma pack()\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1\r
\r
// Register offsets from Physical Layer PCI-E Ext Cap Header\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 32; // Reserved bit 0:31\r
+ UINT32 Reserved : 32; // Reserved bit 0:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;\r
\r
typedef union {\r
struct {\r
- UINT32 Reserved : 32; // Reserved bit 0:31\r
+ UINT32 Reserved : 32; // Reserved bit 0:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT32 EqualizationComplete : 1; // bit 0\r
- UINT32 EqualizationPhase1Success : 1; // bit 1\r
- UINT32 EqualizationPhase2Success : 1; // bit 2\r
- UINT32 EqualizationPhase3Success : 1; // bit 3\r
- UINT32 LinkEqualizationRequest : 1; // bit 4\r
- UINT32 Reserved : 27; // Reserved bit 5:31\r
+ UINT32 EqualizationComplete : 1; // bit 0\r
+ UINT32 EqualizationPhase1Success : 1; // bit 1\r
+ UINT32 EqualizationPhase2Success : 1; // bit 2\r
+ UINT32 EqualizationPhase3Success : 1; // bit 3\r
+ UINT32 LinkEqualizationRequest : 1; // bit 4\r
+ UINT32 Reserved : 27; // Reserved bit 5:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r
- UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7\r
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\r
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\r
- UINT32 LocalDataParityMismatchStatus;\r
- UINT32 FirstRetimerDataParityMismatchStatus;\r
- UINT32 SecondRetimerDataParityMismatchStatus;\r
- UINT32 Reserved;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;\r
+ UINT32 LocalDataParityMismatchStatus;\r
+ UINT32 FirstRetimerDataParityMismatchStatus;\r
+ UINT32 SecondRetimerDataParityMismatchStatus;\r
+ UINT32 Reserved;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;\r
///@}\r
\r
///@{\r
typedef union {\r
struct {\r
- UINT32 DvsecVendorId : 16; //bit 0..15\r
- UINT32 DvsecRevision : 4; //bit 16..19\r
- UINT32 DvsecLength : 12; //bit 20..31\r
- }Bits;\r
- UINT32 Uint32;\r
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
+ UINT32 DvsecVendorId : 16; // bit 0..15\r
+ UINT32 DvsecRevision : 4; // bit 16..19\r
+ UINT32 DvsecLength : 12; // bit 20..31\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;\r
\r
typedef union {\r
struct {\r
- UINT16 DvsecId : 16; //bit 0..15\r
- }Bits;\r
- UINT16 Uint16;\r
-}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
+ UINT16 DvsecId : 16; // bit 0..15\r
+ } Bits;\r
+ UINT16 Uint16;\r
+} PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;\r
- PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;\r
- UINT8 DesignatedVendorSpecific[1];\r
-}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1;\r
+ PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2;\r
+ UINT8 DesignatedVendorSpecific[1];\r
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;\r
///@}\r
\r
#pragma pack()\r
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1\r
\r
// Register offsets from Physical Layer PCI-E Ext Cap Header\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C\r
-#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C\r
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20\r
\r
typedef union {\r
struct {\r
- UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0\r
- UINT32 NoEqualizationNeededSupport : 1; // bit 1\r
- UINT32 Reserved1 : 6; // Reserved bit 2:7\r
- UINT32 ModifiedTSUsageMode0Support : 1; // bit 8\r
- UINT32 ModifiedTSUsageMode1Support : 1; // bit 9\r
- UINT32 ModifiedTSUsageMode2Support : 1; // bit 10\r
- UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15\r
- UINT32 Reserved2 : 16; // Reserved bit 16:31\r
+ UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0\r
+ UINT32 NoEqualizationNeededSupport : 1; // bit 1\r
+ UINT32 Reserved1 : 6; // Reserved bit 2:7\r
+ UINT32 ModifiedTSUsageMode0Support : 1; // bit 8\r
+ UINT32 ModifiedTSUsageMode1Support : 1; // bit 9\r
+ UINT32 ModifiedTSUsageMode2Support : 1; // bit 10\r
+ UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15\r
+ UINT32 Reserved2 : 16; // Reserved bit 16:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;\r
\r
typedef union {\r
struct {\r
- UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0\r
- UINT32 NoEqualizationNeededDisable : 1; // bit 1\r
- UINT32 Reserved1 : 6; // Reserved bit 2:7\r
- UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10\r
- UINT32 Reserved2 : 21; // Reserved bit 11:31\r
+ UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0\r
+ UINT32 NoEqualizationNeededDisable : 1; // bit 1\r
+ UINT32 Reserved1 : 6; // Reserved bit 2:7\r
+ UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10\r
+ UINT32 Reserved2 : 21; // Reserved bit 11:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT32 EqualizationComplete : 1; // bit 0\r
- UINT32 EqualizationPhase1Success : 1; // bit 1\r
- UINT32 EqualizationPhase2Success : 1; // bit 2\r
- UINT32 EqualizationPhase3Success : 1; // bit 3\r
- UINT32 LinkEqualizationRequest : 1; // bit 4\r
- UINT32 ModifiedTSRcvd : 1; // bit 5\r
- UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7\r
- UINT32 TransmitterPrecodingOn : 1; // bit 8\r
- UINT32 TransmitterPrecodeRequest : 1; // bit 9\r
- UINT32 NoEqualizationNeededRcvd : 1; // bit 10\r
- UINT32 Reserved : 21; // Reserved bit 11:31\r
+ UINT32 EqualizationComplete : 1; // bit 0\r
+ UINT32 EqualizationPhase1Success : 1; // bit 1\r
+ UINT32 EqualizationPhase2Success : 1; // bit 2\r
+ UINT32 EqualizationPhase3Success : 1; // bit 3\r
+ UINT32 LinkEqualizationRequest : 1; // bit 4\r
+ UINT32 ModifiedTSRcvd : 1; // bit 5\r
+ UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7\r
+ UINT32 TransmitterPrecodingOn : 1; // bit 8\r
+ UINT32 TransmitterPrecodeRequest : 1; // bit 9\r
+ UINT32 NoEqualizationNeededRcvd : 1; // bit 10\r
+ UINT32 Reserved : 21; // Reserved bit 11:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;\r
\r
typedef union {\r
struct {\r
- UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2\r
- UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15\r
- UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31\r
+ UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2\r
+ UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15\r
+ UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;\r
\r
typedef union {\r
struct {\r
- UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23\r
- UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
- UINT32 Reserved : 6; // Reserved bit 26:31\r
+ UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23\r
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
+ UINT32 Reserved : 6; // Reserved bit 26:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;\r
\r
typedef union {\r
struct {\r
- UINT32 TransModifiedTSUsageMode : 3; // bit 0:2\r
- UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15\r
- UINT32 TransModifiedTSVendorId : 16; // bit 16:31\r
+ UINT32 TransModifiedTSUsageMode : 3; // bit 0:2\r
+ UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15\r
+ UINT32 TransModifiedTSVendorId : 16; // bit 16:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;\r
\r
typedef union {\r
struct {\r
- UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23\r
- UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
- UINT32 Reserved : 6; // Reserved bit 26:31\r
+ UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23\r
+ UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25\r
+ UINT32 Reserved : 6; // Reserved bit 26:31\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;\r
\r
typedef union {\r
struct {\r
- UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3\r
- UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7\r
+ UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3\r
+ UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7\r
} Bits;\r
- UINT8 Uint8;\r
+ UINT8 Uint8;\r
} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;\r
\r
typedef struct {\r
- PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;\r
- PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;\r
+ PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];\r
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;\r
///@}\r
\r
//\r
// PE32+ Subsystem type for EFI images\r
//\r
-#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10\r
-#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11\r
-#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12\r
-#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13 ///< defined PI Specification, 1.0\r
-\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION 10\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11\r
+#define EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12\r
+#define EFI_IMAGE_SUBSYSTEM_SAL_RUNTIME_DRIVER 13///< defined PI Specification, 1.0\r
\r
//\r
// PE32+ Machine type for EFI images\r
/// under DOS it can print an error message.\r
///\r
typedef struct {\r
- UINT16 e_magic; ///< Magic number.\r
- UINT16 e_cblp; ///< Bytes on last page of file.\r
- UINT16 e_cp; ///< Pages in file.\r
- UINT16 e_crlc; ///< Relocations.\r
- UINT16 e_cparhdr; ///< Size of header in paragraphs.\r
- UINT16 e_minalloc; ///< Minimum extra paragraphs needed.\r
- UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.\r
- UINT16 e_ss; ///< Initial (relative) SS value.\r
- UINT16 e_sp; ///< Initial SP value.\r
- UINT16 e_csum; ///< Checksum.\r
- UINT16 e_ip; ///< Initial IP value.\r
- UINT16 e_cs; ///< Initial (relative) CS value.\r
- UINT16 e_lfarlc; ///< File address of relocation table.\r
- UINT16 e_ovno; ///< Overlay number.\r
- UINT16 e_res[4]; ///< Reserved words.\r
- UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).\r
- UINT16 e_oeminfo; ///< OEM information; e_oemid specific.\r
- UINT16 e_res2[10]; ///< Reserved words.\r
- UINT32 e_lfanew; ///< File address of new exe header.\r
+ UINT16 e_magic; ///< Magic number.\r
+ UINT16 e_cblp; ///< Bytes on last page of file.\r
+ UINT16 e_cp; ///< Pages in file.\r
+ UINT16 e_crlc; ///< Relocations.\r
+ UINT16 e_cparhdr; ///< Size of header in paragraphs.\r
+ UINT16 e_minalloc; ///< Minimum extra paragraphs needed.\r
+ UINT16 e_maxalloc; ///< Maximum extra paragraphs needed.\r
+ UINT16 e_ss; ///< Initial (relative) SS value.\r
+ UINT16 e_sp; ///< Initial SP value.\r
+ UINT16 e_csum; ///< Checksum.\r
+ UINT16 e_ip; ///< Initial IP value.\r
+ UINT16 e_cs; ///< Initial (relative) CS value.\r
+ UINT16 e_lfarlc; ///< File address of relocation table.\r
+ UINT16 e_ovno; ///< Overlay number.\r
+ UINT16 e_res[4]; ///< Reserved words.\r
+ UINT16 e_oemid; ///< OEM identifier (for e_oeminfo).\r
+ UINT16 e_oeminfo; ///< OEM information; e_oemid specific.\r
+ UINT16 e_res2[10]; ///< Reserved words.\r
+ UINT32 e_lfanew; ///< File address of new exe header.\r
} EFI_IMAGE_DOS_HEADER;\r
\r
///\r
/// COFF File Header (Object and Image).\r
///\r
typedef struct {\r
- UINT16 Machine;\r
- UINT16 NumberOfSections;\r
- UINT32 TimeDateStamp;\r
- UINT32 PointerToSymbolTable;\r
- UINT32 NumberOfSymbols;\r
- UINT16 SizeOfOptionalHeader;\r
- UINT16 Characteristics;\r
+ UINT16 Machine;\r
+ UINT16 NumberOfSections;\r
+ UINT32 TimeDateStamp;\r
+ UINT32 PointerToSymbolTable;\r
+ UINT32 NumberOfSymbols;\r
+ UINT16 SizeOfOptionalHeader;\r
+ UINT16 Characteristics;\r
} EFI_IMAGE_FILE_HEADER;\r
\r
///\r
/// Size of EFI_IMAGE_FILE_HEADER.\r
///\r
-#define EFI_IMAGE_SIZEOF_FILE_HEADER 20\r
+#define EFI_IMAGE_SIZEOF_FILE_HEADER 20\r
\r
//\r
// Characteristics\r
/// Header Data Directories.\r
///\r
typedef struct {\r
- UINT32 VirtualAddress;\r
- UINT32 Size;\r
+ UINT32 VirtualAddress;\r
+ UINT32 Size;\r
} EFI_IMAGE_DATA_DIRECTORY;\r
\r
//\r
// Directory Entries\r
//\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9\r
-#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXPORT 0\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_IMPORT 1\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE 2\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION 3\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_SECURITY 4\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC 5\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT 7\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR 8\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_TLS 9\r
+#define EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG 10\r
\r
-#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16\r
+#define EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES 16\r
\r
///\r
/// @attention\r
/// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary\r
/// after NT additional fields.\r
///\r
-#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b\r
+#define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b\r
\r
///\r
/// Optional Header Standard Fields for PE32.\r
///\r
/// Standard fields.\r
///\r
- UINT16 Magic;\r
- UINT8 MajorLinkerVersion;\r
- UINT8 MinorLinkerVersion;\r
- UINT32 SizeOfCode;\r
- UINT32 SizeOfInitializedData;\r
- UINT32 SizeOfUninitializedData;\r
- UINT32 AddressOfEntryPoint;\r
- UINT32 BaseOfCode;\r
- UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.\r
+ UINT16 Magic;\r
+ UINT8 MajorLinkerVersion;\r
+ UINT8 MinorLinkerVersion;\r
+ UINT32 SizeOfCode;\r
+ UINT32 SizeOfInitializedData;\r
+ UINT32 SizeOfUninitializedData;\r
+ UINT32 AddressOfEntryPoint;\r
+ UINT32 BaseOfCode;\r
+ UINT32 BaseOfData; ///< PE32 contains this additional field, which is absent in PE32+.\r
///\r
/// Optional Header Windows-Specific Fields.\r
///\r
- UINT32 ImageBase;\r
- UINT32 SectionAlignment;\r
- UINT32 FileAlignment;\r
- UINT16 MajorOperatingSystemVersion;\r
- UINT16 MinorOperatingSystemVersion;\r
- UINT16 MajorImageVersion;\r
- UINT16 MinorImageVersion;\r
- UINT16 MajorSubsystemVersion;\r
- UINT16 MinorSubsystemVersion;\r
- UINT32 Win32VersionValue;\r
- UINT32 SizeOfImage;\r
- UINT32 SizeOfHeaders;\r
- UINT32 CheckSum;\r
- UINT16 Subsystem;\r
- UINT16 DllCharacteristics;\r
- UINT32 SizeOfStackReserve;\r
- UINT32 SizeOfStackCommit;\r
- UINT32 SizeOfHeapReserve;\r
- UINT32 SizeOfHeapCommit;\r
- UINT32 LoaderFlags;\r
- UINT32 NumberOfRvaAndSizes;\r
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
+ UINT32 ImageBase;\r
+ UINT32 SectionAlignment;\r
+ UINT32 FileAlignment;\r
+ UINT16 MajorOperatingSystemVersion;\r
+ UINT16 MinorOperatingSystemVersion;\r
+ UINT16 MajorImageVersion;\r
+ UINT16 MinorImageVersion;\r
+ UINT16 MajorSubsystemVersion;\r
+ UINT16 MinorSubsystemVersion;\r
+ UINT32 Win32VersionValue;\r
+ UINT32 SizeOfImage;\r
+ UINT32 SizeOfHeaders;\r
+ UINT32 CheckSum;\r
+ UINT16 Subsystem;\r
+ UINT16 DllCharacteristics;\r
+ UINT32 SizeOfStackReserve;\r
+ UINT32 SizeOfStackCommit;\r
+ UINT32 SizeOfHeapReserve;\r
+ UINT32 SizeOfHeapCommit;\r
+ UINT32 LoaderFlags;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
} EFI_IMAGE_OPTIONAL_HEADER32;\r
\r
///\r
/// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary\r
/// after NT additional fields.\r
///\r
-#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b\r
+#define EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b\r
\r
///\r
/// Optional Header Standard Fields for PE32+.\r
///\r
/// Standard fields.\r
///\r
- UINT16 Magic;\r
- UINT8 MajorLinkerVersion;\r
- UINT8 MinorLinkerVersion;\r
- UINT32 SizeOfCode;\r
- UINT32 SizeOfInitializedData;\r
- UINT32 SizeOfUninitializedData;\r
- UINT32 AddressOfEntryPoint;\r
- UINT32 BaseOfCode;\r
+ UINT16 Magic;\r
+ UINT8 MajorLinkerVersion;\r
+ UINT8 MinorLinkerVersion;\r
+ UINT32 SizeOfCode;\r
+ UINT32 SizeOfInitializedData;\r
+ UINT32 SizeOfUninitializedData;\r
+ UINT32 AddressOfEntryPoint;\r
+ UINT32 BaseOfCode;\r
///\r
/// Optional Header Windows-Specific Fields.\r
///\r
- UINT64 ImageBase;\r
- UINT32 SectionAlignment;\r
- UINT32 FileAlignment;\r
- UINT16 MajorOperatingSystemVersion;\r
- UINT16 MinorOperatingSystemVersion;\r
- UINT16 MajorImageVersion;\r
- UINT16 MinorImageVersion;\r
- UINT16 MajorSubsystemVersion;\r
- UINT16 MinorSubsystemVersion;\r
- UINT32 Win32VersionValue;\r
- UINT32 SizeOfImage;\r
- UINT32 SizeOfHeaders;\r
- UINT32 CheckSum;\r
- UINT16 Subsystem;\r
- UINT16 DllCharacteristics;\r
- UINT64 SizeOfStackReserve;\r
- UINT64 SizeOfStackCommit;\r
- UINT64 SizeOfHeapReserve;\r
- UINT64 SizeOfHeapCommit;\r
- UINT32 LoaderFlags;\r
- UINT32 NumberOfRvaAndSizes;\r
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
+ UINT64 ImageBase;\r
+ UINT32 SectionAlignment;\r
+ UINT32 FileAlignment;\r
+ UINT16 MajorOperatingSystemVersion;\r
+ UINT16 MinorOperatingSystemVersion;\r
+ UINT16 MajorImageVersion;\r
+ UINT16 MinorImageVersion;\r
+ UINT16 MajorSubsystemVersion;\r
+ UINT16 MinorSubsystemVersion;\r
+ UINT32 Win32VersionValue;\r
+ UINT32 SizeOfImage;\r
+ UINT32 SizeOfHeaders;\r
+ UINT32 CheckSum;\r
+ UINT16 Subsystem;\r
+ UINT16 DllCharacteristics;\r
+ UINT64 SizeOfStackReserve;\r
+ UINT64 SizeOfStackCommit;\r
+ UINT64 SizeOfHeapReserve;\r
+ UINT64 SizeOfHeapCommit;\r
+ UINT32 LoaderFlags;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];\r
} EFI_IMAGE_OPTIONAL_HEADER64;\r
\r
-\r
///\r
/// @attention\r
/// EFI_IMAGE_NT_HEADERS32 is for use ONLY by tools.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- EFI_IMAGE_FILE_HEADER FileHeader;\r
- EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;\r
+ UINT32 Signature;\r
+ EFI_IMAGE_FILE_HEADER FileHeader;\r
+ EFI_IMAGE_OPTIONAL_HEADER32 OptionalHeader;\r
} EFI_IMAGE_NT_HEADERS32;\r
\r
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)\r
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL32_HEADER sizeof (EFI_IMAGE_NT_HEADERS32)\r
\r
///\r
/// @attention\r
/// EFI_IMAGE_HEADERS64 is for use ONLY by tools.\r
///\r
typedef struct {\r
- UINT32 Signature;\r
- EFI_IMAGE_FILE_HEADER FileHeader;\r
- EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;\r
+ UINT32 Signature;\r
+ EFI_IMAGE_FILE_HEADER FileHeader;\r
+ EFI_IMAGE_OPTIONAL_HEADER64 OptionalHeader;\r
} EFI_IMAGE_NT_HEADERS64;\r
\r
-#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)\r
+#define EFI_IMAGE_SIZEOF_NT_OPTIONAL64_HEADER sizeof (EFI_IMAGE_NT_HEADERS64)\r
\r
//\r
// Other Windows Subsystem Values\r
//\r
-#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0\r
-#define EFI_IMAGE_SUBSYSTEM_NATIVE 1\r
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2\r
-#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3\r
-#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5\r
-#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7\r
+#define EFI_IMAGE_SUBSYSTEM_UNKNOWN 0\r
+#define EFI_IMAGE_SUBSYSTEM_NATIVE 1\r
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2\r
+#define EFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3\r
+#define EFI_IMAGE_SUBSYSTEM_OS2_CUI 5\r
+#define EFI_IMAGE_SUBSYSTEM_POSIX_CUI 7\r
\r
///\r
/// Length of ShortName.\r
///\r
-#define EFI_IMAGE_SIZEOF_SHORT_NAME 8\r
+#define EFI_IMAGE_SIZEOF_SHORT_NAME 8\r
\r
///\r
/// Section Table. This table immediately follows the optional header.\r
///\r
typedef struct {\r
- UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];\r
+ UINT8 Name[EFI_IMAGE_SIZEOF_SHORT_NAME];\r
union {\r
- UINT32 PhysicalAddress;\r
- UINT32 VirtualSize;\r
+ UINT32 PhysicalAddress;\r
+ UINT32 VirtualSize;\r
} Misc;\r
- UINT32 VirtualAddress;\r
- UINT32 SizeOfRawData;\r
- UINT32 PointerToRawData;\r
- UINT32 PointerToRelocations;\r
- UINT32 PointerToLinenumbers;\r
- UINT16 NumberOfRelocations;\r
- UINT16 NumberOfLinenumbers;\r
- UINT32 Characteristics;\r
+ UINT32 VirtualAddress;\r
+ UINT32 SizeOfRawData;\r
+ UINT32 PointerToRawData;\r
+ UINT32 PointerToRelocations;\r
+ UINT32 PointerToLinenumbers;\r
+ UINT16 NumberOfRelocations;\r
+ UINT16 NumberOfLinenumbers;\r
+ UINT32 Characteristics;\r
} EFI_IMAGE_SECTION_HEADER;\r
\r
///\r
/// Size of EFI_IMAGE_SECTION_HEADER.\r
///\r
-#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40\r
+#define EFI_IMAGE_SIZEOF_SECTION_HEADER 40\r
\r
//\r
// Section Flags Values\r
//\r
-#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.\r
-#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020\r
-#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040\r
-#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080\r
-\r
-#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.\r
-#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.\r
-#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.\r
-#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000\r
-\r
-#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000\r
-#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000\r
-#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000\r
-#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000\r
-#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000\r
-#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000\r
-#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000\r
-\r
-#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000\r
-#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000\r
-#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000\r
-#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000\r
-#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000\r
-#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000\r
-#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000\r
+#define EFI_IMAGE_SCN_TYPE_NO_PAD BIT3 ///< 0x00000008 ///< Reserved.\r
+#define EFI_IMAGE_SCN_CNT_CODE BIT5 ///< 0x00000020\r
+#define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA BIT6 ///< 0x00000040\r
+#define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA BIT7 ///< 0x00000080\r
+\r
+#define EFI_IMAGE_SCN_LNK_OTHER BIT8 ///< 0x00000100 ///< Reserved.\r
+#define EFI_IMAGE_SCN_LNK_INFO BIT9 ///< 0x00000200 ///< Section contains comments or some other type of information.\r
+#define EFI_IMAGE_SCN_LNK_REMOVE BIT11 ///< 0x00000800 ///< Section contents will not become part of image.\r
+#define EFI_IMAGE_SCN_LNK_COMDAT BIT12 ///< 0x00001000\r
+\r
+#define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000\r
+#define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000\r
+#define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000\r
+#define EFI_IMAGE_SCN_ALIGN_8BYTES BIT22 ///< 0x00400000\r
+#define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000\r
+#define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000\r
+#define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000\r
+\r
+#define EFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 ///< 0x02000000\r
+#define EFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 ///< 0x04000000\r
+#define EFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 ///< 0x08000000\r
+#define EFI_IMAGE_SCN_MEM_SHARED BIT28 ///< 0x10000000\r
+#define EFI_IMAGE_SCN_MEM_EXECUTE BIT29 ///< 0x20000000\r
+#define EFI_IMAGE_SCN_MEM_READ BIT30 ///< 0x40000000\r
+#define EFI_IMAGE_SCN_MEM_WRITE BIT31 ///< 0x80000000\r
\r
///\r
/// Size of a Symbol Table Record.\r
///\r
-#define EFI_IMAGE_SIZEOF_SYMBOL 18\r
+#define EFI_IMAGE_SIZEOF_SYMBOL 18\r
\r
//\r
// Symbols have a section number of the section in which they are\r
// defined. Otherwise, section numbers have the following meanings:\r
//\r
-#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.\r
-#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.\r
-#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.\r
+#define EFI_IMAGE_SYM_UNDEFINED (UINT16) 0 ///< Symbol is undefined or is common.\r
+#define EFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 ///< Symbol is an absolute value.\r
+#define EFI_IMAGE_SYM_DEBUG (UINT16) -2 ///< Symbol is a special debug item.\r
\r
//\r
// Symbol Type (fundamental) values.\r
//\r
-#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.\r
-#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.\r
-#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.\r
-#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.\r
-#define EFI_IMAGE_SYM_TYPE_INT 4\r
-#define EFI_IMAGE_SYM_TYPE_LONG 5\r
-#define EFI_IMAGE_SYM_TYPE_FLOAT 6\r
-#define EFI_IMAGE_SYM_TYPE_DOUBLE 7\r
-#define EFI_IMAGE_SYM_TYPE_STRUCT 8\r
-#define EFI_IMAGE_SYM_TYPE_UNION 9\r
-#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.\r
-#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.\r
-#define EFI_IMAGE_SYM_TYPE_BYTE 12\r
-#define EFI_IMAGE_SYM_TYPE_WORD 13\r
-#define EFI_IMAGE_SYM_TYPE_UINT 14\r
-#define EFI_IMAGE_SYM_TYPE_DWORD 15\r
+#define EFI_IMAGE_SYM_TYPE_NULL 0 ///< no type.\r
+#define EFI_IMAGE_SYM_TYPE_VOID 1 ///< no valid type.\r
+#define EFI_IMAGE_SYM_TYPE_CHAR 2 ///< type character.\r
+#define EFI_IMAGE_SYM_TYPE_SHORT 3 ///< type short integer.\r
+#define EFI_IMAGE_SYM_TYPE_INT 4\r
+#define EFI_IMAGE_SYM_TYPE_LONG 5\r
+#define EFI_IMAGE_SYM_TYPE_FLOAT 6\r
+#define EFI_IMAGE_SYM_TYPE_DOUBLE 7\r
+#define EFI_IMAGE_SYM_TYPE_STRUCT 8\r
+#define EFI_IMAGE_SYM_TYPE_UNION 9\r
+#define EFI_IMAGE_SYM_TYPE_ENUM 10 ///< enumeration.\r
+#define EFI_IMAGE_SYM_TYPE_MOE 11 ///< member of enumeration.\r
+#define EFI_IMAGE_SYM_TYPE_BYTE 12\r
+#define EFI_IMAGE_SYM_TYPE_WORD 13\r
+#define EFI_IMAGE_SYM_TYPE_UINT 14\r
+#define EFI_IMAGE_SYM_TYPE_DWORD 15\r
\r
//\r
// Symbol Type (derived) values.\r
//\r
// Communal selection types.\r
//\r
-#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1\r
-#define EFI_IMAGE_COMDAT_SELECT_ANY 2\r
-#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3\r
-#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4\r
-#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5\r
+#define EFI_IMAGE_COMDAT_SELECT_NODUPLICATES 1\r
+#define EFI_IMAGE_COMDAT_SELECT_ANY 2\r
+#define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE 3\r
+#define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH 4\r
+#define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE 5\r
\r
//\r
// the following values only be referred in PeCoff, not defined in PECOFF.\r
/// Relocation format.\r
///\r
typedef struct {\r
- UINT32 VirtualAddress;\r
- UINT32 SymbolTableIndex;\r
- UINT16 Type;\r
+ UINT32 VirtualAddress;\r
+ UINT32 SymbolTableIndex;\r
+ UINT16 Type;\r
} EFI_IMAGE_RELOCATION;\r
\r
///\r
/// Size of EFI_IMAGE_RELOCATION\r
///\r
-#define EFI_IMAGE_SIZEOF_RELOCATION 10\r
+#define EFI_IMAGE_SIZEOF_RELOCATION 10\r
\r
//\r
// I386 relocation types.\r
//\r
-#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.\r
-#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.\r
-#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.\r
-#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.\r
-#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.\r
-#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.\r
-#define EFI_IMAGE_REL_I386_SECTION 0x000A\r
-#define EFI_IMAGE_REL_I386_SECREL 0x000B\r
-#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.\r
+#define EFI_IMAGE_REL_I386_ABSOLUTE 0x0000 ///< Reference is absolute, no relocation is necessary.\r
+#define EFI_IMAGE_REL_I386_DIR16 0x0001 ///< Direct 16-bit reference to the symbols virtual address.\r
+#define EFI_IMAGE_REL_I386_REL16 0x0002 ///< PC-relative 16-bit reference to the symbols virtual address.\r
+#define EFI_IMAGE_REL_I386_DIR32 0x0006 ///< Direct 32-bit reference to the symbols virtual address.\r
+#define EFI_IMAGE_REL_I386_DIR32NB 0x0007 ///< Direct 32-bit reference to the symbols virtual address, base not included.\r
+#define EFI_IMAGE_REL_I386_SEG12 0x0009 ///< Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.\r
+#define EFI_IMAGE_REL_I386_SECTION 0x000A\r
+#define EFI_IMAGE_REL_I386_SECREL 0x000B\r
+#define EFI_IMAGE_REL_I386_REL32 0x0014 ///< PC-relative 32-bit reference to the symbols virtual address.\r
\r
//\r
// x64 processor relocation types.\r
/// Based relocation format.\r
///\r
typedef struct {\r
- UINT32 VirtualAddress;\r
- UINT32 SizeOfBlock;\r
+ UINT32 VirtualAddress;\r
+ UINT32 SizeOfBlock;\r
} EFI_IMAGE_BASE_RELOCATION;\r
\r
///\r
///\r
/// Relocation types of RISC-V processor.\r
///\r
-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5\r
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7\r
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8\r
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5\r
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7\r
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8\r
\r
///\r
/// Line number format.\r
///\r
typedef struct {\r
union {\r
- UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.\r
- UINT32 VirtualAddress; ///< Virtual address of line number.\r
+ UINT32 SymbolTableIndex; ///< Symbol table index of function name if Linenumber is 0.\r
+ UINT32 VirtualAddress; ///< Virtual address of line number.\r
} Type;\r
- UINT16 Linenumber; ///< Line number.\r
+ UINT16 Linenumber; ///< Line number.\r
} EFI_IMAGE_LINENUMBER;\r
\r
///\r
/// Size of EFI_IMAGE_LINENUMBER.\r
///\r
-#define EFI_IMAGE_SIZEOF_LINENUMBER 6\r
+#define EFI_IMAGE_SIZEOF_LINENUMBER 6\r
\r
//\r
// Archive format.\r
/// Archive Member Headers\r
///\r
typedef struct {\r
- UINT8 Name[16]; ///< File member name - `/' terminated.\r
- UINT8 Date[12]; ///< File member date - decimal.\r
- UINT8 UserID[6]; ///< File member user id - decimal.\r
- UINT8 GroupID[6]; ///< File member group id - decimal.\r
- UINT8 Mode[8]; ///< File member mode - octal.\r
- UINT8 Size[10]; ///< File member size - decimal.\r
- UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).\r
+ UINT8 Name[16]; ///< File member name - `/' terminated.\r
+ UINT8 Date[12]; ///< File member date - decimal.\r
+ UINT8 UserID[6]; ///< File member user id - decimal.\r
+ UINT8 GroupID[6]; ///< File member group id - decimal.\r
+ UINT8 Mode[8]; ///< File member mode - octal.\r
+ UINT8 Size[10]; ///< File member size - decimal.\r
+ UINT8 EndHeader[2]; ///< String to end header. (0x60 0x0A).\r
} EFI_IMAGE_ARCHIVE_MEMBER_HEADER;\r
\r
///\r
/// Size of EFI_IMAGE_ARCHIVE_MEMBER_HEADER.\r
///\r
-#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60\r
-\r
+#define EFI_IMAGE_SIZEOF_ARCHIVE_MEMBER_HDR 60\r
\r
//\r
// DLL Support\r
/// Export Directory Table.\r
///\r
typedef struct {\r
- UINT32 Characteristics;\r
- UINT32 TimeDateStamp;\r
- UINT16 MajorVersion;\r
- UINT16 MinorVersion;\r
- UINT32 Name;\r
- UINT32 Base;\r
- UINT32 NumberOfFunctions;\r
- UINT32 NumberOfNames;\r
- UINT32 AddressOfFunctions;\r
- UINT32 AddressOfNames;\r
- UINT32 AddressOfNameOrdinals;\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT16 MajorVersion;\r
+ UINT16 MinorVersion;\r
+ UINT32 Name;\r
+ UINT32 Base;\r
+ UINT32 NumberOfFunctions;\r
+ UINT32 NumberOfNames;\r
+ UINT32 AddressOfFunctions;\r
+ UINT32 AddressOfNames;\r
+ UINT32 AddressOfNameOrdinals;\r
} EFI_IMAGE_EXPORT_DIRECTORY;\r
\r
///\r
/// Hint/Name Table.\r
///\r
typedef struct {\r
- UINT16 Hint;\r
- UINT8 Name[1];\r
+ UINT16 Hint;\r
+ UINT8 Name[1];\r
} EFI_IMAGE_IMPORT_BY_NAME;\r
\r
///\r
///\r
typedef struct {\r
union {\r
- UINT32 Function;\r
- UINT32 Ordinal;\r
- EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;\r
+ UINT32 Function;\r
+ UINT32 Ordinal;\r
+ EFI_IMAGE_IMPORT_BY_NAME *AddressOfData;\r
} u1;\r
} EFI_IMAGE_THUNK_DATA;\r
\r
-#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.\r
+#define EFI_IMAGE_ORDINAL_FLAG BIT31 ///< Flag for PE32.\r
#define EFI_IMAGE_SNAP_BY_ORDINAL(Ordinal) ((Ordinal & EFI_IMAGE_ORDINAL_FLAG) != 0)\r
#define EFI_IMAGE_ORDINAL(Ordinal) (Ordinal & 0xffff)\r
\r
/// Import Directory Table\r
///\r
typedef struct {\r
- UINT32 Characteristics;\r
- UINT32 TimeDateStamp;\r
- UINT32 ForwarderChain;\r
- UINT32 Name;\r
- EFI_IMAGE_THUNK_DATA *FirstThunk;\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT32 ForwarderChain;\r
+ UINT32 Name;\r
+ EFI_IMAGE_THUNK_DATA *FirstThunk;\r
} EFI_IMAGE_IMPORT_DESCRIPTOR;\r
\r
-\r
///\r
/// Debug Directory Format.\r
///\r
typedef struct {\r
- UINT32 Characteristics;\r
- UINT32 TimeDateStamp;\r
- UINT16 MajorVersion;\r
- UINT16 MinorVersion;\r
- UINT32 Type;\r
- UINT32 SizeOfData;\r
- UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.\r
- UINT32 FileOffset; ///< The file pointer to the debug data.\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT16 MajorVersion;\r
+ UINT16 MinorVersion;\r
+ UINT32 Type;\r
+ UINT32 SizeOfData;\r
+ UINT32 RVA; ///< The address of the debug data when loaded, relative to the image base.\r
+ UINT32 FileOffset; ///< The file pointer to the debug data.\r
} EFI_IMAGE_DEBUG_DIRECTORY_ENTRY;\r
\r
-#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.\r
+#define EFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 ///< The Visual C++ debug information.\r
\r
///\r
/// Debug Data Structure defined in Microsoft C++.\r
///\r
#define CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0')\r
typedef struct {\r
- UINT32 Signature; ///< "NB10"\r
- UINT32 Unknown;\r
- UINT32 Unknown2;\r
- UINT32 Unknown3;\r
+ UINT32 Signature; ///< "NB10"\r
+ UINT32 Unknown;\r
+ UINT32 Unknown2;\r
+ UINT32 Unknown3;\r
//\r
// Filename of .PDB goes here\r
//\r
///\r
#define CODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S')\r
typedef struct {\r
- UINT32 Signature; ///< "RSDS".\r
- UINT32 Unknown;\r
- UINT32 Unknown2;\r
- UINT32 Unknown3;\r
- UINT32 Unknown4;\r
- UINT32 Unknown5;\r
+ UINT32 Signature; ///< "RSDS".\r
+ UINT32 Unknown;\r
+ UINT32 Unknown2;\r
+ UINT32 Unknown3;\r
+ UINT32 Unknown4;\r
+ UINT32 Unknown5;\r
//\r
// Filename of .PDB goes here\r
//\r
} EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY;\r
\r
-\r
///\r
/// Debug Data Structure defined by Apple Mach-O to Coff utility.\r
///\r
/// Resource format.\r
///\r
typedef struct {\r
- UINT32 Characteristics;\r
- UINT32 TimeDateStamp;\r
- UINT16 MajorVersion;\r
- UINT16 MinorVersion;\r
- UINT16 NumberOfNamedEntries;\r
- UINT16 NumberOfIdEntries;\r
+ UINT32 Characteristics;\r
+ UINT32 TimeDateStamp;\r
+ UINT16 MajorVersion;\r
+ UINT16 MinorVersion;\r
+ UINT16 NumberOfNamedEntries;\r
+ UINT16 NumberOfIdEntries;\r
//\r
// Array of EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY entries goes here.\r
//\r
typedef struct {\r
union {\r
struct {\r
- UINT32 NameOffset:31;\r
- UINT32 NameIsString:1;\r
+ UINT32 NameOffset : 31;\r
+ UINT32 NameIsString : 1;\r
} s;\r
- UINT32 Id;\r
+ UINT32 Id;\r
} u1;\r
union {\r
- UINT32 OffsetToData;\r
+ UINT32 OffsetToData;\r
struct {\r
- UINT32 OffsetToDirectory:31;\r
- UINT32 DataIsDirectory:1;\r
+ UINT32 OffsetToDirectory : 31;\r
+ UINT32 DataIsDirectory : 1;\r
} s;\r
} u2;\r
} EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY;\r
/// Resource directory entry for string.\r
///\r
typedef struct {\r
- UINT16 Length;\r
- CHAR16 String[1];\r
+ UINT16 Length;\r
+ CHAR16 String[1];\r
} EFI_IMAGE_RESOURCE_DIRECTORY_STRING;\r
\r
///\r
/// Resource directory entry for data array.\r
///\r
typedef struct {\r
- UINT32 OffsetToData;\r
- UINT32 Size;\r
- UINT32 CodePage;\r
- UINT32 Reserved;\r
+ UINT32 OffsetToData;\r
+ UINT32 Size;\r
+ UINT32 CodePage;\r
+ UINT32 Reserved;\r
} EFI_IMAGE_RESOURCE_DATA_ENTRY;\r
\r
///\r
/// Header format for TE images, defined in the PI Specification, 1.0.\r
///\r
typedef struct {\r
- UINT16 Signature; ///< The signature for TE format = "VZ".\r
- UINT16 Machine; ///< From the original file header.\r
- UINT8 NumberOfSections; ///< From the original file header.\r
- UINT8 Subsystem; ///< From original optional header.\r
- UINT16 StrippedSize; ///< Number of bytes we removed from the header.\r
- UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.\r
- UINT32 BaseOfCode; ///< From original image -- required for ITP debug.\r
- UINT64 ImageBase; ///< From original file header.\r
- EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.\r
+ UINT16 Signature; ///< The signature for TE format = "VZ".\r
+ UINT16 Machine; ///< From the original file header.\r
+ UINT8 NumberOfSections; ///< From the original file header.\r
+ UINT8 Subsystem; ///< From original optional header.\r
+ UINT16 StrippedSize; ///< Number of bytes we removed from the header.\r
+ UINT32 AddressOfEntryPoint; ///< Offset to entry point -- from original optional header.\r
+ UINT32 BaseOfCode; ///< From original image -- required for ITP debug.\r
+ UINT64 ImageBase; ///< From original file header.\r
+ EFI_IMAGE_DATA_DIRECTORY DataDirectory[2]; ///< Only base relocation and debug directory.\r
} EFI_TE_IMAGE_HEADER;\r
\r
-\r
#define EFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z')\r
\r
//\r
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC 0\r
#define EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG 1\r
\r
-\r
///\r
/// Union of PE32, PE32+, and TE headers.\r
///\r
typedef union {\r
- EFI_IMAGE_NT_HEADERS32 Pe32;\r
- EFI_IMAGE_NT_HEADERS64 Pe32Plus;\r
- EFI_TE_IMAGE_HEADER Te;\r
+ EFI_IMAGE_NT_HEADERS32 Pe32;\r
+ EFI_IMAGE_NT_HEADERS64 Pe32Plus;\r
+ EFI_TE_IMAGE_HEADER Te;\r
} EFI_IMAGE_OPTIONAL_HEADER_UNION;\r
\r
typedef union {\r
- EFI_IMAGE_NT_HEADERS32 *Pe32;\r
- EFI_IMAGE_NT_HEADERS64 *Pe32Plus;\r
- EFI_TE_IMAGE_HEADER *Te;\r
- EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;\r
+ EFI_IMAGE_NT_HEADERS32 *Pe32;\r
+ EFI_IMAGE_NT_HEADERS64 *Pe32Plus;\r
+ EFI_TE_IMAGE_HEADER *Te;\r
+ EFI_IMAGE_OPTIONAL_HEADER_UNION *Union;\r
} EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION;\r
\r
#endif\r
//\r
// Commands for all device types\r
//\r
-#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40\r
-#define EFI_SCSI_OP_COMPARE 0x39\r
-#define EFI_SCSI_OP_COPY 0x18\r
-#define EFI_SCSI_OP_COPY_VERIFY 0x3a\r
-#define EFI_SCSI_OP_INQUIRY 0x12\r
-#define EFI_SCSI_OP_LOG_SELECT 0x4c\r
-#define EFI_SCSI_OP_LOG_SENSE 0x4d\r
-#define EFI_SCSI_OP_MODE_SEL6 0x15\r
-#define EFI_SCSI_OP_MODE_SEL10 0x55\r
-#define EFI_SCSI_OP_MODE_SEN6 0x1a\r
-#define EFI_SCSI_OP_MODE_SEN10 0x5a\r
-#define EFI_SCSI_OP_READ_BUFFER 0x3c\r
-#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c\r
-#define EFI_SCSI_OP_REQUEST_SENSE 0x03\r
-#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
-#define EFI_SCSI_OP_TEST_UNIT_READY 0x00\r
-#define EFI_SCSI_OP_WRITE_BUFF 0x3b\r
+#define EFI_SCSI_OP_CHANGE_DEFINITION 0x40\r
+#define EFI_SCSI_OP_COMPARE 0x39\r
+#define EFI_SCSI_OP_COPY 0x18\r
+#define EFI_SCSI_OP_COPY_VERIFY 0x3a\r
+#define EFI_SCSI_OP_INQUIRY 0x12\r
+#define EFI_SCSI_OP_LOG_SELECT 0x4c\r
+#define EFI_SCSI_OP_LOG_SENSE 0x4d\r
+#define EFI_SCSI_OP_MODE_SEL6 0x15\r
+#define EFI_SCSI_OP_MODE_SEL10 0x55\r
+#define EFI_SCSI_OP_MODE_SEN6 0x1a\r
+#define EFI_SCSI_OP_MODE_SEN10 0x5a\r
+#define EFI_SCSI_OP_READ_BUFFER 0x3c\r
+#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c\r
+#define EFI_SCSI_OP_REQUEST_SENSE 0x03\r
+#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
+#define EFI_SCSI_OP_TEST_UNIT_READY 0x00\r
+#define EFI_SCSI_OP_WRITE_BUFF 0x3b\r
\r
//\r
// Additional commands for Direct Access Devices\r
//\r
-#define EFI_SCSI_OP_FORMAT 0x04\r
-#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36\r
-#define EFI_SCSI_OP_PREFETCH 0x34\r
-#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e\r
-#define EFI_SCSI_OP_READ6 0x08\r
-#define EFI_SCSI_OP_READ10 0x28\r
-#define EFI_SCSI_OP_READ16 0x88\r
-#define EFI_SCSI_OP_READ_CAPACITY 0x25\r
-#define EFI_SCSI_OP_READ_CAPACITY16 0x9e\r
-#define EFI_SCSI_OP_READ_DEFECT 0x37\r
-#define EFI_SCSI_OP_READ_LONG 0x3e\r
-#define EFI_SCSI_OP_REASSIGN_BLK 0x07\r
-#define EFI_SCSI_OP_RELEASE 0x17\r
-#define EFI_SCSI_OP_REZERO 0x01\r
-#define EFI_SCSI_OP_SEARCH_DATA_E 0x31\r
-#define EFI_SCSI_OP_SEARCH_DATA_H 0x30\r
-#define EFI_SCSI_OP_SEARCH_DATA_L 0x32\r
-#define EFI_SCSI_OP_SEEK6 0x0b\r
-#define EFI_SCSI_OP_SEEK10 0x2b\r
-#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
-#define EFI_SCSI_OP_SET_LIMIT 0x33\r
-#define EFI_SCSI_OP_START_STOP_UNIT 0x1b\r
-#define EFI_SCSI_OP_SYNC_CACHE 0x35\r
-#define EFI_SCSI_OP_VERIFY 0x2f\r
-#define EFI_SCSI_OP_WRITE6 0x0a\r
-#define EFI_SCSI_OP_WRITE10 0x2a\r
-#define EFI_SCSI_OP_WRITE16 0x8a\r
-#define EFI_SCSI_OP_WRITE_VERIFY 0x2e\r
-#define EFI_SCSI_OP_WRITE_LONG 0x3f\r
-#define EFI_SCSI_OP_WRITE_SAME 0x41\r
-#define EFI_SCSI_OP_UNMAP 0x42\r
+#define EFI_SCSI_OP_FORMAT 0x04\r
+#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36\r
+#define EFI_SCSI_OP_PREFETCH 0x34\r
+#define EFI_SCSI_OP_MEDIA_REMOVAL 0x1e\r
+#define EFI_SCSI_OP_READ6 0x08\r
+#define EFI_SCSI_OP_READ10 0x28\r
+#define EFI_SCSI_OP_READ16 0x88\r
+#define EFI_SCSI_OP_READ_CAPACITY 0x25\r
+#define EFI_SCSI_OP_READ_CAPACITY16 0x9e\r
+#define EFI_SCSI_OP_READ_DEFECT 0x37\r
+#define EFI_SCSI_OP_READ_LONG 0x3e\r
+#define EFI_SCSI_OP_REASSIGN_BLK 0x07\r
+#define EFI_SCSI_OP_RELEASE 0x17\r
+#define EFI_SCSI_OP_REZERO 0x01\r
+#define EFI_SCSI_OP_SEARCH_DATA_E 0x31\r
+#define EFI_SCSI_OP_SEARCH_DATA_H 0x30\r
+#define EFI_SCSI_OP_SEARCH_DATA_L 0x32\r
+#define EFI_SCSI_OP_SEEK6 0x0b\r
+#define EFI_SCSI_OP_SEEK10 0x2b\r
+#define EFI_SCSI_OP_SEND_DIAG 0x1d\r
+#define EFI_SCSI_OP_SET_LIMIT 0x33\r
+#define EFI_SCSI_OP_START_STOP_UNIT 0x1b\r
+#define EFI_SCSI_OP_SYNC_CACHE 0x35\r
+#define EFI_SCSI_OP_VERIFY 0x2f\r
+#define EFI_SCSI_OP_WRITE6 0x0a\r
+#define EFI_SCSI_OP_WRITE10 0x2a\r
+#define EFI_SCSI_OP_WRITE16 0x8a\r
+#define EFI_SCSI_OP_WRITE_VERIFY 0x2e\r
+#define EFI_SCSI_OP_WRITE_LONG 0x3f\r
+#define EFI_SCSI_OP_WRITE_SAME 0x41\r
+#define EFI_SCSI_OP_UNMAP 0x42\r
\r
//\r
// Additional commands for Sequential Access Devices\r
//\r
// Additional commands for Processor Devices\r
//\r
-#define EFI_SCSI_OP_RECEIVE 0x08\r
-#define EFI_SCSI_OP_SEND 0x0a\r
+#define EFI_SCSI_OP_RECEIVE 0x08\r
+#define EFI_SCSI_OP_SEND 0x0a\r
\r
//\r
// Additional commands for Write-Once Devices\r
//\r
// Additional commands for Scanner Devices\r
//\r
-#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34\r
-#define EFI_SCSI_OP_GET_WINDOW 0x25\r
-#define EFI_SCSI_OP_OBJECT_POS 0x31\r
-#define EFI_SCSI_OP_SCAN 0x1b\r
-#define EFI_SCSI_OP_SET_WINDOW 0x24\r
+#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34\r
+#define EFI_SCSI_OP_GET_WINDOW 0x25\r
+#define EFI_SCSI_OP_OBJECT_POS 0x31\r
+#define EFI_SCSI_OP_SCAN 0x1b\r
+#define EFI_SCSI_OP_SET_WINDOW 0x24\r
\r
//\r
// Additional commands for Optical Memory Devices\r
//\r
// Additional commands for Medium Changer Devices\r
//\r
-#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6\r
-#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07\r
-#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b\r
-#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5\r
-#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6\r
+#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6\r
+#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07\r
+#define EFI_SCSI_OP_POS_TO_ELEMENT 0x2b\r
+#define EFI_SCSI_OP_REQUEST_VE_ADDR 0xb5\r
+#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6\r
\r
//\r
// Additional commands for Communication Devices\r
//\r
// Additional commands for Secure Transactions\r
//\r
-#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2\r
-#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5\r
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN 0xa2\r
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5\r
\r
//\r
// SCSI Data Transfer Direction\r
//\r
-#define EFI_SCSI_DATA_IN 0\r
-#define EFI_SCSI_DATA_OUT 1\r
+#define EFI_SCSI_DATA_IN 0\r
+#define EFI_SCSI_DATA_OUT 1\r
\r
//\r
// SCSI Block Command Cache Control Parameters\r
//\r
// Peripheral Device Type Definitions\r
//\r
-#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)\r
-#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)\r
-#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device\r
-#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device\r
-#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)\r
-#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device\r
-#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete)\r
-#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)\r
-#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)\r
-#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete)\r
-#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)\r
-#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)\r
-#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)\r
-#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device\r
-#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)\r
-#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device\r
-#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands\r
-#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device\r
-#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface\r
-#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device\r
-#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low)\r
-#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high)\r
-#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit\r
-#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type\r
+#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)\r
+#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)\r
+#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device\r
+#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device\r
+#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)\r
+#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD/DVD device\r
+#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device (obsolete)\r
+#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)\r
+#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)\r
+#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device (obsolete)\r
+#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)\r
+#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)\r
+#define EFI_SCSI_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)\r
+#define EFI_SCSI_TYPE_SES 0x0D ///< Enclosure services device\r
+#define EFI_SCSI_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)\r
+#define EFI_SCSI_TYPE_OCRW 0x0F ///< Optical card reader/writer device\r
+#define EFI_SCSI_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands\r
+#define EFI_SCSI_TYPE_OSD 0x11 ///< Object-based Storage Device\r
+#define EFI_SCSI_TYPE_AUTOMATION 0x12 ///< Automation/Drive Interface\r
+#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13 ///< Security manager device\r
+#define EFI_SCSI_TYPE_RESERVED_LOW 0x14 ///< Reserved (low)\r
+#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1D ///< Reserved (high)\r
+#define EFI_SCSI_TYPE_WLUN 0x1E ///< Well known logical unit\r
+#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type\r
\r
//\r
// Page Codes for INQUIRY command\r
//\r
-#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00\r
-#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0\r
+#define EFI_SCSI_PAGE_CODE_SUPPORTED_VPD 0x00\r
+#define EFI_SCSI_PAGE_CODE_BLOCK_LIMITS_VPD 0xB0\r
\r
#pragma pack(1)\r
///\r
/// Standard INQUIRY data format\r
///\r
typedef struct {\r
- UINT8 Peripheral_Type : 5;\r
- UINT8 Peripheral_Qualifier : 3;\r
- UINT8 DeviceType_Modifier : 7;\r
- UINT8 Rmb : 1;\r
- UINT8 Version;\r
- UINT8 Response_Data_Format;\r
- UINT8 Addnl_Length;\r
- UINT8 Reserved_5_95[95 - 5 + 1];\r
+ UINT8 Peripheral_Type : 5;\r
+ UINT8 Peripheral_Qualifier : 3;\r
+ UINT8 DeviceType_Modifier : 7;\r
+ UINT8 Rmb : 1;\r
+ UINT8 Version;\r
+ UINT8 Response_Data_Format;\r
+ UINT8 Addnl_Length;\r
+ UINT8 Reserved_5_95[95 - 5 + 1];\r
} EFI_SCSI_INQUIRY_DATA;\r
\r
///\r
/// Supported VPD Pages VPD page\r
///\r
typedef struct {\r
- UINT8 Peripheral_Type : 5;\r
- UINT8 Peripheral_Qualifier : 3;\r
- UINT8 PageCode;\r
- UINT8 PageLength2;\r
- UINT8 PageLength1;\r
- UINT8 SupportedVpdPageList[0x100];\r
+ UINT8 Peripheral_Type : 5;\r
+ UINT8 Peripheral_Qualifier : 3;\r
+ UINT8 PageCode;\r
+ UINT8 PageLength2;\r
+ UINT8 PageLength1;\r
+ UINT8 SupportedVpdPageList[0x100];\r
} EFI_SCSI_SUPPORTED_VPD_PAGES_VPD_PAGE;\r
\r
///\r
/// Block Limits VPD page\r
///\r
typedef struct {\r
- UINT8 Peripheral_Type : 5;\r
- UINT8 Peripheral_Qualifier : 3;\r
- UINT8 PageCode;\r
- UINT8 PageLength2;\r
- UINT8 PageLength1;\r
- UINT8 WriteSameNonZero : 1;\r
- UINT8 Reserved_4 : 7;\r
- UINT8 MaximumCompareAndWriteLength;\r
- UINT8 OptimalTransferLengthGranularity2;\r
- UINT8 OptimalTransferLengthGranularity1;\r
- UINT8 MaximumTransferLength4;\r
- UINT8 MaximumTransferLength3;\r
- UINT8 MaximumTransferLength2;\r
- UINT8 MaximumTransferLength1;\r
- UINT8 OptimalTransferLength4;\r
- UINT8 OptimalTransferLength3;\r
- UINT8 OptimalTransferLength2;\r
- UINT8 OptimalTransferLength1;\r
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;\r
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;\r
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;\r
- UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;\r
- UINT8 MaximumUnmapLbaCount4;\r
- UINT8 MaximumUnmapLbaCount3;\r
- UINT8 MaximumUnmapLbaCount2;\r
- UINT8 MaximumUnmapLbaCount1;\r
- UINT8 MaximumUnmapBlockDescriptorCount4;\r
- UINT8 MaximumUnmapBlockDescriptorCount3;\r
- UINT8 MaximumUnmapBlockDescriptorCount2;\r
- UINT8 MaximumUnmapBlockDescriptorCount1;\r
- UINT8 OptimalUnmapGranularity4;\r
- UINT8 OptimalUnmapGranularity3;\r
- UINT8 OptimalUnmapGranularity2;\r
- UINT8 OptimalUnmapGranularity1;\r
- UINT8 UnmapGranularityAlignment4 : 7;\r
- UINT8 UnmapGranularityAlignmentValid : 1;\r
- UINT8 UnmapGranularityAlignment3;\r
- UINT8 UnmapGranularityAlignment2;\r
- UINT8 UnmapGranularityAlignment1;\r
- UINT8 MaximumWriteSameLength4;\r
- UINT8 MaximumWriteSameLength3;\r
- UINT8 MaximumWriteSameLength2;\r
- UINT8 MaximumWriteSameLength1;\r
- UINT8 MaximumAtomicTransferLength4;\r
- UINT8 MaximumAtomicTransferLength3;\r
- UINT8 MaximumAtomicTransferLength2;\r
- UINT8 MaximumAtomicTransferLength1;\r
- UINT8 AtomicAlignment4;\r
- UINT8 AtomicAlignment3;\r
- UINT8 AtomicAlignment2;\r
- UINT8 AtomicAlignment1;\r
- UINT8 AtomicTransferLengthGranularity4;\r
- UINT8 AtomicTransferLengthGranularity3;\r
- UINT8 AtomicTransferLengthGranularity2;\r
- UINT8 AtomicTransferLengthGranularity1;\r
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;\r
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;\r
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;\r
- UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;\r
- UINT8 MaximumAtomicBoundarySize4;\r
- UINT8 MaximumAtomicBoundarySize3;\r
- UINT8 MaximumAtomicBoundarySize2;\r
- UINT8 MaximumAtomicBoundarySize1;\r
+ UINT8 Peripheral_Type : 5;\r
+ UINT8 Peripheral_Qualifier : 3;\r
+ UINT8 PageCode;\r
+ UINT8 PageLength2;\r
+ UINT8 PageLength1;\r
+ UINT8 WriteSameNonZero : 1;\r
+ UINT8 Reserved_4 : 7;\r
+ UINT8 MaximumCompareAndWriteLength;\r
+ UINT8 OptimalTransferLengthGranularity2;\r
+ UINT8 OptimalTransferLengthGranularity1;\r
+ UINT8 MaximumTransferLength4;\r
+ UINT8 MaximumTransferLength3;\r
+ UINT8 MaximumTransferLength2;\r
+ UINT8 MaximumTransferLength1;\r
+ UINT8 OptimalTransferLength4;\r
+ UINT8 OptimalTransferLength3;\r
+ UINT8 OptimalTransferLength2;\r
+ UINT8 OptimalTransferLength1;\r
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength4;\r
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength3;\r
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength2;\r
+ UINT8 MaximumPrefetchXdreadXdwriteTransferLength1;\r
+ UINT8 MaximumUnmapLbaCount4;\r
+ UINT8 MaximumUnmapLbaCount3;\r
+ UINT8 MaximumUnmapLbaCount2;\r
+ UINT8 MaximumUnmapLbaCount1;\r
+ UINT8 MaximumUnmapBlockDescriptorCount4;\r
+ UINT8 MaximumUnmapBlockDescriptorCount3;\r
+ UINT8 MaximumUnmapBlockDescriptorCount2;\r
+ UINT8 MaximumUnmapBlockDescriptorCount1;\r
+ UINT8 OptimalUnmapGranularity4;\r
+ UINT8 OptimalUnmapGranularity3;\r
+ UINT8 OptimalUnmapGranularity2;\r
+ UINT8 OptimalUnmapGranularity1;\r
+ UINT8 UnmapGranularityAlignment4 : 7;\r
+ UINT8 UnmapGranularityAlignmentValid : 1;\r
+ UINT8 UnmapGranularityAlignment3;\r
+ UINT8 UnmapGranularityAlignment2;\r
+ UINT8 UnmapGranularityAlignment1;\r
+ UINT8 MaximumWriteSameLength4;\r
+ UINT8 MaximumWriteSameLength3;\r
+ UINT8 MaximumWriteSameLength2;\r
+ UINT8 MaximumWriteSameLength1;\r
+ UINT8 MaximumAtomicTransferLength4;\r
+ UINT8 MaximumAtomicTransferLength3;\r
+ UINT8 MaximumAtomicTransferLength2;\r
+ UINT8 MaximumAtomicTransferLength1;\r
+ UINT8 AtomicAlignment4;\r
+ UINT8 AtomicAlignment3;\r
+ UINT8 AtomicAlignment2;\r
+ UINT8 AtomicAlignment1;\r
+ UINT8 AtomicTransferLengthGranularity4;\r
+ UINT8 AtomicTransferLengthGranularity3;\r
+ UINT8 AtomicTransferLengthGranularity2;\r
+ UINT8 AtomicTransferLengthGranularity1;\r
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary4;\r
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary3;\r
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary2;\r
+ UINT8 MaximumAtomicTransferLengthWithAtomicBoundary1;\r
+ UINT8 MaximumAtomicBoundarySize4;\r
+ UINT8 MaximumAtomicBoundarySize3;\r
+ UINT8 MaximumAtomicBoundarySize2;\r
+ UINT8 MaximumAtomicBoundarySize1;\r
} EFI_SCSI_BLOCK_LIMITS_VPD_PAGE;\r
\r
///\r
/// Error codes 70h and 71h sense data format\r
///\r
typedef struct {\r
- UINT8 Error_Code : 7;\r
- UINT8 Valid : 1;\r
- UINT8 Segment_Number;\r
- UINT8 Sense_Key : 4;\r
- UINT8 Reserved_21 : 1;\r
- UINT8 Ili : 1;\r
- UINT8 Reserved_22 : 2;\r
- UINT8 Information_3_6[4];\r
- UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)\r
- UINT8 Vendor_Specific_8_11[4];\r
- UINT8 Addnl_Sense_Code; ///< Additional sense code\r
- UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier\r
- UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code\r
- UINT8 Reserved_15_17[3];\r
+ UINT8 Error_Code : 7;\r
+ UINT8 Valid : 1;\r
+ UINT8 Segment_Number;\r
+ UINT8 Sense_Key : 4;\r
+ UINT8 Reserved_21 : 1;\r
+ UINT8 Ili : 1;\r
+ UINT8 Reserved_22 : 2;\r
+ UINT8 Information_3_6[4];\r
+ UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)\r
+ UINT8 Vendor_Specific_8_11[4];\r
+ UINT8 Addnl_Sense_Code; ///< Additional sense code\r
+ UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier\r
+ UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code\r
+ UINT8 Reserved_15_17[3];\r
} EFI_SCSI_SENSE_DATA;\r
\r
///\r
/// SCSI Disk READ CAPACITY Data\r
///\r
typedef struct {\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 BlockSize3;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
+ UINT8 LastLba3;\r
+ UINT8 LastLba2;\r
+ UINT8 LastLba1;\r
+ UINT8 LastLba0;\r
+ UINT8 BlockSize3;\r
+ UINT8 BlockSize2;\r
+ UINT8 BlockSize1;\r
+ UINT8 BlockSize0;\r
} EFI_SCSI_DISK_CAPACITY_DATA;\r
\r
typedef struct {\r
- UINT8 LastLba7;\r
- UINT8 LastLba6;\r
- UINT8 LastLba5;\r
- UINT8 LastLba4;\r
- UINT8 LastLba3;\r
- UINT8 LastLba2;\r
- UINT8 LastLba1;\r
- UINT8 LastLba0;\r
- UINT8 BlockSize3;\r
- UINT8 BlockSize2;\r
- UINT8 BlockSize1;\r
- UINT8 BlockSize0;\r
- UINT8 Protection;\r
- UINT8 LogicPerPhysical;\r
- UINT8 LowestAlignLogic2;\r
- UINT8 LowestAlignLogic1;\r
- UINT8 Reserved[16];\r
+ UINT8 LastLba7;\r
+ UINT8 LastLba6;\r
+ UINT8 LastLba5;\r
+ UINT8 LastLba4;\r
+ UINT8 LastLba3;\r
+ UINT8 LastLba2;\r
+ UINT8 LastLba1;\r
+ UINT8 LastLba0;\r
+ UINT8 BlockSize3;\r
+ UINT8 BlockSize2;\r
+ UINT8 BlockSize1;\r
+ UINT8 BlockSize0;\r
+ UINT8 Protection;\r
+ UINT8 LogicPerPhysical;\r
+ UINT8 LowestAlignLogic2;\r
+ UINT8 LowestAlignLogic1;\r
+ UINT8 Reserved[16];\r
} EFI_SCSI_DISK_CAPACITY_DATA16;\r
\r
typedef struct {\r
- UINT16 DataLen;\r
- UINT16 BlkDespDataLen;\r
- UINT8 Reserved[4];\r
+ UINT16 DataLen;\r
+ UINT16 BlkDespDataLen;\r
+ UINT8 Reserved[4];\r
} EFI_SCSI_DISK_UNMAP_PARAM_LIST_HEADER;\r
\r
typedef struct {\r
- UINT64 Lba;\r
- UINT32 BlockNum;\r
- UINT8 Reserved[4];\r
+ UINT64 Lba;\r
+ UINT32 BlockNum;\r
+ UINT8 Reserved[4];\r
} EFI_SCSI_DISK_UNMAP_BLOCK_DESP;\r
\r
-\r
#pragma pack()\r
\r
//\r
// Sense Key\r
//\r
-#define EFI_SCSI_SK_NO_SENSE (0x0)\r
-#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)\r
-#define EFI_SCSI_SK_NOT_READY (0x2)\r
-#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)\r
-#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)\r
-#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)\r
-#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)\r
-#define EFI_SCSI_SK_DATA_PROTECT (0x7)\r
-#define EFI_SCSI_SK_BLANK_CHECK (0x8)\r
-#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)\r
-#define EFI_SCSI_SK_RESERVED_A (0xA)\r
-#define EFI_SCSI_SK_ABORT (0xB)\r
-#define EFI_SCSI_SK_RESERVED_C (0xC)\r
-#define EFI_SCSI_SK_OVERFLOW (0xD)\r
-#define EFI_SCSI_SK_MISCOMPARE (0xE)\r
-#define EFI_SCSI_SK_RESERVED_F (0xF)\r
+#define EFI_SCSI_SK_NO_SENSE (0x0)\r
+#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)\r
+#define EFI_SCSI_SK_NOT_READY (0x2)\r
+#define EFI_SCSI_SK_MEDIUM_ERROR (0x3)\r
+#define EFI_SCSI_SK_HARDWARE_ERROR (0x4)\r
+#define EFI_SCSI_SK_ILLEGAL_REQUEST (0x5)\r
+#define EFI_SCSI_SK_UNIT_ATTENTION (0x6)\r
+#define EFI_SCSI_SK_DATA_PROTECT (0x7)\r
+#define EFI_SCSI_SK_BLANK_CHECK (0x8)\r
+#define EFI_SCSI_SK_VENDOR_SPECIFIC (0x9)\r
+#define EFI_SCSI_SK_RESERVED_A (0xA)\r
+#define EFI_SCSI_SK_ABORT (0xB)\r
+#define EFI_SCSI_SK_RESERVED_C (0xC)\r
+#define EFI_SCSI_SK_OVERFLOW (0xD)\r
+#define EFI_SCSI_SK_MISCOMPARE (0xE)\r
+#define EFI_SCSI_SK_RESERVED_F (0xF)\r
\r
//\r
// Additional Sense Codes and Sense Code Qualifiers.\r
// Only some frequently used additional sense codes and qualifiers are\r
// defined here. Please refer to SCSI standard for full value definition.\r
//\r
-#define EFI_SCSI_ASC_NOT_READY (0x04)\r
-#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)\r
+#define EFI_SCSI_ASC_NOT_READY (0x04)\r
+#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)\r
\r
#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)\r
#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)\r
//\r
// SD command index\r
//\r
-#define SD_GO_IDLE_STATE 0\r
-#define SD_ALL_SEND_CID 2\r
-#define SD_SET_RELATIVE_ADDR 3\r
-#define SD_SET_DSR 4\r
-#define SDIO_SEND_OP_COND 5\r
-#define SD_SWITCH_FUNC 6\r
-#define SD_SELECT_DESELECT_CARD 7\r
-#define SD_SEND_IF_COND 8\r
-#define SD_SEND_CSD 9\r
-#define SD_SEND_CID 10\r
-#define SD_VOLTAGE_SWITCH 11\r
-#define SD_STOP_TRANSMISSION 12\r
-#define SD_SEND_STATUS 13\r
-#define SD_GO_INACTIVE_STATE 15\r
-#define SD_SET_BLOCKLEN 16\r
-#define SD_READ_SINGLE_BLOCK 17\r
-#define SD_READ_MULTIPLE_BLOCK 18\r
-#define SD_SEND_TUNING_BLOCK 19\r
-#define SD_SPEED_CLASS_CONTROL 20\r
-#define SD_SET_BLOCK_COUNT 23\r
-#define SD_WRITE_SINGLE_BLOCK 24\r
-#define SD_WRITE_MULTIPLE_BLOCK 25\r
-#define SD_PROGRAM_CSD 27\r
-#define SD_SET_WRITE_PROT 28\r
-#define SD_CLR_WRITE_PROT 29\r
-#define SD_SEND_WRITE_PROT 30\r
-#define SD_ERASE_WR_BLK_START 32\r
-#define SD_ERASE_WR_BLK_END 33\r
-#define SD_ERASE 38\r
-#define SD_LOCK_UNLOCK 42\r
-#define SD_READ_EXTR_SINGLE 48\r
-#define SD_WRITE_EXTR_SINGLE 49\r
-#define SDIO_RW_DIRECT 52\r
-#define SDIO_RW_EXTENDED 53\r
-#define SD_APP_CMD 55\r
-#define SD_GEN_CMD 56\r
-#define SD_READ_EXTR_MULTI 58\r
-#define SD_WRITE_EXTR_MULTI 59\r
+#define SD_GO_IDLE_STATE 0\r
+#define SD_ALL_SEND_CID 2\r
+#define SD_SET_RELATIVE_ADDR 3\r
+#define SD_SET_DSR 4\r
+#define SDIO_SEND_OP_COND 5\r
+#define SD_SWITCH_FUNC 6\r
+#define SD_SELECT_DESELECT_CARD 7\r
+#define SD_SEND_IF_COND 8\r
+#define SD_SEND_CSD 9\r
+#define SD_SEND_CID 10\r
+#define SD_VOLTAGE_SWITCH 11\r
+#define SD_STOP_TRANSMISSION 12\r
+#define SD_SEND_STATUS 13\r
+#define SD_GO_INACTIVE_STATE 15\r
+#define SD_SET_BLOCKLEN 16\r
+#define SD_READ_SINGLE_BLOCK 17\r
+#define SD_READ_MULTIPLE_BLOCK 18\r
+#define SD_SEND_TUNING_BLOCK 19\r
+#define SD_SPEED_CLASS_CONTROL 20\r
+#define SD_SET_BLOCK_COUNT 23\r
+#define SD_WRITE_SINGLE_BLOCK 24\r
+#define SD_WRITE_MULTIPLE_BLOCK 25\r
+#define SD_PROGRAM_CSD 27\r
+#define SD_SET_WRITE_PROT 28\r
+#define SD_CLR_WRITE_PROT 29\r
+#define SD_SEND_WRITE_PROT 30\r
+#define SD_ERASE_WR_BLK_START 32\r
+#define SD_ERASE_WR_BLK_END 33\r
+#define SD_ERASE 38\r
+#define SD_LOCK_UNLOCK 42\r
+#define SD_READ_EXTR_SINGLE 48\r
+#define SD_WRITE_EXTR_SINGLE 49\r
+#define SDIO_RW_DIRECT 52\r
+#define SDIO_RW_EXTENDED 53\r
+#define SD_APP_CMD 55\r
+#define SD_GEN_CMD 56\r
+#define SD_READ_EXTR_MULTI 58\r
+#define SD_WRITE_EXTR_MULTI 59\r
\r
#define SD_SET_BUS_WIDTH 6 // ACMD6\r
#define SD_STATUS 13 // ACMD13\r
\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 NotUsed:1; // Not used [0:0]\r
- UINT8 Crc:7; // CRC [7:1]\r
- UINT16 ManufacturingDate:12; // Manufacturing date [19:8]\r
- UINT16 Reserved:4; // Reserved [23:20]\r
- UINT8 ProductSerialNumber[4]; // Product serial number [55:24]\r
- UINT8 ProductRevision; // Product revision [63:56]\r
- UINT8 ProductName[5]; // Product name [103:64]\r
- UINT8 OemId[2]; // OEM/Application ID [119:104]\r
- UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
+ UINT8 NotUsed : 1; // Not used [0:0]\r
+ UINT8 Crc : 7; // CRC [7:1]\r
+ UINT16 ManufacturingDate : 12; // Manufacturing date [19:8]\r
+ UINT16 Reserved : 4; // Reserved [23:20]\r
+ UINT8 ProductSerialNumber[4]; // Product serial number [55:24]\r
+ UINT8 ProductRevision; // Product revision [63:56]\r
+ UINT8 ProductName[5]; // Product name [103:64]\r
+ UINT8 OemId[2]; // OEM/Application ID [119:104]\r
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
} SD_CID;\r
\r
typedef struct {\r
- UINT32 NotUsed:1; // Not used [0:0]\r
- UINT32 Crc:7; // CRC [7:1]\r
- UINT32 Reserved:2; // Reserved [9:8]\r
- UINT32 FileFormat:2; // File format [11:10]\r
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
- UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
- UINT32 FileFormatGrp:1; // File format group [15:15]\r
- UINT32 Reserved1:5; // Reserved [20:16]\r
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
- UINT32 R2WFactor:3; // Write speed factor [28:26]\r
- UINT32 Reserved2:2; // Manufacturer default ECC [30:29]\r
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
-\r
- UINT32 WpGrpSize:7; // Write protect group size [38:32]\r
- UINT32 SectorSize:7; // Erase sector size [45:39]\r
- UINT32 EraseBlkEn:1; // Erase single block enable [46:46]\r
- UINT32 CSizeMul:3; // device size multiplier [49:47]\r
- UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50]\r
- UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53]\r
- UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56]\r
- UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59]\r
- UINT32 CSizeLow:2; // Device size low 2 bits [63:62]\r
-\r
- UINT32 CSizeHigh:10; // Device size high 10 bits [73:64]\r
- UINT32 Reserved4:2; // Reserved [75:74]\r
- UINT32 DsrImp:1; // DSR implemented [76:76]\r
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
- UINT32 Ccc:12; // Card command classes [95:84]\r
-\r
- UINT32 TranSpeed:8; // Max. data transfer rate [103:96]\r
- UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
- UINT32 Taac:8; // Data read access-time [119:112]\r
- UINT32 Reserved5:6; // Reserved [125:120]\r
- UINT32 CsdStructure:2; // CSD structure [127:126]\r
+ UINT32 NotUsed : 1; // Not used [0:0]\r
+ UINT32 Crc : 7; // CRC [7:1]\r
+ UINT32 Reserved : 2; // Reserved [9:8]\r
+ UINT32 FileFormat : 2; // File format [11:10]\r
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]\r
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp : 1; // File format group [15:15]\r
+ UINT32 Reserved1 : 5; // Reserved [20:16]\r
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]\r
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]\r
+\r
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]\r
+ UINT32 SectorSize : 7; // Erase sector size [45:39]\r
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]\r
+ UINT32 CSizeMul : 3; // device size multiplier [49:47]\r
+ UINT32 VddWCurrMax : 3; // max. write current @VDD max [52:50]\r
+ UINT32 VddWCurrMin : 3; // max. write current @VDD min [55:53]\r
+ UINT32 VddRCurrMax : 3; // max. read current @VDD max [58:56]\r
+ UINT32 VddRCurrMin : 3; // max. read current @VDD min [61:59]\r
+ UINT32 CSizeLow : 2; // Device size low 2 bits [63:62]\r
+\r
+ UINT32 CSizeHigh : 10; // Device size high 10 bits [73:64]\r
+ UINT32 Reserved4 : 2; // Reserved [75:74]\r
+ UINT32 DsrImp : 1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]\r
+ UINT32 Ccc : 12; // Card command classes [95:84]\r
+\r
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]\r
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac : 8; // Data read access-time [119:112]\r
+ UINT32 Reserved5 : 6; // Reserved [125:120]\r
+ UINT32 CsdStructure : 2; // CSD structure [127:126]\r
} SD_CSD;\r
\r
typedef struct {\r
- UINT32 NotUsed:1; // Not used [0:0]\r
- UINT32 Crc:7; // CRC [7:1]\r
- UINT32 Reserved:2; // Reserved [9:8]\r
- UINT32 FileFormat:2; // File format [11:10]\r
- UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
- UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
- UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
- UINT32 FileFormatGrp:1; // File format group [15:15]\r
- UINT32 Reserved1:5; // Reserved [20:16]\r
- UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
- UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
- UINT32 R2WFactor:3; // Write speed factor [28:26]\r
- UINT32 Reserved2:2; // Manufacturer default ECC [30:29]\r
- UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
-\r
- UINT32 WpGrpSize:7; // Write protect group size [38:32]\r
- UINT32 SectorSize:7; // Erase sector size [45:39]\r
- UINT32 EraseBlkEn:1; // Erase single block enable [46:46]\r
- UINT32 Reserved3:1; // Reserved [47:47]\r
- UINT32 CSizeLow:16; // Device size low 16 bits [63:48]\r
-\r
- UINT32 CSizeHigh:6; // Device size high 6 bits [69:64]\r
- UINT32 Reserved4:6; // Reserved [75:70]\r
- UINT32 DsrImp:1; // DSR implemented [76:76]\r
- UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
- UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
- UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
- UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
- UINT32 Ccc:12; // Card command classes [95:84]\r
-\r
- UINT32 TranSpeed:8; // Max. data transfer rate [103:96]\r
- UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
- UINT32 Taac:8; // Data read access-time [119:112]\r
- UINT32 Reserved5:6; // Reserved [125:120]\r
- UINT32 CsdStructure:2; // CSD structure [127:126]\r
+ UINT32 NotUsed : 1; // Not used [0:0]\r
+ UINT32 Crc : 7; // CRC [7:1]\r
+ UINT32 Reserved : 2; // Reserved [9:8]\r
+ UINT32 FileFormat : 2; // File format [11:10]\r
+ UINT32 TmpWriteProtect : 1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect : 1; // Permanent write protection [13:13]\r
+ UINT32 Copy : 1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp : 1; // File format group [15:15]\r
+ UINT32 Reserved1 : 5; // Reserved [20:16]\r
+ UINT32 WriteBlPartial : 1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen : 4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor : 3; // Write speed factor [28:26]\r
+ UINT32 Reserved2 : 2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable : 1; // Write protect group enable [31:31]\r
+\r
+ UINT32 WpGrpSize : 7; // Write protect group size [38:32]\r
+ UINT32 SectorSize : 7; // Erase sector size [45:39]\r
+ UINT32 EraseBlkEn : 1; // Erase single block enable [46:46]\r
+ UINT32 Reserved3 : 1; // Reserved [47:47]\r
+ UINT32 CSizeLow : 16; // Device size low 16 bits [63:48]\r
+\r
+ UINT32 CSizeHigh : 6; // Device size high 6 bits [69:64]\r
+ UINT32 Reserved4 : 6; // Reserved [75:70]\r
+ UINT32 DsrImp : 1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign : 1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign : 1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial : 1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen : 4; // Max. read data block length [83:80]\r
+ UINT32 Ccc : 12; // Card command classes [95:84]\r
+\r
+ UINT32 TranSpeed : 8; // Max. data transfer rate [103:96]\r
+ UINT32 Nsac : 8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac : 8; // Data read access-time [119:112]\r
+ UINT32 Reserved5 : 6; // Reserved [125:120]\r
+ UINT32 CsdStructure : 2; // CSD structure [127:126]\r
} SD_CSD2;\r
\r
typedef struct {\r
- UINT32 Reserved; // Reserved [31:0]\r
-\r
- UINT32 CmdSupport:4; // Command Support bits [35:32]\r
- UINT32 Reserved1:6; // Reserved [41:36]\r
- UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42]\r
- UINT32 ExSecurity:4; // Extended Security Support [46:43]\r
- UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47]\r
- UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48]\r
- UINT32 SdSecurity:3; // CPRM security support [54:52]\r
- UINT32 DataStatAfterErase:1; // Data status after erases [55]\r
- UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56]\r
- UINT32 ScrStructure:4; // SCR Structure [63:60]\r
+ UINT32 Reserved; // Reserved [31:0]\r
+\r
+ UINT32 CmdSupport : 4; // Command Support bits [35:32]\r
+ UINT32 Reserved1 : 6; // Reserved [41:36]\r
+ UINT32 SdSpec4 : 1; // Spec. Version 4.00 or higher [42:42]\r
+ UINT32 ExSecurity : 4; // Extended Security Support [46:43]\r
+ UINT32 SdSpec3 : 1; // Spec. Version 3.00 or higher [47:47]\r
+ UINT32 SdBusWidths : 4; // DAT Bus widths supported [51:48]\r
+ UINT32 SdSecurity : 3; // CPRM security support [54:52]\r
+ UINT32 DataStatAfterErase : 1; // Data status after erases [55]\r
+ UINT32 SdSpec : 4; // SD Memory Card Spec. Version [59:56]\r
+ UINT32 ScrStructure : 4; // SCR Structure [63:60]\r
} SD_SCR;\r
\r
#pragma pack()\r
//\r
// SDRAM SPD field definitions\r
//\r
-#define SPD_MEMORY_TYPE 2\r
-#define SPD_SDRAM_ROW_ADDR 3\r
-#define SPD_SDRAM_COL_ADDR 4\r
-#define SPD_SDRAM_MODULE_ROWS 5\r
-#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r
-#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r
-#define SPD_SDRAM_ECC_SUPPORT 11\r
-#define SPD_SDRAM_REFRESH 12\r
-#define SPD_SDRAM_WIDTH 13\r
-#define SPD_SDRAM_ERROR_WIDTH 14\r
-#define SPD_SDRAM_BURST_LENGTH 16\r
-#define SPD_SDRAM_NO_OF_BANKS 17\r
-#define SPD_SDRAM_CAS_LATENCY 18\r
-#define SPD_SDRAM_MODULE_ATTR 21\r
+#define SPD_MEMORY_TYPE 2\r
+#define SPD_SDRAM_ROW_ADDR 3\r
+#define SPD_SDRAM_COL_ADDR 4\r
+#define SPD_SDRAM_MODULE_ROWS 5\r
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r
+#define SPD_SDRAM_ECC_SUPPORT 11\r
+#define SPD_SDRAM_REFRESH 12\r
+#define SPD_SDRAM_WIDTH 13\r
+#define SPD_SDRAM_ERROR_WIDTH 14\r
+#define SPD_SDRAM_BURST_LENGTH 16\r
+#define SPD_SDRAM_NO_OF_BANKS 17\r
+#define SPD_SDRAM_CAS_LATENCY 18\r
+#define SPD_SDRAM_MODULE_ATTR 21\r
\r
-#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency\r
-#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency\r
-#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency\r
-#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency\r
-#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency\r
-#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency\r
-#define SPD_SDRAM_MIN_PRECHARGE 27\r
-#define SPD_SDRAM_ACTIVE_MIN 28\r
-#define SPD_SDRAM_RAS_CAS 29\r
-#define SPD_SDRAM_RAS_PULSE 30\r
-#define SPD_SDRAM_DENSITY 31\r
+#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency\r
+#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency\r
+#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency\r
+#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency\r
+#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency\r
+#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency\r
+#define SPD_SDRAM_MIN_PRECHARGE 27\r
+#define SPD_SDRAM_ACTIVE_MIN 28\r
+#define SPD_SDRAM_RAS_CAS 29\r
+#define SPD_SDRAM_RAS_PULSE 30\r
+#define SPD_SDRAM_DENSITY 31\r
\r
//\r
// Memory Type Definitions\r
//\r
-#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory\r
-#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory\r
-#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r
-#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory\r
-#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory\r
-#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory\r
-#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory\r
+#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory\r
+#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory\r
+#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r
+#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory\r
+#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory\r
+#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory\r
+#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory\r
\r
//\r
// ECC Type Definitions\r
//\r
-#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking\r
-#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking\r
-#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only\r
+#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking\r
+#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking\r
+#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only\r
//\r
// Module Attributes (Bit positions)\r
//\r
\r
typedef union {\r
struct {\r
- UINT8 BytesUsed : 4; ///< Bits 3:0\r
- UINT8 BytesTotal : 3; ///< Bits 6:4\r
- UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_DEVICE_DESCRIPTION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Minor : 4; ///< Bits 3:0\r
- UINT8 Major : 4; ///< Bits 7:4\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_REVISION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Type : 8; ///< Bits 7:0\r
+ UINT8 Type : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_DRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ModuleType : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Density : 4; ///< Bits 3:0\r
- UINT8 BankAddress : 3; ///< Bits 6:4\r
- UINT8 Reserved : 1; ///< Bits 7:7\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 3; ///< Bits 6:4\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_DENSITY_BANKS_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ColumnAddress : 3; ///< Bits 2:0\r
- UINT8 RowAddress : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_ADDRESSING_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
- UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
- UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
- UINT8 Reserved : 5; ///< Bits 7:3\r
+ UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r
+ UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
- UINT8 RankCount : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_ORGANIZATION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
- UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Divisor : 4; ///< Bits 3:0\r
- UINT8 Dividend : 4; ///< Bits 7:4\r
+ UINT8 Divisor : 4; ///< Bits 3:0\r
+ UINT8 Dividend : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_FINE_TIMEBASE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Dividend : 8; ///< Bits 7:0\r
+ UINT8 Dividend : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Divisor : 8; ///< Bits 7:0\r
+ UINT8 Divisor : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;\r
\r
typedef struct {\r
- SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
- SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
+ SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r
+ SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r
} SPD3_MEDIUM_TIMEBASE;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmin : 8; ///< Bits 7:0\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TCK_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 Cl4 : 1; ///< Bits 0:0\r
- UINT16 Cl5 : 1; ///< Bits 1:1\r
- UINT16 Cl6 : 1; ///< Bits 2:2\r
- UINT16 Cl7 : 1; ///< Bits 3:3\r
- UINT16 Cl8 : 1; ///< Bits 4:4\r
- UINT16 Cl9 : 1; ///< Bits 5:5\r
- UINT16 Cl10 : 1; ///< Bits 6:6\r
- UINT16 Cl11 : 1; ///< Bits 7:7\r
- UINT16 Cl12 : 1; ///< Bits 8:8\r
- UINT16 Cl13 : 1; ///< Bits 9:9\r
- UINT16 Cl14 : 1; ///< Bits 10:10\r
- UINT16 Cl15 : 1; ///< Bits 11:11\r
- UINT16 Cl16 : 1; ///< Bits 12:12\r
- UINT16 Cl17 : 1; ///< Bits 13:13\r
- UINT16 Cl18 : 1; ///< Bits 14:14\r
- UINT16 Reserved : 1; ///< Bits 15:15\r
- } Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Cl4 : 1; ///< Bits 0:0\r
+ UINT16 Cl5 : 1; ///< Bits 1:1\r
+ UINT16 Cl6 : 1; ///< Bits 2:2\r
+ UINT16 Cl7 : 1; ///< Bits 3:3\r
+ UINT16 Cl8 : 1; ///< Bits 4:4\r
+ UINT16 Cl9 : 1; ///< Bits 5:5\r
+ UINT16 Cl10 : 1; ///< Bits 6:6\r
+ UINT16 Cl11 : 1; ///< Bits 7:7\r
+ UINT16 Cl12 : 1; ///< Bits 8:8\r
+ UINT16 Cl13 : 1; ///< Bits 9:9\r
+ UINT16 Cl14 : 1; ///< Bits 10:10\r
+ UINT16 Cl15 : 1; ///< Bits 11:11\r
+ UINT16 Cl16 : 1; ///< Bits 12:12\r
+ UINT16 Cl17 : 1; ///< Bits 13:13\r
+ UINT16 Cl18 : 1; ///< Bits 14:14\r
+ UINT16 Reserved : 1; ///< Bits 15:15\r
+ } Bits;\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tAAmin : 8; ///< Bits 7:0\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TAA_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWRmin : 8; ///< Bits 7:0\r
+ UINT8 tWRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TWR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRCD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRRDmin : 8; ///< Bits 7:0\r
+ UINT8 tRRDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRRD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRPmin : 8; ///< Bits 7:0\r
+ UINT8 tRPmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRP_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASminUpper : 4; ///< Bits 3:0\r
- UINT8 tRCminUpper : 4; ///< Bits 7:4\r
+ UINT8 tRASminUpper : 4; ///< Bits 3:0\r
+ UINT8 tRCminUpper : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRAS_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASmin : 8; ///< Bits 7:0\r
+ UINT8 tRASmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRAS_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCmin : 8; ///< Bits 7:0\r
+ UINT8 tRCmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 tRFCmin : 16; ///< Bits 15:0\r
+ UINT16 tRFCmin : 16; ///< Bits 15:0\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_TRFC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWTRmin : 8; ///< Bits 7:0\r
+ UINT8 tWTRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TWTR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRTPmin : 8; ///< Bits 7:0\r
+ UINT8 tRTPmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TRTP_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TFAW_MIN_MTB_UPPER_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWmin : 8; ///< Bits 7:0\r
+ UINT8 tFAWmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_TFAW_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Rzq6 : 1; ///< Bits 0:0\r
- UINT8 Rzq7 : 1; ///< Bits 1:1\r
- UINT8 Reserved : 5; ///< Bits 6:2\r
- UINT8 DllOff : 1; ///< Bits 7:7\r
+ UINT8 Rzq6 : 1; ///< Bits 0:0\r
+ UINT8 Rzq7 : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 5; ///< Bits 6:2\r
+ UINT8 DllOff : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
- UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
- UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
- UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
- UINT8 Reserved : 3; ///< Bits 6:4\r
- UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
+ UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r
+ UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r
+ UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r
+ UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r
+ UINT8 Reserved : 3; ///< Bits 6:4\r
+ UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_THERMAL_REFRESH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
- UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MODULE_THERMAL_SENSOR_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SignalLoading : 2; ///< Bits 1:0\r
- UINT8 Reserved : 2; ///< Bits 3:2\r
- UINT8 DieCount : 3; ///< Bits 6:4\r
- UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 Reserved : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_SDRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKminFine : 8; ///< Bits 7:0\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TCK_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tAAminFine : 8; ///< Bits 7:0\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TAA_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRCD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRPminFine : 8; ///< Bits 7:0\r
+ INT8 tRPminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRP_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCminFine : 8; ///< Bits 7:0\r
+ INT8 tRCminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD3_TRC_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
- UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
- UINT8 VendorSpecific : 2; ///< Bits 7:6\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 VendorSpecific : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 MappingRank1 : 1; ///< Bits 0:0\r
- UINT8 Reserved : 7; ///< Bits 7:1\r
+ UINT8 MappingRank1 : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_UNBUF_ADDRESS_MAPPING;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
- UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
\r
typedef union {\r
struct {\r
- UINT16 ContinuationCount : 7; ///< Bits 6:0\r
- UINT16 ContinuationParity : 1; ///< Bits 7:7\r
- UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD3_MANUFACTURER_ID_CODE;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_REVISION_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 Bit0 : 1; ///< Bits 0:0\r
- UINT8 Bit1 : 1; ///< Bits 1:1\r
- UINT8 Bit2 : 1; ///< Bits 2:2\r
- UINT8 Reserved : 5; ///< Bits 7:3\r
+ UINT8 Bit0 : 1; ///< Bits 0:0\r
+ UINT8 Bit1 : 1; ///< Bits 1:1\r
+ UINT8 Bit2 : 1; ///< Bits 2:2\r
+ UINT8 Reserved : 5; ///< Bits 7:3\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_TYPE;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 4; ///< Bits 0:3\r
- UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
- UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
+ UINT8 Reserved : 4; ///< Bits 0:3\r
+ UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r
+ UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
- UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
- UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
- UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r
+ UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved0 : 4; ///< Bits 0:3\r
- UINT8 Reserved1 : 4; ///< Bits 7:4\r
+ UINT8 Reserved0 : 4; ///< Bits 0:3\r
+ UINT8 Reserved1 : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_RDIMM_REGISTER_CONTROL_RESERVED;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
- UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
- UINT8 Reserved0 : 1; ///< Bits 2:2\r
- UINT8 Reserved1 : 1; ///< Bits 3:3\r
- UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
- UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
+ UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r
+ UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r
+ UINT8 Reserved0 : 1; ///< Bits 2:2\r
+ UINT8 Reserved1 : 1; ///< Bits 3:3\r
+ UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r
+ UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
- UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
- UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
- UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
+ UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r
+ UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r
+ UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r
+ UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
- UINT8 QxCS_n : 2; ///< Bits 3:2\r
- UINT8 QxOdt : 2; ///< Bits 5:4\r
- UINT8 QxCke : 2; ///< Bits 7:6\r
+ UINT8 YExtendedDelay : 2; ///< Bits 1:0\r
+ UINT8 QxCS_n : 2; ///< Bits 3:2\r
+ UINT8 QxOdt : 2; ///< Bits 5:4\r
+ UINT8 QxCke : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_EXTENDED_DELAY;\r
\r
typedef union {\r
struct {\r
- UINT8 DelayY : 3; ///< Bits 2:0\r
- UINT8 Reserved : 1; ///< Bits 3:3\r
- UINT8 QxCS_n : 4; ///< Bits 7:4\r
+ UINT8 DelayY : 3; ///< Bits 2:0\r
+ UINT8 Reserved : 1; ///< Bits 3:3\r
+ UINT8 QxCS_n : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;\r
\r
typedef union {\r
struct {\r
- UINT8 QxCS_n : 4; ///< Bits 3:0\r
- UINT8 QxOdt : 4; ///< Bits 7:4\r
+ UINT8 QxCS_n : 4; ///< Bits 3:0\r
+ UINT8 QxOdt : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;\r
\r
typedef union {\r
struct {\r
- UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
- UINT8 RC8Reserved : 1; ///< Bits 3:3\r
- UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
- UINT8 RC9Reserved : 1; ///< Bits 7:7\r
+ UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r
+ UINT8 RC8Reserved : 1; ///< Bits 3:3\r
+ UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r
+ UINT8 RC9Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
- UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
- UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
- UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
- UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
- UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
- UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
- UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
+ UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r
+ UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r
+ UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r
+ UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r
+ UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r
+ UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r
+ UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r
+ UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;\r
\r
typedef union {\r
struct {\r
- UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
- UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
- UINT8 Reserved : 1; ///< Bits 5:5\r
- UINT8 Rtt_WR : 2; ///< Bits 7:6\r
+ UINT8 Driver_Impedance : 2; ///< Bits 1:0\r
+ UINT8 Rtt_Nom : 3; ///< Bits 4:2\r
+ UINT8 Reserved : 1; ///< Bits 5:5\r
+ UINT8 Rtt_WR : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MR_1_2;\r
\r
typedef union {\r
struct {\r
- UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
- UINT8 Reserved : 1; ///< Bits 7:7\r
+ UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD3_LRDIMM_MODULE_DELAY_TIME;\r
\r
typedef struct {\r
- UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
- UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
} SPD3_MANUFACTURING_DATE;\r
\r
typedef union {\r
- UINT32 Data;\r
- UINT16 SerialNumber16[2];\r
- UINT8 SerialNumber8[4];\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
} SPD3_MANUFACTURER_SERIAL_NUMBER;\r
\r
typedef struct {\r
- UINT8 Location; ///< Module Manufacturing Location\r
+ UINT8 Location; ///< Module Manufacturing Location\r
} SPD3_MANUFACTURING_LOCATION;\r
\r
typedef struct {\r
- SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
- SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
- SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
- SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+ SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
} SPD3_UNIQUE_MODULE_ID;\r
\r
typedef union {\r
- UINT16 Crc[1];\r
- UINT8 Data8[2];\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
} SPD3_CYCLIC_REDUNDANCY_CODE;\r
\r
typedef struct {\r
- SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
- SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
- SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
- SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
- SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
- SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
- SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
- SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
- SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
- SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
- SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
- SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
- UINT8 Reserved0; ///< 13 Reserved\r
- SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
- SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
- SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
- SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
- SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
- SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
- SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
- SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
- SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
- SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
- SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
- SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
- SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
- SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
- SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
- SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
- SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
- SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
- SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
- SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
- SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
- UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
- SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
- UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
+ SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r
+ SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r
+ SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r
+ SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r
+ SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r
+ SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r
+ UINT8 Reserved0; ///< 13 Reserved\r
+ SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r
+ SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r
+ SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r
+ SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r
+ SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
+ SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
+ SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r
+ SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r
+ SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r
+ SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r
+ SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r
+ SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r
+ SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r
+ SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r
+ SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r
+ SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
+ UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r
+ SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r
+ UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r
} SPD3_BASE_SECTION;\r
\r
typedef struct {\r
- SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
- UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r
} SPD3_MODULE_UNBUFFERED;\r
\r
typedef struct {\r
- SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
- SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
- SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
- SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
- SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
- SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
- SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
- UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
+ SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r
+ SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r
+ SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r
+ SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r
+ SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r
+ SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r
+ SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r
+ UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r
} SPD3_MODULE_REGISTERED;\r
\r
typedef struct {\r
- SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
+ SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r
} SPD3_MODULE_CLOCKED;\r
\r
typedef struct {\r
- SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
- SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
- SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
- SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
- UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
- SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
- SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
- SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
- SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
- SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
- SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r
+ SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r
+ SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r
+ SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r
+ UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r
+ SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r
+ SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r
+ SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r
+ SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r
+ SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r
SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
- SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
- SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
- UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
- UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r
+ SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r
+ SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r
+ UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r
+ UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r
} SPD3_MODULE_LOADREDUCED;\r
\r
typedef union {\r
- SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
- SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
- SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
- SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
+ SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r
+ SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
} SPD3_MODULE_SPECIFIC;\r
\r
typedef struct {\r
- UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
+ UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r
} SPD3_MODULE_PART_NUMBER;\r
\r
typedef struct {\r
- UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
+ UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r
} SPD3_MODULE_REVISION_CODE;\r
\r
typedef struct {\r
- UINT8 ManufacturerSpecificData[175 - 150 + 1];///< 150-175 Manufacturer's Specific Data\r
+ UINT8 ManufacturerSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data\r
} SPD3_MANUFACTURER_SPECIFIC;\r
\r
///\r
/// DDR3 Serial Presence Detect structure\r
///\r
typedef struct {\r
- SPD3_BASE_SECTION General; ///< 0-59 General Section\r
- SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
- SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
- SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
- SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
- SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
- SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
- SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
- UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
+ SPD3_BASE_SECTION General; ///< 0-59 General Section\r
+ SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r
+ SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r
+ SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+ SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r
+ SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r
+ SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r
+ SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r
+ UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r
} SPD_DDR3;\r
\r
#pragma pack (pop)\r
\r
typedef union {\r
struct {\r
- UINT8 BytesUsed : 4; ///< Bits 3:0\r
- UINT8 BytesTotal : 3; ///< Bits 6:4\r
- UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_DEVICE_DESCRIPTION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Minor : 4; ///< Bits 3:0\r
- UINT8 Major : 4; ///< Bits 7:4\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_REVISION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Type : 8; ///< Bits 7:0\r
+ UINT8 Type : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_DRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ModuleType : 4; ///< Bits 3:0\r
- UINT8 HybridMedia : 3; ///< Bits 6:4\r
- UINT8 Hybrid : 1; ///< Bits 7:7\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 HybridMedia : 3; ///< Bits 6:4\r
+ UINT8 Hybrid : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Density : 4; ///< Bits 3:0\r
- UINT8 BankAddress : 2; ///< Bits 5:4\r
- UINT8 BankGroup : 2; ///< Bits 7:6\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 2; ///< Bits 5:4\r
+ UINT8 BankGroup : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_SDRAM_DENSITY_BANKS_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ColumnAddress : 3; ///< Bits 2:0\r
- UINT8 RowAddress : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_SDRAM_ADDRESSING_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SignalLoading : 2; ///< Bits 1:0\r
- UINT8 Reserved : 2; ///< Bits 3:2\r
- UINT8 DieCount : 3; ///< Bits 6:4\r
- UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 Reserved : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
- UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 8; ///< Bits 7:0\r
+ UINT8 Reserved : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 5; ///< Bits 4:0\r
- UINT8 SoftPPR : 1; ///< Bits 5:5\r
- UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
+ UINT8 Reserved : 5; ///< Bits 4:0\r
+ UINT8 SoftPPR : 1; ///< Bits 5:5\r
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SignalLoading : 2; ///< Bits 1:0\r
- UINT8 DRAMDensityRatio : 2; ///< Bits 3:2\r
- UINT8 DieCount : 3; ///< Bits 6:4\r
- UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 DRAMDensityRatio : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
- UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
- UINT8 Reserved : 6; ///< Bits 7:2\r
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 6; ///< Bits 7:2\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
- UINT8 RankCount : 3; ///< Bits 5:3\r
- UINT8 RankMix : 1; ///< Bits 6:6\r
- UINT8 Reserved : 1; ///< Bits 7:7\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 RankMix : 1; ///< Bits 6:6\r
+ UINT8 Reserved : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_MODULE_ORGANIZATION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
- UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 7; ///< Bits 6:0\r
- UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ UINT8 Reserved : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_MODULE_THERMAL_SENSOR_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_EXTENDED_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Fine : 2; ///< Bits 1:0\r
- UINT8 Medium : 2; ///< Bits 3:2\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 Fine : 2; ///< Bits 1:0\r
+ UINT8 Medium : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TIMEBASE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmin : 8; ///< Bits 7:0\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TCK_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmax : 8; ///< Bits 7:0\r
+ UINT8 tCKmax : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TCK_MAX_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT32 Cl7 : 1; ///< Bits 0:0\r
- UINT32 Cl8 : 1; ///< Bits 1:1\r
- UINT32 Cl9 : 1; ///< Bits 2:2\r
- UINT32 Cl10 : 1; ///< Bits 3:3\r
- UINT32 Cl11 : 1; ///< Bits 4:4\r
- UINT32 Cl12 : 1; ///< Bits 5:5\r
- UINT32 Cl13 : 1; ///< Bits 6:6\r
- UINT32 Cl14 : 1; ///< Bits 7:7\r
- UINT32 Cl15 : 1; ///< Bits 8:8\r
- UINT32 Cl16 : 1; ///< Bits 9:9\r
- UINT32 Cl17 : 1; ///< Bits 10:10\r
- UINT32 Cl18 : 1; ///< Bits 11:11\r
- UINT32 Cl19 : 1; ///< Bits 12:12\r
- UINT32 Cl20 : 1; ///< Bits 13:13\r
- UINT32 Cl21 : 1; ///< Bits 14:14\r
- UINT32 Cl22 : 1; ///< Bits 15:15\r
- UINT32 Cl23 : 1; ///< Bits 16:16\r
- UINT32 Cl24 : 1; ///< Bits 17:17\r
- UINT32 Cl25 : 1; ///< Bits 18:18\r
- UINT32 Cl26 : 1; ///< Bits 19:19\r
- UINT32 Cl27 : 1; ///< Bits 20:20\r
- UINT32 Cl28 : 1; ///< Bits 21:21\r
- UINT32 Cl29 : 1; ///< Bits 22:22\r
- UINT32 Cl30 : 1; ///< Bits 23:23\r
- UINT32 Cl31 : 1; ///< Bits 24:24\r
- UINT32 Cl32 : 1; ///< Bits 25:25\r
- UINT32 Cl33 : 1; ///< Bits 26:26\r
- UINT32 Cl34 : 1; ///< Bits 27:27\r
- UINT32 Cl35 : 1; ///< Bits 28:28\r
- UINT32 Cl36 : 1; ///< Bits 29:29\r
- UINT32 Reserved : 1; ///< Bits 30:30\r
- UINT32 ClRange : 1; ///< Bits 31:31\r
- } Bits;\r
- struct {\r
- UINT32 Cl23 : 1; ///< Bits 0:0\r
- UINT32 Cl24 : 1; ///< Bits 1:1\r
- UINT32 Cl25 : 1; ///< Bits 2:2\r
- UINT32 Cl26 : 1; ///< Bits 3:3\r
- UINT32 Cl27 : 1; ///< Bits 4:4\r
- UINT32 Cl28 : 1; ///< Bits 5:5\r
- UINT32 Cl29 : 1; ///< Bits 6:6\r
- UINT32 Cl30 : 1; ///< Bits 7:7\r
- UINT32 Cl31 : 1; ///< Bits 8:8\r
- UINT32 Cl32 : 1; ///< Bits 9:9\r
- UINT32 Cl33 : 1; ///< Bits 10:10\r
- UINT32 Cl34 : 1; ///< Bits 11:11\r
- UINT32 Cl35 : 1; ///< Bits 12:12\r
- UINT32 Cl36 : 1; ///< Bits 13:13\r
- UINT32 Cl37 : 1; ///< Bits 14:14\r
- UINT32 Cl38 : 1; ///< Bits 15:15\r
- UINT32 Cl39 : 1; ///< Bits 16:16\r
- UINT32 Cl40 : 1; ///< Bits 17:17\r
- UINT32 Cl41 : 1; ///< Bits 18:18\r
- UINT32 Cl42 : 1; ///< Bits 19:19\r
- UINT32 Cl43 : 1; ///< Bits 20:20\r
- UINT32 Cl44 : 1; ///< Bits 21:21\r
- UINT32 Cl45 : 1; ///< Bits 22:22\r
- UINT32 Cl46 : 1; ///< Bits 23:23\r
- UINT32 Cl47 : 1; ///< Bits 24:24\r
- UINT32 Cl48 : 1; ///< Bits 25:25\r
- UINT32 Cl49 : 1; ///< Bits 26:26\r
- UINT32 Cl50 : 1; ///< Bits 27:27\r
- UINT32 Cl51 : 1; ///< Bits 28:28\r
- UINT32 Cl52 : 1; ///< Bits 29:29\r
- UINT32 Reserved : 1; ///< Bits 30:30\r
- UINT32 ClRange : 1; ///< Bits 31:31\r
+ UINT32 Cl7 : 1; ///< Bits 0:0\r
+ UINT32 Cl8 : 1; ///< Bits 1:1\r
+ UINT32 Cl9 : 1; ///< Bits 2:2\r
+ UINT32 Cl10 : 1; ///< Bits 3:3\r
+ UINT32 Cl11 : 1; ///< Bits 4:4\r
+ UINT32 Cl12 : 1; ///< Bits 5:5\r
+ UINT32 Cl13 : 1; ///< Bits 6:6\r
+ UINT32 Cl14 : 1; ///< Bits 7:7\r
+ UINT32 Cl15 : 1; ///< Bits 8:8\r
+ UINT32 Cl16 : 1; ///< Bits 9:9\r
+ UINT32 Cl17 : 1; ///< Bits 10:10\r
+ UINT32 Cl18 : 1; ///< Bits 11:11\r
+ UINT32 Cl19 : 1; ///< Bits 12:12\r
+ UINT32 Cl20 : 1; ///< Bits 13:13\r
+ UINT32 Cl21 : 1; ///< Bits 14:14\r
+ UINT32 Cl22 : 1; ///< Bits 15:15\r
+ UINT32 Cl23 : 1; ///< Bits 16:16\r
+ UINT32 Cl24 : 1; ///< Bits 17:17\r
+ UINT32 Cl25 : 1; ///< Bits 18:18\r
+ UINT32 Cl26 : 1; ///< Bits 19:19\r
+ UINT32 Cl27 : 1; ///< Bits 20:20\r
+ UINT32 Cl28 : 1; ///< Bits 21:21\r
+ UINT32 Cl29 : 1; ///< Bits 22:22\r
+ UINT32 Cl30 : 1; ///< Bits 23:23\r
+ UINT32 Cl31 : 1; ///< Bits 24:24\r
+ UINT32 Cl32 : 1; ///< Bits 25:25\r
+ UINT32 Cl33 : 1; ///< Bits 26:26\r
+ UINT32 Cl34 : 1; ///< Bits 27:27\r
+ UINT32 Cl35 : 1; ///< Bits 28:28\r
+ UINT32 Cl36 : 1; ///< Bits 29:29\r
+ UINT32 Reserved : 1; ///< Bits 30:30\r
+ UINT32 ClRange : 1; ///< Bits 31:31\r
+ } Bits;\r
+ struct {\r
+ UINT32 Cl23 : 1; ///< Bits 0:0\r
+ UINT32 Cl24 : 1; ///< Bits 1:1\r
+ UINT32 Cl25 : 1; ///< Bits 2:2\r
+ UINT32 Cl26 : 1; ///< Bits 3:3\r
+ UINT32 Cl27 : 1; ///< Bits 4:4\r
+ UINT32 Cl28 : 1; ///< Bits 5:5\r
+ UINT32 Cl29 : 1; ///< Bits 6:6\r
+ UINT32 Cl30 : 1; ///< Bits 7:7\r
+ UINT32 Cl31 : 1; ///< Bits 8:8\r
+ UINT32 Cl32 : 1; ///< Bits 9:9\r
+ UINT32 Cl33 : 1; ///< Bits 10:10\r
+ UINT32 Cl34 : 1; ///< Bits 11:11\r
+ UINT32 Cl35 : 1; ///< Bits 12:12\r
+ UINT32 Cl36 : 1; ///< Bits 13:13\r
+ UINT32 Cl37 : 1; ///< Bits 14:14\r
+ UINT32 Cl38 : 1; ///< Bits 15:15\r
+ UINT32 Cl39 : 1; ///< Bits 16:16\r
+ UINT32 Cl40 : 1; ///< Bits 17:17\r
+ UINT32 Cl41 : 1; ///< Bits 18:18\r
+ UINT32 Cl42 : 1; ///< Bits 19:19\r
+ UINT32 Cl43 : 1; ///< Bits 20:20\r
+ UINT32 Cl44 : 1; ///< Bits 21:21\r
+ UINT32 Cl45 : 1; ///< Bits 22:22\r
+ UINT32 Cl46 : 1; ///< Bits 23:23\r
+ UINT32 Cl47 : 1; ///< Bits 24:24\r
+ UINT32 Cl48 : 1; ///< Bits 25:25\r
+ UINT32 Cl49 : 1; ///< Bits 26:26\r
+ UINT32 Cl50 : 1; ///< Bits 27:27\r
+ UINT32 Cl51 : 1; ///< Bits 28:28\r
+ UINT32 Cl52 : 1; ///< Bits 29:29\r
+ UINT32 Reserved : 1; ///< Bits 30:30\r
+ UINT32 ClRange : 1; ///< Bits 31:31\r
} HighRangeBits;\r
- UINT32 Data;\r
- UINT16 Data16[2];\r
- UINT8 Data8[4];\r
+ UINT32 Data;\r
+ UINT16 Data16[2];\r
+ UINT8 Data8[4];\r
} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tAAmin : 8; ///< Bits 7:0\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TAA_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRCD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRPmin : 8; ///< Bits 7:0\r
+ UINT8 tRPmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRP_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASminUpper : 4; ///< Bits 3:0\r
- UINT8 tRCminUpper : 4; ///< Bits 7:4\r
+ UINT8 tRASminUpper : 4; ///< Bits 3:0\r
+ UINT8 tRCminUpper : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRAS_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRASmin : 8; ///< Bits 7:0\r
+ UINT8 tRASmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRAS_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCmin : 8; ///< Bits 7:0\r
+ UINT8 tRCmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 tRFCmin : 16; ///< Bits 15:0\r
+ UINT16 tRFCmin : 16; ///< Bits 15:0\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD4_TRFC_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TFAW_MIN_MTB_UPPER_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tFAWmin : 8; ///< Bits 7:0\r
+ UINT8 tFAWmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TFAW_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRRDmin : 8; ///< Bits 7:0\r
+ UINT8 tRRDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TRRD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tCCDmin : 8; ///< Bits 7:0\r
+ UINT8 tCCDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TCCD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 tWRminMostSignificantNibble : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TWR_UPPER_NIBBLE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWRmin : 8; ///< Bits 7:0\r
+ UINT8 tWRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TWR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0\r
- UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4\r
+ UINT8 tWTR_SminMostSignificantNibble : 4; ///< Bits 3:0\r
+ UINT8 tWTR_LminMostSignificantNibble : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TWTR_UPPER_NIBBLE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tWTRmin : 8; ///< Bits 7:0\r
+ UINT8 tWTRmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_TWTR_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
- UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
- UINT8 PackageRankMap : 2; ///< Bits 7:6\r
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
+ UINT8 PackageRankMap : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCCDminFine : 8; ///< Bits 7:0\r
+ INT8 tCCDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TCCD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRRDminFine : 8; ///< Bits 7:0\r
+ INT8 tRRDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TRRD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCminFine : 8; ///< Bits 7:0\r
+ INT8 tRCminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TRC_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRPminFine : 8; ///< Bits 7:0\r
+ INT8 tRPminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TRP_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TRCD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tAAminFine : 8; ///< Bits 7:0\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TAA_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKmaxFine : 8; ///< Bits 7:0\r
+ INT8 tCKmaxFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TCK_MAX_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKminFine : 8; ///< Bits 7:0\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD4_TCK_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_UNBUF_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_UNBUF_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 MappingRank1 : 1; ///< Bits 0:0\r
- UINT8 Reserved : 7; ///< Bits 7:1\r
+ UINT8 MappingRank1 : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_UNBUF_ADDRESS_MAPPING;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
- UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
\r
typedef union {\r
struct {\r
- UINT16 ContinuationCount : 7; ///< Bits 6:0\r
- UINT16 ContinuationParity : 1; ///< Bits 7:7\r
- UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD4_MANUFACTURER_ID_CODE;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_REGISTER_REVISION_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
- UINT8 Reserved : 7; ///< Bits 7:1\r
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
\r
typedef union {\r
struct {\r
- UINT8 Cke : 2; ///< Bits 1:0\r
- UINT8 Odt : 2; ///< Bits 3:2\r
- UINT8 CommandAddress : 2; ///< Bits 5:4\r
- UINT8 ChipSelect : 2; ///< Bits 7:6\r
+ UINT8 Cke : 2; ///< Bits 1:0\r
+ UINT8 Odt : 2; ///< Bits 3:2\r
+ UINT8 CommandAddress : 2; ///< Bits 5:4\r
+ UINT8 ChipSelect : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Y0Y2 : 2; ///< Bits 1:0\r
- UINT8 Y1Y3 : 2; ///< Bits 3:2\r
- UINT8 Reserved0 : 2; ///< Bits 5:4\r
- UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
- UINT8 Reserved1 : 1; ///< Bits 7:7\r
+ UINT8 Y0Y2 : 2; ///< Bits 1:0\r
+ UINT8 Y1Y3 : 2; ///< Bits 3:2\r
+ UINT8 Reserved0 : 2; ///< Bits 5:4\r
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
+ UINT8 Reserved1 : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterCount : 2; ///< Bits 1:0\r
- UINT8 DramRowCount : 2; ///< Bits 3:2\r
- UINT8 RegisterType : 4; ///< Bits 7:4\r
+ UINT8 RegisterCount : 2; ///< Bits 1:0\r
+ UINT8 DramRowCount : 2; ///< Bits 3:2\r
+ UINT8 RegisterType : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_MODULE_ATTRIBUTES;\r
\r
typedef union {\r
struct {\r
- UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
- UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
+ UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r
+ UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r
\r
typedef union {\r
struct {\r
- UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
+ UINT8 RegisterRevisionNumber; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_REGISTER_REVISION_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
- UINT8 Reserved : 7; ///< Bits 7:1\r
+ UINT8 Rank1Mapping : 1; ///< Bits 0:0\r
+ UINT8 Reserved : 7; ///< Bits 7:1\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM;\r
\r
typedef union {\r
struct {\r
- UINT8 Cke : 2; ///< Bits 1:0\r
- UINT8 Odt : 2; ///< Bits 3:2\r
- UINT8 CommandAddress : 2; ///< Bits 5:4\r
- UINT8 ChipSelect : 2; ///< Bits 7:6\r
+ UINT8 Cke : 2; ///< Bits 1:0\r
+ UINT8 Odt : 2; ///< Bits 3:2\r
+ UINT8 CommandAddress : 2; ///< Bits 5:4\r
+ UINT8 ChipSelect : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Y0Y2 : 2; ///< Bits 1:0\r
- UINT8 Y1Y3 : 2; ///< Bits 3:2\r
- UINT8 Reserved0 : 2; ///< Bits 5:4\r
- UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
- UINT8 Reserved1 : 1; ///< Bits 7:7\r
+ UINT8 Y0Y2 : 2; ///< Bits 1:0\r
+ UINT8 Y1Y3 : 2; ///< Bits 3:2\r
+ UINT8 Reserved0 : 2; ///< Bits 5:4\r
+ UINT8 RcdOutputSlewRateControl : 1; ///< Bits 6:6\r
+ UINT8 Reserved1 : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK;\r
\r
typedef struct {\r
- UINT8 DataBufferRevisionNumber;\r
+ UINT8 DataBufferRevisionNumber;\r
} SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER;\r
\r
typedef union {\r
struct {\r
- UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 DramVrefDQForPackageRank0 : 6; ///< Bits 5:0\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK;\r
\r
typedef struct {\r
- UINT8 DataBufferVrefDQforDramInterface;\r
+ UINT8 DataBufferVrefDQforDramInterface;\r
} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE;\r
\r
typedef union {\r
struct {\r
- UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0\r
- UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4\r
+ UINT8 DramInterfaceMdqDriveStrength : 4; ///< Bits 3:0\r
+ UINT8 DramInterfaceMdqReadTerminationStrength : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE;\r
\r
typedef union {\r
struct {\r
- UINT8 DataRateLe1866 : 2; ///< Bits 1:0\r
- UINT8 DataRateLe2400 : 2; ///< Bits 3:2\r
- UINT8 DataRateLe3200 : 2; ///< Bits 5:4\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 DataRateLe1866 : 2; ///< Bits 1:0\r
+ UINT8 DataRateLe2400 : 2; ///< Bits 3:2\r
+ UINT8 DataRateLe3200 : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DRAM_DRIVE_STRENGTH;\r
\r
typedef union {\r
struct {\r
- UINT8 Rtt_Nom : 3; ///< Bits 2:0\r
- UINT8 Rtt_WR : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 Rtt_Nom : 3; ///< Bits 2:0\r
+ UINT8 Rtt_WR : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE;\r
\r
typedef union {\r
struct {\r
- UINT8 PackageRanks0_1 : 3; ///< Bits 2:0\r
- UINT8 PackageRanks2_3 : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 PackageRanks0_1 : 3; ///< Bits 2:0\r
+ UINT8 PackageRanks2_3 : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE;\r
\r
typedef union {\r
struct {\r
- UINT8 Rank0 : 1; ///< Bits 0:0\r
- UINT8 Rank1 : 1; ///< Bits 1:1\r
- UINT8 Rank2 : 1; ///< Bits 2:2\r
- UINT8 Rank3 : 1; ///< Bits 3:3\r
- UINT8 DataBuffer : 1; ///< Bits 4:4\r
- UINT8 Reserved : 3; ///< Bits 7:5\r
+ UINT8 Rank0 : 1; ///< Bits 0:0\r
+ UINT8 Rank1 : 1; ///< Bits 1:1\r
+ UINT8 Rank2 : 1; ///< Bits 2:2\r
+ UINT8 Rank3 : 1; ///< Bits 3:3\r
+ UINT8 DataBuffer : 1; ///< Bits 4:4\r
+ UINT8 Reserved : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE;\r
\r
typedef union {\r
struct {\r
- UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0\r
- UINT8 DataBufferDfe : 1; ///< Bits 1:1\r
- UINT8 Reserved : 6; ///< Bits 7:2\r
+ UINT8 DataBufferGainAdjustment : 1; ///< Bits 0:0\r
+ UINT8 DataBufferDfe : 1; ///< Bits 1:1\r
+ UINT8 Reserved : 6; ///< Bits 7:2\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION;\r
\r
typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER;\r
\r
typedef union {\r
struct {\r
- UINT16 ContinuationCount : 7; ///< Bits 6:0\r
- UINT16 ContinuationParity : 1; ///< Bits 7:7\r
- UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE;\r
\r
typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_NVDIMM_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 4; ///< Bits 3:0\r
- UINT8 Extension : 4; ///< Bits 7:4\r
+ UINT8 Reserved : 4; ///< Bits 3:0\r
+ UINT8 Extension : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD4_NVDIMM_MODULE_CHARACTERISTICS;\r
\r
typedef struct {\r
- UINT8 Reserved;\r
- UINT8 MediaType;\r
+ UINT8 Reserved;\r
+ UINT8 MediaType;\r
} SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES;\r
\r
typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME;\r
\r
typedef union {\r
struct {\r
- UINT16 FunctionInterface : 5; ///< Bits 4:0\r
- UINT16 FunctionClass : 5; ///< Bits 9:5\r
- UINT16 BlockOffset : 4; ///< Bits 13:10\r
- UINT16 Reserved : 1; ///< Bits 14:14\r
- UINT16 Implemented : 1; ///< Bits 15:15\r
+ UINT16 FunctionInterface : 5; ///< Bits 4:0\r
+ UINT16 FunctionClass : 5; ///< Bits 9:5\r
+ UINT16 BlockOffset : 4; ///< Bits 13:10\r
+ UINT16 Reserved : 1; ///< Bits 14:14\r
+ UINT16 Implemented : 1; ///< Bits 15:15\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR;\r
\r
typedef struct {\r
- UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
- UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
} SPD4_MANUFACTURING_DATE;\r
\r
typedef union {\r
- UINT32 Data;\r
- UINT16 SerialNumber16[2];\r
- UINT8 SerialNumber8[4];\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
} SPD4_MANUFACTURER_SERIAL_NUMBER;\r
\r
typedef struct {\r
- UINT8 Location; ///< Module Manufacturing Location\r
+ UINT8 Location; ///< Module Manufacturing Location\r
} SPD4_MANUFACTURING_LOCATION;\r
\r
typedef struct {\r
- SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
- SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
- SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
- SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+ SPD4_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD4_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD4_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
} SPD4_UNIQUE_MODULE_ID;\r
\r
typedef union {\r
- UINT16 Crc[1];\r
- UINT8 Data8[2];\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
} SPD4_CYCLIC_REDUNDANCY_CODE;\r
\r
typedef struct {\r
- SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
- SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
- SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
- SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
- SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
- SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
- SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type\r
- SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
- SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
- SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
- SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType;///< 10 Secondary SDRAM Package Type\r
- SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
- SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
- SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
- SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
- SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
- UINT8 Reserved0; ///< 16 Reserved\r
- SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
- SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
- SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
- SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
- SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
- SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)\r
- SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC\r
- SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
- SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
- SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)\r
- SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)\r
- SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)\r
- SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW\r
- SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)\r
- SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group\r
- SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group\r
- SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group\r
- SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin\r
- SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)\r
- SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin\r
- SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group\r
- SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group\r
- UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved\r
- SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
- UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved\r
- SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group\r
- SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group\r
- SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group\r
- SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
- SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)\r
- SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
- SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)\r
- SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)\r
- SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+ SPD4_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD4_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD4_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType; ///< 6 Primary SDRAM Package Type\r
+ SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
+ SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
+ SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
+ SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType; ///< 10 Secondary SDRAM Package Type\r
+ SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
+ SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
+ SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
+ SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
+ SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
+ UINT8 Reserved0; ///< 16 Reserved\r
+ SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
+ SPD4_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
+ SPD4_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
+ SPD4_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD4_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)\r
+ SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC\r
+ SPD4_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r
+ SPD4_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)\r
+ SPD4_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)\r
+ SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW\r
+ SPD4_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)\r
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group\r
+ SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group\r
+ SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group\r
+ SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble; ///< 41 Upper Nibble for tWRmin\r
+ SPD4_TWR_MIN_MTB_STRUCT tWRmin; ///< 42 Minimum Write Recovery Time (tWRmin)\r
+ SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble; ///< 43 Upper Nibbles for tWTRmin\r
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group\r
+ SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group\r
+ UINT8 Reserved1[59 - 46 + 1]; ///< 46-59 Reserved\r
+ SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
+ UINT8 Reserved2[116 - 78 + 1]; ///< 78-116 Reserved\r
+ SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group\r
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group\r
+ SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group\r
+ SPD4_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r
+ SPD4_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)\r
+ SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD4_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)\r
+ SPD4_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
} SPD4_BASE_SECTION;\r
\r
typedef struct {\r
- SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
- SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
- SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
- SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM\r
- UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved\r
- SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+ SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM\r
+ UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
} SPD4_MODULE_UNBUFFERED;\r
\r
typedef struct {\r
- SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
- SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
- SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
- SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
- SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
- SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
- SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
- SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM\r
- SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
- SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
- UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved\r
- SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+ SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
+ SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
+ SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
+ SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM; ///< 136 Address Mapping from Register to DRAM\r
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
+ SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
+ UINT8 Reserved[253 - 139 + 1]; ///< 253-139 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
} SPD4_MODULE_REGISTERED;\r
\r
typedef struct {\r
- SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
- SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
- SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
- SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
- SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
- SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
- SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
- SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM\r
- SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
- SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
- SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number\r
- SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0\r
- SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1\r
- SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2\r
- SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3\r
- SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface\r
- SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866\r
- SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400\r
- SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200\r
- SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength\r
- SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866\r
- SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400\r
- SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200\r
- SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866\r
- SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400\r
- SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200\r
- SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range\r
- SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization\r
- UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved\r
- SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+ SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes\r
+ SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 132 RDIMM Thermal Heat Spreader Solution\r
+ SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 133-134 Register Manufacturer ID Code\r
+ SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 135 Register Revision Number\r
+ SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram; ///< 136 Address Mapping from Register to DRAM\r
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress; ///< 137 Register Output Drive Strength for Control and Command Address\r
+ SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock; ///< 138 Register Output Drive Strength for Clock\r
+ SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber; ///< 139 Data Buffer Revision Number\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0; ///< 140 DRAM VrefDQ for Package Rank 0\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1; ///< 141 DRAM VrefDQ for Package Rank 1\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2; ///< 142 DRAM VrefDQ for Package Rank 2\r
+ SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3; ///< 143 DRAM VrefDQ for Package Rank 3\r
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface; ///< 144 Data Buffer VrefDQ for DRAM Interface\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400\r
+ SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200\r
+ SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength; ///< 148 DRAM Drive Strength\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400\r
+ SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200\r
+ SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange; ///< 155 Data Buffer VrefDQ for DRAM Interface Range\r
+ SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization; ///< 156 Data Buffer DQ Decision Feedback Equalization\r
+ UINT8 Reserved[253 - 157 + 1]; ///< 253-132 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
} SPD4_MODULE_LOADREDUCED;\r
\r
typedef struct {\r
- UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved\r
- SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier\r
- SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code\r
- SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier\r
- SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code\r
- SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used\r
- SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics\r
- SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types\r
- SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time\r
- SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors\r
- UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved\r
- SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+ UINT8 Reserved0[191 - 128 + 1]; ///< 128-191 Reserved\r
+ SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier; ///< 192-193 Module Product Identifier\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode; ///< 194-195 Subsystem Controller Manufacturer's ID Code\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier; ///< 196-197 Subsystem Controller Identifier\r
+ SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode; ///< 198 Subsystem Controller Revision Code\r
+ SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 199 Reference Raw Card Used\r
+ SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics; ///< 200 Module Characteristics\r
+ SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes; ///< 201-202 Hybrid Module Media Types\r
+ SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime; ///< 203 Maximum Non-Volatile Memory Initialization Time\r
+ SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors[8]; ///< 204-219 Function Interface Descriptors\r
+ UINT8 Reserved[253 - 220 + 1]; ///< 220-253 Reserved\r
+ SPD4_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
} SPD4_MODULE_NVDIMM;\r
\r
typedef union {\r
- SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
- SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
- SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
- SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters\r
+ SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r
+ SPD4_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r
+ SPD4_MODULE_NVDIMM NonVolatile; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters\r
} SPD4_MODULE_SPECIFIC;\r
\r
typedef struct {\r
- UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
} SPD4_MODULE_PART_NUMBER;\r
\r
typedef struct {\r
- UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
} SPD4_MANUFACTURER_SPECIFIC;\r
\r
-typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
-typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping\r
+typedef UINT8 SPD4_MODULE_REVISION_CODE; ///< 349 Module Revision Code\r
+typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping\r
\r
typedef struct {\r
- SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
- SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
- SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
- SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
- SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
- SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
- UINT8 Reserved[2]; ///< 382-383 Reserved\r
+ SPD4_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
+ SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
+ SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
+ SPD4_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
+ SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
+ SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 Reserved[2]; ///< 382-383 Reserved\r
} SPD4_MANUFACTURING_DATA;\r
\r
typedef struct {\r
- UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types\r
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types\r
} SPD4_END_USER_SECTION;\r
\r
///\r
/// DDR4 Serial Presence Detect structure\r
///\r
typedef struct {\r
- SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
- SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
- UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved\r
- SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
- SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
+ SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
+ SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Reserved\r
+ SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
+ SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
} SPD_DDR4;\r
\r
#pragma pack (pop)\r
\r
typedef union {\r
struct {\r
- UINT8 BytesUsed : 4; ///< Bits 3:0\r
- UINT8 BytesTotal : 3; ///< Bits 6:4\r
- UINT8 CrcCoverage : 1; ///< Bits 7:7\r
+ UINT8 BytesUsed : 4; ///< Bits 3:0\r
+ UINT8 BytesTotal : 3; ///< Bits 6:4\r
+ UINT8 CrcCoverage : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Minor : 4; ///< Bits 3:0\r
- UINT8 Major : 4; ///< Bits 7:4\r
+ UINT8 Minor : 4; ///< Bits 3:0\r
+ UINT8 Major : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_REVISION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Type : 8; ///< Bits 7:0\r
+ UINT8 Type : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ModuleType : 4; ///< Bits 3:0\r
- UINT8 HybridMedia : 3; ///< Bits 6:4\r
- UINT8 Hybrid : 1; ///< Bits 7:7\r
+ UINT8 ModuleType : 4; ///< Bits 3:0\r
+ UINT8 HybridMedia : 3; ///< Bits 6:4\r
+ UINT8 Hybrid : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Density : 4; ///< Bits 3:0\r
- UINT8 BankAddress : 2; ///< Bits 5:4\r
- UINT8 BankGroup : 2; ///< Bits 7:6\r
+ UINT8 Density : 4; ///< Bits 3:0\r
+ UINT8 BankAddress : 2; ///< Bits 5:4\r
+ UINT8 BankGroup : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ColumnAddress : 3; ///< Bits 2:0\r
- UINT8 RowAddress : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 ColumnAddress : 3; ///< Bits 2:0\r
+ UINT8 RowAddress : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SignalLoading : 2; ///< Bits 1:0\r
- UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r
- UINT8 DieCount : 3; ///< Bits 6:4\r
- UINT8 SdramPackageType : 1; ///< Bits 7:7\r
+ UINT8 SignalLoading : 2; ///< Bits 1:0\r
+ UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r
+ UINT8 DieCount : 3; ///< Bits 6:4\r
+ UINT8 SdramPackageType : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
- UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
+ UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 8; ///< Bits 7:0\r
+ UINT8 Reserved : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 5; ///< Bits 4:0\r
- UINT8 SoftPPR : 1; ///< Bits 5:5\r
- UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
+ UINT8 Reserved : 5; ///< Bits 4:0\r
+ UINT8 SoftPPR : 1; ///< Bits 5:5\r
+ UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
- UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
- UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r
- UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r
- UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r
- UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
+ UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r
+ UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r
+ UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r
+ UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
- UINT8 RankCount : 3; ///< Bits 5:3\r
- UINT8 Reserved : 2; ///< Bits 7:6\r
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
+ UINT8 RankCount : 3; ///< Bits 5:3\r
+ UINT8 Reserved : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
- UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
- UINT8 NumberofChannels : 3; ///< Bits 7:5\r
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
+ UINT8 NumberofChannels : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Reserved : 7; ///< Bits 6:0\r
- UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
+ UINT8 Reserved : 7; ///< Bits 6:0\r
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r
- UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r
- UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r
+ UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r
+ UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r
+ UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_SIGNAL_LOADING_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 Fine : 2; ///< Bits 1:0\r
- UINT8 Medium : 2; ///< Bits 3:2\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 Fine : 2; ///< Bits 1:0\r
+ UINT8 Medium : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TIMEBASE_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmin : 8; ///< Bits 7:0\r
+ UINT8 tCKmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TCK_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tCKmax : 8; ///< Bits 7:0\r
+ UINT8 tCKmax : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TCK_MAX_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT32 Cl3 : 1; ///< Bits 0:0\r
- UINT32 Cl6 : 1; ///< Bits 1:1\r
- UINT32 Cl8 : 1; ///< Bits 2:2\r
- UINT32 Cl9 : 1; ///< Bits 3:3\r
- UINT32 Cl10 : 1; ///< Bits 4:4\r
- UINT32 Cl11 : 1; ///< Bits 5:5\r
- UINT32 Cl12 : 1; ///< Bits 6:6\r
- UINT32 Cl14 : 1; ///< Bits 7:7\r
- UINT32 Cl16 : 1; ///< Bits 8:8\r
- UINT32 Reserved0 : 1; ///< Bits 9:9\r
- UINT32 Cl20 : 1; ///< Bits 10:10\r
- UINT32 Cl22 : 1; ///< Bits 11:11\r
- UINT32 Cl24 : 1; ///< Bits 12:12\r
- UINT32 Reserved1 : 1; ///< Bits 13:13\r
- UINT32 Cl28 : 1; ///< Bits 14:14\r
- UINT32 Reserved2 : 1; ///< Bits 15:15\r
- UINT32 Cl32 : 1; ///< Bits 16:16\r
- UINT32 Reserved3 : 1; ///< Bits 17:17\r
- UINT32 Cl36 : 1; ///< Bits 18:18\r
- UINT32 Reserved4 : 1; ///< Bits 19:19\r
- UINT32 Cl40 : 1; ///< Bits 20:20\r
- UINT32 Reserved5 : 11; ///< Bits 31:21\r
- } Bits;\r
- UINT32 Data;\r
- UINT16 Data16[2];\r
- UINT8 Data8[4];\r
+ UINT32 Cl3 : 1; ///< Bits 0:0\r
+ UINT32 Cl6 : 1; ///< Bits 1:1\r
+ UINT32 Cl8 : 1; ///< Bits 2:2\r
+ UINT32 Cl9 : 1; ///< Bits 3:3\r
+ UINT32 Cl10 : 1; ///< Bits 4:4\r
+ UINT32 Cl11 : 1; ///< Bits 5:5\r
+ UINT32 Cl12 : 1; ///< Bits 6:6\r
+ UINT32 Cl14 : 1; ///< Bits 7:7\r
+ UINT32 Cl16 : 1; ///< Bits 8:8\r
+ UINT32 Reserved0 : 1; ///< Bits 9:9\r
+ UINT32 Cl20 : 1; ///< Bits 10:10\r
+ UINT32 Cl22 : 1; ///< Bits 11:11\r
+ UINT32 Cl24 : 1; ///< Bits 12:12\r
+ UINT32 Reserved1 : 1; ///< Bits 13:13\r
+ UINT32 Cl28 : 1; ///< Bits 14:14\r
+ UINT32 Reserved2 : 1; ///< Bits 15:15\r
+ UINT32 Cl32 : 1; ///< Bits 16:16\r
+ UINT32 Reserved3 : 1; ///< Bits 17:17\r
+ UINT32 Cl36 : 1; ///< Bits 18:18\r
+ UINT32 Reserved4 : 1; ///< Bits 19:19\r
+ UINT32 Cl40 : 1; ///< Bits 20:20\r
+ UINT32 Reserved5 : 11; ///< Bits 31:21\r
+ } Bits;\r
+ UINT32 Data;\r
+ UINT16 Data16[2];\r
+ UINT8 Data8[4];\r
} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tAAmin : 8; ///< Bits 7:0\r
+ UINT8 tAAmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TAA_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r
- UINT8 WriteLatencySet : 2; ///< Bits 3:2\r
- UINT8 Reserved : 4; ///< Bits 7:4\r
+ UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r
+ UINT8 WriteLatencySet : 2; ///< Bits 3:2\r
+ UINT8 Reserved : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRCDmin : 8; ///< Bits 7:0\r
+ UINT8 tRCDmin : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRPab : 8; ///< Bits 7:0\r
+ UINT8 tRPab : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TRP_AB_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 tRPpb : 8; ///< Bits 7:0\r
+ UINT8 tRPpb : 8; ///< Bits 7:0\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_TRP_PB_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 tRFCab : 16; ///< Bits 15:0\r
+ UINT16 tRFCab : 16; ///< Bits 15:0\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD_LPDDR_TRFC_AB_MTB_STRUCT;\r
\r
typedef union {\r
-struct {\r
- UINT16 tRFCpb : 16; ///< Bits 15:0\r
+ struct {\r
+ UINT16 tRFCpb : 16; ///< Bits 15:0\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD_LPDDR_TRFC_PB_MTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
- UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
- UINT8 PackageRankMap : 2; ///< Bits 7:6\r
+ UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
+ UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
+ UINT8 PackageRankMap : 2; ///< Bits 7:6\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRPpbFine : 8; ///< Bits 7:0\r
+ INT8 tRPpbFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TRP_PB_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRPabFine : 8; ///< Bits 7:0\r
+ INT8 tRPabFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TRP_AB_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tRCDminFine : 8; ///< Bits 7:0\r
+ INT8 tRCDminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tAAminFine : 8; ///< Bits 7:0\r
+ INT8 tAAminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TAA_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKmaxFine : 8; ///< Bits 7:0\r
+ INT8 tCKmaxFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TCK_MAX_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- INT8 tCKminFine : 8; ///< Bits 7:0\r
+ INT8 tCKminFine : 8; ///< Bits 7:0\r
} Bits;\r
- INT8 Data;\r
+ INT8 Data;\r
} SPD_LPDDR_TCK_MIN_FTB_STRUCT;\r
\r
typedef union {\r
struct {\r
- UINT16 ContinuationCount : 7; ///< Bits 6:0\r
- UINT16 ContinuationParity : 1; ///< Bits 7:7\r
- UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
+ UINT16 ContinuationCount : 7; ///< Bits 6:0\r
+ UINT16 ContinuationParity : 1; ///< Bits 7:7\r
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
} Bits;\r
- UINT16 Data;\r
- UINT8 Data8[2];\r
+ UINT16 Data;\r
+ UINT8 Data8[2];\r
} SPD_LPDDR_MANUFACTURER_ID_CODE;\r
\r
typedef struct {\r
- UINT8 Location; ///< Module Manufacturing Location\r
+ UINT8 Location; ///< Module Manufacturing Location\r
} SPD_LPDDR_MANUFACTURING_LOCATION;\r
\r
typedef struct {\r
- UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
- UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
} SPD_LPDDR_MANUFACTURING_DATE;\r
\r
typedef union {\r
- UINT32 Data;\r
- UINT16 SerialNumber16[2];\r
- UINT8 SerialNumber8[4];\r
+ UINT32 Data;\r
+ UINT16 SerialNumber16[2];\r
+ UINT8 SerialNumber8[4];\r
} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;\r
\r
typedef struct {\r
- SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
- SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
- SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
- SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
+ SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
+ SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
+ SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
} SPD_LPDDR_UNIQUE_MODULE_ID;\r
\r
typedef union {\r
struct {\r
- UINT8 FrontThickness : 4; ///< Bits 3:0\r
- UINT8 BackThickness : 4; ///< Bits 7:4\r
+ UINT8 FrontThickness : 4; ///< Bits 3:0\r
+ UINT8 BackThickness : 4; ///< Bits 7:4\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;\r
\r
typedef union {\r
struct {\r
- UINT8 Height : 5; ///< Bits 4:0\r
- UINT8 RawCardExtension : 3; ///< Bits 7:5\r
+ UINT8 Height : 5; ///< Bits 4:0\r
+ UINT8 RawCardExtension : 3; ///< Bits 7:5\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;\r
\r
typedef union {\r
struct {\r
- UINT8 Card : 5; ///< Bits 4:0\r
- UINT8 Revision : 2; ///< Bits 6:5\r
- UINT8 Extension : 1; ///< Bits 7:7\r
+ UINT8 Card : 5; ///< Bits 4:0\r
+ UINT8 Revision : 2; ///< Bits 6:5\r
+ UINT8 Extension : 1; ///< Bits 7:7\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} SPD_LPDDR_REFERENCE_RAW_CARD;\r
\r
typedef union {\r
- UINT16 Crc[1];\r
- UINT8 Data8[2];\r
+ UINT16 Crc[1];\r
+ UINT8 Data8[2];\r
} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;\r
\r
typedef struct {\r
- SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
- SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
- SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
- SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
- SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
- SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
- SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r
- SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
- SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
- SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
- UINT8 Reserved0; ///< 10 Reserved\r
- SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
- SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
- SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
- SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
- SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
- SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r
- SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
- SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
- SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
- SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
- SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
- SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r
- SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r
- SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r
- SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r
- SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r
- UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r
- SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
- UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r
- SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r
- SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r
- SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
- SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
- SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r
- SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
- SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
+ SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
+ SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
+ SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
+ SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
+ SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
+ SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
+ SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r
+ SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
+ SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
+ SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
+ UINT8 Reserved0; ///< 10 Reserved\r
+ SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
+ SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
+ SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
+ SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
+ SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
+ SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r
+ SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
+ SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
+ SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r
+ SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r
+ SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r
+ SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r
+ SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r
+ UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r
+ SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
+ UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r
+ SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r
+ SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r
+ SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
+ SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
+ SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r
+ SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
} SPD_LPDDR_BASE_SECTION;\r
\r
typedef struct {\r
- SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
- SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
- SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
- UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r
- SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
+ SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
+ SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
+ SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
+ UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r
+ SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
} SPD_LPDDR_MODULE_LPDIMM;\r
\r
typedef struct {\r
- SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r
+ SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r
} SPD_LPDDR_MODULE_SPECIFIC;\r
\r
typedef struct {\r
- UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
} SPD_LPDDR_MODULE_PART_NUMBER;\r
\r
typedef struct {\r
- UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
} SPD_LPDDR_MANUFACTURER_SPECIFIC;\r
\r
-typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
-typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r
+typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE; ///< 349 Module Revision Code\r
+typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r
\r
typedef struct {\r
- SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
- SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
- SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
- SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
- SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
- SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
- UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r
+ SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
+ SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
+ SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
+ SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
+ SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
+ SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
+ UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r
} SPD_LPDDR_MANUFACTURING_DATA;\r
\r
typedef struct {\r
- UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r
+ UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r
} SPD_LPDDR_END_USER_SECTION;\r
\r
///\r
/// LPDDR Serial Presence Detect structure\r
///\r
typedef struct {\r
- SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
- SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
- UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r
- SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
- SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
+ SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
+ SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
+ UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r
+ SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
+ SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
} SPD_LPDDR;\r
\r
#pragma pack (pop)\r
#ifndef _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_\r
#define _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_\r
\r
-\r
#include <IndustryStandard/Acpi.h>\r
\r
//\r
///\r
/// SPCR Revision (defined in spec)\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x02\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x02\r
\r
///\r
/// Serial Port Console Redirection Table Format\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT8 InterfaceType;\r
- UINT8 Reserved1[3];\r
- EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
- UINT8 InterruptType;\r
- UINT8 Irq;\r
- UINT32 GlobalSystemInterrupt;\r
- UINT8 BaudRate;\r
- UINT8 Parity;\r
- UINT8 StopBits;\r
- UINT8 FlowControl;\r
- UINT8 TerminalType;\r
- UINT8 Reserved2;\r
- UINT16 PciDeviceId;\r
- UINT16 PciVendorId;\r
- UINT8 PciBusNumber;\r
- UINT8 PciDeviceNumber;\r
- UINT8 PciFunctionNumber;\r
- UINT32 PciFlags;\r
- UINT8 PciSegment;\r
- UINT32 Reserved3;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT8 InterfaceType;\r
+ UINT8 Reserved1[3];\r
+ EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
+ UINT8 InterruptType;\r
+ UINT8 Irq;\r
+ UINT32 GlobalSystemInterrupt;\r
+ UINT8 BaudRate;\r
+ UINT8 Parity;\r
+ UINT8 StopBits;\r
+ UINT8 FlowControl;\r
+ UINT8 TerminalType;\r
+ UINT8 Reserved2;\r
+ UINT16 PciDeviceId;\r
+ UINT16 PciVendorId;\r
+ UINT8 PciBusNumber;\r
+ UINT8 PciDeviceNumber;\r
+ UINT8 PciFunctionNumber;\r
+ UINT32 PciFlags;\r
+ UINT8 PciSegment;\r
+ UINT32 Reserved3;\r
} EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE;\r
\r
#pragma pack()\r
///\r
/// Full 16550 interface\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 0\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 0\r
///\r
/// Full 16450 interface\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450 1\r
-\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450 1\r
\r
//\r
// The Serial Port Subtypes for ARM are documented in Table 3 of the DBG2 Specification\r
///\r
/// ARM PL011 UART\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART 0x03\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART 0x03\r
\r
///\r
/// NVIDIA 16550 UART\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_NVIDIA_16550_UART 0x05\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_NVIDIA_16550_UART 0x05\r
\r
///\r
/// ARM SBSA Generic UART (2.x) supporting 32-bit only accesses [deprecated]\r
///\r
/// ARM SBSA Generic UART\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART 0x0e\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART 0x0e\r
\r
///\r
/// ARM DCC\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_DCC 0x0f\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_DCC 0x0f\r
\r
///\r
/// BCM2835 UART\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART 0x10\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART 0x10\r
\r
///\r
/// 16550-compatible with parameters defined in Generic Address Structure\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550_WITH_GAS 0x12\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550_WITH_GAS 0x12\r
\r
//\r
// Interrupt Type\r
///\r
/// PC-AT-compatible dual-8259 IRQ interrupt\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259 0x1\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259 0x1\r
///\r
/// I/O APIC interrupt (Global System Interrupt)\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC 0x2\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC 0x2\r
///\r
/// I/O SAPIC interrupt (Global System Interrupt)\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC 0x4\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC 0x4\r
///\r
/// ARMH GIC interrupt (Global System Interrupt)\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC 0x8\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC 0x8\r
\r
//\r
// Baud Rate\r
//\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600 3\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200 4\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600 6\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200 7\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_9600 3\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_19200 4\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_57600 6\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200 7\r
\r
//\r
// Parity\r
//\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY 0\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY 0\r
\r
//\r
// Stop Bits\r
//\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1 1\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1 1\r
\r
//\r
// Flow Control\r
///\r
/// DCD required for transmit\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD 0x1\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD 0x1\r
///\r
/// RTS/CTS hardware flow control\r
///\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS 0x2\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS 0x2\r
///\r
/// XON/XOFF software control\r
///\r
//\r
// Terminal Type\r
//\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100 0\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100_PLUS 1\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8 2\r
-#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI 3\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100 0\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT100_PLUS 1\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8 2\r
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI 3\r
\r
#endif\r
v2.0 Revision 1.1, Dated October 2013.\r
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf\r
**/\r
+\r
#ifndef _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_\r
#define _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_\r
\r
/// For PCI IPMI device\r
///\r
struct {\r
- UINT8 SegmentGroup;\r
- UINT8 Bus;\r
- UINT8 Device;\r
- UINT8 Function;\r
+ UINT8 SegmentGroup;\r
+ UINT8 Bus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
} Pci;\r
///\r
/// For non-PCI IPMI device, the ACPI _UID value of the device\r
///\r
- UINT32 Uid;\r
+ UINT32 Uid;\r
} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID;\r
\r
-\r
///\r
/// Definition for Service Processor Management Interface Description Table\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
///\r
/// Indicates the type of IPMI interface.\r
///\r
- UINT8 InterfaceType;\r
+ UINT8 InterfaceType;\r
///\r
/// This field must always be 01h to be compatible with any software that\r
/// implements previous versions of this spec.\r
///\r
- UINT8 Reserved1;\r
+ UINT8 Reserved1;\r
///\r
/// Identifies the IPMI specification revision, in BCD format.\r
///\r
- UINT16 SpecificationRevision;\r
+ UINT16 SpecificationRevision;\r
///\r
/// Interrupt type(s) used by the interface.\r
///\r
- UINT8 InterruptType;\r
+ UINT8 InterruptType;\r
///\r
/// The bit assignment of the SCI interrupt within the GPEx_STS register of a\r
/// GPE described if the FADT that the interface triggers.\r
///\r
- UINT8 Gpe;\r
+ UINT8 Gpe;\r
///\r
/// Reserved, must be 00h.\r
///\r
- UINT8 Reserved2;\r
+ UINT8 Reserved2;\r
///\r
/// PCI Device Flag.\r
///\r
- UINT8 PciDeviceFlag;\r
+ UINT8 PciDeviceFlag;\r
///\r
/// The I/O APIC or I/O SAPIC Global System Interrupt used by the interface.\r
///\r
- UINT32 GlobalSystemInterrupt;\r
+ UINT32 GlobalSystemInterrupt;\r
///\r
/// The base address of the interface register set described using the\r
/// Generic Address Structure (GAS, See [ACPI 2.0] for the definition).\r
///\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
///\r
/// Device identification information.\r
///\r
/// This field must always be null (0x00) to be compatible with any software\r
/// that implements previous versions of this spec.\r
///\r
- UINT8 Reserved3;\r
+ UINT8 Reserved3;\r
} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE;\r
\r
#pragma pack()\r
/// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for\r
/// use by this specification.\r
///\r
-#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r
+#define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r
\r
///\r
/// Reference SMBIOS 2.7, chapter 6.1.2.\r
/// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."\r
/// This number is not used for any other purpose by the SMBIOS specification.\r
///\r
-#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r
+#define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r
\r
///\r
/// Reference SMBIOS 2.6, chapter 3.1.3.\r
/// Reference SMBIOS 2.7, chapter 6.1.3.\r
/// It will have no limit on the length of each individual text string.\r
///\r
-#define SMBIOS_STRING_MAX_LENGTH 64\r
+#define SMBIOS_STRING_MAX_LENGTH 64\r
\r
//\r
// The length of the entire structure table (including all strings) must be reported\r
// in the Structure Table Length field of the SMBIOS Structure Table Entry Point,\r
// which is a WORD field limited to 65,535 bytes.\r
//\r
-#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF\r
+#define SMBIOS_TABLE_MAX_LENGTH 0xFFFF\r
\r
//\r
// For SMBIOS 3.0, Structure table maximum size in Entry Point structure is DWORD field limited to 0xFFFFFFFF bytes.\r
//\r
-#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF\r
+#define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF\r
\r
//\r
// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.\r
//\r
-#define SMBIOS_TYPE_BIOS_INFORMATION 0\r
-#define SMBIOS_TYPE_SYSTEM_INFORMATION 1\r
-#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2\r
-#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3\r
-#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4\r
-#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5\r
-#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6\r
-#define SMBIOS_TYPE_CACHE_INFORMATION 7\r
-#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8\r
-#define SMBIOS_TYPE_SYSTEM_SLOTS 9\r
-#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10\r
-#define SMBIOS_TYPE_OEM_STRINGS 11\r
-#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12\r
-#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13\r
-#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14\r
-#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15\r
-#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16\r
-#define SMBIOS_TYPE_MEMORY_DEVICE 17\r
-#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18\r
-#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19\r
-#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20\r
-#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21\r
-#define SMBIOS_TYPE_PORTABLE_BATTERY 22\r
-#define SMBIOS_TYPE_SYSTEM_RESET 23\r
-#define SMBIOS_TYPE_HARDWARE_SECURITY 24\r
-#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25\r
-#define SMBIOS_TYPE_VOLTAGE_PROBE 26\r
-#define SMBIOS_TYPE_COOLING_DEVICE 27\r
-#define SMBIOS_TYPE_TEMPERATURE_PROBE 28\r
-#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29\r
-#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30\r
-#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31\r
-#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32\r
-#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33\r
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34\r
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35\r
-#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36\r
-#define SMBIOS_TYPE_MEMORY_CHANNEL 37\r
-#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38\r
-#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39\r
-#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40\r
-#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41\r
-#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42\r
-#define SMBIOS_TYPE_TPM_DEVICE 43\r
-#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44\r
+#define SMBIOS_TYPE_BIOS_INFORMATION 0\r
+#define SMBIOS_TYPE_SYSTEM_INFORMATION 1\r
+#define SMBIOS_TYPE_BASEBOARD_INFORMATION 2\r
+#define SMBIOS_TYPE_SYSTEM_ENCLOSURE 3\r
+#define SMBIOS_TYPE_PROCESSOR_INFORMATION 4\r
+#define SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION 5\r
+#define SMBIOS_TYPE_MEMORY_MODULE_INFORMATON 6\r
+#define SMBIOS_TYPE_CACHE_INFORMATION 7\r
+#define SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION 8\r
+#define SMBIOS_TYPE_SYSTEM_SLOTS 9\r
+#define SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION 10\r
+#define SMBIOS_TYPE_OEM_STRINGS 11\r
+#define SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS 12\r
+#define SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION 13\r
+#define SMBIOS_TYPE_GROUP_ASSOCIATIONS 14\r
+#define SMBIOS_TYPE_SYSTEM_EVENT_LOG 15\r
+#define SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY 16\r
+#define SMBIOS_TYPE_MEMORY_DEVICE 17\r
+#define SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION 18\r
+#define SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS 19\r
+#define SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS 20\r
+#define SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE 21\r
+#define SMBIOS_TYPE_PORTABLE_BATTERY 22\r
+#define SMBIOS_TYPE_SYSTEM_RESET 23\r
+#define SMBIOS_TYPE_HARDWARE_SECURITY 24\r
+#define SMBIOS_TYPE_SYSTEM_POWER_CONTROLS 25\r
+#define SMBIOS_TYPE_VOLTAGE_PROBE 26\r
+#define SMBIOS_TYPE_COOLING_DEVICE 27\r
+#define SMBIOS_TYPE_TEMPERATURE_PROBE 28\r
+#define SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE 29\r
+#define SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS 30\r
+#define SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE 31\r
+#define SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION 32\r
+#define SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION 33\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE 34\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT 35\r
+#define SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA 36\r
+#define SMBIOS_TYPE_MEMORY_CHANNEL 37\r
+#define SMBIOS_TYPE_IPMI_DEVICE_INFORMATION 38\r
+#define SMBIOS_TYPE_SYSTEM_POWER_SUPPLY 39\r
+#define SMBIOS_TYPE_ADDITIONAL_INFORMATION 40\r
+#define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41\r
+#define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42\r
+#define SMBIOS_TYPE_TPM_DEVICE 43\r
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION 44\r
\r
///\r
/// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r
/// Upper-level software that interprets the SMBIOS structure-table should bypass an\r
/// Inactive structure just like a structure type that the software does not recognize.\r
///\r
-#define SMBIOS_TYPE_INACTIVE 0x007E\r
+#define SMBIOS_TYPE_INACTIVE 0x007E\r
\r
///\r
/// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.\r
/// The end-of-table indicator is used in the last physical structure in a table\r
///\r
-#define SMBIOS_TYPE_END_OF_TABLE 0x007F\r
+#define SMBIOS_TYPE_END_OF_TABLE 0x007F\r
\r
-#define SMBIOS_OEM_BEGIN 128\r
-#define SMBIOS_OEM_END 255\r
+#define SMBIOS_OEM_BEGIN 128\r
+#define SMBIOS_OEM_END 255\r
\r
///\r
/// Types 0 through 127 (7Fh) are reserved for and defined by this\r
/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.\r
///\r
-typedef UINT8 SMBIOS_TYPE;\r
+typedef UINT8 SMBIOS_TYPE;\r
\r
///\r
/// Specifies the structure's handle, a unique 16-bit number in the range 0 to 0FFFEh (for version\r
///\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 AnchorString[4];\r
- UINT8 EntryPointStructureChecksum;\r
- UINT8 EntryPointLength;\r
- UINT8 MajorVersion;\r
- UINT8 MinorVersion;\r
- UINT16 MaxStructureSize;\r
- UINT8 EntryPointRevision;\r
- UINT8 FormattedArea[5];\r
- UINT8 IntermediateAnchorString[5];\r
- UINT8 IntermediateChecksum;\r
- UINT16 TableLength;\r
- UINT32 TableAddress;\r
- UINT16 NumberOfSmbiosStructures;\r
- UINT8 SmbiosBcdRevision;\r
+ UINT8 AnchorString[4];\r
+ UINT8 EntryPointStructureChecksum;\r
+ UINT8 EntryPointLength;\r
+ UINT8 MajorVersion;\r
+ UINT8 MinorVersion;\r
+ UINT16 MaxStructureSize;\r
+ UINT8 EntryPointRevision;\r
+ UINT8 FormattedArea[5];\r
+ UINT8 IntermediateAnchorString[5];\r
+ UINT8 IntermediateChecksum;\r
+ UINT16 TableLength;\r
+ UINT32 TableAddress;\r
+ UINT16 NumberOfSmbiosStructures;\r
+ UINT8 SmbiosBcdRevision;\r
} SMBIOS_TABLE_ENTRY_POINT;\r
\r
typedef struct {\r
- UINT8 AnchorString[5];\r
- UINT8 EntryPointStructureChecksum;\r
- UINT8 EntryPointLength;\r
- UINT8 MajorVersion;\r
- UINT8 MinorVersion;\r
- UINT8 DocRev;\r
- UINT8 EntryPointRevision;\r
- UINT8 Reserved;\r
- UINT32 TableMaximumSize;\r
- UINT64 TableAddress;\r
+ UINT8 AnchorString[5];\r
+ UINT8 EntryPointStructureChecksum;\r
+ UINT8 EntryPointLength;\r
+ UINT8 MajorVersion;\r
+ UINT8 MinorVersion;\r
+ UINT8 DocRev;\r
+ UINT8 EntryPointRevision;\r
+ UINT8 Reserved;\r
+ UINT32 TableMaximumSize;\r
+ UINT64 TableAddress;\r
} SMBIOS_TABLE_3_0_ENTRY_POINT;\r
\r
///\r
/// The Smbios structure header.\r
///\r
typedef struct {\r
- SMBIOS_TYPE Type;\r
- UINT8 Length;\r
- SMBIOS_HANDLE Handle;\r
+ SMBIOS_TYPE Type;\r
+ UINT8 Length;\r
+ SMBIOS_HANDLE Handle;\r
} SMBIOS_STRUCTURE;\r
\r
///\r
/// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.\r
///\r
typedef struct {\r
- UINT32 Reserved :2; ///< Bits 0-1.\r
- UINT32 Unknown :1;\r
- UINT32 BiosCharacteristicsNotSupported :1;\r
- UINT32 IsaIsSupported :1;\r
- UINT32 McaIsSupported :1;\r
- UINT32 EisaIsSupported :1;\r
- UINT32 PciIsSupported :1;\r
- UINT32 PcmciaIsSupported :1;\r
- UINT32 PlugAndPlayIsSupported :1;\r
- UINT32 ApmIsSupported :1;\r
- UINT32 BiosIsUpgradable :1;\r
- UINT32 BiosShadowingAllowed :1;\r
- UINT32 VlVesaIsSupported :1;\r
- UINT32 EscdSupportIsAvailable :1;\r
- UINT32 BootFromCdIsSupported :1;\r
- UINT32 SelectableBootIsSupported :1;\r
- UINT32 RomBiosIsSocketed :1;\r
- UINT32 BootFromPcmciaIsSupported :1;\r
- UINT32 EDDSpecificationIsSupported :1;\r
- UINT32 JapaneseNecFloppyIsSupported :1;\r
- UINT32 JapaneseToshibaFloppyIsSupported :1;\r
- UINT32 Floppy525_360IsSupported :1;\r
- UINT32 Floppy525_12IsSupported :1;\r
- UINT32 Floppy35_720IsSupported :1;\r
- UINT32 Floppy35_288IsSupported :1;\r
- UINT32 PrintScreenIsSupported :1;\r
- UINT32 Keyboard8042IsSupported :1;\r
- UINT32 SerialIsSupported :1;\r
- UINT32 PrinterIsSupported :1;\r
- UINT32 CgaMonoIsSupported :1;\r
- UINT32 NecPc98 :1;\r
- UINT32 ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor\r
- ///< and bits 48-63 reserved for System Vendor.\r
+ UINT32 Reserved : 2; ///< Bits 0-1.\r
+ UINT32 Unknown : 1;\r
+ UINT32 BiosCharacteristicsNotSupported : 1;\r
+ UINT32 IsaIsSupported : 1;\r
+ UINT32 McaIsSupported : 1;\r
+ UINT32 EisaIsSupported : 1;\r
+ UINT32 PciIsSupported : 1;\r
+ UINT32 PcmciaIsSupported : 1;\r
+ UINT32 PlugAndPlayIsSupported : 1;\r
+ UINT32 ApmIsSupported : 1;\r
+ UINT32 BiosIsUpgradable : 1;\r
+ UINT32 BiosShadowingAllowed : 1;\r
+ UINT32 VlVesaIsSupported : 1;\r
+ UINT32 EscdSupportIsAvailable : 1;\r
+ UINT32 BootFromCdIsSupported : 1;\r
+ UINT32 SelectableBootIsSupported : 1;\r
+ UINT32 RomBiosIsSocketed : 1;\r
+ UINT32 BootFromPcmciaIsSupported : 1;\r
+ UINT32 EDDSpecificationIsSupported : 1;\r
+ UINT32 JapaneseNecFloppyIsSupported : 1;\r
+ UINT32 JapaneseToshibaFloppyIsSupported : 1;\r
+ UINT32 Floppy525_360IsSupported : 1;\r
+ UINT32 Floppy525_12IsSupported : 1;\r
+ UINT32 Floppy35_720IsSupported : 1;\r
+ UINT32 Floppy35_288IsSupported : 1;\r
+ UINT32 PrintScreenIsSupported : 1;\r
+ UINT32 Keyboard8042IsSupported : 1;\r
+ UINT32 SerialIsSupported : 1;\r
+ UINT32 PrinterIsSupported : 1;\r
+ UINT32 CgaMonoIsSupported : 1;\r
+ UINT32 NecPc98 : 1;\r
+ UINT32 ReservedForVendor : 32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor\r
+ ///< and bits 48-63 reserved for System Vendor.\r
} MISC_BIOS_CHARACTERISTICS;\r
\r
///\r
/// within the BIOS Information structure.\r
///\r
typedef struct {\r
- UINT8 AcpiIsSupported :1;\r
- UINT8 UsbLegacyIsSupported :1;\r
- UINT8 AgpIsSupported :1;\r
- UINT8 I2OBootIsSupported :1;\r
- UINT8 Ls120BootIsSupported :1;\r
- UINT8 AtapiZipDriveBootIsSupported :1;\r
- UINT8 Boot1394IsSupported :1;\r
- UINT8 SmartBatteryIsSupported :1;\r
+ UINT8 AcpiIsSupported : 1;\r
+ UINT8 UsbLegacyIsSupported : 1;\r
+ UINT8 AgpIsSupported : 1;\r
+ UINT8 I2OBootIsSupported : 1;\r
+ UINT8 Ls120BootIsSupported : 1;\r
+ UINT8 AtapiZipDriveBootIsSupported : 1;\r
+ UINT8 Boot1394IsSupported : 1;\r
+ UINT8 SmartBatteryIsSupported : 1;\r
} MBCE_BIOS_RESERVED;\r
\r
///\r
/// within the BIOS Information structure.\r
///\r
typedef struct {\r
- UINT8 BiosBootSpecIsSupported :1;\r
- UINT8 FunctionKeyNetworkBootIsSupported :1;\r
- UINT8 TargetContentDistributionEnabled :1;\r
- UINT8 UefiSpecificationSupported :1;\r
- UINT8 VirtualMachineSupported :1;\r
- UINT8 ExtensionByte2Reserved :3;\r
+ UINT8 BiosBootSpecIsSupported : 1;\r
+ UINT8 FunctionKeyNetworkBootIsSupported : 1;\r
+ UINT8 TargetContentDistributionEnabled : 1;\r
+ UINT8 UefiSpecificationSupported : 1;\r
+ UINT8 VirtualMachineSupported : 1;\r
+ UINT8 ExtensionByte2Reserved : 3;\r
} MBCE_SYSTEM_RESERVED;\r
\r
///\r
/// BIOS Characteristics Extension Bytes.\r
///\r
typedef struct {\r
- MBCE_BIOS_RESERVED BiosReserved;\r
- MBCE_SYSTEM_RESERVED SystemReserved;\r
+ MBCE_BIOS_RESERVED BiosReserved;\r
+ MBCE_SYSTEM_RESERVED SystemReserved;\r
} MISC_BIOS_CHARACTERISTICS_EXTENSION;\r
\r
///\r
/// Extended BIOS ROM size.\r
///\r
typedef struct {\r
- UINT16 Size :14;\r
- UINT16 Unit :2;\r
+ UINT16 Size : 14;\r
+ UINT16 Unit : 2;\r
} EXTENDED_BIOS_ROM_SIZE;\r
\r
///\r
/// BIOS Information (Type 0).\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Vendor;\r
- SMBIOS_TABLE_STRING BiosVersion;\r
- UINT16 BiosSegment;\r
- SMBIOS_TABLE_STRING BiosReleaseDate;\r
- UINT8 BiosSize;\r
- MISC_BIOS_CHARACTERISTICS BiosCharacteristics;\r
- UINT8 BIOSCharacteristicsExtensionBytes[2];\r
- UINT8 SystemBiosMajorRelease;\r
- UINT8 SystemBiosMinorRelease;\r
- UINT8 EmbeddedControllerFirmwareMajorRelease;\r
- UINT8 EmbeddedControllerFirmwareMinorRelease;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Vendor;\r
+ SMBIOS_TABLE_STRING BiosVersion;\r
+ UINT16 BiosSegment;\r
+ SMBIOS_TABLE_STRING BiosReleaseDate;\r
+ UINT8 BiosSize;\r
+ MISC_BIOS_CHARACTERISTICS BiosCharacteristics;\r
+ UINT8 BIOSCharacteristicsExtensionBytes[2];\r
+ UINT8 SystemBiosMajorRelease;\r
+ UINT8 SystemBiosMinorRelease;\r
+ UINT8 EmbeddedControllerFirmwareMajorRelease;\r
+ UINT8 EmbeddedControllerFirmwareMinorRelease;\r
//\r
// Add for smbios 3.1.0\r
//\r
- EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;\r
+ EXTENDED_BIOS_ROM_SIZE ExtendedBiosSize;\r
} SMBIOS_TABLE_TYPE0;\r
\r
///\r
/// System Wake-up Type.\r
///\r
typedef enum {\r
- SystemWakeupTypeReserved = 0x00,\r
- SystemWakeupTypeOther = 0x01,\r
- SystemWakeupTypeUnknown = 0x02,\r
- SystemWakeupTypeApmTimer = 0x03,\r
- SystemWakeupTypeModemRing = 0x04,\r
- SystemWakeupTypeLanRemote = 0x05,\r
- SystemWakeupTypePowerSwitch = 0x06,\r
- SystemWakeupTypePciPme = 0x07,\r
- SystemWakeupTypeAcPowerRestored = 0x08\r
+ SystemWakeupTypeReserved = 0x00,\r
+ SystemWakeupTypeOther = 0x01,\r
+ SystemWakeupTypeUnknown = 0x02,\r
+ SystemWakeupTypeApmTimer = 0x03,\r
+ SystemWakeupTypeModemRing = 0x04,\r
+ SystemWakeupTypeLanRemote = 0x05,\r
+ SystemWakeupTypePowerSwitch = 0x06,\r
+ SystemWakeupTypePciPme = 0x07,\r
+ SystemWakeupTypeAcPowerRestored = 0x08\r
} MISC_SYSTEM_WAKEUP_TYPE;\r
\r
///\r
/// one and only one System Information (Type 1) structure.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- SMBIOS_TABLE_STRING ProductName;\r
- SMBIOS_TABLE_STRING Version;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- GUID Uuid;\r
- UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.\r
- SMBIOS_TABLE_STRING SKUNumber;\r
- SMBIOS_TABLE_STRING Family;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ SMBIOS_TABLE_STRING ProductName;\r
+ SMBIOS_TABLE_STRING Version;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ GUID Uuid;\r
+ UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.\r
+ SMBIOS_TABLE_STRING SKUNumber;\r
+ SMBIOS_TABLE_STRING Family;\r
} SMBIOS_TABLE_TYPE1;\r
\r
///\r
/// Base Board - Feature Flags.\r
///\r
typedef struct {\r
- UINT8 Motherboard :1;\r
- UINT8 RequiresDaughterCard :1;\r
- UINT8 Removable :1;\r
- UINT8 Replaceable :1;\r
- UINT8 HotSwappable :1;\r
- UINT8 Reserved :3;\r
+ UINT8 Motherboard : 1;\r
+ UINT8 RequiresDaughterCard : 1;\r
+ UINT8 Removable : 1;\r
+ UINT8 Replaceable : 1;\r
+ UINT8 HotSwappable : 1;\r
+ UINT8 Reserved : 3;\r
} BASE_BOARD_FEATURE_FLAGS;\r
\r
///\r
/// Base Board - Board Type.\r
///\r
typedef enum {\r
- BaseBoardTypeUnknown = 0x1,\r
- BaseBoardTypeOther = 0x2,\r
- BaseBoardTypeServerBlade = 0x3,\r
- BaseBoardTypeConnectivitySwitch = 0x4,\r
- BaseBoardTypeSystemManagementModule = 0x5,\r
- BaseBoardTypeProcessorModule = 0x6,\r
- BaseBoardTypeIOModule = 0x7,\r
- BaseBoardTypeMemoryModule = 0x8,\r
- BaseBoardTypeDaughterBoard = 0x9,\r
- BaseBoardTypeMotherBoard = 0xA,\r
- BaseBoardTypeProcessorMemoryModule = 0xB,\r
- BaseBoardTypeProcessorIOModule = 0xC,\r
- BaseBoardTypeInterconnectBoard = 0xD\r
+ BaseBoardTypeUnknown = 0x1,\r
+ BaseBoardTypeOther = 0x2,\r
+ BaseBoardTypeServerBlade = 0x3,\r
+ BaseBoardTypeConnectivitySwitch = 0x4,\r
+ BaseBoardTypeSystemManagementModule = 0x5,\r
+ BaseBoardTypeProcessorModule = 0x6,\r
+ BaseBoardTypeIOModule = 0x7,\r
+ BaseBoardTypeMemoryModule = 0x8,\r
+ BaseBoardTypeDaughterBoard = 0x9,\r
+ BaseBoardTypeMotherBoard = 0xA,\r
+ BaseBoardTypeProcessorMemoryModule = 0xB,\r
+ BaseBoardTypeProcessorIOModule = 0xC,\r
+ BaseBoardTypeInterconnectBoard = 0xD\r
} BASE_BOARD_TYPE;\r
\r
///\r
/// for example a motherboard, planar, or server blade or other standard system module.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- SMBIOS_TABLE_STRING ProductName;\r
- SMBIOS_TABLE_STRING Version;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING AssetTag;\r
- BASE_BOARD_FEATURE_FLAGS FeatureFlag;\r
- SMBIOS_TABLE_STRING LocationInChassis;\r
- UINT16 ChassisHandle;\r
- UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.\r
- UINT8 NumberOfContainedObjectHandles;\r
- UINT16 ContainedObjectHandles[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ SMBIOS_TABLE_STRING ProductName;\r
+ SMBIOS_TABLE_STRING Version;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING AssetTag;\r
+ BASE_BOARD_FEATURE_FLAGS FeatureFlag;\r
+ SMBIOS_TABLE_STRING LocationInChassis;\r
+ UINT16 ChassisHandle;\r
+ UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.\r
+ UINT8 NumberOfContainedObjectHandles;\r
+ UINT16 ContainedObjectHandles[1];\r
} SMBIOS_TABLE_TYPE2;\r
\r
///\r
/// System Enclosure or Chassis Types\r
///\r
typedef enum {\r
- MiscChassisTypeOther = 0x01,\r
- MiscChassisTypeUnknown = 0x02,\r
- MiscChassisTypeDeskTop = 0x03,\r
- MiscChassisTypeLowProfileDesktop = 0x04,\r
- MiscChassisTypePizzaBox = 0x05,\r
- MiscChassisTypeMiniTower = 0x06,\r
- MiscChassisTypeTower = 0x07,\r
- MiscChassisTypePortable = 0x08,\r
- MiscChassisTypeLapTop = 0x09,\r
- MiscChassisTypeNotebook = 0x0A,\r
- MiscChassisTypeHandHeld = 0x0B,\r
- MiscChassisTypeDockingStation = 0x0C,\r
- MiscChassisTypeAllInOne = 0x0D,\r
- MiscChassisTypeSubNotebook = 0x0E,\r
- MiscChassisTypeSpaceSaving = 0x0F,\r
- MiscChassisTypeLunchBox = 0x10,\r
- MiscChassisTypeMainServerChassis = 0x11,\r
- MiscChassisTypeExpansionChassis = 0x12,\r
- MiscChassisTypeSubChassis = 0x13,\r
- MiscChassisTypeBusExpansionChassis = 0x14,\r
- MiscChassisTypePeripheralChassis = 0x15,\r
- MiscChassisTypeRaidChassis = 0x16,\r
- MiscChassisTypeRackMountChassis = 0x17,\r
- MiscChassisTypeSealedCasePc = 0x18,\r
- MiscChassisMultiSystemChassis = 0x19,\r
- MiscChassisCompactPCI = 0x1A,\r
- MiscChassisAdvancedTCA = 0x1B,\r
- MiscChassisBlade = 0x1C,\r
- MiscChassisBladeEnclosure = 0x1D,\r
- MiscChassisTablet = 0x1E,\r
- MiscChassisConvertible = 0x1F,\r
- MiscChassisDetachable = 0x20,\r
- MiscChassisIoTGateway = 0x21,\r
- MiscChassisEmbeddedPc = 0x22,\r
- MiscChassisMiniPc = 0x23,\r
- MiscChassisStickPc = 0x24\r
+ MiscChassisTypeOther = 0x01,\r
+ MiscChassisTypeUnknown = 0x02,\r
+ MiscChassisTypeDeskTop = 0x03,\r
+ MiscChassisTypeLowProfileDesktop = 0x04,\r
+ MiscChassisTypePizzaBox = 0x05,\r
+ MiscChassisTypeMiniTower = 0x06,\r
+ MiscChassisTypeTower = 0x07,\r
+ MiscChassisTypePortable = 0x08,\r
+ MiscChassisTypeLapTop = 0x09,\r
+ MiscChassisTypeNotebook = 0x0A,\r
+ MiscChassisTypeHandHeld = 0x0B,\r
+ MiscChassisTypeDockingStation = 0x0C,\r
+ MiscChassisTypeAllInOne = 0x0D,\r
+ MiscChassisTypeSubNotebook = 0x0E,\r
+ MiscChassisTypeSpaceSaving = 0x0F,\r
+ MiscChassisTypeLunchBox = 0x10,\r
+ MiscChassisTypeMainServerChassis = 0x11,\r
+ MiscChassisTypeExpansionChassis = 0x12,\r
+ MiscChassisTypeSubChassis = 0x13,\r
+ MiscChassisTypeBusExpansionChassis = 0x14,\r
+ MiscChassisTypePeripheralChassis = 0x15,\r
+ MiscChassisTypeRaidChassis = 0x16,\r
+ MiscChassisTypeRackMountChassis = 0x17,\r
+ MiscChassisTypeSealedCasePc = 0x18,\r
+ MiscChassisMultiSystemChassis = 0x19,\r
+ MiscChassisCompactPCI = 0x1A,\r
+ MiscChassisAdvancedTCA = 0x1B,\r
+ MiscChassisBlade = 0x1C,\r
+ MiscChassisBladeEnclosure = 0x1D,\r
+ MiscChassisTablet = 0x1E,\r
+ MiscChassisConvertible = 0x1F,\r
+ MiscChassisDetachable = 0x20,\r
+ MiscChassisIoTGateway = 0x21,\r
+ MiscChassisEmbeddedPc = 0x22,\r
+ MiscChassisMiniPc = 0x23,\r
+ MiscChassisStickPc = 0x24\r
} MISC_CHASSIS_TYPE;\r
\r
///\r
/// System Enclosure or Chassis States .\r
///\r
typedef enum {\r
- ChassisStateOther = 0x01,\r
- ChassisStateUnknown = 0x02,\r
- ChassisStateSafe = 0x03,\r
- ChassisStateWarning = 0x04,\r
- ChassisStateCritical = 0x05,\r
- ChassisStateNonRecoverable = 0x06\r
+ ChassisStateOther = 0x01,\r
+ ChassisStateUnknown = 0x02,\r
+ ChassisStateSafe = 0x03,\r
+ ChassisStateWarning = 0x04,\r
+ ChassisStateCritical = 0x05,\r
+ ChassisStateNonRecoverable = 0x06\r
} MISC_CHASSIS_STATE;\r
\r
///\r
/// Contained Element record\r
///\r
typedef struct {\r
- UINT8 ContainedElementType;\r
- UINT8 ContainedElementMinimum;\r
- UINT8 ContainedElementMaximum;\r
+ UINT8 ContainedElementType;\r
+ UINT8 ContainedElementMinimum;\r
+ UINT8 ContainedElementMaximum;\r
} CONTAINED_ELEMENT;\r
\r
-\r
///\r
/// System Enclosure or Chassis (Type 3).\r
///\r
/// support the population of the CIM_Chassis class.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- UINT8 Type;\r
- SMBIOS_TABLE_STRING Version;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING AssetTag;\r
- UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
- UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
- UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
- UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.\r
- UINT8 OemDefined[4];\r
- UINT8 Height;\r
- UINT8 NumberofPowerCords;\r
- UINT8 ContainedElementCount;\r
- UINT8 ContainedElementRecordLength;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ UINT8 Type;\r
+ SMBIOS_TABLE_STRING Version;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING AssetTag;\r
+ UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
+ UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
+ UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.\r
+ UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.\r
+ UINT8 OemDefined[4];\r
+ UINT8 Height;\r
+ UINT8 NumberofPowerCords;\r
+ UINT8 ContainedElementCount;\r
+ UINT8 ContainedElementRecordLength;\r
//\r
// Can have 0 to (ContainedElementCount * ContainedElementRecordLength) contained elements\r
//\r
- CONTAINED_ELEMENT ContainedElements[1];\r
+ CONTAINED_ELEMENT ContainedElements[1];\r
//\r
// Add for smbios 2.7\r
//\r
/// Processor Information - Processor Family.\r
///\r
typedef enum {\r
- ProcessorFamilyOther = 0x01,\r
- ProcessorFamilyUnknown = 0x02,\r
- ProcessorFamily8086 = 0x03,\r
- ProcessorFamily80286 = 0x04,\r
- ProcessorFamilyIntel386 = 0x05,\r
- ProcessorFamilyIntel486 = 0x06,\r
- ProcessorFamily8087 = 0x07,\r
- ProcessorFamily80287 = 0x08,\r
- ProcessorFamily80387 = 0x09,\r
- ProcessorFamily80487 = 0x0A,\r
- ProcessorFamilyPentium = 0x0B,\r
- ProcessorFamilyPentiumPro = 0x0C,\r
- ProcessorFamilyPentiumII = 0x0D,\r
- ProcessorFamilyPentiumMMX = 0x0E,\r
- ProcessorFamilyCeleron = 0x0F,\r
- ProcessorFamilyPentiumIIXeon = 0x10,\r
- ProcessorFamilyPentiumIII = 0x11,\r
- ProcessorFamilyM1 = 0x12,\r
- ProcessorFamilyM2 = 0x13,\r
- ProcessorFamilyIntelCeleronM = 0x14,\r
- ProcessorFamilyIntelPentium4Ht = 0x15,\r
- ProcessorFamilyAmdDuron = 0x18,\r
- ProcessorFamilyK5 = 0x19,\r
- ProcessorFamilyK6 = 0x1A,\r
- ProcessorFamilyK6_2 = 0x1B,\r
- ProcessorFamilyK6_3 = 0x1C,\r
- ProcessorFamilyAmdAthlon = 0x1D,\r
- ProcessorFamilyAmd29000 = 0x1E,\r
- ProcessorFamilyK6_2Plus = 0x1F,\r
- ProcessorFamilyPowerPC = 0x20,\r
- ProcessorFamilyPowerPC601 = 0x21,\r
- ProcessorFamilyPowerPC603 = 0x22,\r
- ProcessorFamilyPowerPC603Plus = 0x23,\r
- ProcessorFamilyPowerPC604 = 0x24,\r
- ProcessorFamilyPowerPC620 = 0x25,\r
- ProcessorFamilyPowerPCx704 = 0x26,\r
- ProcessorFamilyPowerPC750 = 0x27,\r
- ProcessorFamilyIntelCoreDuo = 0x28,\r
- ProcessorFamilyIntelCoreDuoMobile = 0x29,\r
- ProcessorFamilyIntelCoreSoloMobile = 0x2A,\r
- ProcessorFamilyIntelAtom = 0x2B,\r
- ProcessorFamilyIntelCoreM = 0x2C,\r
- ProcessorFamilyIntelCorem3 = 0x2D,\r
- ProcessorFamilyIntelCorem5 = 0x2E,\r
- ProcessorFamilyIntelCorem7 = 0x2F,\r
- ProcessorFamilyAlpha = 0x30,\r
- ProcessorFamilyAlpha21064 = 0x31,\r
- ProcessorFamilyAlpha21066 = 0x32,\r
- ProcessorFamilyAlpha21164 = 0x33,\r
- ProcessorFamilyAlpha21164PC = 0x34,\r
- ProcessorFamilyAlpha21164a = 0x35,\r
- ProcessorFamilyAlpha21264 = 0x36,\r
- ProcessorFamilyAlpha21364 = 0x37,\r
- ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,\r
- ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,\r
- ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,\r
- ProcessorFamilyAmdOpteron6100Series = 0x3B,\r
- ProcessorFamilyAmdOpteron4100Series = 0x3C,\r
- ProcessorFamilyAmdOpteron6200Series = 0x3D,\r
- ProcessorFamilyAmdOpteron4200Series = 0x3E,\r
- ProcessorFamilyAmdFxSeries = 0x3F,\r
- ProcessorFamilyMips = 0x40,\r
- ProcessorFamilyMIPSR4000 = 0x41,\r
- ProcessorFamilyMIPSR4200 = 0x42,\r
- ProcessorFamilyMIPSR4400 = 0x43,\r
- ProcessorFamilyMIPSR4600 = 0x44,\r
- ProcessorFamilyMIPSR10000 = 0x45,\r
- ProcessorFamilyAmdCSeries = 0x46,\r
- ProcessorFamilyAmdESeries = 0x47,\r
- ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name\r
- ProcessorFamilyAmdGSeries = 0x49,\r
- ProcessorFamilyAmdZSeries = 0x4A,\r
- ProcessorFamilyAmdRSeries = 0x4B,\r
- ProcessorFamilyAmdOpteron4300 = 0x4C,\r
- ProcessorFamilyAmdOpteron6300 = 0x4D,\r
- ProcessorFamilyAmdOpteron3300 = 0x4E,\r
- ProcessorFamilyAmdFireProSeries = 0x4F,\r
- ProcessorFamilySparc = 0x50,\r
- ProcessorFamilySuperSparc = 0x51,\r
- ProcessorFamilymicroSparcII = 0x52,\r
- ProcessorFamilymicroSparcIIep = 0x53,\r
- ProcessorFamilyUltraSparc = 0x54,\r
- ProcessorFamilyUltraSparcII = 0x55,\r
- ProcessorFamilyUltraSparcIii = 0x56,\r
- ProcessorFamilyUltraSparcIII = 0x57,\r
- ProcessorFamilyUltraSparcIIIi = 0x58,\r
- ProcessorFamily68040 = 0x60,\r
- ProcessorFamily68xxx = 0x61,\r
- ProcessorFamily68000 = 0x62,\r
- ProcessorFamily68010 = 0x63,\r
- ProcessorFamily68020 = 0x64,\r
- ProcessorFamily68030 = 0x65,\r
- ProcessorFamilyAmdAthlonX4QuadCore = 0x66,\r
- ProcessorFamilyAmdOpteronX1000Series = 0x67,\r
- ProcessorFamilyAmdOpteronX2000Series = 0x68,\r
- ProcessorFamilyAmdOpteronASeries = 0x69,\r
- ProcessorFamilyAmdOpteronX3000Series = 0x6A,\r
- ProcessorFamilyAmdZen = 0x6B,\r
- ProcessorFamilyHobbit = 0x70,\r
- ProcessorFamilyCrusoeTM5000 = 0x78,\r
- ProcessorFamilyCrusoeTM3000 = 0x79,\r
- ProcessorFamilyEfficeonTM8000 = 0x7A,\r
- ProcessorFamilyWeitek = 0x80,\r
- ProcessorFamilyItanium = 0x82,\r
- ProcessorFamilyAmdAthlon64 = 0x83,\r
- ProcessorFamilyAmdOpteron = 0x84,\r
- ProcessorFamilyAmdSempron = 0x85,\r
- ProcessorFamilyAmdTurion64Mobile = 0x86,\r
- ProcessorFamilyDualCoreAmdOpteron = 0x87,\r
- ProcessorFamilyAmdAthlon64X2DualCore = 0x88,\r
- ProcessorFamilyAmdTurion64X2Mobile = 0x89,\r
- ProcessorFamilyQuadCoreAmdOpteron = 0x8A,\r
- ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,\r
- ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,\r
- ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,\r
- ProcessorFamilyAmdPhenomX2DualCore = 0x8E,\r
- ProcessorFamilyAmdAthlonX2DualCore = 0x8F,\r
- ProcessorFamilyPARISC = 0x90,\r
- ProcessorFamilyPaRisc8500 = 0x91,\r
- ProcessorFamilyPaRisc8000 = 0x92,\r
- ProcessorFamilyPaRisc7300LC = 0x93,\r
- ProcessorFamilyPaRisc7200 = 0x94,\r
- ProcessorFamilyPaRisc7100LC = 0x95,\r
- ProcessorFamilyPaRisc7100 = 0x96,\r
- ProcessorFamilyV30 = 0xA0,\r
- ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,\r
- ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,\r
- ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,\r
- ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,\r
- ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,\r
- ProcessorFamilyDualCoreIntelXeonLV = 0xA6,\r
- ProcessorFamilyDualCoreIntelXeonULV = 0xA7,\r
- ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,\r
- ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,\r
- ProcessorFamilyQuadCoreIntelXeon = 0xAA,\r
- ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,\r
- ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,\r
- ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,\r
- ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,\r
- ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,\r
- ProcessorFamilyPentiumIIIXeon = 0xB0,\r
- ProcessorFamilyPentiumIIISpeedStep = 0xB1,\r
- ProcessorFamilyPentium4 = 0xB2,\r
- ProcessorFamilyIntelXeon = 0xB3,\r
- ProcessorFamilyAS400 = 0xB4,\r
- ProcessorFamilyIntelXeonMP = 0xB5,\r
- ProcessorFamilyAMDAthlonXP = 0xB6,\r
- ProcessorFamilyAMDAthlonMP = 0xB7,\r
- ProcessorFamilyIntelItanium2 = 0xB8,\r
- ProcessorFamilyIntelPentiumM = 0xB9,\r
- ProcessorFamilyIntelCeleronD = 0xBA,\r
- ProcessorFamilyIntelPentiumD = 0xBB,\r
- ProcessorFamilyIntelPentiumEx = 0xBC,\r
- ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value\r
- ProcessorFamilyReserved = 0xBE,\r
- ProcessorFamilyIntelCore2 = 0xBF,\r
- ProcessorFamilyIntelCore2Solo = 0xC0,\r
- ProcessorFamilyIntelCore2Extreme = 0xC1,\r
- ProcessorFamilyIntelCore2Quad = 0xC2,\r
- ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,\r
- ProcessorFamilyIntelCore2DuoMobile = 0xC4,\r
- ProcessorFamilyIntelCore2SoloMobile = 0xC5,\r
- ProcessorFamilyIntelCoreI7 = 0xC6,\r
- ProcessorFamilyDualCoreIntelCeleron = 0xC7,\r
- ProcessorFamilyIBM390 = 0xC8,\r
- ProcessorFamilyG4 = 0xC9,\r
- ProcessorFamilyG5 = 0xCA,\r
- ProcessorFamilyG6 = 0xCB,\r
- ProcessorFamilyzArchitecture = 0xCC,\r
- ProcessorFamilyIntelCoreI5 = 0xCD,\r
- ProcessorFamilyIntelCoreI3 = 0xCE,\r
- ProcessorFamilyIntelCoreI9 = 0xCF,\r
- ProcessorFamilyViaC7M = 0xD2,\r
- ProcessorFamilyViaC7D = 0xD3,\r
- ProcessorFamilyViaC7 = 0xD4,\r
- ProcessorFamilyViaEden = 0xD5,\r
- ProcessorFamilyMultiCoreIntelXeon = 0xD6,\r
- ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,\r
- ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,\r
- ProcessorFamilyViaNano = 0xD9,\r
- ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,\r
- ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,\r
- ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,\r
- ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,\r
- ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,\r
- ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r
- ProcessorFamilyAmdOpteron3000Series = 0xE4,\r
- ProcessorFamilyAmdSempronII = 0xE5,\r
- ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,\r
- ProcessorFamilyAmdPhenomTripleCore = 0xE7,\r
- ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r
- ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,\r
- ProcessorFamilyAmdAthlonDualCore = 0xEA,\r
- ProcessorFamilyAmdSempronSI = 0xEB,\r
- ProcessorFamilyAmdPhenomII = 0xEC,\r
- ProcessorFamilyAmdAthlonII = 0xED,\r
- ProcessorFamilySixCoreAmdOpteron = 0xEE,\r
- ProcessorFamilyAmdSempronM = 0xEF,\r
- ProcessorFamilyi860 = 0xFA,\r
- ProcessorFamilyi960 = 0xFB,\r
- ProcessorFamilyIndicatorFamily2 = 0xFE,\r
- ProcessorFamilyReserved1 = 0xFF\r
+ ProcessorFamilyOther = 0x01,\r
+ ProcessorFamilyUnknown = 0x02,\r
+ ProcessorFamily8086 = 0x03,\r
+ ProcessorFamily80286 = 0x04,\r
+ ProcessorFamilyIntel386 = 0x05,\r
+ ProcessorFamilyIntel486 = 0x06,\r
+ ProcessorFamily8087 = 0x07,\r
+ ProcessorFamily80287 = 0x08,\r
+ ProcessorFamily80387 = 0x09,\r
+ ProcessorFamily80487 = 0x0A,\r
+ ProcessorFamilyPentium = 0x0B,\r
+ ProcessorFamilyPentiumPro = 0x0C,\r
+ ProcessorFamilyPentiumII = 0x0D,\r
+ ProcessorFamilyPentiumMMX = 0x0E,\r
+ ProcessorFamilyCeleron = 0x0F,\r
+ ProcessorFamilyPentiumIIXeon = 0x10,\r
+ ProcessorFamilyPentiumIII = 0x11,\r
+ ProcessorFamilyM1 = 0x12,\r
+ ProcessorFamilyM2 = 0x13,\r
+ ProcessorFamilyIntelCeleronM = 0x14,\r
+ ProcessorFamilyIntelPentium4Ht = 0x15,\r
+ ProcessorFamilyAmdDuron = 0x18,\r
+ ProcessorFamilyK5 = 0x19,\r
+ ProcessorFamilyK6 = 0x1A,\r
+ ProcessorFamilyK6_2 = 0x1B,\r
+ ProcessorFamilyK6_3 = 0x1C,\r
+ ProcessorFamilyAmdAthlon = 0x1D,\r
+ ProcessorFamilyAmd29000 = 0x1E,\r
+ ProcessorFamilyK6_2Plus = 0x1F,\r
+ ProcessorFamilyPowerPC = 0x20,\r
+ ProcessorFamilyPowerPC601 = 0x21,\r
+ ProcessorFamilyPowerPC603 = 0x22,\r
+ ProcessorFamilyPowerPC603Plus = 0x23,\r
+ ProcessorFamilyPowerPC604 = 0x24,\r
+ ProcessorFamilyPowerPC620 = 0x25,\r
+ ProcessorFamilyPowerPCx704 = 0x26,\r
+ ProcessorFamilyPowerPC750 = 0x27,\r
+ ProcessorFamilyIntelCoreDuo = 0x28,\r
+ ProcessorFamilyIntelCoreDuoMobile = 0x29,\r
+ ProcessorFamilyIntelCoreSoloMobile = 0x2A,\r
+ ProcessorFamilyIntelAtom = 0x2B,\r
+ ProcessorFamilyIntelCoreM = 0x2C,\r
+ ProcessorFamilyIntelCorem3 = 0x2D,\r
+ ProcessorFamilyIntelCorem5 = 0x2E,\r
+ ProcessorFamilyIntelCorem7 = 0x2F,\r
+ ProcessorFamilyAlpha = 0x30,\r
+ ProcessorFamilyAlpha21064 = 0x31,\r
+ ProcessorFamilyAlpha21066 = 0x32,\r
+ ProcessorFamilyAlpha21164 = 0x33,\r
+ ProcessorFamilyAlpha21164PC = 0x34,\r
+ ProcessorFamilyAlpha21164a = 0x35,\r
+ ProcessorFamilyAlpha21264 = 0x36,\r
+ ProcessorFamilyAlpha21364 = 0x37,\r
+ ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,\r
+ ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,\r
+ ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,\r
+ ProcessorFamilyAmdOpteron6100Series = 0x3B,\r
+ ProcessorFamilyAmdOpteron4100Series = 0x3C,\r
+ ProcessorFamilyAmdOpteron6200Series = 0x3D,\r
+ ProcessorFamilyAmdOpteron4200Series = 0x3E,\r
+ ProcessorFamilyAmdFxSeries = 0x3F,\r
+ ProcessorFamilyMips = 0x40,\r
+ ProcessorFamilyMIPSR4000 = 0x41,\r
+ ProcessorFamilyMIPSR4200 = 0x42,\r
+ ProcessorFamilyMIPSR4400 = 0x43,\r
+ ProcessorFamilyMIPSR4600 = 0x44,\r
+ ProcessorFamilyMIPSR10000 = 0x45,\r
+ ProcessorFamilyAmdCSeries = 0x46,\r
+ ProcessorFamilyAmdESeries = 0x47,\r
+ ProcessorFamilyAmdASeries = 0x48, ///< SMBIOS spec 2.8.0 updated the name\r
+ ProcessorFamilyAmdGSeries = 0x49,\r
+ ProcessorFamilyAmdZSeries = 0x4A,\r
+ ProcessorFamilyAmdRSeries = 0x4B,\r
+ ProcessorFamilyAmdOpteron4300 = 0x4C,\r
+ ProcessorFamilyAmdOpteron6300 = 0x4D,\r
+ ProcessorFamilyAmdOpteron3300 = 0x4E,\r
+ ProcessorFamilyAmdFireProSeries = 0x4F,\r
+ ProcessorFamilySparc = 0x50,\r
+ ProcessorFamilySuperSparc = 0x51,\r
+ ProcessorFamilymicroSparcII = 0x52,\r
+ ProcessorFamilymicroSparcIIep = 0x53,\r
+ ProcessorFamilyUltraSparc = 0x54,\r
+ ProcessorFamilyUltraSparcII = 0x55,\r
+ ProcessorFamilyUltraSparcIii = 0x56,\r
+ ProcessorFamilyUltraSparcIII = 0x57,\r
+ ProcessorFamilyUltraSparcIIIi = 0x58,\r
+ ProcessorFamily68040 = 0x60,\r
+ ProcessorFamily68xxx = 0x61,\r
+ ProcessorFamily68000 = 0x62,\r
+ ProcessorFamily68010 = 0x63,\r
+ ProcessorFamily68020 = 0x64,\r
+ ProcessorFamily68030 = 0x65,\r
+ ProcessorFamilyAmdAthlonX4QuadCore = 0x66,\r
+ ProcessorFamilyAmdOpteronX1000Series = 0x67,\r
+ ProcessorFamilyAmdOpteronX2000Series = 0x68,\r
+ ProcessorFamilyAmdOpteronASeries = 0x69,\r
+ ProcessorFamilyAmdOpteronX3000Series = 0x6A,\r
+ ProcessorFamilyAmdZen = 0x6B,\r
+ ProcessorFamilyHobbit = 0x70,\r
+ ProcessorFamilyCrusoeTM5000 = 0x78,\r
+ ProcessorFamilyCrusoeTM3000 = 0x79,\r
+ ProcessorFamilyEfficeonTM8000 = 0x7A,\r
+ ProcessorFamilyWeitek = 0x80,\r
+ ProcessorFamilyItanium = 0x82,\r
+ ProcessorFamilyAmdAthlon64 = 0x83,\r
+ ProcessorFamilyAmdOpteron = 0x84,\r
+ ProcessorFamilyAmdSempron = 0x85,\r
+ ProcessorFamilyAmdTurion64Mobile = 0x86,\r
+ ProcessorFamilyDualCoreAmdOpteron = 0x87,\r
+ ProcessorFamilyAmdAthlon64X2DualCore = 0x88,\r
+ ProcessorFamilyAmdTurion64X2Mobile = 0x89,\r
+ ProcessorFamilyQuadCoreAmdOpteron = 0x8A,\r
+ ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,\r
+ ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,\r
+ ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,\r
+ ProcessorFamilyAmdPhenomX2DualCore = 0x8E,\r
+ ProcessorFamilyAmdAthlonX2DualCore = 0x8F,\r
+ ProcessorFamilyPARISC = 0x90,\r
+ ProcessorFamilyPaRisc8500 = 0x91,\r
+ ProcessorFamilyPaRisc8000 = 0x92,\r
+ ProcessorFamilyPaRisc7300LC = 0x93,\r
+ ProcessorFamilyPaRisc7200 = 0x94,\r
+ ProcessorFamilyPaRisc7100LC = 0x95,\r
+ ProcessorFamilyPaRisc7100 = 0x96,\r
+ ProcessorFamilyV30 = 0xA0,\r
+ ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,\r
+ ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,\r
+ ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,\r
+ ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,\r
+ ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,\r
+ ProcessorFamilyDualCoreIntelXeonLV = 0xA6,\r
+ ProcessorFamilyDualCoreIntelXeonULV = 0xA7,\r
+ ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,\r
+ ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,\r
+ ProcessorFamilyQuadCoreIntelXeon = 0xAA,\r
+ ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,\r
+ ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,\r
+ ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,\r
+ ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,\r
+ ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,\r
+ ProcessorFamilyPentiumIIIXeon = 0xB0,\r
+ ProcessorFamilyPentiumIIISpeedStep = 0xB1,\r
+ ProcessorFamilyPentium4 = 0xB2,\r
+ ProcessorFamilyIntelXeon = 0xB3,\r
+ ProcessorFamilyAS400 = 0xB4,\r
+ ProcessorFamilyIntelXeonMP = 0xB5,\r
+ ProcessorFamilyAMDAthlonXP = 0xB6,\r
+ ProcessorFamilyAMDAthlonMP = 0xB7,\r
+ ProcessorFamilyIntelItanium2 = 0xB8,\r
+ ProcessorFamilyIntelPentiumM = 0xB9,\r
+ ProcessorFamilyIntelCeleronD = 0xBA,\r
+ ProcessorFamilyIntelPentiumD = 0xBB,\r
+ ProcessorFamilyIntelPentiumEx = 0xBC,\r
+ ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 updated this value\r
+ ProcessorFamilyReserved = 0xBE,\r
+ ProcessorFamilyIntelCore2 = 0xBF,\r
+ ProcessorFamilyIntelCore2Solo = 0xC0,\r
+ ProcessorFamilyIntelCore2Extreme = 0xC1,\r
+ ProcessorFamilyIntelCore2Quad = 0xC2,\r
+ ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,\r
+ ProcessorFamilyIntelCore2DuoMobile = 0xC4,\r
+ ProcessorFamilyIntelCore2SoloMobile = 0xC5,\r
+ ProcessorFamilyIntelCoreI7 = 0xC6,\r
+ ProcessorFamilyDualCoreIntelCeleron = 0xC7,\r
+ ProcessorFamilyIBM390 = 0xC8,\r
+ ProcessorFamilyG4 = 0xC9,\r
+ ProcessorFamilyG5 = 0xCA,\r
+ ProcessorFamilyG6 = 0xCB,\r
+ ProcessorFamilyzArchitecture = 0xCC,\r
+ ProcessorFamilyIntelCoreI5 = 0xCD,\r
+ ProcessorFamilyIntelCoreI3 = 0xCE,\r
+ ProcessorFamilyIntelCoreI9 = 0xCF,\r
+ ProcessorFamilyViaC7M = 0xD2,\r
+ ProcessorFamilyViaC7D = 0xD3,\r
+ ProcessorFamilyViaC7 = 0xD4,\r
+ ProcessorFamilyViaEden = 0xD5,\r
+ ProcessorFamilyMultiCoreIntelXeon = 0xD6,\r
+ ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,\r
+ ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,\r
+ ProcessorFamilyViaNano = 0xD9,\r
+ ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,\r
+ ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,\r
+ ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,\r
+ ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,\r
+ ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,\r
+ ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r
+ ProcessorFamilyAmdOpteron3000Series = 0xE4,\r
+ ProcessorFamilyAmdSempronII = 0xE5,\r
+ ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,\r
+ ProcessorFamilyAmdPhenomTripleCore = 0xE7,\r
+ ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r
+ ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,\r
+ ProcessorFamilyAmdAthlonDualCore = 0xEA,\r
+ ProcessorFamilyAmdSempronSI = 0xEB,\r
+ ProcessorFamilyAmdPhenomII = 0xEC,\r
+ ProcessorFamilyAmdAthlonII = 0xED,\r
+ ProcessorFamilySixCoreAmdOpteron = 0xEE,\r
+ ProcessorFamilyAmdSempronM = 0xEF,\r
+ ProcessorFamilyi860 = 0xFA,\r
+ ProcessorFamilyi960 = 0xFB,\r
+ ProcessorFamilyIndicatorFamily2 = 0xFE,\r
+ ProcessorFamilyReserved1 = 0xFF\r
} PROCESSOR_FAMILY_DATA;\r
\r
///\r
/// Processor Information2 - Processor Family2.\r
///\r
typedef enum {\r
- ProcessorFamilyARMv7 = 0x0100,\r
- ProcessorFamilyARMv8 = 0x0101,\r
- ProcessorFamilySH3 = 0x0104,\r
- ProcessorFamilySH4 = 0x0105,\r
- ProcessorFamilyARM = 0x0118,\r
- ProcessorFamilyStrongARM = 0x0119,\r
- ProcessorFamily6x86 = 0x012C,\r
- ProcessorFamilyMediaGX = 0x012D,\r
- ProcessorFamilyMII = 0x012E,\r
- ProcessorFamilyWinChip = 0x0140,\r
- ProcessorFamilyDSP = 0x015E,\r
- ProcessorFamilyVideoProcessor = 0x01F4,\r
- ProcessorFamilyRiscvRV32 = 0x0200,\r
- ProcessorFamilyRiscVRV64 = 0x0201,\r
- ProcessorFamilyRiscVRV128 = 0x0202\r
+ ProcessorFamilyARMv7 = 0x0100,\r
+ ProcessorFamilyARMv8 = 0x0101,\r
+ ProcessorFamilySH3 = 0x0104,\r
+ ProcessorFamilySH4 = 0x0105,\r
+ ProcessorFamilyARM = 0x0118,\r
+ ProcessorFamilyStrongARM = 0x0119,\r
+ ProcessorFamily6x86 = 0x012C,\r
+ ProcessorFamilyMediaGX = 0x012D,\r
+ ProcessorFamilyMII = 0x012E,\r
+ ProcessorFamilyWinChip = 0x0140,\r
+ ProcessorFamilyDSP = 0x015E,\r
+ ProcessorFamilyVideoProcessor = 0x01F4,\r
+ ProcessorFamilyRiscvRV32 = 0x0200,\r
+ ProcessorFamilyRiscVRV64 = 0x0201,\r
+ ProcessorFamilyRiscVRV128 = 0x0202\r
} PROCESSOR_FAMILY2_DATA;\r
\r
///\r
/// Processor Information - Voltage.\r
///\r
typedef struct {\r
- UINT8 ProcessorVoltageCapability5V :1;\r
- UINT8 ProcessorVoltageCapability3_3V :1;\r
- UINT8 ProcessorVoltageCapability2_9V :1;\r
- UINT8 ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero.\r
- UINT8 ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero.\r
- UINT8 ProcessorVoltageIndicateLegacy :1;\r
+ UINT8 ProcessorVoltageCapability5V : 1;\r
+ UINT8 ProcessorVoltageCapability3_3V : 1;\r
+ UINT8 ProcessorVoltageCapability2_9V : 1;\r
+ UINT8 ProcessorVoltageCapabilityReserved : 1; ///< Bit 3, must be zero.\r
+ UINT8 ProcessorVoltageReserved : 3; ///< Bits 4-6, must be zero.\r
+ UINT8 ProcessorVoltageIndicateLegacy : 1;\r
} PROCESSOR_VOLTAGE;\r
\r
///\r
/// Processor Information - Processor Upgrade.\r
///\r
typedef enum {\r
- ProcessorUpgradeOther = 0x01,\r
- ProcessorUpgradeUnknown = 0x02,\r
- ProcessorUpgradeDaughterBoard = 0x03,\r
- ProcessorUpgradeZIFSocket = 0x04,\r
- ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.\r
- ProcessorUpgradeNone = 0x06,\r
- ProcessorUpgradeLIFSocket = 0x07,\r
- ProcessorUpgradeSlot1 = 0x08,\r
- ProcessorUpgradeSlot2 = 0x09,\r
- ProcessorUpgrade370PinSocket = 0x0A,\r
- ProcessorUpgradeSlotA = 0x0B,\r
- ProcessorUpgradeSlotM = 0x0C,\r
- ProcessorUpgradeSocket423 = 0x0D,\r
- ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.\r
- ProcessorUpgradeSocket478 = 0x0F,\r
- ProcessorUpgradeSocket754 = 0x10,\r
- ProcessorUpgradeSocket940 = 0x11,\r
- ProcessorUpgradeSocket939 = 0x12,\r
- ProcessorUpgradeSocketmPGA604 = 0x13,\r
- ProcessorUpgradeSocketLGA771 = 0x14,\r
- ProcessorUpgradeSocketLGA775 = 0x15,\r
- ProcessorUpgradeSocketS1 = 0x16,\r
- ProcessorUpgradeAM2 = 0x17,\r
- ProcessorUpgradeF1207 = 0x18,\r
- ProcessorSocketLGA1366 = 0x19,\r
- ProcessorUpgradeSocketG34 = 0x1A,\r
- ProcessorUpgradeSocketAM3 = 0x1B,\r
- ProcessorUpgradeSocketC32 = 0x1C,\r
- ProcessorUpgradeSocketLGA1156 = 0x1D,\r
- ProcessorUpgradeSocketLGA1567 = 0x1E,\r
- ProcessorUpgradeSocketPGA988A = 0x1F,\r
- ProcessorUpgradeSocketBGA1288 = 0x20,\r
- ProcessorUpgradeSocketrPGA988B = 0x21,\r
- ProcessorUpgradeSocketBGA1023 = 0x22,\r
- ProcessorUpgradeSocketBGA1224 = 0x23,\r
- ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name\r
- ProcessorUpgradeSocketLGA1356 = 0x25,\r
- ProcessorUpgradeSocketLGA2011 = 0x26,\r
- ProcessorUpgradeSocketFS1 = 0x27,\r
- ProcessorUpgradeSocketFS2 = 0x28,\r
- ProcessorUpgradeSocketFM1 = 0x29,\r
- ProcessorUpgradeSocketFM2 = 0x2A,\r
+ ProcessorUpgradeOther = 0x01,\r
+ ProcessorUpgradeUnknown = 0x02,\r
+ ProcessorUpgradeDaughterBoard = 0x03,\r
+ ProcessorUpgradeZIFSocket = 0x04,\r
+ ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.\r
+ ProcessorUpgradeNone = 0x06,\r
+ ProcessorUpgradeLIFSocket = 0x07,\r
+ ProcessorUpgradeSlot1 = 0x08,\r
+ ProcessorUpgradeSlot2 = 0x09,\r
+ ProcessorUpgrade370PinSocket = 0x0A,\r
+ ProcessorUpgradeSlotA = 0x0B,\r
+ ProcessorUpgradeSlotM = 0x0C,\r
+ ProcessorUpgradeSocket423 = 0x0D,\r
+ ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.\r
+ ProcessorUpgradeSocket478 = 0x0F,\r
+ ProcessorUpgradeSocket754 = 0x10,\r
+ ProcessorUpgradeSocket940 = 0x11,\r
+ ProcessorUpgradeSocket939 = 0x12,\r
+ ProcessorUpgradeSocketmPGA604 = 0x13,\r
+ ProcessorUpgradeSocketLGA771 = 0x14,\r
+ ProcessorUpgradeSocketLGA775 = 0x15,\r
+ ProcessorUpgradeSocketS1 = 0x16,\r
+ ProcessorUpgradeAM2 = 0x17,\r
+ ProcessorUpgradeF1207 = 0x18,\r
+ ProcessorSocketLGA1366 = 0x19,\r
+ ProcessorUpgradeSocketG34 = 0x1A,\r
+ ProcessorUpgradeSocketAM3 = 0x1B,\r
+ ProcessorUpgradeSocketC32 = 0x1C,\r
+ ProcessorUpgradeSocketLGA1156 = 0x1D,\r
+ ProcessorUpgradeSocketLGA1567 = 0x1E,\r
+ ProcessorUpgradeSocketPGA988A = 0x1F,\r
+ ProcessorUpgradeSocketBGA1288 = 0x20,\r
+ ProcessorUpgradeSocketrPGA988B = 0x21,\r
+ ProcessorUpgradeSocketBGA1023 = 0x22,\r
+ ProcessorUpgradeSocketBGA1224 = 0x23,\r
+ ProcessorUpgradeSocketLGA1155 = 0x24, ///< SMBIOS spec 2.8.0 updated the name\r
+ ProcessorUpgradeSocketLGA1356 = 0x25,\r
+ ProcessorUpgradeSocketLGA2011 = 0x26,\r
+ ProcessorUpgradeSocketFS1 = 0x27,\r
+ ProcessorUpgradeSocketFS2 = 0x28,\r
+ ProcessorUpgradeSocketFM1 = 0x29,\r
+ ProcessorUpgradeSocketFM2 = 0x2A,\r
ProcessorUpgradeSocketLGA2011_3 = 0x2B,\r
ProcessorUpgradeSocketLGA1356_3 = 0x2C,\r
ProcessorUpgradeSocketLGA1150 = 0x2D,\r
/// Processor ID Field Description\r
///\r
typedef struct {\r
- UINT32 ProcessorSteppingId:4;\r
- UINT32 ProcessorModel: 4;\r
- UINT32 ProcessorFamily: 4;\r
- UINT32 ProcessorType: 2;\r
- UINT32 ProcessorReserved1: 2;\r
- UINT32 ProcessorXModel: 4;\r
- UINT32 ProcessorXFamily: 8;\r
- UINT32 ProcessorReserved2: 4;\r
+ UINT32 ProcessorSteppingId : 4;\r
+ UINT32 ProcessorModel : 4;\r
+ UINT32 ProcessorFamily : 4;\r
+ UINT32 ProcessorType : 2;\r
+ UINT32 ProcessorReserved1 : 2;\r
+ UINT32 ProcessorXModel : 4;\r
+ UINT32 ProcessorXFamily : 8;\r
+ UINT32 ProcessorReserved2 : 4;\r
} PROCESSOR_SIGNATURE;\r
\r
typedef struct {\r
- UINT32 ProcessorFpu :1;\r
- UINT32 ProcessorVme :1;\r
- UINT32 ProcessorDe :1;\r
- UINT32 ProcessorPse :1;\r
- UINT32 ProcessorTsc :1;\r
- UINT32 ProcessorMsr :1;\r
- UINT32 ProcessorPae :1;\r
- UINT32 ProcessorMce :1;\r
- UINT32 ProcessorCx8 :1;\r
- UINT32 ProcessorApic :1;\r
- UINT32 ProcessorReserved1 :1;\r
- UINT32 ProcessorSep :1;\r
- UINT32 ProcessorMtrr :1;\r
- UINT32 ProcessorPge :1;\r
- UINT32 ProcessorMca :1;\r
- UINT32 ProcessorCmov :1;\r
- UINT32 ProcessorPat :1;\r
- UINT32 ProcessorPse36 :1;\r
- UINT32 ProcessorPsn :1;\r
- UINT32 ProcessorClfsh :1;\r
- UINT32 ProcessorReserved2 :1;\r
- UINT32 ProcessorDs :1;\r
- UINT32 ProcessorAcpi :1;\r
- UINT32 ProcessorMmx :1;\r
- UINT32 ProcessorFxsr :1;\r
- UINT32 ProcessorSse :1;\r
- UINT32 ProcessorSse2 :1;\r
- UINT32 ProcessorSs :1;\r
- UINT32 ProcessorReserved3 :1;\r
- UINT32 ProcessorTm :1;\r
- UINT32 ProcessorReserved4 :2;\r
+ UINT32 ProcessorFpu : 1;\r
+ UINT32 ProcessorVme : 1;\r
+ UINT32 ProcessorDe : 1;\r
+ UINT32 ProcessorPse : 1;\r
+ UINT32 ProcessorTsc : 1;\r
+ UINT32 ProcessorMsr : 1;\r
+ UINT32 ProcessorPae : 1;\r
+ UINT32 ProcessorMce : 1;\r
+ UINT32 ProcessorCx8 : 1;\r
+ UINT32 ProcessorApic : 1;\r
+ UINT32 ProcessorReserved1 : 1;\r
+ UINT32 ProcessorSep : 1;\r
+ UINT32 ProcessorMtrr : 1;\r
+ UINT32 ProcessorPge : 1;\r
+ UINT32 ProcessorMca : 1;\r
+ UINT32 ProcessorCmov : 1;\r
+ UINT32 ProcessorPat : 1;\r
+ UINT32 ProcessorPse36 : 1;\r
+ UINT32 ProcessorPsn : 1;\r
+ UINT32 ProcessorClfsh : 1;\r
+ UINT32 ProcessorReserved2 : 1;\r
+ UINT32 ProcessorDs : 1;\r
+ UINT32 ProcessorAcpi : 1;\r
+ UINT32 ProcessorMmx : 1;\r
+ UINT32 ProcessorFxsr : 1;\r
+ UINT32 ProcessorSse : 1;\r
+ UINT32 ProcessorSse2 : 1;\r
+ UINT32 ProcessorSs : 1;\r
+ UINT32 ProcessorReserved3 : 1;\r
+ UINT32 ProcessorTm : 1;\r
+ UINT32 ProcessorReserved4 : 2;\r
} PROCESSOR_FEATURE_FLAGS;\r
\r
typedef struct {\r
- UINT16 ProcessorReserved1 :1;\r
- UINT16 ProcessorUnknown :1;\r
- UINT16 Processor64BitCapable :1;\r
- UINT16 ProcessorMultiCore :1;\r
- UINT16 ProcessorHardwareThread :1;\r
- UINT16 ProcessorExecuteProtection :1;\r
- UINT16 ProcessorEnhancedVirtualization :1;\r
- UINT16 ProcessorPowerPerformanceCtrl :1;\r
- UINT16 Processor128BitCapable :1;\r
- UINT16 ProcessorArm64SocId :1;\r
- UINT16 ProcessorReserved2 :6;\r
+ UINT16 ProcessorReserved1 : 1;\r
+ UINT16 ProcessorUnknown : 1;\r
+ UINT16 Processor64BitCapable : 1;\r
+ UINT16 ProcessorMultiCore : 1;\r
+ UINT16 ProcessorHardwareThread : 1;\r
+ UINT16 ProcessorExecuteProtection : 1;\r
+ UINT16 ProcessorEnhancedVirtualization : 1;\r
+ UINT16 ProcessorPowerPerformanceCtrl : 1;\r
+ UINT16 Processor128BitCapable : 1;\r
+ UINT16 ProcessorArm64SocId : 1;\r
+ UINT16 ProcessorReserved2 : 6;\r
} PROCESSOR_CHARACTERISTIC_FLAGS;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT8 CpuStatus :3; ///< Indicates the status of the processor.\r
- UINT8 Reserved1 :3; ///< Reserved for future use. Must be set to zero.\r
- UINT8 SocketPopulated :1; ///< Indicates if the processor socket is populated or not.\r
- UINT8 Reserved2 :1; ///< Reserved for future use. Must be set to zero.\r
+ UINT8 CpuStatus : 3; ///< Indicates the status of the processor.\r
+ UINT8 Reserved1 : 3; ///< Reserved for future use. Must be set to zero.\r
+ UINT8 SocketPopulated : 1; ///< Indicates if the processor socket is populated or not.\r
+ UINT8 Reserved2 : 1; ///< Reserved for future use. Must be set to zero.\r
} Bits;\r
- UINT8 Data;\r
+ UINT8 Data;\r
} PROCESSOR_STATUS_DATA;\r
\r
typedef struct {\r
- PROCESSOR_SIGNATURE Signature;\r
- PROCESSOR_FEATURE_FLAGS FeatureFlags;\r
+ PROCESSOR_SIGNATURE Signature;\r
+ PROCESSOR_FEATURE_FLAGS FeatureFlags;\r
} PROCESSOR_ID_DATA;\r
\r
///\r
/// to describe the main CPU, and a second structure to describe the 80487 co-processor.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Socket;\r
- UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.\r
- UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.\r
- SMBIOS_TABLE_STRING ProcessorManufacturer;\r
- PROCESSOR_ID_DATA ProcessorId;\r
- SMBIOS_TABLE_STRING ProcessorVersion;\r
- PROCESSOR_VOLTAGE Voltage;\r
- UINT16 ExternalClock;\r
- UINT16 MaxSpeed;\r
- UINT16 CurrentSpeed;\r
- UINT8 Status;\r
- UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.\r
- UINT16 L1CacheHandle;\r
- UINT16 L2CacheHandle;\r
- UINT16 L3CacheHandle;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING AssetTag;\r
- SMBIOS_TABLE_STRING PartNumber;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Socket;\r
+ UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.\r
+ UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.\r
+ SMBIOS_TABLE_STRING ProcessorManufacturer;\r
+ PROCESSOR_ID_DATA ProcessorId;\r
+ SMBIOS_TABLE_STRING ProcessorVersion;\r
+ PROCESSOR_VOLTAGE Voltage;\r
+ UINT16 ExternalClock;\r
+ UINT16 MaxSpeed;\r
+ UINT16 CurrentSpeed;\r
+ UINT8 Status;\r
+ UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.\r
+ UINT16 L1CacheHandle;\r
+ UINT16 L2CacheHandle;\r
+ UINT16 L3CacheHandle;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING AssetTag;\r
+ SMBIOS_TABLE_STRING PartNumber;\r
//\r
// Add for smbios 2.5\r
//\r
- UINT8 CoreCount;\r
- UINT8 EnabledCoreCount;\r
- UINT8 ThreadCount;\r
- UINT16 ProcessorCharacteristics;\r
+ UINT8 CoreCount;\r
+ UINT8 EnabledCoreCount;\r
+ UINT8 ThreadCount;\r
+ UINT16 ProcessorCharacteristics;\r
//\r
// Add for smbios 2.6\r
//\r
- UINT16 ProcessorFamily2;\r
+ UINT16 ProcessorFamily2;\r
//\r
// Add for smbios 3.0\r
//\r
- UINT16 CoreCount2;\r
- UINT16 EnabledCoreCount2;\r
- UINT16 ThreadCount2;\r
+ UINT16 CoreCount2;\r
+ UINT16 EnabledCoreCount2;\r
+ UINT16 ThreadCount2;\r
} SMBIOS_TABLE_TYPE4;\r
\r
///\r
/// Memory Controller Error Correcting Capability.\r
///\r
typedef struct {\r
- UINT8 Other :1;\r
- UINT8 Unknown :1;\r
- UINT8 None :1;\r
- UINT8 SingleBitErrorCorrect :1;\r
- UINT8 DoubleBitErrorCorrect :1;\r
- UINT8 ErrorScrubbing :1;\r
- UINT8 Reserved :2;\r
+ UINT8 Other : 1;\r
+ UINT8 Unknown : 1;\r
+ UINT8 None : 1;\r
+ UINT8 SingleBitErrorCorrect : 1;\r
+ UINT8 DoubleBitErrorCorrect : 1;\r
+ UINT8 ErrorScrubbing : 1;\r
+ UINT8 Reserved : 2;\r
} MEMORY_ERROR_CORRECT_CAPABILITY;\r
\r
///\r
/// Memory Controller Information - Memory Speeds.\r
///\r
typedef struct {\r
- UINT16 Other :1;\r
- UINT16 Unknown :1;\r
- UINT16 SeventyNs:1;\r
- UINT16 SixtyNs :1;\r
- UINT16 FiftyNs :1;\r
- UINT16 Reserved :11;\r
+ UINT16 Other : 1;\r
+ UINT16 Unknown : 1;\r
+ UINT16 SeventyNs : 1;\r
+ UINT16 SixtyNs : 1;\r
+ UINT16 FiftyNs : 1;\r
+ UINT16 Reserved : 11;\r
} MEMORY_SPEED_TYPE;\r
\r
///\r
/// to properly display the system's memory attributes.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.\r
- MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;\r
- UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.\r
- UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .\r
- UINT8 MaxMemoryModuleSize;\r
- MEMORY_SPEED_TYPE SupportSpeed;\r
- UINT16 SupportMemoryType;\r
- UINT8 MemoryModuleVoltage;\r
- UINT8 AssociatedMemorySlotNum;\r
- UINT16 MemoryModuleConfigHandles[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.\r
+ MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;\r
+ UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.\r
+ UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .\r
+ UINT8 MaxMemoryModuleSize;\r
+ MEMORY_SPEED_TYPE SupportSpeed;\r
+ UINT16 SupportMemoryType;\r
+ UINT8 MemoryModuleVoltage;\r
+ UINT8 AssociatedMemorySlotNum;\r
+ UINT16 MemoryModuleConfigHandles[1];\r
} SMBIOS_TABLE_TYPE5;\r
\r
///\r
/// Memory Module Information - Memory Types\r
///\r
typedef struct {\r
- UINT16 Other :1;\r
- UINT16 Unknown :1;\r
- UINT16 Standard :1;\r
- UINT16 FastPageMode:1;\r
- UINT16 Edo :1;\r
- UINT16 Parity :1;\r
- UINT16 Ecc :1;\r
- UINT16 Simm :1;\r
- UINT16 Dimm :1;\r
- UINT16 BurstEdo :1;\r
- UINT16 Sdram :1;\r
- UINT16 Reserved :5;\r
+ UINT16 Other : 1;\r
+ UINT16 Unknown : 1;\r
+ UINT16 Standard : 1;\r
+ UINT16 FastPageMode : 1;\r
+ UINT16 Edo : 1;\r
+ UINT16 Parity : 1;\r
+ UINT16 Ecc : 1;\r
+ UINT16 Simm : 1;\r
+ UINT16 Dimm : 1;\r
+ UINT16 BurstEdo : 1;\r
+ UINT16 Sdram : 1;\r
+ UINT16 Reserved : 5;\r
} MEMORY_CURRENT_TYPE;\r
\r
///\r
/// Memory Module Information - Memory Size.\r
///\r
typedef struct {\r
- UINT8 InstalledOrEnabledSize :7; ///< Size (n), where 2**n is the size in MB.\r
- UINT8 SingleOrDoubleBank :1;\r
+ UINT8 InstalledOrEnabledSize : 7; ///< Size (n), where 2**n is the size in MB.\r
+ UINT8 SingleOrDoubleBank : 1;\r
} MEMORY_INSTALLED_ENABLED_SIZE;\r
\r
///\r
/// and Memory Device (Type 17) structures should be used instead.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING SocketDesignation;\r
- UINT8 BankConnections;\r
- UINT8 CurrentSpeed;\r
- MEMORY_CURRENT_TYPE CurrentMemoryType;\r
- MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;\r
- MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;\r
- UINT8 ErrorStatus;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING SocketDesignation;\r
+ UINT8 BankConnections;\r
+ UINT8 CurrentSpeed;\r
+ MEMORY_CURRENT_TYPE CurrentMemoryType;\r
+ MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;\r
+ MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;\r
+ UINT8 ErrorStatus;\r
} SMBIOS_TABLE_TYPE6;\r
\r
///\r
/// Cache Information - SRAM Type.\r
///\r
typedef struct {\r
- UINT16 Other :1;\r
- UINT16 Unknown :1;\r
- UINT16 NonBurst :1;\r
- UINT16 Burst :1;\r
- UINT16 PipelineBurst :1;\r
- UINT16 Synchronous :1;\r
- UINT16 Asynchronous :1;\r
- UINT16 Reserved :9;\r
+ UINT16 Other : 1;\r
+ UINT16 Unknown : 1;\r
+ UINT16 NonBurst : 1;\r
+ UINT16 Burst : 1;\r
+ UINT16 PipelineBurst : 1;\r
+ UINT16 Synchronous : 1;\r
+ UINT16 Asynchronous : 1;\r
+ UINT16 Reserved : 9;\r
} CACHE_SRAM_TYPE_DATA;\r
\r
///\r
/// in one or two ways, depending on the SMBIOS version.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING SocketDesignation;\r
- UINT16 CacheConfiguration;\r
- UINT16 MaximumCacheSize;\r
- UINT16 InstalledSize;\r
- CACHE_SRAM_TYPE_DATA SupportedSRAMType;\r
- CACHE_SRAM_TYPE_DATA CurrentSRAMType;\r
- UINT8 CacheSpeed;\r
- UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r
- UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.\r
- UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING SocketDesignation;\r
+ UINT16 CacheConfiguration;\r
+ UINT16 MaximumCacheSize;\r
+ UINT16 InstalledSize;\r
+ CACHE_SRAM_TYPE_DATA SupportedSRAMType;\r
+ CACHE_SRAM_TYPE_DATA CurrentSRAMType;\r
+ UINT8 CacheSpeed;\r
+ UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r
+ UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.\r
+ UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r
//\r
// Add for smbios 3.1.0\r
//\r
- UINT32 MaximumCacheSize2;\r
- UINT32 InstalledSize2;\r
+ UINT32 MaximumCacheSize2;\r
+ UINT32 InstalledSize2;\r
} SMBIOS_TABLE_TYPE7;\r
\r
///\r
/// Port Connector Information - Connector Types.\r
///\r
typedef enum {\r
- PortConnectorTypeNone = 0x00,\r
- PortConnectorTypeCentronics = 0x01,\r
- PortConnectorTypeMiniCentronics = 0x02,\r
- PortConnectorTypeProprietary = 0x03,\r
- PortConnectorTypeDB25Male = 0x04,\r
- PortConnectorTypeDB25Female = 0x05,\r
- PortConnectorTypeDB15Male = 0x06,\r
- PortConnectorTypeDB15Female = 0x07,\r
- PortConnectorTypeDB9Male = 0x08,\r
- PortConnectorTypeDB9Female = 0x09,\r
- PortConnectorTypeRJ11 = 0x0A,\r
- PortConnectorTypeRJ45 = 0x0B,\r
- PortConnectorType50PinMiniScsi = 0x0C,\r
- PortConnectorTypeMiniDin = 0x0D,\r
- PortConnectorTypeMicroDin = 0x0E,\r
- PortConnectorTypePS2 = 0x0F,\r
- PortConnectorTypeInfrared = 0x10,\r
- PortConnectorTypeHpHil = 0x11,\r
- PortConnectorTypeUsb = 0x12,\r
- PortConnectorTypeSsaScsi = 0x13,\r
- PortConnectorTypeCircularDin8Male = 0x14,\r
- PortConnectorTypeCircularDin8Female = 0x15,\r
- PortConnectorTypeOnboardIde = 0x16,\r
- PortConnectorTypeOnboardFloppy = 0x17,\r
- PortConnectorType9PinDualInline = 0x18,\r
- PortConnectorType25PinDualInline = 0x19,\r
- PortConnectorType50PinDualInline = 0x1A,\r
- PortConnectorType68PinDualInline = 0x1B,\r
- PortConnectorTypeOnboardSoundInput = 0x1C,\r
- PortConnectorTypeMiniCentronicsType14 = 0x1D,\r
- PortConnectorTypeMiniCentronicsType26 = 0x1E,\r
- PortConnectorTypeHeadPhoneMiniJack = 0x1F,\r
- PortConnectorTypeBNC = 0x20,\r
- PortConnectorType1394 = 0x21,\r
- PortConnectorTypeSasSata = 0x22,\r
- PortConnectorTypeUsbTypeC = 0x23,\r
- PortConnectorTypePC98 = 0xA0,\r
- PortConnectorTypePC98Hireso = 0xA1,\r
- PortConnectorTypePCH98 = 0xA2,\r
- PortConnectorTypePC98Note = 0xA3,\r
- PortConnectorTypePC98Full = 0xA4,\r
- PortConnectorTypeOther = 0xFF\r
+ PortConnectorTypeNone = 0x00,\r
+ PortConnectorTypeCentronics = 0x01,\r
+ PortConnectorTypeMiniCentronics = 0x02,\r
+ PortConnectorTypeProprietary = 0x03,\r
+ PortConnectorTypeDB25Male = 0x04,\r
+ PortConnectorTypeDB25Female = 0x05,\r
+ PortConnectorTypeDB15Male = 0x06,\r
+ PortConnectorTypeDB15Female = 0x07,\r
+ PortConnectorTypeDB9Male = 0x08,\r
+ PortConnectorTypeDB9Female = 0x09,\r
+ PortConnectorTypeRJ11 = 0x0A,\r
+ PortConnectorTypeRJ45 = 0x0B,\r
+ PortConnectorType50PinMiniScsi = 0x0C,\r
+ PortConnectorTypeMiniDin = 0x0D,\r
+ PortConnectorTypeMicroDin = 0x0E,\r
+ PortConnectorTypePS2 = 0x0F,\r
+ PortConnectorTypeInfrared = 0x10,\r
+ PortConnectorTypeHpHil = 0x11,\r
+ PortConnectorTypeUsb = 0x12,\r
+ PortConnectorTypeSsaScsi = 0x13,\r
+ PortConnectorTypeCircularDin8Male = 0x14,\r
+ PortConnectorTypeCircularDin8Female = 0x15,\r
+ PortConnectorTypeOnboardIde = 0x16,\r
+ PortConnectorTypeOnboardFloppy = 0x17,\r
+ PortConnectorType9PinDualInline = 0x18,\r
+ PortConnectorType25PinDualInline = 0x19,\r
+ PortConnectorType50PinDualInline = 0x1A,\r
+ PortConnectorType68PinDualInline = 0x1B,\r
+ PortConnectorTypeOnboardSoundInput = 0x1C,\r
+ PortConnectorTypeMiniCentronicsType14 = 0x1D,\r
+ PortConnectorTypeMiniCentronicsType26 = 0x1E,\r
+ PortConnectorTypeHeadPhoneMiniJack = 0x1F,\r
+ PortConnectorTypeBNC = 0x20,\r
+ PortConnectorType1394 = 0x21,\r
+ PortConnectorTypeSasSata = 0x22,\r
+ PortConnectorTypeUsbTypeC = 0x23,\r
+ PortConnectorTypePC98 = 0xA0,\r
+ PortConnectorTypePC98Hireso = 0xA1,\r
+ PortConnectorTypePCH98 = 0xA2,\r
+ PortConnectorTypePC98Note = 0xA3,\r
+ PortConnectorTypePC98Full = 0xA4,\r
+ PortConnectorTypeOther = 0xFF\r
} MISC_PORT_CONNECTOR_TYPE;\r
\r
///\r
/// Port Connector Information - Port Types\r
///\r
typedef enum {\r
- PortTypeNone = 0x00,\r
- PortTypeParallelXtAtCompatible = 0x01,\r
- PortTypeParallelPortPs2 = 0x02,\r
- PortTypeParallelPortEcp = 0x03,\r
- PortTypeParallelPortEpp = 0x04,\r
- PortTypeParallelPortEcpEpp = 0x05,\r
- PortTypeSerialXtAtCompatible = 0x06,\r
- PortTypeSerial16450Compatible = 0x07,\r
- PortTypeSerial16550Compatible = 0x08,\r
- PortTypeSerial16550ACompatible = 0x09,\r
- PortTypeScsi = 0x0A,\r
- PortTypeMidi = 0x0B,\r
- PortTypeJoyStick = 0x0C,\r
- PortTypeKeyboard = 0x0D,\r
- PortTypeMouse = 0x0E,\r
- PortTypeSsaScsi = 0x0F,\r
- PortTypeUsb = 0x10,\r
- PortTypeFireWire = 0x11,\r
- PortTypePcmciaTypeI = 0x12,\r
- PortTypePcmciaTypeII = 0x13,\r
- PortTypePcmciaTypeIII = 0x14,\r
- PortTypeCardBus = 0x15,\r
- PortTypeAccessBusPort = 0x16,\r
- PortTypeScsiII = 0x17,\r
- PortTypeScsiWide = 0x18,\r
- PortTypePC98 = 0x19,\r
- PortTypePC98Hireso = 0x1A,\r
- PortTypePCH98 = 0x1B,\r
- PortTypeVideoPort = 0x1C,\r
- PortTypeAudioPort = 0x1D,\r
- PortTypeModemPort = 0x1E,\r
- PortTypeNetworkPort = 0x1F,\r
- PortTypeSata = 0x20,\r
- PortTypeSas = 0x21,\r
- PortTypeMfdp = 0x22, ///< Multi-Function Display Port\r
- PortTypeThunderbolt = 0x23,\r
- PortType8251Compatible = 0xA0,\r
- PortType8251FifoCompatible = 0xA1,\r
- PortTypeOther = 0xFF\r
+ PortTypeNone = 0x00,\r
+ PortTypeParallelXtAtCompatible = 0x01,\r
+ PortTypeParallelPortPs2 = 0x02,\r
+ PortTypeParallelPortEcp = 0x03,\r
+ PortTypeParallelPortEpp = 0x04,\r
+ PortTypeParallelPortEcpEpp = 0x05,\r
+ PortTypeSerialXtAtCompatible = 0x06,\r
+ PortTypeSerial16450Compatible = 0x07,\r
+ PortTypeSerial16550Compatible = 0x08,\r
+ PortTypeSerial16550ACompatible = 0x09,\r
+ PortTypeScsi = 0x0A,\r
+ PortTypeMidi = 0x0B,\r
+ PortTypeJoyStick = 0x0C,\r
+ PortTypeKeyboard = 0x0D,\r
+ PortTypeMouse = 0x0E,\r
+ PortTypeSsaScsi = 0x0F,\r
+ PortTypeUsb = 0x10,\r
+ PortTypeFireWire = 0x11,\r
+ PortTypePcmciaTypeI = 0x12,\r
+ PortTypePcmciaTypeII = 0x13,\r
+ PortTypePcmciaTypeIII = 0x14,\r
+ PortTypeCardBus = 0x15,\r
+ PortTypeAccessBusPort = 0x16,\r
+ PortTypeScsiII = 0x17,\r
+ PortTypeScsiWide = 0x18,\r
+ PortTypePC98 = 0x19,\r
+ PortTypePC98Hireso = 0x1A,\r
+ PortTypePCH98 = 0x1B,\r
+ PortTypeVideoPort = 0x1C,\r
+ PortTypeAudioPort = 0x1D,\r
+ PortTypeModemPort = 0x1E,\r
+ PortTypeNetworkPort = 0x1F,\r
+ PortTypeSata = 0x20,\r
+ PortTypeSas = 0x21,\r
+ PortTypeMfdp = 0x22, ///< Multi-Function Display Port\r
+ PortTypeThunderbolt = 0x23,\r
+ PortType8251Compatible = 0xA0,\r
+ PortType8251FifoCompatible = 0xA1,\r
+ PortTypeOther = 0xFF\r
} MISC_PORT_TYPE;\r
\r
///\r
/// are provided. One structure is present for each port provided by the system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING InternalReferenceDesignator;\r
- UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
- SMBIOS_TABLE_STRING ExternalReferenceDesignator;\r
- UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
- UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING InternalReferenceDesignator;\r
+ UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
+ SMBIOS_TABLE_STRING ExternalReferenceDesignator;\r
+ UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r
+ UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.\r
} SMBIOS_TABLE_TYPE8;\r
\r
///\r
/// System Slots - Slot Type\r
///\r
typedef enum {\r
- SlotTypeOther = 0x01,\r
- SlotTypeUnknown = 0x02,\r
- SlotTypeIsa = 0x03,\r
- SlotTypeMca = 0x04,\r
- SlotTypeEisa = 0x05,\r
- SlotTypePci = 0x06,\r
- SlotTypePcmcia = 0x07,\r
- SlotTypeVlVesa = 0x08,\r
- SlotTypeProprietary = 0x09,\r
- SlotTypeProcessorCardSlot = 0x0A,\r
- SlotTypeProprietaryMemoryCardSlot = 0x0B,\r
- SlotTypeIORiserCardSlot = 0x0C,\r
- SlotTypeNuBus = 0x0D,\r
- SlotTypePci66MhzCapable = 0x0E,\r
- SlotTypeAgp = 0x0F,\r
- SlotTypeApg2X = 0x10,\r
- SlotTypeAgp4X = 0x11,\r
- SlotTypePciX = 0x12,\r
- SlotTypeAgp8X = 0x13,\r
- SlotTypeM2Socket1_DP = 0x14,\r
- SlotTypeM2Socket1_SD = 0x15,\r
- SlotTypeM2Socket2 = 0x16,\r
- SlotTypeM2Socket3 = 0x17,\r
- SlotTypeMxmTypeI = 0x18,\r
- SlotTypeMxmTypeII = 0x19,\r
- SlotTypeMxmTypeIIIStandard = 0x1A,\r
- SlotTypeMxmTypeIIIHe = 0x1B,\r
- SlotTypeMxmTypeIV = 0x1C,\r
- SlotTypeMxm30TypeA = 0x1D,\r
- SlotTypeMxm30TypeB = 0x1E,\r
- SlotTypePciExpressGen2Sff_8639 = 0x1F,\r
- SlotTypePciExpressGen3Sff_8639 = 0x20,\r
- SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.\r
+ SlotTypeOther = 0x01,\r
+ SlotTypeUnknown = 0x02,\r
+ SlotTypeIsa = 0x03,\r
+ SlotTypeMca = 0x04,\r
+ SlotTypeEisa = 0x05,\r
+ SlotTypePci = 0x06,\r
+ SlotTypePcmcia = 0x07,\r
+ SlotTypeVlVesa = 0x08,\r
+ SlotTypeProprietary = 0x09,\r
+ SlotTypeProcessorCardSlot = 0x0A,\r
+ SlotTypeProprietaryMemoryCardSlot = 0x0B,\r
+ SlotTypeIORiserCardSlot = 0x0C,\r
+ SlotTypeNuBus = 0x0D,\r
+ SlotTypePci66MhzCapable = 0x0E,\r
+ SlotTypeAgp = 0x0F,\r
+ SlotTypeApg2X = 0x10,\r
+ SlotTypeAgp4X = 0x11,\r
+ SlotTypePciX = 0x12,\r
+ SlotTypeAgp8X = 0x13,\r
+ SlotTypeM2Socket1_DP = 0x14,\r
+ SlotTypeM2Socket1_SD = 0x15,\r
+ SlotTypeM2Socket2 = 0x16,\r
+ SlotTypeM2Socket3 = 0x17,\r
+ SlotTypeMxmTypeI = 0x18,\r
+ SlotTypeMxmTypeII = 0x19,\r
+ SlotTypeMxmTypeIIIStandard = 0x1A,\r
+ SlotTypeMxmTypeIIIHe = 0x1B,\r
+ SlotTypeMxmTypeIV = 0x1C,\r
+ SlotTypeMxm30TypeA = 0x1D,\r
+ SlotTypeMxm30TypeB = 0x1E,\r
+ SlotTypePciExpressGen2Sff_8639 = 0x1F,\r
+ SlotTypePciExpressGen3Sff_8639 = 0x20,\r
+ SlotTypePciExpressMini52pinWithBSKO = 0x21, ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.\r
SlotTypePciExpressMini52pinWithoutBSKO = 0x22, ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.\r
- SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.\r
- SlotTypeCXLFlexbus10 = 0x30,\r
- SlotTypePC98C20 = 0xA0,\r
- SlotTypePC98C24 = 0xA1,\r
- SlotTypePC98E = 0xA2,\r
- SlotTypePC98LocalBus = 0xA3,\r
- SlotTypePC98Card = 0xA4,\r
- SlotTypePciExpress = 0xA5,\r
- SlotTypePciExpressX1 = 0xA6,\r
- SlotTypePciExpressX2 = 0xA7,\r
- SlotTypePciExpressX4 = 0xA8,\r
- SlotTypePciExpressX8 = 0xA9,\r
- SlotTypePciExpressX16 = 0xAA,\r
- SlotTypePciExpressGen2 = 0xAB,\r
- SlotTypePciExpressGen2X1 = 0xAC,\r
- SlotTypePciExpressGen2X2 = 0xAD,\r
- SlotTypePciExpressGen2X4 = 0xAE,\r
- SlotTypePciExpressGen2X8 = 0xAF,\r
- SlotTypePciExpressGen2X16 = 0xB0,\r
- SlotTypePciExpressGen3 = 0xB1,\r
- SlotTypePciExpressGen3X1 = 0xB2,\r
- SlotTypePciExpressGen3X2 = 0xB3,\r
- SlotTypePciExpressGen3X4 = 0xB4,\r
- SlotTypePciExpressGen3X8 = 0xB5,\r
- SlotTypePciExpressGen3X16 = 0xB6,\r
- SlotTypePciExpressGen4 = 0xB8,\r
- SlotTypePciExpressGen4X1 = 0xB9,\r
- SlotTypePciExpressGen4X2 = 0xBA,\r
- SlotTypePciExpressGen4X4 = 0xBB,\r
- SlotTypePciExpressGen4X8 = 0xBC,\r
- SlotTypePciExpressGen4X16 = 0xBD\r
+ SlotTypePciExpressMini76pin = 0x23, ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.\r
+ SlotTypeCXLFlexbus10 = 0x30,\r
+ SlotTypePC98C20 = 0xA0,\r
+ SlotTypePC98C24 = 0xA1,\r
+ SlotTypePC98E = 0xA2,\r
+ SlotTypePC98LocalBus = 0xA3,\r
+ SlotTypePC98Card = 0xA4,\r
+ SlotTypePciExpress = 0xA5,\r
+ SlotTypePciExpressX1 = 0xA6,\r
+ SlotTypePciExpressX2 = 0xA7,\r
+ SlotTypePciExpressX4 = 0xA8,\r
+ SlotTypePciExpressX8 = 0xA9,\r
+ SlotTypePciExpressX16 = 0xAA,\r
+ SlotTypePciExpressGen2 = 0xAB,\r
+ SlotTypePciExpressGen2X1 = 0xAC,\r
+ SlotTypePciExpressGen2X2 = 0xAD,\r
+ SlotTypePciExpressGen2X4 = 0xAE,\r
+ SlotTypePciExpressGen2X8 = 0xAF,\r
+ SlotTypePciExpressGen2X16 = 0xB0,\r
+ SlotTypePciExpressGen3 = 0xB1,\r
+ SlotTypePciExpressGen3X1 = 0xB2,\r
+ SlotTypePciExpressGen3X2 = 0xB3,\r
+ SlotTypePciExpressGen3X4 = 0xB4,\r
+ SlotTypePciExpressGen3X8 = 0xB5,\r
+ SlotTypePciExpressGen3X16 = 0xB6,\r
+ SlotTypePciExpressGen4 = 0xB8,\r
+ SlotTypePciExpressGen4X1 = 0xB9,\r
+ SlotTypePciExpressGen4X2 = 0xBA,\r
+ SlotTypePciExpressGen4X4 = 0xBB,\r
+ SlotTypePciExpressGen4X8 = 0xBC,\r
+ SlotTypePciExpressGen4X16 = 0xBD\r
} MISC_SLOT_TYPE;\r
\r
///\r
/// System Slots - Slot Data Bus Width.\r
///\r
typedef enum {\r
- SlotDataBusWidthOther = 0x01,\r
- SlotDataBusWidthUnknown = 0x02,\r
- SlotDataBusWidth8Bit = 0x03,\r
- SlotDataBusWidth16Bit = 0x04,\r
- SlotDataBusWidth32Bit = 0x05,\r
- SlotDataBusWidth64Bit = 0x06,\r
- SlotDataBusWidth128Bit = 0x07,\r
- SlotDataBusWidth1X = 0x08, ///< Or X1\r
- SlotDataBusWidth2X = 0x09, ///< Or X2\r
- SlotDataBusWidth4X = 0x0A, ///< Or X4\r
- SlotDataBusWidth8X = 0x0B, ///< Or X8\r
- SlotDataBusWidth12X = 0x0C, ///< Or X12\r
- SlotDataBusWidth16X = 0x0D, ///< Or X16\r
- SlotDataBusWidth32X = 0x0E ///< Or X32\r
+ SlotDataBusWidthOther = 0x01,\r
+ SlotDataBusWidthUnknown = 0x02,\r
+ SlotDataBusWidth8Bit = 0x03,\r
+ SlotDataBusWidth16Bit = 0x04,\r
+ SlotDataBusWidth32Bit = 0x05,\r
+ SlotDataBusWidth64Bit = 0x06,\r
+ SlotDataBusWidth128Bit = 0x07,\r
+ SlotDataBusWidth1X = 0x08, ///< Or X1\r
+ SlotDataBusWidth2X = 0x09, ///< Or X2\r
+ SlotDataBusWidth4X = 0x0A, ///< Or X4\r
+ SlotDataBusWidth8X = 0x0B, ///< Or X8\r
+ SlotDataBusWidth12X = 0x0C, ///< Or X12\r
+ SlotDataBusWidth16X = 0x0D, ///< Or X16\r
+ SlotDataBusWidth32X = 0x0E ///< Or X32\r
} MISC_SLOT_DATA_BUS_WIDTH;\r
\r
///\r
/// System Slots - Current Usage.\r
///\r
typedef enum {\r
- SlotUsageOther = 0x01,\r
- SlotUsageUnknown = 0x02,\r
- SlotUsageAvailable = 0x03,\r
- SlotUsageInUse = 0x04,\r
- SlotUsageUnavailable = 0x05\r
+ SlotUsageOther = 0x01,\r
+ SlotUsageUnknown = 0x02,\r
+ SlotUsageAvailable = 0x03,\r
+ SlotUsageInUse = 0x04,\r
+ SlotUsageUnavailable = 0x05\r
} MISC_SLOT_USAGE;\r
\r
///\r
/// System Slots - Slot Characteristics 1.\r
///\r
typedef struct {\r
- UINT8 CharacteristicsUnknown :1;\r
- UINT8 Provides50Volts :1;\r
- UINT8 Provides33Volts :1;\r
- UINT8 SharedSlot :1;\r
- UINT8 PcCard16Supported :1;\r
- UINT8 CardBusSupported :1;\r
- UINT8 ZoomVideoSupported :1;\r
- UINT8 ModemRingResumeSupported:1;\r
+ UINT8 CharacteristicsUnknown : 1;\r
+ UINT8 Provides50Volts : 1;\r
+ UINT8 Provides33Volts : 1;\r
+ UINT8 SharedSlot : 1;\r
+ UINT8 PcCard16Supported : 1;\r
+ UINT8 CardBusSupported : 1;\r
+ UINT8 ZoomVideoSupported : 1;\r
+ UINT8 ModemRingResumeSupported : 1;\r
} MISC_SLOT_CHARACTERISTICS1;\r
///\r
/// System Slots - Slot Characteristics 2.\r
///\r
typedef struct {\r
- UINT8 PmeSignalSupported :1;\r
- UINT8 HotPlugDevicesSupported :1;\r
- UINT8 SmbusSignalSupported :1;\r
- UINT8 BifurcationSupported :1;\r
- UINT8 AsyncSurpriseRemoval :1;\r
- UINT8 FlexbusSlotCxl10Capable :1;\r
- UINT8 FlexbusSlotCxl20Capable :1;\r
- UINT8 Reserved :1; ///< Set to 0.\r
+ UINT8 PmeSignalSupported : 1;\r
+ UINT8 HotPlugDevicesSupported : 1;\r
+ UINT8 SmbusSignalSupported : 1;\r
+ UINT8 BifurcationSupported : 1;\r
+ UINT8 AsyncSurpriseRemoval : 1;\r
+ UINT8 FlexbusSlotCxl10Capable : 1;\r
+ UINT8 FlexbusSlotCxl20Capable : 1;\r
+ UINT8 Reserved : 1; ///< Set to 0.\r
} MISC_SLOT_CHARACTERISTICS2;\r
\r
///\r
/// System Slots - Peer Segment/Bus/Device/Function/Width Groups\r
///\r
typedef struct {\r
- UINT16 SegmentGroupNum;\r
- UINT8 BusNum;\r
- UINT8 DevFuncNum;\r
- UINT8 DataBusWidth;\r
+ UINT16 SegmentGroupNum;\r
+ UINT8 BusNum;\r
+ UINT8 DevFuncNum;\r
+ UINT8 DataBusWidth;\r
} MISC_SLOT_PEER_GROUP;\r
\r
///\r
///\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING SlotDesignation;\r
- UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.\r
- UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.\r
- UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.\r
- UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.\r
- UINT16 SlotID;\r
- MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;\r
- MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING SlotDesignation;\r
+ UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.\r
+ UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.\r
+ UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.\r
+ UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.\r
+ UINT16 SlotID;\r
+ MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;\r
+ MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;\r
//\r
// Add for smbios 2.6\r
//\r
- UINT16 SegmentGroupNum;\r
- UINT8 BusNum;\r
- UINT8 DevFuncNum;\r
+ UINT16 SegmentGroupNum;\r
+ UINT8 BusNum;\r
+ UINT8 DevFuncNum;\r
//\r
// Add for smbios 3.2\r
//\r
- UINT8 DataBusWidth;\r
- UINT8 PeerGroupingCount;\r
- MISC_SLOT_PEER_GROUP PeerGroups[1];\r
+ UINT8 DataBusWidth;\r
+ UINT8 PeerGroupingCount;\r
+ MISC_SLOT_PEER_GROUP PeerGroups[1];\r
//\r
// Add for smbios 3.4\r
//\r
- UINT8 SlotInformation;\r
- UINT8 SlotPhysicalWidth;\r
- UINT16 SlotPitch;\r
+ UINT8 SlotInformation;\r
+ UINT8 SlotPhysicalWidth;\r
+ UINT16 SlotPitch;\r
} SMBIOS_TABLE_TYPE9;\r
\r
///\r
/// Device Item Entry\r
///\r
typedef struct {\r
- UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.\r
+ UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.\r
///< Bit 7 - 1 : device enabled, 0 : device disabled.\r
- SMBIOS_TABLE_STRING DescriptionString;\r
+ SMBIOS_TABLE_STRING DescriptionString;\r
} DEVICE_STRUCT;\r
\r
///\r
/// has some level of control over the enabling of the associated device for use by the system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- DEVICE_STRUCT Device[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ DEVICE_STRUCT Device[1];\r
} SMBIOS_TABLE_TYPE10;\r
\r
///\r
/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 StringCount;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 StringCount;\r
} SMBIOS_TABLE_TYPE11;\r
\r
///\r
/// This structure contains information required to configure the base board's Jumpers and Switches.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 StringCount;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 StringCount;\r
} SMBIOS_TABLE_TYPE12;\r
\r
-\r
///\r
/// BIOS Language Information (Type 13).\r
///\r
/// The information in this structure defines the installable language attributes of the BIOS.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 InstallableLanguages;\r
- UINT8 Flags;\r
- UINT8 Reserved[15];\r
- SMBIOS_TABLE_STRING CurrentLanguages;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 InstallableLanguages;\r
+ UINT8 Flags;\r
+ UINT8 Reserved[15];\r
+ SMBIOS_TABLE_STRING CurrentLanguages;\r
} SMBIOS_TABLE_TYPE13;\r
\r
///\r
/// Group Item Entry\r
///\r
typedef struct {\r
- UINT8 ItemType;\r
- UINT16 ItemHandle;\r
+ UINT8 ItemType;\r
+ UINT16 ItemHandle;\r
} GROUP_STRUCT;\r
\r
///\r
/// within the system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING GroupName;\r
- GROUP_STRUCT Group[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING GroupName;\r
+ GROUP_STRUCT Group[1];\r
} SMBIOS_TABLE_TYPE14;\r
\r
///\r
/// System Event Log - Event Log Types.\r
///\r
typedef enum {\r
- EventLogTypeReserved = 0x00,\r
- EventLogTypeSingleBitECC = 0x01,\r
- EventLogTypeMultiBitECC = 0x02,\r
- EventLogTypeParityMemErr = 0x03,\r
- EventLogTypeBusTimeOut = 0x04,\r
- EventLogTypeIOChannelCheck = 0x05,\r
- EventLogTypeSoftwareNMI = 0x06,\r
- EventLogTypePOSTMemResize = 0x07,\r
- EventLogTypePOSTErr = 0x08,\r
- EventLogTypePCIParityErr = 0x09,\r
- EventLogTypePCISystemErr = 0x0A,\r
- EventLogTypeCPUFailure = 0x0B,\r
- EventLogTypeEISATimeOut = 0x0C,\r
- EventLogTypeMemLogDisabled = 0x0D,\r
- EventLogTypeLoggingDisabled = 0x0E,\r
- EventLogTypeSysLimitExce = 0x10,\r
- EventLogTypeAsyncHWTimer = 0x11,\r
- EventLogTypeSysConfigInfo = 0x12,\r
- EventLogTypeHDInfo = 0x13,\r
- EventLogTypeSysReconfig = 0x14,\r
- EventLogTypeUncorrectCPUErr = 0x15,\r
- EventLogTypeAreaResetAndClr = 0x16,\r
- EventLogTypeSystemBoot = 0x17,\r
- EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F\r
- EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE\r
- EventLogTypeEndOfLog = 0xFF\r
+ EventLogTypeReserved = 0x00,\r
+ EventLogTypeSingleBitECC = 0x01,\r
+ EventLogTypeMultiBitECC = 0x02,\r
+ EventLogTypeParityMemErr = 0x03,\r
+ EventLogTypeBusTimeOut = 0x04,\r
+ EventLogTypeIOChannelCheck = 0x05,\r
+ EventLogTypeSoftwareNMI = 0x06,\r
+ EventLogTypePOSTMemResize = 0x07,\r
+ EventLogTypePOSTErr = 0x08,\r
+ EventLogTypePCIParityErr = 0x09,\r
+ EventLogTypePCISystemErr = 0x0A,\r
+ EventLogTypeCPUFailure = 0x0B,\r
+ EventLogTypeEISATimeOut = 0x0C,\r
+ EventLogTypeMemLogDisabled = 0x0D,\r
+ EventLogTypeLoggingDisabled = 0x0E,\r
+ EventLogTypeSysLimitExce = 0x10,\r
+ EventLogTypeAsyncHWTimer = 0x11,\r
+ EventLogTypeSysConfigInfo = 0x12,\r
+ EventLogTypeHDInfo = 0x13,\r
+ EventLogTypeSysReconfig = 0x14,\r
+ EventLogTypeUncorrectCPUErr = 0x15,\r
+ EventLogTypeAreaResetAndClr = 0x16,\r
+ EventLogTypeSystemBoot = 0x17,\r
+ EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F\r
+ EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE\r
+ EventLogTypeEndOfLog = 0xFF\r
} EVENT_LOG_TYPE_DATA;\r
\r
///\r
/// System Event Log - Variable Data Format Types.\r
///\r
typedef enum {\r
- EventLogVariableNone = 0x00,\r
- EventLogVariableHandle = 0x01,\r
- EventLogVariableMutilEvent = 0x02,\r
- EventLogVariableMutilEventHandle = 0x03,\r
- EventLogVariablePOSTResultBitmap = 0x04,\r
- EventLogVariableSysManagementType = 0x05,\r
- EventLogVariableMutliEventSysManagmentType = 0x06,\r
- EventLogVariableUnused = 0x07,\r
- EventLogVariableOEMAssigned = 0x80\r
+ EventLogVariableNone = 0x00,\r
+ EventLogVariableHandle = 0x01,\r
+ EventLogVariableMutilEvent = 0x02,\r
+ EventLogVariableMutilEventHandle = 0x03,\r
+ EventLogVariablePOSTResultBitmap = 0x04,\r
+ EventLogVariableSysManagementType = 0x05,\r
+ EventLogVariableMutliEventSysManagmentType = 0x06,\r
+ EventLogVariableUnused = 0x07,\r
+ EventLogVariableOEMAssigned = 0x80\r
} EVENT_LOG_VARIABLE_DATA;\r
\r
///\r
/// Event Log Type Descriptors\r
///\r
typedef struct {\r
- UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.\r
- UINT8 DataFormatType;\r
+ UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.\r
+ UINT8 DataFormatType;\r
} EVENT_LOG_TYPE;\r
\r
///\r
/// record, followed by one or more variable-length log records.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT16 LogAreaLength;\r
- UINT16 LogHeaderStartOffset;\r
- UINT16 LogDataStartOffset;\r
- UINT8 AccessMethod;\r
- UINT8 LogStatus;\r
- UINT32 LogChangeToken;\r
- UINT32 AccessMethodAddress;\r
- UINT8 LogHeaderFormat;\r
- UINT8 NumberOfSupportedLogTypeDescriptors;\r
- UINT8 LengthOfLogTypeDescriptor;\r
- EVENT_LOG_TYPE EventLogTypeDescriptors[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT16 LogAreaLength;\r
+ UINT16 LogHeaderStartOffset;\r
+ UINT16 LogDataStartOffset;\r
+ UINT8 AccessMethod;\r
+ UINT8 LogStatus;\r
+ UINT32 LogChangeToken;\r
+ UINT32 AccessMethodAddress;\r
+ UINT8 LogHeaderFormat;\r
+ UINT8 NumberOfSupportedLogTypeDescriptors;\r
+ UINT8 LengthOfLogTypeDescriptor;\r
+ EVENT_LOG_TYPE EventLogTypeDescriptors[1];\r
} SMBIOS_TABLE_TYPE15;\r
\r
///\r
/// Physical Memory Array - Use.\r
///\r
typedef enum {\r
- MemoryArrayUseOther = 0x01,\r
- MemoryArrayUseUnknown = 0x02,\r
- MemoryArrayUseSystemMemory = 0x03,\r
- MemoryArrayUseVideoMemory = 0x04,\r
- MemoryArrayUseFlashMemory = 0x05,\r
- MemoryArrayUseNonVolatileRam = 0x06,\r
- MemoryArrayUseCacheMemory = 0x07\r
+ MemoryArrayUseOther = 0x01,\r
+ MemoryArrayUseUnknown = 0x02,\r
+ MemoryArrayUseSystemMemory = 0x03,\r
+ MemoryArrayUseVideoMemory = 0x04,\r
+ MemoryArrayUseFlashMemory = 0x05,\r
+ MemoryArrayUseNonVolatileRam = 0x06,\r
+ MemoryArrayUseCacheMemory = 0x07\r
} MEMORY_ARRAY_USE;\r
\r
///\r
/// Physical Memory Array - Error Correction Types.\r
///\r
typedef enum {\r
- MemoryErrorCorrectionOther = 0x01,\r
- MemoryErrorCorrectionUnknown = 0x02,\r
- MemoryErrorCorrectionNone = 0x03,\r
- MemoryErrorCorrectionParity = 0x04,\r
- MemoryErrorCorrectionSingleBitEcc = 0x05,\r
- MemoryErrorCorrectionMultiBitEcc = 0x06,\r
- MemoryErrorCorrectionCrc = 0x07\r
+ MemoryErrorCorrectionOther = 0x01,\r
+ MemoryErrorCorrectionUnknown = 0x02,\r
+ MemoryErrorCorrectionNone = 0x03,\r
+ MemoryErrorCorrectionParity = 0x04,\r
+ MemoryErrorCorrectionSingleBitEcc = 0x05,\r
+ MemoryErrorCorrectionMultiBitEcc = 0x06,\r
+ MemoryErrorCorrectionCrc = 0x07\r
} MEMORY_ERROR_CORRECTION;\r
\r
///\r
/// together to form a memory address space.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.\r
- UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.\r
- UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.\r
- UINT32 MaximumCapacity;\r
- UINT16 MemoryErrorInformationHandle;\r
- UINT16 NumberOfMemoryDevices;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.\r
+ UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.\r
+ UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.\r
+ UINT32 MaximumCapacity;\r
+ UINT16 MemoryErrorInformationHandle;\r
+ UINT16 NumberOfMemoryDevices;\r
//\r
// Add for smbios 2.7\r
//\r
- UINT64 ExtendedMaximumCapacity;\r
+ UINT64 ExtendedMaximumCapacity;\r
} SMBIOS_TABLE_TYPE16;\r
\r
///\r
/// Memory Device - Form Factor.\r
///\r
typedef enum {\r
- MemoryFormFactorOther = 0x01,\r
- MemoryFormFactorUnknown = 0x02,\r
- MemoryFormFactorSimm = 0x03,\r
- MemoryFormFactorSip = 0x04,\r
- MemoryFormFactorChip = 0x05,\r
- MemoryFormFactorDip = 0x06,\r
- MemoryFormFactorZip = 0x07,\r
- MemoryFormFactorProprietaryCard = 0x08,\r
- MemoryFormFactorDimm = 0x09,\r
- MemoryFormFactorTsop = 0x0A,\r
- MemoryFormFactorRowOfChips = 0x0B,\r
- MemoryFormFactorRimm = 0x0C,\r
- MemoryFormFactorSodimm = 0x0D,\r
- MemoryFormFactorSrimm = 0x0E,\r
- MemoryFormFactorFbDimm = 0x0F,\r
- MemoryFormFactorDie = 0x10\r
+ MemoryFormFactorOther = 0x01,\r
+ MemoryFormFactorUnknown = 0x02,\r
+ MemoryFormFactorSimm = 0x03,\r
+ MemoryFormFactorSip = 0x04,\r
+ MemoryFormFactorChip = 0x05,\r
+ MemoryFormFactorDip = 0x06,\r
+ MemoryFormFactorZip = 0x07,\r
+ MemoryFormFactorProprietaryCard = 0x08,\r
+ MemoryFormFactorDimm = 0x09,\r
+ MemoryFormFactorTsop = 0x0A,\r
+ MemoryFormFactorRowOfChips = 0x0B,\r
+ MemoryFormFactorRimm = 0x0C,\r
+ MemoryFormFactorSodimm = 0x0D,\r
+ MemoryFormFactorSrimm = 0x0E,\r
+ MemoryFormFactorFbDimm = 0x0F,\r
+ MemoryFormFactorDie = 0x10\r
} MEMORY_FORM_FACTOR;\r
\r
///\r
/// Memory Device - Type\r
///\r
typedef enum {\r
- MemoryTypeOther = 0x01,\r
- MemoryTypeUnknown = 0x02,\r
- MemoryTypeDram = 0x03,\r
- MemoryTypeEdram = 0x04,\r
- MemoryTypeVram = 0x05,\r
- MemoryTypeSram = 0x06,\r
- MemoryTypeRam = 0x07,\r
- MemoryTypeRom = 0x08,\r
- MemoryTypeFlash = 0x09,\r
- MemoryTypeEeprom = 0x0A,\r
- MemoryTypeFeprom = 0x0B,\r
- MemoryTypeEprom = 0x0C,\r
- MemoryTypeCdram = 0x0D,\r
- MemoryType3Dram = 0x0E,\r
- MemoryTypeSdram = 0x0F,\r
- MemoryTypeSgram = 0x10,\r
- MemoryTypeRdram = 0x11,\r
- MemoryTypeDdr = 0x12,\r
- MemoryTypeDdr2 = 0x13,\r
- MemoryTypeDdr2FbDimm = 0x14,\r
- MemoryTypeDdr3 = 0x18,\r
- MemoryTypeFbd2 = 0x19,\r
- MemoryTypeDdr4 = 0x1A,\r
- MemoryTypeLpddr = 0x1B,\r
- MemoryTypeLpddr2 = 0x1C,\r
- MemoryTypeLpddr3 = 0x1D,\r
- MemoryTypeLpddr4 = 0x1E,\r
- MemoryTypeLogicalNonVolatileDevice = 0x1F,\r
- MemoryTypeHBM = 0x20,\r
- MemoryTypeHBM2 = 0x21,\r
- MemoryTypeDdr5 = 0x22,\r
- MemoryTypeLpddr5 = 0x23\r
+ MemoryTypeOther = 0x01,\r
+ MemoryTypeUnknown = 0x02,\r
+ MemoryTypeDram = 0x03,\r
+ MemoryTypeEdram = 0x04,\r
+ MemoryTypeVram = 0x05,\r
+ MemoryTypeSram = 0x06,\r
+ MemoryTypeRam = 0x07,\r
+ MemoryTypeRom = 0x08,\r
+ MemoryTypeFlash = 0x09,\r
+ MemoryTypeEeprom = 0x0A,\r
+ MemoryTypeFeprom = 0x0B,\r
+ MemoryTypeEprom = 0x0C,\r
+ MemoryTypeCdram = 0x0D,\r
+ MemoryType3Dram = 0x0E,\r
+ MemoryTypeSdram = 0x0F,\r
+ MemoryTypeSgram = 0x10,\r
+ MemoryTypeRdram = 0x11,\r
+ MemoryTypeDdr = 0x12,\r
+ MemoryTypeDdr2 = 0x13,\r
+ MemoryTypeDdr2FbDimm = 0x14,\r
+ MemoryTypeDdr3 = 0x18,\r
+ MemoryTypeFbd2 = 0x19,\r
+ MemoryTypeDdr4 = 0x1A,\r
+ MemoryTypeLpddr = 0x1B,\r
+ MemoryTypeLpddr2 = 0x1C,\r
+ MemoryTypeLpddr3 = 0x1D,\r
+ MemoryTypeLpddr4 = 0x1E,\r
+ MemoryTypeLogicalNonVolatileDevice = 0x1F,\r
+ MemoryTypeHBM = 0x20,\r
+ MemoryTypeHBM2 = 0x21,\r
+ MemoryTypeDdr5 = 0x22,\r
+ MemoryTypeLpddr5 = 0x23\r
} MEMORY_DEVICE_TYPE;\r
\r
///\r
/// Memory Device - Type Detail\r
///\r
typedef struct {\r
- UINT16 Reserved :1;\r
- UINT16 Other :1;\r
- UINT16 Unknown :1;\r
- UINT16 FastPaged :1;\r
- UINT16 StaticColumn :1;\r
- UINT16 PseudoStatic :1;\r
- UINT16 Rambus :1;\r
- UINT16 Synchronous :1;\r
- UINT16 Cmos :1;\r
- UINT16 Edo :1;\r
- UINT16 WindowDram :1;\r
- UINT16 CacheDram :1;\r
- UINT16 Nonvolatile :1;\r
- UINT16 Registered :1;\r
- UINT16 Unbuffered :1;\r
- UINT16 LrDimm :1;\r
+ UINT16 Reserved : 1;\r
+ UINT16 Other : 1;\r
+ UINT16 Unknown : 1;\r
+ UINT16 FastPaged : 1;\r
+ UINT16 StaticColumn : 1;\r
+ UINT16 PseudoStatic : 1;\r
+ UINT16 Rambus : 1;\r
+ UINT16 Synchronous : 1;\r
+ UINT16 Cmos : 1;\r
+ UINT16 Edo : 1;\r
+ UINT16 WindowDram : 1;\r
+ UINT16 CacheDram : 1;\r
+ UINT16 Nonvolatile : 1;\r
+ UINT16 Registered : 1;\r
+ UINT16 Unbuffered : 1;\r
+ UINT16 LrDimm : 1;\r
} MEMORY_DEVICE_TYPE_DETAIL;\r
\r
///\r
/// Memory Device - Memory Technology\r
///\r
typedef enum {\r
- MemoryTechnologyOther = 0x01,\r
- MemoryTechnologyUnknown = 0x02,\r
- MemoryTechnologyDram = 0x03,\r
- MemoryTechnologyNvdimmN = 0x04,\r
- MemoryTechnologyNvdimmF = 0x05,\r
- MemoryTechnologyNvdimmP = 0x06,\r
+ MemoryTechnologyOther = 0x01,\r
+ MemoryTechnologyUnknown = 0x02,\r
+ MemoryTechnologyDram = 0x03,\r
+ MemoryTechnologyNvdimmN = 0x04,\r
+ MemoryTechnologyNvdimmF = 0x05,\r
+ MemoryTechnologyNvdimmP = 0x06,\r
//\r
// This definition is updated to represent Intel\r
// Optane DC Persistent Memory in SMBIOS spec 3.4.0\r
//\r
- MemoryTechnologyIntelOptanePersistentMemory = 0x07\r
-\r
+ MemoryTechnologyIntelOptanePersistentMemory = 0x07\r
} MEMORY_DEVICE_TECHNOLOGY;\r
\r
///\r
/// Individual bit fields\r
///\r
struct {\r
- UINT16 Reserved :1; ///< Set to 0.\r
- UINT16 Other :1;\r
- UINT16 Unknown :1;\r
- UINT16 VolatileMemory :1;\r
- UINT16 ByteAccessiblePersistentMemory :1;\r
- UINT16 BlockAccessiblePersistentMemory :1;\r
- UINT16 Reserved2 :10; ///< Set to 0.\r
+ UINT16 Reserved : 1; ///< Set to 0.\r
+ UINT16 Other : 1;\r
+ UINT16 Unknown : 1;\r
+ UINT16 VolatileMemory : 1;\r
+ UINT16 ByteAccessiblePersistentMemory : 1;\r
+ UINT16 BlockAccessiblePersistentMemory : 1;\r
+ UINT16 Reserved2 : 10; ///< Set to 0.\r
} Bits;\r
///\r
/// All bit fields as a 16-bit value\r
///\r
- UINT16 Uint16;\r
+ UINT16 Uint16;\r
} MEMORY_DEVICE_OPERATING_MODE_CAPABILITY;\r
\r
///\r
/// socket is currently populated.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT16 MemoryArrayHandle;\r
- UINT16 MemoryErrorInformationHandle;\r
- UINT16 TotalWidth;\r
- UINT16 DataWidth;\r
- UINT16 Size;\r
- UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.\r
- UINT8 DeviceSet;\r
- SMBIOS_TABLE_STRING DeviceLocator;\r
- SMBIOS_TABLE_STRING BankLocator;\r
- UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.\r
- MEMORY_DEVICE_TYPE_DETAIL TypeDetail;\r
- UINT16 Speed;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING AssetTag;\r
- SMBIOS_TABLE_STRING PartNumber;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT16 MemoryArrayHandle;\r
+ UINT16 MemoryErrorInformationHandle;\r
+ UINT16 TotalWidth;\r
+ UINT16 DataWidth;\r
+ UINT16 Size;\r
+ UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.\r
+ UINT8 DeviceSet;\r
+ SMBIOS_TABLE_STRING DeviceLocator;\r
+ SMBIOS_TABLE_STRING BankLocator;\r
+ UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.\r
+ MEMORY_DEVICE_TYPE_DETAIL TypeDetail;\r
+ UINT16 Speed;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING AssetTag;\r
+ SMBIOS_TABLE_STRING PartNumber;\r
//\r
// Add for smbios 2.6\r
//\r
- UINT8 Attributes;\r
+ UINT8 Attributes;\r
//\r
// Add for smbios 2.7\r
//\r
- UINT32 ExtendedSize;\r
+ UINT32 ExtendedSize;\r
//\r
// Keep using name "ConfiguredMemoryClockSpeed" for compatibility\r
// although this field is renamed from "Configured Memory Clock Speed"\r
// to "Configured Memory Speed" in smbios 3.2.0.\r
//\r
- UINT16 ConfiguredMemoryClockSpeed;\r
+ UINT16 ConfiguredMemoryClockSpeed;\r
//\r
// Add for smbios 2.8.0\r
//\r
- UINT16 MinimumVoltage;\r
- UINT16 MaximumVoltage;\r
- UINT16 ConfiguredVoltage;\r
+ UINT16 MinimumVoltage;\r
+ UINT16 MaximumVoltage;\r
+ UINT16 ConfiguredVoltage;\r
//\r
// Add for smbios 3.2.0\r
//\r
- UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY\r
- MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;\r
- SMBIOS_TABLE_STRING FirmwareVersion;\r
- UINT16 ModuleManufacturerID;\r
- UINT16 ModuleProductID;\r
- UINT16 MemorySubsystemControllerManufacturerID;\r
- UINT16 MemorySubsystemControllerProductID;\r
- UINT64 NonVolatileSize;\r
- UINT64 VolatileSize;\r
- UINT64 CacheSize;\r
- UINT64 LogicalSize;\r
+ UINT8 MemoryTechnology; ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY\r
+ MEMORY_DEVICE_OPERATING_MODE_CAPABILITY MemoryOperatingModeCapability;\r
+ SMBIOS_TABLE_STRING FirmwareVersion;\r
+ UINT16 ModuleManufacturerID;\r
+ UINT16 ModuleProductID;\r
+ UINT16 MemorySubsystemControllerManufacturerID;\r
+ UINT16 MemorySubsystemControllerProductID;\r
+ UINT64 NonVolatileSize;\r
+ UINT64 VolatileSize;\r
+ UINT64 CacheSize;\r
+ UINT64 LogicalSize;\r
//\r
// Add for smbios 3.3.0\r
//\r
- UINT32 ExtendedSpeed;\r
- UINT32 ExtendedConfiguredMemorySpeed;\r
+ UINT32 ExtendedSpeed;\r
+ UINT32 ExtendedConfiguredMemorySpeed;\r
} SMBIOS_TABLE_TYPE17;\r
\r
///\r
/// 32-bit Memory Error Information - Error Type.\r
///\r
typedef enum {\r
- MemoryErrorOther = 0x01,\r
- MemoryErrorUnknown = 0x02,\r
- MemoryErrorOk = 0x03,\r
- MemoryErrorBadRead = 0x04,\r
- MemoryErrorParity = 0x05,\r
- MemoryErrorSigleBit = 0x06,\r
- MemoryErrorDoubleBit = 0x07,\r
- MemoryErrorMultiBit = 0x08,\r
- MemoryErrorNibble = 0x09,\r
- MemoryErrorChecksum = 0x0A,\r
- MemoryErrorCrc = 0x0B,\r
- MemoryErrorCorrectSingleBit = 0x0C,\r
- MemoryErrorCorrected = 0x0D,\r
- MemoryErrorUnCorrectable = 0x0E\r
+ MemoryErrorOther = 0x01,\r
+ MemoryErrorUnknown = 0x02,\r
+ MemoryErrorOk = 0x03,\r
+ MemoryErrorBadRead = 0x04,\r
+ MemoryErrorParity = 0x05,\r
+ MemoryErrorSigleBit = 0x06,\r
+ MemoryErrorDoubleBit = 0x07,\r
+ MemoryErrorMultiBit = 0x08,\r
+ MemoryErrorNibble = 0x09,\r
+ MemoryErrorChecksum = 0x0A,\r
+ MemoryErrorCrc = 0x0B,\r
+ MemoryErrorCorrectSingleBit = 0x0C,\r
+ MemoryErrorCorrected = 0x0D,\r
+ MemoryErrorUnCorrectable = 0x0E\r
} MEMORY_ERROR_TYPE;\r
\r
///\r
/// 32-bit Memory Error Information - Error Granularity.\r
///\r
typedef enum {\r
- MemoryGranularityOther = 0x01,\r
- MemoryGranularityOtherUnknown = 0x02,\r
- MemoryGranularityDeviceLevel = 0x03,\r
- MemoryGranularityMemPartitionLevel = 0x04\r
+ MemoryGranularityOther = 0x01,\r
+ MemoryGranularityOtherUnknown = 0x02,\r
+ MemoryGranularityDeviceLevel = 0x03,\r
+ MemoryGranularityMemPartitionLevel = 0x04\r
} MEMORY_ERROR_GRANULARITY;\r
\r
///\r
/// 32-bit Memory Error Information - Error Operation.\r
///\r
typedef enum {\r
- MemoryErrorOperationOther = 0x01,\r
- MemoryErrorOperationUnknown = 0x02,\r
- MemoryErrorOperationRead = 0x03,\r
- MemoryErrorOperationWrite = 0x04,\r
- MemoryErrorOperationPartialWrite = 0x05\r
+ MemoryErrorOperationOther = 0x01,\r
+ MemoryErrorOperationUnknown = 0x02,\r
+ MemoryErrorOperationRead = 0x03,\r
+ MemoryErrorOperationWrite = 0x04,\r
+ MemoryErrorOperationPartialWrite = 0x05\r
} MEMORY_ERROR_OPERATION;\r
\r
///\r
/// within a Physical Memory Array.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r
- UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
- UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
- UINT32 VendorSyndrome;\r
- UINT32 MemoryArrayErrorAddress;\r
- UINT32 DeviceErrorAddress;\r
- UINT32 ErrorResolution;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
+ UINT32 VendorSyndrome;\r
+ UINT32 MemoryArrayErrorAddress;\r
+ UINT32 DeviceErrorAddress;\r
+ UINT32 ErrorResolution;\r
} SMBIOS_TABLE_TYPE18;\r
\r
///\r
/// One structure is present for each contiguous address range described.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT32 StartingAddress;\r
- UINT32 EndingAddress;\r
- UINT16 MemoryArrayHandle;\r
- UINT8 PartitionWidth;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT32 StartingAddress;\r
+ UINT32 EndingAddress;\r
+ UINT16 MemoryArrayHandle;\r
+ UINT8 PartitionWidth;\r
//\r
// Add for smbios 2.7\r
//\r
- UINT64 ExtendedStartingAddress;\r
- UINT64 ExtendedEndingAddress;\r
+ UINT64 ExtendedStartingAddress;\r
+ UINT64 ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE19;\r
\r
///\r
/// One structure is present for each contiguous address range described.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT32 StartingAddress;\r
- UINT32 EndingAddress;\r
- UINT16 MemoryDeviceHandle;\r
- UINT16 MemoryArrayMappedAddressHandle;\r
- UINT8 PartitionRowPosition;\r
- UINT8 InterleavePosition;\r
- UINT8 InterleavedDataDepth;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT32 StartingAddress;\r
+ UINT32 EndingAddress;\r
+ UINT16 MemoryDeviceHandle;\r
+ UINT16 MemoryArrayMappedAddressHandle;\r
+ UINT8 PartitionRowPosition;\r
+ UINT8 InterleavePosition;\r
+ UINT8 InterleavedDataDepth;\r
//\r
// Add for smbios 2.7\r
//\r
- UINT64 ExtendedStartingAddress;\r
- UINT64 ExtendedEndingAddress;\r
+ UINT64 ExtendedStartingAddress;\r
+ UINT64 ExtendedEndingAddress;\r
} SMBIOS_TABLE_TYPE20;\r
\r
///\r
/// Built-in Pointing Device - Type\r
///\r
typedef enum {\r
- PointingDeviceTypeOther = 0x01,\r
- PointingDeviceTypeUnknown = 0x02,\r
- PointingDeviceTypeMouse = 0x03,\r
- PointingDeviceTypeTrackBall = 0x04,\r
- PointingDeviceTypeTrackPoint = 0x05,\r
- PointingDeviceTypeGlidePoint = 0x06,\r
- PointingDeviceTouchPad = 0x07,\r
- PointingDeviceTouchScreen = 0x08,\r
- PointingDeviceOpticalSensor = 0x09\r
+ PointingDeviceTypeOther = 0x01,\r
+ PointingDeviceTypeUnknown = 0x02,\r
+ PointingDeviceTypeMouse = 0x03,\r
+ PointingDeviceTypeTrackBall = 0x04,\r
+ PointingDeviceTypeTrackPoint = 0x05,\r
+ PointingDeviceTypeGlidePoint = 0x06,\r
+ PointingDeviceTouchPad = 0x07,\r
+ PointingDeviceTouchScreen = 0x08,\r
+ PointingDeviceOpticalSensor = 0x09\r
} BUILTIN_POINTING_DEVICE_TYPE;\r
\r
///\r
/// Built-in Pointing Device - Interface.\r
///\r
typedef enum {\r
- PointingDeviceInterfaceOther = 0x01,\r
- PointingDeviceInterfaceUnknown = 0x02,\r
- PointingDeviceInterfaceSerial = 0x03,\r
- PointingDeviceInterfacePs2 = 0x04,\r
- PointingDeviceInterfaceInfrared = 0x05,\r
- PointingDeviceInterfaceHpHil = 0x06,\r
- PointingDeviceInterfaceBusMouse = 0x07,\r
- PointingDeviceInterfaceADB = 0x08,\r
- PointingDeviceInterfaceBusMouseDB9 = 0xA0,\r
- PointingDeviceInterfaceBusMouseMicroDin = 0xA1,\r
- PointingDeviceInterfaceUsb = 0xA2\r
+ PointingDeviceInterfaceOther = 0x01,\r
+ PointingDeviceInterfaceUnknown = 0x02,\r
+ PointingDeviceInterfaceSerial = 0x03,\r
+ PointingDeviceInterfacePs2 = 0x04,\r
+ PointingDeviceInterfaceInfrared = 0x05,\r
+ PointingDeviceInterfaceHpHil = 0x06,\r
+ PointingDeviceInterfaceBusMouse = 0x07,\r
+ PointingDeviceInterfaceADB = 0x08,\r
+ PointingDeviceInterfaceBusMouseDB9 = 0xA0,\r
+ PointingDeviceInterfaceBusMouseMicroDin = 0xA1,\r
+ PointingDeviceInterfaceUsb = 0xA2\r
} BUILTIN_POINTING_DEVICE_INTERFACE;\r
\r
///\r
/// pointing device is active for the system's use!\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.\r
- UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.\r
- UINT8 NumberOfButtons;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.\r
+ UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.\r
+ UINT8 NumberOfButtons;\r
} SMBIOS_TABLE_TYPE21;\r
\r
///\r
/// Portable Battery - Device Chemistry\r
///\r
typedef enum {\r
- PortableBatteryDeviceChemistryOther = 0x01,\r
- PortableBatteryDeviceChemistryUnknown = 0x02,\r
- PortableBatteryDeviceChemistryLeadAcid = 0x03,\r
- PortableBatteryDeviceChemistryNickelCadmium = 0x04,\r
- PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,\r
- PortableBatteryDeviceChemistryLithiumIon = 0x06,\r
- PortableBatteryDeviceChemistryZincAir = 0x07,\r
- PortableBatteryDeviceChemistryLithiumPolymer = 0x08\r
+ PortableBatteryDeviceChemistryOther = 0x01,\r
+ PortableBatteryDeviceChemistryUnknown = 0x02,\r
+ PortableBatteryDeviceChemistryLeadAcid = 0x03,\r
+ PortableBatteryDeviceChemistryNickelCadmium = 0x04,\r
+ PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,\r
+ PortableBatteryDeviceChemistryLithiumIon = 0x06,\r
+ PortableBatteryDeviceChemistryZincAir = 0x07,\r
+ PortableBatteryDeviceChemistryLithiumPolymer = 0x08\r
} PORTABLE_BATTERY_DEVICE_CHEMISTRY;\r
\r
///\r
/// a single battery pack's attributes.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Location;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- SMBIOS_TABLE_STRING ManufactureDate;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING DeviceName;\r
- UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.\r
- UINT16 DeviceCapacity;\r
- UINT16 DesignVoltage;\r
- SMBIOS_TABLE_STRING SBDSVersionNumber;\r
- UINT8 MaximumErrorInBatteryData;\r
- UINT16 SBDSSerialNumber;\r
- UINT16 SBDSManufactureDate;\r
- SMBIOS_TABLE_STRING SBDSDeviceChemistry;\r
- UINT8 DesignCapacityMultiplier;\r
- UINT32 OEMSpecific;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Location;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ SMBIOS_TABLE_STRING ManufactureDate;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING DeviceName;\r
+ UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.\r
+ UINT16 DeviceCapacity;\r
+ UINT16 DesignVoltage;\r
+ SMBIOS_TABLE_STRING SBDSVersionNumber;\r
+ UINT8 MaximumErrorInBatteryData;\r
+ UINT16 SBDSSerialNumber;\r
+ UINT16 SBDSManufactureDate;\r
+ SMBIOS_TABLE_STRING SBDSDeviceChemistry;\r
+ UINT8 DesignCapacityMultiplier;\r
+ UINT32 OEMSpecific;\r
} SMBIOS_TABLE_TYPE22;\r
\r
///\r
/// the system will re-boot according to the Boot Option at Limit.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 Capabilities;\r
- UINT16 ResetCount;\r
- UINT16 ResetLimit;\r
- UINT16 TimerInterval;\r
- UINT16 Timeout;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 Capabilities;\r
+ UINT16 ResetCount;\r
+ UINT16 ResetLimit;\r
+ UINT16 TimerInterval;\r
+ UINT16 Timeout;\r
} SMBIOS_TABLE_TYPE23;\r
\r
///\r
/// This structure describes the system-wide hardware security settings.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 HardwareSecuritySettings;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 HardwareSecuritySettings;\r
} SMBIOS_TABLE_TYPE24;\r
\r
///\r
/// this structure implies that a timed power-on facility is available for the system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 NextScheduledPowerOnMonth;\r
- UINT8 NextScheduledPowerOnDayOfMonth;\r
- UINT8 NextScheduledPowerOnHour;\r
- UINT8 NextScheduledPowerOnMinute;\r
- UINT8 NextScheduledPowerOnSecond;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 NextScheduledPowerOnMonth;\r
+ UINT8 NextScheduledPowerOnDayOfMonth;\r
+ UINT8 NextScheduledPowerOnHour;\r
+ UINT8 NextScheduledPowerOnMinute;\r
+ UINT8 NextScheduledPowerOnSecond;\r
} SMBIOS_TABLE_TYPE25;\r
\r
///\r
/// Voltage Probe - Location and Status.\r
///\r
typedef struct {\r
- UINT8 VoltageProbeSite :5;\r
- UINT8 VoltageProbeStatus :3;\r
+ UINT8 VoltageProbeSite : 5;\r
+ UINT8 VoltageProbeStatus : 3;\r
} MISC_VOLTAGE_PROBE_LOCATION;\r
\r
///\r
/// Each structure describes a single voltage probe.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Description;\r
- MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;\r
- UINT16 MaximumValue;\r
- UINT16 MinimumValue;\r
- UINT16 Resolution;\r
- UINT16 Tolerance;\r
- UINT16 Accuracy;\r
- UINT32 OEMDefined;\r
- UINT16 NominalValue;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Description;\r
+ MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;\r
+ UINT16 MaximumValue;\r
+ UINT16 MinimumValue;\r
+ UINT16 Resolution;\r
+ UINT16 Tolerance;\r
+ UINT16 Accuracy;\r
+ UINT32 OEMDefined;\r
+ UINT16 NominalValue;\r
} SMBIOS_TABLE_TYPE26;\r
\r
///\r
/// Cooling Device - Device Type and Status.\r
///\r
typedef struct {\r
- UINT8 CoolingDevice :5;\r
- UINT8 CoolingDeviceStatus :3;\r
+ UINT8 CoolingDevice : 5;\r
+ UINT8 CoolingDeviceStatus : 3;\r
} MISC_COOLING_DEVICE_TYPE;\r
\r
///\r
/// Each structure describes a single cooling device.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT16 TemperatureProbeHandle;\r
- MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;\r
- UINT8 CoolingUnitGroup;\r
- UINT32 OEMDefined;\r
- UINT16 NominalSpeed;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT16 TemperatureProbeHandle;\r
+ MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;\r
+ UINT8 CoolingUnitGroup;\r
+ UINT32 OEMDefined;\r
+ UINT16 NominalSpeed;\r
//\r
// Add for smbios 2.7\r
//\r
- SMBIOS_TABLE_STRING Description;\r
+ SMBIOS_TABLE_STRING Description;\r
} SMBIOS_TABLE_TYPE27;\r
\r
///\r
/// Temperature Probe - Location and Status.\r
///\r
typedef struct {\r
- UINT8 TemperatureProbeSite :5;\r
- UINT8 TemperatureProbeStatus :3;\r
+ UINT8 TemperatureProbeSite : 5;\r
+ UINT8 TemperatureProbeStatus : 3;\r
} MISC_TEMPERATURE_PROBE_LOCATION;\r
\r
///\r
/// Each structure describes a single temperature probe.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Description;\r
- MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;\r
- UINT16 MaximumValue;\r
- UINT16 MinimumValue;\r
- UINT16 Resolution;\r
- UINT16 Tolerance;\r
- UINT16 Accuracy;\r
- UINT32 OEMDefined;\r
- UINT16 NominalValue;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Description;\r
+ MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;\r
+ UINT16 MaximumValue;\r
+ UINT16 MinimumValue;\r
+ UINT16 Resolution;\r
+ UINT16 Tolerance;\r
+ UINT16 Accuracy;\r
+ UINT32 OEMDefined;\r
+ UINT16 NominalValue;\r
} SMBIOS_TABLE_TYPE28;\r
\r
///\r
/// Electrical Current Probe - Location and Status.\r
///\r
typedef struct {\r
- UINT8 ElectricalCurrentProbeSite :5;\r
- UINT8 ElectricalCurrentProbeStatus :3;\r
+ UINT8 ElectricalCurrentProbeSite : 5;\r
+ UINT8 ElectricalCurrentProbeStatus : 3;\r
} MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;\r
\r
///\r
/// Each structure describes a single electrical current probe.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Description;\r
- MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;\r
- UINT16 MaximumValue;\r
- UINT16 MinimumValue;\r
- UINT16 Resolution;\r
- UINT16 Tolerance;\r
- UINT16 Accuracy;\r
- UINT32 OEMDefined;\r
- UINT16 NominalValue;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Description;\r
+ MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;\r
+ UINT16 MaximumValue;\r
+ UINT16 MinimumValue;\r
+ UINT16 Resolution;\r
+ UINT16 Tolerance;\r
+ UINT16 Accuracy;\r
+ UINT32 OEMDefined;\r
+ UINT16 NominalValue;\r
} SMBIOS_TABLE_TYPE29;\r
\r
///\r
/// is not available due to power-down status, hardware failures, or boot failures.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING ManufacturerName;\r
- UINT8 Connections;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING ManufacturerName;\r
+ UINT8 Connections;\r
} SMBIOS_TABLE_TYPE30;\r
\r
///\r
/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS).\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 Checksum;\r
- UINT8 Reserved1;\r
- UINT16 Reserved2;\r
- UINT32 BisEntry16;\r
- UINT32 BisEntry32;\r
- UINT64 Reserved3;\r
- UINT32 Reserved4;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 Checksum;\r
+ UINT8 Reserved1;\r
+ UINT16 Reserved2;\r
+ UINT32 BisEntry16;\r
+ UINT32 BisEntry32;\r
+ UINT64 Reserved3;\r
+ UINT32 Reserved4;\r
} SMBIOS_TABLE_TYPE31;\r
\r
///\r
/// System Boot Information - System Boot Status.\r
///\r
typedef enum {\r
- BootInformationStatusNoError = 0x00,\r
- BootInformationStatusNoBootableMedia = 0x01,\r
- BootInformationStatusNormalOSFailedLoading = 0x02,\r
- BootInformationStatusFirmwareDetectedFailure = 0x03,\r
- BootInformationStatusOSDetectedFailure = 0x04,\r
- BootInformationStatusUserRequestedBoot = 0x05,\r
- BootInformationStatusSystemSecurityViolation = 0x06,\r
- BootInformationStatusPreviousRequestedImage = 0x07,\r
- BootInformationStatusWatchdogTimerExpired = 0x08,\r
- BootInformationStatusStartReserved = 0x09,\r
- BootInformationStatusStartOemSpecific = 0x80,\r
- BootInformationStatusStartProductSpecific = 0xC0\r
+ BootInformationStatusNoError = 0x00,\r
+ BootInformationStatusNoBootableMedia = 0x01,\r
+ BootInformationStatusNormalOSFailedLoading = 0x02,\r
+ BootInformationStatusFirmwareDetectedFailure = 0x03,\r
+ BootInformationStatusOSDetectedFailure = 0x04,\r
+ BootInformationStatusUserRequestedBoot = 0x05,\r
+ BootInformationStatusSystemSecurityViolation = 0x06,\r
+ BootInformationStatusPreviousRequestedImage = 0x07,\r
+ BootInformationStatusWatchdogTimerExpired = 0x08,\r
+ BootInformationStatusStartReserved = 0x09,\r
+ BootInformationStatusStartOemSpecific = 0x80,\r
+ BootInformationStatusStartProductSpecific = 0xC0\r
} MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;\r
\r
///\r
/// reason code indicated either a firmware- or operating system-detected hardware failure.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 Reserved[6];\r
- UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 Reserved[6];\r
+ UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.\r
} SMBIOS_TABLE_TYPE32;\r
\r
///\r
/// when the error address is above 4G (0xFFFFFFFF).\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r
- UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
- UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
- UINT32 VendorSyndrome;\r
- UINT64 MemoryArrayErrorAddress;\r
- UINT64 DeviceErrorAddress;\r
- UINT32 ErrorResolution;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r
+ UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r
+ UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r
+ UINT32 VendorSyndrome;\r
+ UINT64 MemoryArrayErrorAddress;\r
+ UINT64 DeviceErrorAddress;\r
+ UINT32 ErrorResolution;\r
} SMBIOS_TABLE_TYPE33;\r
\r
///\r
/// Management Device - Type.\r
///\r
typedef enum {\r
- ManagementDeviceTypeOther = 0x01,\r
- ManagementDeviceTypeUnknown = 0x02,\r
- ManagementDeviceTypeLm75 = 0x03,\r
- ManagementDeviceTypeLm78 = 0x04,\r
- ManagementDeviceTypeLm79 = 0x05,\r
- ManagementDeviceTypeLm80 = 0x06,\r
- ManagementDeviceTypeLm81 = 0x07,\r
- ManagementDeviceTypeAdm9240 = 0x08,\r
- ManagementDeviceTypeDs1780 = 0x09,\r
- ManagementDeviceTypeMaxim1617 = 0x0A,\r
- ManagementDeviceTypeGl518Sm = 0x0B,\r
- ManagementDeviceTypeW83781D = 0x0C,\r
- ManagementDeviceTypeHt82H791 = 0x0D\r
+ ManagementDeviceTypeOther = 0x01,\r
+ ManagementDeviceTypeUnknown = 0x02,\r
+ ManagementDeviceTypeLm75 = 0x03,\r
+ ManagementDeviceTypeLm78 = 0x04,\r
+ ManagementDeviceTypeLm79 = 0x05,\r
+ ManagementDeviceTypeLm80 = 0x06,\r
+ ManagementDeviceTypeLm81 = 0x07,\r
+ ManagementDeviceTypeAdm9240 = 0x08,\r
+ ManagementDeviceTypeDs1780 = 0x09,\r
+ ManagementDeviceTypeMaxim1617 = 0x0A,\r
+ ManagementDeviceTypeGl518Sm = 0x0B,\r
+ ManagementDeviceTypeW83781D = 0x0C,\r
+ ManagementDeviceTypeHt82H791 = 0x0D\r
} MISC_MANAGEMENT_DEVICE_TYPE;\r
\r
///\r
/// probes as defined by one or more Management Device Component structures.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Description;\r
- UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.\r
- UINT32 Address;\r
- UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Description;\r
+ UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.\r
+ UINT32 Address;\r
+ UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.\r
} SMBIOS_TABLE_TYPE34;\r
\r
///\r
/// that define the controlling hardware device and (optionally) the component's thresholds.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING Description;\r
- UINT16 ManagementDeviceHandle;\r
- UINT16 ComponentHandle;\r
- UINT16 ThresholdHandle;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING Description;\r
+ UINT16 ManagementDeviceHandle;\r
+ UINT16 ComponentHandle;\r
+ UINT16 ThresholdHandle;\r
} SMBIOS_TABLE_TYPE35;\r
\r
///\r
/// a component (probe or cooling-unit) contained within a Management Device.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT16 LowerThresholdNonCritical;\r
- UINT16 UpperThresholdNonCritical;\r
- UINT16 LowerThresholdCritical;\r
- UINT16 UpperThresholdCritical;\r
- UINT16 LowerThresholdNonRecoverable;\r
- UINT16 UpperThresholdNonRecoverable;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT16 LowerThresholdNonCritical;\r
+ UINT16 UpperThresholdNonCritical;\r
+ UINT16 LowerThresholdCritical;\r
+ UINT16 UpperThresholdCritical;\r
+ UINT16 LowerThresholdNonRecoverable;\r
+ UINT16 UpperThresholdNonRecoverable;\r
} SMBIOS_TABLE_TYPE36;\r
\r
///\r
/// Memory Channel Entry.\r
///\r
typedef struct {\r
- UINT8 DeviceLoad;\r
- UINT16 DeviceHandle;\r
+ UINT8 DeviceLoad;\r
+ UINT16 DeviceHandle;\r
} MEMORY_DEVICE;\r
\r
///\r
/// Memory Channel - Channel Type.\r
///\r
typedef enum {\r
- MemoryChannelTypeOther = 0x01,\r
- MemoryChannelTypeUnknown = 0x02,\r
- MemoryChannelTypeRambus = 0x03,\r
- MemoryChannelTypeSyncLink = 0x04\r
+ MemoryChannelTypeOther = 0x01,\r
+ MemoryChannelTypeUnknown = 0x02,\r
+ MemoryChannelTypeRambus = 0x03,\r
+ MemoryChannelTypeSyncLink = 0x04\r
} MEMORY_CHANNEL_TYPE;\r
\r
///\r
/// The sum of all device loads cannot exceed the channel's defined maximum.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 ChannelType;\r
- UINT8 MaximumChannelLoad;\r
- UINT8 MemoryDeviceCount;\r
- MEMORY_DEVICE MemoryDevice[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 ChannelType;\r
+ UINT8 MaximumChannelLoad;\r
+ UINT8 MemoryDeviceCount;\r
+ MEMORY_DEVICE MemoryDevice[1];\r
} SMBIOS_TABLE_TYPE37;\r
\r
///\r
/// IPMI Device Information - BMC Interface Type\r
///\r
typedef enum {\r
- IPMIDeviceInfoInterfaceTypeUnknown = 0x00,\r
- IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.\r
- IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.\r
- IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer\r
- IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface\r
+ IPMIDeviceInfoInterfaceTypeUnknown = 0x00,\r
+ IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.\r
+ IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.\r
+ IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer\r
+ IPMIDeviceInfoInterfaceTypeSSIF = 0x04 ///< SMBus System Interface\r
} BMC_INTERFACE_TYPE;\r
\r
///\r
/// Providing Type 38 is recommended for backward compatibility.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.\r
- UINT8 IPMISpecificationRevision;\r
- UINT8 I2CSlaveAddress;\r
- UINT8 NVStorageDeviceAddress;\r
- UINT64 BaseAddress;\r
- UINT8 BaseAddressModifier_InterruptInfo;\r
- UINT8 InterruptNumber;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.\r
+ UINT8 IPMISpecificationRevision;\r
+ UINT8 I2CSlaveAddress;\r
+ UINT8 NVStorageDeviceAddress;\r
+ UINT64 BaseAddress;\r
+ UINT8 BaseAddressModifier_InterruptInfo;\r
+ UINT8 InterruptNumber;\r
} SMBIOS_TABLE_TYPE38;\r
\r
///\r
/// System Power Supply - Power Supply Characteristics.\r
///\r
typedef struct {\r
- UINT16 PowerSupplyHotReplaceable:1;\r
- UINT16 PowerSupplyPresent :1;\r
- UINT16 PowerSupplyUnplugged :1;\r
- UINT16 InputVoltageRangeSwitch :4;\r
- UINT16 PowerSupplyStatus :3;\r
- UINT16 PowerSupplyType :4;\r
- UINT16 Reserved :2;\r
+ UINT16 PowerSupplyHotReplaceable : 1;\r
+ UINT16 PowerSupplyPresent : 1;\r
+ UINT16 PowerSupplyUnplugged : 1;\r
+ UINT16 InputVoltageRangeSwitch : 4;\r
+ UINT16 PowerSupplyStatus : 3;\r
+ UINT16 PowerSupplyType : 4;\r
+ UINT16 Reserved : 2;\r
} SYS_POWER_SUPPLY_CHARACTERISTICS;\r
\r
///\r
/// of this record is present for each possible power supply in a system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 PowerUnitGroup;\r
- SMBIOS_TABLE_STRING Location;\r
- SMBIOS_TABLE_STRING DeviceName;\r
- SMBIOS_TABLE_STRING Manufacturer;\r
- SMBIOS_TABLE_STRING SerialNumber;\r
- SMBIOS_TABLE_STRING AssetTagNumber;\r
- SMBIOS_TABLE_STRING ModelPartNumber;\r
- SMBIOS_TABLE_STRING RevisionLevel;\r
- UINT16 MaxPowerCapacity;\r
- SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;\r
- UINT16 InputVoltageProbeHandle;\r
- UINT16 CoolingDeviceHandle;\r
- UINT16 InputCurrentProbeHandle;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 PowerUnitGroup;\r
+ SMBIOS_TABLE_STRING Location;\r
+ SMBIOS_TABLE_STRING DeviceName;\r
+ SMBIOS_TABLE_STRING Manufacturer;\r
+ SMBIOS_TABLE_STRING SerialNumber;\r
+ SMBIOS_TABLE_STRING AssetTagNumber;\r
+ SMBIOS_TABLE_STRING ModelPartNumber;\r
+ SMBIOS_TABLE_STRING RevisionLevel;\r
+ UINT16 MaxPowerCapacity;\r
+ SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;\r
+ UINT16 InputVoltageProbeHandle;\r
+ UINT16 CoolingDeviceHandle;\r
+ UINT16 InputCurrentProbeHandle;\r
} SMBIOS_TABLE_TYPE39;\r
\r
///\r
/// Additional Information Entry Format.\r
///\r
typedef struct {\r
- UINT8 EntryLength;\r
- UINT16 ReferencedHandle;\r
- UINT8 ReferencedOffset;\r
- SMBIOS_TABLE_STRING EntryString;\r
- UINT8 Value[1];\r
+ UINT8 EntryLength;\r
+ UINT16 ReferencedHandle;\r
+ UINT8 ReferencedOffset;\r
+ SMBIOS_TABLE_STRING EntryString;\r
+ UINT8 Value[1];\r
} ADDITIONAL_INFORMATION_ENTRY;\r
\r
///\r
/// enumerated values and interim field updates in another structure.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 NumberOfAdditionalInformationEntries;\r
- ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 NumberOfAdditionalInformationEntries;\r
+ ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];\r
} SMBIOS_TABLE_TYPE40;\r
\r
///\r
/// Onboard Devices Extended Information - Onboard Device Types.\r
///\r
-typedef enum{\r
+typedef enum {\r
OnBoardDeviceExtendedTypeOther = 0x01,\r
OnBoardDeviceExtendedTypeUnknown = 0x02,\r
OnBoardDeviceExtendedTypeVideo = 0x03,\r
/// control over the enabling of the associated device for use by the system.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_TABLE_STRING ReferenceDesignation;\r
- UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE\r
- UINT8 DeviceTypeInstance;\r
- UINT16 SegmentGroupNum;\r
- UINT8 BusNum;\r
- UINT8 DevFuncNum;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_TABLE_STRING ReferenceDesignation;\r
+ UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE\r
+ UINT8 DeviceTypeInstance;\r
+ UINT16 SegmentGroupNum;\r
+ UINT8 BusNum;\r
+ UINT8 DevFuncNum;\r
} SMBIOS_TABLE_TYPE41;\r
\r
///\r
/// Management Controller Host Interface - Protocol Record Data Format.\r
///\r
typedef struct {\r
- UINT8 ProtocolType;\r
- UINT8 ProtocolTypeDataLen;\r
- UINT8 ProtocolTypeData[1];\r
+ UINT8 ProtocolType;\r
+ UINT8 ProtocolTypeDataLen;\r
+ UINT8 ProtocolTypeData[1];\r
} MC_HOST_INTERFACE_PROTOCOL_RECORD;\r
\r
///\r
/// Management Controller Host Interface - Interface Types.\r
/// 00h - 3Fh: MCTP Host Interfaces\r
///\r
-typedef enum{\r
- MCHostInterfaceTypeNetworkHostInterface = 0x40,\r
- MCHostInterfaceTypeOemDefined = 0xF0\r
+typedef enum {\r
+ MCHostInterfaceTypeNetworkHostInterface = 0x40,\r
+ MCHostInterfaceTypeOemDefined = 0xF0\r
} MC_HOST_INTERFACE_TYPE;\r
\r
///\r
/// Management Controller Host Interface - Protocol Types.\r
///\r
-typedef enum{\r
- MCHostInterfaceProtocolTypeIPMI = 0x02,\r
- MCHostInterfaceProtocolTypeMCTP = 0x03,\r
- MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,\r
- MCHostInterfaceProtocolTypeOemDefined = 0xF0\r
+typedef enum {\r
+ MCHostInterfaceProtocolTypeIPMI = 0x02,\r
+ MCHostInterfaceProtocolTypeMCTP = 0x03,\r
+ MCHostInterfaceProtocolTypeRedfishOverIP = 0x04,\r
+ MCHostInterfaceProtocolTypeOemDefined = 0xF0\r
} MC_HOST_INTERFACE_PROTOCOL_TYPE;\r
\r
///\r
/// that do not yet recognize the Type 42 structure.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE\r
- UINT8 InterfaceTypeSpecificDataLength;\r
- UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 InterfaceType; ///< The enumeration value from MC_HOST_INTERFACE_TYPE\r
+ UINT8 InterfaceTypeSpecificDataLength;\r
+ UINT8 InterfaceTypeSpecificData[4]; ///< This field has a minimum of four bytes\r
} SMBIOS_TABLE_TYPE42;\r
\r
-\r
///\r
/// Processor Specific Block - Processor Architecture Type\r
///\r
-typedef enum{\r
+typedef enum {\r
ProcessorSpecificBlockArchTypeReserved = 0x00,\r
ProcessorSpecificBlockArchTypeIa32 = 0x01,\r
ProcessorSpecificBlockArchTypeX64 = 0x02,\r
/// Processor Specific Block is the standard container of processor-specific data.\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 ProcessorArchType;\r
+ UINT8 Length;\r
+ UINT8 ProcessorArchType;\r
///\r
/// Below followed by Processor-specific data\r
///\r
/// architecture workgroups or vendors in separate documents.\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4\r
+ SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_HANDLE RefHandle; ///< This field refer to associated SMBIOS type 4\r
///\r
/// Below followed by Processor-specific block\r
///\r
- PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;\r
+ PROCESSOR_SPECIFIC_BLOCK ProcessorSpecificBlock;\r
} SMBIOS_TABLE_TYPE44;\r
\r
///\r
/// TPM Device (Type 43).\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
- UINT8 VendorID[4];\r
- UINT8 MajorSpecVersion;\r
- UINT8 MinorSpecVersion;\r
- UINT32 FirmwareVersion1;\r
- UINT32 FirmwareVersion2;\r
- SMBIOS_TABLE_STRING Description;\r
- UINT64 Characteristics;\r
- UINT32 OemDefined;\r
+ SMBIOS_STRUCTURE Hdr;\r
+ UINT8 VendorID[4];\r
+ UINT8 MajorSpecVersion;\r
+ UINT8 MinorSpecVersion;\r
+ UINT32 FirmwareVersion1;\r
+ UINT32 FirmwareVersion2;\r
+ SMBIOS_TABLE_STRING Description;\r
+ UINT64 Characteristics;\r
+ UINT32 OemDefined;\r
} SMBIOS_TABLE_TYPE43;\r
\r
///\r
/// Inactive (Type 126)\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_STRUCTURE Hdr;\r
} SMBIOS_TABLE_TYPE126;\r
\r
///\r
/// End-of-Table (Type 127)\r
///\r
typedef struct {\r
- SMBIOS_STRUCTURE Hdr;\r
+ SMBIOS_STRUCTURE Hdr;\r
} SMBIOS_TABLE_TYPE127;\r
\r
///\r
/// Union of all the possible SMBIOS record types.\r
///\r
typedef union {\r
- SMBIOS_STRUCTURE *Hdr;\r
- SMBIOS_TABLE_TYPE0 *Type0;\r
- SMBIOS_TABLE_TYPE1 *Type1;\r
- SMBIOS_TABLE_TYPE2 *Type2;\r
- SMBIOS_TABLE_TYPE3 *Type3;\r
- SMBIOS_TABLE_TYPE4 *Type4;\r
- SMBIOS_TABLE_TYPE5 *Type5;\r
- SMBIOS_TABLE_TYPE6 *Type6;\r
- SMBIOS_TABLE_TYPE7 *Type7;\r
- SMBIOS_TABLE_TYPE8 *Type8;\r
- SMBIOS_TABLE_TYPE9 *Type9;\r
- SMBIOS_TABLE_TYPE10 *Type10;\r
- SMBIOS_TABLE_TYPE11 *Type11;\r
- SMBIOS_TABLE_TYPE12 *Type12;\r
- SMBIOS_TABLE_TYPE13 *Type13;\r
- SMBIOS_TABLE_TYPE14 *Type14;\r
- SMBIOS_TABLE_TYPE15 *Type15;\r
- SMBIOS_TABLE_TYPE16 *Type16;\r
- SMBIOS_TABLE_TYPE17 *Type17;\r
- SMBIOS_TABLE_TYPE18 *Type18;\r
- SMBIOS_TABLE_TYPE19 *Type19;\r
- SMBIOS_TABLE_TYPE20 *Type20;\r
- SMBIOS_TABLE_TYPE21 *Type21;\r
- SMBIOS_TABLE_TYPE22 *Type22;\r
- SMBIOS_TABLE_TYPE23 *Type23;\r
- SMBIOS_TABLE_TYPE24 *Type24;\r
- SMBIOS_TABLE_TYPE25 *Type25;\r
- SMBIOS_TABLE_TYPE26 *Type26;\r
- SMBIOS_TABLE_TYPE27 *Type27;\r
- SMBIOS_TABLE_TYPE28 *Type28;\r
- SMBIOS_TABLE_TYPE29 *Type29;\r
- SMBIOS_TABLE_TYPE30 *Type30;\r
- SMBIOS_TABLE_TYPE31 *Type31;\r
- SMBIOS_TABLE_TYPE32 *Type32;\r
- SMBIOS_TABLE_TYPE33 *Type33;\r
- SMBIOS_TABLE_TYPE34 *Type34;\r
- SMBIOS_TABLE_TYPE35 *Type35;\r
- SMBIOS_TABLE_TYPE36 *Type36;\r
- SMBIOS_TABLE_TYPE37 *Type37;\r
- SMBIOS_TABLE_TYPE38 *Type38;\r
- SMBIOS_TABLE_TYPE39 *Type39;\r
- SMBIOS_TABLE_TYPE40 *Type40;\r
- SMBIOS_TABLE_TYPE41 *Type41;\r
- SMBIOS_TABLE_TYPE42 *Type42;\r
- SMBIOS_TABLE_TYPE43 *Type43;\r
- SMBIOS_TABLE_TYPE44 *Type44;\r
- SMBIOS_TABLE_TYPE126 *Type126;\r
- SMBIOS_TABLE_TYPE127 *Type127;\r
- UINT8 *Raw;\r
+ SMBIOS_STRUCTURE *Hdr;\r
+ SMBIOS_TABLE_TYPE0 *Type0;\r
+ SMBIOS_TABLE_TYPE1 *Type1;\r
+ SMBIOS_TABLE_TYPE2 *Type2;\r
+ SMBIOS_TABLE_TYPE3 *Type3;\r
+ SMBIOS_TABLE_TYPE4 *Type4;\r
+ SMBIOS_TABLE_TYPE5 *Type5;\r
+ SMBIOS_TABLE_TYPE6 *Type6;\r
+ SMBIOS_TABLE_TYPE7 *Type7;\r
+ SMBIOS_TABLE_TYPE8 *Type8;\r
+ SMBIOS_TABLE_TYPE9 *Type9;\r
+ SMBIOS_TABLE_TYPE10 *Type10;\r
+ SMBIOS_TABLE_TYPE11 *Type11;\r
+ SMBIOS_TABLE_TYPE12 *Type12;\r
+ SMBIOS_TABLE_TYPE13 *Type13;\r
+ SMBIOS_TABLE_TYPE14 *Type14;\r
+ SMBIOS_TABLE_TYPE15 *Type15;\r
+ SMBIOS_TABLE_TYPE16 *Type16;\r
+ SMBIOS_TABLE_TYPE17 *Type17;\r
+ SMBIOS_TABLE_TYPE18 *Type18;\r
+ SMBIOS_TABLE_TYPE19 *Type19;\r
+ SMBIOS_TABLE_TYPE20 *Type20;\r
+ SMBIOS_TABLE_TYPE21 *Type21;\r
+ SMBIOS_TABLE_TYPE22 *Type22;\r
+ SMBIOS_TABLE_TYPE23 *Type23;\r
+ SMBIOS_TABLE_TYPE24 *Type24;\r
+ SMBIOS_TABLE_TYPE25 *Type25;\r
+ SMBIOS_TABLE_TYPE26 *Type26;\r
+ SMBIOS_TABLE_TYPE27 *Type27;\r
+ SMBIOS_TABLE_TYPE28 *Type28;\r
+ SMBIOS_TABLE_TYPE29 *Type29;\r
+ SMBIOS_TABLE_TYPE30 *Type30;\r
+ SMBIOS_TABLE_TYPE31 *Type31;\r
+ SMBIOS_TABLE_TYPE32 *Type32;\r
+ SMBIOS_TABLE_TYPE33 *Type33;\r
+ SMBIOS_TABLE_TYPE34 *Type34;\r
+ SMBIOS_TABLE_TYPE35 *Type35;\r
+ SMBIOS_TABLE_TYPE36 *Type36;\r
+ SMBIOS_TABLE_TYPE37 *Type37;\r
+ SMBIOS_TABLE_TYPE38 *Type38;\r
+ SMBIOS_TABLE_TYPE39 *Type39;\r
+ SMBIOS_TABLE_TYPE40 *Type40;\r
+ SMBIOS_TABLE_TYPE41 *Type41;\r
+ SMBIOS_TABLE_TYPE42 *Type42;\r
+ SMBIOS_TABLE_TYPE43 *Type43;\r
+ SMBIOS_TABLE_TYPE44 *Type44;\r
+ SMBIOS_TABLE_TYPE126 *Type126;\r
+ SMBIOS_TABLE_TYPE127 *Type127;\r
+ UINT8 *Raw;\r
} SMBIOS_STRUCTURE_POINTER;\r
\r
#pragma pack()\r
#ifndef _SMBUS_H_\r
#define _SMBUS_H_\r
\r
-\r
///\r
/// UDID of SMBUS device.\r
///\r
typedef struct {\r
- UINT32 VendorSpecificId;\r
- UINT16 SubsystemDeviceId;\r
- UINT16 SubsystemVendorId;\r
- UINT16 Interface;\r
- UINT16 DeviceId;\r
- UINT16 VendorId;\r
- UINT8 VendorRevision;\r
- UINT8 DeviceCapabilities;\r
+ UINT32 VendorSpecificId;\r
+ UINT16 SubsystemDeviceId;\r
+ UINT16 SubsystemVendorId;\r
+ UINT16 Interface;\r
+ UINT16 DeviceId;\r
+ UINT16 VendorId;\r
+ UINT8 VendorRevision;\r
+ UINT8 DeviceCapabilities;\r
} EFI_SMBUS_UDID;\r
\r
///\r
///\r
/// The SMBUS hardware address to which the SMBUS device is preassigned or allocated.\r
///\r
- UINTN SmbusDeviceAddress : 7;\r
+ UINTN SmbusDeviceAddress : 7;\r
} EFI_SMBUS_DEVICE_ADDRESS;\r
\r
typedef struct {\r
/// The SMBUS hardware address to which the SMBUS device is preassigned or\r
/// allocated. Type EFI_SMBUS_DEVICE_ADDRESS is defined in EFI_PEI_SMBUS2_PPI.Execute().\r
///\r
- EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;\r
+ EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;\r
///\r
/// The SMBUS Unique Device Identifier (UDID) as defined in EFI_SMBUS_UDID.\r
/// Type EFI_SMBUS_UDID is defined in EFI_PEI_SMBUS2_PPI.ArpDevice().\r
///\r
- EFI_SMBUS_UDID SmbusDeviceUdid;\r
+ EFI_SMBUS_UDID SmbusDeviceUdid;\r
} EFI_SMBUS_DEVICE_MAP;\r
\r
///\r
///\r
/// EFI_SMBUS_DEVICE_COMMAND\r
///\r
-typedef UINTN EFI_SMBUS_DEVICE_COMMAND;\r
+typedef UINTN EFI_SMBUS_DEVICE_COMMAND;\r
\r
#endif\r
-\r
\r
**/\r
\r
-\r
#ifndef __SPDM_H__\r
#define __SPDM_H__\r
\r
///\r
/// SPDM response code\r
///\r
-#define SPDM_DIGESTS 0x01\r
-#define SPDM_CERTIFICATE 0x02\r
-#define SPDM_CHALLENGE_AUTH 0x03\r
-#define SPDM_VERSION 0x04\r
-#define SPDM_MEASUREMENTS 0x60\r
-#define SPDM_CAPABILITIES 0x61\r
-#define SPDM_SET_CERT_RESPONSE 0x62\r
-#define SPDM_ALGORITHMS 0x63\r
-#define SPDM_ERROR 0x7F\r
+#define SPDM_DIGESTS 0x01\r
+#define SPDM_CERTIFICATE 0x02\r
+#define SPDM_CHALLENGE_AUTH 0x03\r
+#define SPDM_VERSION 0x04\r
+#define SPDM_MEASUREMENTS 0x60\r
+#define SPDM_CAPABILITIES 0x61\r
+#define SPDM_SET_CERT_RESPONSE 0x62\r
+#define SPDM_ALGORITHMS 0x63\r
+#define SPDM_ERROR 0x7F\r
///\r
/// SPDM request code\r
///\r
/// SPDM message header\r
///\r
typedef struct {\r
- UINT8 SPDMVersion;\r
- UINT8 RequestResponseCode;\r
- UINT8 Param1;\r
- UINT8 Param2;\r
+ UINT8 SPDMVersion;\r
+ UINT8 RequestResponseCode;\r
+ UINT8 Param1;\r
+ UINT8 Param2;\r
} SPDM_MESSAGE_HEADER;\r
\r
#define SPDM_MESSAGE_VERSION 0x10\r
/// SPDM GET_VERSION request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
+ SPDM_MESSAGE_HEADER Header;\r
} SPDM_GET_VERSION_REQUEST;\r
\r
///\r
/// SPDM GET_VERSION response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT8 Reserved;\r
- UINT8 VersionNumberEntryCount;\r
-//SPDM_VERSION_NUMBER VersionNumberEntry[VersionNumberEntryCount];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT8 Reserved;\r
+ UINT8 VersionNumberEntryCount;\r
+ // SPDM_VERSION_NUMBER VersionNumberEntry[VersionNumberEntryCount];\r
} SPDM_VERSION_RESPONSE;\r
\r
///\r
/// SPDM VERSION structure\r
///\r
typedef struct {\r
- UINT16 Alpha:4;\r
- UINT16 UpdateVersionNumber:4;\r
- UINT16 MinorVersion:4;\r
- UINT16 MajorVersion:4;\r
+ UINT16 Alpha : 4;\r
+ UINT16 UpdateVersionNumber : 4;\r
+ UINT16 MinorVersion : 4;\r
+ UINT16 MajorVersion : 4;\r
} SPDM_VERSION_NUMBER;\r
\r
///\r
/// SPDM GET_CAPABILITIES request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
+ SPDM_MESSAGE_HEADER Header;\r
} SPDM_GET_CAPABILITIES_REQUEST;\r
\r
///\r
/// SPDM GET_CAPABILITIES response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT8 Reserved;\r
- UINT8 CTExponent;\r
- UINT16 Reserved2;\r
- UINT32 Flags;\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT8 Reserved;\r
+ UINT8 CTExponent;\r
+ UINT16 Reserved2;\r
+ UINT32 Flags;\r
} SPDM_CAPABILITIES_RESPONSE;\r
\r
///\r
/// SPDM GET_CAPABILITIES response Flags\r
///\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP BIT0\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP BIT1\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP BIT2\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG BIT3\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4\r
-#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP BIT5\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP BIT0\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP BIT1\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP BIT2\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP (BIT3 | BIT4)\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG BIT3\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG BIT4\r
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP BIT5\r
\r
///\r
/// SPDM NEGOTIATE_ALGORITHMS request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT16 Length;\r
- UINT8 MeasurementSpecification;\r
- UINT8 Reserved;\r
- UINT32 BaseAsymAlgo;\r
- UINT32 BaseHashAlgo;\r
- UINT8 Reserved2[12];\r
- UINT8 ExtAsymCount;\r
- UINT8 ExtHashCount;\r
- UINT16 Reserved3;\r
-//UINT32 ExtAsym[ExtAsymCount];\r
-//UINT32 ExtHash[ExtHashCount];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT16 Length;\r
+ UINT8 MeasurementSpecification;\r
+ UINT8 Reserved;\r
+ UINT32 BaseAsymAlgo;\r
+ UINT32 BaseHashAlgo;\r
+ UINT8 Reserved2[12];\r
+ UINT8 ExtAsymCount;\r
+ UINT8 ExtHashCount;\r
+ UINT16 Reserved3;\r
+ // UINT32 ExtAsym[ExtAsymCount];\r
+ // UINT32 ExtHash[ExtHashCount];\r
} SPDM_NEGOTIATE_ALGORITHMS_REQUEST;\r
\r
///\r
/// SPDM NEGOTIATE_ALGORITHMS request BaseAsymAlgo\r
///\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 BIT0\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 BIT1\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 BIT2\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 BIT3\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 BIT5\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 BIT6\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 BIT7\r
-#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 BIT8\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048 BIT0\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048 BIT1\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072 BIT2\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072 BIT3\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256 BIT4\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096 BIT5\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096 BIT6\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384 BIT7\r
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521 BIT8\r
\r
///\r
/// SPDM NEGOTIATE_ALGORITHMS request BaseHashAlgo\r
///\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 BIT0\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 BIT1\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 BIT2\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 BIT3\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4\r
-#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 BIT5\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256 BIT0\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384 BIT1\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512 BIT2\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256 BIT3\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384 BIT4\r
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512 BIT5\r
\r
///\r
/// SPDM NEGOTIATE_ALGORITHMS response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT16 Length;\r
- UINT8 MeasurementSpecificationSel;\r
- UINT8 Reserved;\r
- UINT32 MeasurementHashAlgo;\r
- UINT32 BaseAsymSel;\r
- UINT32 BaseHashSel;\r
- UINT8 Reserved2[12];\r
- UINT8 ExtAsymSelCount;\r
- UINT8 ExtHashSelCount;\r
- UINT16 Reserved3;\r
-//UINT32 ExtAsymSel[ExtAsymSelCount];\r
-//UINT32 ExtHashSel[ExtHashSelCount];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT16 Length;\r
+ UINT8 MeasurementSpecificationSel;\r
+ UINT8 Reserved;\r
+ UINT32 MeasurementHashAlgo;\r
+ UINT32 BaseAsymSel;\r
+ UINT32 BaseHashSel;\r
+ UINT8 Reserved2[12];\r
+ UINT8 ExtAsymSelCount;\r
+ UINT8 ExtHashSelCount;\r
+ UINT16 Reserved3;\r
+ // UINT32 ExtAsymSel[ExtAsymSelCount];\r
+ // UINT32 ExtHashSel[ExtHashSelCount];\r
} SPDM_ALGORITHMS_RESPONSE;\r
\r
///\r
/// SPDM NEGOTIATE_ALGORITHMS response MeasurementHashAlgo\r
///\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 BIT1\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 BIT2\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 BIT3\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 BIT5\r
-#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 BIT6\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256 BIT1\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384 BIT2\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512 BIT3\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256 BIT4\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384 BIT5\r
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512 BIT6\r
\r
///\r
/// SPDM GET_DIGESTS request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
+ SPDM_MESSAGE_HEADER Header;\r
} SPDM_GET_DIGESTS_REQUEST;\r
\r
///\r
/// SPDM GET_DIGESTS response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
-//UINT8 Digest[DigestSize];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ // UINT8 Digest[DigestSize];\r
} SPDM_DIGESTS_RESPONSE;\r
\r
///\r
/// SPDM GET_DIGESTS request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT16 Offset;\r
- UINT16 Length;\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT16 Offset;\r
+ UINT16 Length;\r
} SPDM_GET_CERTIFICATE_REQUEST;\r
\r
///\r
/// SPDM GET_DIGESTS response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT16 PortionLength;\r
- UINT16 RemainderLength;\r
-//UINT8 CertChain[CertChainSize];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT16 PortionLength;\r
+ UINT16 RemainderLength;\r
+ // UINT8 CertChain[CertChainSize];\r
} SPDM_CERTIFICATE_RESPONSE;\r
\r
///\r
/// SPDM CHALLENGE request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT8 Nonce[32];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT8 Nonce[32];\r
} SPDM_CHALLENGE_REQUEST;\r
\r
///\r
/// SPDM CHALLENGE response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
-//UINT8 CertChainHash[DigestSize];\r
-//UINT8 Nonce[32];\r
-//UINT8 MeasurementSummaryHash[DigestSize];\r
-//UINT16 OpaqueLength;\r
-//UINT8 OpaqueData[OpaqueLength];\r
-//UINT8 Signature[KeySize];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ // UINT8 CertChainHash[DigestSize];\r
+ // UINT8 Nonce[32];\r
+ // UINT8 MeasurementSummaryHash[DigestSize];\r
+ // UINT16 OpaqueLength;\r
+ // UINT8 OpaqueData[OpaqueLength];\r
+ // UINT8 Signature[KeySize];\r
} SPDM_CHALLENGE_AUTH_RESPONSE;\r
\r
///\r
/// SPDM GET_MEASUREMENTS request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT8 Nonce[32];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT8 Nonce[32];\r
} SPDM_GET_MEASUREMENTS_REQUEST;\r
\r
///\r
/// SPDM MEASUREMENTS block common header\r
///\r
typedef struct {\r
- UINT8 Index;\r
- UINT8 MeasurementSpecification;\r
- UINT16 MeasurementSize;\r
-//UINT8 Measurement[MeasurementSize];\r
+ UINT8 Index;\r
+ UINT8 MeasurementSpecification;\r
+ UINT16 MeasurementSize;\r
+ // UINT8 Measurement[MeasurementSize];\r
} SPDM_MEASUREMENT_BLOCK_COMMON_HEADER;\r
\r
-#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0\r
+#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0\r
\r
///\r
/// SPDM MEASUREMENTS block DMTF header\r
///\r
typedef struct {\r
- UINT8 DMTFSpecMeasurementValueType;\r
- UINT16 DMTFSpecMeasurementValueSize;\r
-//UINT8 DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize];\r
+ UINT8 DMTFSpecMeasurementValueType;\r
+ UINT16 DMTFSpecMeasurementValueSize;\r
+ // UINT8 DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize];\r
} SPDM_MEASUREMENT_BLOCK_DMTF_HEADER;\r
\r
///\r
/// SPDM GET_MEASUREMENTS response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
- UINT8 NumberOfBlocks;\r
- UINT8 MeasurementRecordLength[3];\r
-//UINT8 MeasurementRecord[MeasurementRecordLength];\r
-//UINT8 Nonce[32];\r
-//UINT16 OpaqueLength;\r
-//UINT8 OpaqueData[OpaqueLength];\r
-//UINT8 Signature[KeySize];\r
+ SPDM_MESSAGE_HEADER Header;\r
+ UINT8 NumberOfBlocks;\r
+ UINT8 MeasurementRecordLength[3];\r
+ // UINT8 MeasurementRecord[MeasurementRecordLength];\r
+ // UINT8 Nonce[32];\r
+ // UINT16 OpaqueLength;\r
+ // UINT8 OpaqueData[OpaqueLength];\r
+ // UINT8 Signature[KeySize];\r
} SPDM_MEASUREMENTS_RESPONSE;\r
\r
///\r
/// SPDM ERROR response\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
+ SPDM_MESSAGE_HEADER Header;\r
// Param1 == Error Code\r
// Param2 == Error Data\r
-//UINT8 ExtendedErrorData[];\r
+ // UINT8 ExtendedErrorData[];\r
} SPDM_ERROR_RESPONSE;\r
\r
///\r
/// SPDM RESPONSE_IF_READY request\r
///\r
typedef struct {\r
- SPDM_MESSAGE_HEADER Header;\r
+ SPDM_MESSAGE_HEADER Header;\r
// Param1 == RequestCode\r
// Param2 == Token\r
} SPDM_RESPONSE_IF_READY_REQUEST;\r
#pragma pack()\r
\r
#endif\r
-\r
//\r
// TCG PP definition for physical presence ACPI function\r
//\r
-#define TCG_ACPI_FUNCTION_GET_PHYSICAL_PRESENCE_INTERFACE_VERSION 1\r
-#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS 2\r
-#define TCG_ACPI_FUNCTION_GET_PENDING_REQUEST_BY_OS 3\r
-#define TCG_ACPI_FUNCTION_GET_PLATFORM_ACTION_TO_TRANSITION_TO_BIOS 4\r
-#define TCG_ACPI_FUNCTION_RETURN_REQUEST_RESPONSE_TO_OS 5\r
-#define TCG_ACPI_FUNCTION_SUBMIT_PREFERRED_USER_LANGUAGE 6\r
-#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS_2 7\r
-#define TCG_ACPI_FUNCTION_GET_USER_CONFIRMATION_STATUS_FOR_REQUEST 8\r
+#define TCG_ACPI_FUNCTION_GET_PHYSICAL_PRESENCE_INTERFACE_VERSION 1\r
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS 2\r
+#define TCG_ACPI_FUNCTION_GET_PENDING_REQUEST_BY_OS 3\r
+#define TCG_ACPI_FUNCTION_GET_PLATFORM_ACTION_TO_TRANSITION_TO_BIOS 4\r
+#define TCG_ACPI_FUNCTION_RETURN_REQUEST_RESPONSE_TO_OS 5\r
+#define TCG_ACPI_FUNCTION_SUBMIT_PREFERRED_USER_LANGUAGE 6\r
+#define TCG_ACPI_FUNCTION_SUBMIT_REQUEST_TO_BIOS_2 7\r
+#define TCG_ACPI_FUNCTION_GET_USER_CONFIRMATION_STATUS_FOR_REQUEST 8\r
\r
//\r
// TCG PP definition for TPM Operation Response to OS Environment\r
//\r
-#define TCG_PP_OPERATION_RESPONSE_SUCCESS 0x0\r
-#define TCG_PP_OPERATION_RESPONSE_USER_ABORT 0xFFFFFFF0\r
-#define TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE 0xFFFFFFF1\r
+#define TCG_PP_OPERATION_RESPONSE_SUCCESS 0x0\r
+#define TCG_PP_OPERATION_RESPONSE_USER_ABORT 0xFFFFFFF0\r
+#define TCG_PP_OPERATION_RESPONSE_BIOS_FAILURE 0xFFFFFFF1\r
\r
//\r
// TCG PP definition of return code for Return TPM Operation Response to OS Environment\r
//\r
-#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS 0\r
-#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_FAILURE 1\r
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_SUCCESS 0\r
+#define TCG_PP_RETURN_TPM_OPERATION_RESPONSE_FAILURE 1\r
\r
//\r
// TCG PP definition of return code for Submit TPM Request to Pre-OS Environment\r
// and Submit TPM Request to Pre-OS Environment 2\r
//\r
-#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS 0\r
-#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED 1\r
-#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE 2\r
-#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_BLOCKED_BY_BIOS_SETTINGS 3\r
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_SUCCESS 0\r
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_NOT_IMPLEMENTED 1\r
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_GENERAL_FAILURE 2\r
+#define TCG_PP_SUBMIT_REQUEST_TO_PREOS_BLOCKED_BY_BIOS_SETTINGS 3\r
\r
//\r
// TCG PP definition of return code for Get User Confirmation Status for Operation\r
//\r
-#define TCG_PP_GET_USER_CONFIRMATION_NOT_IMPLEMENTED 0\r
-#define TCG_PP_GET_USER_CONFIRMATION_BIOS_ONLY 1\r
-#define TCG_PP_GET_USER_CONFIRMATION_BLOCKED_BY_BIOS_CONFIGURATION 2\r
-#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_REQUIRED 3\r
-#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_NOT_REQUIRED 4\r
+#define TCG_PP_GET_USER_CONFIRMATION_NOT_IMPLEMENTED 0\r
+#define TCG_PP_GET_USER_CONFIRMATION_BIOS_ONLY 1\r
+#define TCG_PP_GET_USER_CONFIRMATION_BLOCKED_BY_BIOS_CONFIGURATION 2\r
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_REQUIRED 3\r
+#define TCG_PP_GET_USER_CONFIRMATION_ALLOWED_AND_PPUSER_NOT_REQUIRED 4\r
\r
//\r
// TCG PP definition of physical presence operation actions for TPM12\r
//\r
-#define TCG_PHYSICAL_PRESENCE_NO_ACTION 0\r
-#define TCG_PHYSICAL_PRESENCE_ENABLE 1\r
-#define TCG_PHYSICAL_PRESENCE_DISABLE 2\r
-#define TCG_PHYSICAL_PRESENCE_ACTIVATE 3\r
-#define TCG_PHYSICAL_PRESENCE_DEACTIVATE 4\r
-#define TCG_PHYSICAL_PRESENCE_CLEAR 5\r
-#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE 6\r
-#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE 7\r
-#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_TRUE 8\r
-#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_FALSE 9\r
-#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_OWNER_TRUE 10\r
-#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE_OWNER_FALSE 11\r
-#define TCG_PHYSICAL_PRESENCE_DEFERRED_PP_UNOWNERED_FIELD_UPGRADE 12\r
-#define TCG_PHYSICAL_PRESENCE_SET_OPERATOR_AUTH 13\r
-#define TCG_PHYSICAL_PRESENCE_CLEAR_ENABLE_ACTIVATE 14\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_FALSE 15\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_TRUE 16\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE 17\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE 18\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_FALSE 19\r
-#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_TRUE 20\r
-#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR 21\r
-#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE 22\r
+#define TCG_PHYSICAL_PRESENCE_NO_ACTION 0\r
+#define TCG_PHYSICAL_PRESENCE_ENABLE 1\r
+#define TCG_PHYSICAL_PRESENCE_DISABLE 2\r
+#define TCG_PHYSICAL_PRESENCE_ACTIVATE 3\r
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE 4\r
+#define TCG_PHYSICAL_PRESENCE_CLEAR 5\r
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE 6\r
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE 7\r
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_TRUE 8\r
+#define TCG_PHYSICAL_PRESENCE_SET_OWNER_INSTALL_FALSE 9\r
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_OWNER_TRUE 10\r
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE_OWNER_FALSE 11\r
+#define TCG_PHYSICAL_PRESENCE_DEFERRED_PP_UNOWNERED_FIELD_UPGRADE 12\r
+#define TCG_PHYSICAL_PRESENCE_SET_OPERATOR_AUTH 13\r
+#define TCG_PHYSICAL_PRESENCE_CLEAR_ENABLE_ACTIVATE 14\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_FALSE 15\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_PROVISION_TRUE 16\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_FALSE 17\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_CLEAR_TRUE 18\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_FALSE 19\r
+#define TCG_PHYSICAL_PRESENCE_SET_NO_PPI_MAINTENANCE_TRUE 20\r
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR 21\r
+#define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE_CLEAR_ENABLE_ACTIVATE 22\r
\r
-#define TCG_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128\r
+#define TCG_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128\r
\r
//\r
// TCG PP definition of physical presence operation actions for TPM2\r
//\r
-#define TCG2_PHYSICAL_PRESENCE_NO_ACTION 0\r
-#define TCG2_PHYSICAL_PRESENCE_ENABLE 1\r
-#define TCG2_PHYSICAL_PRESENCE_DISABLE 2\r
-#define TCG2_PHYSICAL_PRESENCE_CLEAR 5\r
-#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR 14\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18\r
-#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_2 21\r
-#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_3 22\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS 23\r
-#define TCG2_PHYSICAL_PRESENCE_CHANGE_EPS 24\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31\r
-#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32\r
-#define TCG2_PHYSICAL_PRESENCE_LOG_ALL_DIGESTS 33\r
-#define TCG2_PHYSICAL_PRESENCE_DISABLE_ENDORSEMENT_ENABLE_STORAGE_HIERARCHY 34\r
-#define TCG2_PHYSICAL_PRESENCE_NO_ACTION_MAX 34\r
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION 0\r
+#define TCG2_PHYSICAL_PRESENCE_ENABLE 1\r
+#define TCG2_PHYSICAL_PRESENCE_DISABLE 2\r
+#define TCG2_PHYSICAL_PRESENCE_CLEAR 5\r
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR 14\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18\r
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_2 21\r
+#define TCG2_PHYSICAL_PRESENCE_ENABLE_CLEAR_3 22\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PCR_BANKS 23\r
+#define TCG2_PHYSICAL_PRESENCE_CHANGE_EPS 24\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31\r
+#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32\r
+#define TCG2_PHYSICAL_PRESENCE_LOG_ALL_DIGESTS 33\r
+#define TCG2_PHYSICAL_PRESENCE_DISABLE_ENDORSEMENT_ENABLE_STORAGE_HIERARCHY 34\r
+#define TCG2_PHYSICAL_PRESENCE_NO_ACTION_MAX 34\r
\r
//\r
// TCG PP definition of physical presence operation actions for storage management\r
#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_TRUE 100\r
#define TCG2_PHYSICAL_PRESENCE_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FUNC_FALSE 101\r
\r
-#define TCG2_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128\r
+#define TCG2_PHYSICAL_PRESENCE_VENDOR_SPECIFIC_OPERATION 128\r
\r
#endif\r
/// UID in host native byte order\r
typedef UINT64 TCG_UID;\r
\r
-#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TCG_UID)( \\r
+#define TCG_TO_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TCG_UID)(\\r
(UINT64)(b0) | \\r
((UINT64)(b1) << 8) | \\r
((UINT64)(b2) << 16) | \\r
((UINT64)(b7) << 56))\r
\r
typedef struct {\r
- UINT32 ReservedBE;\r
- UINT16 ComIDBE;\r
- UINT16 ComIDExtensionBE;\r
- UINT32 OutstandingDataBE;\r
- UINT32 MinTransferBE;\r
- UINT32 LengthBE;\r
- UINT8 Payload[0];\r
+ UINT32 ReservedBE;\r
+ UINT16 ComIDBE;\r
+ UINT16 ComIDExtensionBE;\r
+ UINT32 OutstandingDataBE;\r
+ UINT32 MinTransferBE;\r
+ UINT32 LengthBE;\r
+ UINT8 Payload[0];\r
} TCG_COM_PACKET;\r
\r
typedef struct {\r
- UINT32 TperSessionNumberBE;\r
- UINT32 HostSessionNumberBE;\r
- UINT32 SequenceNumberBE;\r
- UINT16 ReservedBE;\r
- UINT16 AckTypeBE;\r
- UINT32 AcknowledgementBE;\r
- UINT32 LengthBE;\r
- UINT8 Payload[0];\r
+ UINT32 TperSessionNumberBE;\r
+ UINT32 HostSessionNumberBE;\r
+ UINT32 SequenceNumberBE;\r
+ UINT16 ReservedBE;\r
+ UINT16 AckTypeBE;\r
+ UINT32 AcknowledgementBE;\r
+ UINT32 LengthBE;\r
+ UINT8 Payload[0];\r
} TCG_PACKET;\r
\r
-#define TCG_SUBPACKET_ALIGNMENT 4 // 4-byte alignment per spec\r
+#define TCG_SUBPACKET_ALIGNMENT 4// 4-byte alignment per spec\r
\r
typedef struct {\r
- UINT8 ReservedBE[6];\r
- UINT16 KindBE;\r
- UINT32 LengthBE;\r
- UINT8 Payload[0];\r
+ UINT8 ReservedBE[6];\r
+ UINT16 KindBE;\r
+ UINT32 LengthBE;\r
+ UINT8 Payload[0];\r
} TCG_SUB_PACKET;\r
\r
-#define SUBPACKET_KIND_DATA 0x0000\r
-#define SUBPACKET_KIND_CREDIT_CONTROL 0x8001\r
+#define SUBPACKET_KIND_DATA 0x0000\r
+#define SUBPACKET_KIND_CREDIT_CONTROL 0x8001\r
\r
-#define TCG_ATOM_TYPE_INTEGER 0x0\r
-#define TCG_ATOM_TYPE_BYTE 0x1\r
+#define TCG_ATOM_TYPE_INTEGER 0x0\r
+#define TCG_ATOM_TYPE_BYTE 0x1\r
typedef struct {\r
- UINT8 Data : 6;\r
- UINT8 Sign : 1;\r
- UINT8 IsZero : 1;\r
+ UINT8 Data : 6;\r
+ UINT8 Sign : 1;\r
+ UINT8 IsZero : 1;\r
} TCG_TINY_ATOM_BITS;\r
\r
typedef union {\r
- UINT8 Raw;\r
- TCG_TINY_ATOM_BITS TinyAtomBits;\r
+ UINT8 Raw;\r
+ TCG_TINY_ATOM_BITS TinyAtomBits;\r
} TCG_SIMPLE_TOKEN_TINY_ATOM;\r
\r
-\r
typedef struct {\r
- UINT8 Length : 4;\r
- UINT8 SignOrCont : 1;\r
- UINT8 ByteOrInt : 1;\r
- UINT8 IsZero : 1;\r
- UINT8 IsOne : 1;\r
+ UINT8 Length : 4;\r
+ UINT8 SignOrCont : 1;\r
+ UINT8 ByteOrInt : 1;\r
+ UINT8 IsZero : 1;\r
+ UINT8 IsOne : 1;\r
} TCG_SHORT_ATOM_BITS;\r
\r
typedef union {\r
- UINT8 RawHeader;\r
- TCG_SHORT_ATOM_BITS ShortAtomBits;\r
+ UINT8 RawHeader;\r
+ TCG_SHORT_ATOM_BITS ShortAtomBits;\r
} TCG_SIMPLE_TOKEN_SHORT_ATOM;\r
\r
-\r
-#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 0x8\r
-#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7\r
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 0x8\r
+#define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7\r
\r
typedef struct {\r
- UINT8 LengthHigh : 3;\r
- UINT8 SignOrCont : 1;\r
- UINT8 ByteOrInt : 1;\r
- UINT8 IsZero : 1;\r
- UINT8 IsOne1 : 1;\r
- UINT8 IsOne2 : 1;\r
- UINT8 LengthLow;\r
+ UINT8 LengthHigh : 3;\r
+ UINT8 SignOrCont : 1;\r
+ UINT8 ByteOrInt : 1;\r
+ UINT8 IsZero : 1;\r
+ UINT8 IsOne1 : 1;\r
+ UINT8 IsOne2 : 1;\r
+ UINT8 LengthLow;\r
} TCG_MEDIUM_ATOM_BITS;\r
\r
typedef union {\r
- UINT16 RawHeader;\r
- TCG_MEDIUM_ATOM_BITS MediumAtomBits;\r
+ UINT16 RawHeader;\r
+ TCG_MEDIUM_ATOM_BITS MediumAtomBits;\r
} TCG_SIMPLE_TOKEN_MEDIUM_ATOM;\r
\r
-\r
-#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16\r
-#define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8\r
+#define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16\r
+#define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8\r
\r
typedef struct {\r
- UINT8 SignOrCont : 1;\r
- UINT8 ByteOrInt : 1;\r
- UINT8 Reserved : 2;\r
- UINT8 IsZero : 1;\r
- UINT8 IsOne1 : 1;\r
- UINT8 IsOne2 : 1;\r
- UINT8 IsOne3 : 1;\r
- UINT8 LengthHigh;\r
- UINT8 LengthMid;\r
- UINT8 LengthLow;\r
+ UINT8 SignOrCont : 1;\r
+ UINT8 ByteOrInt : 1;\r
+ UINT8 Reserved : 2;\r
+ UINT8 IsZero : 1;\r
+ UINT8 IsOne1 : 1;\r
+ UINT8 IsOne2 : 1;\r
+ UINT8 IsOne3 : 1;\r
+ UINT8 LengthHigh;\r
+ UINT8 LengthMid;\r
+ UINT8 LengthLow;\r
} TCG_LONG_ATOM_BITS;\r
\r
typedef union {\r
- UINT32 RawHeader;\r
- TCG_LONG_ATOM_BITS LongAtomBits;\r
+ UINT32 RawHeader;\r
+ TCG_LONG_ATOM_BITS LongAtomBits;\r
} TCG_SIMPLE_TOKEN_LONG_ATOM;\r
\r
-\r
// TCG Core Spec v2 - Table 04 - Token Types\r
typedef enum {\r
TcgTokenTypeReserved,\r
#define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE 0x7FF\r
#define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE 0xFFFFFF\r
\r
-#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F\r
-#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F\r
-#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32\r
+#define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F\r
+#define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F\r
+#define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32\r
\r
// TOKEN TYPES\r
#define TCG_TOKEN_TINYATOM 0x00\r
#define TCG_TOKEN_STARTTRANSACTION 0xFB\r
#define TCG_TOKEN_ENDTRANSACTION 0xFC\r
// 0xFD - 0xFE TCG Reserved\r
-#define TCG_TOKEN_EMPTY 0xFF\r
+#define TCG_TOKEN_EMPTY 0xFF\r
\r
// CELLBLOCK reserved Names\r
-#define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00\r
-#define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01\r
-#define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02\r
-#define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03\r
-#define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04\r
+#define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00\r
+#define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01\r
+#define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02\r
+#define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03\r
+#define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04\r
\r
// METHOD STATUS CODES\r
-#define TCG_METHOD_STATUS_CODE_SUCCESS 0x00\r
-#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01\r
-#define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02\r
-#define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03\r
-#define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04\r
-#define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05\r
-#define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06\r
-#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07\r
-#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08\r
-#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09\r
-#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A\r
-#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C\r
-#define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D\r
-#define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E\r
-#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F\r
-#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10\r
-#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11\r
-#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12\r
-#define TCG_METHOD_STATUS_CODE_FAIL 0x3F\r
-\r
+#define TCG_METHOD_STATUS_CODE_SUCCESS 0x00\r
+#define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01\r
+#define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02\r
+#define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03\r
+#define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04\r
+#define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05\r
+#define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06\r
+#define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07\r
+#define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08\r
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09\r
+#define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A\r
+#define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C\r
+#define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D\r
+#define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E\r
+#define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F\r
+#define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10\r
+#define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11\r
+#define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12\r
+#define TCG_METHOD_STATUS_CODE_FAIL 0x3F\r
\r
// Feature Codes\r
#define TCG_FEATURE_INVALID (UINT16)0x0000\r
#define TCG_FEATURE_DATA_REMOVAL (UINT16)0x0404\r
\r
// ACE Expression values\r
-#define TCG_ACE_EXPRESSION_AND 0x0\r
-#define TCG_ACE_EXPRESSION_OR 0x1\r
+#define TCG_ACE_EXPRESSION_AND 0x0\r
+#define TCG_ACE_EXPRESSION_OR 0x1\r
\r
/****************************************************************************\r
TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)\r
ATA 8 Rev6a Table 68 7.57.6.2\r
****************************************************************************/\r
// Security Protocol IDs\r
-#define TCG_SECURITY_PROTOCOL_INFO 0x00\r
-#define TCG_OPAL_SECURITY_PROTOCOL_1 0x01\r
-#define TCG_OPAL_SECURITY_PROTOCOL_2 0x02\r
-#define TCG_SECURITY_PROTOCOL_TCG3 0x03\r
-#define TCG_SECURITY_PROTOCOL_TCG4 0x04\r
-#define TCG_SECURITY_PROTOCOL_TCG5 0x05\r
-#define TCG_SECURITY_PROTOCOL_TCG6 0x06\r
-#define TCG_SECURITY_PROTOCOL_CBCS 0x07\r
-#define TCG_SECURITY_PROTOCOL_TAPE_DATA 0x20\r
-#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21\r
-#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40\r
-#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI 0x41\r
-#define TCG_SECURITY_PROTOCOL_JEDEC_UFS 0xEC\r
-#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY 0xED\r
-#define TCG_SECURITY_PROTOCOL_IEEE_1667 0xEE\r
-#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF\r
+#define TCG_SECURITY_PROTOCOL_INFO 0x00\r
+#define TCG_OPAL_SECURITY_PROTOCOL_1 0x01\r
+#define TCG_OPAL_SECURITY_PROTOCOL_2 0x02\r
+#define TCG_SECURITY_PROTOCOL_TCG3 0x03\r
+#define TCG_SECURITY_PROTOCOL_TCG4 0x04\r
+#define TCG_SECURITY_PROTOCOL_TCG5 0x05\r
+#define TCG_SECURITY_PROTOCOL_TCG6 0x06\r
+#define TCG_SECURITY_PROTOCOL_CBCS 0x07\r
+#define TCG_SECURITY_PROTOCOL_TAPE_DATA 0x20\r
+#define TCG_SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21\r
+#define TCG_SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40\r
+#define TCG_SECURITY_PROTOCOL_IKEV2_SCSI 0x41\r
+#define TCG_SECURITY_PROTOCOL_JEDEC_UFS 0xEC\r
+#define TCG_SECURITY_PROTOCOL_SDCARD_SECURITY 0xED\r
+#define TCG_SECURITY_PROTOCOL_IEEE_1667 0xEE\r
+#define TCG_SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF\r
\r
// Security Protocol Specific IDs\r
-#define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000\r
-#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001\r
+#define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000\r
+#define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001\r
\r
-#define TCG_RESERVED_COMID 0x0000\r
+#define TCG_RESERVED_COMID 0x0000\r
\r
// Defined in TCG Storage Feature Set:Block SID Authentication spec,\r
// ComId used for BlockSid command is hardcode 0x0005.\r
-#define TCG_BLOCKSID_COMID 0x0005\r
+#define TCG_BLOCKSID_COMID 0x0005\r
\r
#pragma pack(1)\r
typedef struct {\r
- UINT8 Reserved[6];\r
- UINT16 ListLength_BE; // 6 - 7\r
- UINT8 List[504]; // 8...\r
+ UINT8 Reserved[6];\r
+ UINT16 ListLength_BE; // 6 - 7\r
+ UINT8 List[504]; // 8...\r
} TCG_SUPPORTED_SECURITY_PROTOCOLS;\r
\r
-\r
// Level 0 Discovery\r
typedef struct {\r
- UINT32 LengthBE; // number of valid bytes in discovery response, not including length field\r
- UINT16 VerMajorBE;\r
- UINT16 VerMinorBE;\r
- UINT8 Reserved[8];\r
- UINT8 VendorUnique[32];\r
+ UINT32 LengthBE; // number of valid bytes in discovery response, not including length field\r
+ UINT16 VerMajorBE;\r
+ UINT16 VerMinorBE;\r
+ UINT8 Reserved[8];\r
+ UINT8 VendorUnique[32];\r
} TCG_LEVEL0_DISCOVERY_HEADER;\r
\r
typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {\r
- UINT16 FeatureCode_BE;\r
- UINT8 Reserved : 4;\r
- UINT8 Version : 4;\r
- UINT8 Length; // length of feature dependent data in bytes\r
+ UINT16 FeatureCode_BE;\r
+ UINT8 Reserved : 4;\r
+ UINT8 Version : 4;\r
+ UINT8 Length; // length of feature dependent data in bytes\r
} TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;\r
\r
-\r
typedef struct {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT8 LockingSupported : 1;\r
- UINT8 LockingEnabled : 1; // means the locking security provider (SP) is enabled\r
- UINT8 Locked : 1; // means at least 1 locking range is enabled\r
- UINT8 MediaEncryption : 1;\r
- UINT8 MbrEnabled : 1;\r
- UINT8 MbrDone : 1;\r
- UINT8 Reserved : 2;\r
- UINT8 Reserved515[11];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT8 LockingSupported : 1;\r
+ UINT8 LockingEnabled : 1; // means the locking security provider (SP) is enabled\r
+ UINT8 Locked : 1; // means at least 1 locking range is enabled\r
+ UINT8 MediaEncryption : 1;\r
+ UINT8 MbrEnabled : 1;\r
+ UINT8 MbrDone : 1;\r
+ UINT8 Reserved : 2;\r
+ UINT8 Reserved515[11];\r
} TCG_LOCKING_FEATURE_DESCRIPTOR;\r
\r
typedef struct {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT8 SIDValueState : 1;\r
- UINT8 SIDBlockedState : 1;\r
- UINT8 Reserved4 : 6;\r
- UINT8 HardwareReset : 1;\r
- UINT8 Reserved5 : 7;\r
- UINT8 Reserved615[10];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT8 SIDValueState : 1;\r
+ UINT8 SIDBlockedState : 1;\r
+ UINT8 Reserved4 : 6;\r
+ UINT8 HardwareReset : 1;\r
+ UINT8 Reserved5 : 7;\r
+ UINT8 Reserved615[10];\r
} TCG_BLOCK_SID_FEATURE_DESCRIPTOR;\r
\r
-\r
typedef struct {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT8 SyncSupported : 1;\r
- UINT8 AsyncSupported : 1;\r
- UINT8 AckNakSupported : 1;\r
- UINT8 BufferMgmtSupported : 1;\r
- UINT8 StreamingSupported : 1;\r
- UINT8 Reserved4b5 : 1;\r
- UINT8 ComIdMgmtSupported : 1;\r
- UINT8 Reserved4b7 : 1;\r
- UINT8 Reserved515[11];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT8 SyncSupported : 1;\r
+ UINT8 AsyncSupported : 1;\r
+ UINT8 AckNakSupported : 1;\r
+ UINT8 BufferMgmtSupported : 1;\r
+ UINT8 StreamingSupported : 1;\r
+ UINT8 Reserved4b5 : 1;\r
+ UINT8 ComIdMgmtSupported : 1;\r
+ UINT8 Reserved4b7 : 1;\r
+ UINT8 Reserved515[11];\r
} TCG_TPER_FEATURE_DESCRIPTOR;\r
\r
#pragma pack()\r
\r
// Special Purpose UIDs\r
-#define TCG_UID_NULL TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)\r
-#define TCG_UID_THIS_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)\r
-#define TCG_UID_SMUID TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)\r
+#define TCG_UID_NULL TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)\r
+#define TCG_UID_THIS_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)\r
+#define TCG_UID_SMUID TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)\r
\r
// Session Manager Method UIDS\r
-#define TCG_UID_SM_PROPERTIES TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)\r
-#define TCG_UID_SM_START_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)\r
-#define TCG_UID_SM_SYNC_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)\r
-#define TCG_UID_SM_START_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)\r
-#define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)\r
-#define TCG_UID_SM_CLOSE_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)\r
+#define TCG_UID_SM_PROPERTIES TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)\r
+#define TCG_UID_SM_START_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)\r
+#define TCG_UID_SM_SYNC_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)\r
+#define TCG_UID_SM_START_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)\r
+#define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)\r
+#define TCG_UID_SM_CLOSE_SESSION TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)\r
\r
// MethodID UIDs\r
-#define TCG_UID_METHOD_DELETE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)\r
-#define TCG_UID_METHOD_CREATE_TABLE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)\r
-#define TCG_UID_METHOD_DELETE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)\r
-#define TCG_UID_METHOD_CREATE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)\r
-#define TCG_UID_METHOD_DELETE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)\r
-#define TCG_UID_METHOD_NEXT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)\r
-#define TCG_UID_METHOD_GET_FREE_SPACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)\r
-#define TCG_UID_METHOD_GET_FREE_ROWS TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)\r
-#define TCG_UID_METHOD_DELETE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)\r
-#define TCG_UID_METHOD_GET_ACL TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)\r
-#define TCG_UID_METHOD_ADD_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)\r
-#define TCG_UID_METHOD_REMOVE_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)\r
-#define TCG_UID_METHOD_GEN_KEY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)\r
-#define TCG_UID_METHOD_GET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)\r
-#define TCG_UID_METHOD_SET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)\r
-#define TCG_UID_METHOD_GET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)\r
-#define TCG_UID_METHOD_SET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)\r
-#define TCG_UID_METHOD_AUTHENTICATE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)\r
-#define TCG_UID_METHOD_ISSUE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)\r
-#define TCG_UID_METHOD_GET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)\r
-#define TCG_UID_METHOD_RESET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)\r
-#define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)\r
-#define TCG_UID_METHOD_SET_LAG_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)\r
-#define TCG_UID_METHOD_SET_CLOCK_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)\r
-#define TCG_UID_METHOD_SET_LAG_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)\r
-#define TCG_UID_METHOD_INCREMENT_COUNTER TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)\r
-#define TCG_UID_METHOD_RANDOM TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)\r
-#define TCG_UID_METHOD_SALT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)\r
-#define TCG_UID_METHOD_DECRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)\r
-#define TCG_UID_METHOD_DECRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)\r
-#define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)\r
-#define TCG_UID_METHOD_ENCRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)\r
-#define TCG_UID_METHOD_ENCRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)\r
-#define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)\r
-#define TCG_UID_METHOD_HMAC_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)\r
-#define TCG_UID_METHOD_HMAC TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)\r
-#define TCG_UID_METHOD_HMAC_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)\r
-#define TCG_UID_METHOD_HASH_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)\r
-#define TCG_UID_METHOD_HASH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)\r
-#define TCG_UID_METHOD_HASH_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)\r
-#define TCG_UID_METHOD_SIGN TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)\r
-#define TCG_UID_METHOD_VERIFY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)\r
-#define TCG_UID_METHOD_XOR TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)\r
-#define TCG_UID_METHOD_ADD_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)\r
-#define TCG_UID_METHOD_CREATE_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)\r
-#define TCG_UID_METHOD_CLEAR_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)\r
-#define TCG_UID_METHOD_FLUSH_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)\r
+#define TCG_UID_METHOD_DELETE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)\r
+#define TCG_UID_METHOD_CREATE_TABLE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)\r
+#define TCG_UID_METHOD_DELETE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)\r
+#define TCG_UID_METHOD_CREATE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)\r
+#define TCG_UID_METHOD_DELETE_ROW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)\r
+#define TCG_UID_METHOD_NEXT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)\r
+#define TCG_UID_METHOD_GET_FREE_SPACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)\r
+#define TCG_UID_METHOD_GET_FREE_ROWS TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)\r
+#define TCG_UID_METHOD_DELETE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)\r
+#define TCG_UID_METHOD_GET_ACL TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)\r
+#define TCG_UID_METHOD_ADD_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)\r
+#define TCG_UID_METHOD_REMOVE_ACE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)\r
+#define TCG_UID_METHOD_GEN_KEY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)\r
+#define TCG_UID_METHOD_GET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)\r
+#define TCG_UID_METHOD_SET_PACKAGE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)\r
+#define TCG_UID_METHOD_GET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)\r
+#define TCG_UID_METHOD_SET TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)\r
+#define TCG_UID_METHOD_AUTHENTICATE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)\r
+#define TCG_UID_METHOD_ISSUE_SP TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)\r
+#define TCG_UID_METHOD_GET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)\r
+#define TCG_UID_METHOD_RESET_CLOCK TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)\r
+#define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)\r
+#define TCG_UID_METHOD_SET_LAG_HIGH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)\r
+#define TCG_UID_METHOD_SET_CLOCK_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)\r
+#define TCG_UID_METHOD_SET_LAG_LOW TCG_TO_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)\r
+#define TCG_UID_METHOD_INCREMENT_COUNTER TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)\r
+#define TCG_UID_METHOD_RANDOM TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)\r
+#define TCG_UID_METHOD_SALT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)\r
+#define TCG_UID_METHOD_DECRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)\r
+#define TCG_UID_METHOD_DECRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)\r
+#define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)\r
+#define TCG_UID_METHOD_ENCRYPT_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)\r
+#define TCG_UID_METHOD_ENCRYPT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)\r
+#define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)\r
+#define TCG_UID_METHOD_HMAC_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)\r
+#define TCG_UID_METHOD_HMAC TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)\r
+#define TCG_UID_METHOD_HMAC_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)\r
+#define TCG_UID_METHOD_HASH_INIT TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)\r
+#define TCG_UID_METHOD_HASH TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)\r
+#define TCG_UID_METHOD_HASH_FINALIZE TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)\r
+#define TCG_UID_METHOD_SIGN TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)\r
+#define TCG_UID_METHOD_VERIFY TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)\r
+#define TCG_UID_METHOD_XOR TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)\r
+#define TCG_UID_METHOD_ADD_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)\r
+#define TCG_UID_METHOD_CREATE_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)\r
+#define TCG_UID_METHOD_CLEAR_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)\r
+#define TCG_UID_METHOD_FLUSH_LOG TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)\r
\r
#endif // TCG_H_\r
\r
#include <IndustryStandard/TcgStorageCore.h>\r
\r
-#define OPAL_UID_ADMIN_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x01)\r
-#define OPAL_UID_ADMIN_SP_C_PIN_MSID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x84, 0x02)\r
-#define OPAL_UID_ADMIN_SP_C_PIN_SID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x01)\r
-#define OPAL_UID_LOCKING_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02)\r
+#define OPAL_UID_ADMIN_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x01)\r
+#define OPAL_UID_ADMIN_SP_C_PIN_MSID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x84, 0x02)\r
+#define OPAL_UID_ADMIN_SP_C_PIN_SID TCG_TO_UID(0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x01)\r
+#define OPAL_UID_LOCKING_SP TCG_TO_UID(0x00, 0x00, 0x02, 0x05, 0x00, 0x00, 0x00, 0x02)\r
\r
// ADMIN_SP\r
// Authorities\r
-#define OPAL_ADMIN_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)\r
-#define OPAL_ADMIN_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)\r
-#define OPAL_ADMIN_SP_MAKERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03)\r
-#define OPAL_ADMIN_SP_SID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06)\r
-#define OPAL_ADMIN_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x01)\r
-#define OPAL_ADMIN_SP_PSID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0xFF, 0x01)\r
+#define OPAL_ADMIN_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)\r
+#define OPAL_ADMIN_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)\r
+#define OPAL_ADMIN_SP_MAKERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03)\r
+#define OPAL_ADMIN_SP_SID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06)\r
+#define OPAL_ADMIN_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x01)\r
+#define OPAL_ADMIN_SP_PSID_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0xFF, 0x01)\r
\r
-#define OPAL_ADMIN_SP_ACTIVATE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03)\r
-#define OPAL_ADMIN_SP_REVERT_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02)\r
+#define OPAL_ADMIN_SP_ACTIVATE_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03)\r
+#define OPAL_ADMIN_SP_REVERT_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02)\r
\r
// ADMIN_SP\r
// Data Removal mechanism\r
\r
// LOCKING SP\r
// Authorities\r
-#define OPAL_LOCKING_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)\r
-#define OPAL_LOCKING_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)\r
-#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01)\r
-#define OPAL_LOCKING_SP_USERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x00)\r
-#define OPAL_LOCKING_SP_USER1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01)\r
+#define OPAL_LOCKING_SP_ANYBODY_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x01)\r
+#define OPAL_LOCKING_SP_ADMINS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02)\r
+#define OPAL_LOCKING_SP_ADMIN1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x01, 0x00, 0x01)\r
+#define OPAL_LOCKING_SP_USERS_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x00)\r
+#define OPAL_LOCKING_SP_USER1_AUTHORITY TCG_TO_UID(0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x01)\r
\r
-#define OPAL_LOCKING_SP_REVERTSP_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11)\r
+#define OPAL_LOCKING_SP_REVERTSP_METHOD TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11)\r
\r
// C_PIN Table Rows\r
-#define OPAL_LOCKING_SP_C_PIN_ADMIN1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01 )\r
-#define OPAL_LOCKING_SP_C_PIN_USER1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x03, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_C_PIN_ADMIN1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x01, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_C_PIN_USER1 TCG_TO_UID( 0x00, 0x00, 0x00, 0x0B, 0x00, 0x03, 0x00, 0x01 )\r
\r
// Locking Table\r
-#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01 )\r
-#define OPAL_LOCKING_SP_LOCKING_RANGE1 TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x03, 0x00, 0x01 )\r
-\r
+#define OPAL_LOCKING_SP_LOCKING_GLOBALRANGE TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_LOCKING_RANGE1 TCG_TO_UID( 0x00, 0x00, 0x08, 0x02, 0x00, 0x03, 0x00, 0x01 )\r
\r
// LOCKING SP ACE Table Preconfiguration\r
-#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_GET_ALL TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xD0, 0x00 )\r
-#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_RDLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE0, 0x00 )\r
-#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_WRLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE8, 0x00 )\r
-\r
-#define OPAL_LOCKING_SP_ACE_K_AES_256_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB8, 0x00 )\r
-#define OPAL_LOCKING_SP_ACE_K_AES_128_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB0, 0x00 )\r
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_GET_ALL TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xD0, 0x00 )\r
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_RDLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE0, 0x00 )\r
+#define OPAL_LOCKING_SP_ACE_LOCKING_GLOBALRANGE_SET_WRLOCKED TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xE8, 0x00 )\r
\r
+#define OPAL_LOCKING_SP_ACE_K_AES_256_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB8, 0x00 )\r
+#define OPAL_LOCKING_SP_ACE_K_AES_128_GLOBALRANGE_GENKEY TCG_TO_UID( 0x00, 0x00, 0x00, 0x08, 0x00, 0x03, 0xB0, 0x00 )\r
\r
// LOCKING SP LockingInfo Table Preconfiguration\r
-#define OPAL_LOCKING_SP_LOCKING_INFO TCG_TO_UID( 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_LOCKING_INFO TCG_TO_UID( 0x00, 0x00, 0x08, 0x01, 0x00, 0x00, 0x00, 0x01 )\r
\r
-#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTREQUIRED_COL 0x7\r
-#define OPAL_LOCKING_SP_LOCKINGINFO_LOGICALBLOCKSIZE_COL 0x8\r
-#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTGRANULARITY_COL 0x9\r
-#define OPAL_LOCKING_SP_LOCKINGINFO_LOWESTALIGNEDLBA_COL 0xA\r
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTREQUIRED_COL 0x7\r
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOGICALBLOCKSIZE_COL 0x8\r
+#define OPAL_LOCKING_SP_LOCKINGINFO_ALIGNMENTGRANULARITY_COL 0x9\r
+#define OPAL_LOCKING_SP_LOCKINGINFO_LOWESTALIGNEDLBA_COL 0xA\r
\r
// K_AES_256 Table Preconfiguration\r
-#define OPAL_LOCKING_SP_K_AES_256_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x06, 0x00, 0x00, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_K_AES_256_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x06, 0x00, 0x00, 0x00, 0x01 )\r
\r
// K_AES_128 Table Preconfiguration\r
-#define OPAL_LOCKING_SP_K_AES_128_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01 )\r
+#define OPAL_LOCKING_SP_K_AES_128_GLOBALRANGE_KEY TCG_TO_UID( 0x00, 0x00, 0x08, 0x05, 0x00, 0x00, 0x00, 0x01 )\r
\r
// Minimum Properties that an Opal Compliant SD Shall support\r
-#define OPAL_MIN_MAX_COM_PACKET_SIZE 2048\r
-#define OPAL_MIN_MAX_REPONSE_COM_PACKET_SIZE 2048\r
-#define OPAL_MIN_MAX_PACKET_SIZE 2028\r
-#define OPAL_MIN_MAX_IND_TOKEN_SIZE 1992\r
-#define OPAL_MIN_MAX_PACKETS 1\r
-#define OPAL_MIN_MAX_SUBPACKETS 1\r
-#define OPAL_MIN_MAX_METHODS 1\r
-#define OPAL_MIN_MAX_SESSIONS 1\r
-#define OPAL_MIN_MAX_AUTHENTICATIONS 2\r
-#define OPAL_MIN_MAX_TRANSACTION_LIMIT 1\r
-\r
-#define OPAL_ADMIN_SP_PIN_COL 3\r
-#define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5\r
-#define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32\r
+#define OPAL_MIN_MAX_COM_PACKET_SIZE 2048\r
+#define OPAL_MIN_MAX_REPONSE_COM_PACKET_SIZE 2048\r
+#define OPAL_MIN_MAX_PACKET_SIZE 2028\r
+#define OPAL_MIN_MAX_IND_TOKEN_SIZE 1992\r
+#define OPAL_MIN_MAX_PACKETS 1\r
+#define OPAL_MIN_MAX_SUBPACKETS 1\r
+#define OPAL_MIN_MAX_METHODS 1\r
+#define OPAL_MIN_MAX_SESSIONS 1\r
+#define OPAL_MIN_MAX_AUTHENTICATIONS 2\r
+#define OPAL_MIN_MAX_TRANSACTION_LIMIT 1\r
+\r
+#define OPAL_ADMIN_SP_PIN_COL 3\r
+#define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5\r
+#define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32\r
\r
// Data Removal Mechanism column.\r
#define OPAL_ADMIN_SP_ACTIVE_DATA_REMOVAL_MECHANISM_COL 1\r
#pragma pack(1)\r
\r
typedef struct _OPAL_GEOMETRY_REPORTING_FEATURE {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT8 Reserved[8];\r
- UINT32 LogicalBlockSizeBE;\r
- UINT64 AlignmentGranularityBE;\r
- UINT64 LowestAlignedLBABE;\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT8 Reserved[8];\r
+ UINT32 LogicalBlockSizeBE;\r
+ UINT64 AlignmentGranularityBE;\r
+ UINT64 LowestAlignedLBABE;\r
} OPAL_GEOMETRY_REPORTING_FEATURE;\r
\r
typedef struct _OPAL_SINGLE_USER_MODE_FEATURE {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT32 NumLockingObjectsSupportedBE;\r
- UINT8 Any : 1;\r
- UINT8 All : 1;\r
- UINT8 Policy : 1;\r
- UINT8 Reserved : 5;\r
- UINT8 Reserved2[7];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT32 NumLockingObjectsSupportedBE;\r
+ UINT8 Any : 1;\r
+ UINT8 All : 1;\r
+ UINT8 Policy : 1;\r
+ UINT8 Reserved : 5;\r
+ UINT8 Reserved2[7];\r
} OPAL_SINGLE_USER_MODE_FEATURE;\r
\r
typedef struct _OPAL_DATASTORE_TABLE_FEATURE {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 Reserved;\r
- UINT16 MaxNumTablesBE;\r
- UINT32 MaxTotalSizeBE;\r
- UINT32 SizeAlignmentBE;\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 Reserved;\r
+ UINT16 MaxNumTablesBE;\r
+ UINT32 MaxTotalSizeBE;\r
+ UINT32 SizeAlignmentBE;\r
} OPAL_DATASTORE_TABLE_FEATURE;\r
\r
typedef struct _OPAL_SSCV1_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 BaseComdIdBE;\r
- UINT16 NumComIdsBE;\r
- UINT8 RangeCrossing : 1;\r
- UINT8 Reserved : 7;\r
- UINT8 Future[11];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 BaseComdIdBE;\r
+ UINT16 NumComIdsBE;\r
+ UINT8 RangeCrossing : 1;\r
+ UINT8 Reserved : 7;\r
+ UINT8 Future[11];\r
} OPAL_SSCV1_FEATURE_DESCRIPTOR;\r
\r
typedef struct _OPAL_SSCV2_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 BaseComdIdBE;\r
- UINT16 NumComIdsBE;\r
- UINT8 Reserved;\r
- UINT16 NumLockingSpAdminAuthoritiesSupportedBE;\r
- UINT16 NumLockingSpUserAuthoritiesSupportedBE;\r
- UINT8 InitialCPINSIDPIN;\r
- UINT8 CPINSIDPINRevertBehavior;\r
- UINT8 Future[5];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 BaseComdIdBE;\r
+ UINT16 NumComIdsBE;\r
+ UINT8 Reserved;\r
+ UINT16 NumLockingSpAdminAuthoritiesSupportedBE;\r
+ UINT16 NumLockingSpUserAuthoritiesSupportedBE;\r
+ UINT8 InitialCPINSIDPIN;\r
+ UINT8 CPINSIDPINRevertBehavior;\r
+ UINT8 Future[5];\r
} OPAL_SSCV2_FEATURE_DESCRIPTOR;\r
\r
typedef struct _OPAL_SSCLITE_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 BaseComdIdBE;\r
- UINT16 NumComIdsBE;\r
- UINT8 Reserved[5];\r
- UINT8 InitialCPINSIDPIN;\r
- UINT8 CPINSIDPINRevertBehavior;\r
- UINT8 Future[5];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 BaseComdIdBE;\r
+ UINT16 NumComIdsBE;\r
+ UINT8 Reserved[5];\r
+ UINT8 InitialCPINSIDPIN;\r
+ UINT8 CPINSIDPINRevertBehavior;\r
+ UINT8 Future[5];\r
} OPAL_SSCLITE_FEATURE_DESCRIPTOR;\r
\r
typedef struct _PYRITE_SSC_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 BaseComdIdBE;\r
- UINT16 NumComIdsBE;\r
- UINT8 Reserved[5];\r
- UINT8 InitialCPINSIDPIN;\r
- UINT8 CPINSIDPINRevertBehavior;\r
- UINT8 Future[5];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 BaseComdIdBE;\r
+ UINT16 NumComIdsBE;\r
+ UINT8 Reserved[5];\r
+ UINT8 InitialCPINSIDPIN;\r
+ UINT8 CPINSIDPINRevertBehavior;\r
+ UINT8 Future[5];\r
} PYRITE_SSC_FEATURE_DESCRIPTOR;\r
\r
typedef struct _PYRITE_SSCV2_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT16 BaseComdIdBE;\r
- UINT16 NumComIdsBE;\r
- UINT8 Reserved[5];\r
- UINT8 InitialCPINSIDPIN;\r
- UINT8 CPINSIDPINRevertBehavior;\r
- UINT8 Future[5];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT16 BaseComdIdBE;\r
+ UINT16 NumComIdsBE;\r
+ UINT8 Reserved[5];\r
+ UINT8 InitialCPINSIDPIN;\r
+ UINT8 CPINSIDPINRevertBehavior;\r
+ UINT8 Future[5];\r
} PYRITE_SSCV2_FEATURE_DESCRIPTOR;\r
\r
typedef struct _DATA_REMOVAL_FEATURE_DESCRIPTOR {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
- UINT8 Reserved;\r
- UINT8 OperationProcessing : 1;\r
- UINT8 Reserved2 : 7;\r
- UINT8 RemovalMechanism;\r
- UINT8 FormatBit0 : 1; // Data Removal Time Format for Bit 0\r
- UINT8 FormatBit1 : 1; // Data Removal Time Format for Bit 1\r
- UINT8 FormatBit2 : 1; // Data Removal Time Format for Bit 2\r
- UINT8 FormatBit3 : 1; // Data Removal Time Format for Bit 3\r
- UINT8 FormatBit4 : 1; // Data Removal Time Format for Bit 4\r
- UINT8 FormatBit5 : 1; // Data Removal Time Format for Bit 5\r
- UINT8 Reserved3 : 2;\r
- UINT16 TimeBit0; // Data Removal Time for Supported Data Removal Mechanism Bit 0\r
- UINT16 TimeBit1; // Data Removal Time for Supported Data Removal Mechanism Bit 1\r
- UINT16 TimeBit2; // Data Removal Time for Supported Data Removal Mechanism Bit 2\r
- UINT16 TimeBit3; // Data Removal Time for Supported Data Removal Mechanism Bit 3\r
- UINT16 TimeBit4; // Data Removal Time for Supported Data Removal Mechanism Bit 4\r
- UINT16 TimeBit5; // Data Removal Time for Supported Data Removal Mechanism Bit 5\r
- UINT8 Future[16];\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;\r
+ UINT8 Reserved;\r
+ UINT8 OperationProcessing : 1;\r
+ UINT8 Reserved2 : 7;\r
+ UINT8 RemovalMechanism;\r
+ UINT8 FormatBit0 : 1; // Data Removal Time Format for Bit 0\r
+ UINT8 FormatBit1 : 1; // Data Removal Time Format for Bit 1\r
+ UINT8 FormatBit2 : 1; // Data Removal Time Format for Bit 2\r
+ UINT8 FormatBit3 : 1; // Data Removal Time Format for Bit 3\r
+ UINT8 FormatBit4 : 1; // Data Removal Time Format for Bit 4\r
+ UINT8 FormatBit5 : 1; // Data Removal Time Format for Bit 5\r
+ UINT8 Reserved3 : 2;\r
+ UINT16 TimeBit0; // Data Removal Time for Supported Data Removal Mechanism Bit 0\r
+ UINT16 TimeBit1; // Data Removal Time for Supported Data Removal Mechanism Bit 1\r
+ UINT16 TimeBit2; // Data Removal Time for Supported Data Removal Mechanism Bit 2\r
+ UINT16 TimeBit3; // Data Removal Time for Supported Data Removal Mechanism Bit 3\r
+ UINT16 TimeBit4; // Data Removal Time for Supported Data Removal Mechanism Bit 4\r
+ UINT16 TimeBit5; // Data Removal Time for Supported Data Removal Mechanism Bit 5\r
+ UINT8 Future[16];\r
} DATA_REMOVAL_FEATURE_DESCRIPTOR;\r
\r
typedef union {\r
- TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER CommonHeader;\r
- TCG_TPER_FEATURE_DESCRIPTOR Tper;\r
- TCG_LOCKING_FEATURE_DESCRIPTOR Locking;\r
- OPAL_GEOMETRY_REPORTING_FEATURE Geometry;\r
- OPAL_SINGLE_USER_MODE_FEATURE SingleUser;\r
- OPAL_DATASTORE_TABLE_FEATURE DataStore;\r
- OPAL_SSCV1_FEATURE_DESCRIPTOR OpalSscV1;\r
- OPAL_SSCV2_FEATURE_DESCRIPTOR OpalSscV2;\r
- OPAL_SSCLITE_FEATURE_DESCRIPTOR OpalSscLite;\r
- PYRITE_SSC_FEATURE_DESCRIPTOR PyriteSsc;\r
- PYRITE_SSCV2_FEATURE_DESCRIPTOR PyriteSscV2;\r
- TCG_BLOCK_SID_FEATURE_DESCRIPTOR BlockSid;\r
- DATA_REMOVAL_FEATURE_DESCRIPTOR DataRemoval;\r
+ TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER CommonHeader;\r
+ TCG_TPER_FEATURE_DESCRIPTOR Tper;\r
+ TCG_LOCKING_FEATURE_DESCRIPTOR Locking;\r
+ OPAL_GEOMETRY_REPORTING_FEATURE Geometry;\r
+ OPAL_SINGLE_USER_MODE_FEATURE SingleUser;\r
+ OPAL_DATASTORE_TABLE_FEATURE DataStore;\r
+ OPAL_SSCV1_FEATURE_DESCRIPTOR OpalSscV1;\r
+ OPAL_SSCV2_FEATURE_DESCRIPTOR OpalSscV2;\r
+ OPAL_SSCLITE_FEATURE_DESCRIPTOR OpalSscLite;\r
+ PYRITE_SSC_FEATURE_DESCRIPTOR PyriteSsc;\r
+ PYRITE_SSCV2_FEATURE_DESCRIPTOR PyriteSscV2;\r
+ TCG_BLOCK_SID_FEATURE_DESCRIPTOR BlockSid;\r
+ DATA_REMOVAL_FEATURE_DESCRIPTOR DataRemoval;\r
} OPAL_LEVEL0_FEATURE_DESCRIPTOR;\r
\r
#pragma pack()\r
#pragma pack (1)\r
\r
typedef struct _EFI_TCG_CLIENT_ACPI_TABLE {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT16 PlatformClass;\r
- UINT32 Laml;\r
- UINT64 Lasa;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT16 PlatformClass;\r
+ UINT32 Laml;\r
+ UINT64 Lasa;\r
} EFI_TCG_CLIENT_ACPI_TABLE;\r
\r
typedef struct _EFI_TCG_SERVER_ACPI_TABLE {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT16 PlatformClass;\r
- UINT16 Reserved0;\r
- UINT64 Laml;\r
- UINT64 Lasa;\r
- UINT16 SpecRev;\r
- UINT8 DeviceFlags;\r
- UINT8 InterruptFlags;\r
- UINT8 Gpe;\r
- UINT8 Reserved1[3];\r
- UINT32 GlobalSysInt;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
- UINT32 Reserved2;\r
- EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ConfigAddress;\r
- UINT8 PciSegNum;\r
- UINT8 PciBusNum;\r
- UINT8 PciDevNum;\r
- UINT8 PciFuncNum;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT16 PlatformClass;\r
+ UINT16 Reserved0;\r
+ UINT64 Laml;\r
+ UINT64 Lasa;\r
+ UINT16 SpecRev;\r
+ UINT8 DeviceFlags;\r
+ UINT8 InterruptFlags;\r
+ UINT8 Gpe;\r
+ UINT8 Reserved1[3];\r
+ UINT32 GlobalSysInt;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;\r
+ UINT32 Reserved2;\r
+ EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE ConfigAddress;\r
+ UINT8 PciSegNum;\r
+ UINT8 PciBusNum;\r
+ UINT8 PciDevNum;\r
+ UINT8 PciFuncNum;\r
} EFI_TCG_SERVER_ACPI_TABLE;\r
\r
//\r
// TCG Platform Type based on TCG ACPI Specification Version 1.00\r
//\r
-#define TCG_PLATFORM_TYPE_CLIENT 0\r
-#define TCG_PLATFORM_TYPE_SERVER 1\r
+#define TCG_PLATFORM_TYPE_CLIENT 0\r
+#define TCG_PLATFORM_TYPE_SERVER 1\r
\r
#pragma pack ()\r
\r
///\r
/// TLS Cipher Suite, refers to A.5 of rfc-2246, rfc-4346 and rfc-5246.\r
///\r
-#define TLS_RSA_WITH_NULL_MD5 {0x00, 0x01}\r
-#define TLS_RSA_WITH_NULL_SHA {0x00, 0x02}\r
-#define TLS_RSA_WITH_RC4_128_MD5 {0x00, 0x04}\r
-#define TLS_RSA_WITH_RC4_128_SHA {0x00, 0x05}\r
-#define TLS_RSA_WITH_IDEA_CBC_SHA {0x00, 0x07}\r
-#define TLS_RSA_WITH_DES_CBC_SHA {0x00, 0x09}\r
-#define TLS_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x0A}\r
-#define TLS_DH_DSS_WITH_DES_CBC_SHA {0x00, 0x0C}\r
-#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x0D}\r
-#define TLS_DH_RSA_WITH_DES_CBC_SHA {0x00, 0x0F}\r
-#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x10}\r
-#define TLS_DHE_DSS_WITH_DES_CBC_SHA {0x00, 0x12}\r
-#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x13}\r
-#define TLS_DHE_RSA_WITH_DES_CBC_SHA {0x00, 0x15}\r
-#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x16}\r
-#define TLS_RSA_WITH_AES_128_CBC_SHA {0x00, 0x2F}\r
-#define TLS_DH_DSS_WITH_AES_128_CBC_SHA {0x00, 0x30}\r
-#define TLS_DH_RSA_WITH_AES_128_CBC_SHA {0x00, 0x31}\r
-#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA {0x00, 0x32}\r
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA {0x00, 0x33}\r
-#define TLS_RSA_WITH_AES_256_CBC_SHA {0x00, 0x35}\r
-#define TLS_DH_DSS_WITH_AES_256_CBC_SHA {0x00, 0x36}\r
-#define TLS_DH_RSA_WITH_AES_256_CBC_SHA {0x00, 0x37}\r
-#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA {0x00, 0x38}\r
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA {0x00, 0x39}\r
-#define TLS_RSA_WITH_NULL_SHA256 {0x00, 0x3B}\r
-#define TLS_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3C}\r
-#define TLS_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x3D}\r
-#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x3E}\r
-#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3F}\r
-#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x40}\r
-#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x67}\r
-#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x68}\r
-#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x69}\r
-#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x6A}\r
-#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x6B}\r
+#define TLS_RSA_WITH_NULL_MD5 {0x00, 0x01}\r
+#define TLS_RSA_WITH_NULL_SHA {0x00, 0x02}\r
+#define TLS_RSA_WITH_RC4_128_MD5 {0x00, 0x04}\r
+#define TLS_RSA_WITH_RC4_128_SHA {0x00, 0x05}\r
+#define TLS_RSA_WITH_IDEA_CBC_SHA {0x00, 0x07}\r
+#define TLS_RSA_WITH_DES_CBC_SHA {0x00, 0x09}\r
+#define TLS_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x0A}\r
+#define TLS_DH_DSS_WITH_DES_CBC_SHA {0x00, 0x0C}\r
+#define TLS_DH_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x0D}\r
+#define TLS_DH_RSA_WITH_DES_CBC_SHA {0x00, 0x0F}\r
+#define TLS_DH_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x10}\r
+#define TLS_DHE_DSS_WITH_DES_CBC_SHA {0x00, 0x12}\r
+#define TLS_DHE_DSS_WITH_3DES_EDE_CBC_SHA {0x00, 0x13}\r
+#define TLS_DHE_RSA_WITH_DES_CBC_SHA {0x00, 0x15}\r
+#define TLS_DHE_RSA_WITH_3DES_EDE_CBC_SHA {0x00, 0x16}\r
+#define TLS_RSA_WITH_AES_128_CBC_SHA {0x00, 0x2F}\r
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA {0x00, 0x30}\r
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA {0x00, 0x31}\r
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA {0x00, 0x32}\r
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA {0x00, 0x33}\r
+#define TLS_RSA_WITH_AES_256_CBC_SHA {0x00, 0x35}\r
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA {0x00, 0x36}\r
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA {0x00, 0x37}\r
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA {0x00, 0x38}\r
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA {0x00, 0x39}\r
+#define TLS_RSA_WITH_NULL_SHA256 {0x00, 0x3B}\r
+#define TLS_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3C}\r
+#define TLS_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x3D}\r
+#define TLS_DH_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x3E}\r
+#define TLS_DH_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x3F}\r
+#define TLS_DHE_DSS_WITH_AES_128_CBC_SHA256 {0x00, 0x40}\r
+#define TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 {0x00, 0x67}\r
+#define TLS_DH_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x68}\r
+#define TLS_DH_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x69}\r
+#define TLS_DHE_DSS_WITH_AES_256_CBC_SHA256 {0x00, 0x6A}\r
+#define TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 {0x00, 0x6B}\r
\r
///\r
/// TLS Version, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.\r
/// TLS Record Header, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.\r
///\r
typedef struct {\r
- UINT8 ContentType;\r
- EFI_TLS_VERSION Version;\r
- UINT16 Length;\r
+ UINT8 ContentType;\r
+ EFI_TLS_VERSION Version;\r
+ UINT16 Length;\r
} TLS_RECORD_HEADER;\r
\r
-#define TLS_RECORD_HEADER_LENGTH 5\r
+#define TLS_RECORD_HEADER_LENGTH 5\r
\r
//\r
// The length (in bytes) of the TLSPlaintext records payload MUST NOT exceed 2^14.\r
// Refers to section 6.2 of RFC5246.\r
//\r
-#define TLS_PLAINTEXT_RECORD_MAX_PAYLOAD_LENGTH 16384\r
+#define TLS_PLAINTEXT_RECORD_MAX_PAYLOAD_LENGTH 16384\r
\r
//\r
// The length (in bytes) of the TLSCiphertext records payload MUST NOT exceed 2^14 + 2048.\r
// Refers to section 6.2 of RFC5246.\r
//\r
-#define TLS_CIPHERTEXT_RECORD_MAX_PAYLOAD_LENGTH 18432\r
+#define TLS_CIPHERTEXT_RECORD_MAX_PAYLOAD_LENGTH 18432\r
\r
#pragma pack()\r
\r
#endif\r
-\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
-\r
#ifndef _TPM12_H_\r
#define _TPM12_H_\r
\r
///\r
/// The start of TPM return codes\r
///\r
-#define TPM_BASE 0\r
+#define TPM_BASE 0\r
\r
//\r
// All structures MUST be packed on a byte boundary.\r
///\r
/// Indicates the conditions where it is required that authorization be presented\r
///\r
-typedef UINT8 TPM_AUTH_DATA_USAGE;\r
+typedef UINT8 TPM_AUTH_DATA_USAGE;\r
///\r
/// The information as to what the payload is in an encrypted structure\r
///\r
-typedef UINT8 TPM_PAYLOAD_TYPE;\r
+typedef UINT8 TPM_PAYLOAD_TYPE;\r
///\r
/// The version info breakdown\r
///\r
-typedef UINT8 TPM_VERSION_BYTE;\r
+typedef UINT8 TPM_VERSION_BYTE;\r
///\r
/// The state of the dictionary attack mitigation logic\r
///\r
-typedef UINT8 TPM_DA_STATE;\r
+typedef UINT8 TPM_DA_STATE;\r
///\r
/// The request or response authorization type\r
///\r
-typedef UINT16 TPM_TAG;\r
+typedef UINT16 TPM_TAG;\r
///\r
/// The protocol in use\r
///\r
-typedef UINT16 TPM_PROTOCOL_ID;\r
+typedef UINT16 TPM_PROTOCOL_ID;\r
///\r
/// Indicates the start state\r
///\r
-typedef UINT16 TPM_STARTUP_TYPE;\r
+typedef UINT16 TPM_STARTUP_TYPE;\r
///\r
/// The definition of the encryption scheme\r
///\r
-typedef UINT16 TPM_ENC_SCHEME;\r
+typedef UINT16 TPM_ENC_SCHEME;\r
///\r
/// The definition of the signature scheme\r
///\r
-typedef UINT16 TPM_SIG_SCHEME;\r
+typedef UINT16 TPM_SIG_SCHEME;\r
///\r
/// The definition of the migration scheme\r
///\r
-typedef UINT16 TPM_MIGRATE_SCHEME;\r
+typedef UINT16 TPM_MIGRATE_SCHEME;\r
///\r
/// Sets the state of the physical presence mechanism\r
///\r
-typedef UINT16 TPM_PHYSICAL_PRESENCE;\r
+typedef UINT16 TPM_PHYSICAL_PRESENCE;\r
///\r
/// Indicates the types of entity that are supported by the TPM\r
///\r
-typedef UINT16 TPM_ENTITY_TYPE;\r
+typedef UINT16 TPM_ENTITY_TYPE;\r
///\r
/// Indicates the permitted usage of the key\r
///\r
-typedef UINT16 TPM_KEY_USAGE;\r
+typedef UINT16 TPM_KEY_USAGE;\r
///\r
/// The type of asymmetric encrypted structure in use by the endorsement key\r
///\r
-typedef UINT16 TPM_EK_TYPE;\r
+typedef UINT16 TPM_EK_TYPE;\r
///\r
/// The tag for the structure\r
///\r
-typedef UINT16 TPM_STRUCTURE_TAG;\r
+typedef UINT16 TPM_STRUCTURE_TAG;\r
///\r
/// The platform specific spec to which the information relates to\r
///\r
-typedef UINT16 TPM_PLATFORM_SPECIFIC;\r
+typedef UINT16 TPM_PLATFORM_SPECIFIC;\r
///\r
/// The command ordinal\r
///\r
-typedef UINT32 TPM_COMMAND_CODE;\r
+typedef UINT32 TPM_COMMAND_CODE;\r
///\r
/// Identifies a TPM capability area\r
///\r
-typedef UINT32 TPM_CAPABILITY_AREA;\r
+typedef UINT32 TPM_CAPABILITY_AREA;\r
///\r
/// Indicates information regarding a key\r
///\r
-typedef UINT32 TPM_KEY_FLAGS;\r
+typedef UINT32 TPM_KEY_FLAGS;\r
///\r
/// Indicates the type of algorithm\r
///\r
-typedef UINT32 TPM_ALGORITHM_ID;\r
+typedef UINT32 TPM_ALGORITHM_ID;\r
///\r
/// The locality modifier\r
///\r
-typedef UINT32 TPM_MODIFIER_INDICATOR;\r
+typedef UINT32 TPM_MODIFIER_INDICATOR;\r
///\r
/// The actual number of a counter\r
///\r
-typedef UINT32 TPM_ACTUAL_COUNT;\r
+typedef UINT32 TPM_ACTUAL_COUNT;\r
///\r
/// Attributes that define what options are in use for a transport session\r
///\r
-typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;\r
+typedef UINT32 TPM_TRANSPORT_ATTRIBUTES;\r
///\r
/// Handle to an authorization session\r
///\r
-typedef UINT32 TPM_AUTHHANDLE;\r
+typedef UINT32 TPM_AUTHHANDLE;\r
///\r
/// Index to a DIR register\r
///\r
-typedef UINT32 TPM_DIRINDEX;\r
+typedef UINT32 TPM_DIRINDEX;\r
///\r
/// The area where a key is held assigned by the TPM\r
///\r
-typedef UINT32 TPM_KEY_HANDLE;\r
+typedef UINT32 TPM_KEY_HANDLE;\r
///\r
/// Index to a PCR register\r
///\r
-typedef UINT32 TPM_PCRINDEX;\r
+typedef UINT32 TPM_PCRINDEX;\r
///\r
/// The return code from a function\r
///\r
-typedef UINT32 TPM_RESULT;\r
+typedef UINT32 TPM_RESULT;\r
///\r
/// The types of resources that a TPM may have using internal resources\r
///\r
-typedef UINT32 TPM_RESOURCE_TYPE;\r
+typedef UINT32 TPM_RESOURCE_TYPE;\r
///\r
/// Allows for controlling of the key when loaded and how to handle TPM_Startup issues\r
///\r
-typedef UINT32 TPM_KEY_CONTROL;\r
+typedef UINT32 TPM_KEY_CONTROL;\r
///\r
/// The index into the NV storage area\r
///\r
-typedef UINT32 TPM_NV_INDEX;\r
+typedef UINT32 TPM_NV_INDEX;\r
///\r
/// The family ID. Family IDs are automatically assigned a sequence number by the TPM.\r
/// A trusted process can set the FamilyID value in an individual row to NULL, which\r
/// invalidates that row. The family ID resets to NULL on each change of TPM Owner.\r
///\r
-typedef UINT32 TPM_FAMILY_ID;\r
+typedef UINT32 TPM_FAMILY_ID;\r
///\r
/// IA value used as a label for the most recent verification of this family. Set to zero when not in use.\r
///\r
-typedef UINT32 TPM_FAMILY_VERIFICATION;\r
+typedef UINT32 TPM_FAMILY_VERIFICATION;\r
///\r
/// How the TPM handles var\r
///\r
-typedef UINT32 TPM_STARTUP_EFFECTS;\r
+typedef UINT32 TPM_STARTUP_EFFECTS;\r
///\r
/// The mode of a symmetric encryption\r
///\r
-typedef UINT32 TPM_SYM_MODE;\r
+typedef UINT32 TPM_SYM_MODE;\r
///\r
/// The family flags\r
///\r
-typedef UINT32 TPM_FAMILY_FLAGS;\r
+typedef UINT32 TPM_FAMILY_FLAGS;\r
///\r
/// The index value for the delegate NV table\r
///\r
-typedef UINT32 TPM_DELEGATE_INDEX;\r
+typedef UINT32 TPM_DELEGATE_INDEX;\r
///\r
/// The restrictions placed on delegation of CMK commands\r
///\r
-typedef UINT32 TPM_CMK_DELEGATE;\r
+typedef UINT32 TPM_CMK_DELEGATE;\r
///\r
/// The ID value of a monotonic counter\r
///\r
-typedef UINT32 TPM_COUNT_ID;\r
+typedef UINT32 TPM_COUNT_ID;\r
///\r
/// A command to execute\r
///\r
-typedef UINT32 TPM_REDIT_COMMAND;\r
+typedef UINT32 TPM_REDIT_COMMAND;\r
///\r
/// A transport session handle\r
///\r
-typedef UINT32 TPM_TRANSHANDLE;\r
+typedef UINT32 TPM_TRANSHANDLE;\r
///\r
/// A generic handle could be key, transport etc\r
///\r
-typedef UINT32 TPM_HANDLE;\r
+typedef UINT32 TPM_HANDLE;\r
///\r
/// What operation is happening\r
///\r
-typedef UINT32 TPM_FAMILY_OPERATION;\r
+typedef UINT32 TPM_FAMILY_OPERATION;\r
\r
//\r
// Part 2, section 2.2.4: Vendor specific\r
// The following defines allow for the quick specification of a\r
// vendor specific item.\r
//\r
-#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)\r
-#define TPM_Vendor_Specific8 ((UINT8) 0x80)\r
+#define TPM_Vendor_Specific32 ((UINT32) 0x00000400)\r
+#define TPM_Vendor_Specific8 ((UINT8) 0x80)\r
\r
//\r
// Part 2, section 3.1: TPM_STRUCTURE_TAG\r
//\r
-#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)\r
-#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)\r
-#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)\r
-#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)\r
-#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)\r
-#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)\r
-#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)\r
-#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)\r
-#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)\r
-#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)\r
-#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)\r
-#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)\r
-#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)\r
-#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)\r
-#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)\r
-#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)\r
-#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)\r
-#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)\r
-#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)\r
-#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)\r
-#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)\r
-#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)\r
-#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)\r
-#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)\r
-#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)\r
-#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)\r
-#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)\r
-#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)\r
-#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)\r
-#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)\r
-#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)\r
-#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)\r
-#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)\r
-#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)\r
-#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)\r
-#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)\r
-#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)\r
-#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)\r
-#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)\r
-#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)\r
-#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)\r
-#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)\r
-#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)\r
-#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)\r
-#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)\r
-#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)\r
-#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)\r
-#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)\r
-#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)\r
-#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)\r
-#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)\r
-#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)\r
-#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)\r
-#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)\r
-#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037)\r
-#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038)\r
-#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039)\r
+#define TPM_TAG_CONTEXTBLOB ((TPM_STRUCTURE_TAG) 0x0001)\r
+#define TPM_TAG_CONTEXT_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0002)\r
+#define TPM_TAG_CONTEXTPOINTER ((TPM_STRUCTURE_TAG) 0x0003)\r
+#define TPM_TAG_CONTEXTLIST ((TPM_STRUCTURE_TAG) 0x0004)\r
+#define TPM_TAG_SIGNINFO ((TPM_STRUCTURE_TAG) 0x0005)\r
+#define TPM_TAG_PCR_INFO_LONG ((TPM_STRUCTURE_TAG) 0x0006)\r
+#define TPM_TAG_PERSISTENT_FLAGS ((TPM_STRUCTURE_TAG) 0x0007)\r
+#define TPM_TAG_VOLATILE_FLAGS ((TPM_STRUCTURE_TAG) 0x0008)\r
+#define TPM_TAG_PERSISTENT_DATA ((TPM_STRUCTURE_TAG) 0x0009)\r
+#define TPM_TAG_VOLATILE_DATA ((TPM_STRUCTURE_TAG) 0x000A)\r
+#define TPM_TAG_SV_DATA ((TPM_STRUCTURE_TAG) 0x000B)\r
+#define TPM_TAG_EK_BLOB ((TPM_STRUCTURE_TAG) 0x000C)\r
+#define TPM_TAG_EK_BLOB_AUTH ((TPM_STRUCTURE_TAG) 0x000D)\r
+#define TPM_TAG_COUNTER_VALUE ((TPM_STRUCTURE_TAG) 0x000E)\r
+#define TPM_TAG_TRANSPORT_INTERNAL ((TPM_STRUCTURE_TAG) 0x000F)\r
+#define TPM_TAG_TRANSPORT_LOG_IN ((TPM_STRUCTURE_TAG) 0x0010)\r
+#define TPM_TAG_TRANSPORT_LOG_OUT ((TPM_STRUCTURE_TAG) 0x0011)\r
+#define TPM_TAG_AUDIT_EVENT_IN ((TPM_STRUCTURE_TAG) 0x0012)\r
+#define TPM_TAG_AUDIT_EVENT_OUT ((TPM_STRUCTURE_TAG) 0x0013)\r
+#define TPM_TAG_CURRENT_TICKS ((TPM_STRUCTURE_TAG) 0x0014)\r
+#define TPM_TAG_KEY ((TPM_STRUCTURE_TAG) 0x0015)\r
+#define TPM_TAG_STORED_DATA12 ((TPM_STRUCTURE_TAG) 0x0016)\r
+#define TPM_TAG_NV_ATTRIBUTES ((TPM_STRUCTURE_TAG) 0x0017)\r
+#define TPM_TAG_NV_DATA_PUBLIC ((TPM_STRUCTURE_TAG) 0x0018)\r
+#define TPM_TAG_NV_DATA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0019)\r
+#define TPM_TAG_DELEGATIONS ((TPM_STRUCTURE_TAG) 0x001A)\r
+#define TPM_TAG_DELEGATE_PUBLIC ((TPM_STRUCTURE_TAG) 0x001B)\r
+#define TPM_TAG_DELEGATE_TABLE_ROW ((TPM_STRUCTURE_TAG) 0x001C)\r
+#define TPM_TAG_TRANSPORT_AUTH ((TPM_STRUCTURE_TAG) 0x001D)\r
+#define TPM_TAG_TRANSPORT_PUBLIC ((TPM_STRUCTURE_TAG) 0x001E)\r
+#define TPM_TAG_PERMANENT_FLAGS ((TPM_STRUCTURE_TAG) 0x001F)\r
+#define TPM_TAG_STCLEAR_FLAGS ((TPM_STRUCTURE_TAG) 0x0020)\r
+#define TPM_TAG_STANY_FLAGS ((TPM_STRUCTURE_TAG) 0x0021)\r
+#define TPM_TAG_PERMANENT_DATA ((TPM_STRUCTURE_TAG) 0x0022)\r
+#define TPM_TAG_STCLEAR_DATA ((TPM_STRUCTURE_TAG) 0x0023)\r
+#define TPM_TAG_STANY_DATA ((TPM_STRUCTURE_TAG) 0x0024)\r
+#define TPM_TAG_FAMILY_TABLE_ENTRY ((TPM_STRUCTURE_TAG) 0x0025)\r
+#define TPM_TAG_DELEGATE_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0026)\r
+#define TPM_TAG_DELG_KEY_BLOB ((TPM_STRUCTURE_TAG) 0x0027)\r
+#define TPM_TAG_KEY12 ((TPM_STRUCTURE_TAG) 0x0028)\r
+#define TPM_TAG_CERTIFY_INFO2 ((TPM_STRUCTURE_TAG) 0x0029)\r
+#define TPM_TAG_DELEGATE_OWNER_BLOB ((TPM_STRUCTURE_TAG) 0x002A)\r
+#define TPM_TAG_EK_BLOB_ACTIVATE ((TPM_STRUCTURE_TAG) 0x002B)\r
+#define TPM_TAG_DAA_BLOB ((TPM_STRUCTURE_TAG) 0x002C)\r
+#define TPM_TAG_DAA_CONTEXT ((TPM_STRUCTURE_TAG) 0x002D)\r
+#define TPM_TAG_DAA_ENFORCE ((TPM_STRUCTURE_TAG) 0x002E)\r
+#define TPM_TAG_DAA_ISSUER ((TPM_STRUCTURE_TAG) 0x002F)\r
+#define TPM_TAG_CAP_VERSION_INFO ((TPM_STRUCTURE_TAG) 0x0030)\r
+#define TPM_TAG_DAA_SENSITIVE ((TPM_STRUCTURE_TAG) 0x0031)\r
+#define TPM_TAG_DAA_TPM ((TPM_STRUCTURE_TAG) 0x0032)\r
+#define TPM_TAG_CMK_MIGAUTH ((TPM_STRUCTURE_TAG) 0x0033)\r
+#define TPM_TAG_CMK_SIGTICKET ((TPM_STRUCTURE_TAG) 0x0034)\r
+#define TPM_TAG_CMK_MA_APPROVAL ((TPM_STRUCTURE_TAG) 0x0035)\r
+#define TPM_TAG_QUOTE_INFO2 ((TPM_STRUCTURE_TAG) 0x0036)\r
+#define TPM_TAG_DA_INFO ((TPM_STRUCTURE_TAG) 0x0037)\r
+#define TPM_TAG_DA_LIMITED ((TPM_STRUCTURE_TAG) 0x0038)\r
+#define TPM_TAG_DA_ACTION_TYPE ((TPM_STRUCTURE_TAG) 0x0039)\r
\r
//\r
// Part 2, section 4: TPM Types\r
//\r
// Part 2, section 4.1: TPM_RESOURCE_TYPE\r
//\r
-#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation\r
-#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP\r
-#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes\r
-#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport\r
-#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands\r
-#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters\r
-#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM\r
-#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob\r
-#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter\r
-#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter\r
+#define TPM_RT_KEY ((TPM_RESOURCE_TYPE) 0x00000001) ///< The handle is a key handle and is the result of a LoadKey type operation\r
+#define TPM_RT_AUTH ((TPM_RESOURCE_TYPE) 0x00000002) ///< The handle is an authorization handle. Auth handles come from TPM_OIAP, TPM_OSAP and TPM_DSAP\r
+#define TPM_RT_HASH ((TPM_RESOURCE_TYPE) 0x00000003) ///< Reserved for hashes\r
+#define TPM_RT_TRANS ((TPM_RESOURCE_TYPE) 0x00000004) ///< The handle is for a transport session. Transport handles come from TPM_EstablishTransport\r
+#define TPM_RT_CONTEXT ((TPM_RESOURCE_TYPE) 0x00000005) ///< Resource wrapped and held outside the TPM using the context save/restore commands\r
+#define TPM_RT_COUNTER ((TPM_RESOURCE_TYPE) 0x00000006) ///< Reserved for counters\r
+#define TPM_RT_DELEGATE ((TPM_RESOURCE_TYPE) 0x00000007) ///< The handle is for a delegate row. These are the internal rows held in NV storage by the TPM\r
+#define TPM_RT_DAA_TPM ((TPM_RESOURCE_TYPE) 0x00000008) ///< The value is a DAA TPM specific blob\r
+#define TPM_RT_DAA_V0 ((TPM_RESOURCE_TYPE) 0x00000009) ///< The value is a DAA V0 parameter\r
+#define TPM_RT_DAA_V1 ((TPM_RESOURCE_TYPE) 0x0000000A) ///< The value is a DAA V1 parameter\r
\r
//\r
// Part 2, section 4.2: TPM_PAYLOAD_TYPE\r
//\r
-#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key\r
-#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data\r
-#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob\r
-#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob\r
-#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data\r
-#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key\r
-#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key\r
-#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob\r
-#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads\r
+#define TPM_PT_ASYM ((TPM_PAYLOAD_TYPE) 0x01) ///< The entity is an asymmetric key\r
+#define TPM_PT_BIND ((TPM_PAYLOAD_TYPE) 0x02) ///< The entity is bound data\r
+#define TPM_PT_MIGRATE ((TPM_PAYLOAD_TYPE) 0x03) ///< The entity is a migration blob\r
+#define TPM_PT_MAINT ((TPM_PAYLOAD_TYPE) 0x04) ///< The entity is a maintenance blob\r
+#define TPM_PT_SEAL ((TPM_PAYLOAD_TYPE) 0x05) ///< The entity is sealed data\r
+#define TPM_PT_MIGRATE_RESTRICTED ((TPM_PAYLOAD_TYPE) 0x06) ///< The entity is a restricted-migration asymmetric key\r
+#define TPM_PT_MIGRATE_EXTERNAL ((TPM_PAYLOAD_TYPE) 0x07) ///< The entity is a external migratable key\r
+#define TPM_PT_CMK_MIGRATE ((TPM_PAYLOAD_TYPE) 0x08) ///< The entity is a CMK migratable blob\r
+#define TPM_PT_VENDOR_SPECIFIC ((TPM_PAYLOAD_TYPE) 0x80) ///< 0x80 - 0xFF Vendor specific payloads\r
\r
//\r
// Part 2, section 4.3: TPM_ENTITY_TYPE\r
//\r
-#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key\r
-#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner\r
-#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data\r
-#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK\r
-#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle\r
-#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value\r
-#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob\r
-#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row\r
-#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob\r
-#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter\r
-#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index\r
-#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator\r
-#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.\r
+#define TPM_ET_KEYHANDLE ((UINT16) 0x0001) ///< The entity is a keyHandle or key\r
+#define TPM_ET_OWNER ((UINT16) 0x0002) ///< The entity is the TPM Owner\r
+#define TPM_ET_DATA ((UINT16) 0x0003) ///< The entity is some data\r
+#define TPM_ET_SRK ((UINT16) 0x0004) ///< The entity is the SRK\r
+#define TPM_ET_KEY ((UINT16) 0x0005) ///< The entity is a key or keyHandle\r
+#define TPM_ET_REVOKE ((UINT16) 0x0006) ///< The entity is the RevokeTrust value\r
+#define TPM_ET_DEL_OWNER_BLOB ((UINT16) 0x0007) ///< The entity is a delegate owner blob\r
+#define TPM_ET_DEL_ROW ((UINT16) 0x0008) ///< The entity is a delegate row\r
+#define TPM_ET_DEL_KEY_BLOB ((UINT16) 0x0009) ///< The entity is a delegate key blob\r
+#define TPM_ET_COUNTER ((UINT16) 0x000A) ///< The entity is a counter\r
+#define TPM_ET_NV ((UINT16) 0x000B) ///< The entity is a NV index\r
+#define TPM_ET_OPERATOR ((UINT16) 0x000C) ///< The entity is the operator\r
+#define TPM_ET_RESERVED_HANDLE ((UINT16) 0x0040) ///< Reserved. This value avoids collisions with the handle MSB setting.\r
//\r
// TPM_ENTITY_TYPE MSB Values: The MSB is used to indicate the ADIP encryption sheme when applicable\r
//\r
-#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR\r
-#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits\r
+#define TPM_ET_XOR ((UINT16) 0x0000) ///< ADIP encryption scheme: XOR\r
+#define TPM_ET_AES128 ((UINT16) 0x0006) ///< ADIP encryption scheme: AES 128 bits\r
\r
//\r
// Part 2, section 4.4.1: Reserved Key Handles\r
//\r
-#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK\r
-#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner\r
-#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value\r
-#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization\r
-#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth\r
-#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth\r
-#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub\r
+#define TPM_KH_SRK ((TPM_KEY_HANDLE) 0x40000000) ///< The handle points to the SRK\r
+#define TPM_KH_OWNER ((TPM_KEY_HANDLE) 0x40000001) ///< The handle points to the TPM Owner\r
+#define TPM_KH_REVOKE ((TPM_KEY_HANDLE) 0x40000002) ///< The handle points to the RevokeTrust value\r
+#define TPM_KH_TRANSPORT ((TPM_KEY_HANDLE) 0x40000003) ///< The handle points to the EstablishTransport static authorization\r
+#define TPM_KH_OPERATOR ((TPM_KEY_HANDLE) 0x40000004) ///< The handle points to the Operator auth\r
+#define TPM_KH_ADMIN ((TPM_KEY_HANDLE) 0x40000005) ///< The handle points to the delegation administration auth\r
+#define TPM_KH_EK ((TPM_KEY_HANDLE) 0x40000006) ///< The handle points to the PUBEK, only usable with TPM_OwnerReadInternalPub\r
\r
//\r
// Part 2, section 4.5: TPM_STARTUP_TYPE\r
//\r
-#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state\r
-#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state\r
-#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE\r
+#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) ///< The TPM is starting up from a clean state\r
+#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) ///< The TPM is starting up from a saved state\r
+#define TPM_ST_DEACTIVATED ((TPM_STARTUP_TYPE) 0x0003) ///< The TPM is to startup and set the deactivated flag to TRUE\r
\r
//\r
// Part 2, section 4.6: TPM_STATUP_EFFECTS\r
//\r
// Part 2, section 4.7: TPM_PROTOCOL_ID\r
//\r
-#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.\r
-#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.\r
-#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.\r
-#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.\r
-#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.\r
-#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol\r
-#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol\r
+#define TPM_PID_OIAP ((TPM_PROTOCOL_ID) 0x0001) ///< The OIAP protocol.\r
+#define TPM_PID_OSAP ((TPM_PROTOCOL_ID) 0x0002) ///< The OSAP protocol.\r
+#define TPM_PID_ADIP ((TPM_PROTOCOL_ID) 0x0003) ///< The ADIP protocol.\r
+#define TPM_PID_ADCP ((TPM_PROTOCOL_ID) 0x0004) ///< The ADCP protocol.\r
+#define TPM_PID_OWNER ((TPM_PROTOCOL_ID) 0x0005) ///< The protocol for taking ownership of a TPM.\r
+#define TPM_PID_DSAP ((TPM_PROTOCOL_ID) 0x0006) ///< The DSAP protocol\r
+#define TPM_PID_TRANSPORT ((TPM_PROTOCOL_ID) 0x0007) ///< The transport protocol\r
\r
//\r
// Part 2, section 4.8: TPM_ALGORITHM_ID\r
// The TPM MUST support the algorithms TPM_ALG_RSA, TPM_ALG_SHA, TPM_ALG_HMAC,\r
// TPM_ALG_MGF1\r
//\r
-#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.\r
-#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm\r
-#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode\r
-#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm\r
-#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm\r
-#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128\r
-#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block\r
-#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192\r
-#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256\r
-#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces\r
+#define TPM_ALG_RSA ((TPM_ALGORITHM_ID) 0x00000001) ///< The RSA algorithm.\r
+#define TPM_ALG_DES ((TPM_ALGORITHM_ID) 0x00000002) ///< The DES algorithm\r
+#define TPM_ALG_3DES ((TPM_ALGORITHM_ID) 0x00000003) ///< The 3DES algorithm in EDE mode\r
+#define TPM_ALG_SHA ((TPM_ALGORITHM_ID) 0x00000004) ///< The SHA1 algorithm\r
+#define TPM_ALG_HMAC ((TPM_ALGORITHM_ID) 0x00000005) ///< The RFC 2104 HMAC algorithm\r
+#define TPM_ALG_AES128 ((TPM_ALGORITHM_ID) 0x00000006) ///< The AES algorithm, key size 128\r
+#define TPM_ALG_MGF1 ((TPM_ALGORITHM_ID) 0x00000007) ///< The XOR algorithm using MGF1 to create a string the size of the encrypted block\r
+#define TPM_ALG_AES192 ((TPM_ALGORITHM_ID) 0x00000008) ///< AES, key size 192\r
+#define TPM_ALG_AES256 ((TPM_ALGORITHM_ID) 0x00000009) ///< AES, key size 256\r
+#define TPM_ALG_XOR ((TPM_ALGORITHM_ID) 0x0000000A) ///< XOR using the rolling nonces\r
\r
//\r
// Part 2, section 4.9: TPM_PHYSICAL_PRESENCE\r
//\r
-#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE\r
-#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE\r
-#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE\r
-#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE\r
-#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE\r
-#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE\r
-#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE\r
-#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE\r
+#define TPM_PHYSICAL_PRESENCE_HW_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0200) ///< Sets the physicalPresenceHWEnable to FALSE\r
+#define TPM_PHYSICAL_PRESENCE_CMD_DISABLE ((TPM_PHYSICAL_PRESENCE) 0x0100) ///< Sets the physicalPresenceCMDEnable to FALSE\r
+#define TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0080) ///< Sets the physicalPresenceLifetimeLock to TRUE\r
+#define TPM_PHYSICAL_PRESENCE_HW_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0040) ///< Sets the physicalPresenceHWEnable to TRUE\r
+#define TPM_PHYSICAL_PRESENCE_CMD_ENABLE ((TPM_PHYSICAL_PRESENCE) 0x0020) ///< Sets the physicalPresenceCMDEnable to TRUE\r
+#define TPM_PHYSICAL_PRESENCE_NOTPRESENT ((TPM_PHYSICAL_PRESENCE) 0x0010) ///< Sets PhysicalPresence = FALSE\r
+#define TPM_PHYSICAL_PRESENCE_PRESENT ((TPM_PHYSICAL_PRESENCE) 0x0008) ///< Sets PhysicalPresence = TRUE\r
+#define TPM_PHYSICAL_PRESENCE_LOCK ((TPM_PHYSICAL_PRESENCE) 0x0004) ///< Sets PhysicalPresenceLock = TRUE\r
\r
//\r
// Part 2, section 4.10: TPM_MIGRATE_SCHEME\r
//\r
-#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.\r
-#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.\r
-#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands\r
-#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.\r
-#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping\r
+#define TPM_MS_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0001) ///< A public key that can be used with all TPM migration commands other than 'ReWrap' mode.\r
+#define TPM_MS_REWRAP ((TPM_MIGRATE_SCHEME) 0x0002) ///< A public key that can be used for the ReWrap mode of TPM_CreateMigrationBlob.\r
+#define TPM_MS_MAINT ((TPM_MIGRATE_SCHEME) 0x0003) ///< A public key that can be used for the Maintenance commands\r
+#define TPM_MS_RESTRICT_MIGRATE ((TPM_MIGRATE_SCHEME) 0x0004) ///< The key is to be migrated to a Migration Authority.\r
+#define TPM_MS_RESTRICT_APPROVE_DOUBLE ((TPM_MIGRATE_SCHEME) 0x0005) ///< The key is to be migrated to an entity approved by a Migration Authority using double wrapping\r
\r
//\r
// Part 2, section 4.11: TPM_EK_TYPE\r
//\r
-#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE\r
-#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH\r
+#define TPM_EK_TYPE_ACTIVATE ((TPM_EK_TYPE) 0x0001) ///< The blob MUST be TPM_EK_BLOB_ACTIVATE\r
+#define TPM_EK_TYPE_AUTH ((TPM_EK_TYPE) 0x0002) ///< The blob MUST be TPM_EK_BLOB_AUTH\r
\r
//\r
// Part 2, section 4.12: TPM_PLATFORM_SPECIFIC\r
//\r
-#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1\r
-#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2\r
-#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2\r
-#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2\r
-#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2\r
+#define TPM_PS_PC_11 ((TPM_PLATFORM_SPECIFIC) 0x0001) ///< PC Specific version 1.1\r
+#define TPM_PS_PC_12 ((TPM_PLATFORM_SPECIFIC) 0x0002) ///< PC Specific version 1.2\r
+#define TPM_PS_PDA_12 ((TPM_PLATFORM_SPECIFIC) 0x0003) ///< PDA Specific version 1.2\r
+#define TPM_PS_Server_12 ((TPM_PLATFORM_SPECIFIC) 0x0004) ///< Server Specific version 1.2\r
+#define TPM_PS_Mobile_12 ((TPM_PLATFORM_SPECIFIC) 0x0005) ///< Mobil Specific version 1.2\r
\r
//\r
// Part 2, section 5: Basic Structures\r
/// Part 2, section 5.1: TPM_STRUCT_VER\r
///\r
typedef struct tdTPM_STRUCT_VER {\r
- UINT8 major;\r
- UINT8 minor;\r
- UINT8 revMajor;\r
- UINT8 revMinor;\r
+ UINT8 major;\r
+ UINT8 minor;\r
+ UINT8 revMajor;\r
+ UINT8 revMinor;\r
} TPM_STRUCT_VER;\r
\r
///\r
/// Part 2, section 5.3: TPM_VERSION\r
///\r
typedef struct tdTPM_VERSION {\r
- TPM_VERSION_BYTE major;\r
- TPM_VERSION_BYTE minor;\r
- UINT8 revMajor;\r
- UINT8 revMinor;\r
+ TPM_VERSION_BYTE major;\r
+ TPM_VERSION_BYTE minor;\r
+ UINT8 revMajor;\r
+ UINT8 revMinor;\r
} TPM_VERSION;\r
\r
-\r
-#define TPM_SHA1_160_HASH_LEN 0x14\r
-#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN\r
+#define TPM_SHA1_160_HASH_LEN 0x14\r
+#define TPM_SHA1BASED_NONCE_LEN TPM_SHA1_160_HASH_LEN\r
\r
///\r
/// Part 2, section 5.4: TPM_DIGEST\r
///\r
-typedef struct tdTPM_DIGEST{\r
- UINT8 digest[TPM_SHA1_160_HASH_LEN];\r
+typedef struct tdTPM_DIGEST {\r
+ UINT8 digest[TPM_SHA1_160_HASH_LEN];\r
} TPM_DIGEST;\r
\r
///\r
/// This SHALL be the digest of the chosen identityLabel and privacyCA for a new TPM identity\r
///\r
-typedef TPM_DIGEST TPM_CHOSENID_HASH;\r
+typedef TPM_DIGEST TPM_CHOSENID_HASH;\r
///\r
/// This SHALL be the hash of a list of PCR indexes and PCR values that a key or data is bound to\r
///\r
-typedef TPM_DIGEST TPM_COMPOSITE_HASH;\r
+typedef TPM_DIGEST TPM_COMPOSITE_HASH;\r
///\r
/// This SHALL be the value of a DIR register\r
///\r
-typedef TPM_DIGEST TPM_DIRVALUE;\r
+typedef TPM_DIGEST TPM_DIRVALUE;\r
\r
-typedef TPM_DIGEST TPM_HMAC;\r
+typedef TPM_DIGEST TPM_HMAC;\r
///\r
/// The value inside of the PCR\r
///\r
-typedef TPM_DIGEST TPM_PCRVALUE;\r
+typedef TPM_DIGEST TPM_PCRVALUE;\r
///\r
/// This SHALL be the value of the current internal audit state\r
///\r
-typedef TPM_DIGEST TPM_AUDITDIGEST;\r
+typedef TPM_DIGEST TPM_AUDITDIGEST;\r
\r
///\r
/// Part 2, section 5.5: TPM_NONCE\r
///\r
-typedef struct tdTPM_NONCE{\r
- UINT8 nonce[20];\r
+typedef struct tdTPM_NONCE {\r
+ UINT8 nonce[20];\r
} TPM_NONCE;\r
\r
///\r
/// This SHALL be a random value generated by a TPM immediately after the EK is installed\r
/// in that TPM, whenever an EK is installed in that TPM\r
///\r
-typedef TPM_NONCE TPM_DAA_TPM_SEED;\r
+typedef TPM_NONCE TPM_DAA_TPM_SEED;\r
///\r
/// This SHALL be a random value\r
///\r
-typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;\r
+typedef TPM_NONCE TPM_DAA_CONTEXT_SEED;\r
\r
//\r
// Part 2, section 5.6: TPM_AUTHDATA\r
/// The AuthData data is the information that is saved or passed to provide proof of ownership\r
/// 296 of an entity\r
///\r
-typedef UINT8 tdTPM_AUTHDATA[20];\r
+typedef UINT8 tdTPM_AUTHDATA[20];\r
\r
-typedef tdTPM_AUTHDATA TPM_AUTHDATA;\r
+typedef tdTPM_AUTHDATA TPM_AUTHDATA;\r
///\r
/// A secret plaintext value used in the authorization process\r
///\r
-typedef TPM_AUTHDATA TPM_SECRET;\r
+typedef TPM_AUTHDATA TPM_SECRET;\r
///\r
/// A ciphertext (encrypted) version of AuthData data. The encryption mechanism depends on the context\r
///\r
-typedef TPM_AUTHDATA TPM_ENCAUTH;\r
+typedef TPM_AUTHDATA TPM_ENCAUTH;\r
\r
///\r
/// Part 2, section 5.7: TPM_KEY_HANDLE_LIST\r
/// Size of handle is loaded * sizeof(TPM_KEY_HANDLE)\r
///\r
typedef struct tdTPM_KEY_HANDLE_LIST {\r
- UINT16 loaded;\r
- TPM_KEY_HANDLE handle[1];\r
+ UINT16 loaded;\r
+ TPM_KEY_HANDLE handle[1];\r
} TPM_KEY_HANDLE_LIST;\r
\r
//\r
/// used for signing operations, only. This means that it MUST be a leaf of the\r
/// Protected Storage key hierarchy.\r
///\r
-#define TPM_KEY_SIGNING ((UINT16) 0x0010)\r
+#define TPM_KEY_SIGNING ((UINT16) 0x0010)\r
///\r
/// TPM_KEY_STORAGE SHALL indicate a storage key. The key SHALL be used to wrap\r
/// and unwrap other keys in the Protected Storage hierarchy\r
///\r
-#define TPM_KEY_STORAGE ((UINT16) 0x0011)\r
+#define TPM_KEY_STORAGE ((UINT16) 0x0011)\r
///\r
/// TPM_KEY_IDENTITY SHALL indicate an identity key. The key SHALL be used for\r
/// operations that require a TPM identity, only.\r
///\r
-#define TPM_KEY_IDENTITY ((UINT16) 0x0012)\r
+#define TPM_KEY_IDENTITY ((UINT16) 0x0012)\r
///\r
/// TPM_KEY_AUTHCHANGE SHALL indicate an ephemeral key that is in use during\r
/// the ChangeAuthAsym process, only.\r
///\r
-#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)\r
+#define TPM_KEY_AUTHCHANGE ((UINT16) 0x0013)\r
///\r
/// TPM_KEY_BIND SHALL indicate a key that can be used for TPM_Bind and\r
/// TPM_Unbind operations only.\r
///\r
-#define TPM_KEY_BIND ((UINT16) 0x0014)\r
+#define TPM_KEY_BIND ((UINT16) 0x0014)\r
///\r
/// TPM_KEY_LEGACY SHALL indicate a key that can perform signing and binding\r
/// operations. The key MAY be used for both signing and binding operations.\r
/// key type is not recommended TPM_KEY_MIGRATE 0x0016 This SHALL indicate a\r
/// key in use for TPM_MigrateKey\r
///\r
-#define TPM_KEY_LEGACY ((UINT16) 0x0015)\r
+#define TPM_KEY_LEGACY ((UINT16) 0x0015)\r
///\r
/// TPM_KEY_MIGRAGE SHALL indicate a key in use for TPM_MigrateKey\r
///\r
-#define TPM_KEY_MIGRATE ((UINT16) 0x0016)\r
+#define TPM_KEY_MIGRATE ((UINT16) 0x0016)\r
\r
//\r
// Part 2, section 5.8.1: Mandatory Key Usage Schemes\r
//\r
// Part 2, section 5.9: TPM_AUTH_DATA_USAGE values\r
//\r
-#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)\r
-#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)\r
-#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)\r
+#define TPM_AUTH_NEVER ((TPM_AUTH_DATA_USAGE) 0x00)\r
+#define TPM_AUTH_ALWAYS ((TPM_AUTH_DATA_USAGE) 0x01)\r
+#define TPM_AUTH_PRIV_USE_ONLY ((TPM_AUTH_DATA_USAGE) 0x03)\r
\r
///\r
/// Part 2, section 5.10: TPM_KEY_FLAGS\r
///\r
typedef enum tdTPM_KEY_FLAGS {\r
- redirection = 0x00000001,\r
- migratable = 0x00000002,\r
- isVolatile = 0x00000004,\r
- pcrIgnoredOnRead = 0x00000008,\r
- migrateAuthority = 0x00000010\r
+ redirection = 0x00000001,\r
+ migratable = 0x00000002,\r
+ isVolatile = 0x00000004,\r
+ pcrIgnoredOnRead = 0x00000008,\r
+ migrateAuthority = 0x00000010\r
} TPM_KEY_FLAGS_BITS;\r
\r
///\r
/// Part 2, section 5.11: TPM_CHANGEAUTH_VALIDATE\r
///\r
typedef struct tdTPM_CHANGEAUTH_VALIDATE {\r
- TPM_SECRET newAuthSecret;\r
- TPM_NONCE n1;\r
+ TPM_SECRET newAuthSecret;\r
+ TPM_NONCE n1;\r
} TPM_CHANGEAUTH_VALIDATE;\r
\r
///\r
/// [size_is(parmSize)] BYTE* parms;\r
///\r
typedef struct tdTPM_KEY_PARMS {\r
- TPM_ALGORITHM_ID algorithmID;\r
- TPM_ENC_SCHEME encScheme;\r
- TPM_SIG_SCHEME sigScheme;\r
- UINT32 parmSize;\r
- UINT8 *parms;\r
+ TPM_ALGORITHM_ID algorithmID;\r
+ TPM_ENC_SCHEME encScheme;\r
+ TPM_SIG_SCHEME sigScheme;\r
+ UINT32 parmSize;\r
+ UINT8 *parms;\r
} TPM_KEY_PARMS;\r
\r
///\r
/// Part 2, section 10.4: TPM_STORE_PUBKEY\r
///\r
typedef struct tdTPM_STORE_PUBKEY {\r
- UINT32 keyLength;\r
- UINT8 key[1];\r
+ UINT32 keyLength;\r
+ UINT8 key[1];\r
} TPM_STORE_PUBKEY;\r
\r
///\r
/// Part 2, section 10.5: TPM_PUBKEY\r
///\r
-typedef struct tdTPM_PUBKEY{\r
- TPM_KEY_PARMS algorithmParms;\r
- TPM_STORE_PUBKEY pubKey;\r
+typedef struct tdTPM_PUBKEY {\r
+ TPM_KEY_PARMS algorithmParms;\r
+ TPM_STORE_PUBKEY pubKey;\r
} TPM_PUBKEY;\r
\r
///\r
/// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH\r
///\r
-typedef struct tdTPM_MIGRATIONKEYAUTH{\r
- TPM_PUBKEY migrationKey;\r
- TPM_MIGRATE_SCHEME migrationScheme;\r
- TPM_DIGEST digest;\r
+typedef struct tdTPM_MIGRATIONKEYAUTH {\r
+ TPM_PUBKEY migrationKey;\r
+ TPM_MIGRATE_SCHEME migrationScheme;\r
+ TPM_DIGEST digest;\r
} TPM_MIGRATIONKEYAUTH;\r
\r
///\r
/// Part 2, section 5.13: TPM_COUNTER_VALUE\r
///\r
-typedef struct tdTPM_COUNTER_VALUE{\r
- TPM_STRUCTURE_TAG tag;\r
- UINT8 label[4];\r
- TPM_ACTUAL_COUNT counter;\r
+typedef struct tdTPM_COUNTER_VALUE {\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT8 label[4];\r
+ TPM_ACTUAL_COUNT counter;\r
} TPM_COUNTER_VALUE;\r
\r
///\r
/// Size of data indicated by dataLen\r
///\r
typedef struct tdTPM_SIGN_INFO {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT8 fixed[4];\r
- TPM_NONCE replay;\r
- UINT32 dataLen;\r
- UINT8 *data;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT8 fixed[4];\r
+ TPM_NONCE replay;\r
+ UINT32 dataLen;\r
+ UINT8 *data;\r
} TPM_SIGN_INFO;\r
\r
///\r
/// Number of migAuthDigest indicated by MSAlist\r
///\r
typedef struct tdTPM_MSA_COMPOSITE {\r
- UINT32 MSAlist;\r
- TPM_DIGEST migAuthDigest[1];\r
+ UINT32 MSAlist;\r
+ TPM_DIGEST migAuthDigest[1];\r
} TPM_MSA_COMPOSITE;\r
\r
///\r
/// Part 2, section 5.16: TPM_CMK_AUTH\r
///\r
-typedef struct tdTPM_CMK_AUTH{\r
- TPM_DIGEST migrationAuthorityDigest;\r
- TPM_DIGEST destinationKeyDigest;\r
- TPM_DIGEST sourceKeyDigest;\r
+typedef struct tdTPM_CMK_AUTH {\r
+ TPM_DIGEST migrationAuthorityDigest;\r
+ TPM_DIGEST destinationKeyDigest;\r
+ TPM_DIGEST sourceKeyDigest;\r
} TPM_CMK_AUTH;\r
\r
//\r
// Part 2, section 5.17: TPM_CMK_DELEGATE\r
//\r
-#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31)\r
-#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30)\r
-#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29)\r
-#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28)\r
-#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27)\r
+#define TPM_CMK_DELEGATE_SIGNING ((TPM_CMK_DELEGATE) BIT31)\r
+#define TPM_CMK_DELEGATE_STORAGE ((TPM_CMK_DELEGATE) BIT30)\r
+#define TPM_CMK_DELEGATE_BIND ((TPM_CMK_DELEGATE) BIT29)\r
+#define TPM_CMK_DELEGATE_LEGACY ((TPM_CMK_DELEGATE) BIT28)\r
+#define TPM_CMK_DELEGATE_MIGRATE ((TPM_CMK_DELEGATE) BIT27)\r
\r
///\r
/// Part 2, section 5.18: TPM_SELECT_SIZE\r
///\r
typedef struct tdTPM_SELECT_SIZE {\r
- UINT8 major;\r
- UINT8 minor;\r
- UINT16 reqSize;\r
+ UINT8 major;\r
+ UINT8 minor;\r
+ UINT16 reqSize;\r
} TPM_SELECT_SIZE;\r
\r
///\r
/// Part 2, section 5,19: TPM_CMK_MIGAUTH\r
///\r
-typedef struct tdTPM_CMK_MIGAUTH{\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST msaDigest;\r
- TPM_DIGEST pubKeyDigest;\r
+typedef struct tdTPM_CMK_MIGAUTH {\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST msaDigest;\r
+ TPM_DIGEST pubKeyDigest;\r
} TPM_CMK_MIGAUTH;\r
\r
///\r
/// Part 2, section 5.20: TPM_CMK_SIGTICKET\r
///\r
-typedef struct tdTPM_CMK_SIGTICKET{\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST verKeyDigest;\r
- TPM_DIGEST signedData;\r
+typedef struct tdTPM_CMK_SIGTICKET {\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST verKeyDigest;\r
+ TPM_DIGEST signedData;\r
} TPM_CMK_SIGTICKET;\r
\r
///\r
/// Part 2, section 5.21: TPM_CMK_MA_APPROVAL\r
///\r
-typedef struct tdTPM_CMK_MA_APPROVAL{\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST migrationAuthorityDigest;\r
+typedef struct tdTPM_CMK_MA_APPROVAL {\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST migrationAuthorityDigest;\r
} TPM_CMK_MA_APPROVAL;\r
\r
//\r
// Part 2, section 6: Command Tags\r
//\r
-#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)\r
-#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)\r
-#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)\r
-#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)\r
-#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)\r
-#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)\r
+#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1)\r
+#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2)\r
+#define TPM_TAG_RQU_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C3)\r
+#define TPM_TAG_RSP_COMMAND ((TPM_STRUCTURE_TAG) 0x00C4)\r
+#define TPM_TAG_RSP_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C5)\r
+#define TPM_TAG_RSP_AUTH2_COMMAND ((TPM_STRUCTURE_TAG) 0x00C6)\r
\r
///\r
/// Part 2, section 7.1: TPM_PERMANENT_FLAGS\r
///\r
-typedef struct tdTPM_PERMANENT_FLAGS{\r
- TPM_STRUCTURE_TAG tag;\r
- BOOLEAN disable;\r
- BOOLEAN ownership;\r
- BOOLEAN deactivated;\r
- BOOLEAN readPubek;\r
- BOOLEAN disableOwnerClear;\r
- BOOLEAN allowMaintenance;\r
- BOOLEAN physicalPresenceLifetimeLock;\r
- BOOLEAN physicalPresenceHWEnable;\r
- BOOLEAN physicalPresenceCMDEnable;\r
- BOOLEAN CEKPUsed;\r
- BOOLEAN TPMpost;\r
- BOOLEAN TPMpostLock;\r
- BOOLEAN FIPS;\r
+typedef struct tdTPM_PERMANENT_FLAGS {\r
+ TPM_STRUCTURE_TAG tag;\r
+ BOOLEAN disable;\r
+ BOOLEAN ownership;\r
+ BOOLEAN deactivated;\r
+ BOOLEAN readPubek;\r
+ BOOLEAN disableOwnerClear;\r
+ BOOLEAN allowMaintenance;\r
+ BOOLEAN physicalPresenceLifetimeLock;\r
+ BOOLEAN physicalPresenceHWEnable;\r
+ BOOLEAN physicalPresenceCMDEnable;\r
+ BOOLEAN CEKPUsed;\r
+ BOOLEAN TPMpost;\r
+ BOOLEAN TPMpostLock;\r
+ BOOLEAN FIPS;\r
BOOLEAN operator;\r
BOOLEAN enableRevokeEK;\r
- BOOLEAN nvLocked;\r
- BOOLEAN readSRKPub;\r
- BOOLEAN tpmEstablished;\r
- BOOLEAN maintenanceDone;\r
- BOOLEAN disableFullDALogicInfo;\r
+ BOOLEAN nvLocked;\r
+ BOOLEAN readSRKPub;\r
+ BOOLEAN tpmEstablished;\r
+ BOOLEAN maintenanceDone;\r
+ BOOLEAN disableFullDALogicInfo;\r
} TPM_PERMANENT_FLAGS;\r
\r
//\r
// Part 2, section 7.1.1: Flag Restrictions (of TPM_PERMANENT_FLAGS)\r
//\r
-#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)\r
-#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)\r
-#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)\r
-#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)\r
-#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)\r
-#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)\r
-#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)\r
-#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)\r
-#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)\r
-#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)\r
-#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)\r
-#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)\r
-#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)\r
-#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)\r
-#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)\r
-#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)\r
-#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)\r
-#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)\r
-#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)\r
-#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20)\r
+#define TPM_PF_DISABLE ((TPM_CAPABILITY_AREA) 1)\r
+#define TPM_PF_OWNERSHIP ((TPM_CAPABILITY_AREA) 2)\r
+#define TPM_PF_DEACTIVATED ((TPM_CAPABILITY_AREA) 3)\r
+#define TPM_PF_READPUBEK ((TPM_CAPABILITY_AREA) 4)\r
+#define TPM_PF_DISABLEOWNERCLEAR ((TPM_CAPABILITY_AREA) 5)\r
+#define TPM_PF_ALLOWMAINTENANCE ((TPM_CAPABILITY_AREA) 6)\r
+#define TPM_PF_PHYSICALPRESENCELIFETIMELOCK ((TPM_CAPABILITY_AREA) 7)\r
+#define TPM_PF_PHYSICALPRESENCEHWENABLE ((TPM_CAPABILITY_AREA) 8)\r
+#define TPM_PF_PHYSICALPRESENCECMDENABLE ((TPM_CAPABILITY_AREA) 9)\r
+#define TPM_PF_CEKPUSED ((TPM_CAPABILITY_AREA) 10)\r
+#define TPM_PF_TPMPOST ((TPM_CAPABILITY_AREA) 11)\r
+#define TPM_PF_TPMPOSTLOCK ((TPM_CAPABILITY_AREA) 12)\r
+#define TPM_PF_FIPS ((TPM_CAPABILITY_AREA) 13)\r
+#define TPM_PF_OPERATOR ((TPM_CAPABILITY_AREA) 14)\r
+#define TPM_PF_ENABLEREVOKEEK ((TPM_CAPABILITY_AREA) 15)\r
+#define TPM_PF_NV_LOCKED ((TPM_CAPABILITY_AREA) 16)\r
+#define TPM_PF_READSRKPUB ((TPM_CAPABILITY_AREA) 17)\r
+#define TPM_PF_TPMESTABLISHED ((TPM_CAPABILITY_AREA) 18)\r
+#define TPM_PF_MAINTENANCEDONE ((TPM_CAPABILITY_AREA) 19)\r
+#define TPM_PF_DISABLEFULLDALOGICINFO ((TPM_CAPABILITY_AREA) 20)\r
\r
///\r
/// Part 2, section 7.2: TPM_STCLEAR_FLAGS\r
///\r
-typedef struct tdTPM_STCLEAR_FLAGS{\r
- TPM_STRUCTURE_TAG tag;\r
- BOOLEAN deactivated;\r
- BOOLEAN disableForceClear;\r
- BOOLEAN physicalPresence;\r
- BOOLEAN physicalPresenceLock;\r
- BOOLEAN bGlobalLock;\r
+typedef struct tdTPM_STCLEAR_FLAGS {\r
+ TPM_STRUCTURE_TAG tag;\r
+ BOOLEAN deactivated;\r
+ BOOLEAN disableForceClear;\r
+ BOOLEAN physicalPresence;\r
+ BOOLEAN physicalPresenceLock;\r
+ BOOLEAN bGlobalLock;\r
} TPM_STCLEAR_FLAGS;\r
\r
//\r
// Part 2, section 7.2.1: Flag Restrictions (of TPM_STCLEAR_FLAGS)\r
//\r
-#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)\r
-#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)\r
-#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)\r
-#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)\r
-#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)\r
+#define TPM_SF_DEACTIVATED ((TPM_CAPABILITY_AREA) 1)\r
+#define TPM_SF_DISABLEFORCECLEAR ((TPM_CAPABILITY_AREA) 2)\r
+#define TPM_SF_PHYSICALPRESENCE ((TPM_CAPABILITY_AREA) 3)\r
+#define TPM_SF_PHYSICALPRESENCELOCK ((TPM_CAPABILITY_AREA) 4)\r
+#define TPM_SF_BGLOBALLOCK ((TPM_CAPABILITY_AREA) 5)\r
\r
///\r
/// Part 2, section 7.3: TPM_STANY_FLAGS\r
///\r
-typedef struct tdTPM_STANY_FLAGS{\r
- TPM_STRUCTURE_TAG tag;\r
- BOOLEAN postInitialise;\r
- TPM_MODIFIER_INDICATOR localityModifier;\r
- BOOLEAN transportExclusive;\r
- BOOLEAN TOSPresent;\r
+typedef struct tdTPM_STANY_FLAGS {\r
+ TPM_STRUCTURE_TAG tag;\r
+ BOOLEAN postInitialise;\r
+ TPM_MODIFIER_INDICATOR localityModifier;\r
+ BOOLEAN transportExclusive;\r
+ BOOLEAN TOSPresent;\r
} TPM_STANY_FLAGS;\r
\r
//\r
// Part 2, section 7.3.1: Flag Restrictions (of TPM_STANY_FLAGS)\r
//\r
-#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)\r
-#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)\r
-#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)\r
-#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)\r
+#define TPM_AF_POSTINITIALISE ((TPM_CAPABILITY_AREA) 1)\r
+#define TPM_AF_LOCALITYMODIFIER ((TPM_CAPABILITY_AREA) 2)\r
+#define TPM_AF_TRANSPORTEXCLUSIVE ((TPM_CAPABILITY_AREA) 3)\r
+#define TPM_AF_TOSPRESENT ((TPM_CAPABILITY_AREA) 4)\r
\r
//\r
// All those structures defined in section 7.4, 7.5, 7.6 are not normative and\r
//\r
// Part 2, section 7.4: TPM_PERMANENT_DATA\r
//\r
-#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4\r
-#define TPM_DELEGATE_KEY TPM_KEY\r
-#define TPM_NUM_PCR 16\r
-#define TPM_MAX_NV_WRITE_NOOWNER 64\r
+#define TPM_MIN_COUNTERS 4 ///< the minimum number of counters is 4\r
+#define TPM_DELEGATE_KEY TPM_KEY\r
+#define TPM_NUM_PCR 16\r
+#define TPM_MAX_NV_WRITE_NOOWNER 64\r
\r
//\r
// Part 2, section 7.4.1: PERMANENT_DATA Subcap for SetCapability\r
/// Part 2, section 7.5: TPM_STCLEAR_DATA\r
/// available inside TPM only\r
///\r
- typedef struct tdTPM_STCLEAR_DATA{\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_NONCE contextNonceKey;\r
- TPM_COUNT_ID countID;\r
- UINT32 ownerReference;\r
- BOOLEAN disableResetLock;\r
- TPM_PCRVALUE PCR[TPM_NUM_PCR];\r
- UINT32 deferredPhysicalPresence;\r
- }TPM_STCLEAR_DATA;\r
+typedef struct tdTPM_STCLEAR_DATA {\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_NONCE contextNonceKey;\r
+ TPM_COUNT_ID countID;\r
+ UINT32 ownerReference;\r
+ BOOLEAN disableResetLock;\r
+ TPM_PCRVALUE PCR[TPM_NUM_PCR];\r
+ UINT32 deferredPhysicalPresence;\r
+} TPM_STCLEAR_DATA;\r
\r
//\r
// Part 2, section 7.5.1: STCLEAR_DATA Subcap for SetCapability\r
//\r
-#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001)\r
-#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002)\r
-#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003)\r
-#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004)\r
-#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005)\r
-#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006)\r
+#define TPM_SD_CONTEXTNONCEKEY ((TPM_CAPABILITY_AREA)0x00000001)\r
+#define TPM_SD_COUNTID ((TPM_CAPABILITY_AREA)0x00000002)\r
+#define TPM_SD_OWNERREFERENCE ((TPM_CAPABILITY_AREA)0x00000003)\r
+#define TPM_SD_DISABLERESETLOCK ((TPM_CAPABILITY_AREA)0x00000004)\r
+#define TPM_SD_PCR ((TPM_CAPABILITY_AREA)0x00000005)\r
+#define TPM_SD_DEFERREDPHYSICALPRESENCE ((TPM_CAPABILITY_AREA)0x00000006)\r
\r
//\r
// Part 2, section 7.6.1: STANY_DATA Subcap for SetCapability\r
//\r
-#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1)\r
-#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2)\r
-#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3)\r
-#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4)\r
-#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5)\r
-#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6)\r
+#define TPM_AD_CONTEXTNONCESESSION ((TPM_CAPABILITY_AREA) 1)\r
+#define TPM_AD_AUDITDIGEST ((TPM_CAPABILITY_AREA) 2)\r
+#define TPM_AD_CURRENTTICKS ((TPM_CAPABILITY_AREA) 3)\r
+#define TPM_AD_CONTEXTCOUNT ((TPM_CAPABILITY_AREA) 4)\r
+#define TPM_AD_CONTEXTLIST ((TPM_CAPABILITY_AREA) 5)\r
+#define TPM_AD_SESSIONS ((TPM_CAPABILITY_AREA) 6)\r
\r
//\r
// Part 2, section 8: PCR Structures\r
/// Size of pcrSelect[] indicated by sizeOfSelect\r
///\r
typedef struct tdTPM_PCR_SELECTION {\r
- UINT16 sizeOfSelect;\r
- UINT8 pcrSelect[1];\r
+ UINT16 sizeOfSelect;\r
+ UINT8 pcrSelect[1];\r
} TPM_PCR_SELECTION;\r
\r
///\r
/// Size of pcrValue[] indicated by valueSize\r
///\r
typedef struct tdTPM_PCR_COMPOSITE {\r
- TPM_PCR_SELECTION select;\r
- UINT32 valueSize;\r
- TPM_PCRVALUE pcrValue[1];\r
+ TPM_PCR_SELECTION select;\r
+ UINT32 valueSize;\r
+ TPM_PCRVALUE pcrValue[1];\r
} TPM_PCR_COMPOSITE;\r
\r
///\r
/// Part 2, section 8.3: TPM_PCR_INFO\r
///\r
typedef struct tdTPM_PCR_INFO {\r
- TPM_PCR_SELECTION pcrSelection;\r
- TPM_COMPOSITE_HASH digestAtRelease;\r
- TPM_COMPOSITE_HASH digestAtCreation;\r
+ TPM_PCR_SELECTION pcrSelection;\r
+ TPM_COMPOSITE_HASH digestAtRelease;\r
+ TPM_COMPOSITE_HASH digestAtCreation;\r
} TPM_PCR_INFO;\r
\r
///\r
/// Part 2, section 8.6: TPM_LOCALITY_SELECTION\r
///\r
-typedef UINT8 TPM_LOCALITY_SELECTION;\r
+typedef UINT8 TPM_LOCALITY_SELECTION;\r
\r
-#define TPM_LOC_FOUR ((UINT8) 0x10)\r
-#define TPM_LOC_THREE ((UINT8) 0x08)\r
-#define TPM_LOC_TWO ((UINT8) 0x04)\r
-#define TPM_LOC_ONE ((UINT8) 0x02)\r
-#define TPM_LOC_ZERO ((UINT8) 0x01)\r
+#define TPM_LOC_FOUR ((UINT8) 0x10)\r
+#define TPM_LOC_THREE ((UINT8) 0x08)\r
+#define TPM_LOC_TWO ((UINT8) 0x04)\r
+#define TPM_LOC_ONE ((UINT8) 0x02)\r
+#define TPM_LOC_ZERO ((UINT8) 0x01)\r
\r
///\r
/// Part 2, section 8.4: TPM_PCR_INFO_LONG\r
///\r
typedef struct tdTPM_PCR_INFO_LONG {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_LOCALITY_SELECTION localityAtCreation;\r
- TPM_LOCALITY_SELECTION localityAtRelease;\r
- TPM_PCR_SELECTION creationPCRSelection;\r
- TPM_PCR_SELECTION releasePCRSelection;\r
- TPM_COMPOSITE_HASH digestAtCreation;\r
- TPM_COMPOSITE_HASH digestAtRelease;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_LOCALITY_SELECTION localityAtCreation;\r
+ TPM_LOCALITY_SELECTION localityAtRelease;\r
+ TPM_PCR_SELECTION creationPCRSelection;\r
+ TPM_PCR_SELECTION releasePCRSelection;\r
+ TPM_COMPOSITE_HASH digestAtCreation;\r
+ TPM_COMPOSITE_HASH digestAtRelease;\r
} TPM_PCR_INFO_LONG;\r
\r
///\r
/// Part 2, section 8.5: TPM_PCR_INFO_SHORT\r
///\r
-typedef struct tdTPM_PCR_INFO_SHORT{\r
- TPM_PCR_SELECTION pcrSelection;\r
- TPM_LOCALITY_SELECTION localityAtRelease;\r
- TPM_COMPOSITE_HASH digestAtRelease;\r
+typedef struct tdTPM_PCR_INFO_SHORT {\r
+ TPM_PCR_SELECTION pcrSelection;\r
+ TPM_LOCALITY_SELECTION localityAtRelease;\r
+ TPM_COMPOSITE_HASH digestAtRelease;\r
} TPM_PCR_INFO_SHORT;\r
\r
///\r
/// Part 2, section 8.8: TPM_PCR_ATTRIBUTES\r
///\r
-typedef struct tdTPM_PCR_ATTRIBUTES{\r
- BOOLEAN pcrReset;\r
- TPM_LOCALITY_SELECTION pcrExtendLocal;\r
- TPM_LOCALITY_SELECTION pcrResetLocal;\r
+typedef struct tdTPM_PCR_ATTRIBUTES {\r
+ BOOLEAN pcrReset;\r
+ TPM_LOCALITY_SELECTION pcrExtendLocal;\r
+ TPM_LOCALITY_SELECTION pcrResetLocal;\r
} TPM_PCR_ATTRIBUTES;\r
\r
//\r
/// [size_is(encDataSize)] BYTE* encData;\r
///\r
typedef struct tdTPM_STORED_DATA {\r
- TPM_STRUCT_VER ver;\r
- UINT32 sealInfoSize;\r
- UINT8 *sealInfo;\r
- UINT32 encDataSize;\r
- UINT8 *encData;\r
+ TPM_STRUCT_VER ver;\r
+ UINT32 sealInfoSize;\r
+ UINT8 *sealInfo;\r
+ UINT32 encDataSize;\r
+ UINT8 *encData;\r
} TPM_STORED_DATA;\r
\r
///\r
/// [size_is(encDataSize)] BYTE* encData;\r
///\r
typedef struct tdTPM_STORED_DATA12 {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_ENTITY_TYPE et;\r
- UINT32 sealInfoSize;\r
- UINT8 *sealInfo;\r
- UINT32 encDataSize;\r
- UINT8 *encData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_ENTITY_TYPE et;\r
+ UINT32 sealInfoSize;\r
+ UINT8 *sealInfo;\r
+ UINT32 encDataSize;\r
+ UINT8 *encData;\r
} TPM_STORED_DATA12;\r
\r
///\r
/// [size_is(dataSize)] BYTE* data;\r
///\r
typedef struct tdTPM_SEALED_DATA {\r
- TPM_PAYLOAD_TYPE payload;\r
- TPM_SECRET authData;\r
- TPM_NONCE tpmProof;\r
- TPM_DIGEST storedDigest;\r
- UINT32 dataSize;\r
- UINT8 *data;\r
+ TPM_PAYLOAD_TYPE payload;\r
+ TPM_SECRET authData;\r
+ TPM_NONCE tpmProof;\r
+ TPM_DIGEST storedDigest;\r
+ UINT32 dataSize;\r
+ UINT8 *data;\r
} TPM_SEALED_DATA;\r
\r
///\r
/// [size_is(size)] BYTE* data;\r
///\r
typedef struct tdTPM_SYMMETRIC_KEY {\r
- TPM_ALGORITHM_ID algId;\r
- TPM_ENC_SCHEME encScheme;\r
- UINT16 dataSize;\r
- UINT8 *data;\r
+ TPM_ALGORITHM_ID algId;\r
+ TPM_ENC_SCHEME encScheme;\r
+ UINT16 dataSize;\r
+ UINT8 *data;\r
} TPM_SYMMETRIC_KEY;\r
\r
///\r
/// Part 2, section 9.5: TPM_BOUND_DATA\r
///\r
typedef struct tdTPM_BOUND_DATA {\r
- TPM_STRUCT_VER ver;\r
- TPM_PAYLOAD_TYPE payload;\r
- UINT8 payloadData[1];\r
+ TPM_STRUCT_VER ver;\r
+ TPM_PAYLOAD_TYPE payload;\r
+ UINT8 payloadData[1];\r
} TPM_BOUND_DATA;\r
\r
//\r
/// Part 2, section 10.2: TPM_KEY\r
/// [size_is(encDataSize)] BYTE* encData;\r
///\r
-typedef struct tdTPM_KEY{\r
- TPM_STRUCT_VER ver;\r
- TPM_KEY_USAGE keyUsage;\r
- TPM_KEY_FLAGS keyFlags;\r
- TPM_AUTH_DATA_USAGE authDataUsage;\r
- TPM_KEY_PARMS algorithmParms;\r
- UINT32 PCRInfoSize;\r
- UINT8 *PCRInfo;\r
- TPM_STORE_PUBKEY pubKey;\r
- UINT32 encDataSize;\r
- UINT8 *encData;\r
+typedef struct tdTPM_KEY {\r
+ TPM_STRUCT_VER ver;\r
+ TPM_KEY_USAGE keyUsage;\r
+ TPM_KEY_FLAGS keyFlags;\r
+ TPM_AUTH_DATA_USAGE authDataUsage;\r
+ TPM_KEY_PARMS algorithmParms;\r
+ UINT32 PCRInfoSize;\r
+ UINT8 *PCRInfo;\r
+ TPM_STORE_PUBKEY pubKey;\r
+ UINT32 encDataSize;\r
+ UINT8 *encData;\r
} TPM_KEY;\r
\r
///\r
/// Part 2, section 10.3: TPM_KEY12\r
/// [size_is(encDataSize)] BYTE* encData;\r
///\r
-typedef struct tdTPM_KEY12{\r
- TPM_STRUCTURE_TAG tag;\r
- UINT16 fill;\r
- TPM_KEY_USAGE keyUsage;\r
- TPM_KEY_FLAGS keyFlags;\r
- TPM_AUTH_DATA_USAGE authDataUsage;\r
- TPM_KEY_PARMS algorithmParms;\r
- UINT32 PCRInfoSize;\r
- UINT8 *PCRInfo;\r
- TPM_STORE_PUBKEY pubKey;\r
- UINT32 encDataSize;\r
- UINT8 *encData;\r
+typedef struct tdTPM_KEY12 {\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT16 fill;\r
+ TPM_KEY_USAGE keyUsage;\r
+ TPM_KEY_FLAGS keyFlags;\r
+ TPM_AUTH_DATA_USAGE authDataUsage;\r
+ TPM_KEY_PARMS algorithmParms;\r
+ UINT32 PCRInfoSize;\r
+ UINT8 *PCRInfo;\r
+ TPM_STORE_PUBKEY pubKey;\r
+ UINT32 encDataSize;\r
+ UINT8 *encData;\r
} TPM_KEY12;\r
\r
///\r
/// [size_is(keyLength)] BYTE* key;\r
///\r
typedef struct tdTPM_STORE_PRIVKEY {\r
- UINT32 keyLength;\r
- UINT8 *key;\r
+ UINT32 keyLength;\r
+ UINT8 *key;\r
} TPM_STORE_PRIVKEY;\r
\r
///\r
/// Part 2, section 10.6: TPM_STORE_ASYMKEY\r
///\r
-typedef struct tdTPM_STORE_ASYMKEY { // pos len total\r
- TPM_PAYLOAD_TYPE payload; // 0 1 1\r
- TPM_SECRET usageAuth; // 1 20 21\r
- TPM_SECRET migrationAuth; // 21 20 41\r
- TPM_DIGEST pubDataDigest; // 41 20 61\r
- TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214\r
+typedef struct tdTPM_STORE_ASYMKEY {\r
+ // pos len total\r
+ TPM_PAYLOAD_TYPE payload; // 0 1 1\r
+ TPM_SECRET usageAuth; // 1 20 21\r
+ TPM_SECRET migrationAuth; // 21 20 41\r
+ TPM_DIGEST pubDataDigest; // 41 20 61\r
+ TPM_STORE_PRIVKEY privKey; // 61 132-151 193-214\r
} TPM_STORE_ASYMKEY;\r
\r
///\r
/// Part 2, section 10.8: TPM_MIGRATE_ASYMKEY\r
/// [size_is(partPrivKeyLen)] BYTE* partPrivKey;\r
///\r
-typedef struct tdTPM_MIGRATE_ASYMKEY { // pos len total\r
- TPM_PAYLOAD_TYPE payload; // 0 1 1\r
- TPM_SECRET usageAuth; // 1 20 21\r
- TPM_DIGEST pubDataDigest; // 21 20 41\r
- UINT32 partPrivKeyLen; // 41 4 45\r
- UINT8 *partPrivKey; // 45 112-127 157-172\r
+typedef struct tdTPM_MIGRATE_ASYMKEY {\r
+ // pos len total\r
+ TPM_PAYLOAD_TYPE payload; // 0 1 1\r
+ TPM_SECRET usageAuth; // 1 20 21\r
+ TPM_DIGEST pubDataDigest; // 21 20 41\r
+ UINT32 partPrivKeyLen; // 41 4 45\r
+ UINT8 *partPrivKey; // 45 112-127 157-172\r
} TPM_MIGRATE_ASYMKEY;\r
\r
///\r
/// Part 2, section 10.9: TPM_KEY_CONTROL\r
///\r
-#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)\r
+#define TPM_KEY_CONTROL_OWNER_EVICT ((UINT32) 0x00000001)\r
\r
//\r
// Part 2, section 11: Signed Structures\r
/// Part 2, section 11.1: TPM_CERTIFY_INFO Structure\r
///\r
typedef struct tdTPM_CERTIFY_INFO {\r
- TPM_STRUCT_VER version;\r
- TPM_KEY_USAGE keyUsage;\r
- TPM_KEY_FLAGS keyFlags;\r
- TPM_AUTH_DATA_USAGE authDataUsage;\r
- TPM_KEY_PARMS algorithmParms;\r
- TPM_DIGEST pubkeyDigest;\r
- TPM_NONCE data;\r
- BOOLEAN parentPCRStatus;\r
- UINT32 PCRInfoSize;\r
- UINT8 *PCRInfo;\r
+ TPM_STRUCT_VER version;\r
+ TPM_KEY_USAGE keyUsage;\r
+ TPM_KEY_FLAGS keyFlags;\r
+ TPM_AUTH_DATA_USAGE authDataUsage;\r
+ TPM_KEY_PARMS algorithmParms;\r
+ TPM_DIGEST pubkeyDigest;\r
+ TPM_NONCE data;\r
+ BOOLEAN parentPCRStatus;\r
+ UINT32 PCRInfoSize;\r
+ UINT8 *PCRInfo;\r
} TPM_CERTIFY_INFO;\r
\r
///\r
/// Part 2, section 11.2: TPM_CERTIFY_INFO2 Structure\r
///\r
typedef struct tdTPM_CERTIFY_INFO2 {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT8 fill;\r
- TPM_PAYLOAD_TYPE payloadType;\r
- TPM_KEY_USAGE keyUsage;\r
- TPM_KEY_FLAGS keyFlags;\r
- TPM_AUTH_DATA_USAGE authDataUsage;\r
- TPM_KEY_PARMS algorithmParms;\r
- TPM_DIGEST pubkeyDigest;\r
- TPM_NONCE data;\r
- BOOLEAN parentPCRStatus;\r
- UINT32 PCRInfoSize;\r
- UINT8 *PCRInfo;\r
- UINT32 migrationAuthoritySize;\r
- UINT8 *migrationAuthority;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT8 fill;\r
+ TPM_PAYLOAD_TYPE payloadType;\r
+ TPM_KEY_USAGE keyUsage;\r
+ TPM_KEY_FLAGS keyFlags;\r
+ TPM_AUTH_DATA_USAGE authDataUsage;\r
+ TPM_KEY_PARMS algorithmParms;\r
+ TPM_DIGEST pubkeyDigest;\r
+ TPM_NONCE data;\r
+ BOOLEAN parentPCRStatus;\r
+ UINT32 PCRInfoSize;\r
+ UINT8 *PCRInfo;\r
+ UINT32 migrationAuthoritySize;\r
+ UINT8 *migrationAuthority;\r
} TPM_CERTIFY_INFO2;\r
\r
///\r
/// Part 2, section 11.3 TPM_QUOTE_INFO Structure\r
///\r
typedef struct tdTPM_QUOTE_INFO {\r
- TPM_STRUCT_VER version;\r
- UINT8 fixed[4];\r
- TPM_COMPOSITE_HASH digestValue;\r
- TPM_NONCE externalData;\r
+ TPM_STRUCT_VER version;\r
+ UINT8 fixed[4];\r
+ TPM_COMPOSITE_HASH digestValue;\r
+ TPM_NONCE externalData;\r
} TPM_QUOTE_INFO;\r
\r
///\r
/// Part 2, section 11.4 TPM_QUOTE_INFO2 Structure\r
///\r
typedef struct tdTPM_QUOTE_INFO2 {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT8 fixed[4];\r
- TPM_NONCE externalData;\r
- TPM_PCR_INFO_SHORT infoShort;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT8 fixed[4];\r
+ TPM_NONCE externalData;\r
+ TPM_PCR_INFO_SHORT infoShort;\r
} TPM_QUOTE_INFO2;\r
\r
//\r
/// Part 2, section 12.1 TPM_EK_BLOB\r
///\r
typedef struct tdTPM_EK_BLOB {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_EK_TYPE ekType;\r
- UINT32 blobSize;\r
- UINT8 *blob;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_EK_TYPE ekType;\r
+ UINT32 blobSize;\r
+ UINT8 *blob;\r
} TPM_EK_BLOB;\r
\r
///\r
/// Part 2, section 12.2 TPM_EK_BLOB_ACTIVATE\r
///\r
typedef struct tdTPM_EK_BLOB_ACTIVATE {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_SYMMETRIC_KEY sessionKey;\r
- TPM_DIGEST idDigest;\r
- TPM_PCR_INFO_SHORT pcrInfo;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_SYMMETRIC_KEY sessionKey;\r
+ TPM_DIGEST idDigest;\r
+ TPM_PCR_INFO_SHORT pcrInfo;\r
} TPM_EK_BLOB_ACTIVATE;\r
\r
///\r
/// Part 2, section 12.3 TPM_EK_BLOB_AUTH\r
///\r
typedef struct tdTPM_EK_BLOB_AUTH {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_SECRET authValue;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_SECRET authValue;\r
} TPM_EK_BLOB_AUTH;\r
\r
-\r
///\r
/// Part 2, section 12.5 TPM_IDENTITY_CONTENTS\r
///\r
typedef struct tdTPM_IDENTITY_CONTENTS {\r
- TPM_STRUCT_VER ver;\r
- UINT32 ordinal;\r
- TPM_CHOSENID_HASH labelPrivCADigest;\r
- TPM_PUBKEY identityPubKey;\r
+ TPM_STRUCT_VER ver;\r
+ UINT32 ordinal;\r
+ TPM_CHOSENID_HASH labelPrivCADigest;\r
+ TPM_PUBKEY identityPubKey;\r
} TPM_IDENTITY_CONTENTS;\r
\r
///\r
/// Part 2, section 12.6 TPM_IDENTITY_REQ\r
///\r
typedef struct tdTPM_IDENTITY_REQ {\r
- UINT32 asymSize;\r
- UINT32 symSize;\r
- TPM_KEY_PARMS asymAlgorithm;\r
- TPM_KEY_PARMS symAlgorithm;\r
- UINT8 *asymBlob;\r
- UINT8 *symBlob;\r
+ UINT32 asymSize;\r
+ UINT32 symSize;\r
+ TPM_KEY_PARMS asymAlgorithm;\r
+ TPM_KEY_PARMS symAlgorithm;\r
+ UINT8 *asymBlob;\r
+ UINT8 *symBlob;\r
} TPM_IDENTITY_REQ;\r
\r
///\r
/// Part 2, section 12.7 TPM_IDENTITY_PROOF\r
///\r
typedef struct tdTPM_IDENTITY_PROOF {\r
- TPM_STRUCT_VER ver;\r
- UINT32 labelSize;\r
- UINT32 identityBindingSize;\r
- UINT32 endorsementSize;\r
- UINT32 platformSize;\r
- UINT32 conformanceSize;\r
- TPM_PUBKEY identityKey;\r
- UINT8 *labelArea;\r
- UINT8 *identityBinding;\r
- UINT8 *endorsementCredential;\r
- UINT8 *platformCredential;\r
- UINT8 *conformanceCredential;\r
+ TPM_STRUCT_VER ver;\r
+ UINT32 labelSize;\r
+ UINT32 identityBindingSize;\r
+ UINT32 endorsementSize;\r
+ UINT32 platformSize;\r
+ UINT32 conformanceSize;\r
+ TPM_PUBKEY identityKey;\r
+ UINT8 *labelArea;\r
+ UINT8 *identityBinding;\r
+ UINT8 *endorsementCredential;\r
+ UINT8 *platformCredential;\r
+ UINT8 *conformanceCredential;\r
} TPM_IDENTITY_PROOF;\r
\r
///\r
/// Part 2, section 12.8 TPM_ASYM_CA_CONTENTS\r
///\r
typedef struct tdTPM_ASYM_CA_CONTENTS {\r
- TPM_SYMMETRIC_KEY sessionKey;\r
- TPM_DIGEST idDigest;\r
+ TPM_SYMMETRIC_KEY sessionKey;\r
+ TPM_DIGEST idDigest;\r
} TPM_ASYM_CA_CONTENTS;\r
\r
///\r
/// Part 2, section 12.9 TPM_SYM_CA_ATTESTATION\r
///\r
typedef struct tdTPM_SYM_CA_ATTESTATION {\r
- UINT32 credSize;\r
- TPM_KEY_PARMS algorithm;\r
- UINT8 *credential;\r
+ UINT32 credSize;\r
+ TPM_KEY_PARMS algorithm;\r
+ UINT8 *credential;\r
} TPM_SYM_CA_ATTESTATION;\r
\r
///\r
/// Placed here out of order because definitions are used in section 13.\r
///\r
typedef struct tdTPM_CURRENT_TICKS {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT64 currentTicks;\r
- UINT16 tickRate;\r
- TPM_NONCE tickNonce;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT64 currentTicks;\r
+ UINT16 tickRate;\r
+ TPM_NONCE tickNonce;\r
} TPM_CURRENT_TICKS;\r
\r
///\r
/// Part 2, section 13.1: TPM _TRANSPORT_PUBLIC\r
///\r
typedef struct tdTPM_TRANSPORT_PUBLIC {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_TRANSPORT_ATTRIBUTES transAttributes;\r
- TPM_ALGORITHM_ID algId;\r
- TPM_ENC_SCHEME encScheme;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_TRANSPORT_ATTRIBUTES transAttributes;\r
+ TPM_ALGORITHM_ID algId;\r
+ TPM_ENC_SCHEME encScheme;\r
} TPM_TRANSPORT_PUBLIC;\r
\r
//\r
// Part 2, section 13.1.1 TPM_TRANSPORT_ATTRIBUTES Definitions\r
//\r
-#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0)\r
-#define TPM_TRANSPORT_LOG ((UINT32)BIT1)\r
-#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2)\r
+#define TPM_TRANSPORT_ENCRYPT ((UINT32)BIT0)\r
+#define TPM_TRANSPORT_LOG ((UINT32)BIT1)\r
+#define TPM_TRANSPORT_EXCLUSIVE ((UINT32)BIT2)\r
\r
///\r
/// Part 2, section 13.2 TPM_TRANSPORT_INTERNAL\r
///\r
typedef struct tdTPM_TRANSPORT_INTERNAL {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_AUTHDATA authData;\r
- TPM_TRANSPORT_PUBLIC transPublic;\r
- TPM_TRANSHANDLE transHandle;\r
- TPM_NONCE transNonceEven;\r
- TPM_DIGEST transDigest;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_AUTHDATA authData;\r
+ TPM_TRANSPORT_PUBLIC transPublic;\r
+ TPM_TRANSHANDLE transHandle;\r
+ TPM_NONCE transNonceEven;\r
+ TPM_DIGEST transDigest;\r
} TPM_TRANSPORT_INTERNAL;\r
\r
///\r
/// Part 2, section 13.3 TPM_TRANSPORT_LOG_IN structure\r
///\r
typedef struct tdTPM_TRANSPORT_LOG_IN {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST parameters;\r
- TPM_DIGEST pubKeyHash;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST parameters;\r
+ TPM_DIGEST pubKeyHash;\r
} TPM_TRANSPORT_LOG_IN;\r
\r
///\r
/// Part 2, section 13.4 TPM_TRANSPORT_LOG_OUT structure\r
///\r
typedef struct tdTPM_TRANSPORT_LOG_OUT {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_CURRENT_TICKS currentTicks;\r
- TPM_DIGEST parameters;\r
- TPM_MODIFIER_INDICATOR locality;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_CURRENT_TICKS currentTicks;\r
+ TPM_DIGEST parameters;\r
+ TPM_MODIFIER_INDICATOR locality;\r
} TPM_TRANSPORT_LOG_OUT;\r
\r
///\r
/// Part 2, section 13.5 TPM_TRANSPORT_AUTH structure\r
///\r
typedef struct tdTPM_TRANSPORT_AUTH {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_AUTHDATA authData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_AUTHDATA authData;\r
} TPM_TRANSPORT_AUTH;\r
\r
//\r
/// Part 2, section 14.1 TPM_AUDIT_EVENT_IN structure\r
///\r
typedef struct tdTPM_AUDIT_EVENT_IN {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST inputParms;\r
- TPM_COUNTER_VALUE auditCount;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST inputParms;\r
+ TPM_COUNTER_VALUE auditCount;\r
} TPM_AUDIT_EVENT_IN;\r
\r
///\r
/// Part 2, section 14.2 TPM_AUDIT_EVENT_OUT structure\r
///\r
typedef struct tdTPM_AUDIT_EVENT_OUT {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_COMMAND_CODE ordinal;\r
- TPM_DIGEST outputParms;\r
- TPM_COUNTER_VALUE auditCount;\r
- TPM_RESULT returnCode;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_COMMAND_CODE ordinal;\r
+ TPM_DIGEST outputParms;\r
+ TPM_COUNTER_VALUE auditCount;\r
+ TPM_RESULT returnCode;\r
} TPM_AUDIT_EVENT_OUT;\r
\r
//\r
// Part 2, section 16: Return Codes\r
//\r
\r
-#define TPM_VENDOR_ERROR TPM_Vendor_Specific32\r
-#define TPM_NON_FATAL 0x00000800\r
+#define TPM_VENDOR_ERROR TPM_Vendor_Specific32\r
+#define TPM_NON_FATAL 0x00000800\r
\r
#define TPM_SUCCESS ((TPM_RESULT) TPM_BASE)\r
#define TPM_AUTHFAIL ((TPM_RESULT) (TPM_BASE + 1))\r
#define TPM_BAD_SIGNATURE ((TPM_RESULT) (TPM_BASE + 98))\r
#define TPM_NOCONTEXTSPACE ((TPM_RESULT) (TPM_BASE + 99))\r
\r
-#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))\r
-#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))\r
-#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))\r
-#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))\r
+#define TPM_RETRY ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL))\r
+#define TPM_NEEDS_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 1))\r
+#define TPM_DOING_SELFTEST ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 2))\r
+#define TPM_DEFEND_LOCK_RUNNING ((TPM_RESULT) (TPM_BASE + TPM_NON_FATAL + 3))\r
\r
//\r
// Part 2, section 17: Ordinals\r
// * All reserved area bits are set to 0.\r
//\r
\r
-#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)\r
-#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)\r
-#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)\r
-#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)\r
-#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)\r
-#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)\r
-#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)\r
-#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)\r
-#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)\r
-#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)\r
-#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)\r
-#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)\r
-#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)\r
-#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)\r
-#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)\r
-#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)\r
-#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)\r
-#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)\r
-#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)\r
-#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)\r
-#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)\r
-#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)\r
-#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)\r
-#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)\r
-#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)\r
-#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)\r
-#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)\r
-#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)\r
-#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)\r
-#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)\r
-#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)\r
-#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)\r
-#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)\r
-#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)\r
-#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)\r
-#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)\r
-#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)\r
-#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)\r
-#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)\r
-#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)\r
-#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)\r
-#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)\r
-#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)\r
-#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)\r
-#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)\r
-#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)\r
-#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)\r
-#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)\r
-#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)\r
-#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)\r
-#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)\r
-#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)\r
-#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)\r
-#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)\r
-#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)\r
-#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)\r
-#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)\r
-#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)\r
-#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)\r
-#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)\r
-#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)\r
-#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)\r
-#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)\r
-#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)\r
-#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)\r
-#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)\r
-#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)\r
-#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)\r
-#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)\r
-#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)\r
-#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)\r
-#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)\r
-#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)\r
-#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)\r
-#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)\r
-#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)\r
-#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)\r
-#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)\r
-#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)\r
-#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)\r
-#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)\r
-#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)\r
-#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)\r
-#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)\r
-#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)\r
-#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)\r
-#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)\r
-#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)\r
-#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)\r
-#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)\r
-#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)\r
-#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)\r
-#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)\r
-#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)\r
-#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)\r
-#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)\r
-#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)\r
-#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)\r
-#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)\r
-#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)\r
-#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)\r
-#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)\r
-#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)\r
-#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)\r
-#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)\r
-#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)\r
-#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)\r
-#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)\r
-#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)\r
-#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)\r
-#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)\r
-#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)\r
-#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)\r
-#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)\r
-#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)\r
-#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)\r
-#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)\r
-#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)\r
-#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)\r
-#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)\r
-#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)\r
-#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)\r
-#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)\r
-#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)\r
-#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)\r
+#define TPM_ORD_ActivateIdentity ((TPM_COMMAND_CODE) 0x0000007A)\r
+#define TPM_ORD_AuthorizeMigrationKey ((TPM_COMMAND_CODE) 0x0000002B)\r
+#define TPM_ORD_CertifyKey ((TPM_COMMAND_CODE) 0x00000032)\r
+#define TPM_ORD_CertifyKey2 ((TPM_COMMAND_CODE) 0x00000033)\r
+#define TPM_ORD_CertifySelfTest ((TPM_COMMAND_CODE) 0x00000052)\r
+#define TPM_ORD_ChangeAuth ((TPM_COMMAND_CODE) 0x0000000C)\r
+#define TPM_ORD_ChangeAuthAsymFinish ((TPM_COMMAND_CODE) 0x0000000F)\r
+#define TPM_ORD_ChangeAuthAsymStart ((TPM_COMMAND_CODE) 0x0000000E)\r
+#define TPM_ORD_ChangeAuthOwner ((TPM_COMMAND_CODE) 0x00000010)\r
+#define TPM_ORD_CMK_ApproveMA ((TPM_COMMAND_CODE) 0x0000001D)\r
+#define TPM_ORD_CMK_ConvertMigration ((TPM_COMMAND_CODE) 0x00000024)\r
+#define TPM_ORD_CMK_CreateBlob ((TPM_COMMAND_CODE) 0x0000001B)\r
+#define TPM_ORD_CMK_CreateKey ((TPM_COMMAND_CODE) 0x00000013)\r
+#define TPM_ORD_CMK_CreateTicket ((TPM_COMMAND_CODE) 0x00000012)\r
+#define TPM_ORD_CMK_SetRestrictions ((TPM_COMMAND_CODE) 0x0000001C)\r
+#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053)\r
+#define TPM_ORD_ConvertMigrationBlob ((TPM_COMMAND_CODE) 0x0000002A)\r
+#define TPM_ORD_CreateCounter ((TPM_COMMAND_CODE) 0x000000DC)\r
+#define TPM_ORD_CreateEndorsementKeyPair ((TPM_COMMAND_CODE) 0x00000078)\r
+#define TPM_ORD_CreateMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002C)\r
+#define TPM_ORD_CreateMigrationBlob ((TPM_COMMAND_CODE) 0x00000028)\r
+#define TPM_ORD_CreateRevocableEK ((TPM_COMMAND_CODE) 0x0000007F)\r
+#define TPM_ORD_CreateWrapKey ((TPM_COMMAND_CODE) 0x0000001F)\r
+#define TPM_ORD_DAA_JOIN ((TPM_COMMAND_CODE) 0x00000029)\r
+#define TPM_ORD_DAA_SIGN ((TPM_COMMAND_CODE) 0x00000031)\r
+#define TPM_ORD_Delegate_CreateKeyDelegation ((TPM_COMMAND_CODE) 0x000000D4)\r
+#define TPM_ORD_Delegate_CreateOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D5)\r
+#define TPM_ORD_Delegate_LoadOwnerDelegation ((TPM_COMMAND_CODE) 0x000000D8)\r
+#define TPM_ORD_Delegate_Manage ((TPM_COMMAND_CODE) 0x000000D2)\r
+#define TPM_ORD_Delegate_ReadTable ((TPM_COMMAND_CODE) 0x000000DB)\r
+#define TPM_ORD_Delegate_UpdateVerification ((TPM_COMMAND_CODE) 0x000000D1)\r
+#define TPM_ORD_Delegate_VerifyDelegation ((TPM_COMMAND_CODE) 0x000000D6)\r
+#define TPM_ORD_DirRead ((TPM_COMMAND_CODE) 0x0000001A)\r
+#define TPM_ORD_DirWriteAuth ((TPM_COMMAND_CODE) 0x00000019)\r
+#define TPM_ORD_DisableForceClear ((TPM_COMMAND_CODE) 0x0000005E)\r
+#define TPM_ORD_DisableOwnerClear ((TPM_COMMAND_CODE) 0x0000005C)\r
+#define TPM_ORD_DisablePubekRead ((TPM_COMMAND_CODE) 0x0000007E)\r
+#define TPM_ORD_DSAP ((TPM_COMMAND_CODE) 0x00000011)\r
+#define TPM_ORD_EstablishTransport ((TPM_COMMAND_CODE) 0x000000E6)\r
+#define TPM_ORD_EvictKey ((TPM_COMMAND_CODE) 0x00000022)\r
+#define TPM_ORD_ExecuteTransport ((TPM_COMMAND_CODE) 0x000000E7)\r
+#define TPM_ORD_Extend ((TPM_COMMAND_CODE) 0x00000014)\r
+#define TPM_ORD_FieldUpgrade ((TPM_COMMAND_CODE) 0x000000AA)\r
+#define TPM_ORD_FlushSpecific ((TPM_COMMAND_CODE) 0x000000BA)\r
+#define TPM_ORD_ForceClear ((TPM_COMMAND_CODE) 0x0000005D)\r
+#define TPM_ORD_GetAuditDigest ((TPM_COMMAND_CODE) 0x00000085)\r
+#define TPM_ORD_GetAuditDigestSigned ((TPM_COMMAND_CODE) 0x00000086)\r
+#define TPM_ORD_GetAuditEvent ((TPM_COMMAND_CODE) 0x00000082)\r
+#define TPM_ORD_GetAuditEventSigned ((TPM_COMMAND_CODE) 0x00000083)\r
+#define TPM_ORD_GetCapability ((TPM_COMMAND_CODE) 0x00000065)\r
+#define TPM_ORD_GetCapabilityOwner ((TPM_COMMAND_CODE) 0x00000066)\r
+#define TPM_ORD_GetCapabilitySigned ((TPM_COMMAND_CODE) 0x00000064)\r
+#define TPM_ORD_GetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008C)\r
+#define TPM_ORD_GetPubKey ((TPM_COMMAND_CODE) 0x00000021)\r
+#define TPM_ORD_GetRandom ((TPM_COMMAND_CODE) 0x00000046)\r
+#define TPM_ORD_GetTestResult ((TPM_COMMAND_CODE) 0x00000054)\r
+#define TPM_ORD_GetTicks ((TPM_COMMAND_CODE) 0x000000F1)\r
+#define TPM_ORD_IncrementCounter ((TPM_COMMAND_CODE) 0x000000DD)\r
+#define TPM_ORD_Init ((TPM_COMMAND_CODE) 0x00000097)\r
+#define TPM_ORD_KeyControlOwner ((TPM_COMMAND_CODE) 0x00000023)\r
+#define TPM_ORD_KillMaintenanceFeature ((TPM_COMMAND_CODE) 0x0000002E)\r
+#define TPM_ORD_LoadAuthContext ((TPM_COMMAND_CODE) 0x000000B7)\r
+#define TPM_ORD_LoadContext ((TPM_COMMAND_CODE) 0x000000B9)\r
+#define TPM_ORD_LoadKey ((TPM_COMMAND_CODE) 0x00000020)\r
+#define TPM_ORD_LoadKey2 ((TPM_COMMAND_CODE) 0x00000041)\r
+#define TPM_ORD_LoadKeyContext ((TPM_COMMAND_CODE) 0x000000B5)\r
+#define TPM_ORD_LoadMaintenanceArchive ((TPM_COMMAND_CODE) 0x0000002D)\r
+#define TPM_ORD_LoadManuMaintPub ((TPM_COMMAND_CODE) 0x0000002F)\r
+#define TPM_ORD_MakeIdentity ((TPM_COMMAND_CODE) 0x00000079)\r
+#define TPM_ORD_MigrateKey ((TPM_COMMAND_CODE) 0x00000025)\r
+#define TPM_ORD_NV_DefineSpace ((TPM_COMMAND_CODE) 0x000000CC)\r
+#define TPM_ORD_NV_ReadValue ((TPM_COMMAND_CODE) 0x000000CF)\r
+#define TPM_ORD_NV_ReadValueAuth ((TPM_COMMAND_CODE) 0x000000D0)\r
+#define TPM_ORD_NV_WriteValue ((TPM_COMMAND_CODE) 0x000000CD)\r
+#define TPM_ORD_NV_WriteValueAuth ((TPM_COMMAND_CODE) 0x000000CE)\r
+#define TPM_ORD_OIAP ((TPM_COMMAND_CODE) 0x0000000A)\r
+#define TPM_ORD_OSAP ((TPM_COMMAND_CODE) 0x0000000B)\r
+#define TPM_ORD_OwnerClear ((TPM_COMMAND_CODE) 0x0000005B)\r
+#define TPM_ORD_OwnerReadInternalPub ((TPM_COMMAND_CODE) 0x00000081)\r
+#define TPM_ORD_OwnerReadPubek ((TPM_COMMAND_CODE) 0x0000007D)\r
+#define TPM_ORD_OwnerSetDisable ((TPM_COMMAND_CODE) 0x0000006E)\r
+#define TPM_ORD_PCR_Reset ((TPM_COMMAND_CODE) 0x000000C8)\r
+#define TPM_ORD_PcrRead ((TPM_COMMAND_CODE) 0x00000015)\r
+#define TPM_ORD_PhysicalDisable ((TPM_COMMAND_CODE) 0x00000070)\r
+#define TPM_ORD_PhysicalEnable ((TPM_COMMAND_CODE) 0x0000006F)\r
+#define TPM_ORD_PhysicalSetDeactivated ((TPM_COMMAND_CODE) 0x00000072)\r
+#define TPM_ORD_Quote ((TPM_COMMAND_CODE) 0x00000016)\r
+#define TPM_ORD_Quote2 ((TPM_COMMAND_CODE) 0x0000003E)\r
+#define TPM_ORD_ReadCounter ((TPM_COMMAND_CODE) 0x000000DE)\r
+#define TPM_ORD_ReadManuMaintPub ((TPM_COMMAND_CODE) 0x00000030)\r
+#define TPM_ORD_ReadPubek ((TPM_COMMAND_CODE) 0x0000007C)\r
+#define TPM_ORD_ReleaseCounter ((TPM_COMMAND_CODE) 0x000000DF)\r
+#define TPM_ORD_ReleaseCounterOwner ((TPM_COMMAND_CODE) 0x000000E0)\r
+#define TPM_ORD_ReleaseTransportSigned ((TPM_COMMAND_CODE) 0x000000E8)\r
+#define TPM_ORD_Reset ((TPM_COMMAND_CODE) 0x0000005A)\r
+#define TPM_ORD_ResetLockValue ((TPM_COMMAND_CODE) 0x00000040)\r
+#define TPM_ORD_RevokeTrust ((TPM_COMMAND_CODE) 0x00000080)\r
+#define TPM_ORD_SaveAuthContext ((TPM_COMMAND_CODE) 0x000000B6)\r
+#define TPM_ORD_SaveContext ((TPM_COMMAND_CODE) 0x000000B8)\r
+#define TPM_ORD_SaveKeyContext ((TPM_COMMAND_CODE) 0x000000B4)\r
+#define TPM_ORD_SaveState ((TPM_COMMAND_CODE) 0x00000098)\r
+#define TPM_ORD_Seal ((TPM_COMMAND_CODE) 0x00000017)\r
+#define TPM_ORD_Sealx ((TPM_COMMAND_CODE) 0x0000003D)\r
+#define TPM_ORD_SelfTestFull ((TPM_COMMAND_CODE) 0x00000050)\r
+#define TPM_ORD_SetCapability ((TPM_COMMAND_CODE) 0x0000003F)\r
+#define TPM_ORD_SetOperatorAuth ((TPM_COMMAND_CODE) 0x00000074)\r
+#define TPM_ORD_SetOrdinalAuditStatus ((TPM_COMMAND_CODE) 0x0000008D)\r
+#define TPM_ORD_SetOwnerInstall ((TPM_COMMAND_CODE) 0x00000071)\r
+#define TPM_ORD_SetOwnerPointer ((TPM_COMMAND_CODE) 0x00000075)\r
+#define TPM_ORD_SetRedirection ((TPM_COMMAND_CODE) 0x0000009A)\r
+#define TPM_ORD_SetTempDeactivated ((TPM_COMMAND_CODE) 0x00000073)\r
+#define TPM_ORD_SHA1Complete ((TPM_COMMAND_CODE) 0x000000A2)\r
+#define TPM_ORD_SHA1CompleteExtend ((TPM_COMMAND_CODE) 0x000000A3)\r
+#define TPM_ORD_SHA1Start ((TPM_COMMAND_CODE) 0x000000A0)\r
+#define TPM_ORD_SHA1Update ((TPM_COMMAND_CODE) 0x000000A1)\r
+#define TPM_ORD_Sign ((TPM_COMMAND_CODE) 0x0000003C)\r
+#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099)\r
+#define TPM_ORD_StirRandom ((TPM_COMMAND_CODE) 0x00000047)\r
+#define TPM_ORD_TakeOwnership ((TPM_COMMAND_CODE) 0x0000000D)\r
+#define TPM_ORD_Terminate_Handle ((TPM_COMMAND_CODE) 0x00000096)\r
+#define TPM_ORD_TickStampBlob ((TPM_COMMAND_CODE) 0x000000F2)\r
+#define TPM_ORD_UnBind ((TPM_COMMAND_CODE) 0x0000001E)\r
+#define TPM_ORD_Unseal ((TPM_COMMAND_CODE) 0x00000018)\r
+#define TSC_ORD_PhysicalPresence ((TPM_COMMAND_CODE) 0x4000000A)\r
+#define TSC_ORD_ResetEstablishmentBit ((TPM_COMMAND_CODE) 0x4000000B)\r
\r
//\r
// Part 2, section 18: Context structures\r
/// Part 2, section 18.1: TPM_CONTEXT_BLOB\r
///\r
typedef struct tdTPM_CONTEXT_BLOB {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_RESOURCE_TYPE resourceType;\r
- TPM_HANDLE handle;\r
- UINT8 label[16];\r
- UINT32 contextCount;\r
- TPM_DIGEST integrityDigest;\r
- UINT32 additionalSize;\r
- UINT8 *additionalData;\r
- UINT32 sensitiveSize;\r
- UINT8 *sensitiveData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_RESOURCE_TYPE resourceType;\r
+ TPM_HANDLE handle;\r
+ UINT8 label[16];\r
+ UINT32 contextCount;\r
+ TPM_DIGEST integrityDigest;\r
+ UINT32 additionalSize;\r
+ UINT8 *additionalData;\r
+ UINT32 sensitiveSize;\r
+ UINT8 *sensitiveData;\r
} TPM_CONTEXT_BLOB;\r
\r
///\r
/// Part 2, section 18.2 TPM_CONTEXT_SENSITIVE\r
///\r
typedef struct tdTPM_CONTEXT_SENSITIVE {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_NONCE contextNonce;\r
- UINT32 internalSize;\r
- UINT8 *internalData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_NONCE contextNonce;\r
+ UINT32 internalSize;\r
+ UINT8 *internalData;\r
} TPM_CONTEXT_SENSITIVE;\r
\r
//\r
//\r
// Part 2, section 19.1.1: Required TPM_NV_INDEX values\r
//\r
-#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)\r
-#define TPM_NV_INDEX0 ((UINT32)0x00000000)\r
-#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)\r
-#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)\r
-#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)\r
-#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)\r
-#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)\r
+#define TPM_NV_INDEX_LOCK ((UINT32)0xffffffff)\r
+#define TPM_NV_INDEX0 ((UINT32)0x00000000)\r
+#define TPM_NV_INDEX_DIR ((UINT32)0x10000001)\r
+#define TPM_NV_INDEX_EKCert ((UINT32)0x0000f000)\r
+#define TPM_NV_INDEX_TPM_CC ((UINT32)0x0000f001)\r
+#define TPM_NV_INDEX_PlatformCert ((UINT32)0x0000f002)\r
+#define TPM_NV_INDEX_Platform_CC ((UINT32)0x0000f003)\r
//\r
// Part 2, section 19.1.2: Reserved Index values\r
//\r
-#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)\r
-#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)\r
-#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)\r
-#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)\r
-#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)\r
-#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)\r
+#define TPM_NV_INDEX_TSS_BASE ((UINT32)0x00011100)\r
+#define TPM_NV_INDEX_PC_BASE ((UINT32)0x00011200)\r
+#define TPM_NV_INDEX_SERVER_BASE ((UINT32)0x00011300)\r
+#define TPM_NV_INDEX_MOBILE_BASE ((UINT32)0x00011400)\r
+#define TPM_NV_INDEX_PERIPHERAL_BASE ((UINT32)0x00011500)\r
+#define TPM_NV_INDEX_GROUP_RESV_BASE ((UINT32)0x00010000)\r
\r
///\r
/// Part 2, section 19.2: TPM_NV_ATTRIBUTES\r
///\r
typedef struct tdTPM_NV_ATTRIBUTES {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 attributes;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 attributes;\r
} TPM_NV_ATTRIBUTES;\r
\r
-#define TPM_NV_PER_READ_STCLEAR (BIT31)\r
-#define TPM_NV_PER_AUTHREAD (BIT18)\r
-#define TPM_NV_PER_OWNERREAD (BIT17)\r
-#define TPM_NV_PER_PPREAD (BIT16)\r
-#define TPM_NV_PER_GLOBALLOCK (BIT15)\r
-#define TPM_NV_PER_WRITE_STCLEAR (BIT14)\r
-#define TPM_NV_PER_WRITEDEFINE (BIT13)\r
-#define TPM_NV_PER_WRITEALL (BIT12)\r
-#define TPM_NV_PER_AUTHWRITE (BIT2)\r
-#define TPM_NV_PER_OWNERWRITE (BIT1)\r
-#define TPM_NV_PER_PPWRITE (BIT0)\r
+#define TPM_NV_PER_READ_STCLEAR (BIT31)\r
+#define TPM_NV_PER_AUTHREAD (BIT18)\r
+#define TPM_NV_PER_OWNERREAD (BIT17)\r
+#define TPM_NV_PER_PPREAD (BIT16)\r
+#define TPM_NV_PER_GLOBALLOCK (BIT15)\r
+#define TPM_NV_PER_WRITE_STCLEAR (BIT14)\r
+#define TPM_NV_PER_WRITEDEFINE (BIT13)\r
+#define TPM_NV_PER_WRITEALL (BIT12)\r
+#define TPM_NV_PER_AUTHWRITE (BIT2)\r
+#define TPM_NV_PER_OWNERWRITE (BIT1)\r
+#define TPM_NV_PER_PPWRITE (BIT0)\r
\r
///\r
/// Part 2, section 19.3: TPM_NV_DATA_PUBLIC\r
///\r
typedef struct tdTPM_NV_DATA_PUBLIC {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_NV_INDEX nvIndex;\r
- TPM_PCR_INFO_SHORT pcrInfoRead;\r
- TPM_PCR_INFO_SHORT pcrInfoWrite;\r
- TPM_NV_ATTRIBUTES permission;\r
- BOOLEAN bReadSTClear;\r
- BOOLEAN bWriteSTClear;\r
- BOOLEAN bWriteDefine;\r
- UINT32 dataSize;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_NV_INDEX nvIndex;\r
+ TPM_PCR_INFO_SHORT pcrInfoRead;\r
+ TPM_PCR_INFO_SHORT pcrInfoWrite;\r
+ TPM_NV_ATTRIBUTES permission;\r
+ BOOLEAN bReadSTClear;\r
+ BOOLEAN bWriteSTClear;\r
+ BOOLEAN bWriteDefine;\r
+ UINT32 dataSize;\r
} TPM_NV_DATA_PUBLIC;\r
\r
//\r
// Part 2, section 20: Delegate Structures\r
//\r
\r
-#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)\r
-#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)\r
+#define TPM_DEL_OWNER_BITS ((UINT32)0x00000001)\r
+#define TPM_DEL_KEY_BITS ((UINT32)0x00000002)\r
///\r
/// Part 2, section 20.2: Delegate Definitions\r
///\r
typedef struct tdTPM_DELEGATIONS {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 delegateType;\r
- UINT32 per1;\r
- UINT32 per2;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 delegateType;\r
+ UINT32 per1;\r
+ UINT32 per2;\r
} TPM_DELEGATIONS;\r
\r
//\r
// Part 2, section 20.2.1: Owner Permission Settings\r
//\r
-#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30)\r
-#define TPM_DELEGATE_DirWriteAuth (BIT29)\r
-#define TPM_DELEGATE_CMK_ApproveMA (BIT28)\r
-#define TPM_DELEGATE_NV_WriteValue (BIT27)\r
-#define TPM_DELEGATE_CMK_CreateTicket (BIT26)\r
-#define TPM_DELEGATE_NV_ReadValue (BIT25)\r
-#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24)\r
-#define TPM_DELEGATE_DAA_Join (BIT23)\r
-#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22)\r
-#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21)\r
-#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20)\r
-#define TPM_DELEGATE_KillMaintenanceFeature (BIT19)\r
-#define TPM_DELEGATE_OwnerReadInteralPub (BIT18)\r
-#define TPM_DELEGATE_ResetLockValue (BIT17)\r
-#define TPM_DELEGATE_OwnerClear (BIT16)\r
-#define TPM_DELEGATE_DisableOwnerClear (BIT15)\r
-#define TPM_DELEGATE_NV_DefineSpace (BIT14)\r
-#define TPM_DELEGATE_OwnerSetDisable (BIT13)\r
-#define TPM_DELEGATE_SetCapability (BIT12)\r
-#define TPM_DELEGATE_MakeIdentity (BIT11)\r
-#define TPM_DELEGATE_ActivateIdentity (BIT10)\r
-#define TPM_DELEGATE_OwnerReadPubek (BIT9)\r
-#define TPM_DELEGATE_DisablePubekRead (BIT8)\r
-#define TPM_DELEGATE_SetRedirection (BIT7)\r
-#define TPM_DELEGATE_FieldUpgrade (BIT6)\r
-#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5)\r
-#define TPM_DELEGATE_CreateCounter (BIT4)\r
-#define TPM_DELEGATE_ReleaseCounterOwner (BIT3)\r
-#define TPM_DELEGATE_DelegateManage (BIT2)\r
-#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)\r
-#define TPM_DELEGATE_DAA_Sign (BIT0)\r
+#define TPM_DELEGATE_SetOrdinalAuditStatus (BIT30)\r
+#define TPM_DELEGATE_DirWriteAuth (BIT29)\r
+#define TPM_DELEGATE_CMK_ApproveMA (BIT28)\r
+#define TPM_DELEGATE_NV_WriteValue (BIT27)\r
+#define TPM_DELEGATE_CMK_CreateTicket (BIT26)\r
+#define TPM_DELEGATE_NV_ReadValue (BIT25)\r
+#define TPM_DELEGATE_Delegate_LoadOwnerDelegation (BIT24)\r
+#define TPM_DELEGATE_DAA_Join (BIT23)\r
+#define TPM_DELEGATE_AuthorizeMigrationKey (BIT22)\r
+#define TPM_DELEGATE_CreateMaintenanceArchive (BIT21)\r
+#define TPM_DELEGATE_LoadMaintenanceArchive (BIT20)\r
+#define TPM_DELEGATE_KillMaintenanceFeature (BIT19)\r
+#define TPM_DELEGATE_OwnerReadInteralPub (BIT18)\r
+#define TPM_DELEGATE_ResetLockValue (BIT17)\r
+#define TPM_DELEGATE_OwnerClear (BIT16)\r
+#define TPM_DELEGATE_DisableOwnerClear (BIT15)\r
+#define TPM_DELEGATE_NV_DefineSpace (BIT14)\r
+#define TPM_DELEGATE_OwnerSetDisable (BIT13)\r
+#define TPM_DELEGATE_SetCapability (BIT12)\r
+#define TPM_DELEGATE_MakeIdentity (BIT11)\r
+#define TPM_DELEGATE_ActivateIdentity (BIT10)\r
+#define TPM_DELEGATE_OwnerReadPubek (BIT9)\r
+#define TPM_DELEGATE_DisablePubekRead (BIT8)\r
+#define TPM_DELEGATE_SetRedirection (BIT7)\r
+#define TPM_DELEGATE_FieldUpgrade (BIT6)\r
+#define TPM_DELEGATE_Delegate_UpdateVerification (BIT5)\r
+#define TPM_DELEGATE_CreateCounter (BIT4)\r
+#define TPM_DELEGATE_ReleaseCounterOwner (BIT3)\r
+#define TPM_DELEGATE_DelegateManage (BIT2)\r
+#define TPM_DELEGATE_Delegate_CreateOwnerDelegation (BIT1)\r
+#define TPM_DELEGATE_DAA_Sign (BIT0)\r
\r
//\r
// Part 2, section 20.2.3: Key Permission settings\r
//\r
-#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28)\r
-#define TPM_KEY_DELEGATE_TickStampBlob (BIT27)\r
-#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26)\r
-#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25)\r
-#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24)\r
-#define TPM_KEY_DELEGATE_MigrateKey (BIT23)\r
-#define TPM_KEY_DELEGATE_LoadKey2 (BIT22)\r
-#define TPM_KEY_DELEGATE_EstablishTransport (BIT21)\r
-#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20)\r
-#define TPM_KEY_DELEGATE_Quote2 (BIT19)\r
-#define TPM_KEY_DELEGATE_Sealx (BIT18)\r
-#define TPM_KEY_DELEGATE_MakeIdentity (BIT17)\r
-#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16)\r
-#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15)\r
-#define TPM_KEY_DELEGATE_Sign (BIT14)\r
-#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13)\r
-#define TPM_KEY_DELEGATE_CertifyKey (BIT12)\r
-#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11)\r
-#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10)\r
-#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9)\r
-#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8)\r
-#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7)\r
-#define TPM_KEY_DELEGATE_ChangeAuth (BIT6)\r
-#define TPM_KEY_DELEGATE_GetPubKey (BIT5)\r
-#define TPM_KEY_DELEGATE_UnBind (BIT4)\r
-#define TPM_KEY_DELEGATE_Quote (BIT3)\r
-#define TPM_KEY_DELEGATE_Unseal (BIT2)\r
-#define TPM_KEY_DELEGATE_Seal (BIT1)\r
-#define TPM_KEY_DELEGATE_LoadKey (BIT0)\r
+#define TPM_KEY_DELEGATE_CMK_ConvertMigration (BIT28)\r
+#define TPM_KEY_DELEGATE_TickStampBlob (BIT27)\r
+#define TPM_KEY_DELEGATE_ChangeAuthAsymStart (BIT26)\r
+#define TPM_KEY_DELEGATE_ChangeAuthAsymFinish (BIT25)\r
+#define TPM_KEY_DELEGATE_CMK_CreateKey (BIT24)\r
+#define TPM_KEY_DELEGATE_MigrateKey (BIT23)\r
+#define TPM_KEY_DELEGATE_LoadKey2 (BIT22)\r
+#define TPM_KEY_DELEGATE_EstablishTransport (BIT21)\r
+#define TPM_KEY_DELEGATE_ReleaseTransportSigned (BIT20)\r
+#define TPM_KEY_DELEGATE_Quote2 (BIT19)\r
+#define TPM_KEY_DELEGATE_Sealx (BIT18)\r
+#define TPM_KEY_DELEGATE_MakeIdentity (BIT17)\r
+#define TPM_KEY_DELEGATE_ActivateIdentity (BIT16)\r
+#define TPM_KEY_DELEGATE_GetAuditDigestSigned (BIT15)\r
+#define TPM_KEY_DELEGATE_Sign (BIT14)\r
+#define TPM_KEY_DELEGATE_CertifyKey2 (BIT13)\r
+#define TPM_KEY_DELEGATE_CertifyKey (BIT12)\r
+#define TPM_KEY_DELEGATE_CreateWrapKey (BIT11)\r
+#define TPM_KEY_DELEGATE_CMK_CreateBlob (BIT10)\r
+#define TPM_KEY_DELEGATE_CreateMigrationBlob (BIT9)\r
+#define TPM_KEY_DELEGATE_ConvertMigrationBlob (BIT8)\r
+#define TPM_KEY_DELEGATE_CreateKeyDelegation (BIT7)\r
+#define TPM_KEY_DELEGATE_ChangeAuth (BIT6)\r
+#define TPM_KEY_DELEGATE_GetPubKey (BIT5)\r
+#define TPM_KEY_DELEGATE_UnBind (BIT4)\r
+#define TPM_KEY_DELEGATE_Quote (BIT3)\r
+#define TPM_KEY_DELEGATE_Unseal (BIT2)\r
+#define TPM_KEY_DELEGATE_Seal (BIT1)\r
+#define TPM_KEY_DELEGATE_LoadKey (BIT0)\r
\r
//\r
// Part 2, section 20.3: TPM_FAMILY_FLAGS\r
//\r
-#define TPM_DELEGATE_ADMIN_LOCK (BIT1)\r
-#define TPM_FAMFLAG_ENABLE (BIT0)\r
+#define TPM_DELEGATE_ADMIN_LOCK (BIT1)\r
+#define TPM_FAMFLAG_ENABLE (BIT0)\r
\r
///\r
/// Part 2, section 20.4: TPM_FAMILY_LABEL\r
///\r
typedef struct tdTPM_FAMILY_LABEL {\r
- UINT8 label;\r
+ UINT8 label;\r
} TPM_FAMILY_LABEL;\r
\r
///\r
/// Part 2, section 20.5: TPM_FAMILY_TABLE_ENTRY\r
///\r
typedef struct tdTPM_FAMILY_TABLE_ENTRY {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_FAMILY_LABEL label;\r
- TPM_FAMILY_ID familyID;\r
- TPM_FAMILY_VERIFICATION verificationCount;\r
- TPM_FAMILY_FLAGS flags;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_FAMILY_LABEL label;\r
+ TPM_FAMILY_ID familyID;\r
+ TPM_FAMILY_VERIFICATION verificationCount;\r
+ TPM_FAMILY_FLAGS flags;\r
} TPM_FAMILY_TABLE_ENTRY;\r
\r
//\r
// Part 2, section 20.6: TPM_FAMILY_TABLE\r
//\r
-#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8\r
+#define TPM_NUM_FAMILY_TABLE_ENTRY_MIN 8\r
\r
-typedef struct tdTPM_FAMILY_TABLE{\r
- TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];\r
+typedef struct tdTPM_FAMILY_TABLE {\r
+ TPM_FAMILY_TABLE_ENTRY famTableRow[TPM_NUM_FAMILY_TABLE_ENTRY_MIN];\r
} TPM_FAMILY_TABLE;\r
\r
///\r
/// Part 2, section 20.7: TPM_DELEGATE_LABEL\r
///\r
typedef struct tdTPM_DELEGATE_LABEL {\r
- UINT8 label;\r
+ UINT8 label;\r
} TPM_DELEGATE_LABEL;\r
\r
///\r
/// Part 2, section 20.8: TPM_DELEGATE_PUBLIC\r
///\r
typedef struct tdTPM_DELEGATE_PUBLIC {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DELEGATE_LABEL label;\r
- TPM_PCR_INFO_SHORT pcrInfo;\r
- TPM_DELEGATIONS permissions;\r
- TPM_FAMILY_ID familyID;\r
- TPM_FAMILY_VERIFICATION verificationCount;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DELEGATE_LABEL label;\r
+ TPM_PCR_INFO_SHORT pcrInfo;\r
+ TPM_DELEGATIONS permissions;\r
+ TPM_FAMILY_ID familyID;\r
+ TPM_FAMILY_VERIFICATION verificationCount;\r
} TPM_DELEGATE_PUBLIC;\r
\r
///\r
/// Part 2, section 20.9: TPM_DELEGATE_TABLE_ROW\r
///\r
typedef struct tdTPM_DELEGATE_TABLE_ROW {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DELEGATE_PUBLIC pub;\r
- TPM_SECRET authValue;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DELEGATE_PUBLIC pub;\r
+ TPM_SECRET authValue;\r
} TPM_DELEGATE_TABLE_ROW;\r
\r
//\r
// Part 2, section 20.10: TPM_DELEGATE_TABLE\r
//\r
-#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2\r
+#define TPM_NUM_DELEGATE_TABLE_ENTRY_MIN 2\r
\r
-typedef struct tdTPM_DELEGATE_TABLE{\r
- TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];\r
+typedef struct tdTPM_DELEGATE_TABLE {\r
+ TPM_DELEGATE_TABLE_ROW delRow[TPM_NUM_DELEGATE_TABLE_ENTRY_MIN];\r
} TPM_DELEGATE_TABLE;\r
\r
///\r
/// Part 2, section 20.11: TPM_DELEGATE_SENSITIVE\r
///\r
typedef struct tdTPM_DELEGATE_SENSITIVE {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_SECRET authValue;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_SECRET authValue;\r
} TPM_DELEGATE_SENSITIVE;\r
\r
///\r
/// Part 2, section 20.12: TPM_DELEGATE_OWNER_BLOB\r
///\r
typedef struct tdTPM_DELEGATE_OWNER_BLOB {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DELEGATE_PUBLIC pub;\r
- TPM_DIGEST integrityDigest;\r
- UINT32 additionalSize;\r
- UINT8 *additionalArea;\r
- UINT32 sensitiveSize;\r
- UINT8 *sensitiveArea;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DELEGATE_PUBLIC pub;\r
+ TPM_DIGEST integrityDigest;\r
+ UINT32 additionalSize;\r
+ UINT8 *additionalArea;\r
+ UINT32 sensitiveSize;\r
+ UINT8 *sensitiveArea;\r
} TPM_DELEGATE_OWNER_BLOB;\r
\r
///\r
/// Part 2, section 20.13: TTPM_DELEGATE_KEY_BLOB\r
///\r
typedef struct tdTPM_DELEGATE_KEY_BLOB {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DELEGATE_PUBLIC pub;\r
- TPM_DIGEST integrityDigest;\r
- TPM_DIGEST pubKeyDigest;\r
- UINT32 additionalSize;\r
- UINT8 *additionalArea;\r
- UINT32 sensitiveSize;\r
- UINT8 *sensitiveArea;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DELEGATE_PUBLIC pub;\r
+ TPM_DIGEST integrityDigest;\r
+ TPM_DIGEST pubKeyDigest;\r
+ UINT32 additionalSize;\r
+ UINT8 *additionalArea;\r
+ UINT32 sensitiveSize;\r
+ UINT8 *sensitiveArea;\r
} TPM_DELEGATE_KEY_BLOB;\r
\r
//\r
// Part 2, section 20.14: TPM_FAMILY_OPERATION Values\r
//\r
-#define TPM_FAMILY_CREATE ((UINT32)0x00000001)\r
-#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)\r
-#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)\r
-#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)\r
+#define TPM_FAMILY_CREATE ((UINT32)0x00000001)\r
+#define TPM_FAMILY_ENABLE ((UINT32)0x00000002)\r
+#define TPM_FAMILY_ADMIN ((UINT32)0x00000003)\r
+#define TPM_FAMILY_INVALIDATE ((UINT32)0x00000004)\r
\r
//\r
// Part 2, section 21.1: TPM_CAPABILITY_AREA for GetCapability\r
//\r
-#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)\r
-#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)\r
-#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)\r
-#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)\r
-#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)\r
-#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)\r
-#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)\r
-#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)\r
-#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)\r
-#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)\r
-#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)\r
-#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)\r
-#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)\r
-#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)\r
-#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)\r
-#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)\r
-#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)\r
-#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)\r
-#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)\r
-\r
-#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)\r
-#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)\r
+#define TPM_CAP_ORD ((TPM_CAPABILITY_AREA) 0x00000001)\r
+#define TPM_CAP_ALG ((TPM_CAPABILITY_AREA) 0x00000002)\r
+#define TPM_CAP_PID ((TPM_CAPABILITY_AREA) 0x00000003)\r
+#define TPM_CAP_FLAG ((TPM_CAPABILITY_AREA) 0x00000004)\r
+#define TPM_CAP_PROPERTY ((TPM_CAPABILITY_AREA) 0x00000005)\r
+#define TPM_CAP_VERSION ((TPM_CAPABILITY_AREA) 0x00000006)\r
+#define TPM_CAP_KEY_HANDLE ((TPM_CAPABILITY_AREA) 0x00000007)\r
+#define TPM_CAP_CHECK_LOADED ((TPM_CAPABILITY_AREA) 0x00000008)\r
+#define TPM_CAP_SYM_MODE ((TPM_CAPABILITY_AREA) 0x00000009)\r
+#define TPM_CAP_KEY_STATUS ((TPM_CAPABILITY_AREA) 0x0000000C)\r
+#define TPM_CAP_NV_LIST ((TPM_CAPABILITY_AREA) 0x0000000D)\r
+#define TPM_CAP_MFR ((TPM_CAPABILITY_AREA) 0x00000010)\r
+#define TPM_CAP_NV_INDEX ((TPM_CAPABILITY_AREA) 0x00000011)\r
+#define TPM_CAP_TRANS_ALG ((TPM_CAPABILITY_AREA) 0x00000012)\r
+#define TPM_CAP_HANDLE ((TPM_CAPABILITY_AREA) 0x00000014)\r
+#define TPM_CAP_TRANS_ES ((TPM_CAPABILITY_AREA) 0x00000015)\r
+#define TPM_CAP_AUTH_ENCRYPT ((TPM_CAPABILITY_AREA) 0x00000017)\r
+#define TPM_CAP_SELECT_SIZE ((TPM_CAPABILITY_AREA) 0x00000018)\r
+#define TPM_CAP_VERSION_VAL ((TPM_CAPABILITY_AREA) 0x0000001A)\r
+\r
+#define TPM_CAP_FLAG_PERMANENT ((TPM_CAPABILITY_AREA) 0x00000108)\r
+#define TPM_CAP_FLAG_VOLATILE ((TPM_CAPABILITY_AREA) 0x00000109)\r
\r
//\r
// Part 2, section 21.2: CAP_PROPERTY Subcap values for GetCapability\r
//\r
-#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)\r
-#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)\r
-#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)\r
-#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)\r
-#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)\r
-#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)\r
-#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)\r
-#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)\r
-#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)\r
-#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)\r
-#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)\r
-#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)\r
-#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)\r
-#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)\r
-#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)\r
-#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)\r
-#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)\r
-#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)\r
-#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)\r
-#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)\r
-#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)\r
-#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)\r
-#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)\r
-#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)\r
-#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)\r
-#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)\r
-#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)\r
-#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)\r
-#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)\r
-#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)\r
+#define TPM_CAP_PROP_PCR ((TPM_CAPABILITY_AREA) 0x00000101)\r
+#define TPM_CAP_PROP_DIR ((TPM_CAPABILITY_AREA) 0x00000102)\r
+#define TPM_CAP_PROP_MANUFACTURER ((TPM_CAPABILITY_AREA) 0x00000103)\r
+#define TPM_CAP_PROP_KEYS ((TPM_CAPABILITY_AREA) 0x00000104)\r
+#define TPM_CAP_PROP_MIN_COUNTER ((TPM_CAPABILITY_AREA) 0x00000107)\r
+#define TPM_CAP_PROP_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010A)\r
+#define TPM_CAP_PROP_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010B)\r
+#define TPM_CAP_PROP_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010C)\r
+#define TPM_CAP_PROP_MAX_AUTHSESS ((TPM_CAPABILITY_AREA) 0x0000010D)\r
+#define TPM_CAP_PROP_MAX_TRANSESS ((TPM_CAPABILITY_AREA) 0x0000010E)\r
+#define TPM_CAP_PROP_MAX_COUNTERS ((TPM_CAPABILITY_AREA) 0x0000010F)\r
+#define TPM_CAP_PROP_MAX_KEYS ((TPM_CAPABILITY_AREA) 0x00000110)\r
+#define TPM_CAP_PROP_OWNER ((TPM_CAPABILITY_AREA) 0x00000111)\r
+#define TPM_CAP_PROP_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000112)\r
+#define TPM_CAP_PROP_MAX_CONTEXT ((TPM_CAPABILITY_AREA) 0x00000113)\r
+#define TPM_CAP_PROP_FAMILYROWS ((TPM_CAPABILITY_AREA) 0x00000114)\r
+#define TPM_CAP_PROP_TIS_TIMEOUT ((TPM_CAPABILITY_AREA) 0x00000115)\r
+#define TPM_CAP_PROP_STARTUP_EFFECT ((TPM_CAPABILITY_AREA) 0x00000116)\r
+#define TPM_CAP_PROP_DELEGATE_ROW ((TPM_CAPABILITY_AREA) 0x00000117)\r
+#define TPM_CAP_PROP_DAA_MAX ((TPM_CAPABILITY_AREA) 0x00000119)\r
+#define CAP_PROP_SESSION_DAA ((TPM_CAPABILITY_AREA) 0x0000011A)\r
+#define TPM_CAP_PROP_CONTEXT_DIST ((TPM_CAPABILITY_AREA) 0x0000011B)\r
+#define TPM_CAP_PROP_DAA_INTERRUPT ((TPM_CAPABILITY_AREA) 0x0000011C)\r
+#define TPM_CAP_PROP_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011D)\r
+#define TPM_CAP_PROP_MAX_SESSIONS ((TPM_CAPABILITY_AREA) 0x0000011E)\r
+#define TPM_CAP_PROP_CMK_RESTRICTION ((TPM_CAPABILITY_AREA) 0x0000011F)\r
+#define TPM_CAP_PROP_DURATION ((TPM_CAPABILITY_AREA) 0x00000120)\r
+#define TPM_CAP_PROP_ACTIVE_COUNTER ((TPM_CAPABILITY_AREA) 0x00000122)\r
+#define TPM_CAP_PROP_MAX_NV_AVAILABLE ((TPM_CAPABILITY_AREA) 0x00000123)\r
+#define TPM_CAP_PROP_INPUT_BUFFER ((TPM_CAPABILITY_AREA) 0x00000124)\r
\r
//\r
// Part 2, section 21.4: TPM_CAPABILITY_AREA for SetCapability\r
//\r
-#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001)\r
-#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002)\r
-#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003)\r
-#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004)\r
-#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005)\r
-#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006)\r
+#define TPM_SET_PERM_FLAGS ((TPM_CAPABILITY_AREA) 0x00000001)\r
+#define TPM_SET_PERM_DATA ((TPM_CAPABILITY_AREA) 0x00000002)\r
+#define TPM_SET_STCLEAR_FLAGS ((TPM_CAPABILITY_AREA) 0x00000003)\r
+#define TPM_SET_STCLEAR_DATA ((TPM_CAPABILITY_AREA) 0x00000004)\r
+#define TPM_SET_STANY_FLAGS ((TPM_CAPABILITY_AREA) 0x00000005)\r
+#define TPM_SET_STANY_DATA ((TPM_CAPABILITY_AREA) 0x00000006)\r
\r
///\r
/// Part 2, section 21.6: TPM_CAP_VERSION_INFO\r
/// [size_is(vendorSpecificSize)] BYTE* vendorSpecific;\r
///\r
typedef struct tdTPM_CAP_VERSION_INFO {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_VERSION version;\r
- UINT16 specLevel;\r
- UINT8 errataRev;\r
- UINT8 tpmVendorID[4];\r
- UINT16 vendorSpecificSize;\r
- UINT8 *vendorSpecific;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_VERSION version;\r
+ UINT16 specLevel;\r
+ UINT8 errataRev;\r
+ UINT8 tpmVendorID[4];\r
+ UINT16 vendorSpecificSize;\r
+ UINT8 *vendorSpecific;\r
} TPM_CAP_VERSION_INFO;\r
\r
///\r
/// Part 2, section 21.10: TPM_DA_ACTION_TYPE\r
///\r
typedef struct tdTPM_DA_ACTION_TYPE {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 actions;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 actions;\r
} TPM_DA_ACTION_TYPE;\r
\r
-#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3)\r
-#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2)\r
-#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1)\r
-#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0)\r
+#define TPM_DA_ACTION_FAILURE_MODE (((UINT32)1)<<3)\r
+#define TPM_DA_ACTION_DEACTIVATE (((UINT32)1)<<2)\r
+#define TPM_DA_ACTION_DISABLE (((UINT32)1)<<1)\r
+#define TPM_DA_ACTION_TIMEOUT (((UINT32)1)<<0)\r
\r
///\r
/// Part 2, section 21.7: TPM_DA_INFO\r
///\r
typedef struct tdTPM_DA_INFO {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DA_STATE state;\r
- UINT16 currentCount;\r
- UINT16 thresholdCount;\r
- TPM_DA_ACTION_TYPE actionAtThreshold;\r
- UINT32 actionDependValue;\r
- UINT32 vendorDataSize;\r
- UINT8 *vendorData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DA_STATE state;\r
+ UINT16 currentCount;\r
+ UINT16 thresholdCount;\r
+ TPM_DA_ACTION_TYPE actionAtThreshold;\r
+ UINT32 actionDependValue;\r
+ UINT32 vendorDataSize;\r
+ UINT8 *vendorData;\r
} TPM_DA_INFO;\r
\r
///\r
/// Part 2, section 21.8: TPM_DA_INFO_LIMITED\r
///\r
typedef struct tdTPM_DA_INFO_LIMITED {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DA_STATE state;\r
- TPM_DA_ACTION_TYPE actionAtThreshold;\r
- UINT32 vendorDataSize;\r
- UINT8 *vendorData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DA_STATE state;\r
+ TPM_DA_ACTION_TYPE actionAtThreshold;\r
+ UINT32 vendorDataSize;\r
+ UINT8 *vendorData;\r
} TPM_DA_INFO_LIMITED;\r
\r
//\r
// Part 2, section 21.9: CAP_PROPERTY Subcap values for GetCapability\r
//\r
-#define TPM_DA_STATE_INACTIVE ((UINT8)0x00)\r
-#define TPM_DA_STATE_ACTIVE ((UINT8)0x01)\r
+#define TPM_DA_STATE_INACTIVE ((UINT8)0x00)\r
+#define TPM_DA_STATE_ACTIVE ((UINT8)0x01)\r
\r
//\r
// Part 2, section 22: DAA Structures\r
//\r
// Part 2, section 22.1: Size definitions\r
//\r
-#define TPM_DAA_SIZE_r0 (43)\r
-#define TPM_DAA_SIZE_r1 (43)\r
-#define TPM_DAA_SIZE_r2 (128)\r
-#define TPM_DAA_SIZE_r3 (168)\r
-#define TPM_DAA_SIZE_r4 (219)\r
-#define TPM_DAA_SIZE_NT (20)\r
-#define TPM_DAA_SIZE_v0 (128)\r
-#define TPM_DAA_SIZE_v1 (192)\r
-#define TPM_DAA_SIZE_NE (256)\r
-#define TPM_DAA_SIZE_w (256)\r
-#define TPM_DAA_SIZE_issuerModulus (256)\r
+#define TPM_DAA_SIZE_r0 (43)\r
+#define TPM_DAA_SIZE_r1 (43)\r
+#define TPM_DAA_SIZE_r2 (128)\r
+#define TPM_DAA_SIZE_r3 (168)\r
+#define TPM_DAA_SIZE_r4 (219)\r
+#define TPM_DAA_SIZE_NT (20)\r
+#define TPM_DAA_SIZE_v0 (128)\r
+#define TPM_DAA_SIZE_v1 (192)\r
+#define TPM_DAA_SIZE_NE (256)\r
+#define TPM_DAA_SIZE_w (256)\r
+#define TPM_DAA_SIZE_issuerModulus (256)\r
//\r
// Part 2, section 22.2: Constant definitions\r
//\r
-#define TPM_DAA_power0 (104)\r
-#define TPM_DAA_power1 (1024)\r
+#define TPM_DAA_power0 (104)\r
+#define TPM_DAA_power1 (1024)\r
\r
///\r
/// Part 2, section 22.3: TPM_DAA_ISSUER\r
///\r
typedef struct tdTPM_DAA_ISSUER {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST DAA_digest_R0;\r
- TPM_DIGEST DAA_digest_R1;\r
- TPM_DIGEST DAA_digest_S0;\r
- TPM_DIGEST DAA_digest_S1;\r
- TPM_DIGEST DAA_digest_n;\r
- TPM_DIGEST DAA_digest_gamma;\r
- UINT8 DAA_generic_q[26];\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST DAA_digest_R0;\r
+ TPM_DIGEST DAA_digest_R1;\r
+ TPM_DIGEST DAA_digest_S0;\r
+ TPM_DIGEST DAA_digest_S1;\r
+ TPM_DIGEST DAA_digest_n;\r
+ TPM_DIGEST DAA_digest_gamma;\r
+ UINT8 DAA_generic_q[26];\r
} TPM_DAA_ISSUER;\r
\r
///\r
/// Part 2, section 22.4: TPM_DAA_TPM\r
///\r
typedef struct tdTPM_DAA_TPM {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST DAA_digestIssuer;\r
- TPM_DIGEST DAA_digest_v0;\r
- TPM_DIGEST DAA_digest_v1;\r
- TPM_DIGEST DAA_rekey;\r
- UINT32 DAA_count;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST DAA_digestIssuer;\r
+ TPM_DIGEST DAA_digest_v0;\r
+ TPM_DIGEST DAA_digest_v1;\r
+ TPM_DIGEST DAA_rekey;\r
+ UINT32 DAA_count;\r
} TPM_DAA_TPM;\r
\r
///\r
/// Part 2, section 22.5: TPM_DAA_CONTEXT\r
///\r
typedef struct tdTPM_DAA_CONTEXT {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_DIGEST DAA_digestContext;\r
- TPM_DIGEST DAA_digest;\r
- TPM_DAA_CONTEXT_SEED DAA_contextSeed;\r
- UINT8 DAA_scratch[256];\r
- UINT8 DAA_stage;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_DIGEST DAA_digestContext;\r
+ TPM_DIGEST DAA_digest;\r
+ TPM_DAA_CONTEXT_SEED DAA_contextSeed;\r
+ UINT8 DAA_scratch[256];\r
+ UINT8 DAA_stage;\r
} TPM_DAA_CONTEXT;\r
\r
///\r
/// Part 2, section 22.6: TPM_DAA_JOINDATA\r
///\r
typedef struct tdTPM_DAA_JOINDATA {\r
- UINT8 DAA_join_u0[128];\r
- UINT8 DAA_join_u1[138];\r
- TPM_DIGEST DAA_digest_n0;\r
+ UINT8 DAA_join_u0[128];\r
+ UINT8 DAA_join_u1[138];\r
+ TPM_DIGEST DAA_digest_n0;\r
} TPM_DAA_JOINDATA;\r
\r
///\r
/// Part 2, section 22.8: TPM_DAA_BLOB\r
///\r
typedef struct tdTPM_DAA_BLOB {\r
- TPM_STRUCTURE_TAG tag;\r
- TPM_RESOURCE_TYPE resourceType;\r
- UINT8 label[16];\r
- TPM_DIGEST blobIntegrity;\r
- UINT32 additionalSize;\r
- UINT8 *additionalData;\r
- UINT32 sensitiveSize;\r
- UINT8 *sensitiveData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ TPM_RESOURCE_TYPE resourceType;\r
+ UINT8 label[16];\r
+ TPM_DIGEST blobIntegrity;\r
+ UINT32 additionalSize;\r
+ UINT8 *additionalData;\r
+ UINT32 sensitiveSize;\r
+ UINT8 *sensitiveData;\r
} TPM_DAA_BLOB;\r
\r
///\r
/// Part 2, section 22.9: TPM_DAA_SENSITIVE\r
///\r
typedef struct tdTPM_DAA_SENSITIVE {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 internalSize;\r
- UINT8 *internalData;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 internalSize;\r
+ UINT8 *internalData;\r
} TPM_DAA_SENSITIVE;\r
\r
-\r
//\r
// Part 2, section 23: Redirection\r
//\r
/// refers to exactly one name but does not give its value. We join\r
/// them here.\r
///\r
-#define TPM_REDIR_GPIO (0x00000001)\r
+#define TPM_REDIR_GPIO (0x00000001)\r
\r
///\r
/// TPM Command Headers defined in Part 3\r
///\r
typedef struct tdTPM_RQU_COMMAND_HDR {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 paramSize;\r
- TPM_COMMAND_CODE ordinal;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 paramSize;\r
+ TPM_COMMAND_CODE ordinal;\r
} TPM_RQU_COMMAND_HDR;\r
\r
///\r
/// TPM Response Headers defined in Part 3\r
///\r
typedef struct tdTPM_RSP_COMMAND_HDR {\r
- TPM_STRUCTURE_TAG tag;\r
- UINT32 paramSize;\r
- TPM_RESULT returnCode;\r
+ TPM_STRUCTURE_TAG tag;\r
+ UINT32 paramSize;\r
+ TPM_RESULT returnCode;\r
} TPM_RSP_COMMAND_HDR;\r
\r
#pragma pack ()\r
\r
**/\r
\r
-\r
#ifndef _TPM20_H_\r
#define _TPM20_H_\r
\r
// Annex A Algorithm Constants\r
\r
// Table 205 - Defines for SHA1 Hash Values\r
-#define SHA1_DIGEST_SIZE 20\r
-#define SHA1_BLOCK_SIZE 64\r
+#define SHA1_DIGEST_SIZE 20\r
+#define SHA1_BLOCK_SIZE 64\r
\r
// Table 206 - Defines for SHA256 Hash Values\r
-#define SHA256_DIGEST_SIZE 32\r
-#define SHA256_BLOCK_SIZE 64\r
+#define SHA256_DIGEST_SIZE 32\r
+#define SHA256_BLOCK_SIZE 64\r
\r
// Table 207 - Defines for SHA384 Hash Values\r
-#define SHA384_DIGEST_SIZE 48\r
-#define SHA384_BLOCK_SIZE 128\r
+#define SHA384_DIGEST_SIZE 48\r
+#define SHA384_BLOCK_SIZE 128\r
\r
// Table 208 - Defines for SHA512 Hash Values\r
-#define SHA512_DIGEST_SIZE 64\r
-#define SHA512_BLOCK_SIZE 128\r
+#define SHA512_DIGEST_SIZE 64\r
+#define SHA512_BLOCK_SIZE 128\r
\r
// Table 209 - Defines for SM3_256 Hash Values\r
-#define SM3_256_DIGEST_SIZE 32\r
-#define SM3_256_BLOCK_SIZE 64\r
+#define SM3_256_DIGEST_SIZE 32\r
+#define SM3_256_BLOCK_SIZE 64\r
\r
// Table 210 - Defines for Architectural Limits Values\r
-#define MAX_SESSION_NUMBER 3\r
+#define MAX_SESSION_NUMBER 3\r
\r
// Annex B Implementation Definitions\r
\r
// Table 211 - Defines for Logic Values\r
-#define YES 1\r
-#define NO 0\r
-#define SET 1\r
-#define CLEAR 0\r
+#define YES 1\r
+#define NO 0\r
+#define SET 1\r
+#define CLEAR 0\r
\r
// Table 215 - Defines for RSA Algorithm Constants\r
-#define MAX_RSA_KEY_BITS 2048\r
-#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)\r
+#define MAX_RSA_KEY_BITS 2048\r
+#define MAX_RSA_KEY_BYTES ((MAX_RSA_KEY_BITS + 7) / 8)\r
\r
// Table 216 - Defines for ECC Algorithm Constants\r
-#define MAX_ECC_KEY_BITS 256\r
-#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)\r
+#define MAX_ECC_KEY_BITS 256\r
+#define MAX_ECC_KEY_BYTES ((MAX_ECC_KEY_BITS + 7) / 8)\r
\r
// Table 217 - Defines for AES Algorithm Constants\r
-#define MAX_AES_KEY_BITS 128\r
-#define MAX_AES_BLOCK_SIZE_BYTES 16\r
-#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8)\r
+#define MAX_AES_KEY_BITS 128\r
+#define MAX_AES_BLOCK_SIZE_BYTES 16\r
+#define MAX_AES_KEY_BYTES ((MAX_AES_KEY_BITS + 7) / 8)\r
\r
// Table 218 - Defines for SM4 Algorithm Constants\r
-#define MAX_SM4_KEY_BITS 128\r
-#define MAX_SM4_BLOCK_SIZE_BYTES 16\r
-#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8)\r
+#define MAX_SM4_KEY_BITS 128\r
+#define MAX_SM4_BLOCK_SIZE_BYTES 16\r
+#define MAX_SM4_KEY_BYTES ((MAX_SM4_KEY_BITS + 7) / 8)\r
\r
// Table 219 - Defines for Symmetric Algorithm Constants\r
-#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS\r
-#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES\r
-#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES\r
+#define MAX_SYM_KEY_BITS MAX_AES_KEY_BITS\r
+#define MAX_SYM_KEY_BYTES MAX_AES_KEY_BYTES\r
+#define MAX_SYM_BLOCK_SIZE MAX_AES_BLOCK_SIZE_BYTES\r
\r
// Table 220 - Defines for Implementation Values\r
-typedef UINT16 BSIZE;\r
-#define BUFFER_ALIGNMENT 4\r
-#define IMPLEMENTATION_PCR 24\r
-#define PLATFORM_PCR 24\r
-#define DRTM_PCR 17\r
-#define NUM_LOCALITIES 5\r
-#define MAX_HANDLE_NUM 3\r
-#define MAX_ACTIVE_SESSIONS 64\r
-typedef UINT16 CONTEXT_SLOT;\r
-typedef UINT64 CONTEXT_COUNTER;\r
-#define MAX_LOADED_SESSIONS 3\r
-#define MAX_SESSION_NUM 3\r
-#define MAX_LOADED_OBJECTS 3\r
-#define MIN_EVICT_OBJECTS 2\r
-#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8)\r
-#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8)\r
-#define NUM_POLICY_PCR_GROUP 1\r
-#define NUM_AUTHVALUE_PCR_GROUP 1\r
-#define MAX_CONTEXT_SIZE 4000\r
-#define MAX_DIGEST_BUFFER 1024\r
-#define MAX_NV_INDEX_SIZE 1024\r
-#define MAX_CAP_BUFFER 1024\r
-#define NV_MEMORY_SIZE 16384\r
-#define NUM_STATIC_PCR 16\r
-#define MAX_ALG_LIST_SIZE 64\r
-#define TIMER_PRESCALE 100000\r
-#define PRIMARY_SEED_SIZE 32\r
-#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES\r
-#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS\r
-#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)\r
-#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256\r
-#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE\r
-#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE\r
-#define NV_CLOCK_UPDATE_INTERVAL 12\r
-#define NUM_POLICY_PCR 1\r
-#define MAX_COMMAND_SIZE 4096\r
-#define MAX_RESPONSE_SIZE 4096\r
-#define ORDERLY_BITS 8\r
-#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1)\r
-#define ALG_ID_FIRST TPM_ALG_FIRST\r
-#define ALG_ID_LAST TPM_ALG_LAST\r
-#define MAX_SYM_DATA 128\r
-#define MAX_RNG_ENTROPY_SIZE 64\r
-#define RAM_INDEX_SPACE 512\r
-#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001\r
-#define CRT_FORMAT_RSA YES\r
-#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))\r
+typedef UINT16 BSIZE;\r
+#define BUFFER_ALIGNMENT 4\r
+#define IMPLEMENTATION_PCR 24\r
+#define PLATFORM_PCR 24\r
+#define DRTM_PCR 17\r
+#define NUM_LOCALITIES 5\r
+#define MAX_HANDLE_NUM 3\r
+#define MAX_ACTIVE_SESSIONS 64\r
+typedef UINT16 CONTEXT_SLOT;\r
+typedef UINT64 CONTEXT_COUNTER;\r
+#define MAX_LOADED_SESSIONS 3\r
+#define MAX_SESSION_NUM 3\r
+#define MAX_LOADED_OBJECTS 3\r
+#define MIN_EVICT_OBJECTS 2\r
+#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8)\r
+#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8)\r
+#define NUM_POLICY_PCR_GROUP 1\r
+#define NUM_AUTHVALUE_PCR_GROUP 1\r
+#define MAX_CONTEXT_SIZE 4000\r
+#define MAX_DIGEST_BUFFER 1024\r
+#define MAX_NV_INDEX_SIZE 1024\r
+#define MAX_CAP_BUFFER 1024\r
+#define NV_MEMORY_SIZE 16384\r
+#define NUM_STATIC_PCR 16\r
+#define MAX_ALG_LIST_SIZE 64\r
+#define TIMER_PRESCALE 100000\r
+#define PRIMARY_SEED_SIZE 32\r
+#define CONTEXT_ENCRYPT_ALG TPM_ALG_AES\r
+#define CONTEXT_ENCRYPT_KEY_BITS MAX_SYM_KEY_BITS\r
+#define CONTEXT_ENCRYPT_KEY_BYTES ((CONTEXT_ENCRYPT_KEY_BITS + 7) / 8)\r
+#define CONTEXT_INTEGRITY_HASH_ALG TPM_ALG_SHA256\r
+#define CONTEXT_INTEGRITY_HASH_SIZE SHA256_DIGEST_SIZE\r
+#define PROOF_SIZE CONTEXT_INTEGRITY_HASH_SIZE\r
+#define NV_CLOCK_UPDATE_INTERVAL 12\r
+#define NUM_POLICY_PCR 1\r
+#define MAX_COMMAND_SIZE 4096\r
+#define MAX_RESPONSE_SIZE 4096\r
+#define ORDERLY_BITS 8\r
+#define MAX_ORDERLY_COUNT ((1 << ORDERLY_BITS) - 1)\r
+#define ALG_ID_FIRST TPM_ALG_FIRST\r
+#define ALG_ID_LAST TPM_ALG_LAST\r
+#define MAX_SYM_DATA 128\r
+#define MAX_RNG_ENTROPY_SIZE 64\r
+#define RAM_INDEX_SPACE 512\r
+#define RSA_DEFAULT_PUBLIC_EXPONENT 0x00010001\r
+#define CRT_FORMAT_RSA YES\r
+#define PRIVATE_VENDOR_SPECIFIC_BYTES ((MAX_RSA_KEY_BYTES / 2) * ( 3 + CRT_FORMAT_RSA * 2))\r
\r
// Capability related MAX_ value\r
-#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))\r
-#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))\r
-#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE))\r
-#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC))\r
-#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))\r
-#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))\r
-#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))\r
+#define MAX_CAP_DATA (MAX_CAP_BUFFER - sizeof(TPM_CAP) - sizeof(UINT32))\r
+#define MAX_CAP_ALGS (MAX_CAP_DATA / sizeof(TPMS_ALG_PROPERTY))\r
+#define MAX_CAP_HANDLES (MAX_CAP_DATA / sizeof(TPM_HANDLE))\r
+#define MAX_CAP_CC (MAX_CAP_DATA / sizeof(TPM_CC))\r
+#define MAX_TPM_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PROPERTY))\r
+#define MAX_PCR_PROPERTIES (MAX_CAP_DATA / sizeof(TPMS_TAGGED_PCR_SELECT))\r
+#define MAX_ECC_CURVES (MAX_CAP_DATA / sizeof(TPM_ECC_CURVE))\r
\r
//\r
// Always set 5 here, because we want to support all hash algo in BIOS.\r
//\r
-#define HASH_COUNT 5\r
+#define HASH_COUNT 5\r
\r
// 5 Base Types\r
\r
//\r
// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)\r
//\r
-//typedef UINT32 TPM_ALGORITHM_ID;\r
-//typedef UINT32 TPM_MODIFIER_INDICATOR;\r
+// typedef UINT32 TPM_ALGORITHM_ID;\r
+// typedef UINT32 TPM_MODIFIER_INDICATOR;\r
typedef UINT32 TPM_AUTHORIZATION_SIZE;\r
typedef UINT32 TPM_PARAMETER_SIZE;\r
typedef UINT16 TPM_KEY_SIZE;\r
\r
// Table 6 - TPM_GENERATED Constants\r
typedef UINT32 TPM_GENERATED;\r
-#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)\r
+#define TPM_GENERATED_VALUE (TPM_GENERATED)(0xff544347)\r
\r
// Table 7 - TPM_ALG_ID Constants\r
typedef UINT16 TPM_ALG_ID;\r
//\r
// NOTE: Comment some algo which has same name as TPM1.2 (value is same, so not runtime issue)\r
//\r
-#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000)\r
-#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001)\r
-//#define TPM_ALG_RSA (TPM_ALG_ID)(0x0001)\r
-//#define TPM_ALG_SHA (TPM_ALG_ID)(0x0004)\r
-#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004)\r
-//#define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005)\r
-#define TPM_ALG_AES (TPM_ALG_ID)(0x0006)\r
-//#define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007)\r
-#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008)\r
-//#define TPM_ALG_XOR (TPM_ALG_ID)(0x000A)\r
-#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B)\r
-#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C)\r
-#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D)\r
-#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010)\r
-#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012)\r
-#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013)\r
-#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014)\r
-#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015)\r
-#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016)\r
-#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017)\r
-#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018)\r
-#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019)\r
-#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A)\r
-#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B)\r
-#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C)\r
-#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D)\r
-#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)\r
-#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021)\r
-#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)\r
-#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023)\r
-#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025)\r
-#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040)\r
-#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041)\r
-#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042)\r
-#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043)\r
-#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044)\r
-#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044)\r
+#define TPM_ALG_ERROR (TPM_ALG_ID)(0x0000)\r
+#define TPM_ALG_FIRST (TPM_ALG_ID)(0x0001)\r
+// #define TPM_ALG_RSA (TPM_ALG_ID)(0x0001)\r
+// #define TPM_ALG_SHA (TPM_ALG_ID)(0x0004)\r
+#define TPM_ALG_SHA1 (TPM_ALG_ID)(0x0004)\r
+// #define TPM_ALG_HMAC (TPM_ALG_ID)(0x0005)\r
+#define TPM_ALG_AES (TPM_ALG_ID)(0x0006)\r
+// #define TPM_ALG_MGF1 (TPM_ALG_ID)(0x0007)\r
+#define TPM_ALG_KEYEDHASH (TPM_ALG_ID)(0x0008)\r
+// #define TPM_ALG_XOR (TPM_ALG_ID)(0x000A)\r
+#define TPM_ALG_SHA256 (TPM_ALG_ID)(0x000B)\r
+#define TPM_ALG_SHA384 (TPM_ALG_ID)(0x000C)\r
+#define TPM_ALG_SHA512 (TPM_ALG_ID)(0x000D)\r
+#define TPM_ALG_NULL (TPM_ALG_ID)(0x0010)\r
+#define TPM_ALG_SM3_256 (TPM_ALG_ID)(0x0012)\r
+#define TPM_ALG_SM4 (TPM_ALG_ID)(0x0013)\r
+#define TPM_ALG_RSASSA (TPM_ALG_ID)(0x0014)\r
+#define TPM_ALG_RSAES (TPM_ALG_ID)(0x0015)\r
+#define TPM_ALG_RSAPSS (TPM_ALG_ID)(0x0016)\r
+#define TPM_ALG_OAEP (TPM_ALG_ID)(0x0017)\r
+#define TPM_ALG_ECDSA (TPM_ALG_ID)(0x0018)\r
+#define TPM_ALG_ECDH (TPM_ALG_ID)(0x0019)\r
+#define TPM_ALG_ECDAA (TPM_ALG_ID)(0x001A)\r
+#define TPM_ALG_SM2 (TPM_ALG_ID)(0x001B)\r
+#define TPM_ALG_ECSCHNORR (TPM_ALG_ID)(0x001C)\r
+#define TPM_ALG_ECMQV (TPM_ALG_ID)(0x001D)\r
+#define TPM_ALG_KDF1_SP800_56a (TPM_ALG_ID)(0x0020)\r
+#define TPM_ALG_KDF2 (TPM_ALG_ID)(0x0021)\r
+#define TPM_ALG_KDF1_SP800_108 (TPM_ALG_ID)(0x0022)\r
+#define TPM_ALG_ECC (TPM_ALG_ID)(0x0023)\r
+#define TPM_ALG_SYMCIPHER (TPM_ALG_ID)(0x0025)\r
+#define TPM_ALG_CTR (TPM_ALG_ID)(0x0040)\r
+#define TPM_ALG_OFB (TPM_ALG_ID)(0x0041)\r
+#define TPM_ALG_CBC (TPM_ALG_ID)(0x0042)\r
+#define TPM_ALG_CFB (TPM_ALG_ID)(0x0043)\r
+#define TPM_ALG_ECB (TPM_ALG_ID)(0x0044)\r
+#define TPM_ALG_LAST (TPM_ALG_ID)(0x0044)\r
\r
// Table 8 - TPM_ECC_CURVE Constants\r
typedef UINT16 TPM_ECC_CURVE;\r
-#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)\r
-#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)\r
-#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)\r
-#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)\r
-#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)\r
-#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)\r
-#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)\r
-#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)\r
-#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)\r
+#define TPM_ECC_NONE (TPM_ECC_CURVE)(0x0000)\r
+#define TPM_ECC_NIST_P192 (TPM_ECC_CURVE)(0x0001)\r
+#define TPM_ECC_NIST_P224 (TPM_ECC_CURVE)(0x0002)\r
+#define TPM_ECC_NIST_P256 (TPM_ECC_CURVE)(0x0003)\r
+#define TPM_ECC_NIST_P384 (TPM_ECC_CURVE)(0x0004)\r
+#define TPM_ECC_NIST_P521 (TPM_ECC_CURVE)(0x0005)\r
+#define TPM_ECC_BN_P256 (TPM_ECC_CURVE)(0x0010)\r
+#define TPM_ECC_BN_P638 (TPM_ECC_CURVE)(0x0011)\r
+#define TPM_ECC_SM2_P256 (TPM_ECC_CURVE)(0x0020)\r
\r
// Table 11 - TPM_CC Constants (Numeric Order)\r
typedef UINT32 TPM_CC;\r
-#define TPM_CC_FIRST (TPM_CC)(0x0000011F)\r
-#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F)\r
-#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F)\r
-#define TPM_CC_EvictControl (TPM_CC)(0x00000120)\r
-#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121)\r
-#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122)\r
-#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124)\r
-#define TPM_CC_ChangePPS (TPM_CC)(0x00000125)\r
-#define TPM_CC_Clear (TPM_CC)(0x00000126)\r
-#define TPM_CC_ClearControl (TPM_CC)(0x00000127)\r
-#define TPM_CC_ClockSet (TPM_CC)(0x00000128)\r
-#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129)\r
-#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A)\r
-#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B)\r
-#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C)\r
-#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D)\r
-#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E)\r
-#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F)\r
-#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130)\r
-#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131)\r
-#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132)\r
-#define TPM_CC_PP_LAST (TPM_CC)(0x00000132)\r
-#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133)\r
-#define TPM_CC_NV_Increment (TPM_CC)(0x00000134)\r
-#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135)\r
-#define TPM_CC_NV_Extend (TPM_CC)(0x00000136)\r
-#define TPM_CC_NV_Write (TPM_CC)(0x00000137)\r
-#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138)\r
-#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139)\r
-#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)\r
-#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B)\r
-#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C)\r
-#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D)\r
-#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E)\r
-#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F)\r
-#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140)\r
-#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141)\r
-#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142)\r
-#define TPM_CC_SelfTest (TPM_CC)(0x00000143)\r
-#define TPM_CC_Startup (TPM_CC)(0x00000144)\r
-#define TPM_CC_Shutdown (TPM_CC)(0x00000145)\r
-#define TPM_CC_StirRandom (TPM_CC)(0x00000146)\r
-#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147)\r
-#define TPM_CC_Certify (TPM_CC)(0x00000148)\r
-#define TPM_CC_PolicyNV (TPM_CC)(0x00000149)\r
-#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A)\r
-#define TPM_CC_Duplicate (TPM_CC)(0x0000014B)\r
-#define TPM_CC_GetTime (TPM_CC)(0x0000014C)\r
-#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D)\r
-#define TPM_CC_NV_Read (TPM_CC)(0x0000014E)\r
-#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F)\r
-#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150)\r
-#define TPM_CC_PolicySecret (TPM_CC)(0x00000151)\r
-#define TPM_CC_Rewrap (TPM_CC)(0x00000152)\r
-#define TPM_CC_Create (TPM_CC)(0x00000153)\r
-#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154)\r
-#define TPM_CC_HMAC (TPM_CC)(0x00000155)\r
-#define TPM_CC_Import (TPM_CC)(0x00000156)\r
-#define TPM_CC_Load (TPM_CC)(0x00000157)\r
-#define TPM_CC_Quote (TPM_CC)(0x00000158)\r
-#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159)\r
-#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B)\r
-#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C)\r
-#define TPM_CC_Sign (TPM_CC)(0x0000015D)\r
-#define TPM_CC_Unseal (TPM_CC)(0x0000015E)\r
-#define TPM_CC_PolicySigned (TPM_CC)(0x00000160)\r
-#define TPM_CC_ContextLoad (TPM_CC)(0x00000161)\r
-#define TPM_CC_ContextSave (TPM_CC)(0x00000162)\r
-#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163)\r
-#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164)\r
-#define TPM_CC_FlushContext (TPM_CC)(0x00000165)\r
-#define TPM_CC_LoadExternal (TPM_CC)(0x00000167)\r
-#define TPM_CC_MakeCredential (TPM_CC)(0x00000168)\r
-#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169)\r
-#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A)\r
-#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B)\r
-#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C)\r
-#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D)\r
-#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E)\r
-#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F)\r
-#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170)\r
-#define TPM_CC_PolicyOR (TPM_CC)(0x00000171)\r
-#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172)\r
-#define TPM_CC_ReadPublic (TPM_CC)(0x00000173)\r
-#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174)\r
-#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176)\r
-#define TPM_CC_VerifySignature (TPM_CC)(0x00000177)\r
-#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178)\r
-#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179)\r
-#define TPM_CC_GetCapability (TPM_CC)(0x0000017A)\r
-#define TPM_CC_GetRandom (TPM_CC)(0x0000017B)\r
-#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C)\r
-#define TPM_CC_Hash (TPM_CC)(0x0000017D)\r
-#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E)\r
-#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F)\r
-#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180)\r
-#define TPM_CC_ReadClock (TPM_CC)(0x00000181)\r
-#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182)\r
-#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183)\r
-#define TPM_CC_NV_Certify (TPM_CC)(0x00000184)\r
-#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185)\r
-#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186)\r
-#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187)\r
-#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188)\r
-#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189)\r
-#define TPM_CC_TestParms (TPM_CC)(0x0000018A)\r
-#define TPM_CC_Commit (TPM_CC)(0x0000018B)\r
-#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C)\r
-#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D)\r
-#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E)\r
-#define TPM_CC_LAST (TPM_CC)(0x0000018E)\r
+#define TPM_CC_FIRST (TPM_CC)(0x0000011F)\r
+#define TPM_CC_PP_FIRST (TPM_CC)(0x0000011F)\r
+#define TPM_CC_NV_UndefineSpaceSpecial (TPM_CC)(0x0000011F)\r
+#define TPM_CC_EvictControl (TPM_CC)(0x00000120)\r
+#define TPM_CC_HierarchyControl (TPM_CC)(0x00000121)\r
+#define TPM_CC_NV_UndefineSpace (TPM_CC)(0x00000122)\r
+#define TPM_CC_ChangeEPS (TPM_CC)(0x00000124)\r
+#define TPM_CC_ChangePPS (TPM_CC)(0x00000125)\r
+#define TPM_CC_Clear (TPM_CC)(0x00000126)\r
+#define TPM_CC_ClearControl (TPM_CC)(0x00000127)\r
+#define TPM_CC_ClockSet (TPM_CC)(0x00000128)\r
+#define TPM_CC_HierarchyChangeAuth (TPM_CC)(0x00000129)\r
+#define TPM_CC_NV_DefineSpace (TPM_CC)(0x0000012A)\r
+#define TPM_CC_PCR_Allocate (TPM_CC)(0x0000012B)\r
+#define TPM_CC_PCR_SetAuthPolicy (TPM_CC)(0x0000012C)\r
+#define TPM_CC_PP_Commands (TPM_CC)(0x0000012D)\r
+#define TPM_CC_SetPrimaryPolicy (TPM_CC)(0x0000012E)\r
+#define TPM_CC_FieldUpgradeStart (TPM_CC)(0x0000012F)\r
+#define TPM_CC_ClockRateAdjust (TPM_CC)(0x00000130)\r
+#define TPM_CC_CreatePrimary (TPM_CC)(0x00000131)\r
+#define TPM_CC_NV_GlobalWriteLock (TPM_CC)(0x00000132)\r
+#define TPM_CC_PP_LAST (TPM_CC)(0x00000132)\r
+#define TPM_CC_GetCommandAuditDigest (TPM_CC)(0x00000133)\r
+#define TPM_CC_NV_Increment (TPM_CC)(0x00000134)\r
+#define TPM_CC_NV_SetBits (TPM_CC)(0x00000135)\r
+#define TPM_CC_NV_Extend (TPM_CC)(0x00000136)\r
+#define TPM_CC_NV_Write (TPM_CC)(0x00000137)\r
+#define TPM_CC_NV_WriteLock (TPM_CC)(0x00000138)\r
+#define TPM_CC_DictionaryAttackLockReset (TPM_CC)(0x00000139)\r
+#define TPM_CC_DictionaryAttackParameters (TPM_CC)(0x0000013A)\r
+#define TPM_CC_NV_ChangeAuth (TPM_CC)(0x0000013B)\r
+#define TPM_CC_PCR_Event (TPM_CC)(0x0000013C)\r
+#define TPM_CC_PCR_Reset (TPM_CC)(0x0000013D)\r
+#define TPM_CC_SequenceComplete (TPM_CC)(0x0000013E)\r
+#define TPM_CC_SetAlgorithmSet (TPM_CC)(0x0000013F)\r
+#define TPM_CC_SetCommandCodeAuditStatus (TPM_CC)(0x00000140)\r
+#define TPM_CC_FieldUpgradeData (TPM_CC)(0x00000141)\r
+#define TPM_CC_IncrementalSelfTest (TPM_CC)(0x00000142)\r
+#define TPM_CC_SelfTest (TPM_CC)(0x00000143)\r
+#define TPM_CC_Startup (TPM_CC)(0x00000144)\r
+#define TPM_CC_Shutdown (TPM_CC)(0x00000145)\r
+#define TPM_CC_StirRandom (TPM_CC)(0x00000146)\r
+#define TPM_CC_ActivateCredential (TPM_CC)(0x00000147)\r
+#define TPM_CC_Certify (TPM_CC)(0x00000148)\r
+#define TPM_CC_PolicyNV (TPM_CC)(0x00000149)\r
+#define TPM_CC_CertifyCreation (TPM_CC)(0x0000014A)\r
+#define TPM_CC_Duplicate (TPM_CC)(0x0000014B)\r
+#define TPM_CC_GetTime (TPM_CC)(0x0000014C)\r
+#define TPM_CC_GetSessionAuditDigest (TPM_CC)(0x0000014D)\r
+#define TPM_CC_NV_Read (TPM_CC)(0x0000014E)\r
+#define TPM_CC_NV_ReadLock (TPM_CC)(0x0000014F)\r
+#define TPM_CC_ObjectChangeAuth (TPM_CC)(0x00000150)\r
+#define TPM_CC_PolicySecret (TPM_CC)(0x00000151)\r
+#define TPM_CC_Rewrap (TPM_CC)(0x00000152)\r
+#define TPM_CC_Create (TPM_CC)(0x00000153)\r
+#define TPM_CC_ECDH_ZGen (TPM_CC)(0x00000154)\r
+#define TPM_CC_HMAC (TPM_CC)(0x00000155)\r
+#define TPM_CC_Import (TPM_CC)(0x00000156)\r
+#define TPM_CC_Load (TPM_CC)(0x00000157)\r
+#define TPM_CC_Quote (TPM_CC)(0x00000158)\r
+#define TPM_CC_RSA_Decrypt (TPM_CC)(0x00000159)\r
+#define TPM_CC_HMAC_Start (TPM_CC)(0x0000015B)\r
+#define TPM_CC_SequenceUpdate (TPM_CC)(0x0000015C)\r
+#define TPM_CC_Sign (TPM_CC)(0x0000015D)\r
+#define TPM_CC_Unseal (TPM_CC)(0x0000015E)\r
+#define TPM_CC_PolicySigned (TPM_CC)(0x00000160)\r
+#define TPM_CC_ContextLoad (TPM_CC)(0x00000161)\r
+#define TPM_CC_ContextSave (TPM_CC)(0x00000162)\r
+#define TPM_CC_ECDH_KeyGen (TPM_CC)(0x00000163)\r
+#define TPM_CC_EncryptDecrypt (TPM_CC)(0x00000164)\r
+#define TPM_CC_FlushContext (TPM_CC)(0x00000165)\r
+#define TPM_CC_LoadExternal (TPM_CC)(0x00000167)\r
+#define TPM_CC_MakeCredential (TPM_CC)(0x00000168)\r
+#define TPM_CC_NV_ReadPublic (TPM_CC)(0x00000169)\r
+#define TPM_CC_PolicyAuthorize (TPM_CC)(0x0000016A)\r
+#define TPM_CC_PolicyAuthValue (TPM_CC)(0x0000016B)\r
+#define TPM_CC_PolicyCommandCode (TPM_CC)(0x0000016C)\r
+#define TPM_CC_PolicyCounterTimer (TPM_CC)(0x0000016D)\r
+#define TPM_CC_PolicyCpHash (TPM_CC)(0x0000016E)\r
+#define TPM_CC_PolicyLocality (TPM_CC)(0x0000016F)\r
+#define TPM_CC_PolicyNameHash (TPM_CC)(0x00000170)\r
+#define TPM_CC_PolicyOR (TPM_CC)(0x00000171)\r
+#define TPM_CC_PolicyTicket (TPM_CC)(0x00000172)\r
+#define TPM_CC_ReadPublic (TPM_CC)(0x00000173)\r
+#define TPM_CC_RSA_Encrypt (TPM_CC)(0x00000174)\r
+#define TPM_CC_StartAuthSession (TPM_CC)(0x00000176)\r
+#define TPM_CC_VerifySignature (TPM_CC)(0x00000177)\r
+#define TPM_CC_ECC_Parameters (TPM_CC)(0x00000178)\r
+#define TPM_CC_FirmwareRead (TPM_CC)(0x00000179)\r
+#define TPM_CC_GetCapability (TPM_CC)(0x0000017A)\r
+#define TPM_CC_GetRandom (TPM_CC)(0x0000017B)\r
+#define TPM_CC_GetTestResult (TPM_CC)(0x0000017C)\r
+#define TPM_CC_Hash (TPM_CC)(0x0000017D)\r
+#define TPM_CC_PCR_Read (TPM_CC)(0x0000017E)\r
+#define TPM_CC_PolicyPCR (TPM_CC)(0x0000017F)\r
+#define TPM_CC_PolicyRestart (TPM_CC)(0x00000180)\r
+#define TPM_CC_ReadClock (TPM_CC)(0x00000181)\r
+#define TPM_CC_PCR_Extend (TPM_CC)(0x00000182)\r
+#define TPM_CC_PCR_SetAuthValue (TPM_CC)(0x00000183)\r
+#define TPM_CC_NV_Certify (TPM_CC)(0x00000184)\r
+#define TPM_CC_EventSequenceComplete (TPM_CC)(0x00000185)\r
+#define TPM_CC_HashSequenceStart (TPM_CC)(0x00000186)\r
+#define TPM_CC_PolicyPhysicalPresence (TPM_CC)(0x00000187)\r
+#define TPM_CC_PolicyDuplicationSelect (TPM_CC)(0x00000188)\r
+#define TPM_CC_PolicyGetDigest (TPM_CC)(0x00000189)\r
+#define TPM_CC_TestParms (TPM_CC)(0x0000018A)\r
+#define TPM_CC_Commit (TPM_CC)(0x0000018B)\r
+#define TPM_CC_PolicyPassword (TPM_CC)(0x0000018C)\r
+#define TPM_CC_ZGen_2Phase (TPM_CC)(0x0000018D)\r
+#define TPM_CC_EC_Ephemeral (TPM_CC)(0x0000018E)\r
+#define TPM_CC_LAST (TPM_CC)(0x0000018E)\r
\r
// Table 15 - TPM_RC Constants (Actions)\r
typedef UINT32 TPM_RC;\r
-#define TPM_RC_SUCCESS (TPM_RC)(0x000)\r
-#define TPM_RC_BAD_TAG (TPM_RC)(0x030)\r
-#define RC_VER1 (TPM_RC)(0x100)\r
-#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000)\r
-#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001)\r
-#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003)\r
-#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B)\r
-#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019)\r
-#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020)\r
-#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021)\r
-#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024)\r
-#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025)\r
-#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026)\r
-#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027)\r
-#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028)\r
-#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D)\r
-#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)\r
-#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F)\r
-#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030)\r
-#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031)\r
-#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042)\r
-#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043)\r
-#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044)\r
-#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045)\r
-#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046)\r
-#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047)\r
-#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048)\r
-#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049)\r
-#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A)\r
-#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B)\r
-#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C)\r
-#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050)\r
-#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051)\r
-#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052)\r
-#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053)\r
-#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054)\r
-#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055)\r
-#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F)\r
-#define RC_FMT1 (TPM_RC)(0x080)\r
-#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001)\r
-#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002)\r
-#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003)\r
-#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004)\r
-#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005)\r
-#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007)\r
-#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008)\r
-#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009)\r
-#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A)\r
-#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B)\r
-#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C)\r
-#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D)\r
-#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E)\r
-#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F)\r
-#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010)\r
-#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012)\r
-#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015)\r
-#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016)\r
-#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017)\r
-#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018)\r
-#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A)\r
-#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B)\r
-#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C)\r
-#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D)\r
-#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F)\r
-#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020)\r
-#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021)\r
-#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022)\r
-#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023)\r
-#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 )\r
-#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025)\r
-#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026)\r
-#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027)\r
-#define RC_WARN (TPM_RC)(0x900)\r
-#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001)\r
-#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002)\r
-#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003)\r
-#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004)\r
-#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005)\r
-#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006)\r
-#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007)\r
-#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008)\r
-#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009)\r
-#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A)\r
-#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010)\r
-#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011)\r
-#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012)\r
-#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013)\r
-#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014)\r
-#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015)\r
-#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016)\r
-#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018)\r
-#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019)\r
-#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A)\r
-#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B)\r
-#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C)\r
-#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D)\r
-#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E)\r
-#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020)\r
-#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021)\r
-#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022)\r
-#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023)\r
-#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F)\r
-#define TPM_RC_H (TPM_RC)(0x000)\r
-#define TPM_RC_P (TPM_RC)(0x040)\r
-#define TPM_RC_S (TPM_RC)(0x800)\r
-#define TPM_RC_1 (TPM_RC)(0x100)\r
-#define TPM_RC_2 (TPM_RC)(0x200)\r
-#define TPM_RC_3 (TPM_RC)(0x300)\r
-#define TPM_RC_4 (TPM_RC)(0x400)\r
-#define TPM_RC_5 (TPM_RC)(0x500)\r
-#define TPM_RC_6 (TPM_RC)(0x600)\r
-#define TPM_RC_7 (TPM_RC)(0x700)\r
-#define TPM_RC_8 (TPM_RC)(0x800)\r
-#define TPM_RC_9 (TPM_RC)(0x900)\r
-#define TPM_RC_A (TPM_RC)(0xA00)\r
-#define TPM_RC_B (TPM_RC)(0xB00)\r
-#define TPM_RC_C (TPM_RC)(0xC00)\r
-#define TPM_RC_D (TPM_RC)(0xD00)\r
-#define TPM_RC_E (TPM_RC)(0xE00)\r
-#define TPM_RC_F (TPM_RC)(0xF00)\r
-#define TPM_RC_N_MASK (TPM_RC)(0xF00)\r
+#define TPM_RC_SUCCESS (TPM_RC)(0x000)\r
+#define TPM_RC_BAD_TAG (TPM_RC)(0x030)\r
+#define RC_VER1 (TPM_RC)(0x100)\r
+#define TPM_RC_INITIALIZE (TPM_RC)(RC_VER1 + 0x000)\r
+#define TPM_RC_FAILURE (TPM_RC)(RC_VER1 + 0x001)\r
+#define TPM_RC_SEQUENCE (TPM_RC)(RC_VER1 + 0x003)\r
+#define TPM_RC_PRIVATE (TPM_RC)(RC_VER1 + 0x00B)\r
+#define TPM_RC_HMAC (TPM_RC)(RC_VER1 + 0x019)\r
+#define TPM_RC_DISABLED (TPM_RC)(RC_VER1 + 0x020)\r
+#define TPM_RC_EXCLUSIVE (TPM_RC)(RC_VER1 + 0x021)\r
+#define TPM_RC_AUTH_TYPE (TPM_RC)(RC_VER1 + 0x024)\r
+#define TPM_RC_AUTH_MISSING (TPM_RC)(RC_VER1 + 0x025)\r
+#define TPM_RC_POLICY (TPM_RC)(RC_VER1 + 0x026)\r
+#define TPM_RC_PCR (TPM_RC)(RC_VER1 + 0x027)\r
+#define TPM_RC_PCR_CHANGED (TPM_RC)(RC_VER1 + 0x028)\r
+#define TPM_RC_UPGRADE (TPM_RC)(RC_VER1 + 0x02D)\r
+#define TPM_RC_TOO_MANY_CONTEXTS (TPM_RC)(RC_VER1 + 0x02E)\r
+#define TPM_RC_AUTH_UNAVAILABLE (TPM_RC)(RC_VER1 + 0x02F)\r
+#define TPM_RC_REBOOT (TPM_RC)(RC_VER1 + 0x030)\r
+#define TPM_RC_UNBALANCED (TPM_RC)(RC_VER1 + 0x031)\r
+#define TPM_RC_COMMAND_SIZE (TPM_RC)(RC_VER1 + 0x042)\r
+#define TPM_RC_COMMAND_CODE (TPM_RC)(RC_VER1 + 0x043)\r
+#define TPM_RC_AUTHSIZE (TPM_RC)(RC_VER1 + 0x044)\r
+#define TPM_RC_AUTH_CONTEXT (TPM_RC)(RC_VER1 + 0x045)\r
+#define TPM_RC_NV_RANGE (TPM_RC)(RC_VER1 + 0x046)\r
+#define TPM_RC_NV_SIZE (TPM_RC)(RC_VER1 + 0x047)\r
+#define TPM_RC_NV_LOCKED (TPM_RC)(RC_VER1 + 0x048)\r
+#define TPM_RC_NV_AUTHORIZATION (TPM_RC)(RC_VER1 + 0x049)\r
+#define TPM_RC_NV_UNINITIALIZED (TPM_RC)(RC_VER1 + 0x04A)\r
+#define TPM_RC_NV_SPACE (TPM_RC)(RC_VER1 + 0x04B)\r
+#define TPM_RC_NV_DEFINED (TPM_RC)(RC_VER1 + 0x04C)\r
+#define TPM_RC_BAD_CONTEXT (TPM_RC)(RC_VER1 + 0x050)\r
+#define TPM_RC_CPHASH (TPM_RC)(RC_VER1 + 0x051)\r
+#define TPM_RC_PARENT (TPM_RC)(RC_VER1 + 0x052)\r
+#define TPM_RC_NEEDS_TEST (TPM_RC)(RC_VER1 + 0x053)\r
+#define TPM_RC_NO_RESULT (TPM_RC)(RC_VER1 + 0x054)\r
+#define TPM_RC_SENSITIVE (TPM_RC)(RC_VER1 + 0x055)\r
+#define RC_MAX_FM0 (TPM_RC)(RC_VER1 + 0x07F)\r
+#define RC_FMT1 (TPM_RC)(0x080)\r
+#define TPM_RC_ASYMMETRIC (TPM_RC)(RC_FMT1 + 0x001)\r
+#define TPM_RC_ATTRIBUTES (TPM_RC)(RC_FMT1 + 0x002)\r
+#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003)\r
+#define TPM_RC_VALUE (TPM_RC)(RC_FMT1 + 0x004)\r
+#define TPM_RC_HIERARCHY (TPM_RC)(RC_FMT1 + 0x005)\r
+#define TPM_RC_KEY_SIZE (TPM_RC)(RC_FMT1 + 0x007)\r
+#define TPM_RC_MGF (TPM_RC)(RC_FMT1 + 0x008)\r
+#define TPM_RC_MODE (TPM_RC)(RC_FMT1 + 0x009)\r
+#define TPM_RC_TYPE (TPM_RC)(RC_FMT1 + 0x00A)\r
+#define TPM_RC_HANDLE (TPM_RC)(RC_FMT1 + 0x00B)\r
+#define TPM_RC_KDF (TPM_RC)(RC_FMT1 + 0x00C)\r
+#define TPM_RC_RANGE (TPM_RC)(RC_FMT1 + 0x00D)\r
+#define TPM_RC_AUTH_FAIL (TPM_RC)(RC_FMT1 + 0x00E)\r
+#define TPM_RC_NONCE (TPM_RC)(RC_FMT1 + 0x00F)\r
+#define TPM_RC_PP (TPM_RC)(RC_FMT1 + 0x010)\r
+#define TPM_RC_SCHEME (TPM_RC)(RC_FMT1 + 0x012)\r
+#define TPM_RC_SIZE (TPM_RC)(RC_FMT1 + 0x015)\r
+#define TPM_RC_SYMMETRIC (TPM_RC)(RC_FMT1 + 0x016)\r
+#define TPM_RC_TAG (TPM_RC)(RC_FMT1 + 0x017)\r
+#define TPM_RC_SELECTOR (TPM_RC)(RC_FMT1 + 0x018)\r
+#define TPM_RC_INSUFFICIENT (TPM_RC)(RC_FMT1 + 0x01A)\r
+#define TPM_RC_SIGNATURE (TPM_RC)(RC_FMT1 + 0x01B)\r
+#define TPM_RC_KEY (TPM_RC)(RC_FMT1 + 0x01C)\r
+#define TPM_RC_POLICY_FAIL (TPM_RC)(RC_FMT1 + 0x01D)\r
+#define TPM_RC_INTEGRITY (TPM_RC)(RC_FMT1 + 0x01F)\r
+#define TPM_RC_TICKET (TPM_RC)(RC_FMT1 + 0x020)\r
+#define TPM_RC_RESERVED_BITS (TPM_RC)(RC_FMT1 + 0x021)\r
+#define TPM_RC_BAD_AUTH (TPM_RC)(RC_FMT1 + 0x022)\r
+#define TPM_RC_EXPIRED (TPM_RC)(RC_FMT1 + 0x023)\r
+#define TPM_RC_POLICY_CC (TPM_RC)(RC_FMT1 + 0x024 )\r
+#define TPM_RC_BINDING (TPM_RC)(RC_FMT1 + 0x025)\r
+#define TPM_RC_CURVE (TPM_RC)(RC_FMT1 + 0x026)\r
+#define TPM_RC_ECC_POINT (TPM_RC)(RC_FMT1 + 0x027)\r
+#define RC_WARN (TPM_RC)(0x900)\r
+#define TPM_RC_CONTEXT_GAP (TPM_RC)(RC_WARN + 0x001)\r
+#define TPM_RC_OBJECT_MEMORY (TPM_RC)(RC_WARN + 0x002)\r
+#define TPM_RC_SESSION_MEMORY (TPM_RC)(RC_WARN + 0x003)\r
+#define TPM_RC_MEMORY (TPM_RC)(RC_WARN + 0x004)\r
+#define TPM_RC_SESSION_HANDLES (TPM_RC)(RC_WARN + 0x005)\r
+#define TPM_RC_OBJECT_HANDLES (TPM_RC)(RC_WARN + 0x006)\r
+#define TPM_RC_LOCALITY (TPM_RC)(RC_WARN + 0x007)\r
+#define TPM_RC_YIELDED (TPM_RC)(RC_WARN + 0x008)\r
+#define TPM_RC_CANCELED (TPM_RC)(RC_WARN + 0x009)\r
+#define TPM_RC_TESTING (TPM_RC)(RC_WARN + 0x00A)\r
+#define TPM_RC_REFERENCE_H0 (TPM_RC)(RC_WARN + 0x010)\r
+#define TPM_RC_REFERENCE_H1 (TPM_RC)(RC_WARN + 0x011)\r
+#define TPM_RC_REFERENCE_H2 (TPM_RC)(RC_WARN + 0x012)\r
+#define TPM_RC_REFERENCE_H3 (TPM_RC)(RC_WARN + 0x013)\r
+#define TPM_RC_REFERENCE_H4 (TPM_RC)(RC_WARN + 0x014)\r
+#define TPM_RC_REFERENCE_H5 (TPM_RC)(RC_WARN + 0x015)\r
+#define TPM_RC_REFERENCE_H6 (TPM_RC)(RC_WARN + 0x016)\r
+#define TPM_RC_REFERENCE_S0 (TPM_RC)(RC_WARN + 0x018)\r
+#define TPM_RC_REFERENCE_S1 (TPM_RC)(RC_WARN + 0x019)\r
+#define TPM_RC_REFERENCE_S2 (TPM_RC)(RC_WARN + 0x01A)\r
+#define TPM_RC_REFERENCE_S3 (TPM_RC)(RC_WARN + 0x01B)\r
+#define TPM_RC_REFERENCE_S4 (TPM_RC)(RC_WARN + 0x01C)\r
+#define TPM_RC_REFERENCE_S5 (TPM_RC)(RC_WARN + 0x01D)\r
+#define TPM_RC_REFERENCE_S6 (TPM_RC)(RC_WARN + 0x01E)\r
+#define TPM_RC_NV_RATE (TPM_RC)(RC_WARN + 0x020)\r
+#define TPM_RC_LOCKOUT (TPM_RC)(RC_WARN + 0x021)\r
+#define TPM_RC_RETRY (TPM_RC)(RC_WARN + 0x022)\r
+#define TPM_RC_NV_UNAVAILABLE (TPM_RC)(RC_WARN + 0x023)\r
+#define TPM_RC_NOT_USED (TPM_RC)(RC_WARN + 0x7F)\r
+#define TPM_RC_H (TPM_RC)(0x000)\r
+#define TPM_RC_P (TPM_RC)(0x040)\r
+#define TPM_RC_S (TPM_RC)(0x800)\r
+#define TPM_RC_1 (TPM_RC)(0x100)\r
+#define TPM_RC_2 (TPM_RC)(0x200)\r
+#define TPM_RC_3 (TPM_RC)(0x300)\r
+#define TPM_RC_4 (TPM_RC)(0x400)\r
+#define TPM_RC_5 (TPM_RC)(0x500)\r
+#define TPM_RC_6 (TPM_RC)(0x600)\r
+#define TPM_RC_7 (TPM_RC)(0x700)\r
+#define TPM_RC_8 (TPM_RC)(0x800)\r
+#define TPM_RC_9 (TPM_RC)(0x900)\r
+#define TPM_RC_A (TPM_RC)(0xA00)\r
+#define TPM_RC_B (TPM_RC)(0xB00)\r
+#define TPM_RC_C (TPM_RC)(0xC00)\r
+#define TPM_RC_D (TPM_RC)(0xD00)\r
+#define TPM_RC_E (TPM_RC)(0xE00)\r
+#define TPM_RC_F (TPM_RC)(0xF00)\r
+#define TPM_RC_N_MASK (TPM_RC)(0xF00)\r
\r
// Table 16 - TPM_CLOCK_ADJUST Constants\r
typedef INT8 TPM_CLOCK_ADJUST;\r
-#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)\r
-#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)\r
-#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1)\r
-#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0)\r
-#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1)\r
-#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)\r
-#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)\r
+#define TPM_CLOCK_COARSE_SLOWER (TPM_CLOCK_ADJUST)(-3)\r
+#define TPM_CLOCK_MEDIUM_SLOWER (TPM_CLOCK_ADJUST)(-2)\r
+#define TPM_CLOCK_FINE_SLOWER (TPM_CLOCK_ADJUST)(-1)\r
+#define TPM_CLOCK_NO_CHANGE (TPM_CLOCK_ADJUST)(0)\r
+#define TPM_CLOCK_FINE_FASTER (TPM_CLOCK_ADJUST)(1)\r
+#define TPM_CLOCK_MEDIUM_FASTER (TPM_CLOCK_ADJUST)(2)\r
+#define TPM_CLOCK_COARSE_FASTER (TPM_CLOCK_ADJUST)(3)\r
\r
// Table 17 - TPM_EO Constants\r
typedef UINT16 TPM_EO;\r
-#define TPM_EO_EQ (TPM_EO)(0x0000)\r
-#define TPM_EO_NEQ (TPM_EO)(0x0001)\r
-#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002)\r
-#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)\r
-#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004)\r
-#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)\r
-#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006)\r
-#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)\r
-#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008)\r
-#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)\r
-#define TPM_EO_BITSET (TPM_EO)(0x000A)\r
-#define TPM_EO_BITCLEAR (TPM_EO)(0x000B)\r
+#define TPM_EO_EQ (TPM_EO)(0x0000)\r
+#define TPM_EO_NEQ (TPM_EO)(0x0001)\r
+#define TPM_EO_SIGNED_GT (TPM_EO)(0x0002)\r
+#define TPM_EO_UNSIGNED_GT (TPM_EO)(0x0003)\r
+#define TPM_EO_SIGNED_LT (TPM_EO)(0x0004)\r
+#define TPM_EO_UNSIGNED_LT (TPM_EO)(0x0005)\r
+#define TPM_EO_SIGNED_GE (TPM_EO)(0x0006)\r
+#define TPM_EO_UNSIGNED_GE (TPM_EO)(0x0007)\r
+#define TPM_EO_SIGNED_LE (TPM_EO)(0x0008)\r
+#define TPM_EO_UNSIGNED_LE (TPM_EO)(0x0009)\r
+#define TPM_EO_BITSET (TPM_EO)(0x000A)\r
+#define TPM_EO_BITCLEAR (TPM_EO)(0x000B)\r
\r
// Table 18 - TPM_ST Constants\r
typedef UINT16 TPM_ST;\r
-#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4)\r
-#define TPM_ST_NULL (TPM_ST)(0X8000)\r
-#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001)\r
-#define TPM_ST_SESSIONS (TPM_ST)(0x8002)\r
-#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014)\r
-#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)\r
-#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)\r
-#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017)\r
-#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018)\r
-#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019)\r
-#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A)\r
-#define TPM_ST_CREATION (TPM_ST)(0x8021)\r
-#define TPM_ST_VERIFIED (TPM_ST)(0x8022)\r
-#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023)\r
-#define TPM_ST_HASHCHECK (TPM_ST)(0x8024)\r
-#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025)\r
-#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029)\r
+#define TPM_ST_RSP_COMMAND (TPM_ST)(0x00C4)\r
+#define TPM_ST_NULL (TPM_ST)(0X8000)\r
+#define TPM_ST_NO_SESSIONS (TPM_ST)(0x8001)\r
+#define TPM_ST_SESSIONS (TPM_ST)(0x8002)\r
+#define TPM_ST_ATTEST_NV (TPM_ST)(0x8014)\r
+#define TPM_ST_ATTEST_COMMAND_AUDIT (TPM_ST)(0x8015)\r
+#define TPM_ST_ATTEST_SESSION_AUDIT (TPM_ST)(0x8016)\r
+#define TPM_ST_ATTEST_CERTIFY (TPM_ST)(0x8017)\r
+#define TPM_ST_ATTEST_QUOTE (TPM_ST)(0x8018)\r
+#define TPM_ST_ATTEST_TIME (TPM_ST)(0x8019)\r
+#define TPM_ST_ATTEST_CREATION (TPM_ST)(0x801A)\r
+#define TPM_ST_CREATION (TPM_ST)(0x8021)\r
+#define TPM_ST_VERIFIED (TPM_ST)(0x8022)\r
+#define TPM_ST_AUTH_SECRET (TPM_ST)(0x8023)\r
+#define TPM_ST_HASHCHECK (TPM_ST)(0x8024)\r
+#define TPM_ST_AUTH_SIGNED (TPM_ST)(0x8025)\r
+#define TPM_ST_FU_MANIFEST (TPM_ST)(0x8029)\r
\r
// Table 19 - TPM_SU Constants\r
typedef UINT16 TPM_SU;\r
-#define TPM_SU_CLEAR (TPM_SU)(0x0000)\r
-#define TPM_SU_STATE (TPM_SU)(0x0001)\r
+#define TPM_SU_CLEAR (TPM_SU)(0x0000)\r
+#define TPM_SU_STATE (TPM_SU)(0x0001)\r
\r
// Table 20 - TPM_SE Constants\r
typedef UINT8 TPM_SE;\r
-#define TPM_SE_HMAC (TPM_SE)(0x00)\r
-#define TPM_SE_POLICY (TPM_SE)(0x01)\r
-#define TPM_SE_TRIAL (TPM_SE)(0x03)\r
+#define TPM_SE_HMAC (TPM_SE)(0x00)\r
+#define TPM_SE_POLICY (TPM_SE)(0x01)\r
+#define TPM_SE_TRIAL (TPM_SE)(0x03)\r
\r
// Table 21 - TPM_CAP Constants\r
typedef UINT32 TPM_CAP;\r
-#define TPM_CAP_FIRST (TPM_CAP)(0x00000000)\r
-#define TPM_CAP_ALGS (TPM_CAP)(0x00000000)\r
-#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001)\r
-#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002)\r
-#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003)\r
-#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004)\r
-#define TPM_CAP_PCRS (TPM_CAP)(0x00000005)\r
-#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006)\r
-#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007)\r
-#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008)\r
-#define TPM_CAP_LAST (TPM_CAP)(0x00000008)\r
-#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)\r
+#define TPM_CAP_FIRST (TPM_CAP)(0x00000000)\r
+#define TPM_CAP_ALGS (TPM_CAP)(0x00000000)\r
+#define TPM_CAP_HANDLES (TPM_CAP)(0x00000001)\r
+#define TPM_CAP_COMMANDS (TPM_CAP)(0x00000002)\r
+#define TPM_CAP_PP_COMMANDS (TPM_CAP)(0x00000003)\r
+#define TPM_CAP_AUDIT_COMMANDS (TPM_CAP)(0x00000004)\r
+#define TPM_CAP_PCRS (TPM_CAP)(0x00000005)\r
+#define TPM_CAP_TPM_PROPERTIES (TPM_CAP)(0x00000006)\r
+#define TPM_CAP_PCR_PROPERTIES (TPM_CAP)(0x00000007)\r
+#define TPM_CAP_ECC_CURVES (TPM_CAP)(0x00000008)\r
+#define TPM_CAP_LAST (TPM_CAP)(0x00000008)\r
+#define TPM_CAP_VENDOR_PROPERTY (TPM_CAP)(0x00000100)\r
\r
// Table 22 - TPM_PT Constants\r
typedef UINT32 TPM_PT;\r
-#define TPM_PT_NONE (TPM_PT)(0x00000000)\r
-#define PT_GROUP (TPM_PT)(0x00000100)\r
-#define PT_FIXED (TPM_PT)(PT_GROUP * 1)\r
-#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0)\r
-#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1)\r
-#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2)\r
-#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3)\r
-#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4)\r
-#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5)\r
-#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6)\r
-#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7)\r
-#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8)\r
-#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9)\r
-#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10)\r
-#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11)\r
-#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12)\r
-#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13)\r
-#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14)\r
-#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15)\r
-#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16)\r
-#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)\r
-#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18)\r
-#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19)\r
-#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20)\r
-#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22)\r
-#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23)\r
-#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24)\r
-#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25)\r
-#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26)\r
-#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27)\r
-#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28)\r
-#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29)\r
-#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30)\r
-#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31)\r
-#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32)\r
-#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33)\r
-#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)\r
-#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)\r
-#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36)\r
-#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37)\r
-#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38)\r
-#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39)\r
-#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40)\r
-#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41)\r
-#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42)\r
-#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43)\r
-#define PT_VAR (TPM_PT)(PT_GROUP * 2)\r
-#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0)\r
-#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1)\r
-#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2)\r
-#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3)\r
-#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4)\r
-#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5)\r
-#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6)\r
-#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7)\r
-#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8)\r
-#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)\r
-#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10)\r
-#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11)\r
-#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12)\r
-#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13)\r
-#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14)\r
-#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15)\r
-#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16)\r
-#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17)\r
-#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18)\r
-#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19)\r
-#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20)\r
+#define TPM_PT_NONE (TPM_PT)(0x00000000)\r
+#define PT_GROUP (TPM_PT)(0x00000100)\r
+#define PT_FIXED (TPM_PT)(PT_GROUP * 1)\r
+#define TPM_PT_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 0)\r
+#define TPM_PT_LEVEL (TPM_PT)(PT_FIXED + 1)\r
+#define TPM_PT_REVISION (TPM_PT)(PT_FIXED + 2)\r
+#define TPM_PT_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 3)\r
+#define TPM_PT_YEAR (TPM_PT)(PT_FIXED + 4)\r
+#define TPM_PT_MANUFACTURER (TPM_PT)(PT_FIXED + 5)\r
+#define TPM_PT_VENDOR_STRING_1 (TPM_PT)(PT_FIXED + 6)\r
+#define TPM_PT_VENDOR_STRING_2 (TPM_PT)(PT_FIXED + 7)\r
+#define TPM_PT_VENDOR_STRING_3 (TPM_PT)(PT_FIXED + 8)\r
+#define TPM_PT_VENDOR_STRING_4 (TPM_PT)(PT_FIXED + 9)\r
+#define TPM_PT_VENDOR_TPM_TYPE (TPM_PT)(PT_FIXED + 10)\r
+#define TPM_PT_FIRMWARE_VERSION_1 (TPM_PT)(PT_FIXED + 11)\r
+#define TPM_PT_FIRMWARE_VERSION_2 (TPM_PT)(PT_FIXED + 12)\r
+#define TPM_PT_INPUT_BUFFER (TPM_PT)(PT_FIXED + 13)\r
+#define TPM_PT_HR_TRANSIENT_MIN (TPM_PT)(PT_FIXED + 14)\r
+#define TPM_PT_HR_PERSISTENT_MIN (TPM_PT)(PT_FIXED + 15)\r
+#define TPM_PT_HR_LOADED_MIN (TPM_PT)(PT_FIXED + 16)\r
+#define TPM_PT_ACTIVE_SESSIONS_MAX (TPM_PT)(PT_FIXED + 17)\r
+#define TPM_PT_PCR_COUNT (TPM_PT)(PT_FIXED + 18)\r
+#define TPM_PT_PCR_SELECT_MIN (TPM_PT)(PT_FIXED + 19)\r
+#define TPM_PT_CONTEXT_GAP_MAX (TPM_PT)(PT_FIXED + 20)\r
+#define TPM_PT_NV_COUNTERS_MAX (TPM_PT)(PT_FIXED + 22)\r
+#define TPM_PT_NV_INDEX_MAX (TPM_PT)(PT_FIXED + 23)\r
+#define TPM_PT_MEMORY (TPM_PT)(PT_FIXED + 24)\r
+#define TPM_PT_CLOCK_UPDATE (TPM_PT)(PT_FIXED + 25)\r
+#define TPM_PT_CONTEXT_HASH (TPM_PT)(PT_FIXED + 26)\r
+#define TPM_PT_CONTEXT_SYM (TPM_PT)(PT_FIXED + 27)\r
+#define TPM_PT_CONTEXT_SYM_SIZE (TPM_PT)(PT_FIXED + 28)\r
+#define TPM_PT_ORDERLY_COUNT (TPM_PT)(PT_FIXED + 29)\r
+#define TPM_PT_MAX_COMMAND_SIZE (TPM_PT)(PT_FIXED + 30)\r
+#define TPM_PT_MAX_RESPONSE_SIZE (TPM_PT)(PT_FIXED + 31)\r
+#define TPM_PT_MAX_DIGEST (TPM_PT)(PT_FIXED + 32)\r
+#define TPM_PT_MAX_OBJECT_CONTEXT (TPM_PT)(PT_FIXED + 33)\r
+#define TPM_PT_MAX_SESSION_CONTEXT (TPM_PT)(PT_FIXED + 34)\r
+#define TPM_PT_PS_FAMILY_INDICATOR (TPM_PT)(PT_FIXED + 35)\r
+#define TPM_PT_PS_LEVEL (TPM_PT)(PT_FIXED + 36)\r
+#define TPM_PT_PS_REVISION (TPM_PT)(PT_FIXED + 37)\r
+#define TPM_PT_PS_DAY_OF_YEAR (TPM_PT)(PT_FIXED + 38)\r
+#define TPM_PT_PS_YEAR (TPM_PT)(PT_FIXED + 39)\r
+#define TPM_PT_SPLIT_MAX (TPM_PT)(PT_FIXED + 40)\r
+#define TPM_PT_TOTAL_COMMANDS (TPM_PT)(PT_FIXED + 41)\r
+#define TPM_PT_LIBRARY_COMMANDS (TPM_PT)(PT_FIXED + 42)\r
+#define TPM_PT_VENDOR_COMMANDS (TPM_PT)(PT_FIXED + 43)\r
+#define PT_VAR (TPM_PT)(PT_GROUP * 2)\r
+#define TPM_PT_PERMANENT (TPM_PT)(PT_VAR + 0)\r
+#define TPM_PT_STARTUP_CLEAR (TPM_PT)(PT_VAR + 1)\r
+#define TPM_PT_HR_NV_INDEX (TPM_PT)(PT_VAR + 2)\r
+#define TPM_PT_HR_LOADED (TPM_PT)(PT_VAR + 3)\r
+#define TPM_PT_HR_LOADED_AVAIL (TPM_PT)(PT_VAR + 4)\r
+#define TPM_PT_HR_ACTIVE (TPM_PT)(PT_VAR + 5)\r
+#define TPM_PT_HR_ACTIVE_AVAIL (TPM_PT)(PT_VAR + 6)\r
+#define TPM_PT_HR_TRANSIENT_AVAIL (TPM_PT)(PT_VAR + 7)\r
+#define TPM_PT_HR_PERSISTENT (TPM_PT)(PT_VAR + 8)\r
+#define TPM_PT_HR_PERSISTENT_AVAIL (TPM_PT)(PT_VAR + 9)\r
+#define TPM_PT_NV_COUNTERS (TPM_PT)(PT_VAR + 10)\r
+#define TPM_PT_NV_COUNTERS_AVAIL (TPM_PT)(PT_VAR + 11)\r
+#define TPM_PT_ALGORITHM_SET (TPM_PT)(PT_VAR + 12)\r
+#define TPM_PT_LOADED_CURVES (TPM_PT)(PT_VAR + 13)\r
+#define TPM_PT_LOCKOUT_COUNTER (TPM_PT)(PT_VAR + 14)\r
+#define TPM_PT_MAX_AUTH_FAIL (TPM_PT)(PT_VAR + 15)\r
+#define TPM_PT_LOCKOUT_INTERVAL (TPM_PT)(PT_VAR + 16)\r
+#define TPM_PT_LOCKOUT_RECOVERY (TPM_PT)(PT_VAR + 17)\r
+#define TPM_PT_NV_WRITE_RECOVERY (TPM_PT)(PT_VAR + 18)\r
+#define TPM_PT_AUDIT_COUNTER_0 (TPM_PT)(PT_VAR + 19)\r
+#define TPM_PT_AUDIT_COUNTER_1 (TPM_PT)(PT_VAR + 20)\r
\r
// Table 23 - TPM_PT_PCR Constants\r
typedef UINT32 TPM_PT_PCR;\r
-#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000)\r
-#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000)\r
-#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001)\r
-#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002)\r
-#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003)\r
-#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004)\r
-#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005)\r
-#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006)\r
-#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007)\r
-#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008)\r
-#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009)\r
-#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A)\r
-#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)\r
-#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012)\r
-#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013)\r
-#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014)\r
-#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014)\r
+#define TPM_PT_PCR_FIRST (TPM_PT_PCR)(0x00000000)\r
+#define TPM_PT_PCR_SAVE (TPM_PT_PCR)(0x00000000)\r
+#define TPM_PT_PCR_EXTEND_L0 (TPM_PT_PCR)(0x00000001)\r
+#define TPM_PT_PCR_RESET_L0 (TPM_PT_PCR)(0x00000002)\r
+#define TPM_PT_PCR_EXTEND_L1 (TPM_PT_PCR)(0x00000003)\r
+#define TPM_PT_PCR_RESET_L1 (TPM_PT_PCR)(0x00000004)\r
+#define TPM_PT_PCR_EXTEND_L2 (TPM_PT_PCR)(0x00000005)\r
+#define TPM_PT_PCR_RESET_L2 (TPM_PT_PCR)(0x00000006)\r
+#define TPM_PT_PCR_EXTEND_L3 (TPM_PT_PCR)(0x00000007)\r
+#define TPM_PT_PCR_RESET_L3 (TPM_PT_PCR)(0x00000008)\r
+#define TPM_PT_PCR_EXTEND_L4 (TPM_PT_PCR)(0x00000009)\r
+#define TPM_PT_PCR_RESET_L4 (TPM_PT_PCR)(0x0000000A)\r
+#define TPM_PT_PCR_NO_INCREMENT (TPM_PT_PCR)(0x00000011)\r
+#define TPM_PT_PCR_DRTM_RESET (TPM_PT_PCR)(0x00000012)\r
+#define TPM_PT_PCR_POLICY (TPM_PT_PCR)(0x00000013)\r
+#define TPM_PT_PCR_AUTH (TPM_PT_PCR)(0x00000014)\r
+#define TPM_PT_PCR_LAST (TPM_PT_PCR)(0x00000014)\r
\r
// Table 24 - TPM_PS Constants\r
typedef UINT32 TPM_PS;\r
-#define TPM_PS_MAIN (TPM_PS)(0x00000000)\r
-#define TPM_PS_PC (TPM_PS)(0x00000001)\r
-#define TPM_PS_PDA (TPM_PS)(0x00000002)\r
-#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003)\r
-#define TPM_PS_SERVER (TPM_PS)(0x00000004)\r
-#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005)\r
-#define TPM_PS_TSS (TPM_PS)(0x00000006)\r
-#define TPM_PS_STORAGE (TPM_PS)(0x00000007)\r
-#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)\r
-#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009)\r
-#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A)\r
-#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)\r
-#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)\r
-#define TPM_PS_TNC (TPM_PS)(0x0000000D)\r
-#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E)\r
-#define TPM_PS_TC (TPM_PS)(0x0000000F)\r
+#define TPM_PS_MAIN (TPM_PS)(0x00000000)\r
+#define TPM_PS_PC (TPM_PS)(0x00000001)\r
+#define TPM_PS_PDA (TPM_PS)(0x00000002)\r
+#define TPM_PS_CELL_PHONE (TPM_PS)(0x00000003)\r
+#define TPM_PS_SERVER (TPM_PS)(0x00000004)\r
+#define TPM_PS_PERIPHERAL (TPM_PS)(0x00000005)\r
+#define TPM_PS_TSS (TPM_PS)(0x00000006)\r
+#define TPM_PS_STORAGE (TPM_PS)(0x00000007)\r
+#define TPM_PS_AUTHENTICATION (TPM_PS)(0x00000008)\r
+#define TPM_PS_EMBEDDED (TPM_PS)(0x00000009)\r
+#define TPM_PS_HARDCOPY (TPM_PS)(0x0000000A)\r
+#define TPM_PS_INFRASTRUCTURE (TPM_PS)(0x0000000B)\r
+#define TPM_PS_VIRTUALIZATION (TPM_PS)(0x0000000C)\r
+#define TPM_PS_TNC (TPM_PS)(0x0000000D)\r
+#define TPM_PS_MULTI_TENANT (TPM_PS)(0x0000000E)\r
+#define TPM_PS_TC (TPM_PS)(0x0000000F)\r
\r
// 7 Handles\r
\r
//\r
// NOTE: Comment because it has same name as TPM1.2 (value is same, so not runtime issue)\r
//\r
-//typedef UINT32 TPM_HANDLE;\r
+// typedef UINT32 TPM_HANDLE;\r
\r
// Table 26 - TPM_HT Constants\r
typedef UINT8 TPM_HT;\r
-#define TPM_HT_PCR (TPM_HT)(0x00)\r
-#define TPM_HT_NV_INDEX (TPM_HT)(0x01)\r
-#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02)\r
-#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)\r
-#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)\r
-#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)\r
-#define TPM_HT_PERMANENT (TPM_HT)(0x40)\r
-#define TPM_HT_TRANSIENT (TPM_HT)(0x80)\r
-#define TPM_HT_PERSISTENT (TPM_HT)(0x81)\r
+#define TPM_HT_PCR (TPM_HT)(0x00)\r
+#define TPM_HT_NV_INDEX (TPM_HT)(0x01)\r
+#define TPM_HT_HMAC_SESSION (TPM_HT)(0x02)\r
+#define TPM_HT_LOADED_SESSION (TPM_HT)(0x02)\r
+#define TPM_HT_POLICY_SESSION (TPM_HT)(0x03)\r
+#define TPM_HT_ACTIVE_SESSION (TPM_HT)(0x03)\r
+#define TPM_HT_PERMANENT (TPM_HT)(0x40)\r
+#define TPM_HT_TRANSIENT (TPM_HT)(0x80)\r
+#define TPM_HT_PERSISTENT (TPM_HT)(0x81)\r
\r
// Table 27 - TPM_RH Constants\r
typedef UINT32 TPM_RH;\r
-#define TPM_RH_FIRST (TPM_RH)(0x40000000)\r
-#define TPM_RH_SRK (TPM_RH)(0x40000000)\r
-#define TPM_RH_OWNER (TPM_RH)(0x40000001)\r
-#define TPM_RH_REVOKE (TPM_RH)(0x40000002)\r
-#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003)\r
-#define TPM_RH_OPERATOR (TPM_RH)(0x40000004)\r
-#define TPM_RH_ADMIN (TPM_RH)(0x40000005)\r
-#define TPM_RH_EK (TPM_RH)(0x40000006)\r
-#define TPM_RH_NULL (TPM_RH)(0x40000007)\r
-#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008)\r
-#define TPM_RS_PW (TPM_RH)(0x40000009)\r
-#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A)\r
-#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)\r
-#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C)\r
-#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)\r
-#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010)\r
-#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F)\r
-#define TPM_RH_LAST (TPM_RH)(0x4000010F)\r
+#define TPM_RH_FIRST (TPM_RH)(0x40000000)\r
+#define TPM_RH_SRK (TPM_RH)(0x40000000)\r
+#define TPM_RH_OWNER (TPM_RH)(0x40000001)\r
+#define TPM_RH_REVOKE (TPM_RH)(0x40000002)\r
+#define TPM_RH_TRANSPORT (TPM_RH)(0x40000003)\r
+#define TPM_RH_OPERATOR (TPM_RH)(0x40000004)\r
+#define TPM_RH_ADMIN (TPM_RH)(0x40000005)\r
+#define TPM_RH_EK (TPM_RH)(0x40000006)\r
+#define TPM_RH_NULL (TPM_RH)(0x40000007)\r
+#define TPM_RH_UNASSIGNED (TPM_RH)(0x40000008)\r
+#define TPM_RS_PW (TPM_RH)(0x40000009)\r
+#define TPM_RH_LOCKOUT (TPM_RH)(0x4000000A)\r
+#define TPM_RH_ENDORSEMENT (TPM_RH)(0x4000000B)\r
+#define TPM_RH_PLATFORM (TPM_RH)(0x4000000C)\r
+#define TPM_RH_PLATFORM_NV (TPM_RH)(0x4000000D)\r
+#define TPM_RH_AUTH_00 (TPM_RH)(0x40000010)\r
+#define TPM_RH_AUTH_FF (TPM_RH)(0x4000010F)\r
+#define TPM_RH_LAST (TPM_RH)(0x4000010F)\r
\r
// Table 28 - TPM_HC Constants\r
typedef TPM_HANDLE TPM_HC;\r
-#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF)\r
-#define HR_RANGE_MASK (TPM_HC)(0xFF000000)\r
-#define HR_SHIFT (TPM_HC)(24)\r
-#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)\r
-#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)\r
-#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)\r
-#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)\r
-#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)\r
-#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)\r
-#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)\r
-#define PCR_FIRST (TPM_HC)(HR_PCR + 0)\r
-#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)\r
-#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0)\r
-#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)\r
-#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)\r
-#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST)\r
-#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)\r
-#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)\r
-#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0)\r
-#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)\r
-#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST)\r
-#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)\r
-#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0)\r
-#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)\r
-#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000)\r
-#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0)\r
-#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)\r
-#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST)\r
-#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST)\r
+#define HR_HANDLE_MASK (TPM_HC)(0x00FFFFFF)\r
+#define HR_RANGE_MASK (TPM_HC)(0xFF000000)\r
+#define HR_SHIFT (TPM_HC)(24)\r
+#define HR_PCR (TPM_HC)((TPM_HC)TPM_HT_PCR << HR_SHIFT)\r
+#define HR_HMAC_SESSION (TPM_HC)((TPM_HC)TPM_HT_HMAC_SESSION << HR_SHIFT)\r
+#define HR_POLICY_SESSION (TPM_HC)((TPM_HC)TPM_HT_POLICY_SESSION << HR_SHIFT)\r
+#define HR_TRANSIENT (TPM_HC)((TPM_HC)TPM_HT_TRANSIENT << HR_SHIFT)\r
+#define HR_PERSISTENT (TPM_HC)((TPM_HC)TPM_HT_PERSISTENT << HR_SHIFT)\r
+#define HR_NV_INDEX (TPM_HC)((TPM_HC)TPM_HT_NV_INDEX << HR_SHIFT)\r
+#define HR_PERMANENT (TPM_HC)((TPM_HC)TPM_HT_PERMANENT << HR_SHIFT)\r
+#define PCR_FIRST (TPM_HC)(HR_PCR + 0)\r
+#define PCR_LAST (TPM_HC)(PCR_FIRST + IMPLEMENTATION_PCR - 1)\r
+#define HMAC_SESSION_FIRST (TPM_HC)(HR_HMAC_SESSION + 0)\r
+#define HMAC_SESSION_LAST (TPM_HC)(HMAC_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)\r
+#define LOADED_SESSION_FIRST (TPM_HC)(HMAC_SESSION_FIRST)\r
+#define LOADED_SESSION_LAST (TPM_HC)(HMAC_SESSION_LAST)\r
+#define POLICY_SESSION_FIRST (TPM_HC)(HR_POLICY_SESSION + 0)\r
+#define POLICY_SESSION_LAST (TPM_HC)(POLICY_SESSION_FIRST + MAX_ACTIVE_SESSIONS - 1)\r
+#define TRANSIENT_FIRST (TPM_HC)(HR_TRANSIENT + 0)\r
+#define ACTIVE_SESSION_FIRST (TPM_HC)(POLICY_SESSION_FIRST)\r
+#define ACTIVE_SESSION_LAST (TPM_HC)(POLICY_SESSION_LAST)\r
+#define TRANSIENT_LAST (TPM_HC)(TRANSIENT_FIRST+MAX_LOADED_OBJECTS - 1)\r
+#define PERSISTENT_FIRST (TPM_HC)(HR_PERSISTENT + 0)\r
+#define PERSISTENT_LAST (TPM_HC)(PERSISTENT_FIRST + 0x00FFFFFF)\r
+#define PLATFORM_PERSISTENT (TPM_HC)(PERSISTENT_FIRST + 0x00800000)\r
+#define NV_INDEX_FIRST (TPM_HC)(HR_NV_INDEX + 0)\r
+#define NV_INDEX_LAST (TPM_HC)(NV_INDEX_FIRST + 0x00FFFFFF)\r
+#define PERMANENT_FIRST (TPM_HC)(TPM_RH_FIRST)\r
+#define PERMANENT_LAST (TPM_HC)(TPM_RH_LAST)\r
\r
// 8 Attribute Structures\r
\r
// Table 29 - TPMA_ALGORITHM Bits\r
typedef struct {\r
- UINT32 asymmetric : 1;\r
- UINT32 symmetric : 1;\r
- UINT32 hash : 1;\r
- UINT32 object : 1;\r
- UINT32 reserved4_7 : 4;\r
- UINT32 signing : 1;\r
- UINT32 encrypting : 1;\r
- UINT32 method : 1;\r
- UINT32 reserved11_31 : 21;\r
+ UINT32 asymmetric : 1;\r
+ UINT32 symmetric : 1;\r
+ UINT32 hash : 1;\r
+ UINT32 object : 1;\r
+ UINT32 reserved4_7 : 4;\r
+ UINT32 signing : 1;\r
+ UINT32 encrypting : 1;\r
+ UINT32 method : 1;\r
+ UINT32 reserved11_31 : 21;\r
} TPMA_ALGORITHM;\r
\r
// Table 30 - TPMA_OBJECT Bits\r
typedef struct {\r
- UINT32 reserved1 : 1;\r
- UINT32 fixedTPM : 1;\r
- UINT32 stClear : 1;\r
- UINT32 reserved4 : 1;\r
- UINT32 fixedParent : 1;\r
- UINT32 sensitiveDataOrigin : 1;\r
- UINT32 userWithAuth : 1;\r
- UINT32 adminWithPolicy : 1;\r
- UINT32 reserved8_9 : 2;\r
- UINT32 noDA : 1;\r
- UINT32 encryptedDuplication : 1;\r
- UINT32 reserved12_15 : 4;\r
- UINT32 restricted : 1;\r
- UINT32 decrypt : 1;\r
- UINT32 sign : 1;\r
- UINT32 reserved19_31 : 13;\r
+ UINT32 reserved1 : 1;\r
+ UINT32 fixedTPM : 1;\r
+ UINT32 stClear : 1;\r
+ UINT32 reserved4 : 1;\r
+ UINT32 fixedParent : 1;\r
+ UINT32 sensitiveDataOrigin : 1;\r
+ UINT32 userWithAuth : 1;\r
+ UINT32 adminWithPolicy : 1;\r
+ UINT32 reserved8_9 : 2;\r
+ UINT32 noDA : 1;\r
+ UINT32 encryptedDuplication : 1;\r
+ UINT32 reserved12_15 : 4;\r
+ UINT32 restricted : 1;\r
+ UINT32 decrypt : 1;\r
+ UINT32 sign : 1;\r
+ UINT32 reserved19_31 : 13;\r
} TPMA_OBJECT;\r
\r
// Table 31 - TPMA_SESSION Bits\r
typedef struct {\r
- UINT8 continueSession : 1;\r
- UINT8 auditExclusive : 1;\r
- UINT8 auditReset : 1;\r
- UINT8 reserved3_4 : 2;\r
- UINT8 decrypt : 1;\r
- UINT8 encrypt : 1;\r
- UINT8 audit : 1;\r
+ UINT8 continueSession : 1;\r
+ UINT8 auditExclusive : 1;\r
+ UINT8 auditReset : 1;\r
+ UINT8 reserved3_4 : 2;\r
+ UINT8 decrypt : 1;\r
+ UINT8 encrypt : 1;\r
+ UINT8 audit : 1;\r
} TPMA_SESSION;\r
\r
// Table 32 - TPMA_LOCALITY Bits\r
// NOTE: Use low case here to resolve conflict\r
//\r
typedef struct {\r
- UINT8 locZero : 1;\r
- UINT8 locOne : 1;\r
- UINT8 locTwo : 1;\r
- UINT8 locThree : 1;\r
- UINT8 locFour : 1;\r
- UINT8 Extended : 3;\r
+ UINT8 locZero : 1;\r
+ UINT8 locOne : 1;\r
+ UINT8 locTwo : 1;\r
+ UINT8 locThree : 1;\r
+ UINT8 locFour : 1;\r
+ UINT8 Extended : 3;\r
} TPMA_LOCALITY;\r
\r
// Table 33 - TPMA_PERMANENT Bits\r
typedef struct {\r
- UINT32 ownerAuthSet : 1;\r
- UINT32 endorsementAuthSet : 1;\r
- UINT32 lockoutAuthSet : 1;\r
- UINT32 reserved3_7 : 5;\r
- UINT32 disableClear : 1;\r
- UINT32 inLockout : 1;\r
- UINT32 tpmGeneratedEPS : 1;\r
- UINT32 reserved11_31 : 21;\r
+ UINT32 ownerAuthSet : 1;\r
+ UINT32 endorsementAuthSet : 1;\r
+ UINT32 lockoutAuthSet : 1;\r
+ UINT32 reserved3_7 : 5;\r
+ UINT32 disableClear : 1;\r
+ UINT32 inLockout : 1;\r
+ UINT32 tpmGeneratedEPS : 1;\r
+ UINT32 reserved11_31 : 21;\r
} TPMA_PERMANENT;\r
\r
// Table 34 - TPMA_STARTUP_CLEAR Bits\r
typedef struct {\r
- UINT32 phEnable : 1;\r
- UINT32 shEnable : 1;\r
- UINT32 ehEnable : 1;\r
- UINT32 reserved3_30 : 28;\r
- UINT32 orderly : 1;\r
+ UINT32 phEnable : 1;\r
+ UINT32 shEnable : 1;\r
+ UINT32 ehEnable : 1;\r
+ UINT32 reserved3_30 : 28;\r
+ UINT32 orderly : 1;\r
} TPMA_STARTUP_CLEAR;\r
\r
// Table 35 - TPMA_MEMORY Bits\r
typedef struct {\r
- UINT32 sharedRAM : 1;\r
- UINT32 sharedNV : 1;\r
- UINT32 objectCopiedToRam : 1;\r
- UINT32 reserved3_31 : 29;\r
+ UINT32 sharedRAM : 1;\r
+ UINT32 sharedNV : 1;\r
+ UINT32 objectCopiedToRam : 1;\r
+ UINT32 reserved3_31 : 29;\r
} TPMA_MEMORY;\r
\r
// Table 36 - TPMA_CC Bits\r
typedef struct {\r
- UINT32 commandIndex : 16;\r
- UINT32 reserved16_21 : 6;\r
- UINT32 nv : 1;\r
- UINT32 extensive : 1;\r
- UINT32 flushed : 1;\r
- UINT32 cHandles : 3;\r
- UINT32 rHandle : 1;\r
- UINT32 V : 1;\r
- UINT32 Res : 2;\r
+ UINT32 commandIndex : 16;\r
+ UINT32 reserved16_21 : 6;\r
+ UINT32 nv : 1;\r
+ UINT32 extensive : 1;\r
+ UINT32 flushed : 1;\r
+ UINT32 cHandles : 3;\r
+ UINT32 rHandle : 1;\r
+ UINT32 V : 1;\r
+ UINT32 Res : 2;\r
} TPMA_CC;\r
\r
// 9 Interface Types\r
\r
// Table 65 - TPMS_ALGORITHM_DESCRIPTION Structure\r
typedef struct {\r
- TPM_ALG_ID alg;\r
- TPMA_ALGORITHM attributes;\r
+ TPM_ALG_ID alg;\r
+ TPMA_ALGORITHM attributes;\r
} TPMS_ALGORITHM_DESCRIPTION;\r
\r
// Table 66 - TPMU_HA Union\r
typedef union {\r
- BYTE sha1[SHA1_DIGEST_SIZE];\r
- BYTE sha256[SHA256_DIGEST_SIZE];\r
- BYTE sm3_256[SM3_256_DIGEST_SIZE];\r
- BYTE sha384[SHA384_DIGEST_SIZE];\r
- BYTE sha512[SHA512_DIGEST_SIZE];\r
+ BYTE sha1[SHA1_DIGEST_SIZE];\r
+ BYTE sha256[SHA256_DIGEST_SIZE];\r
+ BYTE sm3_256[SM3_256_DIGEST_SIZE];\r
+ BYTE sha384[SHA384_DIGEST_SIZE];\r
+ BYTE sha512[SHA512_DIGEST_SIZE];\r
} TPMU_HA;\r
\r
// Table 67 - TPMT_HA Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
- TPMU_HA digest;\r
+ TPMI_ALG_HASH hashAlg;\r
+ TPMU_HA digest;\r
} TPMT_HA;\r
\r
// Table 68 - TPM2B_DIGEST Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(TPMU_HA)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (TPMU_HA)];\r
} TPM2B_DIGEST;\r
\r
// Table 69 - TPM2B_DATA Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(TPMT_HA)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (TPMT_HA)];\r
} TPM2B_DATA;\r
\r
// Table 70 - TPM2B_NONCE Types\r
\r
// Table 73 - TPM2B_EVENT Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[1024];\r
+ UINT16 size;\r
+ BYTE buffer[1024];\r
} TPM2B_EVENT;\r
\r
// Table 74 - TPM2B_MAX_BUFFER Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_DIGEST_BUFFER];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_DIGEST_BUFFER];\r
} TPM2B_MAX_BUFFER;\r
\r
// Table 75 - TPM2B_MAX_NV_BUFFER Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_NV_INDEX_SIZE];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_NV_INDEX_SIZE];\r
} TPM2B_MAX_NV_BUFFER;\r
\r
// Table 76 - TPM2B_TIMEOUT Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(UINT64)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (UINT64)];\r
} TPM2B_TIMEOUT;\r
\r
// Table 77 -- TPM2B_IV Structure <I/O>\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_SYM_BLOCK_SIZE];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_SYM_BLOCK_SIZE];\r
} TPM2B_IV;\r
\r
// Table 78 - TPMU_NAME Union\r
typedef union {\r
- TPMT_HA digest;\r
- TPM_HANDLE handle;\r
+ TPMT_HA digest;\r
+ TPM_HANDLE handle;\r
} TPMU_NAME;\r
\r
// Table 79 - TPM2B_NAME Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE name[sizeof(TPMU_NAME)];\r
+ UINT16 size;\r
+ BYTE name[sizeof (TPMU_NAME)];\r
} TPM2B_NAME;\r
\r
// Table 80 - TPMS_PCR_SELECT Structure\r
typedef struct {\r
- UINT8 sizeofSelect;\r
- BYTE pcrSelect[PCR_SELECT_MAX];\r
+ UINT8 sizeofSelect;\r
+ BYTE pcrSelect[PCR_SELECT_MAX];\r
} TPMS_PCR_SELECT;\r
\r
// Table 81 - TPMS_PCR_SELECTION Structure\r
typedef struct {\r
- TPMI_ALG_HASH hash;\r
- UINT8 sizeofSelect;\r
- BYTE pcrSelect[PCR_SELECT_MAX];\r
+ TPMI_ALG_HASH hash;\r
+ UINT8 sizeofSelect;\r
+ BYTE pcrSelect[PCR_SELECT_MAX];\r
} TPMS_PCR_SELECTION;\r
\r
// Table 84 - TPMT_TK_CREATION Structure\r
typedef struct {\r
- TPM_ST tag;\r
- TPMI_RH_HIERARCHY hierarchy;\r
- TPM2B_DIGEST digest;\r
+ TPM_ST tag;\r
+ TPMI_RH_HIERARCHY hierarchy;\r
+ TPM2B_DIGEST digest;\r
} TPMT_TK_CREATION;\r
\r
// Table 85 - TPMT_TK_VERIFIED Structure\r
typedef struct {\r
- TPM_ST tag;\r
- TPMI_RH_HIERARCHY hierarchy;\r
- TPM2B_DIGEST digest;\r
+ TPM_ST tag;\r
+ TPMI_RH_HIERARCHY hierarchy;\r
+ TPM2B_DIGEST digest;\r
} TPMT_TK_VERIFIED;\r
\r
// Table 86 - TPMT_TK_AUTH Structure\r
typedef struct {\r
- TPM_ST tag;\r
- TPMI_RH_HIERARCHY hierarchy;\r
- TPM2B_DIGEST digest;\r
+ TPM_ST tag;\r
+ TPMI_RH_HIERARCHY hierarchy;\r
+ TPM2B_DIGEST digest;\r
} TPMT_TK_AUTH;\r
\r
// Table 87 - TPMT_TK_HASHCHECK Structure\r
typedef struct {\r
- TPM_ST tag;\r
- TPMI_RH_HIERARCHY hierarchy;\r
- TPM2B_DIGEST digest;\r
+ TPM_ST tag;\r
+ TPMI_RH_HIERARCHY hierarchy;\r
+ TPM2B_DIGEST digest;\r
} TPMT_TK_HASHCHECK;\r
\r
// Table 88 - TPMS_ALG_PROPERTY Structure\r
typedef struct {\r
- TPM_ALG_ID alg;\r
- TPMA_ALGORITHM algProperties;\r
+ TPM_ALG_ID alg;\r
+ TPMA_ALGORITHM algProperties;\r
} TPMS_ALG_PROPERTY;\r
\r
// Table 89 - TPMS_TAGGED_PROPERTY Structure\r
typedef struct {\r
- TPM_PT property;\r
- UINT32 value;\r
+ TPM_PT property;\r
+ UINT32 value;\r
} TPMS_TAGGED_PROPERTY;\r
\r
// Table 90 - TPMS_TAGGED_PCR_SELECT Structure\r
typedef struct {\r
- TPM_PT tag;\r
- UINT8 sizeofSelect;\r
- BYTE pcrSelect[PCR_SELECT_MAX];\r
+ TPM_PT tag;\r
+ UINT8 sizeofSelect;\r
+ BYTE pcrSelect[PCR_SELECT_MAX];\r
} TPMS_TAGGED_PCR_SELECT;\r
\r
// Table 91 - TPML_CC Structure\r
typedef struct {\r
- UINT32 count;\r
- TPM_CC commandCodes[MAX_CAP_CC];\r
+ UINT32 count;\r
+ TPM_CC commandCodes[MAX_CAP_CC];\r
} TPML_CC;\r
\r
// Table 92 - TPML_CCA Structure\r
typedef struct {\r
- UINT32 count;\r
- TPMA_CC commandAttributes[MAX_CAP_CC];\r
+ UINT32 count;\r
+ TPMA_CC commandAttributes[MAX_CAP_CC];\r
} TPML_CCA;\r
\r
// Table 93 - TPML_ALG Structure\r
typedef struct {\r
- UINT32 count;\r
- TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];\r
+ UINT32 count;\r
+ TPM_ALG_ID algorithms[MAX_ALG_LIST_SIZE];\r
} TPML_ALG;\r
\r
// Table 94 - TPML_HANDLE Structure\r
typedef struct {\r
- UINT32 count;\r
- TPM_HANDLE handle[MAX_CAP_HANDLES];\r
+ UINT32 count;\r
+ TPM_HANDLE handle[MAX_CAP_HANDLES];\r
} TPML_HANDLE;\r
\r
// Table 95 - TPML_DIGEST Structure\r
typedef struct {\r
- UINT32 count;\r
- TPM2B_DIGEST digests[8];\r
+ UINT32 count;\r
+ TPM2B_DIGEST digests[8];\r
} TPML_DIGEST;\r
\r
// Table 96 -- TPML_DIGEST_VALUES Structure <I/O>\r
typedef struct {\r
- UINT32 count;\r
- TPMT_HA digests[HASH_COUNT];\r
+ UINT32 count;\r
+ TPMT_HA digests[HASH_COUNT];\r
} TPML_DIGEST_VALUES;\r
\r
// Table 97 - TPM2B_DIGEST_VALUES Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(TPML_DIGEST_VALUES)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (TPML_DIGEST_VALUES)];\r
} TPM2B_DIGEST_VALUES;\r
\r
// Table 98 - TPML_PCR_SELECTION Structure\r
typedef struct {\r
- UINT32 count;\r
- TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];\r
+ UINT32 count;\r
+ TPMS_PCR_SELECTION pcrSelections[HASH_COUNT];\r
} TPML_PCR_SELECTION;\r
\r
// Table 99 - TPML_ALG_PROPERTY Structure\r
typedef struct {\r
- UINT32 count;\r
- TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];\r
+ UINT32 count;\r
+ TPMS_ALG_PROPERTY algProperties[MAX_CAP_ALGS];\r
} TPML_ALG_PROPERTY;\r
\r
// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure\r
typedef struct {\r
- UINT32 count;\r
- TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];\r
+ UINT32 count;\r
+ TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES];\r
} TPML_TAGGED_TPM_PROPERTY;\r
\r
// Table 101 - TPML_TAGGED_PCR_PROPERTY Structure\r
typedef struct {\r
- UINT32 count;\r
- TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];\r
+ UINT32 count;\r
+ TPMS_TAGGED_PCR_SELECT pcrProperty[MAX_PCR_PROPERTIES];\r
} TPML_TAGGED_PCR_PROPERTY;\r
\r
// Table 102 - TPML_ECC_CURVE Structure\r
typedef struct {\r
- UINT32 count;\r
- TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];\r
+ UINT32 count;\r
+ TPM_ECC_CURVE eccCurves[MAX_ECC_CURVES];\r
} TPML_ECC_CURVE;\r
\r
// Table 103 - TPMU_CAPABILITIES Union\r
typedef union {\r
- TPML_ALG_PROPERTY algorithms;\r
- TPML_HANDLE handles;\r
- TPML_CCA command;\r
- TPML_CC ppCommands;\r
- TPML_CC auditCommands;\r
- TPML_PCR_SELECTION assignedPCR;\r
- TPML_TAGGED_TPM_PROPERTY tpmProperties;\r
- TPML_TAGGED_PCR_PROPERTY pcrProperties;\r
- TPML_ECC_CURVE eccCurves;\r
+ TPML_ALG_PROPERTY algorithms;\r
+ TPML_HANDLE handles;\r
+ TPML_CCA command;\r
+ TPML_CC ppCommands;\r
+ TPML_CC auditCommands;\r
+ TPML_PCR_SELECTION assignedPCR;\r
+ TPML_TAGGED_TPM_PROPERTY tpmProperties;\r
+ TPML_TAGGED_PCR_PROPERTY pcrProperties;\r
+ TPML_ECC_CURVE eccCurves;\r
} TPMU_CAPABILITIES;\r
\r
// Table 104 - TPMS_CAPABILITY_DATA Structure\r
typedef struct {\r
- TPM_CAP capability;\r
- TPMU_CAPABILITIES data;\r
+ TPM_CAP capability;\r
+ TPMU_CAPABILITIES data;\r
} TPMS_CAPABILITY_DATA;\r
\r
// Table 105 - TPMS_CLOCK_INFO Structure\r
typedef struct {\r
- UINT64 clock;\r
- UINT32 resetCount;\r
- UINT32 restartCount;\r
- TPMI_YES_NO safe;\r
+ UINT64 clock;\r
+ UINT32 resetCount;\r
+ UINT32 restartCount;\r
+ TPMI_YES_NO safe;\r
} TPMS_CLOCK_INFO;\r
\r
// Table 106 - TPMS_TIME_INFO Structure\r
typedef struct {\r
- UINT64 time;\r
- TPMS_CLOCK_INFO clockInfo;\r
+ UINT64 time;\r
+ TPMS_CLOCK_INFO clockInfo;\r
} TPMS_TIME_INFO;\r
\r
// Table 107 - TPMS_TIME_ATTEST_INFO Structure\r
typedef struct {\r
- TPMS_TIME_INFO time;\r
- UINT64 firmwareVersion;\r
+ TPMS_TIME_INFO time;\r
+ UINT64 firmwareVersion;\r
} TPMS_TIME_ATTEST_INFO;\r
\r
// Table 108 - TPMS_CERTIFY_INFO Structure\r
typedef struct {\r
- TPM2B_NAME name;\r
- TPM2B_NAME qualifiedName;\r
+ TPM2B_NAME name;\r
+ TPM2B_NAME qualifiedName;\r
} TPMS_CERTIFY_INFO;\r
\r
// Table 109 - TPMS_QUOTE_INFO Structure\r
typedef struct {\r
- TPML_PCR_SELECTION pcrSelect;\r
- TPM2B_DIGEST pcrDigest;\r
+ TPML_PCR_SELECTION pcrSelect;\r
+ TPM2B_DIGEST pcrDigest;\r
} TPMS_QUOTE_INFO;\r
\r
// Table 110 - TPMS_COMMAND_AUDIT_INFO Structure\r
typedef struct {\r
- UINT64 auditCounter;\r
- TPM_ALG_ID digestAlg;\r
- TPM2B_DIGEST auditDigest;\r
- TPM2B_DIGEST commandDigest;\r
+ UINT64 auditCounter;\r
+ TPM_ALG_ID digestAlg;\r
+ TPM2B_DIGEST auditDigest;\r
+ TPM2B_DIGEST commandDigest;\r
} TPMS_COMMAND_AUDIT_INFO;\r
\r
// Table 111 - TPMS_SESSION_AUDIT_INFO Structure\r
typedef struct {\r
- TPMI_YES_NO exclusiveSession;\r
- TPM2B_DIGEST sessionDigest;\r
+ TPMI_YES_NO exclusiveSession;\r
+ TPM2B_DIGEST sessionDigest;\r
} TPMS_SESSION_AUDIT_INFO;\r
\r
// Table 112 - TPMS_CREATION_INFO Structure\r
typedef struct {\r
- TPM2B_NAME objectName;\r
- TPM2B_DIGEST creationHash;\r
+ TPM2B_NAME objectName;\r
+ TPM2B_DIGEST creationHash;\r
} TPMS_CREATION_INFO;\r
\r
// Table 113 - TPMS_NV_CERTIFY_INFO Structure\r
typedef struct {\r
- TPM2B_NAME indexName;\r
- UINT16 offset;\r
- TPM2B_MAX_NV_BUFFER nvContents;\r
+ TPM2B_NAME indexName;\r
+ UINT16 offset;\r
+ TPM2B_MAX_NV_BUFFER nvContents;\r
} TPMS_NV_CERTIFY_INFO;\r
\r
// Table 114 - TPMI_ST_ATTEST Type\r
\r
// Table 115 - TPMU_ATTEST Union\r
typedef union {\r
- TPMS_CERTIFY_INFO certify;\r
- TPMS_CREATION_INFO creation;\r
- TPMS_QUOTE_INFO quote;\r
- TPMS_COMMAND_AUDIT_INFO commandAudit;\r
- TPMS_SESSION_AUDIT_INFO sessionAudit;\r
- TPMS_TIME_ATTEST_INFO time;\r
- TPMS_NV_CERTIFY_INFO nv;\r
+ TPMS_CERTIFY_INFO certify;\r
+ TPMS_CREATION_INFO creation;\r
+ TPMS_QUOTE_INFO quote;\r
+ TPMS_COMMAND_AUDIT_INFO commandAudit;\r
+ TPMS_SESSION_AUDIT_INFO sessionAudit;\r
+ TPMS_TIME_ATTEST_INFO time;\r
+ TPMS_NV_CERTIFY_INFO nv;\r
} TPMU_ATTEST;\r
\r
// Table 116 - TPMS_ATTEST Structure\r
typedef struct {\r
- TPM_GENERATED magic;\r
- TPMI_ST_ATTEST type;\r
- TPM2B_NAME qualifiedSigner;\r
- TPM2B_DATA extraData;\r
- TPMS_CLOCK_INFO clockInfo;\r
- UINT64 firmwareVersion;\r
- TPMU_ATTEST attested;\r
+ TPM_GENERATED magic;\r
+ TPMI_ST_ATTEST type;\r
+ TPM2B_NAME qualifiedSigner;\r
+ TPM2B_DATA extraData;\r
+ TPMS_CLOCK_INFO clockInfo;\r
+ UINT64 firmwareVersion;\r
+ TPMU_ATTEST attested;\r
} TPMS_ATTEST;\r
\r
// Table 117 - TPM2B_ATTEST Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE attestationData[sizeof(TPMS_ATTEST)];\r
+ UINT16 size;\r
+ BYTE attestationData[sizeof (TPMS_ATTEST)];\r
} TPM2B_ATTEST;\r
\r
// Table 118 - TPMS_AUTH_COMMAND Structure\r
typedef struct {\r
- TPMI_SH_AUTH_SESSION sessionHandle;\r
- TPM2B_NONCE nonce;\r
- TPMA_SESSION sessionAttributes;\r
- TPM2B_AUTH hmac;\r
+ TPMI_SH_AUTH_SESSION sessionHandle;\r
+ TPM2B_NONCE nonce;\r
+ TPMA_SESSION sessionAttributes;\r
+ TPM2B_AUTH hmac;\r
} TPMS_AUTH_COMMAND;\r
\r
// Table 119 - TPMS_AUTH_RESPONSE Structure\r
typedef struct {\r
- TPM2B_NONCE nonce;\r
- TPMA_SESSION sessionAttributes;\r
- TPM2B_AUTH hmac;\r
+ TPM2B_NONCE nonce;\r
+ TPMA_SESSION sessionAttributes;\r
+ TPM2B_AUTH hmac;\r
} TPMS_AUTH_RESPONSE;\r
\r
// 11 Algorithm Parameters and Structures\r
\r
// Table 122 - TPMU_SYM_KEY_BITS Union\r
typedef union {\r
- TPMI_AES_KEY_BITS aes;\r
- TPMI_SM4_KEY_BITS SM4;\r
- TPM_KEY_BITS sym;\r
+ TPMI_AES_KEY_BITS aes;\r
+ TPMI_SM4_KEY_BITS SM4;\r
+ TPM_KEY_BITS sym;\r
TPMI_ALG_HASH xor;\r
} TPMU_SYM_KEY_BITS;\r
\r
// Table 123 - TPMU_SYM_MODE Union\r
typedef union {\r
- TPMI_ALG_SYM_MODE aes;\r
- TPMI_ALG_SYM_MODE SM4;\r
- TPMI_ALG_SYM_MODE sym;\r
+ TPMI_ALG_SYM_MODE aes;\r
+ TPMI_ALG_SYM_MODE SM4;\r
+ TPMI_ALG_SYM_MODE sym;\r
} TPMU_SYM_MODE;\r
\r
// Table 125 - TPMT_SYM_DEF Structure\r
typedef struct {\r
- TPMI_ALG_SYM algorithm;\r
- TPMU_SYM_KEY_BITS keyBits;\r
- TPMU_SYM_MODE mode;\r
+ TPMI_ALG_SYM algorithm;\r
+ TPMU_SYM_KEY_BITS keyBits;\r
+ TPMU_SYM_MODE mode;\r
} TPMT_SYM_DEF;\r
\r
// Table 126 - TPMT_SYM_DEF_OBJECT Structure\r
typedef struct {\r
- TPMI_ALG_SYM_OBJECT algorithm;\r
- TPMU_SYM_KEY_BITS keyBits;\r
- TPMU_SYM_MODE mode;\r
+ TPMI_ALG_SYM_OBJECT algorithm;\r
+ TPMU_SYM_KEY_BITS keyBits;\r
+ TPMU_SYM_MODE mode;\r
} TPMT_SYM_DEF_OBJECT;\r
\r
// Table 127 - TPM2B_SYM_KEY Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_SYM_KEY_BYTES];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_SYM_KEY_BYTES];\r
} TPM2B_SYM_KEY;\r
\r
// Table 128 - TPMS_SYMCIPHER_PARMS Structure\r
typedef struct {\r
- TPMT_SYM_DEF_OBJECT sym;\r
+ TPMT_SYM_DEF_OBJECT sym;\r
} TPMS_SYMCIPHER_PARMS;\r
\r
// Table 129 - TPM2B_SENSITIVE_DATA Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_SYM_DATA];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_SYM_DATA];\r
} TPM2B_SENSITIVE_DATA;\r
\r
// Table 130 - TPMS_SENSITIVE_CREATE Structure\r
typedef struct {\r
- TPM2B_AUTH userAuth;\r
- TPM2B_SENSITIVE_DATA data;\r
+ TPM2B_AUTH userAuth;\r
+ TPM2B_SENSITIVE_DATA data;\r
} TPMS_SENSITIVE_CREATE;\r
\r
// Table 131 - TPM2B_SENSITIVE_CREATE Structure\r
typedef struct {\r
- UINT16 size;\r
- TPMS_SENSITIVE_CREATE sensitive;\r
+ UINT16 size;\r
+ TPMS_SENSITIVE_CREATE sensitive;\r
} TPM2B_SENSITIVE_CREATE;\r
\r
// Table 132 - TPMS_SCHEME_SIGHASH Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_SIGHASH;\r
\r
// Table 133 - TPMI_ALG_KEYEDHASH_SCHEME Type\r
\r
// Table 135 - TPMS_SCHEME_XOR Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
- TPMI_ALG_KDF kdf;\r
+ TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_KDF kdf;\r
} TPMS_SCHEME_XOR;\r
\r
// Table 136 - TPMU_SCHEME_KEYEDHASH Union\r
typedef union {\r
- TPMS_SCHEME_HMAC hmac;\r
+ TPMS_SCHEME_HMAC hmac;\r
TPMS_SCHEME_XOR xor;\r
} TPMU_SCHEME_KEYEDHASH;\r
\r
// Table 137 - TPMT_KEYEDHASH_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_KEYEDHASH_SCHEME scheme;\r
- TPMU_SCHEME_KEYEDHASH details;\r
+ TPMI_ALG_KEYEDHASH_SCHEME scheme;\r
+ TPMU_SCHEME_KEYEDHASH details;\r
} TPMT_KEYEDHASH_SCHEME;\r
\r
// Table 138 - RSA_SIG_SCHEMES Types\r
\r
// Table 140 - TPMS_SCHEME_ECDAA Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
- UINT16 count;\r
+ TPMI_ALG_HASH hashAlg;\r
+ UINT16 count;\r
} TPMS_SCHEME_ECDAA;\r
\r
// Table 141 - TPMU_SIG_SCHEME Union\r
typedef union {\r
- TPMS_SCHEME_RSASSA rsassa;\r
- TPMS_SCHEME_RSAPSS rsapss;\r
- TPMS_SCHEME_ECDSA ecdsa;\r
- TPMS_SCHEME_ECDAA ecdaa;\r
- TPMS_SCHEME_ECSCHNORR ecSchnorr;\r
- TPMS_SCHEME_HMAC hmac;\r
- TPMS_SCHEME_SIGHASH any;\r
+ TPMS_SCHEME_RSASSA rsassa;\r
+ TPMS_SCHEME_RSAPSS rsapss;\r
+ TPMS_SCHEME_ECDSA ecdsa;\r
+ TPMS_SCHEME_ECDAA ecdaa;\r
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;\r
+ TPMS_SCHEME_HMAC hmac;\r
+ TPMS_SCHEME_SIGHASH any;\r
} TPMU_SIG_SCHEME;\r
\r
// Table 142 - TPMT_SIG_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_SIG_SCHEME scheme;\r
- TPMU_SIG_SCHEME details;\r
+ TPMI_ALG_SIG_SCHEME scheme;\r
+ TPMU_SIG_SCHEME details;\r
} TPMT_SIG_SCHEME;\r
\r
// Table 143 - TPMS_SCHEME_OAEP Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_OAEP;\r
\r
// Table 144 - TPMS_SCHEME_ECDH Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_ECDH;\r
\r
// Table 145 - TPMS_SCHEME_MGF1 Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_MGF1;\r
\r
// Table 146 - TPMS_SCHEME_KDF1_SP800_56a Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_KDF1_SP800_56a;\r
\r
// Table 147 - TPMS_SCHEME_KDF2 Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_KDF2;\r
\r
// Table 148 - TPMS_SCHEME_KDF1_SP800_108 Structure\r
typedef struct {\r
- TPMI_ALG_HASH hashAlg;\r
+ TPMI_ALG_HASH hashAlg;\r
} TPMS_SCHEME_KDF1_SP800_108;\r
\r
// Table 149 - TPMU_KDF_SCHEME Union\r
typedef union {\r
- TPMS_SCHEME_MGF1 mgf1;\r
- TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;\r
- TPMS_SCHEME_KDF2 kdf2;\r
- TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;\r
+ TPMS_SCHEME_MGF1 mgf1;\r
+ TPMS_SCHEME_KDF1_SP800_56a kdf1_SP800_56a;\r
+ TPMS_SCHEME_KDF2 kdf2;\r
+ TPMS_SCHEME_KDF1_SP800_108 kdf1_sp800_108;\r
} TPMU_KDF_SCHEME;\r
\r
// Table 150 - TPMT_KDF_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_KDF scheme;\r
- TPMU_KDF_SCHEME details;\r
+ TPMI_ALG_KDF scheme;\r
+ TPMU_KDF_SCHEME details;\r
} TPMT_KDF_SCHEME;\r
\r
// Table 151 - TPMI_ALG_ASYM_SCHEME Type\r
\r
// Table 152 - TPMU_ASYM_SCHEME Union\r
typedef union {\r
- TPMS_SCHEME_RSASSA rsassa;\r
- TPMS_SCHEME_RSAPSS rsapss;\r
- TPMS_SCHEME_OAEP oaep;\r
- TPMS_SCHEME_ECDSA ecdsa;\r
- TPMS_SCHEME_ECDAA ecdaa;\r
- TPMS_SCHEME_ECSCHNORR ecSchnorr;\r
- TPMS_SCHEME_SIGHASH anySig;\r
+ TPMS_SCHEME_RSASSA rsassa;\r
+ TPMS_SCHEME_RSAPSS rsapss;\r
+ TPMS_SCHEME_OAEP oaep;\r
+ TPMS_SCHEME_ECDSA ecdsa;\r
+ TPMS_SCHEME_ECDAA ecdaa;\r
+ TPMS_SCHEME_ECSCHNORR ecSchnorr;\r
+ TPMS_SCHEME_SIGHASH anySig;\r
} TPMU_ASYM_SCHEME;\r
\r
// Table 153 - TPMT_ASYM_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_ASYM_SCHEME scheme;\r
- TPMU_ASYM_SCHEME details;\r
+ TPMI_ALG_ASYM_SCHEME scheme;\r
+ TPMU_ASYM_SCHEME details;\r
} TPMT_ASYM_SCHEME;\r
\r
// Table 154 - TPMI_ALG_RSA_SCHEME Type\r
\r
// Table 155 - TPMT_RSA_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_RSA_SCHEME scheme;\r
- TPMU_ASYM_SCHEME details;\r
+ TPMI_ALG_RSA_SCHEME scheme;\r
+ TPMU_ASYM_SCHEME details;\r
} TPMT_RSA_SCHEME;\r
\r
// Table 156 - TPMI_ALG_RSA_DECRYPT Type\r
\r
// Table 157 - TPMT_RSA_DECRYPT Structure\r
typedef struct {\r
- TPMI_ALG_RSA_DECRYPT scheme;\r
- TPMU_ASYM_SCHEME details;\r
+ TPMI_ALG_RSA_DECRYPT scheme;\r
+ TPMU_ASYM_SCHEME details;\r
} TPMT_RSA_DECRYPT;\r
\r
// Table 158 - TPM2B_PUBLIC_KEY_RSA Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_RSA_KEY_BYTES];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_RSA_KEY_BYTES];\r
} TPM2B_PUBLIC_KEY_RSA;\r
\r
// Table 159 - TPMI_RSA_KEY_BITS Type\r
\r
// Table 160 - TPM2B_PRIVATE_KEY_RSA Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_RSA_KEY_BYTES/2];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_RSA_KEY_BYTES/2];\r
} TPM2B_PRIVATE_KEY_RSA;\r
\r
// Table 161 - TPM2B_ECC_PARAMETER Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_ECC_KEY_BYTES];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_ECC_KEY_BYTES];\r
} TPM2B_ECC_PARAMETER;\r
\r
// Table 162 - TPMS_ECC_POINT Structure\r
typedef struct {\r
- TPM2B_ECC_PARAMETER x;\r
- TPM2B_ECC_PARAMETER y;\r
+ TPM2B_ECC_PARAMETER x;\r
+ TPM2B_ECC_PARAMETER y;\r
} TPMS_ECC_POINT;\r
\r
// Table 163 -- TPM2B_ECC_POINT Structure <I/O>\r
typedef struct {\r
- UINT16 size;\r
- TPMS_ECC_POINT point;\r
+ UINT16 size;\r
+ TPMS_ECC_POINT point;\r
} TPM2B_ECC_POINT;\r
\r
// Table 164 - TPMI_ALG_ECC_SCHEME Type\r
\r
// Table 166 - TPMT_ECC_SCHEME Structure\r
typedef struct {\r
- TPMI_ALG_ECC_SCHEME scheme;\r
- TPMU_SIG_SCHEME details;\r
+ TPMI_ALG_ECC_SCHEME scheme;\r
+ TPMU_SIG_SCHEME details;\r
} TPMT_ECC_SCHEME;\r
\r
// Table 167 - TPMS_ALGORITHM_DETAIL_ECC Structure\r
typedef struct {\r
- TPM_ECC_CURVE curveID;\r
- UINT16 keySize;\r
- TPMT_KDF_SCHEME kdf;\r
- TPMT_ECC_SCHEME sign;\r
- TPM2B_ECC_PARAMETER p;\r
- TPM2B_ECC_PARAMETER a;\r
- TPM2B_ECC_PARAMETER b;\r
- TPM2B_ECC_PARAMETER gX;\r
- TPM2B_ECC_PARAMETER gY;\r
- TPM2B_ECC_PARAMETER n;\r
- TPM2B_ECC_PARAMETER h;\r
+ TPM_ECC_CURVE curveID;\r
+ UINT16 keySize;\r
+ TPMT_KDF_SCHEME kdf;\r
+ TPMT_ECC_SCHEME sign;\r
+ TPM2B_ECC_PARAMETER p;\r
+ TPM2B_ECC_PARAMETER a;\r
+ TPM2B_ECC_PARAMETER b;\r
+ TPM2B_ECC_PARAMETER gX;\r
+ TPM2B_ECC_PARAMETER gY;\r
+ TPM2B_ECC_PARAMETER n;\r
+ TPM2B_ECC_PARAMETER h;\r
} TPMS_ALGORITHM_DETAIL_ECC;\r
\r
// Table 168 - TPMS_SIGNATURE_RSASSA Structure\r
typedef struct {\r
- TPMI_ALG_HASH hash;\r
- TPM2B_PUBLIC_KEY_RSA sig;\r
+ TPMI_ALG_HASH hash;\r
+ TPM2B_PUBLIC_KEY_RSA sig;\r
} TPMS_SIGNATURE_RSASSA;\r
\r
// Table 169 - TPMS_SIGNATURE_RSAPSS Structure\r
typedef struct {\r
- TPMI_ALG_HASH hash;\r
- TPM2B_PUBLIC_KEY_RSA sig;\r
+ TPMI_ALG_HASH hash;\r
+ TPM2B_PUBLIC_KEY_RSA sig;\r
} TPMS_SIGNATURE_RSAPSS;\r
\r
// Table 170 - TPMS_SIGNATURE_ECDSA Structure\r
typedef struct {\r
- TPMI_ALG_HASH hash;\r
- TPM2B_ECC_PARAMETER signatureR;\r
- TPM2B_ECC_PARAMETER signatureS;\r
+ TPMI_ALG_HASH hash;\r
+ TPM2B_ECC_PARAMETER signatureR;\r
+ TPM2B_ECC_PARAMETER signatureS;\r
} TPMS_SIGNATURE_ECDSA;\r
\r
// Table 171 - TPMU_SIGNATURE Union\r
typedef union {\r
- TPMS_SIGNATURE_RSASSA rsassa;\r
- TPMS_SIGNATURE_RSAPSS rsapss;\r
- TPMS_SIGNATURE_ECDSA ecdsa;\r
- TPMS_SIGNATURE_ECDSA sm2;\r
- TPMS_SIGNATURE_ECDSA ecdaa;\r
- TPMS_SIGNATURE_ECDSA ecschnorr;\r
- TPMT_HA hmac;\r
- TPMS_SCHEME_SIGHASH any;\r
+ TPMS_SIGNATURE_RSASSA rsassa;\r
+ TPMS_SIGNATURE_RSAPSS rsapss;\r
+ TPMS_SIGNATURE_ECDSA ecdsa;\r
+ TPMS_SIGNATURE_ECDSA sm2;\r
+ TPMS_SIGNATURE_ECDSA ecdaa;\r
+ TPMS_SIGNATURE_ECDSA ecschnorr;\r
+ TPMT_HA hmac;\r
+ TPMS_SCHEME_SIGHASH any;\r
} TPMU_SIGNATURE;\r
\r
// Table 172 - TPMT_SIGNATURE Structure\r
typedef struct {\r
- TPMI_ALG_SIG_SCHEME sigAlg;\r
- TPMU_SIGNATURE signature;\r
+ TPMI_ALG_SIG_SCHEME sigAlg;\r
+ TPMU_SIGNATURE signature;\r
} TPMT_SIGNATURE;\r
\r
// Table 173 - TPMU_ENCRYPTED_SECRET Union\r
typedef union {\r
- BYTE ecc[sizeof(TPMS_ECC_POINT)];\r
- BYTE rsa[MAX_RSA_KEY_BYTES];\r
- BYTE symmetric[sizeof(TPM2B_DIGEST)];\r
- BYTE keyedHash[sizeof(TPM2B_DIGEST)];\r
+ BYTE ecc[sizeof (TPMS_ECC_POINT)];\r
+ BYTE rsa[MAX_RSA_KEY_BYTES];\r
+ BYTE symmetric[sizeof (TPM2B_DIGEST)];\r
+ BYTE keyedHash[sizeof (TPM2B_DIGEST)];\r
} TPMU_ENCRYPTED_SECRET;\r
\r
// Table 174 - TPM2B_ENCRYPTED_SECRET Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE secret[sizeof(TPMU_ENCRYPTED_SECRET)];\r
+ UINT16 size;\r
+ BYTE secret[sizeof (TPMU_ENCRYPTED_SECRET)];\r
} TPM2B_ENCRYPTED_SECRET;\r
\r
// 12 Key/Object Complex\r
\r
// Table 176 - TPMU_PUBLIC_ID Union\r
typedef union {\r
- TPM2B_DIGEST keyedHash;\r
- TPM2B_DIGEST sym;\r
- TPM2B_PUBLIC_KEY_RSA rsa;\r
- TPMS_ECC_POINT ecc;\r
+ TPM2B_DIGEST keyedHash;\r
+ TPM2B_DIGEST sym;\r
+ TPM2B_PUBLIC_KEY_RSA rsa;\r
+ TPMS_ECC_POINT ecc;\r
} TPMU_PUBLIC_ID;\r
\r
// Table 177 - TPMS_KEYEDHASH_PARMS Structure\r
typedef struct {\r
- TPMT_KEYEDHASH_SCHEME scheme;\r
+ TPMT_KEYEDHASH_SCHEME scheme;\r
} TPMS_KEYEDHASH_PARMS;\r
\r
// Table 178 - TPMS_ASYM_PARMS Structure\r
typedef struct {\r
- TPMT_SYM_DEF_OBJECT symmetric;\r
- TPMT_ASYM_SCHEME scheme;\r
+ TPMT_SYM_DEF_OBJECT symmetric;\r
+ TPMT_ASYM_SCHEME scheme;\r
} TPMS_ASYM_PARMS;\r
\r
// Table 179 - TPMS_RSA_PARMS Structure\r
typedef struct {\r
- TPMT_SYM_DEF_OBJECT symmetric;\r
- TPMT_RSA_SCHEME scheme;\r
- TPMI_RSA_KEY_BITS keyBits;\r
- UINT32 exponent;\r
+ TPMT_SYM_DEF_OBJECT symmetric;\r
+ TPMT_RSA_SCHEME scheme;\r
+ TPMI_RSA_KEY_BITS keyBits;\r
+ UINT32 exponent;\r
} TPMS_RSA_PARMS;\r
\r
// Table 180 - TPMS_ECC_PARMS Structure\r
typedef struct {\r
- TPMT_SYM_DEF_OBJECT symmetric;\r
- TPMT_ECC_SCHEME scheme;\r
- TPMI_ECC_CURVE curveID;\r
- TPMT_KDF_SCHEME kdf;\r
+ TPMT_SYM_DEF_OBJECT symmetric;\r
+ TPMT_ECC_SCHEME scheme;\r
+ TPMI_ECC_CURVE curveID;\r
+ TPMT_KDF_SCHEME kdf;\r
} TPMS_ECC_PARMS;\r
\r
// Table 181 - TPMU_PUBLIC_PARMS Union\r
typedef union {\r
- TPMS_KEYEDHASH_PARMS keyedHashDetail;\r
- TPMT_SYM_DEF_OBJECT symDetail;\r
- TPMS_RSA_PARMS rsaDetail;\r
- TPMS_ECC_PARMS eccDetail;\r
- TPMS_ASYM_PARMS asymDetail;\r
+ TPMS_KEYEDHASH_PARMS keyedHashDetail;\r
+ TPMT_SYM_DEF_OBJECT symDetail;\r
+ TPMS_RSA_PARMS rsaDetail;\r
+ TPMS_ECC_PARMS eccDetail;\r
+ TPMS_ASYM_PARMS asymDetail;\r
} TPMU_PUBLIC_PARMS;\r
\r
// Table 182 - TPMT_PUBLIC_PARMS Structure\r
typedef struct {\r
- TPMI_ALG_PUBLIC type;\r
- TPMU_PUBLIC_PARMS parameters;\r
+ TPMI_ALG_PUBLIC type;\r
+ TPMU_PUBLIC_PARMS parameters;\r
} TPMT_PUBLIC_PARMS;\r
\r
// Table 183 - TPMT_PUBLIC Structure\r
typedef struct {\r
- TPMI_ALG_PUBLIC type;\r
- TPMI_ALG_HASH nameAlg;\r
- TPMA_OBJECT objectAttributes;\r
- TPM2B_DIGEST authPolicy;\r
- TPMU_PUBLIC_PARMS parameters;\r
- TPMU_PUBLIC_ID unique;\r
+ TPMI_ALG_PUBLIC type;\r
+ TPMI_ALG_HASH nameAlg;\r
+ TPMA_OBJECT objectAttributes;\r
+ TPM2B_DIGEST authPolicy;\r
+ TPMU_PUBLIC_PARMS parameters;\r
+ TPMU_PUBLIC_ID unique;\r
} TPMT_PUBLIC;\r
\r
// Table 184 - TPM2B_PUBLIC Structure\r
typedef struct {\r
- UINT16 size;\r
- TPMT_PUBLIC publicArea;\r
+ UINT16 size;\r
+ TPMT_PUBLIC publicArea;\r
} TPM2B_PUBLIC;\r
\r
// Table 185 - TPM2B_PRIVATE_VENDOR_SPECIFIC Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];\r
+ UINT16 size;\r
+ BYTE buffer[PRIVATE_VENDOR_SPECIFIC_BYTES];\r
} TPM2B_PRIVATE_VENDOR_SPECIFIC;\r
\r
// Table 186 - TPMU_SENSITIVE_COMPOSITE Union\r
typedef union {\r
- TPM2B_PRIVATE_KEY_RSA rsa;\r
- TPM2B_ECC_PARAMETER ecc;\r
- TPM2B_SENSITIVE_DATA bits;\r
- TPM2B_SYM_KEY sym;\r
- TPM2B_PRIVATE_VENDOR_SPECIFIC any;\r
+ TPM2B_PRIVATE_KEY_RSA rsa;\r
+ TPM2B_ECC_PARAMETER ecc;\r
+ TPM2B_SENSITIVE_DATA bits;\r
+ TPM2B_SYM_KEY sym;\r
+ TPM2B_PRIVATE_VENDOR_SPECIFIC any;\r
} TPMU_SENSITIVE_COMPOSITE;\r
\r
// Table 187 - TPMT_SENSITIVE Structure\r
typedef struct {\r
- TPMI_ALG_PUBLIC sensitiveType;\r
- TPM2B_AUTH authValue;\r
- TPM2B_DIGEST seedValue;\r
- TPMU_SENSITIVE_COMPOSITE sensitive;\r
+ TPMI_ALG_PUBLIC sensitiveType;\r
+ TPM2B_AUTH authValue;\r
+ TPM2B_DIGEST seedValue;\r
+ TPMU_SENSITIVE_COMPOSITE sensitive;\r
} TPMT_SENSITIVE;\r
\r
// Table 188 - TPM2B_SENSITIVE Structure\r
typedef struct {\r
- UINT16 size;\r
- TPMT_SENSITIVE sensitiveArea;\r
+ UINT16 size;\r
+ TPMT_SENSITIVE sensitiveArea;\r
} TPM2B_SENSITIVE;\r
\r
// Table 189 - _PRIVATE Structure\r
typedef struct {\r
- TPM2B_DIGEST integrityOuter;\r
- TPM2B_DIGEST integrityInner;\r
- TPMT_SENSITIVE sensitive;\r
+ TPM2B_DIGEST integrityOuter;\r
+ TPM2B_DIGEST integrityInner;\r
+ TPMT_SENSITIVE sensitive;\r
} _PRIVATE;\r
\r
// Table 190 - TPM2B_PRIVATE Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(_PRIVATE)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (_PRIVATE)];\r
} TPM2B_PRIVATE;\r
\r
// Table 191 - _ID_OBJECT Structure\r
typedef struct {\r
- TPM2B_DIGEST integrityHMAC;\r
- TPM2B_DIGEST encIdentity;\r
+ TPM2B_DIGEST integrityHMAC;\r
+ TPM2B_DIGEST encIdentity;\r
} _ID_OBJECT;\r
\r
// Table 192 - TPM2B_ID_OBJECT Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE credential[sizeof(_ID_OBJECT)];\r
+ UINT16 size;\r
+ BYTE credential[sizeof (_ID_OBJECT)];\r
} TPM2B_ID_OBJECT;\r
\r
// 13 NV Storage Structures\r
//\r
// NOTE: Comment here to resolve conflict\r
//\r
-//typedef struct {\r
+// typedef struct {\r
// UINT32 index : 22;\r
// UINT32 space : 2;\r
// UINT32 RH_NV : 8;\r
-//} TPM_NV_INDEX;\r
+// } TPM_NV_INDEX;\r
\r
// Table 195 - TPMA_NV Bits\r
typedef struct {\r
- UINT32 TPMA_NV_PPWRITE : 1;\r
- UINT32 TPMA_NV_OWNERWRITE : 1;\r
- UINT32 TPMA_NV_AUTHWRITE : 1;\r
- UINT32 TPMA_NV_POLICYWRITE : 1;\r
- UINT32 TPMA_NV_COUNTER : 1;\r
- UINT32 TPMA_NV_BITS : 1;\r
- UINT32 TPMA_NV_EXTEND : 1;\r
- UINT32 reserved7_9 : 3;\r
- UINT32 TPMA_NV_POLICY_DELETE : 1;\r
- UINT32 TPMA_NV_WRITELOCKED : 1;\r
- UINT32 TPMA_NV_WRITEALL : 1;\r
- UINT32 TPMA_NV_WRITEDEFINE : 1;\r
- UINT32 TPMA_NV_WRITE_STCLEAR : 1;\r
- UINT32 TPMA_NV_GLOBALLOCK : 1;\r
- UINT32 TPMA_NV_PPREAD : 1;\r
- UINT32 TPMA_NV_OWNERREAD : 1;\r
- UINT32 TPMA_NV_AUTHREAD : 1;\r
- UINT32 TPMA_NV_POLICYREAD : 1;\r
- UINT32 reserved20_24 : 5;\r
- UINT32 TPMA_NV_NO_DA : 1;\r
- UINT32 TPMA_NV_ORDERLY : 1;\r
- UINT32 TPMA_NV_CLEAR_STCLEAR : 1;\r
- UINT32 TPMA_NV_READLOCKED : 1;\r
- UINT32 TPMA_NV_WRITTEN : 1;\r
- UINT32 TPMA_NV_PLATFORMCREATE : 1;\r
- UINT32 TPMA_NV_READ_STCLEAR : 1;\r
+ UINT32 TPMA_NV_PPWRITE : 1;\r
+ UINT32 TPMA_NV_OWNERWRITE : 1;\r
+ UINT32 TPMA_NV_AUTHWRITE : 1;\r
+ UINT32 TPMA_NV_POLICYWRITE : 1;\r
+ UINT32 TPMA_NV_COUNTER : 1;\r
+ UINT32 TPMA_NV_BITS : 1;\r
+ UINT32 TPMA_NV_EXTEND : 1;\r
+ UINT32 reserved7_9 : 3;\r
+ UINT32 TPMA_NV_POLICY_DELETE : 1;\r
+ UINT32 TPMA_NV_WRITELOCKED : 1;\r
+ UINT32 TPMA_NV_WRITEALL : 1;\r
+ UINT32 TPMA_NV_WRITEDEFINE : 1;\r
+ UINT32 TPMA_NV_WRITE_STCLEAR : 1;\r
+ UINT32 TPMA_NV_GLOBALLOCK : 1;\r
+ UINT32 TPMA_NV_PPREAD : 1;\r
+ UINT32 TPMA_NV_OWNERREAD : 1;\r
+ UINT32 TPMA_NV_AUTHREAD : 1;\r
+ UINT32 TPMA_NV_POLICYREAD : 1;\r
+ UINT32 reserved20_24 : 5;\r
+ UINT32 TPMA_NV_NO_DA : 1;\r
+ UINT32 TPMA_NV_ORDERLY : 1;\r
+ UINT32 TPMA_NV_CLEAR_STCLEAR : 1;\r
+ UINT32 TPMA_NV_READLOCKED : 1;\r
+ UINT32 TPMA_NV_WRITTEN : 1;\r
+ UINT32 TPMA_NV_PLATFORMCREATE : 1;\r
+ UINT32 TPMA_NV_READ_STCLEAR : 1;\r
} TPMA_NV;\r
\r
// Table 196 - TPMS_NV_PUBLIC Structure\r
typedef struct {\r
- TPMI_RH_NV_INDEX nvIndex;\r
- TPMI_ALG_HASH nameAlg;\r
- TPMA_NV attributes;\r
- TPM2B_DIGEST authPolicy;\r
- UINT16 dataSize;\r
+ TPMI_RH_NV_INDEX nvIndex;\r
+ TPMI_ALG_HASH nameAlg;\r
+ TPMA_NV attributes;\r
+ TPM2B_DIGEST authPolicy;\r
+ UINT16 dataSize;\r
} TPMS_NV_PUBLIC;\r
\r
// Table 197 - TPM2B_NV_PUBLIC Structure\r
typedef struct {\r
- UINT16 size;\r
- TPMS_NV_PUBLIC nvPublic;\r
+ UINT16 size;\r
+ TPMS_NV_PUBLIC nvPublic;\r
} TPM2B_NV_PUBLIC;\r
\r
// 14 Context Data\r
\r
// Table 198 - TPM2B_CONTEXT_SENSITIVE Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[MAX_CONTEXT_SIZE];\r
+ UINT16 size;\r
+ BYTE buffer[MAX_CONTEXT_SIZE];\r
} TPM2B_CONTEXT_SENSITIVE;\r
\r
// Table 199 - TPMS_CONTEXT_DATA Structure\r
typedef struct {\r
- TPM2B_DIGEST integrity;\r
- TPM2B_CONTEXT_SENSITIVE encrypted;\r
+ TPM2B_DIGEST integrity;\r
+ TPM2B_CONTEXT_SENSITIVE encrypted;\r
} TPMS_CONTEXT_DATA;\r
\r
// Table 200 - TPM2B_CONTEXT_DATA Structure\r
typedef struct {\r
- UINT16 size;\r
- BYTE buffer[sizeof(TPMS_CONTEXT_DATA)];\r
+ UINT16 size;\r
+ BYTE buffer[sizeof (TPMS_CONTEXT_DATA)];\r
} TPM2B_CONTEXT_DATA;\r
\r
// Table 201 - TPMS_CONTEXT Structure\r
typedef struct {\r
- UINT64 sequence;\r
- TPMI_DH_CONTEXT savedHandle;\r
- TPMI_RH_HIERARCHY hierarchy;\r
- TPM2B_CONTEXT_DATA contextBlob;\r
+ UINT64 sequence;\r
+ TPMI_DH_CONTEXT savedHandle;\r
+ TPMI_RH_HIERARCHY hierarchy;\r
+ TPM2B_CONTEXT_DATA contextBlob;\r
} TPMS_CONTEXT;\r
\r
// 15 Creation Data\r
\r
// Table 203 - TPMS_CREATION_DATA Structure\r
typedef struct {\r
- TPML_PCR_SELECTION pcrSelect;\r
- TPM2B_DIGEST pcrDigest;\r
- TPMA_LOCALITY locality;\r
- TPM_ALG_ID parentNameAlg;\r
- TPM2B_NAME parentName;\r
- TPM2B_NAME parentQualifiedName;\r
- TPM2B_DATA outsideInfo;\r
+ TPML_PCR_SELECTION pcrSelect;\r
+ TPM2B_DIGEST pcrDigest;\r
+ TPMA_LOCALITY locality;\r
+ TPM_ALG_ID parentNameAlg;\r
+ TPM2B_NAME parentName;\r
+ TPM2B_NAME parentQualifiedName;\r
+ TPM2B_DATA outsideInfo;\r
} TPMS_CREATION_DATA;\r
\r
// Table 204 - TPM2B_CREATION_DATA Structure\r
typedef struct {\r
- UINT16 size;\r
- TPMS_CREATION_DATA creationData;\r
+ UINT16 size;\r
+ TPMS_CREATION_DATA creationData;\r
} TPM2B_CREATION_DATA;\r
\r
-\r
//\r
// Command Header\r
//\r
typedef struct {\r
- TPM_ST tag;\r
- UINT32 paramSize;\r
- TPM_CC commandCode;\r
+ TPM_ST tag;\r
+ UINT32 paramSize;\r
+ TPM_CC commandCode;\r
} TPM2_COMMAND_HEADER;\r
\r
typedef struct {\r
- TPM_ST tag;\r
- UINT32 paramSize;\r
- TPM_RC responseCode;\r
+ TPM_ST tag;\r
+ UINT32 paramSize;\r
+ TPM_RC responseCode;\r
} TPM2_RESPONSE_HEADER;\r
\r
#pragma pack ()\r
//\r
// TCG Algorithm Registry\r
//\r
-#define HASH_ALG_SHA1 0x00000001\r
-#define HASH_ALG_SHA256 0x00000002\r
-#define HASH_ALG_SHA384 0x00000004\r
-#define HASH_ALG_SHA512 0x00000008\r
-#define HASH_ALG_SM3_256 0x00000010\r
+#define HASH_ALG_SHA1 0x00000001\r
+#define HASH_ALG_SHA256 0x00000002\r
+#define HASH_ALG_SHA384 0x00000004\r
+#define HASH_ALG_SHA512 0x00000008\r
+#define HASH_ALG_SM3_256 0x00000010\r
\r
#endif\r
#define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4\r
\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
// Flags field is replaced in version 4 and above\r
// BIT0~15: PlatformClass This field is only valid for version 4 and above\r
// BIT16~31: Reserved\r
- UINT32 Flags;\r
- UINT64 AddressOfControlArea;\r
- UINT32 StartMethod;\r
-//UINT8 PlatformSpecificParameters[]; // size up to 12\r
-//UINT32 Laml; // Optional\r
-//UINT64 Lasa; // Optional\r
+ UINT32 Flags;\r
+ UINT64 AddressOfControlArea;\r
+ UINT32 StartMethod;\r
+ // UINT8 PlatformSpecificParameters[]; // size up to 12\r
+ // UINT32 Laml; // Optional\r
+ // UINT64 Lasa; // Optional\r
} EFI_TPM2_ACPI_TABLE;\r
\r
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2\r
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6\r
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7\r
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8\r
-#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11\r
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI 2\r
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS 6\r
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7\r
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8\r
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11\r
\r
typedef struct {\r
- UINT32 Reserved;\r
- UINT32 Error;\r
- UINT32 Cancel;\r
- UINT32 Start;\r
- UINT64 InterruptControl;\r
- UINT32 CommandSize;\r
- UINT64 Command;\r
- UINT32 ResponseSize;\r
- UINT64 Response;\r
+ UINT32 Reserved;\r
+ UINT32 Error;\r
+ UINT32 Cancel;\r
+ UINT32 Start;\r
+ UINT64 InterruptControl;\r
+ UINT32 CommandSize;\r
+ UINT64 Command;\r
+ UINT32 ResponseSize;\r
+ UINT64 Response;\r
} EFI_TPM2_ACPI_CONTROL_AREA;\r
\r
//\r
// Refer to Table 9: Start Method Specific Parameters for ARM SMC\r
//\r
typedef struct {\r
- UINT32 Interrupt;\r
- UINT8 Flags;\r
- UINT8 OperationFlags;\r
- UINT8 Reserved[2];\r
- UINT32 SmcFunctionId;\r
+ UINT32 Interrupt;\r
+ UINT8 Flags;\r
+ UINT8 OperationFlags;\r
+ UINT8 Reserved[2];\r
+ UINT32 SmcFunctionId;\r
} EFI_TPM2_ACPI_START_METHOD_SPECIFIC_PARAMETERS_ARM_SMC;\r
\r
#pragma pack ()\r
///\r
/// Used to gain ownership for this particular port.\r
///\r
- UINT8 Access; // 0\r
- UINT8 Reserved1[7]; // 1\r
+ UINT8 Access; // 0\r
+ UINT8 Reserved1[7]; // 1\r
///\r
/// Controls interrupts.\r
///\r
- UINT32 IntEnable; // 8\r
+ UINT32 IntEnable; // 8\r
///\r
/// SIRQ vector to be used by the TPM.\r
///\r
- UINT8 IntVector; // 0ch\r
- UINT8 Reserved2[3]; // 0dh\r
+ UINT8 IntVector; // 0ch\r
+ UINT8 Reserved2[3]; // 0dh\r
///\r
/// What caused interrupt.\r
///\r
- UINT32 IntSts; // 10h\r
+ UINT32 IntSts; // 10h\r
///\r
/// Shows which interrupts are supported by that particular TPM.\r
///\r
- UINT32 InterfaceCapability;// 14h\r
+ UINT32 InterfaceCapability; // 14h\r
///\r
/// Status Register. Provides status of the TPM.\r
///\r
- UINT8 Status; // 18h\r
+ UINT8 Status; // 18h\r
///\r
/// Number of consecutive writes that can be done to the TPM.\r
///\r
- UINT16 BurstCount; // 19h\r
+ UINT16 BurstCount; // 19h\r
///\r
/// Additional Status Register.\r
///\r
- UINT8 StatusEx; // 1Bh\r
- UINT8 Reserved3[8];\r
+ UINT8 StatusEx; // 1Bh\r
+ UINT8 Reserved3[8];\r
///\r
/// Read or write FIFO, depending on transaction.\r
///\r
- UINT32 DataFifo; // 24h\r
- UINT8 Reserved4[8]; // 28h\r
+ UINT32 DataFifo; // 24h\r
+ UINT8 Reserved4[8]; // 28h\r
///\r
/// Used to identify the Interface types supported by the TPM.\r
///\r
- UINT32 InterfaceId; // 30h\r
- UINT8 Reserved5[0x4c]; // 34h\r
+ UINT32 InterfaceId; // 30h\r
+ UINT8 Reserved5[0x4c]; // 34h\r
///\r
/// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r
///\r
- UINT32 XDataFifo; // 80h\r
- UINT8 Reserved6[0xe7c]; // 84h\r
+ UINT32 XDataFifo; // 80h\r
+ UINT8 Reserved6[0xe7c]; // 84h\r
///\r
/// Vendor ID\r
///\r
- UINT16 Vid; // 0f00h\r
+ UINT16 Vid; // 0f00h\r
///\r
/// Device ID\r
///\r
- UINT16 Did; // 0f02h\r
+ UINT16 Did; // 0f02h\r
///\r
/// Revision ID\r
///\r
- UINT8 Rid; // 0f04h\r
- UINT8 Reserved[0xfb]; // 0f05h\r
+ UINT8 Rid; // 0f04h\r
+ UINT8 Reserved[0xfb]; // 0f05h\r
} PTP_FIFO_REGISTERS;\r
\r
//\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
-typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
+typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r
\r
//\r
// Define bits of FIFO Interface Identifier Register\r
//\r
typedef union {\r
struct {\r
- UINT32 InterfaceType:4;\r
- UINT32 InterfaceVersion:4;\r
- UINT32 CapLocality:1;\r
- UINT32 Reserved1:2;\r
- UINT32 CapDataXferSizeSupport:2;\r
- UINT32 CapFIFO:1;\r
- UINT32 CapCRB:1;\r
- UINT32 CapIFRes:2;\r
- UINT32 InterfaceSelector:2;\r
- UINT32 IntfSelLock:1;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:8;\r
+ UINT32 InterfaceType : 4;\r
+ UINT32 InterfaceVersion : 4;\r
+ UINT32 CapLocality : 1;\r
+ UINT32 Reserved1 : 2;\r
+ UINT32 CapDataXferSizeSupport : 2;\r
+ UINT32 CapFIFO : 1;\r
+ UINT32 CapCRB : 1;\r
+ UINT32 CapIFRes : 2;\r
+ UINT32 InterfaceSelector : 2;\r
+ UINT32 IntfSelLock : 1;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PTP_FIFO_INTERFACE_IDENTIFIER;\r
\r
//\r
//\r
typedef union {\r
struct {\r
- UINT32 DataAvailIntSupport:1;\r
- UINT32 StsValidIntSupport:1;\r
- UINT32 LocalityChangeIntSupport:1;\r
- UINT32 InterruptLevelHigh:1;\r
- UINT32 InterruptLevelLow:1;\r
- UINT32 InterruptEdgeRising:1;\r
- UINT32 InterruptEdgeFalling:1;\r
- UINT32 CommandReadyIntSupport:1;\r
- UINT32 BurstCountStatic:1;\r
- UINT32 DataTransferSizeSupport:2;\r
- UINT32 Reserved:17;\r
- UINT32 InterfaceVersion:3;\r
- UINT32 Reserved2:1;\r
+ UINT32 DataAvailIntSupport : 1;\r
+ UINT32 StsValidIntSupport : 1;\r
+ UINT32 LocalityChangeIntSupport : 1;\r
+ UINT32 InterruptLevelHigh : 1;\r
+ UINT32 InterruptLevelLow : 1;\r
+ UINT32 InterruptEdgeRising : 1;\r
+ UINT32 InterruptEdgeFalling : 1;\r
+ UINT32 CommandReadyIntSupport : 1;\r
+ UINT32 BurstCountStatic : 1;\r
+ UINT32 DataTransferSizeSupport : 2;\r
+ UINT32 Reserved : 17;\r
+ UINT32 InterfaceVersion : 3;\r
+ UINT32 Reserved2 : 1;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PTP_FIFO_INTERFACE_CAPABILITY;\r
\r
///\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2\r
#define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3\r
\r
-\r
//\r
// Define bits of ACCESS and STATUS registers\r
//\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
-#define PTP_FIFO_VALID BIT7\r
+#define PTP_FIFO_VALID BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
-#define PTP_FIFO_ACC_ACTIVE BIT5\r
+#define PTP_FIFO_ACC_ACTIVE BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
-#define PTP_FIFO_ACC_SEIZED BIT4\r
+#define PTP_FIFO_ACC_SEIZED BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
-#define PTP_FIFO_ACC_SEIZE BIT3\r
+#define PTP_FIFO_ACC_SEIZE BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
-#define PTP_FIFO_ACC_PENDIND BIT2\r
+#define PTP_FIFO_ACC_PENDIND BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
-#define PTP_FIFO_ACC_RQUUSE BIT1\r
+#define PTP_FIFO_ACC_RQUUSE BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
-#define PTP_FIFO_ACC_ESTABLISH BIT0\r
+#define PTP_FIFO_ACC_ESTABLISH BIT0\r
\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
-#define PTP_FIFO_STS_VALID BIT7\r
+#define PTP_FIFO_STS_VALID BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
-#define PTP_FIFO_STS_READY BIT6\r
+#define PTP_FIFO_STS_READY BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
-#define PTP_FIFO_STS_GO BIT5\r
+#define PTP_FIFO_STS_GO BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
-#define PTP_FIFO_STS_DATA BIT4\r
+#define PTP_FIFO_STS_DATA BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
-#define PTP_FIFO_STS_EXPECT BIT3\r
+#define PTP_FIFO_STS_EXPECT BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
-#define PTP_FIFO_STS_SELFTEST_DONE BIT2\r
+#define PTP_FIFO_STS_SELFTEST_DONE BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
-#define PTP_FIFO_STS_RETRY BIT1\r
+#define PTP_FIFO_STS_RETRY BIT1\r
\r
///\r
/// TPM Family Identifier.\r
/// 00: TPM 1.2 Family\r
/// 01: TPM 2.0 Family\r
///\r
-#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)\r
-#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r
-#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r
-#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r
+#define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r
///\r
/// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r
/// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r
///\r
-#define PTP_FIFO_STS_EX_CANCEL BIT0\r
-\r
+#define PTP_FIFO_STS_EX_CANCEL BIT0\r
\r
//\r
// PTP CRB definition\r
///\r
/// Used to determine current state of Locality of the TPM.\r
///\r
- UINT32 LocalityState; // 0\r
- UINT8 Reserved1[4]; // 4\r
+ UINT32 LocalityState; // 0\r
+ UINT8 Reserved1[4]; // 4\r
///\r
/// Used to gain control of the TPM by this Locality.\r
///\r
- UINT32 LocalityControl; // 8\r
+ UINT32 LocalityControl; // 8\r
///\r
/// Used to determine whether Locality has been granted or Seized.\r
///\r
- UINT32 LocalityStatus; // 0ch\r
- UINT8 Reserved2[0x20]; // 10h\r
+ UINT32 LocalityStatus; // 0ch\r
+ UINT8 Reserved2[0x20]; // 10h\r
///\r
/// Used to identify the Interface types supported by the TPM.\r
///\r
- UINT32 InterfaceId; // 30h\r
+ UINT32 InterfaceId; // 30h\r
///\r
/// Vendor ID\r
///\r
- UINT16 Vid; // 34h\r
+ UINT16 Vid; // 34h\r
///\r
/// Device ID\r
///\r
- UINT16 Did; // 36h\r
+ UINT16 Did; // 36h\r
///\r
/// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r
///\r
- UINT64 CrbControlExtension; // 38h\r
+ UINT64 CrbControlExtension; // 38h\r
///\r
/// Register used to initiate transactions for the CRB interface.\r
///\r
- UINT32 CrbControlRequest; // 40h\r
+ UINT32 CrbControlRequest; // 40h\r
///\r
/// Register used by the TPM to provide status of the CRB interface.\r
///\r
- UINT32 CrbControlStatus; // 44h\r
+ UINT32 CrbControlStatus; // 44h\r
///\r
/// Register used by software to cancel command processing.\r
///\r
- UINT32 CrbControlCancel; // 48h\r
+ UINT32 CrbControlCancel; // 48h\r
///\r
/// Register used to indicate presence of command or response data in the CRB buffer.\r
///\r
- UINT32 CrbControlStart; // 4Ch\r
+ UINT32 CrbControlStart; // 4Ch\r
///\r
/// Register used to configure and respond to interrupts.\r
///\r
- UINT32 CrbInterruptEnable; // 50h\r
- UINT32 CrbInterruptStatus; // 54h\r
+ UINT32 CrbInterruptEnable; // 50h\r
+ UINT32 CrbInterruptStatus; // 54h\r
///\r
/// Size of the Command buffer.\r
///\r
- UINT32 CrbControlCommandSize; // 58h\r
+ UINT32 CrbControlCommandSize; // 58h\r
///\r
/// Command buffer start address\r
///\r
- UINT32 CrbControlCommandAddressLow; // 5Ch\r
- UINT32 CrbControlCommandAddressHigh; // 60h\r
+ UINT32 CrbControlCommandAddressLow; // 5Ch\r
+ UINT32 CrbControlCommandAddressHigh; // 60h\r
///\r
/// Size of the Response buffer\r
///\r
- UINT32 CrbControlResponseSize; // 64h\r
+ UINT32 CrbControlResponseSize; // 64h\r
///\r
/// Address of the start of the Response buffer\r
///\r
- UINT64 CrbControlResponseAddrss; // 68h\r
- UINT8 Reserved4[0x10]; // 70h\r
+ UINT64 CrbControlResponseAddrss; // 68h\r
+ UINT8 Reserved4[0x10]; // 70h\r
///\r
/// Command/Response Data may be defined as large as 3968 (0xF80).\r
///\r
- UINT8 CrbDataBuffer[0xF80]; // 80h\r
+ UINT8 CrbDataBuffer[0xF80]; // 80h\r
} PTP_CRB_REGISTERS;\r
\r
//\r
// Define pointer types used to access CRB registers on PTP\r
//\r
-typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
+typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r
\r
//\r
// Define bits of CRB Interface Identifier Register\r
//\r
typedef union {\r
struct {\r
- UINT32 InterfaceType:4;\r
- UINT32 InterfaceVersion:4;\r
- UINT32 CapLocality:1;\r
- UINT32 CapCRBIdleBypass:1;\r
- UINT32 Reserved1:1;\r
- UINT32 CapDataXferSizeSupport:2;\r
- UINT32 CapFIFO:1;\r
- UINT32 CapCRB:1;\r
- UINT32 CapIFRes:2;\r
- UINT32 InterfaceSelector:2;\r
- UINT32 IntfSelLock:1;\r
- UINT32 Reserved2:4;\r
- UINT32 Rid:8;\r
+ UINT32 InterfaceType : 4;\r
+ UINT32 InterfaceVersion : 4;\r
+ UINT32 CapLocality : 1;\r
+ UINT32 CapCRBIdleBypass : 1;\r
+ UINT32 Reserved1 : 1;\r
+ UINT32 CapDataXferSizeSupport : 2;\r
+ UINT32 CapFIFO : 1;\r
+ UINT32 CapCRB : 1;\r
+ UINT32 CapIFRes : 2;\r
+ UINT32 InterfaceSelector : 2;\r
+ UINT32 IntfSelLock : 1;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Rid : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} PTP_CRB_INTERFACE_IDENTIFIER;\r
\r
///\r
///\r
/// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r
///\r
-#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r
+#define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r
\r
///\r
/// 000 - Locality 0\r
/// 011 - Locality 3\r
/// 100 - Locality 4\r
///\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)\r
-#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)\r
+#define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r
\r
///\r
/// A 0 indicates to the host that no locality is assigned.\r
/// A 1 indicates a locality has been assigned.\r
///\r
-#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r
+#define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r
\r
///\r
/// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r
/// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r
///\r
-#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r
+#define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r
\r
//\r
// Define bits of Locality Control Register\r
///\r
/// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r
///\r
-#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r
+#define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r
\r
///\r
/// Writes (1): The active Locality is done with the TPM.\r
///\r
-#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r
+#define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r
\r
///\r
/// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r
///\r
-#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r
+#define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r
\r
//\r
// Define bits of Locality Status Register\r
/// 0: A higher locality has not initiated a Seize arbitration process.\r
/// 1: A higher locality has Seized the TPM from this locality.\r
///\r
-#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r
+#define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r
\r
///\r
/// 0: Locality has not been granted to the TPM.\r
/// 1: Locality has been granted access to the TPM\r
///\r
-#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r
+#define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r
\r
//\r
// Define bits of CRB Control Area Request Register\r
/// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
-#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r
+#define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r
\r
///\r
/// Used by Software to request the TPM transition to the Ready State.\r
/// 0: Cleared to 0 by TPM to acknowledge the request.\r
/// TPM SHALL complete this transition within TIMEOUT_C.\r
///\r
-#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r
+#define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r
\r
//\r
// Define bits of CRB Control Area Status Register\r
/// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r
/// SHALL be cleared by TIMEOUT_C.\r
///\r
-#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r
\r
///\r
/// Used by the TPM to indicate current status.\r
/// 1: Set by TPM to indicate a FATAL Error\r
/// 0: Indicates TPM is operational\r
///\r
-#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r
+#define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r
\r
//\r
// Define bits of CRB Control Cancel Register\r
/// Writes (0000 0001h): Cancel a command\r
/// Writes (0000 0000h): Clears field when command has been cancelled\r
///\r
-#define PTP_CRB_CONTROL_CANCEL BIT0\r
+#define PTP_CRB_CONTROL_CANCEL BIT0\r
\r
//\r
// Define bits of CRB Control Start Register\r
/// Writes (0000 0001h): TPM transitions to Command Execution\r
/// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r
///\r
-#define PTP_CRB_CONTROL_START BIT0\r
+#define PTP_CRB_CONTROL_START BIT0\r
\r
//\r
// Restore original structure alignment\r
//\r
// Default TimeOut value\r
//\r
-#define PTP_TIMEOUT_A (750 * 1000) // 750ms\r
-#define PTP_TIMEOUT_B (2000 * 1000) // 2s\r
-#define PTP_TIMEOUT_C (200 * 1000) // 200ms\r
-#define PTP_TIMEOUT_D (30 * 1000) // 30ms\r
+#define PTP_TIMEOUT_A (750 * 1000) // 750ms\r
+#define PTP_TIMEOUT_B (2000 * 1000) // 2s\r
+#define PTP_TIMEOUT_C (200 * 1000) // 200ms\r
+#define PTP_TIMEOUT_D (30 * 1000) // 30ms\r
\r
#endif\r
///\r
/// Used to gain ownership for this particular port.\r
///\r
- UINT8 Access; // 0\r
- UINT8 Reserved1[7]; // 1\r
+ UINT8 Access; // 0\r
+ UINT8 Reserved1[7]; // 1\r
///\r
/// Controls interrupts.\r
///\r
- UINT32 IntEnable; // 8\r
+ UINT32 IntEnable; // 8\r
///\r
/// SIRQ vector to be used by the TPM.\r
///\r
- UINT8 IntVector; // 0ch\r
- UINT8 Reserved2[3]; // 0dh\r
+ UINT8 IntVector; // 0ch\r
+ UINT8 Reserved2[3]; // 0dh\r
///\r
/// What caused interrupt.\r
///\r
- UINT32 IntSts; // 10h\r
+ UINT32 IntSts; // 10h\r
///\r
/// Shows which interrupts are supported by that particular TPM.\r
///\r
- UINT32 IntfCapability; // 14h\r
+ UINT32 IntfCapability; // 14h\r
///\r
/// Status Register. Provides status of the TPM.\r
///\r
- UINT8 Status; // 18h\r
+ UINT8 Status; // 18h\r
///\r
/// Number of consecutive writes that can be done to the TPM.\r
///\r
- UINT16 BurstCount; // 19h\r
- UINT8 Reserved3[9];\r
+ UINT16 BurstCount; // 19h\r
+ UINT8 Reserved3[9];\r
///\r
/// Read or write FIFO, depending on transaction.\r
///\r
- UINT32 DataFifo; // 24h\r
- UINT8 Reserved4[0xed8]; // 28h\r
+ UINT32 DataFifo; // 24h\r
+ UINT8 Reserved4[0xed8]; // 28h\r
///\r
/// Vendor ID\r
///\r
- UINT16 Vid; // 0f00h\r
+ UINT16 Vid; // 0f00h\r
///\r
/// Device ID\r
///\r
- UINT16 Did; // 0f02h\r
+ UINT16 Did; // 0f02h\r
///\r
/// Revision ID\r
///\r
- UINT8 Rid; // 0f04h\r
- UINT8 Reserved[0x7b]; // 0f05h\r
+ UINT8 Rid; // 0f04h\r
+ UINT8 Reserved[0x7b]; // 0f05h\r
///\r
/// Alias to I/O legacy space.\r
///\r
- UINT32 LegacyAddress1; // 0f80h\r
+ UINT32 LegacyAddress1; // 0f80h\r
///\r
/// Additional 8 bits for I/O legacy space extension.\r
///\r
- UINT32 LegacyAddress1Ex; // 0f84h\r
+ UINT32 LegacyAddress1Ex; // 0f84h\r
///\r
/// Alias to second I/O legacy space.\r
///\r
- UINT32 LegacyAddress2; // 0f88h\r
+ UINT32 LegacyAddress2; // 0f88h\r
///\r
/// Additional 8 bits for second I/O legacy space extension.\r
///\r
- UINT32 LegacyAddress2Ex; // 0f8ch\r
+ UINT32 LegacyAddress2Ex; // 0f8ch\r
///\r
/// Vendor-defined configuration registers.\r
///\r
- UINT8 VendorDefined[0x70];// 0f90h\r
+ UINT8 VendorDefined[0x70]; // 0f90h\r
} TIS_PC_REGISTERS;\r
\r
//\r
//\r
// Define pointer types used to access TIS registers on PC\r
//\r
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
+typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;\r
\r
//\r
// Define bits of ACCESS and STATUS registers\r
///\r
/// This bit is a 1 to indicate that the other bits in this register are valid.\r
///\r
-#define TIS_PC_VALID BIT7\r
+#define TIS_PC_VALID BIT7\r
///\r
/// Indicate that this locality is active.\r
///\r
-#define TIS_PC_ACC_ACTIVE BIT5\r
+#define TIS_PC_ACC_ACTIVE BIT5\r
///\r
/// Set to 1 to indicate that this locality had the TPM taken away while\r
/// this locality had the TIS_PC_ACC_ACTIVE bit set.\r
///\r
-#define TIS_PC_ACC_SEIZED BIT4\r
+#define TIS_PC_ACC_SEIZED BIT4\r
///\r
/// Set to 1 to indicate that TPM MUST reset the\r
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r
/// locality that is writing this bit.\r
///\r
-#define TIS_PC_ACC_SEIZE BIT3\r
+#define TIS_PC_ACC_SEIZE BIT3\r
///\r
/// When this bit is 1, another locality is requesting usage of the TPM.\r
///\r
-#define TIS_PC_ACC_PENDIND BIT2\r
+#define TIS_PC_ACC_PENDIND BIT2\r
///\r
/// Set to 1 to indicate that this locality is requesting to use TPM.\r
///\r
-#define TIS_PC_ACC_RQUUSE BIT1\r
+#define TIS_PC_ACC_RQUUSE BIT1\r
///\r
/// A value of 1 indicates that a T/OS has not been established on the platform\r
///\r
-#define TIS_PC_ACC_ESTABLISH BIT0\r
+#define TIS_PC_ACC_ESTABLISH BIT0\r
\r
///\r
/// Write a 1 to this bit to notify TPM to cancel currently executing command\r
///\r
-#define TIS_PC_STS_CANCEL BIT24\r
+#define TIS_PC_STS_CANCEL BIT24\r
///\r
/// This field indicates that STS_DATA and STS_EXPECT are valid\r
///\r
-#define TIS_PC_STS_VALID BIT7\r
+#define TIS_PC_STS_VALID BIT7\r
///\r
/// When this bit is 1, TPM is in the Ready state,\r
/// indicating it is ready to receive a new command.\r
///\r
-#define TIS_PC_STS_READY BIT6\r
+#define TIS_PC_STS_READY BIT6\r
///\r
/// Write a 1 to this bit to cause the TPM to execute that command.\r
///\r
-#define TIS_PC_STS_GO BIT5\r
+#define TIS_PC_STS_GO BIT5\r
///\r
/// This bit indicates that the TPM has data available as a response.\r
///\r
-#define TIS_PC_STS_DATA BIT4\r
+#define TIS_PC_STS_DATA BIT4\r
///\r
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r
///\r
-#define TIS_PC_STS_EXPECT BIT3\r
+#define TIS_PC_STS_EXPECT BIT3\r
///\r
/// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r
///\r
-#define TIS_PC_STS_SELFTEST_DONE BIT2\r
+#define TIS_PC_STS_SELFTEST_DONE BIT2\r
///\r
/// Writes a 1 to this bit to force the TPM to re-send the response.\r
///\r
-#define TIS_PC_STS_RETRY BIT1\r
+#define TIS_PC_STS_RETRY BIT1\r
\r
//\r
// Default TimeOut value\r
//\r
-#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
-#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
-#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
-#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_A (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_B (2000 * 1000) // 2s\r
+#define TIS_TIMEOUT_C (750 * 1000) // 750ms\r
+#define TIS_TIMEOUT_D (750 * 1000) // 750ms\r
\r
#endif\r
#define UDF_VRS_START_OFFSET ((UINT64)(16ULL << UDF_LOGICAL_SECTOR_SHIFT))\r
\r
typedef enum {\r
- UdfPrimaryVolumeDescriptor = 1,\r
- UdfAnchorVolumeDescriptorPointer = 2,\r
- UdfVolumeDescriptorPointer = 3,\r
+ UdfPrimaryVolumeDescriptor = 1,\r
+ UdfAnchorVolumeDescriptorPointer = 2,\r
+ UdfVolumeDescriptorPointer = 3,\r
UdfImplemenationUseVolumeDescriptor = 4,\r
- UdfPartitionDescriptor = 5,\r
- UdfLogicalVolumeDescriptor = 6,\r
- UdfUnallocatedSpaceDescriptor = 7,\r
- UdfTerminatingDescriptor = 8,\r
+ UdfPartitionDescriptor = 5,\r
+ UdfLogicalVolumeDescriptor = 6,\r
+ UdfUnallocatedSpaceDescriptor = 7,\r
+ UdfTerminatingDescriptor = 8,\r
UdfLogicalVolumeIntegrityDescriptor = 9,\r
- UdfFileSetDescriptor = 256,\r
- UdfFileIdentifierDescriptor = 257,\r
- UdfAllocationExtentDescriptor = 258,\r
- UdfFileEntry = 261,\r
- UdfExtendedFileEntry = 266,\r
+ UdfFileSetDescriptor = 256,\r
+ UdfFileIdentifierDescriptor = 257,\r
+ UdfAllocationExtentDescriptor = 258,\r
+ UdfFileEntry = 261,\r
+ UdfExtendedFileEntry = 266,\r
} UDF_VOLUME_DESCRIPTOR_ID;\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT16 TagIdentifier;\r
- UINT16 DescriptorVersion;\r
- UINT8 TagChecksum;\r
- UINT8 Reserved;\r
- UINT16 TagSerialNumber;\r
- UINT16 DescriptorCRC;\r
- UINT16 DescriptorCRCLength;\r
- UINT32 TagLocation;\r
+ UINT16 TagIdentifier;\r
+ UINT16 DescriptorVersion;\r
+ UINT8 TagChecksum;\r
+ UINT8 Reserved;\r
+ UINT16 TagSerialNumber;\r
+ UINT16 DescriptorCRC;\r
+ UINT16 DescriptorCRCLength;\r
+ UINT32 TagLocation;\r
} UDF_DESCRIPTOR_TAG;\r
\r
typedef struct {\r
- UINT32 ExtentLength;\r
- UINT32 ExtentLocation;\r
+ UINT32 ExtentLength;\r
+ UINT32 ExtentLocation;\r
} UDF_EXTENT_AD;\r
\r
typedef struct {\r
- UINT8 CharacterSetType;\r
- UINT8 CharacterSetInfo[63];\r
+ UINT8 CharacterSetType;\r
+ UINT8 CharacterSetInfo[63];\r
} UDF_CHAR_SPEC;\r
\r
typedef struct {\r
- UINT8 Flags;\r
- UINT8 Identifier[23];\r
+ UINT8 Flags;\r
+ UINT8 Identifier[23];\r
union {\r
//\r
// Domain Entity Identifier\r
//\r
struct {\r
- UINT16 UdfRevision;\r
- UINT8 DomainFlags;\r
- UINT8 Reserved[5];\r
+ UINT16 UdfRevision;\r
+ UINT8 DomainFlags;\r
+ UINT8 Reserved[5];\r
} Domain;\r
//\r
// UDF Entity Identifier\r
//\r
struct {\r
- UINT16 UdfRevision;\r
- UINT8 OSClass;\r
- UINT8 OSIdentifier;\r
- UINT8 Reserved[4];\r
+ UINT16 UdfRevision;\r
+ UINT8 OSClass;\r
+ UINT8 OSIdentifier;\r
+ UINT8 Reserved[4];\r
} Entity;\r
//\r
// Implementation Entity Identifier\r
//\r
struct {\r
- UINT8 OSClass;\r
- UINT8 OSIdentifier;\r
- UINT8 ImplementationUseArea[6];\r
+ UINT8 OSClass;\r
+ UINT8 OSIdentifier;\r
+ UINT8 ImplementationUseArea[6];\r
} ImplementationEntity;\r
//\r
// Application Entity Identifier\r
//\r
struct {\r
- UINT8 ApplicationUseArea[8];\r
+ UINT8 ApplicationUseArea[8];\r
} ApplicationEntity;\r
//\r
// Raw Identifier Suffix\r
//\r
struct {\r
- UINT8 Data[8];\r
+ UINT8 Data[8];\r
} Raw;\r
} Suffix;\r
} UDF_ENTITY_ID;\r
\r
typedef struct {\r
- UINT32 LogicalBlockNumber;\r
- UINT16 PartitionReferenceNumber;\r
+ UINT32 LogicalBlockNumber;\r
+ UINT16 PartitionReferenceNumber;\r
} UDF_LB_ADDR;\r
\r
typedef struct {\r
- UINT32 ExtentLength;\r
- UDF_LB_ADDR ExtentLocation;\r
- UINT8 ImplementationUse[6];\r
+ UINT32 ExtentLength;\r
+ UDF_LB_ADDR ExtentLocation;\r
+ UINT8 ImplementationUse[6];\r
} UDF_LONG_ALLOCATION_DESCRIPTOR;\r
\r
typedef struct {\r
- UDF_DESCRIPTOR_TAG DescriptorTag;\r
- UDF_EXTENT_AD MainVolumeDescriptorSequenceExtent;\r
- UDF_EXTENT_AD ReserveVolumeDescriptorSequenceExtent;\r
- UINT8 Reserved[480];\r
+ UDF_DESCRIPTOR_TAG DescriptorTag;\r
+ UDF_EXTENT_AD MainVolumeDescriptorSequenceExtent;\r
+ UDF_EXTENT_AD ReserveVolumeDescriptorSequenceExtent;\r
+ UINT8 Reserved[480];\r
} UDF_ANCHOR_VOLUME_DESCRIPTOR_POINTER;\r
\r
typedef struct {\r
- UDF_DESCRIPTOR_TAG DescriptorTag;\r
- UINT32 VolumeDescriptorSequenceNumber;\r
- UDF_CHAR_SPEC DescriptorCharacterSet;\r
- UINT8 LogicalVolumeIdentifier[128];\r
- UINT32 LogicalBlockSize;\r
- UDF_ENTITY_ID DomainIdentifier;\r
- UDF_LONG_ALLOCATION_DESCRIPTOR LogicalVolumeContentsUse;\r
- UINT32 MapTableLength;\r
- UINT32 NumberOfPartitionMaps;\r
- UDF_ENTITY_ID ImplementationIdentifier;\r
- UINT8 ImplementationUse[128];\r
- UDF_EXTENT_AD IntegritySequenceExtent;\r
- UINT8 PartitionMaps[6];\r
+ UDF_DESCRIPTOR_TAG DescriptorTag;\r
+ UINT32 VolumeDescriptorSequenceNumber;\r
+ UDF_CHAR_SPEC DescriptorCharacterSet;\r
+ UINT8 LogicalVolumeIdentifier[128];\r
+ UINT32 LogicalBlockSize;\r
+ UDF_ENTITY_ID DomainIdentifier;\r
+ UDF_LONG_ALLOCATION_DESCRIPTOR LogicalVolumeContentsUse;\r
+ UINT32 MapTableLength;\r
+ UINT32 NumberOfPartitionMaps;\r
+ UDF_ENTITY_ID ImplementationIdentifier;\r
+ UINT8 ImplementationUse[128];\r
+ UDF_EXTENT_AD IntegritySequenceExtent;\r
+ UINT8 PartitionMaps[6];\r
} UDF_LOGICAL_VOLUME_DESCRIPTOR;\r
\r
#pragma pack()\r
//\r
// EFI specific event types\r
//\r
-#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)\r
-#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)\r
-#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)\r
-#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)\r
-#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)\r
-#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)\r
-#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)\r
-#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)\r
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)\r
-#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)\r
-#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA)\r
-#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB)\r
-#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10)\r
-#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0)\r
-#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1)\r
-#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2)\r
+#define EV_EFI_EVENT_BASE ((TCG_EVENTTYPE) 0x80000000)\r
+#define EV_EFI_VARIABLE_DRIVER_CONFIG (EV_EFI_EVENT_BASE + 1)\r
+#define EV_EFI_VARIABLE_BOOT (EV_EFI_EVENT_BASE + 2)\r
+#define EV_EFI_BOOT_SERVICES_APPLICATION (EV_EFI_EVENT_BASE + 3)\r
+#define EV_EFI_BOOT_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 4)\r
+#define EV_EFI_RUNTIME_SERVICES_DRIVER (EV_EFI_EVENT_BASE + 5)\r
+#define EV_EFI_GPT_EVENT (EV_EFI_EVENT_BASE + 6)\r
+#define EV_EFI_ACTION (EV_EFI_EVENT_BASE + 7)\r
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 8)\r
+#define EV_EFI_HANDOFF_TABLES (EV_EFI_EVENT_BASE + 9)\r
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB2 (EV_EFI_EVENT_BASE + 0xA)\r
+#define EV_EFI_HANDOFF_TABLES2 (EV_EFI_EVENT_BASE + 0xB)\r
+#define EV_EFI_HCRTM_EVENT (EV_EFI_EVENT_BASE + 0x10)\r
+#define EV_EFI_VARIABLE_AUTHORITY (EV_EFI_EVENT_BASE + 0xE0)\r
+#define EV_EFI_SPDM_FIRMWARE_BLOB (EV_EFI_EVENT_BASE + 0xE1)\r
+#define EV_EFI_SPDM_FIRMWARE_CONFIG (EV_EFI_EVENT_BASE + 0xE2)\r
\r
#define EFI_CALLING_EFI_APPLICATION \\r
"Calling EFI Application from Boot Option"\r
#define EFI_EXIT_BOOT_SERVICES_SUCCEEDED \\r
"Exit Boot Services Returned with Success"\r
\r
+#define EV_POSTCODE_INFO_POST_CODE "POST CODE"\r
+#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)\r
\r
-#define EV_POSTCODE_INFO_POST_CODE "POST CODE"\r
-#define POST_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_POST_CODE) - 1)\r
+#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE"\r
+#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)\r
\r
-#define EV_POSTCODE_INFO_SMM_CODE "SMM CODE"\r
-#define SMM_CODE_STR_LEN (sizeof(EV_POSTCODE_INFO_SMM_CODE) - 1)\r
+#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA"\r
+#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)\r
\r
-#define EV_POSTCODE_INFO_ACPI_DATA "ACPI DATA"\r
-#define ACPI_DATA_LEN (sizeof(EV_POSTCODE_INFO_ACPI_DATA) - 1)\r
+#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE"\r
+#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)\r
\r
-#define EV_POSTCODE_INFO_BIS_CODE "BIS CODE"\r
-#define BIS_CODE_LEN (sizeof(EV_POSTCODE_INFO_BIS_CODE) - 1)\r
+#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI"\r
+#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)\r
\r
-#define EV_POSTCODE_INFO_UEFI_PI "UEFI PI"\r
-#define UEFI_PI_LEN (sizeof(EV_POSTCODE_INFO_UEFI_PI) - 1)\r
-\r
-#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM"\r
-#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1)\r
+#define EV_POSTCODE_INFO_OPROM "Embedded Option ROM"\r
+#define OPROM_LEN (sizeof(EV_POSTCODE_INFO_OPROM) - 1)\r
\r
#define EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER "Embedded UEFI Driver"\r
#define EMBEDDED_UEFI_DRIVER_LEN (sizeof(EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER) - 1)\r
//\r
#pragma pack (1)\r
\r
-typedef UINT32 TCG_EVENTTYPE;\r
-typedef TPM_PCRINDEX TCG_PCRINDEX;\r
-typedef TPM_DIGEST TCG_DIGEST;\r
+typedef UINT32 TCG_EVENTTYPE;\r
+typedef TPM_PCRINDEX TCG_PCRINDEX;\r
+typedef TPM_DIGEST TCG_DIGEST;\r
///\r
/// Event Log Entry Structure Definition\r
///\r
typedef struct tdTCG_PCR_EVENT {\r
- TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to\r
- TCG_EVENTTYPE EventType; ///< TCG EFI event type\r
- TCG_DIGEST Digest; ///< Value extended into PCRIndex\r
- UINT32 EventSize; ///< Size of the event data\r
- UINT8 Event[1]; ///< The event data\r
+ TCG_PCRINDEX PCRIndex; ///< PCRIndex event extended to\r
+ TCG_EVENTTYPE EventType; ///< TCG EFI event type\r
+ TCG_DIGEST Digest; ///< Value extended into PCRIndex\r
+ UINT32 EventSize; ///< Size of the event data\r
+ UINT8 Event[1]; ///< The event data\r
} TCG_PCR_EVENT;\r
\r
-#define TSS_EVENT_DATA_MAX_SIZE 256\r
+#define TSS_EVENT_DATA_MAX_SIZE 256\r
\r
///\r
/// TCG_PCR_EVENT_HDR\r
///\r
typedef struct tdTCG_PCR_EVENT_HDR {\r
- TCG_PCRINDEX PCRIndex;\r
- TCG_EVENTTYPE EventType;\r
- TCG_DIGEST Digest;\r
- UINT32 EventSize;\r
+ TCG_PCRINDEX PCRIndex;\r
+ TCG_EVENTTYPE EventType;\r
+ TCG_DIGEST Digest;\r
+ UINT32 EventSize;\r
} TCG_PCR_EVENT_HDR;\r
\r
///\r
/// because PEI is 32-bit while DXE is 64-bit on x64 platforms\r
///\r
typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {\r
- EFI_PHYSICAL_ADDRESS BlobBase;\r
- UINT64 BlobLength;\r
+ EFI_PHYSICAL_ADDRESS BlobBase;\r
+ UINT64 BlobLength;\r
} EFI_PLATFORM_FIRMWARE_BLOB;\r
\r
///\r
/// event to facilitate the measurement of firmware volume.\r
///\r
typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB {\r
- EFI_PHYSICAL_ADDRESS BlobBase;\r
- UINT64 BlobLength;\r
+ EFI_PHYSICAL_ADDRESS BlobBase;\r
+ UINT64 BlobLength;\r
} UEFI_PLATFORM_FIRMWARE_BLOB;\r
\r
///\r
/// event to facilitate the measurement of firmware volume.\r
///\r
typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 {\r
- UINT8 BlobDescriptionSize;\r
-//UINT8 BlobDescription[BlobDescriptionSize];\r
-//EFI_PHYSICAL_ADDRESS BlobBase;\r
-//UINT64 BlobLength;\r
+ UINT8 BlobDescriptionSize;\r
+ // UINT8 BlobDescription[BlobDescriptionSize];\r
+ // EFI_PHYSICAL_ADDRESS BlobBase;\r
+ // UINT64 BlobLength;\r
} UEFI_PLATFORM_FIRMWARE_BLOB2;\r
\r
///\r
/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER\r
///\r
typedef struct tdEFI_IMAGE_LOAD_EVENT {\r
- EFI_PHYSICAL_ADDRESS ImageLocationInMemory;\r
- UINTN ImageLengthInMemory;\r
- UINTN ImageLinkTimeAddress;\r
- UINTN LengthOfDevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL DevicePath[1];\r
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;\r
+ UINTN ImageLengthInMemory;\r
+ UINTN ImageLinkTimeAddress;\r
+ UINTN LengthOfDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];\r
} EFI_IMAGE_LOAD_EVENT;\r
\r
///\r
/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER\r
///\r
typedef struct tdUEFI_IMAGE_LOAD_EVENT {\r
- EFI_PHYSICAL_ADDRESS ImageLocationInMemory;\r
- UINT64 ImageLengthInMemory;\r
- UINT64 ImageLinkTimeAddress;\r
- UINT64 LengthOfDevicePath;\r
- EFI_DEVICE_PATH_PROTOCOL DevicePath[1];\r
+ EFI_PHYSICAL_ADDRESS ImageLocationInMemory;\r
+ UINT64 ImageLengthInMemory;\r
+ UINT64 ImageLinkTimeAddress;\r
+ UINT64 LengthOfDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL DevicePath[1];\r
} UEFI_IMAGE_LOAD_EVENT;\r
\r
///\r
/// the measurement of given configuration tables.\r
///\r
typedef struct tdEFI_HANDOFF_TABLE_POINTERS {\r
- UINTN NumberOfTables;\r
- EFI_CONFIGURATION_TABLE TableEntry[1];\r
+ UINTN NumberOfTables;\r
+ EFI_CONFIGURATION_TABLE TableEntry[1];\r
} EFI_HANDOFF_TABLE_POINTERS;\r
\r
///\r
/// the measurement of given configuration tables.\r
///\r
typedef struct tdUEFI_HANDOFF_TABLE_POINTERS {\r
- UINT64 NumberOfTables;\r
- EFI_CONFIGURATION_TABLE TableEntry[1];\r
+ UINT64 NumberOfTables;\r
+ EFI_CONFIGURATION_TABLE TableEntry[1];\r
} UEFI_HANDOFF_TABLE_POINTERS;\r
\r
///\r
/// the measurement of given configuration tables.\r
///\r
typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 {\r
- UINT8 TableDescriptionSize;\r
-//UINT8 TableDescription[TableDescriptionSize];\r
-//UINT64 NumberOfTables;\r
-//EFI_CONFIGURATION_TABLE TableEntry[1];\r
+ UINT8 TableDescriptionSize;\r
+ // UINT8 TableDescription[TableDescriptionSize];\r
+ // UINT64 NumberOfTables;\r
+ // EFI_CONFIGURATION_TABLE TableEntry[1];\r
} UEFI_HANDOFF_TABLE_POINTERS2;\r
\r
///\r
/// This is defined in TCG EFI Platform Spec for TPM1.1 or 1.2 V1.22\r
///\r
typedef struct tdEFI_VARIABLE_DATA {\r
- EFI_GUID VariableName;\r
- UINTN UnicodeNameLength;\r
- UINTN VariableDataLength;\r
- CHAR16 UnicodeName[1];\r
- INT8 VariableData[1]; ///< Driver or platform-specific data\r
+ EFI_GUID VariableName;\r
+ UINTN UnicodeNameLength;\r
+ UINTN VariableDataLength;\r
+ CHAR16 UnicodeName[1];\r
+ INT8 VariableData[1]; ///< Driver or platform-specific data\r
} EFI_VARIABLE_DATA;\r
\r
///\r
/// This is defined in TCG PC Client Firmware Profile Spec 00.21\r
///\r
typedef struct tdUEFI_VARIABLE_DATA {\r
- EFI_GUID VariableName;\r
- UINT64 UnicodeNameLength;\r
- UINT64 VariableDataLength;\r
- CHAR16 UnicodeName[1];\r
- INT8 VariableData[1]; ///< Driver or platform-specific data\r
+ EFI_GUID VariableName;\r
+ UINT64 UnicodeNameLength;\r
+ UINT64 VariableDataLength;\r
+ CHAR16 UnicodeName[1];\r
+ INT8 VariableData[1]; ///< Driver or platform-specific data\r
} UEFI_VARIABLE_DATA;\r
\r
//\r
// For TrEE1.0 compatibility\r
//\r
typedef struct {\r
- EFI_GUID VariableName;\r
- UINT64 UnicodeNameLength; // The TCG Definition used UINTN\r
- UINT64 VariableDataLength; // The TCG Definition used UINTN\r
- CHAR16 UnicodeName[1];\r
- INT8 VariableData[1];\r
+ EFI_GUID VariableName;\r
+ UINT64 UnicodeNameLength; // The TCG Definition used UINTN\r
+ UINT64 VariableDataLength; // The TCG Definition used UINTN\r
+ CHAR16 UnicodeName[1];\r
+ INT8 VariableData[1];\r
} EFI_VARIABLE_DATA_TREE;\r
\r
typedef struct tdEFI_GPT_DATA {\r
- EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;\r
- UINTN NumberOfPartitions;\r
- EFI_PARTITION_ENTRY Partitions[1];\r
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;\r
+ UINTN NumberOfPartitions;\r
+ EFI_PARTITION_ENTRY Partitions[1];\r
} EFI_GPT_DATA;\r
\r
typedef struct tdUEFI_GPT_DATA {\r
- EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;\r
- UINT64 NumberOfPartitions;\r
- EFI_PARTITION_ENTRY Partitions[1];\r
+ EFI_PARTITION_TABLE_HEADER EfiPartitionHeader;\r
+ UINT64 NumberOfPartitions;\r
+ EFI_PARTITION_ENTRY Partitions[1];\r
} UEFI_GPT_DATA;\r
\r
-#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"\r
-#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1\r
+#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"\r
+#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION 1\r
\r
#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_NULL 0\r
#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_PCI 1\r
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.\r
///\r
typedef struct {\r
- UINT8 Signature[16];\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT32 SpdmHashAlgo;\r
- UINT32 DeviceType;\r
-//SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock;\r
+ UINT8 Signature[16];\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT32 SpdmHashAlgo;\r
+ UINT32 DeviceType;\r
+ // SPDM_MEASUREMENT_BLOCK SpdmMeasurementBlock;\r
} TCG_DEVICE_SECURITY_EVENT_DATA_HEADER;\r
\r
#define TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT_VERSION 0\r
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.\r
///\r
typedef struct {\r
- UINT16 Version;\r
- UINT16 Length;\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT8 RevisionID;\r
- UINT8 ClassCode[3];\r
- UINT16 SubsystemVendorID;\r
- UINT16 SubsystemID;\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT8 RevisionID;\r
+ UINT8 ClassCode[3];\r
+ UINT16 SubsystemVendorID;\r
+ UINT16 SubsystemID;\r
} TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT;\r
\r
#define TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT_VERSION 0\r
/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.\r
///\r
typedef struct {\r
- UINT16 Version;\r
- UINT16 Length;\r
-//UINT8 DeviceDescriptor[DescLen];\r
-//UINT8 BodDescriptor[DescLen];\r
-//UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration];\r
+ UINT16 Version;\r
+ UINT16 Length;\r
+ // UINT8 DeviceDescriptor[DescLen];\r
+ // UINT8 BodDescriptor[DescLen];\r
+ // UINT8 ConfigurationDescriptor[DescLen][NumOfConfiguration];\r
} TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT;\r
\r
//\r
// Crypto Agile Log Entry Format\r
//\r
typedef struct tdTCG_PCR_EVENT2 {\r
- TCG_PCRINDEX PCRIndex;\r
- TCG_EVENTTYPE EventType;\r
- TPML_DIGEST_VALUES Digest;\r
- UINT32 EventSize;\r
- UINT8 Event[1];\r
+ TCG_PCRINDEX PCRIndex;\r
+ TCG_EVENTTYPE EventType;\r
+ TPML_DIGEST_VALUES Digest;\r
+ UINT32 EventSize;\r
+ UINT8 Event[1];\r
} TCG_PCR_EVENT2;\r
\r
//\r
// TCG PCR Event2 Header\r
// Follow TCG EFI Protocol Spec 5.2 Crypto Agile Log Entry Format\r
//\r
-typedef struct tdTCG_PCR_EVENT2_HDR{\r
- TCG_PCRINDEX PCRIndex;\r
- TCG_EVENTTYPE EventType;\r
- TPML_DIGEST_VALUES Digests;\r
- UINT32 EventSize;\r
+typedef struct tdTCG_PCR_EVENT2_HDR {\r
+ TCG_PCRINDEX PCRIndex;\r
+ TCG_EVENTTYPE EventType;\r
+ TPML_DIGEST_VALUES Digests;\r
+ UINT32 EventSize;\r
} TCG_PCR_EVENT2_HDR;\r
\r
//\r
//\r
// TCG defined hashing algorithm ID.\r
//\r
- UINT16 algorithmId;\r
+ UINT16 algorithmId;\r
//\r
// The size of the digest for the respective hashing algorithm.\r
//\r
- UINT16 digestSize;\r
+ UINT16 digestSize;\r
} TCG_EfiSpecIdEventAlgorithmSize;\r
\r
-#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"\r
-#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"\r
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_02 "Spec ID Event02"\r
+#define TCG_EfiSpecIDEventStruct_SIGNATURE_03 "Spec ID Event03"\r
\r
-#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1\r
-#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2\r
-#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2\r
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM12 1\r
+#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM12 2\r
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM12 2\r
\r
#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2 2\r
#define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2 0\r
#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2_REV_105 105\r
\r
typedef struct {\r
- UINT8 signature[16];\r
+ UINT8 signature[16];\r
//\r
// The value for the Platform Class.\r
// The enumeration is defined in the TCG ACPI Specification Client Common Header.\r
//\r
- UINT32 platformClass;\r
+ UINT32 platformClass;\r
//\r
// The TCG EFI Platform Specification minor version number this BIOS supports.\r
// Any BIOS supporting version (1.22) MUST set this value to 02h.\r
// Any BIOS supporting version (2.0) SHALL set this value to 0x00.\r
//\r
- UINT8 specVersionMinor;\r
+ UINT8 specVersionMinor;\r
//\r
// The TCG EFI Platform Specification major version number this BIOS supports.\r
// Any BIOS supporting version (1.22) MUST set this value to 01h.\r
// Any BIOS supporting version (2.0) SHALL set this value to 0x02.\r
//\r
- UINT8 specVersionMajor;\r
+ UINT8 specVersionMajor;\r
//\r
// The TCG EFI Platform Specification errata for this specification this BIOS supports.\r
// Any BIOS supporting version and errata (1.22) MUST set this value to 02h.\r
// Any BIOS supporting version and errata (2.0) SHALL set this value to 0x00.\r
//\r
- UINT8 specErrata;\r
+ UINT8 specErrata;\r
//\r
// Specifies the size of the UINTN fields used in various data structures used in this specification.\r
// 0x01 indicates UINT32 and 0x02 indicates UINT64.\r
//\r
- UINT8 uintnSize;\r
+ UINT8 uintnSize;\r
//\r
// This field is added in "Spec ID Event03".\r
// The number of hashing algorithms used in this event log (except the first event).\r
// All events in this event log use all hashing algorithms defined here.\r
//\r
-//UINT32 numberOfAlgorithms;\r
+ // UINT32 numberOfAlgorithms;\r
//\r
// This field is added in "Spec ID Event03".\r
// An array of size numberOfAlgorithms of value pairs.\r
//\r
-//TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];\r
+ // TCG_EfiSpecIdEventAlgorithmSize digestSize[numberOfAlgorithms];\r
//\r
// Size in bytes of the VendorInfo field.\r
// Maximum value SHALL be FFh bytes.\r
//\r
-//UINT8 vendorInfoSize;\r
+ // UINT8 vendorInfoSize;\r
//\r
// Provided for use by the BIOS implementer.\r
// The value might be used, for example, to provide more detailed information about the specific BIOS such as BIOS revision numbers, etc.\r
// The values within this field are not standardized and are implementer-specific.\r
// Platform-specific or -unique information SHALL NOT be provided in this field.\r
//\r
-//UINT8 vendorInfo[vendorInfoSize];\r
+ // UINT8 vendorInfo[vendorInfoSize];\r
} TCG_EfiSpecIDEventStruct;\r
\r
typedef struct tdTCG_PCClientTaggedEvent {\r
- UINT32 taggedEventID;\r
- UINT32 taggedEventDataSize;\r
-//UINT8 taggedEventData[taggedEventDataSize];\r
+ UINT32 taggedEventID;\r
+ UINT32 taggedEventDataSize;\r
+ // UINT8 taggedEventData[taggedEventDataSize];\r
} TCG_PCClientTaggedEvent;\r
\r
-#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event"\r
-#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"\r
+#define TCG_Sp800_155_PlatformId_Event_SIGNATURE "SP800-155 Event"\r
+#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"\r
\r
typedef struct tdTCG_Sp800_155_PlatformId_Event2 {\r
- UINT8 Signature[16];\r
+ UINT8 Signature[16];\r
//\r
// Where Vendor ID is an integer defined\r
// at http://www.iana.org/assignments/enterprisenumbers\r
//\r
- UINT32 VendorId;\r
+ UINT32 VendorId;\r
//\r
// 16-byte identifier of a given platform's static configuration of code\r
//\r
- EFI_GUID ReferenceManifestGuid;\r
+ EFI_GUID ReferenceManifestGuid;\r
//\r
// Below structure is newly added in TCG_Sp800_155_PlatformId_Event2.\r
//\r
-//UINT8 PlatformManufacturerStrSize;\r
-//UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize];\r
-//UINT8 PlatformModelSize;\r
-//UINT8 PlatformModel[PlatformModelSize];\r
-//UINT8 PlatformVersionSize;\r
-//UINT8 PlatformVersion[PlatformVersionSize];\r
-//UINT8 PlatformModelSize;\r
-//UINT8 PlatformModel[PlatformModelSize];\r
-//UINT8 FirmwareManufacturerStrSize;\r
-//UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];\r
-//UINT32 FirmwareManufacturerId;\r
-//UINT8 FirmwareVersion;\r
-//UINT8 FirmwareVersion[FirmwareVersionSize]];\r
+ // UINT8 PlatformManufacturerStrSize;\r
+ // UINT8 PlatformManufacturerStr[PlatformManufacturerStrSize];\r
+ // UINT8 PlatformModelSize;\r
+ // UINT8 PlatformModel[PlatformModelSize];\r
+ // UINT8 PlatformVersionSize;\r
+ // UINT8 PlatformVersion[PlatformVersionSize];\r
+ // UINT8 PlatformModelSize;\r
+ // UINT8 PlatformModel[PlatformModelSize];\r
+ // UINT8 FirmwareManufacturerStrSize;\r
+ // UINT8 FirmwareManufacturerStr[FirmwareManufacturerStrSize];\r
+ // UINT32 FirmwareManufacturerId;\r
+ // UINT8 FirmwareVersion;\r
+ // UINT8 FirmwareVersion[FirmwareVersionSize]];\r
} TCG_Sp800_155_PlatformId_Event2;\r
\r
-#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"\r
-\r
+#define TCG_EfiStartupLocalityEvent_SIGNATURE "StartupLocality"\r
\r
//\r
// The Locality Indicator which sent the TPM2_Startup command\r
//\r
-#define LOCALITY_0_INDICATOR 0x00\r
-#define LOCALITY_3_INDICATOR 0x03\r
+#define LOCALITY_0_INDICATOR 0x00\r
+#define LOCALITY_3_INDICATOR 0x03\r
\r
//\r
// Startup Locality Event\r
//\r
-typedef struct tdTCG_EfiStartupLocalityEvent{\r
- UINT8 Signature[16];\r
+typedef struct tdTCG_EfiStartupLocalityEvent {\r
+ UINT8 Signature[16];\r
//\r
// The Locality Indicator which sent the TPM2_Startup command\r
//\r
- UINT8 StartupLocality;\r
+ UINT8 StartupLocality;\r
} TCG_EfiStartupLocalityEvent;\r
\r
-\r
//\r
// Restore original structure alignment\r
//\r
#pragma pack ()\r
\r
#endif\r
-\r
-\r
//\r
// Usb mass storage class code\r
//\r
-#define USB_MASS_STORE_CLASS 0x08\r
+#define USB_MASS_STORE_CLASS 0x08\r
\r
//\r
// Usb mass storage subclass code, specify the command set used.\r
//\r
-#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands\r
-#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device\r
-#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device\r
-#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device\r
-#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.\r
-#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set\r
+#define USB_MASS_STORE_RBC 0x01 ///< Reduced Block Commands\r
+#define USB_MASS_STORE_8020I 0x02 ///< SFF-8020i, typically a CD/DVD device\r
+#define USB_MASS_STORE_QIC 0x03 ///< Typically a tape device\r
+#define USB_MASS_STORE_UFI 0x04 ///< Typically a floppy disk driver device\r
+#define USB_MASS_STORE_8070I 0x05 ///< SFF-8070i, typically a floppy disk driver device.\r
+#define USB_MASS_STORE_SCSI 0x06 ///< SCSI transparent command set\r
\r
//\r
// Usb mass storage protocol code, specify the transport protocol\r
//\r
-#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt\r
-#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt\r
-#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport\r
+#define USB_MASS_STORE_CBI0 0x00 ///< CBI protocol with command completion interrupt\r
+#define USB_MASS_STORE_CBI1 0x01 ///< CBI protocol without command completion interrupt\r
+#define USB_MASS_STORE_BOT 0x50 ///< Bulk-Only Transport\r
\r
//\r
// Standard device request and request type\r
// USB 2.0 spec, Section 9.4\r
//\r
-#define USB_DEV_GET_STATUS 0x00\r
-#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device\r
-#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface\r
-#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint\r
+#define USB_DEV_GET_STATUS 0x00\r
+#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device\r
+#define USB_DEV_GET_STATUS_REQ_TYPE_I 0x81 // Receiver : Interface\r
+#define USB_DEV_GET_STATUS_REQ_TYPE_E 0x82 // Receiver : Endpoint\r
\r
-#define USB_DEV_CLEAR_FEATURE 0x01\r
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device\r
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface\r
-#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint\r
+#define USB_DEV_CLEAR_FEATURE 0x01\r
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device\r
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface\r
+#define USB_DEV_CLEAR_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint\r
\r
-#define USB_DEV_SET_FEATURE 0x03\r
-#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device\r
-#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface\r
-#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint\r
+#define USB_DEV_SET_FEATURE 0x03\r
+#define USB_DEV_SET_FEATURE_REQ_TYPE_D 0x00 // Receiver : Device\r
+#define USB_DEV_SET_FEATURE_REQ_TYPE_I 0x01 // Receiver : Interface\r
+#define USB_DEV_SET_FEATURE_REQ_TYPE_E 0x02 // Receiver : Endpoint\r
\r
-#define USB_DEV_SET_ADDRESS 0x05\r
-#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00\r
+#define USB_DEV_SET_ADDRESS 0x05\r
+#define USB_DEV_SET_ADDRESS_REQ_TYPE 0x00\r
\r
-#define USB_DEV_GET_DESCRIPTOR 0x06\r
-#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80\r
+#define USB_DEV_GET_DESCRIPTOR 0x06\r
+#define USB_DEV_GET_DESCRIPTOR_REQ_TYPE 0x80\r
\r
-#define USB_DEV_SET_DESCRIPTOR 0x07\r
-#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00\r
+#define USB_DEV_SET_DESCRIPTOR 0x07\r
+#define USB_DEV_SET_DESCRIPTOR_REQ_TYPE 0x00\r
\r
#define USB_DEV_GET_CONFIGURATION 0x08\r
#define USB_DEV_GET_CONFIGURATION_REQ_TYPE 0x80\r
#define USB_DEV_SET_CONFIGURATION 0x09\r
#define USB_DEV_SET_CONFIGURATION_REQ_TYPE 0x00\r
\r
-#define USB_DEV_GET_INTERFACE 0x0A\r
-#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81\r
+#define USB_DEV_GET_INTERFACE 0x0A\r
+#define USB_DEV_GET_INTERFACE_REQ_TYPE 0x81\r
\r
-#define USB_DEV_SET_INTERFACE 0x0B\r
-#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01\r
-\r
-#define USB_DEV_SYNCH_FRAME 0x0C\r
-#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82\r
+#define USB_DEV_SET_INTERFACE 0x0B\r
+#define USB_DEV_SET_INTERFACE_REQ_TYPE 0x01\r
\r
+#define USB_DEV_SYNCH_FRAME 0x0C\r
+#define USB_DEV_SYNCH_FRAME_REQ_TYPE 0x82\r
\r
//\r
// USB standard descriptors and reqeust\r
/// USB 2.0 spec, Section 9.3\r
///\r
typedef struct {\r
- UINT8 RequestType;\r
- UINT8 Request;\r
- UINT16 Value;\r
- UINT16 Index;\r
- UINT16 Length;\r
+ UINT8 RequestType;\r
+ UINT8 Request;\r
+ UINT16 Value;\r
+ UINT16 Index;\r
+ UINT16 Length;\r
} USB_DEVICE_REQUEST;\r
\r
///\r
/// USB 2.0 spec, Section 9.6.1\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- UINT16 BcdUSB;\r
- UINT8 DeviceClass;\r
- UINT8 DeviceSubClass;\r
- UINT8 DeviceProtocol;\r
- UINT8 MaxPacketSize0;\r
- UINT16 IdVendor;\r
- UINT16 IdProduct;\r
- UINT16 BcdDevice;\r
- UINT8 StrManufacturer;\r
- UINT8 StrProduct;\r
- UINT8 StrSerialNumber;\r
- UINT8 NumConfigurations;\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 BcdUSB;\r
+ UINT8 DeviceClass;\r
+ UINT8 DeviceSubClass;\r
+ UINT8 DeviceProtocol;\r
+ UINT8 MaxPacketSize0;\r
+ UINT16 IdVendor;\r
+ UINT16 IdProduct;\r
+ UINT16 BcdDevice;\r
+ UINT8 StrManufacturer;\r
+ UINT8 StrProduct;\r
+ UINT8 StrSerialNumber;\r
+ UINT8 NumConfigurations;\r
} USB_DEVICE_DESCRIPTOR;\r
\r
///\r
/// USB 2.0 spec, Section 9.6.3\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- UINT16 TotalLength;\r
- UINT8 NumInterfaces;\r
- UINT8 ConfigurationValue;\r
- UINT8 Configuration;\r
- UINT8 Attributes;\r
- UINT8 MaxPower;\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 TotalLength;\r
+ UINT8 NumInterfaces;\r
+ UINT8 ConfigurationValue;\r
+ UINT8 Configuration;\r
+ UINT8 Attributes;\r
+ UINT8 MaxPower;\r
} USB_CONFIG_DESCRIPTOR;\r
\r
///\r
/// USB 2.0 spec, Section 9.6.5\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- UINT8 InterfaceNumber;\r
- UINT8 AlternateSetting;\r
- UINT8 NumEndpoints;\r
- UINT8 InterfaceClass;\r
- UINT8 InterfaceSubClass;\r
- UINT8 InterfaceProtocol;\r
- UINT8 Interface;\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT8 InterfaceNumber;\r
+ UINT8 AlternateSetting;\r
+ UINT8 NumEndpoints;\r
+ UINT8 InterfaceClass;\r
+ UINT8 InterfaceSubClass;\r
+ UINT8 InterfaceProtocol;\r
+ UINT8 Interface;\r
} USB_INTERFACE_DESCRIPTOR;\r
\r
///\r
/// USB 2.0 spec, Section 9.6.6\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- UINT8 EndpointAddress;\r
- UINT8 Attributes;\r
- UINT16 MaxPacketSize;\r
- UINT8 Interval;\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT8 EndpointAddress;\r
+ UINT8 Attributes;\r
+ UINT16 MaxPacketSize;\r
+ UINT8 Interval;\r
} USB_ENDPOINT_DESCRIPTOR;\r
\r
///\r
/// USB 2.0 spec, Section 9.6.7\r
///\r
typedef struct {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- CHAR16 String[1];\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ CHAR16 String[1];\r
} EFI_USB_STRING_DESCRIPTOR;\r
\r
#pragma pack()\r
\r
-\r
typedef enum {\r
//\r
// USB request type\r
//\r
- USB_REQ_TYPE_STANDARD = (0x00 << 5),\r
- USB_REQ_TYPE_CLASS = (0x01 << 5),\r
- USB_REQ_TYPE_VENDOR = (0x02 << 5),\r
+ USB_REQ_TYPE_STANDARD = (0x00 << 5),\r
+ USB_REQ_TYPE_CLASS = (0x01 << 5),\r
+ USB_REQ_TYPE_VENDOR = (0x02 << 5),\r
\r
//\r
// Standard control transfer request type, or the value\r
// to fill in EFI_USB_DEVICE_REQUEST.Request\r
//\r
- USB_REQ_GET_STATUS = 0x00,\r
- USB_REQ_CLEAR_FEATURE = 0x01,\r
- USB_REQ_SET_FEATURE = 0x03,\r
- USB_REQ_SET_ADDRESS = 0x05,\r
- USB_REQ_GET_DESCRIPTOR = 0x06,\r
- USB_REQ_SET_DESCRIPTOR = 0x07,\r
- USB_REQ_GET_CONFIG = 0x08,\r
- USB_REQ_SET_CONFIG = 0x09,\r
- USB_REQ_GET_INTERFACE = 0x0A,\r
- USB_REQ_SET_INTERFACE = 0x0B,\r
- USB_REQ_SYNCH_FRAME = 0x0C,\r
+ USB_REQ_GET_STATUS = 0x00,\r
+ USB_REQ_CLEAR_FEATURE = 0x01,\r
+ USB_REQ_SET_FEATURE = 0x03,\r
+ USB_REQ_SET_ADDRESS = 0x05,\r
+ USB_REQ_GET_DESCRIPTOR = 0x06,\r
+ USB_REQ_SET_DESCRIPTOR = 0x07,\r
+ USB_REQ_GET_CONFIG = 0x08,\r
+ USB_REQ_SET_CONFIG = 0x09,\r
+ USB_REQ_GET_INTERFACE = 0x0A,\r
+ USB_REQ_SET_INTERFACE = 0x0B,\r
+ USB_REQ_SYNCH_FRAME = 0x0C,\r
\r
//\r
// Usb control transfer target\r
//\r
- USB_TARGET_DEVICE = 0,\r
- USB_TARGET_INTERFACE = 0x01,\r
- USB_TARGET_ENDPOINT = 0x02,\r
- USB_TARGET_OTHER = 0x03,\r
+ USB_TARGET_DEVICE = 0,\r
+ USB_TARGET_INTERFACE = 0x01,\r
+ USB_TARGET_ENDPOINT = 0x02,\r
+ USB_TARGET_OTHER = 0x03,\r
\r
//\r
// USB Descriptor types\r
//\r
// USB endpoint types: 00: control, 01: isochronous, 10: bulk, 11: interrupt\r
//\r
- USB_ENDPOINT_CONTROL = 0x00,\r
- USB_ENDPOINT_ISO = 0x01,\r
- USB_ENDPOINT_BULK = 0x02,\r
- USB_ENDPOINT_INTERRUPT = 0x03,\r
+ USB_ENDPOINT_CONTROL = 0x00,\r
+ USB_ENDPOINT_ISO = 0x01,\r
+ USB_ENDPOINT_BULK = 0x02,\r
+ USB_ENDPOINT_INTERRUPT = 0x03,\r
\r
- USB_ENDPOINT_TYPE_MASK = 0x03,\r
- USB_ENDPOINT_DIR_IN = 0x80,\r
+ USB_ENDPOINT_TYPE_MASK = 0x03,\r
+ USB_ENDPOINT_DIR_IN = 0x80,\r
\r
//\r
- //Use 200 ms to increase the error handling response time\r
+ // Use 200 ms to increase the error handling response time\r
//\r
EFI_USB_INTERRUPT_DELAY = 2000000\r
} USB_TYPES_DEFINITION;\r
\r
-\r
//\r
// HID constants definition, see Device Class Definition\r
// for Human Interface Devices (HID) rev1.11\r
//\r
// HID specific requests.\r
//\r
-#define USB_HID_CLASS_GET_REQ_TYPE 0xa1\r
-#define USB_HID_CLASS_SET_REQ_TYPE 0x21\r
+#define USB_HID_CLASS_GET_REQ_TYPE 0xa1\r
+#define USB_HID_CLASS_SET_REQ_TYPE 0x21\r
\r
//\r
// HID report item format\r
//\r
-#define HID_ITEM_FORMAT_SHORT 0\r
-#define HID_ITEM_FORMAT_LONG 1\r
+#define HID_ITEM_FORMAT_SHORT 0\r
+#define HID_ITEM_FORMAT_LONG 1\r
\r
//\r
// Special tag indicating long items\r
//\r
-#define HID_ITEM_TAG_LONG 15\r
+#define HID_ITEM_TAG_LONG 15\r
\r
//\r
// HID report descriptor item type (prefix bit 2,3)\r
//\r
// HID report descriptor main item contents\r
//\r
-#define HID_MAIN_ITEM_CONSTANT 0x001\r
-#define HID_MAIN_ITEM_VARIABLE 0x002\r
-#define HID_MAIN_ITEM_RELATIVE 0x004\r
-#define HID_MAIN_ITEM_WRAP 0x008\r
-#define HID_MAIN_ITEM_NONLINEAR 0x010\r
-#define HID_MAIN_ITEM_NO_PREFERRED 0x020\r
-#define HID_MAIN_ITEM_NULL_STATE 0x040\r
-#define HID_MAIN_ITEM_VOLATILE 0x080\r
-#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100\r
+#define HID_MAIN_ITEM_CONSTANT 0x001\r
+#define HID_MAIN_ITEM_VARIABLE 0x002\r
+#define HID_MAIN_ITEM_RELATIVE 0x004\r
+#define HID_MAIN_ITEM_WRAP 0x008\r
+#define HID_MAIN_ITEM_NONLINEAR 0x010\r
+#define HID_MAIN_ITEM_NO_PREFERRED 0x020\r
+#define HID_MAIN_ITEM_NULL_STATE 0x040\r
+#define HID_MAIN_ITEM_VOLATILE 0x080\r
+#define HID_MAIN_ITEM_BUFFERED_BYTE 0x100\r
\r
//\r
// HID report descriptor collection item types\r
//\r
// HID report descriptor local item tags\r
//\r
-#define HID_LOCAL_ITEM_TAG_USAGE 0\r
-#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1\r
-#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2\r
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3\r
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4\r
-#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5\r
-#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7\r
-#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8\r
-#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9\r
-#define HID_LOCAL_ITEM_TAG_DELIMITER 10\r
+#define HID_LOCAL_ITEM_TAG_USAGE 0\r
+#define HID_LOCAL_ITEM_TAG_USAGE_MINIMUM 1\r
+#define HID_LOCAL_ITEM_TAG_USAGE_MAXIMUM 2\r
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 3\r
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MINIMUM 4\r
+#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAXIMUM 5\r
+#define HID_LOCAL_ITEM_TAG_STRING_INDEX 7\r
+#define HID_LOCAL_ITEM_TAG_STRING_MINIMUM 8\r
+#define HID_LOCAL_ITEM_TAG_STRING_MAXIMUM 9\r
+#define HID_LOCAL_ITEM_TAG_DELIMITER 10\r
\r
//\r
// HID report types\r
/// HID 1.1, section 6.2.1\r
///\r
typedef struct hid_class_descriptor {\r
- UINT8 DescriptorType;\r
- UINT16 DescriptorLength;\r
+ UINT8 DescriptorType;\r
+ UINT16 DescriptorLength;\r
} EFI_USB_HID_CLASS_DESCRIPTOR;\r
\r
///\r
/// HID 1.1, section 6.2.1\r
///\r
typedef struct hid_descriptor {\r
- UINT8 Length;\r
- UINT8 DescriptorType;\r
- UINT16 BcdHID;\r
- UINT8 CountryCode;\r
- UINT8 NumDescriptors;\r
- EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];\r
+ UINT8 Length;\r
+ UINT8 DescriptorType;\r
+ UINT16 BcdHID;\r
+ UINT8 CountryCode;\r
+ UINT8 NumDescriptors;\r
+ EFI_USB_HID_CLASS_DESCRIPTOR HidClassDesc[1];\r
} EFI_USB_HID_DESCRIPTOR;\r
\r
#pragma pack()\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
-\r
#ifndef _WATCHDOG_ACTION_TABLE_H_\r
#define _WATCHDOG_ACTION_TABLE_H_\r
\r
/// Watchdog Action Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 WatchdogHeaderLength;\r
- UINT16 PCISegment;\r
- UINT8 PCIBusNumber;\r
- UINT8 PCIDeviceNumber;\r
- UINT8 PCIFunctionNumber;\r
- UINT8 Reserved_45[3];\r
- UINT32 TimerPeriod;\r
- UINT32 MaxCount;\r
- UINT32 MinCount;\r
- UINT8 WatchdogFlags;\r
- UINT8 Reserved_61[3];\r
- UINT32 NumberWatchdogInstructionEntries;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 WatchdogHeaderLength;\r
+ UINT16 PCISegment;\r
+ UINT8 PCIBusNumber;\r
+ UINT8 PCIDeviceNumber;\r
+ UINT8 PCIFunctionNumber;\r
+ UINT8 Reserved_45[3];\r
+ UINT32 TimerPeriod;\r
+ UINT32 MaxCount;\r
+ UINT32 MinCount;\r
+ UINT8 WatchdogFlags;\r
+ UINT8 Reserved_61[3];\r
+ UINT32 NumberWatchdogInstructionEntries;\r
} EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE;\r
\r
///\r
/// Watchdog Instruction Entries\r
///\r
typedef struct {\r
- UINT8 WatchdogAction;\r
- UINT8 InstructionFlags;\r
- UINT8 Reserved_2[2];\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
- UINT32 Value;\r
- UINT32 Mask;\r
+ UINT8 WatchdogAction;\r
+ UINT8 InstructionFlags;\r
+ UINT8 Reserved_2[2];\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;\r
+ UINT32 Value;\r
+ UINT32 Mask;\r
} EFI_ACPI_WATCHDOG_ACTION_1_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY;\r
\r
#pragma pack()\r
///\r
/// WDAT Revision (defined in spec)\r
///\r
-#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION 0x01\r
+#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION 0x01\r
\r
//\r
// WDAT 1.0 Flags\r
//\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED 0x1\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED 0x1\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80\r
\r
//\r
// WDAT 1.0 Watchdog Actions\r
//\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_RESET 0x1\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD 0x5\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD 0x6\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE 0x8\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_RUNNING_STATE 0x9\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE 0xA\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_STOPPED_STATE 0xB\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_REBOOT 0x10\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_REBOOT 0x11\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_SHUTDOWN 0x12\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_SHUTDOWN 0x13\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS 0x20\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS 0x21\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_RESET 0x1\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD 0x5\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD 0x6\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE 0x8\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_RUNNING_STATE 0x9\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE 0xA\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_STOPPED_STATE 0xB\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_REBOOT 0x10\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_REBOOT 0x11\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_SHUTDOWN 0x12\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_SHUTDOWN 0x13\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS 0x20\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS 0x21\r
\r
//\r
// WDAT 1.0 Watchdog Action Entry Instruction Flags\r
//\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_VALUE 0x0\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN 0x1\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_VALUE 0x2\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN 0x3\r
-#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_VALUE 0x0\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN 0x1\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_VALUE 0x2\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN 0x3\r
+#define EFI_ACPI_WDAT_1_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80\r
\r
#endif\r
/// Watchdog Resource Table definition.\r
///\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ControlRegisterAddress;\r
- EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE CountRegisterAddress;\r
- UINT16 PCIDeviceID;\r
- UINT16 PCIVendorID;\r
- UINT8 PCIBusNumber;\r
- UINT8 PCIDeviceNumber;\r
- UINT8 PCIFunctionNumber;\r
- UINT8 PCISegment;\r
- UINT16 MaxCount;\r
- UINT8 Units;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ControlRegisterAddress;\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE CountRegisterAddress;\r
+ UINT16 PCIDeviceID;\r
+ UINT16 PCIVendorID;\r
+ UINT8 PCIBusNumber;\r
+ UINT8 PCIDeviceNumber;\r
+ UINT8 PCIFunctionNumber;\r
+ UINT8 PCISegment;\r
+ UINT16 MaxCount;\r
+ UINT8 Units;\r
} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE;\r
\r
#pragma pack()\r
//\r
// WDRT 1.0 Count Unit\r
//\r
-#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_1_SEC_PER_COUNT 1\r
-#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2\r
-#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT 3\r
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_1_SEC_PER_COUNT 1\r
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2\r
+#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT 3\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_\r
#define _WINDOWS_SMM_SECURITY_MITIGATION_TABLE_H_\r
\r
#define EFI_WSMT_TABLE_REVISION 1\r
\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 ProtectionFlags;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT32 ProtectionFlags;\r
} EFI_ACPI_WSMT_TABLE;\r
\r
-#define EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS 0x1\r
-#define EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION 0x2\r
-#define EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION 0x4\r
+#define EFI_WSMT_PROTECTION_FLAGS_FIXED_COMM_BUFFERS 0x1\r
+#define EFI_WSMT_PROTECTION_FLAGS_COMM_BUFFER_NESTED_PTR_PROTECTION 0x2\r
+#define EFI_WSMT_PROTECTION_FLAGS_SYSTEM_RESOURCE_PROTECTION 0x4\r
\r
#pragma pack()\r
\r
\r
**/\r
\r
-\r
#ifndef _WINDOWS_UX_CAPSULE_GUID_H_\r
#define _WINDOWS_UX_CAPSULE_GUID_H_\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT8 Version;\r
- UINT8 Checksum;\r
- UINT8 ImageType;\r
- UINT8 Reserved;\r
- UINT32 Mode;\r
- UINT32 OffsetX;\r
- UINT32 OffsetY;\r
- //UINT8 Image[];\r
+ UINT8 Version;\r
+ UINT8 Checksum;\r
+ UINT8 ImageType;\r
+ UINT8 Reserved;\r
+ UINT32 Mode;\r
+ UINT32 OffsetX;\r
+ UINT32 OffsetY;\r
+ // UINT8 Image[];\r
} DISPLAY_DISPLAY_PAYLOAD;\r
\r
typedef struct {\r
- EFI_CAPSULE_HEADER CapsuleHeader;\r
- DISPLAY_DISPLAY_PAYLOAD ImagePayload;\r
+ EFI_CAPSULE_HEADER CapsuleHeader;\r
+ DISPLAY_DISPLAY_PAYLOAD ImagePayload;\r
} EFI_DISPLAY_CAPSULE;\r
\r
#pragma pack()\r
0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97} \\r
}\r
\r
-extern EFI_GUID gWindowsUxCapsuleGuid;\r
+extern EFI_GUID gWindowsUxCapsuleGuid;\r
\r
#endif\r
/// The IA-32 architecture context buffer used by SetJump() and LongJump().\r
///\r
typedef struct {\r
- UINT32 Ebx;\r
- UINT32 Esi;\r
- UINT32 Edi;\r
- UINT32 Ebp;\r
- UINT32 Esp;\r
- UINT32 Eip;\r
- UINT32 Ssp;\r
+ UINT32 Ebx;\r
+ UINT32 Esi;\r
+ UINT32 Edi;\r
+ UINT32 Ebp;\r
+ UINT32 Esp;\r
+ UINT32 Eip;\r
+ UINT32 Ssp;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
\r
#endif // defined (MDE_CPU_IA32)\r
\r
/// The x64 architecture context buffer used by SetJump() and LongJump().\r
///\r
typedef struct {\r
- UINT64 Rbx;\r
- UINT64 Rsp;\r
- UINT64 Rbp;\r
- UINT64 Rdi;\r
- UINT64 Rsi;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
- UINT64 Rip;\r
- UINT64 MxCsr;\r
- UINT8 XmmBuffer[160]; ///< XMM6-XMM15.\r
- UINT64 Ssp;\r
+ UINT64 Rbx;\r
+ UINT64 Rsp;\r
+ UINT64 Rbp;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+ UINT64 Rip;\r
+ UINT64 MxCsr;\r
+ UINT8 XmmBuffer[160]; ///< XMM6-XMM15.\r
+ UINT64 Ssp;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
#endif // defined (MDE_CPU_X64)\r
\r
/// The EBC context buffer used by SetJump() and LongJump().\r
///\r
typedef struct {\r
- UINT64 R0;\r
- UINT64 R1;\r
- UINT64 R2;\r
- UINT64 R3;\r
- UINT64 IP;\r
+ UINT64 R0;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 IP;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
#endif // defined (MDE_CPU_EBC)\r
\r
UINT32 R14;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4\r
\r
-#endif // defined (MDE_CPU_ARM)\r
+#endif // defined (MDE_CPU_ARM)\r
\r
#if defined (MDE_CPU_AARCH64)\r
typedef struct {\r
UINT64 D15;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
-#endif // defined (MDE_CPU_AARCH64)\r
+#endif // defined (MDE_CPU_AARCH64)\r
\r
#if defined (MDE_CPU_RISCV64)\r
///\r
/// The RISC-V architecture context buffer used by SetJump() and LongJump().\r
///\r
typedef struct {\r
- UINT64 RA;\r
- UINT64 S0;\r
- UINT64 S1;\r
- UINT64 S2;\r
- UINT64 S3;\r
- UINT64 S4;\r
- UINT64 S5;\r
- UINT64 S6;\r
- UINT64 S7;\r
- UINT64 S8;\r
- UINT64 S9;\r
- UINT64 S10;\r
- UINT64 S11;\r
- UINT64 SP;\r
+ UINT64 RA;\r
+ UINT64 S0;\r
+ UINT64 S1;\r
+ UINT64 S2;\r
+ UINT64 S3;\r
+ UINT64 S4;\r
+ UINT64 S5;\r
+ UINT64 S6;\r
+ UINT64 S7;\r
+ UINT64 S8;\r
+ UINT64 S9;\r
+ UINT64 S10;\r
+ UINT64 S11;\r
+ UINT64 SP;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
\r
#endif // defined (MDE_CPU_RISCV64)\r
\r
// String Services\r
//\r
\r
-\r
/**\r
Returns the length of a Null-terminated Unicode string.\r
\r
UINTN\r
EFIAPI\r
StrnLenS (\r
- IN CONST CHAR16 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN MaxSize\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
StrnSizeS (\r
- IN CONST CHAR16 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN MaxSize\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrCpyS (\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrnCpyS (\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrCatS (\r
- IN OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source\r
+ IN OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrnCatS (\r
- IN OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length\r
+ IN OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrDecimalToUintnS (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrDecimalToUint64S (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrHexToUintnS (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrHexToUint64S (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
AsciiStrnLenS (\r
- IN CONST CHAR8 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN MaxSize\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
AsciiStrnSizeS (\r
- IN CONST CHAR8 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN MaxSize\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrDecimalToUintnS (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrDecimalToUint64S (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToUintnS (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToUint64S (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
);\r
\r
-\r
/**\r
Returns the length of a Null-terminated Unicode string.\r
\r
UINTN\r
EFIAPI\r
StrLen (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
-\r
/**\r
Returns the size of a Null-terminated Unicode string in bytes, including the\r
Null terminator.\r
UINTN\r
EFIAPI\r
StrSize (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
-\r
/**\r
Compares two Null-terminated Unicode strings, and returns the difference\r
between the first mismatched Unicode characters.\r
INTN\r
EFIAPI\r
StrCmp (\r
- IN CONST CHAR16 *FirstString,\r
- IN CONST CHAR16 *SecondString\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString\r
);\r
\r
-\r
/**\r
Compares up to a specified length the contents of two Null-terminated Unicode strings,\r
and returns the difference between the first mismatched Unicode characters.\r
INTN\r
EFIAPI\r
StrnCmp (\r
- IN CONST CHAR16 *FirstString,\r
- IN CONST CHAR16 *SecondString,\r
- IN UINTN Length\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the first occurrence of a Null-terminated Unicode sub-string\r
in a Null-terminated Unicode string.\r
CHAR16 *\r
EFIAPI\r
StrStr (\r
- IN CONST CHAR16 *String,\r
- IN CONST CHAR16 *SearchString\r
+ IN CONST CHAR16 *String,\r
+ IN CONST CHAR16 *SearchString\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
StrDecimalToUintn (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
StrDecimalToUint64 (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
-\r
/**\r
Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.\r
\r
UINTN\r
EFIAPI\r
StrHexToUintn (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
-\r
/**\r
Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.\r
\r
UINT64\r
EFIAPI\r
StrHexToUint64 (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrToIpv6Address (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT IPv6_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT IPv6_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrToIpv4Address (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT IPv4_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT IPv4_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
);\r
\r
#define GUID_STRING_LENGTH 36\r
RETURN_STATUS\r
EFIAPI\r
StrToGuid (\r
- IN CONST CHAR16 *String,\r
- OUT GUID *Guid\r
+ IN CONST CHAR16 *String,\r
+ OUT GUID *Guid\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
StrHexToBytes (\r
- IN CONST CHAR16 *String,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer,\r
- IN UINTN MaxBufferSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN MaxBufferSize\r
);\r
\r
-\r
/**\r
Convert a Null-terminated Unicode string to a Null-terminated\r
ASCII string.\r
RETURN_STATUS\r
EFIAPI\r
UnicodeStrToAsciiStrS (\r
- IN CONST CHAR16 *Source,\r
- OUT CHAR8 *Destination,\r
- IN UINTN DestMax\r
+ IN CONST CHAR16 *Source,\r
+ OUT CHAR8 *Destination,\r
+ IN UINTN DestMax\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
UnicodeStrnToAsciiStrS (\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length,\r
- OUT CHAR8 *Destination,\r
- IN UINTN DestMax,\r
- OUT UINTN *DestinationLength\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length,\r
+ OUT CHAR8 *Destination,\r
+ IN UINTN DestMax,\r
+ OUT UINTN *DestinationLength\r
);\r
\r
-\r
/**\r
Returns the length of a Null-terminated ASCII string.\r
\r
UINTN\r
EFIAPI\r
AsciiStrLen (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
-\r
/**\r
Returns the size of a Null-terminated ASCII string in bytes, including the\r
Null terminator.\r
UINTN\r
EFIAPI\r
AsciiStrSize (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
-\r
/**\r
Compares two Null-terminated ASCII strings, and returns the difference\r
between the first mismatched ASCII characters.\r
INTN\r
EFIAPI\r
AsciiStrCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
);\r
\r
-\r
/**\r
Performs a case insensitive comparison of two Null-terminated ASCII strings,\r
and returns the difference between the first mismatched ASCII characters.\r
INTN\r
EFIAPI\r
AsciiStriCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
);\r
\r
-\r
/**\r
Compares two Null-terminated ASCII strings with maximum lengths, and returns\r
the difference between the first mismatched ASCII characters.\r
INTN\r
EFIAPI\r
AsciiStrnCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString,\r
- IN UINTN Length\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the first occurrence of a Null-terminated ASCII sub-string\r
in a Null-terminated ASCII string.\r
CHAR8 *\r
EFIAPI\r
AsciiStrStr (\r
- IN CONST CHAR8 *String,\r
- IN CONST CHAR8 *SearchString\r
+ IN CONST CHAR8 *String,\r
+ IN CONST CHAR8 *SearchString\r
);\r
\r
-\r
/**\r
Convert a Null-terminated ASCII decimal string to a value of type\r
UINTN.\r
UINTN\r
EFIAPI\r
AsciiStrDecimalToUintn (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
-\r
/**\r
Convert a Null-terminated ASCII decimal string to a value of type\r
UINT64.\r
UINT64\r
EFIAPI\r
AsciiStrDecimalToUint64 (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
-\r
/**\r
Convert a Null-terminated ASCII hexadecimal string to a value of type UINTN.\r
\r
UINTN\r
EFIAPI\r
AsciiStrHexToUintn (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
-\r
/**\r
Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.\r
\r
UINT64\r
EFIAPI\r
AsciiStrHexToUint64 (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToIpv6Address (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT IPv6_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT IPv6_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToIpv4Address (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT IPv4_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT IPv4_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToGuid (\r
- IN CONST CHAR8 *String,\r
- OUT GUID *Guid\r
+ IN CONST CHAR8 *String,\r
+ OUT GUID *Guid\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToBytes (\r
- IN CONST CHAR8 *String,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer,\r
- IN UINTN MaxBufferSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN MaxBufferSize\r
);\r
\r
-\r
/**\r
Convert one Null-terminated ASCII string to a Null-terminated\r
Unicode string.\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToUnicodeStrS (\r
- IN CONST CHAR8 *Source,\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax\r
+ IN CONST CHAR8 *Source,\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrnToUnicodeStrS (\r
- IN CONST CHAR8 *Source,\r
- IN UINTN Length,\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- OUT UINTN *DestinationLength\r
+ IN CONST CHAR8 *Source,\r
+ IN UINTN Length,\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ OUT UINTN *DestinationLength\r
);\r
\r
/**\r
CHAR16\r
EFIAPI\r
CharToUpper (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
);\r
\r
/**\r
CHAR8\r
EFIAPI\r
AsciiCharToUpper (\r
- IN CHAR8 Chr\r
+ IN CHAR8 Chr\r
);\r
\r
/**\r
EFIAPI\r
Base64Encode (\r
IN CONST UINT8 *Source,\r
- IN UINTN SourceLength,\r
+ IN UINTN SourceLength,\r
OUT CHAR8 *Destination OPTIONAL,\r
IN OUT UINTN *DestinationSize\r
);\r
RETURN_STATUS\r
EFIAPI\r
Base64Decode (\r
- IN CONST CHAR8 *Source OPTIONAL,\r
- IN UINTN SourceSize,\r
- OUT UINT8 *Destination OPTIONAL,\r
- IN OUT UINTN *DestinationSize\r
+ IN CONST CHAR8 *Source OPTIONAL,\r
+ IN UINTN SourceSize,\r
+ OUT UINT8 *Destination OPTIONAL,\r
+ IN OUT UINTN *DestinationSize\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
DecimalToBcd8 (\r
- IN UINT8 Value\r
+ IN UINT8 Value\r
);\r
\r
-\r
/**\r
Converts an 8-bit BCD value to an 8-bit value.\r
\r
UINT8\r
EFIAPI\r
BcdToDecimal8 (\r
- IN UINT8 Value\r
+ IN UINT8 Value\r
);\r
\r
//\r
**/\r
BOOLEAN\r
EFIAPI\r
-PathRemoveLastItem(\r
- IN OUT CHAR16 *Path\r
+PathRemoveLastItem (\r
+ IN OUT CHAR16 *Path\r
);\r
\r
/**\r
\r
@return Returns Path, otherwise returns NULL to indicate that an error has occurred.\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
-PathCleanUpDirectories(\r
- IN CHAR16 *Path\r
+PathCleanUpDirectories (\r
+ IN CHAR16 *Path\r
);\r
\r
//\r
BOOLEAN\r
EFIAPI\r
IsNodeInList (\r
- IN CONST LIST_ENTRY *FirstEntry,\r
- IN CONST LIST_ENTRY *SecondEntry\r
+ IN CONST LIST_ENTRY *FirstEntry,\r
+ IN CONST LIST_ENTRY *SecondEntry\r
);\r
\r
-\r
/**\r
Initializes the head node of a doubly linked list, and returns the pointer to\r
the head node of the doubly linked list.\r
LIST_ENTRY *\r
EFIAPI\r
InitializeListHead (\r
- IN OUT LIST_ENTRY *ListHead\r
+ IN OUT LIST_ENTRY *ListHead\r
);\r
\r
-\r
/**\r
Adds a node to the beginning of a doubly linked list, and returns the pointer\r
to the head node of the doubly linked list.\r
LIST_ENTRY *\r
EFIAPI\r
InsertHeadList (\r
- IN OUT LIST_ENTRY *ListHead,\r
- IN OUT LIST_ENTRY *Entry\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
);\r
\r
-\r
/**\r
Adds a node to the end of a doubly linked list, and returns the pointer to\r
the head node of the doubly linked list.\r
LIST_ENTRY *\r
EFIAPI\r
InsertTailList (\r
- IN OUT LIST_ENTRY *ListHead,\r
- IN OUT LIST_ENTRY *Entry\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
);\r
\r
-\r
/**\r
Retrieves the first node of a doubly linked list.\r
\r
LIST_ENTRY *\r
EFIAPI\r
GetFirstNode (\r
- IN CONST LIST_ENTRY *List\r
+ IN CONST LIST_ENTRY *List\r
);\r
\r
-\r
/**\r
Retrieves the next node of a doubly linked list.\r
\r
LIST_ENTRY *\r
EFIAPI\r
GetNextNode (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
);\r
\r
-\r
/**\r
Retrieves the previous node of a doubly linked list.\r
\r
LIST_ENTRY *\r
EFIAPI\r
GetPreviousNode (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
);\r
\r
-\r
/**\r
Checks to see if a doubly linked list is empty or not.\r
\r
BOOLEAN\r
EFIAPI\r
IsListEmpty (\r
- IN CONST LIST_ENTRY *ListHead\r
+ IN CONST LIST_ENTRY *ListHead\r
);\r
\r
-\r
/**\r
Determines if a node in a doubly linked list is the head node of a the same\r
doubly linked list. This function is typically used to terminate a loop that\r
BOOLEAN\r
EFIAPI\r
IsNull (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
);\r
\r
-\r
/**\r
Determines if a node the last node in a doubly linked list.\r
\r
BOOLEAN\r
EFIAPI\r
IsNodeAtEnd (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
);\r
\r
-\r
/**\r
Swaps the location of two nodes in a doubly linked list, and returns the\r
first node after the swap.\r
LIST_ENTRY *\r
EFIAPI\r
SwapListEntries (\r
- IN OUT LIST_ENTRY *FirstEntry,\r
- IN OUT LIST_ENTRY *SecondEntry\r
+ IN OUT LIST_ENTRY *FirstEntry,\r
+ IN OUT LIST_ENTRY *SecondEntry\r
);\r
\r
-\r
/**\r
Removes a node from a doubly linked list, and returns the node that follows\r
the removed node.\r
LIST_ENTRY *\r
EFIAPI\r
RemoveEntryList (\r
- IN CONST LIST_ENTRY *Entry\r
+ IN CONST LIST_ENTRY *Entry\r
);\r
\r
//\r
// Math Services\r
//\r
+\r
/**\r
Prototype for comparison function for any two element types.\r
\r
VOID\r
EFIAPI\r
QuickSort (\r
- IN OUT VOID *BufferToSort,\r
- IN CONST UINTN Count,\r
- IN CONST UINTN ElementSize,\r
- IN BASE_SORT_COMPARE CompareFunction,\r
- OUT VOID *BufferOneElement\r
+ IN OUT VOID *BufferToSort,\r
+ IN CONST UINTN Count,\r
+ IN CONST UINTN ElementSize,\r
+ IN BASE_SORT_COMPARE CompareFunction,\r
+ OUT VOID *BufferOneElement\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
LShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Shifts a 64-bit integer right between 0 and 63 bits. This high bits are\r
filled with zeros. The shifted value is returned.\r
UINT64\r
EFIAPI\r
RShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Shifts a 64-bit integer right between 0 and 63 bits. The high bits are filled\r
with original integer's bit 63. The shifted value is returned.\r
UINT64\r
EFIAPI\r
ARShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Rotates a 32-bit integer left between 0 and 31 bits, filling the low bits\r
with the high bits that were rotated.\r
UINT32\r
EFIAPI\r
LRotU32 (\r
- IN UINT32 Operand,\r
- IN UINTN Count\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Rotates a 32-bit integer right between 0 and 31 bits, filling the high bits\r
with the low bits that were rotated.\r
UINT32\r
EFIAPI\r
RRotU32 (\r
- IN UINT32 Operand,\r
- IN UINTN Count\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Rotates a 64-bit integer left between 0 and 63 bits, filling the low bits\r
with the high bits that were rotated.\r
UINT64\r
EFIAPI\r
LRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Rotates a 64-bit integer right between 0 and 63 bits, filling the high bits\r
with the high low bits that were rotated.\r
UINT64\r
EFIAPI\r
RRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
-\r
/**\r
Returns the bit position of the lowest bit set in a 32-bit value.\r
\r
INTN\r
EFIAPI\r
LowBitSet32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
);\r
\r
-\r
/**\r
Returns the bit position of the lowest bit set in a 64-bit value.\r
\r
INTN\r
EFIAPI\r
LowBitSet64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
);\r
\r
-\r
/**\r
Returns the bit position of the highest bit set in a 32-bit value. Equivalent\r
to log2(x).\r
INTN\r
EFIAPI\r
HighBitSet32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
);\r
\r
-\r
/**\r
Returns the bit position of the highest bit set in a 64-bit value. Equivalent\r
to log2(x).\r
INTN\r
EFIAPI\r
HighBitSet64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
);\r
\r
-\r
/**\r
Returns the value of the highest bit set in a 32-bit value. Equivalent to\r
1 << log2(x).\r
UINT32\r
EFIAPI\r
GetPowerOfTwo32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
);\r
\r
-\r
/**\r
Returns the value of the highest bit set in a 64-bit value. Equivalent to\r
1 << log2(x).\r
UINT64\r
EFIAPI\r
GetPowerOfTwo64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
);\r
\r
-\r
/**\r
Switches the endianness of a 16-bit integer.\r
\r
UINT16\r
EFIAPI\r
SwapBytes16 (\r
- IN UINT16 Value\r
+ IN UINT16 Value\r
);\r
\r
-\r
/**\r
Switches the endianness of a 32-bit integer.\r
\r
UINT32\r
EFIAPI\r
SwapBytes32 (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Switches the endianness of a 64-bit integer.\r
\r
UINT64\r
EFIAPI\r
SwapBytes64 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Multiples a 64-bit unsigned integer by a 32-bit unsigned integer and\r
generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
MultU64x32 (\r
- IN UINT64 Multiplicand,\r
- IN UINT32 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
);\r
\r
-\r
/**\r
Multiples a 64-bit unsigned integer by a 64-bit unsigned integer and\r
generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
MultU64x64 (\r
- IN UINT64 Multiplicand,\r
- IN UINT64 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
);\r
\r
-\r
/**\r
Multiples a 64-bit signed integer by a 64-bit signed integer and generates a\r
64-bit signed result.\r
INT64\r
EFIAPI\r
MultS64x64 (\r
- IN INT64 Multiplicand,\r
- IN INT64 Multiplier\r
+ IN INT64 Multiplicand,\r
+ IN INT64 Multiplier\r
);\r
\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
DivU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
);\r
\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
a 32-bit unsigned remainder.\r
UINT32\r
EFIAPI\r
ModU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
);\r
\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and generates\r
a 64-bit unsigned result and an optional 32-bit unsigned remainder.\r
UINT64\r
EFIAPI\r
DivU64x32Remainder (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor,\r
- OUT UINT32 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
);\r
\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 64-bit unsigned integer and generates\r
a 64-bit unsigned result and an optional 64-bit unsigned remainder.\r
UINT64\r
EFIAPI\r
DivU64x64Remainder (\r
- IN UINT64 Dividend,\r
- IN UINT64 Divisor,\r
- OUT UINT64 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
);\r
\r
-\r
/**\r
Divides a 64-bit signed integer by a 64-bit signed integer and generates a\r
64-bit signed result and a optional 64-bit signed remainder.\r
INT64\r
EFIAPI\r
DivS64x64Remainder (\r
- IN INT64 Dividend,\r
- IN INT64 Divisor,\r
- OUT INT64 *Remainder OPTIONAL\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
);\r
\r
-\r
/**\r
Reads a 16-bit value from memory that may be unaligned.\r
\r
UINT16\r
EFIAPI\r
ReadUnaligned16 (\r
- IN CONST UINT16 *Buffer\r
+ IN CONST UINT16 *Buffer\r
);\r
\r
-\r
/**\r
Writes a 16-bit value to memory that may be unaligned.\r
\r
UINT16\r
EFIAPI\r
WriteUnaligned16 (\r
- OUT UINT16 *Buffer,\r
- IN UINT16 Value\r
+ OUT UINT16 *Buffer,\r
+ IN UINT16 Value\r
);\r
\r
-\r
/**\r
Reads a 24-bit value from memory that may be unaligned.\r
\r
UINT32\r
EFIAPI\r
ReadUnaligned24 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
);\r
\r
-\r
/**\r
Writes a 24-bit value to memory that may be unaligned.\r
\r
UINT32\r
EFIAPI\r
WriteUnaligned24 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Reads a 32-bit value from memory that may be unaligned.\r
\r
UINT32\r
EFIAPI\r
ReadUnaligned32 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
);\r
\r
-\r
/**\r
Writes a 32-bit value to memory that may be unaligned.\r
\r
UINT32\r
EFIAPI\r
WriteUnaligned32 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Reads a 64-bit value from memory that may be unaligned.\r
\r
UINT64\r
EFIAPI\r
ReadUnaligned64 (\r
- IN CONST UINT64 *Buffer\r
+ IN CONST UINT64 *Buffer\r
);\r
\r
-\r
/**\r
Writes a 64-bit value to memory that may be unaligned.\r
\r
UINT64\r
EFIAPI\r
WriteUnaligned64 (\r
- OUT UINT64 *Buffer,\r
- IN UINT64 Value\r
+ OUT UINT64 *Buffer,\r
+ IN UINT64 Value\r
);\r
\r
-\r
//\r
// Bit Field Functions\r
//\r
UINT8\r
EFIAPI\r
BitFieldRead8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to an 8-bit value, and returns the result.\r
\r
UINT8\r
EFIAPI\r
BitFieldWrite8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
-\r
/**\r
Reads a bit field from an 8-bit value, performs a bitwise OR, and returns the\r
result.\r
UINT8\r
EFIAPI\r
BitFieldOr8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field from an 8-bit value, performs a bitwise AND, and returns\r
the result.\r
UINT8\r
EFIAPI\r
BitFieldAnd8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field from an 8-bit value, performs a bitwise AND followed by a\r
bitwise OR, and returns the result.\r
UINT8\r
EFIAPI\r
BitFieldAndThenOr8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
-\r
/**\r
Returns a bit field from a 16-bit value.\r
\r
UINT16\r
EFIAPI\r
BitFieldRead16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to a 16-bit value, and returns the result.\r
\r
UINT16\r
EFIAPI\r
BitFieldWrite16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
-\r
/**\r
Reads a bit field from a 16-bit value, performs a bitwise OR, and returns the\r
result.\r
UINT16\r
EFIAPI\r
BitFieldOr16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 16-bit value, performs a bitwise AND, and returns\r
the result.\r
UINT16\r
EFIAPI\r
BitFieldAnd16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 16-bit value, performs a bitwise AND followed by a\r
bitwise OR, and returns the result.\r
UINT16\r
EFIAPI\r
BitFieldAndThenOr16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
-\r
/**\r
Returns a bit field from a 32-bit value.\r
\r
UINT32\r
EFIAPI\r
BitFieldRead32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to a 32-bit value, and returns the result.\r
\r
UINT32\r
EFIAPI\r
BitFieldWrite32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Reads a bit field from a 32-bit value, performs a bitwise OR, and returns the\r
result.\r
UINT32\r
EFIAPI\r
BitFieldOr32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 32-bit value, performs a bitwise AND, and returns\r
the result.\r
UINT32\r
EFIAPI\r
BitFieldAnd32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 32-bit value, performs a bitwise AND followed by a\r
bitwise OR, and returns the result.\r
UINT32\r
EFIAPI\r
BitFieldAndThenOr32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Returns a bit field from a 64-bit value.\r
\r
UINT64\r
EFIAPI\r
BitFieldRead64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to a 64-bit value, and returns the result.\r
\r
UINT64\r
EFIAPI\r
BitFieldWrite64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Reads a bit field from a 64-bit value, performs a bitwise OR, and returns the\r
result.\r
UINT64\r
EFIAPI\r
BitFieldOr64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 64-bit value, performs a bitwise AND, and returns\r
the result.\r
UINT64\r
EFIAPI\r
BitFieldAnd64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field from a 64-bit value, performs a bitwise AND followed by a\r
bitwise OR, and returns the result.\r
UINT64\r
EFIAPI\r
BitFieldAndThenOr64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
BitFieldCountOnes32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
BitFieldCountOnes64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
//\r
UINT8\r
EFIAPI\r
CalculateSum8 (\r
- IN CONST UINT8 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer\r
of 8-bit values.\r
UINT8\r
EFIAPI\r
CalculateCheckSum8 (\r
- IN CONST UINT8 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the sum of all elements in a buffer of 16-bit values. During\r
calculation, the carry bits are dropped.\r
UINT16\r
EFIAPI\r
CalculateSum16 (\r
- IN CONST UINT16 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
16-bit values.\r
UINT16\r
EFIAPI\r
CalculateCheckSum16 (\r
- IN CONST UINT16 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the sum of all elements in a buffer of 32-bit values. During\r
calculation, the carry bits are dropped.\r
UINT32\r
EFIAPI\r
CalculateSum32 (\r
- IN CONST UINT32 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
32-bit values.\r
UINT32\r
EFIAPI\r
CalculateCheckSum32 (\r
- IN CONST UINT32 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the sum of all elements in a buffer of 64-bit values. During\r
calculation, the carry bits are dropped.\r
UINT64\r
EFIAPI\r
CalculateSum64 (\r
- IN CONST UINT64 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
64-bit values.\r
UINT64\r
EFIAPI\r
CalculateCheckSum64 (\r
- IN CONST UINT64 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
**/\r
UINT32\r
EFIAPI\r
-CalculateCrc32(\r
- IN VOID *Buffer,\r
- IN UINTN Length\r
+CalculateCrc32 (\r
+ IN VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
//\r
IN VOID *Context2 OPTIONAL\r
);\r
\r
-\r
/**\r
Used to serialize load and store operations.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Saves the current CPU context that can be restored with a call to LongJump()\r
and returns 0.\r
OUT BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
);\r
\r
-\r
/**\r
Restores the CPU context that was saved with SetJump().\r
\r
IN UINTN Value\r
);\r
\r
-\r
/**\r
Enables CPU interrupts.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Disables CPU interrupts.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Disables CPU interrupts and returns the interrupt state prior to the disable\r
operation.\r
VOID\r
);\r
\r
-\r
/**\r
Enables CPU interrupts for the smallest window required to capture any\r
pending interrupts.\r
VOID\r
);\r
\r
-\r
/**\r
Retrieves the current CPU interrupt state.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Set the current CPU interrupt state.\r
\r
BOOLEAN\r
EFIAPI\r
SetInterruptState (\r
- IN BOOLEAN InterruptState\r
+ IN BOOLEAN InterruptState\r
);\r
\r
-\r
/**\r
Requests CPU to pause for a short period of time.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Transfers control to a function starting with a new stack.\r
\r
...\r
);\r
\r
-\r
/**\r
Generates a breakpoint on the CPU.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Executes an infinite loop.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Uses as a barrier to stop speculative execution.\r
\r
//\r
// PVALIDATE Return Code.\r
//\r
-#define PVALIDATE_RET_SUCCESS 0\r
-#define PVALIDATE_RET_FAIL_INPUT 1\r
-#define PVALIDATE_RET_SIZE_MISMATCH 6\r
+#define PVALIDATE_RET_SUCCESS 0\r
+#define PVALIDATE_RET_FAIL_INPUT 1\r
+#define PVALIDATE_RET_SIZE_MISMATCH 6\r
\r
//\r
// The PVALIDATE instruction did not make any changes to the RMP entry.\r
//\r
-#define PVALIDATE_RET_NO_RMPUPDATE 255\r
+#define PVALIDATE_RET_NO_RMPUPDATE 255\r
\r
/**\r
Execute a PVALIDATE instruction to validate or to rescinds validation of a guest\r
UINT32\r
EFIAPI\r
AsmPvalidate (\r
- IN PVALIDATE_PAGE_SIZE PageSize,\r
- IN BOOLEAN Validate,\r
- IN PHYSICAL_ADDRESS Address\r
+ IN PVALIDATE_PAGE_SIZE PageSize,\r
+ IN BOOLEAN Validate,\r
+ IN PHYSICAL_ADDRESS Address\r
);\r
\r
//\r
UINT32\r
EFIAPI\r
AsmRmpAdjust (\r
- IN UINT64 Rax,\r
- IN UINT64 Rcx,\r
- IN UINT64 Rdx\r
+ IN UINT64 Rax,\r
+ IN UINT64 Rcx,\r
+ IN UINT64 Rdx\r
);\r
-#endif\r
\r
+#endif\r
\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
+ UINT32 CF : 1; ///< Carry Flag.\r
+ UINT32 Reserved_0 : 1; ///< Reserved.\r
+ UINT32 PF : 1; ///< Parity Flag.\r
+ UINT32 Reserved_1 : 1; ///< Reserved.\r
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2 : 1; ///< Reserved.\r
+ UINT32 ZF : 1; ///< Zero Flag.\r
+ UINT32 SF : 1; ///< Sign Flag.\r
+ UINT32 TF : 1; ///< Trap Flag.\r
+ UINT32 IF : 1; ///< Interrupt Enable Flag.\r
+ UINT32 DF : 1; ///< Direction Flag.\r
+ UINT32 OF : 1; ///< Overflow Flag.\r
+ UINT32 IOPL : 2; ///< I/O Privilege Level.\r
+ UINT32 NT : 1; ///< Nested Task.\r
+ UINT32 Reserved_3 : 1; ///< Reserved.\r
} Bits;\r
UINT16 Uint16;\r
} IA32_FLAGS16;\r
///\r
typedef union {\r
struct {\r
- UINT32 CF:1; ///< Carry Flag.\r
- UINT32 Reserved_0:1; ///< Reserved.\r
- UINT32 PF:1; ///< Parity Flag.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AF:1; ///< Auxiliary Carry Flag.\r
- UINT32 Reserved_2:1; ///< Reserved.\r
- UINT32 ZF:1; ///< Zero Flag.\r
- UINT32 SF:1; ///< Sign Flag.\r
- UINT32 TF:1; ///< Trap Flag.\r
- UINT32 IF:1; ///< Interrupt Enable Flag.\r
- UINT32 DF:1; ///< Direction Flag.\r
- UINT32 OF:1; ///< Overflow Flag.\r
- UINT32 IOPL:2; ///< I/O Privilege Level.\r
- UINT32 NT:1; ///< Nested Task.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- UINT32 RF:1; ///< Resume Flag.\r
- UINT32 VM:1; ///< Virtual 8086 Mode.\r
- UINT32 AC:1; ///< Alignment Check.\r
- UINT32 VIF:1; ///< Virtual Interrupt Flag.\r
- UINT32 VIP:1; ///< Virtual Interrupt Pending.\r
- UINT32 ID:1; ///< ID Flag.\r
- UINT32 Reserved_4:10; ///< Reserved.\r
+ UINT32 CF : 1; ///< Carry Flag.\r
+ UINT32 Reserved_0 : 1; ///< Reserved.\r
+ UINT32 PF : 1; ///< Parity Flag.\r
+ UINT32 Reserved_1 : 1; ///< Reserved.\r
+ UINT32 AF : 1; ///< Auxiliary Carry Flag.\r
+ UINT32 Reserved_2 : 1; ///< Reserved.\r
+ UINT32 ZF : 1; ///< Zero Flag.\r
+ UINT32 SF : 1; ///< Sign Flag.\r
+ UINT32 TF : 1; ///< Trap Flag.\r
+ UINT32 IF : 1; ///< Interrupt Enable Flag.\r
+ UINT32 DF : 1; ///< Direction Flag.\r
+ UINT32 OF : 1; ///< Overflow Flag.\r
+ UINT32 IOPL : 2; ///< I/O Privilege Level.\r
+ UINT32 NT : 1; ///< Nested Task.\r
+ UINT32 Reserved_3 : 1; ///< Reserved.\r
+ UINT32 RF : 1; ///< Resume Flag.\r
+ UINT32 VM : 1; ///< Virtual 8086 Mode.\r
+ UINT32 AC : 1; ///< Alignment Check.\r
+ UINT32 VIF : 1; ///< Virtual Interrupt Flag.\r
+ UINT32 VIP : 1; ///< Virtual Interrupt Pending.\r
+ UINT32 ID : 1; ///< ID Flag.\r
+ UINT32 Reserved_4 : 10; ///< Reserved.\r
} Bits;\r
- UINTN UintN;\r
+ UINTN UintN;\r
} IA32_EFLAGS32;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 PE:1; ///< Protection Enable.\r
- UINT32 MP:1; ///< Monitor Coprocessor.\r
- UINT32 EM:1; ///< Emulation.\r
- UINT32 TS:1; ///< Task Switched.\r
- UINT32 ET:1; ///< Extension Type.\r
- UINT32 NE:1; ///< Numeric Error.\r
- UINT32 Reserved_0:10; ///< Reserved.\r
- UINT32 WP:1; ///< Write Protect.\r
- UINT32 Reserved_1:1; ///< Reserved.\r
- UINT32 AM:1; ///< Alignment Mask.\r
- UINT32 Reserved_2:10; ///< Reserved.\r
- UINT32 NW:1; ///< Mot Write-through.\r
- UINT32 CD:1; ///< Cache Disable.\r
- UINT32 PG:1; ///< Paging.\r
+ UINT32 PE : 1; ///< Protection Enable.\r
+ UINT32 MP : 1; ///< Monitor Coprocessor.\r
+ UINT32 EM : 1; ///< Emulation.\r
+ UINT32 TS : 1; ///< Task Switched.\r
+ UINT32 ET : 1; ///< Extension Type.\r
+ UINT32 NE : 1; ///< Numeric Error.\r
+ UINT32 Reserved_0 : 10; ///< Reserved.\r
+ UINT32 WP : 1; ///< Write Protect.\r
+ UINT32 Reserved_1 : 1; ///< Reserved.\r
+ UINT32 AM : 1; ///< Alignment Mask.\r
+ UINT32 Reserved_2 : 10; ///< Reserved.\r
+ UINT32 NW : 1; ///< Mot Write-through.\r
+ UINT32 CD : 1; ///< Cache Disable.\r
+ UINT32 PG : 1; ///< Paging.\r
} Bits;\r
- UINTN UintN;\r
+ UINTN UintN;\r
} IA32_CR0;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 VME:1; ///< Virtual-8086 Mode Extensions.\r
- UINT32 PVI:1; ///< Protected-Mode Virtual Interrupts.\r
- UINT32 TSD:1; ///< Time Stamp Disable.\r
- UINT32 DE:1; ///< Debugging Extensions.\r
- UINT32 PSE:1; ///< Page Size Extensions.\r
- UINT32 PAE:1; ///< Physical Address Extension.\r
- UINT32 MCE:1; ///< Machine Check Enable.\r
- UINT32 PGE:1; ///< Page Global Enable.\r
- UINT32 PCE:1; ///< Performance Monitoring Counter\r
- ///< Enable.\r
- UINT32 OSFXSR:1; ///< Operating System Support for\r
- ///< FXSAVE and FXRSTOR instructions\r
- UINT32 OSXMMEXCPT:1; ///< Operating System Support for\r
- ///< Unmasked SIMD Floating Point\r
- ///< Exceptions.\r
- UINT32 UMIP:1; ///< User-Mode Instruction Prevention.\r
- UINT32 LA57:1; ///< Linear Address 57bit.\r
- UINT32 VMXE:1; ///< VMX Enable.\r
- UINT32 SMXE:1; ///< SMX Enable.\r
- UINT32 Reserved_3:1; ///< Reserved.\r
- UINT32 FSGSBASE:1; ///< FSGSBASE Enable.\r
- UINT32 PCIDE:1; ///< PCID Enable.\r
- UINT32 OSXSAVE:1; ///< XSAVE and Processor Extended States Enable.\r
- UINT32 Reserved_4:1; ///< Reserved.\r
- UINT32 SMEP:1; ///< SMEP Enable.\r
- UINT32 SMAP:1; ///< SMAP Enable.\r
- UINT32 PKE:1; ///< Protection-Key Enable.\r
- UINT32 Reserved_5:9; ///< Reserved.\r
+ UINT32 VME : 1; ///< Virtual-8086 Mode Extensions.\r
+ UINT32 PVI : 1; ///< Protected-Mode Virtual Interrupts.\r
+ UINT32 TSD : 1; ///< Time Stamp Disable.\r
+ UINT32 DE : 1; ///< Debugging Extensions.\r
+ UINT32 PSE : 1; ///< Page Size Extensions.\r
+ UINT32 PAE : 1; ///< Physical Address Extension.\r
+ UINT32 MCE : 1; ///< Machine Check Enable.\r
+ UINT32 PGE : 1; ///< Page Global Enable.\r
+ UINT32 PCE : 1; ///< Performance Monitoring Counter\r
+ ///< Enable.\r
+ UINT32 OSFXSR : 1; ///< Operating System Support for\r
+ ///< FXSAVE and FXRSTOR instructions\r
+ UINT32 OSXMMEXCPT : 1; ///< Operating System Support for\r
+ ///< Unmasked SIMD Floating Point\r
+ ///< Exceptions.\r
+ UINT32 UMIP : 1; ///< User-Mode Instruction Prevention.\r
+ UINT32 LA57 : 1; ///< Linear Address 57bit.\r
+ UINT32 VMXE : 1; ///< VMX Enable.\r
+ UINT32 SMXE : 1; ///< SMX Enable.\r
+ UINT32 Reserved_3 : 1; ///< Reserved.\r
+ UINT32 FSGSBASE : 1; ///< FSGSBASE Enable.\r
+ UINT32 PCIDE : 1; ///< PCID Enable.\r
+ UINT32 OSXSAVE : 1; ///< XSAVE and Processor Extended States Enable.\r
+ UINT32 Reserved_4 : 1; ///< Reserved.\r
+ UINT32 SMEP : 1; ///< SMEP Enable.\r
+ UINT32 SMAP : 1; ///< SMAP Enable.\r
+ UINT32 PKE : 1; ///< Protection-Key Enable.\r
+ UINT32 Reserved_5 : 9; ///< Reserved.\r
} Bits;\r
- UINTN UintN;\r
+ UINTN UintN;\r
} IA32_CR4;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 LimitLow:16;\r
- UINT32 BaseLow:16;\r
- UINT32 BaseMid:8;\r
- UINT32 Type:4;\r
- UINT32 S:1;\r
- UINT32 DPL:2;\r
- UINT32 P:1;\r
- UINT32 LimitHigh:4;\r
- UINT32 AVL:1;\r
- UINT32 L:1;\r
- UINT32 DB:1;\r
- UINT32 G:1;\r
- UINT32 BaseHigh:8;\r
+ UINT32 LimitLow : 16;\r
+ UINT32 BaseLow : 16;\r
+ UINT32 BaseMid : 8;\r
+ UINT32 Type : 4;\r
+ UINT32 S : 1;\r
+ UINT32 DPL : 2;\r
+ UINT32 P : 1;\r
+ UINT32 LimitHigh : 4;\r
+ UINT32 AVL : 1;\r
+ UINT32 L : 1;\r
+ UINT32 DB : 1;\r
+ UINT32 G : 1;\r
+ UINT32 BaseHigh : 8;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} IA32_SEGMENT_DESCRIPTOR;\r
\r
///\r
/// Byte packed structure for an IDTR, GDTR, LDTR descriptor.\r
///\r
-#pragma pack (1)\r
+ #pragma pack (1)\r
typedef struct {\r
- UINT16 Limit;\r
- UINTN Base;\r
+ UINT16 Limit;\r
+ UINTN Base;\r
} IA32_DESCRIPTOR;\r
-#pragma pack ()\r
+ #pragma pack ()\r
\r
#define IA32_IDT_GATE_TYPE_TASK 0x85\r
#define IA32_IDT_GATE_TYPE_INTERRUPT_16 0x86\r
#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E\r
#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F\r
\r
-#define IA32_GDT_TYPE_TSS 0x9\r
-#define IA32_GDT_ALIGNMENT 8\r
+#define IA32_GDT_TYPE_TSS 0x9\r
+#define IA32_GDT_ALIGNMENT 8\r
\r
-#if defined (MDE_CPU_IA32)\r
+ #if defined (MDE_CPU_IA32)\r
///\r
/// Byte packed structure for an IA-32 Interrupt Gate Descriptor.\r
///\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; ///< Offset bits 15..0.\r
- UINT32 Selector:16; ///< Selector.\r
- UINT32 Reserved_0:8; ///< Reserved.\r
- UINT32 GateType:8; ///< Gate Type. See #defines above.\r
- UINT32 OffsetHigh:16; ///< Offset bits 31..16.\r
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.\r
+ UINT32 Selector : 16; ///< Selector.\r
+ UINT32 Reserved_0 : 8; ///< Reserved.\r
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.\r
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
-#pragma pack (1)\r
+ #pragma pack (1)\r
//\r
// IA32 Task-State Segment Definition\r
//\r
\r
typedef union {\r
struct {\r
- UINT32 LimitLow:16; ///< Segment Limit 15..00\r
- UINT32 BaseLow:16; ///< Base Address 15..00\r
- UINT32 BaseMid:8; ///< Base Address 23..16\r
- UINT32 Type:4; ///< Type (1 0 B 1)\r
- UINT32 Reserved_43:1; ///< 0\r
- UINT32 DPL:2; ///< Descriptor Privilege Level\r
- UINT32 P:1; ///< Segment Present\r
- UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
- UINT32 AVL:1; ///< Available for use by system software\r
- UINT32 Reserved_52:2; ///< 0 0\r
- UINT32 G:1; ///< Granularity\r
- UINT32 BaseHigh:8; ///< Base Address 31..24\r
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow : 16; ///< Base Address 15..00\r
+ UINT32 BaseMid : 8; ///< Base Address 23..16\r
+ UINT32 Type : 4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43 : 1; ///< 0\r
+ UINT32 DPL : 2; ///< Descriptor Privilege Level\r
+ UINT32 P : 1; ///< Segment Present\r
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16\r
+ UINT32 AVL : 1; ///< Available for use by system software\r
+ UINT32 Reserved_52 : 2; ///< 0 0\r
+ UINT32 G : 1; ///< Granularity\r
+ UINT32 BaseHigh : 8; ///< Base Address 31..24\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} IA32_TSS_DESCRIPTOR;\r
-#pragma pack ()\r
+ #pragma pack ()\r
\r
-#endif // defined (MDE_CPU_IA32)\r
+ #endif // defined (MDE_CPU_IA32)\r
\r
-#if defined (MDE_CPU_X64)\r
+ #if defined (MDE_CPU_X64)\r
///\r
/// Byte packed structure for an x64 Interrupt Gate Descriptor.\r
///\r
typedef union {\r
struct {\r
- UINT32 OffsetLow:16; ///< Offset bits 15..0.\r
- UINT32 Selector:16; ///< Selector.\r
- UINT32 Reserved_0:8; ///< Reserved.\r
- UINT32 GateType:8; ///< Gate Type. See #defines above.\r
- UINT32 OffsetHigh:16; ///< Offset bits 31..16.\r
- UINT32 OffsetUpper:32; ///< Offset bits 63..32.\r
- UINT32 Reserved_1:32; ///< Reserved.\r
+ UINT32 OffsetLow : 16; ///< Offset bits 15..0.\r
+ UINT32 Selector : 16; ///< Selector.\r
+ UINT32 Reserved_0 : 8; ///< Reserved.\r
+ UINT32 GateType : 8; ///< Gate Type. See #defines above.\r
+ UINT32 OffsetHigh : 16; ///< Offset bits 31..16.\r
+ UINT32 OffsetUpper : 32; ///< Offset bits 63..32.\r
+ UINT32 Reserved_1 : 32; ///< Reserved.\r
} Bits;\r
struct {\r
- UINT64 Uint64;\r
- UINT64 Uint64_1;\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
} Uint128;\r
} IA32_IDT_GATE_DESCRIPTOR;\r
\r
-#pragma pack (1)\r
+ #pragma pack (1)\r
//\r
// IA32 Task-State Segment Definition\r
//\r
\r
typedef union {\r
struct {\r
- UINT32 LimitLow:16; ///< Segment Limit 15..00\r
- UINT32 BaseLow:16; ///< Base Address 15..00\r
- UINT32 BaseMidl:8; ///< Base Address 23..16\r
- UINT32 Type:4; ///< Type (1 0 B 1)\r
- UINT32 Reserved_43:1; ///< 0\r
- UINT32 DPL:2; ///< Descriptor Privilege Level\r
- UINT32 P:1; ///< Segment Present\r
- UINT32 LimitHigh:4; ///< Segment Limit 19..16\r
- UINT32 AVL:1; ///< Available for use by system software\r
- UINT32 Reserved_52:2; ///< 0 0\r
- UINT32 G:1; ///< Granularity\r
- UINT32 BaseMidh:8; ///< Base Address 31..24\r
- UINT32 BaseHigh:32; ///< Base Address 63..32\r
- UINT32 Reserved_96:32; ///< Reserved\r
+ UINT32 LimitLow : 16; ///< Segment Limit 15..00\r
+ UINT32 BaseLow : 16; ///< Base Address 15..00\r
+ UINT32 BaseMidl : 8; ///< Base Address 23..16\r
+ UINT32 Type : 4; ///< Type (1 0 B 1)\r
+ UINT32 Reserved_43 : 1; ///< 0\r
+ UINT32 DPL : 2; ///< Descriptor Privilege Level\r
+ UINT32 P : 1; ///< Segment Present\r
+ UINT32 LimitHigh : 4; ///< Segment Limit 19..16\r
+ UINT32 AVL : 1; ///< Available for use by system software\r
+ UINT32 Reserved_52 : 2; ///< 0 0\r
+ UINT32 G : 1; ///< Granularity\r
+ UINT32 BaseMidh : 8; ///< Base Address 31..24\r
+ UINT32 BaseHigh : 32; ///< Base Address 63..32\r
+ UINT32 Reserved_96 : 32; ///< Reserved\r
} Bits;\r
struct {\r
- UINT64 Uint64;\r
- UINT64 Uint64_1;\r
+ UINT64 Uint64;\r
+ UINT64 Uint64_1;\r
} Uint128;\r
} IA32_TSS_DESCRIPTOR;\r
-#pragma pack ()\r
+ #pragma pack ()\r
\r
-#endif // defined (MDE_CPU_X64)\r
+ #endif // defined (MDE_CPU_X64)\r
\r
///\r
/// Byte packed structure for an FP/SSE/SSE2 context.\r
///\r
typedef struct {\r
- UINT8 Buffer[512];\r
+ UINT8 Buffer[512];\r
} IA32_FX_BUFFER;\r
\r
///\r
/// Structures for the 16-bit real mode thunks.\r
///\r
typedef struct {\r
- UINT32 Reserved1;\r
- UINT32 Reserved2;\r
- UINT32 Reserved3;\r
- UINT32 Reserved4;\r
- UINT8 BL;\r
- UINT8 BH;\r
- UINT16 Reserved5;\r
- UINT8 DL;\r
- UINT8 DH;\r
- UINT16 Reserved6;\r
- UINT8 CL;\r
- UINT8 CH;\r
- UINT16 Reserved7;\r
- UINT8 AL;\r
- UINT8 AH;\r
- UINT16 Reserved8;\r
+ UINT32 Reserved1;\r
+ UINT32 Reserved2;\r
+ UINT32 Reserved3;\r
+ UINT32 Reserved4;\r
+ UINT8 BL;\r
+ UINT8 BH;\r
+ UINT16 Reserved5;\r
+ UINT8 DL;\r
+ UINT8 DH;\r
+ UINT16 Reserved6;\r
+ UINT8 CL;\r
+ UINT8 CH;\r
+ UINT16 Reserved7;\r
+ UINT8 AL;\r
+ UINT8 AH;\r
+ UINT16 Reserved8;\r
} IA32_BYTE_REGS;\r
\r
typedef struct {\r
- UINT16 DI;\r
- UINT16 Reserved1;\r
- UINT16 SI;\r
- UINT16 Reserved2;\r
- UINT16 BP;\r
- UINT16 Reserved3;\r
- UINT16 SP;\r
- UINT16 Reserved4;\r
- UINT16 BX;\r
- UINT16 Reserved5;\r
- UINT16 DX;\r
- UINT16 Reserved6;\r
- UINT16 CX;\r
- UINT16 Reserved7;\r
- UINT16 AX;\r
- UINT16 Reserved8;\r
+ UINT16 DI;\r
+ UINT16 Reserved1;\r
+ UINT16 SI;\r
+ UINT16 Reserved2;\r
+ UINT16 BP;\r
+ UINT16 Reserved3;\r
+ UINT16 SP;\r
+ UINT16 Reserved4;\r
+ UINT16 BX;\r
+ UINT16 Reserved5;\r
+ UINT16 DX;\r
+ UINT16 Reserved6;\r
+ UINT16 CX;\r
+ UINT16 Reserved7;\r
+ UINT16 AX;\r
+ UINT16 Reserved8;\r
} IA32_WORD_REGS;\r
\r
typedef struct {\r
- UINT32 EDI;\r
- UINT32 ESI;\r
- UINT32 EBP;\r
- UINT32 ESP;\r
- UINT32 EBX;\r
- UINT32 EDX;\r
- UINT32 ECX;\r
- UINT32 EAX;\r
- UINT16 DS;\r
- UINT16 ES;\r
- UINT16 FS;\r
- UINT16 GS;\r
- IA32_EFLAGS32 EFLAGS;\r
- UINT32 Eip;\r
- UINT16 CS;\r
- UINT16 SS;\r
+ UINT32 EDI;\r
+ UINT32 ESI;\r
+ UINT32 EBP;\r
+ UINT32 ESP;\r
+ UINT32 EBX;\r
+ UINT32 EDX;\r
+ UINT32 ECX;\r
+ UINT32 EAX;\r
+ UINT16 DS;\r
+ UINT16 ES;\r
+ UINT16 FS;\r
+ UINT16 GS;\r
+ IA32_EFLAGS32 EFLAGS;\r
+ UINT32 Eip;\r
+ UINT16 CS;\r
+ UINT16 SS;\r
} IA32_DWORD_REGS;\r
\r
typedef union {\r
- IA32_DWORD_REGS E;\r
- IA32_WORD_REGS X;\r
- IA32_BYTE_REGS H;\r
+ IA32_DWORD_REGS E;\r
+ IA32_WORD_REGS X;\r
+ IA32_BYTE_REGS H;\r
} IA32_REGISTER_SET;\r
\r
///\r
/// Byte packed structure for an 16-bit real mode thunks.\r
///\r
typedef struct {\r
- IA32_REGISTER_SET *RealModeState;\r
- VOID *RealModeBuffer;\r
- UINT32 RealModeBufferSize;\r
- UINT32 ThunkAttributes;\r
+ IA32_REGISTER_SET *RealModeState;\r
+ VOID *RealModeBuffer;\r
+ UINT32 RealModeBufferSize;\r
+ UINT32 ThunkAttributes;\r
} THUNK_CONTEXT;\r
\r
-#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001\r
-#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\r
-#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\r
+#define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001\r
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002\r
+#define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004\r
\r
///\r
/// Type definition for representing labels in NASM source code that allow for\r
/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID\r
/// return type and the VOID argument list are merely artifacts.\r
///\r
-typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);\r
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (\r
+ VOID\r
+ );\r
\r
/**\r
Retrieves CPUID information.\r
UINT32\r
EFIAPI\r
AsmCpuid (\r
- IN UINT32 Index,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
);\r
\r
-\r
/**\r
Retrieves CPUID information using an extended leaf identifier.\r
\r
UINT32\r
EFIAPI\r
AsmCpuidEx (\r
- IN UINT32 Index,\r
- IN UINT32 SubIndex,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ IN UINT32 SubIndex,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
);\r
\r
-\r
/**\r
Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Perform a WBINVD and clear both the CD and NW bits of CR0.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns the lower 32-bits of a Machine Specific Register(MSR).\r
\r
UINT32\r
EFIAPI\r
AsmReadMsr32 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
);\r
\r
-\r
/**\r
Writes a 32-bit value to a Machine Specific Register(MSR), and returns the value.\r
The upper 32-bits of the MSR are set to zero.\r
UINT32\r
EFIAPI\r
AsmWriteMsr32 (\r
- IN UINT32 Index,\r
- IN UINT32 Value\r
+ IN UINT32 Index,\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise OR on the lower 32-bits, and\r
writes the result back to the 64-bit MSR.\r
UINT32\r
EFIAPI\r
AsmMsrOr32 (\r
- IN UINT32 Index,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise AND on the lower 32-bits, and writes\r
the result back to the 64-bit MSR.\r
UINT32\r
EFIAPI\r
AsmMsrAnd32 (\r
- IN UINT32 Index,\r
- IN UINT32 AndData\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise OR\r
on the lower 32-bits, and writes the result back to the 64-bit MSR.\r
UINT32\r
EFIAPI\r
AsmMsrAndThenOr32 (\r
- IN UINT32 Index,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field of an MSR.\r
\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldRead32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to an MSR.\r
\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldWrite32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and writes the\r
result back to the bit field in the 64-bit MSR.\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldOr32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r
result back to the bit field in the 64-bit MSR.\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldAnd32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
bitwise OR, and writes the result back to the bit field in the\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldAndThenOr32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
-\r
/**\r
Returns a 64-bit Machine Specific Register(MSR).\r
\r
UINT64\r
EFIAPI\r
AsmReadMsr64 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
);\r
\r
-\r
/**\r
Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
value.\r
UINT64\r
EFIAPI\r
AsmWriteMsr64 (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise OR, and writes the result\r
back to the 64-bit MSR.\r
UINT64\r
EFIAPI\r
AsmMsrOr64 (\r
- IN UINT32 Index,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINT64 OrData\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise AND, and writes the result back to the\r
64-bit MSR.\r
UINT64\r
EFIAPI\r
AsmMsrAnd64 (\r
- IN UINT32 Index,\r
- IN UINT64 AndData\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData\r
);\r
\r
-\r
/**\r
Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise\r
OR, and writes the result back to the 64-bit MSR.\r
UINT64\r
EFIAPI\r
AsmMsrAndThenOr64 (\r
- IN UINT32 Index,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field of an MSR.\r
\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldRead64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Writes a bit field to an MSR.\r
\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldWrite64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise OR, and\r
writes the result back to the bit field in the 64-bit MSR.\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldOr64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND, and writes the\r
result back to the bit field in the 64-bit MSR.\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldAnd64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
);\r
\r
-\r
/**\r
Reads a bit field in a 64-bit MSR, performs a bitwise AND followed by a\r
bitwise OR, and writes the result back to the bit field in the\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldAndThenOr64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
-\r
/**\r
Reads the current value of the EFLAGS register.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of the Control Register 0 (CR0).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of the Control Register 2 (CR2).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of the Control Register 3 (CR3).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of the Control Register 4 (CR4).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Writes a value to Control Register 0 (CR0).\r
\r
UINTN Cr0\r
);\r
\r
-\r
/**\r
Writes a value to Control Register 2 (CR2).\r
\r
UINTN Cr2\r
);\r
\r
-\r
/**\r
Writes a value to Control Register 3 (CR3).\r
\r
UINTN Cr3\r
);\r
\r
-\r
/**\r
Writes a value to Control Register 4 (CR4).\r
\r
UINTN Cr4\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 0 (DR0).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 1 (DR1).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 2 (DR2).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 3 (DR3).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 4 (DR4).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 5 (DR5).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 6 (DR6).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Debug Register 7 (DR7).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 0 (DR0).\r
\r
UINTN Dr0\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 1 (DR1).\r
\r
UINTN Dr1\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 2 (DR2).\r
\r
UINTN Dr2\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 3 (DR3).\r
\r
UINTN Dr3\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 4 (DR4).\r
\r
UINTN Dr4\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 5 (DR5).\r
\r
UINTN Dr5\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 6 (DR6).\r
\r
UINTN Dr6\r
);\r
\r
-\r
/**\r
Writes a value to Debug Register 7 (DR7).\r
\r
UINTN Dr7\r
);\r
\r
-\r
/**\r
Reads the current value of Code Segment Register (CS).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Data Segment Register (DS).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Extra Segment Register (ES).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of FS Data Segment Register (FS).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of GS Data Segment Register (GS).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Stack Segment Register (SS).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of Task Register (TR).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
AsmReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
);\r
\r
-\r
/**\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
AsmWriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
);\r
\r
-\r
/**\r
Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
AsmReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
);\r
\r
-\r
/**\r
Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
AsmWriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
);\r
\r
-\r
/**\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Writes the current Local Descriptor Table Register (LDTR) selector.\r
\r
VOID\r
EFIAPI\r
AsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
);\r
\r
-\r
/**\r
Save the current floating point/SSE/SSE2 context to a buffer.\r
\r
VOID\r
EFIAPI\r
AsmFxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
);\r
\r
-\r
/**\r
Restores the current floating point/SSE/SSE2 context from a buffer.\r
\r
VOID\r
EFIAPI\r
AsmFxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm0 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm1 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm2 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm3 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm4 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm5 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm6 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm7 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
);\r
\r
-\r
/**\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reads the current value of a Performance Counter (PMC).\r
\r
UINT64\r
EFIAPI\r
AsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
);\r
\r
-\r
/**\r
Sets up a monitor buffer that is used by AsmMwait().\r
\r
UINTN\r
EFIAPI\r
AsmMonitor (\r
- IN UINTN Eax,\r
- IN UINTN Ecx,\r
- IN UINTN Edx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
);\r
\r
-\r
/**\r
Executes an MWAIT instruction.\r
\r
UINTN\r
EFIAPI\r
AsmMwait (\r
- IN UINTN Eax,\r
- IN UINTN Ecx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
);\r
\r
-\r
/**\r
Executes a WBINVD instruction.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Executes a INVD instruction.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Flushes a cache line from all the instruction and data caches within the\r
coherency domain of the CPU.\r
VOID *\r
EFIAPI\r
AsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
);\r
\r
-\r
/**\r
Enables the 32-bit paging mode on the CPU.\r
\r
IN VOID *NewStack\r
);\r
\r
-\r
/**\r
Disables the 32-bit paging mode on the CPU.\r
\r
IN VOID *NewStack\r
);\r
\r
-\r
/**\r
Enables the 64-bit paging mode on the CPU.\r
\r
VOID\r
EFIAPI\r
AsmEnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
);\r
\r
-\r
/**\r
Disables the 64-bit paging mode on the CPU.\r
\r
VOID\r
EFIAPI\r
AsmDisablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
);\r
\r
-\r
//\r
// 16-bit thunking services\r
//\r
VOID\r
EFIAPI\r
AsmGetThunk16Properties (\r
- OUT UINT32 *RealModeBufferSize,\r
- OUT UINT32 *ExtraStackSize\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
);\r
\r
-\r
/**\r
Prepares all structures a code required to use AsmThunk16().\r
\r
VOID\r
EFIAPI\r
AsmPrepareThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
);\r
\r
-\r
/**\r
Transfers control to a 16-bit real mode entry point and returns the results.\r
\r
VOID\r
EFIAPI\r
AsmThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
);\r
\r
-\r
/**\r
Prepares all structures and code for a 16-bit real mode thunk, transfers\r
control to a 16-bit real mode entry point, and returns the results.\r
VOID\r
EFIAPI\r
AsmPrepareAndThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
AsmRdRand16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
AsmRdRand32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
AsmRdRand64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
AsmWriteTr (\r
- IN UINT16 Selector\r
+ IN UINT16 Selector\r
);\r
\r
/**\r
VOID\r
);\r
\r
-\r
/**\r
Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
word, dword or qword operand is encoded at the end of the instruction's\r
VOID\r
EFIAPI\r
PatchInstructionX86 (\r
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
- IN UINT64 PatchValue,\r
- IN UINTN ValueSize\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
);\r
\r
#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
);\r
\r
#endif\r
VOID\r
);\r
\r
-\r
#endif\r
#define DEBUG_CACHE 0x00200000 // Memory range cachability changes\r
#define DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may\r
// significantly impact boot performance\r
-#define DEBUG_ERROR 0x80000000 // Error\r
+#define DEBUG_ERROR 0x80000000 // Error\r
\r
//\r
// Aliases of debug message mask bits\r
...\r
);\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
);\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
);\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
IN CONST CHAR8 *Description\r
);\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
IN UINTN Length\r
);\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
);\r
\r
/**\r
\r
**/\r
#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED)\r
+\r
/**\r
Unit test library replacement for DebugAssert() in DebugLib.\r
\r
IN CONST CHAR8 *Description\r
);\r
\r
-#if defined(__clang__) && defined(__FILE_NAME__)\r
+ #if defined (__clang__) && defined (__FILE_NAME__)\r
#define _ASSERT(Expression) UnitTestDebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))\r
-#else\r
+ #else\r
#define _ASSERT(Expression) UnitTestDebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))\r
-#endif\r
+ #endif\r
#else\r
-#if defined(__clang__) && defined(__FILE_NAME__)\r
+ #if defined (__clang__) && defined (__FILE_NAME__)\r
#define _ASSERT(Expression) DebugAssert (__FILE_NAME__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))\r
-#else\r
+ #else\r
#define _ASSERT(Expression) DebugAssert (__FILE__, DEBUG_LINE_NUMBER, DEBUG_EXPRESSION_STRING (Expression))\r
-#endif\r
+ #endif\r
#endif\r
\r
/**\r
\r
**/\r
\r
-#if !defined(MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400)\r
- #define _DEBUG_PRINT(PrintLevel, ...) \\r
+#if !defined (MDE_CPU_EBC) && (!defined (_MSC_VER) || _MSC_VER > 1400)\r
+#define _DEBUG_PRINT(PrintLevel, ...) \\r
do { \\r
if (DebugPrintLevelEnabled (PrintLevel)) { \\r
DebugPrint (PrintLevel, ##__VA_ARGS__); \\r
} \\r
} while (FALSE)\r
- #define _DEBUG(Expression) _DEBUG_PRINT Expression\r
+#define _DEBUG(Expression) _DEBUG_PRINT Expression\r
#else\r
-#define _DEBUG(Expression) DebugPrint Expression\r
+#define _DEBUG(Expression) DebugPrint Expression\r
#endif\r
\r
/**\r
@param Expression Boolean expression.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define ASSERT(Expression) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define ASSERT(Expression) \\r
do { \\r
if (DebugAssertEnabled ()) { \\r
if (!(Expression)) { \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT(Expression)\r
+#define ASSERT(Expression)\r
#endif\r
\r
/**\r
\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define DEBUG(Expression) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define DEBUG(Expression) \\r
do { \\r
if (DebugPrintEnabled ()) { \\r
_DEBUG (Expression); \\r
} \\r
} while (FALSE)\r
#else\r
- #define DEBUG(Expression)\r
+#define DEBUG(Expression)\r
#endif\r
\r
/**\r
@param StatusParameter EFI_STATUS value to evaluate.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define ASSERT_EFI_ERROR(StatusParameter) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define ASSERT_EFI_ERROR(StatusParameter) \\r
do { \\r
if (DebugAssertEnabled ()) { \\r
if (EFI_ERROR (StatusParameter)) { \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT_EFI_ERROR(StatusParameter)\r
+#define ASSERT_EFI_ERROR(StatusParameter)\r
#endif\r
\r
/**\r
@param StatusParameter RETURN_STATUS value to evaluate.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define ASSERT_RETURN_ERROR(StatusParameter) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define ASSERT_RETURN_ERROR(StatusParameter) \\r
do { \\r
if (DebugAssertEnabled ()) { \\r
if (RETURN_ERROR (StatusParameter)) { \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT_RETURN_ERROR(StatusParameter)\r
+#define ASSERT_RETURN_ERROR(StatusParameter)\r
#endif\r
\r
/**\r
@param Guid The pointer to a protocol GUID.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid) \\r
do { \\r
if (DebugAssertEnabled ()) { \\r
VOID *Instance; \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)\r
+#define ASSERT_PROTOCOL_ALREADY_INSTALLED(Handle, Guid)\r
#endif\r
\r
/**\r
**/\r
#define DEBUG_CODE_BEGIN() do { if (DebugCodeEnabled ()) { UINT8 __DebugCodeLocal\r
\r
-\r
/**\r
The macro that marks the end of debug source code.\r
\r
are not included in a module.\r
\r
**/\r
-#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)\r
-\r
+#define DEBUG_CODE_END() __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)\r
\r
/**\r
The macro that declares a section of debug source code.\r
Expression \\r
DEBUG_CODE_END ()\r
\r
-\r
/**\r
The macro that calls DebugClearMemory() to clear a buffer to a default value.\r
\r
} \\r
} while (FALSE)\r
\r
-\r
/**\r
Macro that calls DebugAssert() if the containing record does not have a\r
matching signature. If the signatures matches, then a pointer to the data\r
@param TestSignature The 32-bit signature value to match.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define CR(Record, TYPE, Field, TestSignature) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define CR(Record, TYPE, Field, TestSignature) \\r
(DebugAssertEnabled () && (BASE_CR (Record, TYPE, Field)->Signature != TestSignature)) ? \\r
(TYPE *) (_ASSERT (CR has Bad Signature), Record) : \\r
BASE_CR (Record, TYPE, Field)\r
#else\r
- #define CR(Record, TYPE, Field, TestSignature) \\r
+#define CR(Record, TYPE, Field, TestSignature) \\r
BASE_CR (Record, TYPE, Field)\r
#endif\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+\r
#ifndef _DEBUG_PRINT_ERROR_LEVEL_LIB_H_\r
#define _DEBUG_PRINT_ERROR_LEVEL_LIB_H_\r
\r
SetDebugPrintErrorLevel (\r
UINT32 ErrorLevel\r
);\r
+\r
#endif\r
#ifndef __DEVICE_PATH_LIB_H__\r
#define __DEVICE_PATH_LIB_H__\r
\r
-#define END_DEVICE_PATH_LENGTH (sizeof (EFI_DEVICE_PATH_PROTOCOL))\r
+#define END_DEVICE_PATH_LENGTH (sizeof (EFI_DEVICE_PATH_PROTOCOL))\r
\r
/**\r
Determine whether a given device path is valid.\r
BOOLEAN\r
EFIAPI\r
IsDevicePathValid (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN UINTN MaxSize\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINTN MaxSize\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
GetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
CreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
DevicePathFromHandle (\r
- IN EFI_HANDLE Handle\r
+ IN EFI_HANDLE Handle\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
FileDevicePath (\r
- IN EFI_HANDLE Device OPTIONAL,\r
- IN CONST CHAR16 *FileName\r
+ IN EFI_HANDLE Device OPTIONAL,\r
+ IN CONST CHAR16 *FileName\r
);\r
\r
/**\r
CHAR16 *\r
EFIAPI\r
ConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
);\r
\r
#endif\r
///\r
extern VOID *gHobList;\r
\r
-\r
/**\r
The entry point of PE/COFF Image for the DXE Core.\r
\r
IN VOID *HobStart\r
);\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
IN VOID *HobStart\r
);\r
\r
-\r
/**\r
Autogenerated function that calls the library constructors for all of the module's dependent libraries.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Autogenerated function that calls a set of module entry points.\r
\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromAnyFvByFileType (\r
- IN EFI_FV_FILETYPE FileType,\r
- IN UINTN FileInstance,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN EFI_FV_FILETYPE FileType,\r
+ IN UINTN FileInstance,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromAnyFv (\r
- IN CONST EFI_GUID *NameGuid,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN CONST EFI_GUID *NameGuid,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromFv (\r
- IN CONST EFI_GUID *NameGuid,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN CONST EFI_GUID *NameGuid,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
);\r
\r
-\r
/**\r
Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section.\r
\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromFfs (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
);\r
\r
-\r
/**\r
Get the image file buffer data and buffer size by its device path.\r
\r
VOID *\r
EFIAPI\r
GetFileBufferByFilePath (\r
- IN BOOLEAN BootPolicy,\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath,\r
- OUT UINTN *FileSize,\r
- OUT UINT32 *AuthenticationStatus\r
+ IN BOOLEAN BootPolicy,\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath,\r
+ OUT UINTN *FileSize,\r
+ OUT UINT32 *AuthenticationStatus\r
);\r
\r
/**\r
extern EFI_DXE_SERVICES *gDS;\r
\r
#endif\r
-\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+\r
#ifndef __EXTRACT_GUIDED_SECTION_H__\r
#define __EXTRACT_GUIDED_SECTION_H__\r
\r
\r
/// The tag for use in identifying UNICODE files.\r
/// If the file is UNICODE, the first 16 bits of the file will equal this value.\r
-extern CONST UINT16 gUnicodeFileTag;\r
+extern CONST UINT16 gUnicodeFileTag;\r
\r
/**\r
This function retrieves information about the file for the handle\r
@retval NULL Information could not be retrieved.\r
@retval !NULL The information about the file.\r
**/\r
-EFI_FILE_INFO*\r
+EFI_FILE_INFO *\r
EFIAPI\r
FileHandleGetInfo (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetInfo (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_FILE_INFO *FileInfo\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_FILE_INFO *FileInfo\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleRead(\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
+FileHandleRead (\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleWrite(\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
+FileHandleWrite (\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleClose (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleDelete (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetPosition (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN UINT64 Position\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN UINT64 Position\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetPosition (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- OUT UINT64 *Position\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ OUT UINT64 *Position\r
);\r
+\r
/**\r
Flushes data on a file.\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleFlush (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleIsDirectory (\r
- IN EFI_FILE_HANDLE DirHandle\r
+ IN EFI_FILE_HANDLE DirHandle\r
);\r
\r
/** Retrieve first entry from a directory.\r
EFI_STATUS\r
EFIAPI\r
FileHandleFindFirstFile (\r
- IN EFI_FILE_HANDLE DirHandle,\r
- OUT EFI_FILE_INFO **Buffer\r
+ IN EFI_FILE_HANDLE DirHandle,\r
+ OUT EFI_FILE_INFO **Buffer\r
);\r
\r
/** Retrieve next entries from a directory.\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleFindNextFile(\r
- IN EFI_FILE_HANDLE DirHandle,\r
- OUT EFI_FILE_INFO *Buffer,\r
- OUT BOOLEAN *NoFile\r
+FileHandleFindNextFile (\r
+ IN EFI_FILE_HANDLE DirHandle,\r
+ OUT EFI_FILE_INFO *Buffer,\r
+ OUT BOOLEAN *NoFile\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetSize (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- OUT UINT64 *Size\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ OUT UINT64 *Size\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetSize (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN UINT64 Size\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN UINT64 Size\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetFileName (\r
- IN CONST EFI_FILE_HANDLE Handle,\r
- OUT CHAR16 **FullFileName\r
+ IN CONST EFI_FILE_HANDLE Handle,\r
+ OUT CHAR16 **FullFileName\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleReadLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN OUT CHAR16 *Buffer,\r
- IN OUT UINTN *Size,\r
- IN BOOLEAN Truncate,\r
- IN OUT BOOLEAN *Ascii\r
+FileHandleReadLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN OUT CHAR16 *Buffer,\r
+ IN OUT UINTN *Size,\r
+ IN BOOLEAN Truncate,\r
+ IN OUT BOOLEAN *Ascii\r
);\r
\r
/**\r
\r
@sa FileHandleReadLine\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
-FileHandleReturnLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN OUT BOOLEAN *Ascii\r
+FileHandleReturnLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN OUT BOOLEAN *Ascii\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleWriteLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN CHAR16 *Buffer\r
+FileHandleWriteLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN CHAR16 *Buffer\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandlePrintLine(\r
+FileHandlePrintLine (\r
IN EFI_FILE_HANDLE Handle,\r
IN CONST CHAR16 *Format,\r
...\r
**/\r
BOOLEAN\r
EFIAPI\r
-FileHandleEof(\r
- IN EFI_FILE_HANDLE Handle\r
+FileHandleEof (\r
+ IN EFI_FILE_HANDLE Handle\r
);\r
\r
#endif //_FILE_HANDLE_LIBRARY_HEADER_\r
-\r
VOID *\r
EFIAPI\r
GetNextHob (\r
- IN UINT16 Type,\r
- IN CONST VOID *HobStart\r
+ IN UINT16 Type,\r
+ IN CONST VOID *HobStart\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
GetFirstHob (\r
- IN UINT16 Type\r
+ IN UINT16 Type\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
GetNextGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN CONST VOID *HobStart\r
+ IN CONST EFI_GUID *Guid,\r
+ IN CONST VOID *HobStart\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
GetFirstGuidHob (\r
- IN CONST EFI_GUID *Guid\r
+ IN CONST EFI_GUID *Guid\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildModuleHob (\r
- IN CONST EFI_GUID *ModuleName,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
- IN UINT64 ModuleLength,\r
- IN EFI_PHYSICAL_ADDRESS EntryPoint\r
+ IN CONST EFI_GUID *ModuleName,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
+ IN UINT64 ModuleLength,\r
+ IN EFI_PHYSICAL_ADDRESS EntryPoint\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
BuildGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN DataLength\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
BuildGuidDataHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN VOID *Data,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN VOID *Data,\r
+ IN UINTN DataLength\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildFvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildFv2Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN CONST EFI_GUID *FvName,\r
- IN CONST EFI_GUID *FileName\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GUID *FvName,\r
+ IN CONST EFI_GUID *FileName\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildFv3Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT32 AuthenticationStatus,\r
- IN BOOLEAN ExtractedFv,\r
- IN CONST EFI_GUID *FvName OPTIONAL,\r
- IN CONST EFI_GUID *FileName OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT32 AuthenticationStatus,\r
+ IN BOOLEAN ExtractedFv,\r
+ IN CONST EFI_GUID *FvName OPTIONAL,\r
+ IN CONST EFI_GUID *FileName OPTIONAL\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildCvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildCpuHob (\r
- IN UINT8 SizeOfMemorySpace,\r
- IN UINT8 SizeOfIoSpace\r
+ IN UINT8 SizeOfMemorySpace,\r
+ IN UINT8 SizeOfIoSpace\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildStackHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildBspStoreHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
BuildMemoryAllocationHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetTable (\r
- IN VOID *Hsti,\r
- IN UINTN HstiSize\r
+ IN VOID *Hsti,\r
+ IN UINTN HstiSize\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibGetTable (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- OUT VOID **Hsti,\r
- OUT UINTN *HstiSize\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ OUT VOID **Hsti,\r
+ OUT UINTN *HstiSize\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetFeaturesVerified (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN UINT32 ByteIndex,\r
- IN UINT8 BitMask\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN UINT32 ByteIndex,\r
+ IN UINT8 BitMask\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibClearFeaturesVerified (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN UINT32 ByteIndex,\r
- IN UINT8 BitMask\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN UINT32 ByteIndex,\r
+ IN UINT8 BitMask\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibAppendErrorString (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN CHAR16 *ErrorString\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN CHAR16 *ErrorString\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetErrorString (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN CHAR16 *ErrorString\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN CHAR16 *ErrorString\r
);\r
\r
#endif\r
\r
**/\r
\r
-#define IO_LIB_ADDRESS(Segment,Port) \\r
+#define IO_LIB_ADDRESS(Segment, Port) \\r
( ((Port) & 0xffff) | (((Segment) & 0xffff) << 16) )\r
\r
/**\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
);\r
\r
/**\r
UINT8 *\r
EFIAPI\r
MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
);\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
);\r
\r
/**\r
UINT32 *\r
EFIAPI\r
MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
);\r
\r
/**\r
UINT64 *\r
EFIAPI\r
MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
);\r
\r
/**\r
UINT8 *\r
EFIAPI\r
MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
);\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
);\r
\r
/**\r
UINT32 *\r
EFIAPI\r
MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
);\r
\r
/**\r
UINT64 *\r
EFIAPI\r
MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
);\r
\r
-\r
#endif\r
-\r
VOID\r
EFIAPI\r
FreePool (\r
- IN VOID *Buffer\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
\r
#include <PiMm.h>\r
\r
-extern EFI_MM_SYSTEM_TABLE *gMmst;\r
+extern EFI_MM_SYSTEM_TABLE *gMmst;\r
\r
#endif\r
RETURN_STATUS\r
EFIAPI\r
MmUnblockMemoryRequest (\r
- IN PHYSICAL_ADDRESS UnblockAddress,\r
- IN UINT64 NumberOfPages\r
-);\r
+ IN PHYSICAL_ADDRESS UnblockAddress,\r
+ IN UINT64 NumberOfPages\r
+ );\r
\r
#endif // MM_UNBLOCK_MEMORY_LIB_H_\r
IN CONST VOID *UserStruct\r
);\r
\r
-\r
//\r
// Some functions below are read-only, while others are read-write. If any\r
// write operation is expected to run concurrently with any other operation on\r
VOID *\r
EFIAPI\r
OrderedCollectionUserStruct (\r
- IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
);\r
\r
-\r
/**\r
Allocate and initialize the ORDERED_COLLECTION structure.\r
\r
ORDERED_COLLECTION *\r
EFIAPI\r
OrderedCollectionInit (\r
- IN ORDERED_COLLECTION_USER_COMPARE UserStructCompare,\r
- IN ORDERED_COLLECTION_KEY_COMPARE KeyCompare\r
+ IN ORDERED_COLLECTION_USER_COMPARE UserStructCompare,\r
+ IN ORDERED_COLLECTION_KEY_COMPARE KeyCompare\r
);\r
\r
-\r
/**\r
Check whether the collection is empty (has no entries).\r
\r
BOOLEAN\r
EFIAPI\r
OrderedCollectionIsEmpty (\r
- IN CONST ORDERED_COLLECTION *Collection\r
+ IN CONST ORDERED_COLLECTION *Collection\r
);\r
\r
-\r
/**\r
Uninitialize and release an empty ORDERED_COLLECTION structure.\r
\r
VOID\r
EFIAPI\r
OrderedCollectionUninit (\r
- IN ORDERED_COLLECTION *Collection\r
+ IN ORDERED_COLLECTION *Collection\r
);\r
\r
-\r
/**\r
Look up the collection entry that links the user structure that matches the\r
specified standalone key.\r
ORDERED_COLLECTION_ENTRY *\r
EFIAPI\r
OrderedCollectionFind (\r
- IN CONST ORDERED_COLLECTION *Collection,\r
- IN CONST VOID *StandaloneKey\r
+ IN CONST ORDERED_COLLECTION *Collection,\r
+ IN CONST VOID *StandaloneKey\r
);\r
\r
-\r
/**\r
Find the collection entry of the minimum user structure stored in the\r
collection.\r
ORDERED_COLLECTION_ENTRY *\r
EFIAPI\r
OrderedCollectionMin (\r
- IN CONST ORDERED_COLLECTION *Collection\r
+ IN CONST ORDERED_COLLECTION *Collection\r
);\r
\r
-\r
/**\r
Find the collection entry of the maximum user structure stored in the\r
collection.\r
ORDERED_COLLECTION_ENTRY *\r
EFIAPI\r
OrderedCollectionMax (\r
- IN CONST ORDERED_COLLECTION *Collection\r
+ IN CONST ORDERED_COLLECTION *Collection\r
);\r
\r
-\r
/**\r
Get the collection entry of the least user structure that is greater than the\r
one linked by Entry.\r
ORDERED_COLLECTION_ENTRY *\r
EFIAPI\r
OrderedCollectionNext (\r
- IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
);\r
\r
-\r
/**\r
Get the collection entry of the greatest user structure that is less than the\r
one linked by Entry.\r
ORDERED_COLLECTION_ENTRY *\r
EFIAPI\r
OrderedCollectionPrev (\r
- IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
+ IN CONST ORDERED_COLLECTION_ENTRY *Entry\r
);\r
\r
-\r
/**\r
Insert (link) a user structure into the collection, allocating a new\r
collection entry.\r
RETURN_STATUS\r
EFIAPI\r
OrderedCollectionInsert (\r
- IN OUT ORDERED_COLLECTION *Collection,\r
- OUT ORDERED_COLLECTION_ENTRY **Entry OPTIONAL,\r
- IN VOID *UserStruct\r
+ IN OUT ORDERED_COLLECTION *Collection,\r
+ OUT ORDERED_COLLECTION_ENTRY **Entry OPTIONAL,\r
+ IN VOID *UserStruct\r
);\r
\r
-\r
/**\r
Delete an entry from the collection, unlinking the associated user structure.\r
\r
VOID\r
EFIAPI\r
OrderedCollectionDelete (\r
- IN OUT ORDERED_COLLECTION *Collection,\r
- IN ORDERED_COLLECTION_ENTRY *Entry,\r
- OUT VOID **UserStruct OPTIONAL\r
+ IN OUT ORDERED_COLLECTION *Collection,\r
+ IN ORDERED_COLLECTION_ENTRY *Entry,\r
+ OUT VOID **UserStruct OPTIONAL\r
);\r
\r
#endif\r
#ifndef __PCD_LIB_H__\r
#define __PCD_LIB_H__\r
\r
-\r
/**\r
Retrieves a token number based on a token name.\r
\r
@return The token number associated with the PCD.\r
\r
**/\r
-#define PcdToken(TokenName) _PCD_TOKEN_##TokenName\r
-\r
+#define PcdToken(TokenName) _PCD_TOKEN_##TokenName\r
\r
/**\r
Retrieves a Boolean PCD feature flag based on a token name.\r
@return Boolean value for the PCD feature flag.\r
\r
**/\r
-#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName\r
-\r
+#define FeaturePcdGet(TokenName) _PCD_GET_MODE_BOOL_##TokenName\r
\r
/**\r
Retrieves an 8-bit fixed PCD token value based on a token name.\r
@return 8-bit value for the token specified by TokenName.\r
\r
**/\r
-#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName\r
-\r
+#define FixedPcdGet8(TokenName) _PCD_VALUE_##TokenName\r
\r
/**\r
Retrieves a 16-bit fixed PCD token value based on a token name.\r
@return 16-bit value for the token specified by TokenName.\r
\r
**/\r
-#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName\r
-\r
+#define FixedPcdGet16(TokenName) _PCD_VALUE_##TokenName\r
\r
/**\r
Retrieves a 32-bit fixed PCD token value based on a token name.\r
@return 32-bit value for the token specified by TokenName.\r
\r
**/\r
-#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName\r
-\r
+#define FixedPcdGet32(TokenName) _PCD_VALUE_##TokenName\r
\r
/**\r
Retrieves a 64-bit fixed PCD token value based on a token name.\r
@return 64-bit value for the token specified by TokenName.\r
\r
**/\r
-#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName\r
-\r
+#define FixedPcdGet64(TokenName) _PCD_VALUE_##TokenName\r
\r
/**\r
Retrieves a Boolean fixed PCD token value based on a token name.\r
@return The Boolean value for the token.\r
\r
**/\r
-#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName\r
-\r
+#define FixedPcdGetBool(TokenName) _PCD_VALUE_##TokenName\r
\r
/**\r
Retrieves a pointer to a fixed PCD token buffer based on a token name.\r
@return A pointer to the buffer.\r
\r
**/\r
-#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName)\r
-\r
+#define FixedPcdGetPtr(TokenName) ((VOID *)_PCD_VALUE_##TokenName)\r
\r
/**\r
Retrieves an 8-bit binary patchable PCD token value based on a token name.\r
@return An 8-bit binary patchable PCD token value.\r
\r
**/\r
-#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName\r
+#define PatchPcdGet8(TokenName) _gPcd_BinaryPatch_##TokenName\r
\r
/**\r
Retrieves a 16-bit binary patchable PCD token value based on a token name.\r
@return A 16-bit binary patchable PCD token value.\r
\r
**/\r
-#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName\r
-\r
+#define PatchPcdGet16(TokenName) _gPcd_BinaryPatch_##TokenName\r
\r
/**\r
Retrieves a 32-bit binary patchable PCD token value based on a token name.\r
@return A 32-bit binary patchable PCD token value.\r
\r
**/\r
-#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName\r
-\r
+#define PatchPcdGet32(TokenName) _gPcd_BinaryPatch_##TokenName\r
\r
/**\r
Retrieves a 64-bit binary patchable PCD token value based on a token name.\r
@return A 64-bit binary patchable PCD token value.\r
\r
**/\r
-#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName\r
-\r
+#define PatchPcdGet64(TokenName) _gPcd_BinaryPatch_##TokenName\r
\r
/**\r
Retrieves a Boolean binary patchable PCD token value based on a token name.\r
@return The Boolean value for the token.\r
\r
**/\r
-#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName\r
-\r
+#define PatchPcdGetBool(TokenName) _gPcd_BinaryPatch_##TokenName\r
\r
/**\r
Retrieves a pointer to a binary patchable PCD token buffer based on a token name.\r
@return A pointer to the buffer for the token.\r
\r
**/\r
-#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName)\r
-\r
+#define PatchPcdGetPtr(TokenName) ((VOID *)_gPcd_BinaryPatch_##TokenName)\r
\r
/**\r
Sets an 8-bit binary patchable PCD token value based on a token name.\r
@return Return the Value that was set.\r
\r
**/\r
-#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
-\r
+#define PatchPcdSet8(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
\r
/**\r
Sets a 16-bit binary patchable PCD token value based on a token name.\r
@return Return the Value that was set.\r
\r
**/\r
-#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
-\r
+#define PatchPcdSet16(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
\r
/**\r
Sets a 32-bit binary patchable PCD token value based on a token name.\r
@return Return the Value that was set.\r
\r
**/\r
-#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
-\r
+#define PatchPcdSet32(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
\r
/**\r
Sets a 64-bit binary patchable PCD token value based on a token name.\r
@return Return the Value that was set.\r
\r
**/\r
-#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
-\r
+#define PatchPcdSet64(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
\r
/**\r
Sets a Boolean binary patchable PCD token value based on a token name.\r
@return Return the Value that was set.\r
\r
**/\r
-#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
-\r
+#define PatchPcdSetBool(TokenName, Value) (_gPcd_BinaryPatch_##TokenName = (Value))\r
\r
/**\r
Sets a pointer to a binary patchable PCD token buffer based on a token name.\r
(Size), \\r
(Buffer) \\r
)\r
+\r
/**\r
Retrieves an 8-bit PCD token value based on a token name.\r
\r
@return 8-bit value for the token specified by TokenName.\r
\r
**/\r
-#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName\r
-\r
+#define PcdGet8(TokenName) _PCD_GET_MODE_8_##TokenName\r
\r
/**\r
Retrieves a 16-bit PCD token value based on a token name.\r
@return 16-bit value for the token specified by TokenName.\r
\r
**/\r
-#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName\r
-\r
+#define PcdGet16(TokenName) _PCD_GET_MODE_16_##TokenName\r
\r
/**\r
Retrieves a 32-bit PCD token value based on a token name.\r
@return 32-bit value for the token specified by TokenName.\r
\r
**/\r
-#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName\r
-\r
+#define PcdGet32(TokenName) _PCD_GET_MODE_32_##TokenName\r
\r
/**\r
Retrieves a 64-bit PCD token value based on a token name.\r
@return 64-bit value for the token specified by TokenName.\r
\r
**/\r
-#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName\r
-\r
+#define PcdGet64(TokenName) _PCD_GET_MODE_64_##TokenName\r
\r
/**\r
Retrieves a pointer to a PCD token buffer based on a token name.\r
@return A pointer to the buffer.\r
\r
**/\r
-#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName\r
-\r
+#define PcdGetPtr(TokenName) _PCD_GET_MODE_PTR_##TokenName\r
\r
/**\r
Retrieves a Boolean PCD token value based on a token name.\r
@return A Boolean PCD token value.\r
\r
**/\r
-#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName\r
-\r
+#define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName\r
\r
/**\r
Retrieves the size of a fixed PCD token based on a token name.\r
@return Return the size\r
\r
**/\r
-#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName\r
-\r
+#define FixedPcdGetSize(TokenName) _PCD_SIZE_##TokenName\r
\r
/**\r
Retrieves the size of a binary patchable PCD token based on a token name.\r
@return Return the size\r
\r
**/\r
-#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName\r
-\r
+#define PatchPcdGetSize(TokenName) _gPcd_BinaryPatch_Size_##TokenName\r
\r
/**\r
Retrieves the size of the PCD token based on a token name.\r
@return Return the size\r
\r
**/\r
-#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName\r
-\r
+#define PcdGetSize(TokenName) _PCD_GET_MODE_SIZE_##TokenName\r
\r
/**\r
Retrieve the size of a given PCD token.\r
@return Return the size.\r
\r
**/\r
-#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName))\r
+#define PcdGetExSize(Guid, TokenName) LibPcdGetExSize ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Sets a 8-bit PCD token value based on a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value))\r
+#define PcdSet8S(TokenName, Value) _PCD_SET_MODE_8_S_##TokenName ((Value))\r
\r
/**\r
Sets a 16-bit PCD token value based on a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value))\r
+#define PcdSet16S(TokenName, Value) _PCD_SET_MODE_16_S_##TokenName ((Value))\r
\r
/**\r
Sets a 32-bit PCD token value based on a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value))\r
+#define PcdSet32S(TokenName, Value) _PCD_SET_MODE_32_S_##TokenName ((Value))\r
\r
/**\r
Sets a 64-bit PCD token value based on a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value))\r
+#define PcdSet64S(TokenName, Value) _PCD_SET_MODE_64_S_##TokenName ((Value))\r
\r
/**\r
Sets a pointer to a PCD token buffer based on a token name.\r
#define PcdSetPtrS(TokenName, SizeOfBuffer, Buffer) \\r
_PCD_SET_MODE_PTR_S_##TokenName ((SizeOfBuffer), (Buffer))\r
\r
-\r
-\r
/**\r
Sets a boolean PCD token value based on a token name.\r
\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value))\r
+#define PcdSetBoolS(TokenName, Value) _PCD_SET_MODE_BOOL_S_##TokenName ((Value))\r
\r
/**\r
Retrieves a token number based on a GUID and a token name.\r
@return Return the token number.\r
\r
**/\r
-#define PcdTokenEx(Guid,TokenName) _PCD_TOKEN_EX_##TokenName(Guid)\r
+#define PcdTokenEx(Guid, TokenName) _PCD_TOKEN_EX_##TokenName(Guid)\r
\r
/**\r
Retrieves an 8-bit PCD token value based on a GUID and a token name.\r
@return An 8-bit PCD token value.\r
\r
**/\r
-#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName))\r
+#define PcdGetEx8(Guid, TokenName) LibPcdGetEx8 ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Retrieves a 16-bit PCD token value based on a GUID and a token name.\r
@return A 16-bit PCD token value.\r
\r
**/\r
-#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName))\r
-\r
+#define PcdGetEx16(Guid, TokenName) LibPcdGetEx16 ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Retrieves a 32-bit PCD token value based on a GUID and a token name.\r
@return A 32-bit PCD token value.\r
\r
**/\r
-#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName))\r
-\r
+#define PcdGetEx32(Guid, TokenName) LibPcdGetEx32 ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Retrieves a 64-bit PCD token value based on a GUID and a token name.\r
@return A 64-bit PCD token value.\r
\r
**/\r
-#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName))\r
-\r
+#define PcdGetEx64(Guid, TokenName) LibPcdGetEx64 ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Retrieves a pointer to a PCD token buffer based on a GUID and a token name.\r
@return A pointer to a PCD token buffer.\r
\r
**/\r
-#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName))\r
-\r
+#define PcdGetExPtr(Guid, TokenName) LibPcdGetExPtr ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Retrieves a Boolean PCD token value based on a GUID and a token name.\r
@return A Boolean PCD token value.\r
\r
**/\r
-#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName))\r
-\r
-\r
+#define PcdGetExBool(Guid, TokenName) LibPcdGetExBool ((Guid), PcdTokenEx(Guid,TokenName))\r
\r
/**\r
Sets an 8-bit PCD token value based on a GUID and a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
+#define PcdSetEx8S(Guid, TokenName, Value) LibPcdSetEx8S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
\r
/**\r
Sets an 16-bit PCD token value based on a GUID and a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
+#define PcdSetEx16S(Guid, TokenName, Value) LibPcdSetEx16S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
\r
/**\r
Sets an 32-bit PCD token value based on a GUID and a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
+#define PcdSetEx32S(Guid, TokenName, Value) LibPcdSetEx32S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
\r
/**\r
Sets an 64-bit PCD token value based on a GUID and a token name.\r
@return The status of the set operation.\r
\r
**/\r
-#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
+#define PcdSetEx64S(Guid, TokenName, Value) LibPcdSetEx64S ((Guid), PcdTokenEx(Guid,TokenName), (Value))\r
\r
/**\r
Sets a pointer to a PCD token buffer based on a GUID and a token name.\r
#define PcdSetExPtrS(Guid, TokenName, SizeOfBuffer, Buffer) \\r
LibPcdSetExPtrS ((Guid), PcdTokenEx(Guid,TokenName), (SizeOfBuffer), (Buffer))\r
\r
-\r
/**\r
Sets an boolean PCD token value based on a GUID and a token name.\r
\r
UINTN\r
EFIAPI\r
LibPcdSetSku (\r
- IN UINTN SkuId\r
+ IN UINTN SkuId\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGet8 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGet16 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT32\r
EFIAPI\r
LibPcdGet32 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGet64 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetPtr (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetBool (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetSize (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGetEx8 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGetEx16 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
Returns the 32-bit value for the token specified by TokenNumber and Guid.\r
If Guid is NULL, then ASSERT().\r
UINT32\r
EFIAPI\r
LibPcdGetEx32 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGetEx64 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetExPtr (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetExBool (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetExSize (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
/**\r
This function provides a means by which to set a value for a given PCD token.\r
\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet8S (\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet16S (\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet32S (\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet64S (\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetPtrS (\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetBoolS (\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx8S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx16S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx32S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx64S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExPtrS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN VOID *Buffer\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN VOID *Buffer\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExBoolS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
);\r
\r
/**\r
IN UINTN TokenDataSize\r
);\r
\r
-\r
/**\r
Set up a notification function that is called when a specified token is set.\r
\r
VOID\r
EFIAPI\r
LibPcdCallbackOnSet (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
);\r
\r
-\r
/**\r
Disable a notification function that was established with LibPcdCallbackonSet().\r
\r
VOID\r
EFIAPI\r
LibPcdCancelCallback (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
);\r
\r
-\r
/**\r
Retrieves the next token in a token space.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetNextToken (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Used to retrieve the list of available PCD token space GUIDs.\r
\r
IN CONST GUID *TokenSpaceGuid\r
);\r
\r
-\r
/**\r
Sets a value of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtr (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrS (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtrAndSize (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrAndSizeS (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
);\r
\r
typedef enum {\r
/// The returned information associated with the requested TokenNumber. If\r
/// TokenNumber is 0, then PcdType is set to PCD_TYPE_8.\r
///\r
- PCD_TYPE PcdType;\r
+ PCD_TYPE PcdType;\r
///\r
/// The size of the data in bytes associated with the TokenNumber specified. If\r
/// TokenNumber is 0, then PcdSize is set 0.\r
///\r
- UINTN PcdSize;\r
+ UINTN PcdSize;\r
///\r
/// The null-terminated ASCII string associated with a given token. If the\r
/// TokenNumber specified was 0, then this field corresponds to the null-terminated\r
/// ASCII string associated with the token's namespace Guid. If NULL, there is no\r
/// name associated with this request.\r
///\r
- CHAR8 *PcdName;\r
+ CHAR8 *PcdName;\r
} PCD_INFO;\r
\r
-\r
/**\r
Retrieve additional information associated with a PCD token.\r
\r
VOID\r
EFIAPI\r
LibPcdGetInfo (\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
LibPcdGetInfoEx (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
);\r
\r
/**\r
#ifndef __PCI_CF8_LIB_H__\r
#define __PCI_CF8_LIB_H__\r
\r
-\r
/**\r
Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r
address that can be passed to the PCI Library functions.\r
@return The encode PCI address.\r
\r
**/\r
-#define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r
+#define PCI_CF8_LIB_ADDRESS(Bus, Device, Function, Offset) \\r
(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8Read8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8Write8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8Or8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8And8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8AndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8BitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8Read16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8Write16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8Or16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8And16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8AndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciCf8BitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8Read32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8Write32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8Or32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8And32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8AndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciCf8BitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciCf8ReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciCf8WriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
@return The encode PCI address.\r
\r
**/\r
-#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))\r
+#define PCI_EXPRESS_LIB_ADDRESS(Bus, Device, Function, Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))\r
\r
/**\r
Registers a PCI device so PCI configuration registers may be accessed after\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
@return The encoded PCI address.\r
\r
**/\r
-#define PCI_LIB_ADDRESS(Bus,Device,Function,Register) \\r
+#define PCI_LIB_ADDRESS(Bus, Device, Function, Register) \\r
(((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
/**\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
#define __PCI_SEGMENT_INFO_LIB__\r
\r
typedef struct {\r
- UINT16 SegmentNumber; ///< Segment number.\r
- UINT64 BaseAddress; ///< ECAM Base address.\r
- UINT8 StartBusNumber; ///< Start BUS number, for verifying the PCI Segment address.\r
- UINT8 EndBusNumber; ///< End BUS number, for verifying the PCI Segment address.\r
+ UINT16 SegmentNumber; ///< Segment number.\r
+ UINT64 BaseAddress; ///< ECAM Base address.\r
+ UINT8 StartBusNumber; ///< Start BUS number, for verifying the PCI Segment address.\r
+ UINT8 EndBusNumber; ///< End BUS number, for verifying the PCI Segment address.\r
} PCI_SEGMENT_INFO;\r
\r
/**\r
#ifndef __PCI_SEGMENT_LIB__\r
#define __PCI_SEGMENT_LIB__\r
\r
-\r
/**\r
Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r
and PCI Register to an address that can be passed to the PCI Segment Library functions.\r
@return The address that is compatible with the PCI Segment Library functions.\r
\r
**/\r
-#define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
+#define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \\r
((Segment != 0) ? \\r
( ((Register) & 0xfff) | \\r
(((Function) & 0x07) << 12) | \\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
IN VOID *Pe32Data\r
);\r
\r
-\r
/**\r
Returns the size of the PE/COFF headers\r
\r
UINT32\r
EFIAPI\r
PeCoffGetSizeOfHeaders (\r
- IN VOID *Pe32Data\r
+ IN VOID *Pe32Data\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
PeCoffSearchImageBase (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
#endif\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the ImageBase in the PE/COFF header.\r
///\r
- PHYSICAL_ADDRESS ImageAddress;\r
+ PHYSICAL_ADDRESS ImageAddress;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the SizeOfImage in the PE/COFF header.\r
/// Image size includes the size of Debug Entry if it is present.\r
///\r
- UINT64 ImageSize;\r
+ UINT64 ImageSize;\r
///\r
/// Is set to zero by PeCoffLoaderGetImageInfo(). If DestinationAddress is non-zero,\r
/// PeCoffLoaderRelocateImage() will relocate the image using this base address.\r
/// If the DestinationAddress is zero, the ImageAddress will be used as the base\r
/// address of relocation.\r
///\r
- PHYSICAL_ADDRESS DestinationAddress;\r
+ PHYSICAL_ADDRESS DestinationAddress;\r
///\r
/// PeCoffLoaderLoadImage() sets EntryPoint to to the entry point of the PE/COFF image.\r
///\r
- PHYSICAL_ADDRESS EntryPoint;\r
+ PHYSICAL_ADDRESS EntryPoint;\r
///\r
/// Passed in by the caller to PeCoffLoaderGetImageInfo() and PeCoffLoaderLoadImage()\r
/// to abstract accessing the image from the library.\r
///\r
- PE_COFF_LOADER_READ_FILE ImageRead;\r
+ PE_COFF_LOADER_READ_FILE ImageRead;\r
///\r
/// Used as the FileHandle passed into the ImageRead function when it's called.\r
///\r
- VOID *Handle;\r
+ VOID *Handle;\r
///\r
/// Caller allocated buffer of size FixupDataSize that can be optionally allocated\r
/// prior to calling PeCoffLoaderRelocateImage().\r
/// This buffer is filled with the information used to fix up the image.\r
/// The fixups have been applied to the image and this entry is just for information.\r
///\r
- VOID *FixupData;\r
+ VOID *FixupData;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header.\r
/// If the image is a TE image, then this field is set to 0.\r
///\r
- UINT32 SectionAlignment;\r
+ UINT32 SectionAlignment;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to offset to the PE/COFF header.\r
/// If the PE/COFF image does not start with a DOS header, this value is zero.\r
/// Otherwise, it's the offset to the PE/COFF header.\r
///\r
- UINT32 PeCoffHeaderOffset;\r
+ UINT32 PeCoffHeaderOffset;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the Relative Virtual Address of the debug directory,\r
/// if it exists in the image\r
///\r
- UINT32 DebugDirectoryEntryRva;\r
+ UINT32 DebugDirectoryEntryRva;\r
///\r
/// Set by PeCoffLoaderLoadImage() to CodeView area of the PE/COFF Debug directory.\r
///\r
- VOID *CodeView;\r
+ VOID *CodeView;\r
///\r
/// Set by PeCoffLoaderLoadImage() to point to the PDB entry contained in the CodeView area.\r
/// The PdbPointer points to the filename of the PDB file used for source-level debug of\r
/// the image by a debugger.\r
///\r
- CHAR8 *PdbPointer;\r
+ CHAR8 *PdbPointer;\r
///\r
/// Is set by PeCoffLoaderGetImageInfo() to the Section Alignment in the PE/COFF header.\r
///\r
- UINTN SizeOfHeaders;\r
+ UINTN SizeOfHeaders;\r
///\r
/// Not used by this library class. Other library classes that layer on top of this library\r
/// class fill in this value as part of their GetImageInfo call.\r
/// This allows the caller of the library to know what type of memory needs to be allocated\r
/// to load and relocate the image.\r
///\r
- UINT32 ImageCodeMemoryType;\r
+ UINT32 ImageCodeMemoryType;\r
///\r
/// Not used by this library class. Other library classes that layer on top of this library\r
/// class fill in this value as part of their GetImageInfo call.\r
/// This allows the caller of the library to know what type of memory needs to be allocated\r
/// to load and relocate the image.\r
///\r
- UINT32 ImageDataMemoryType;\r
+ UINT32 ImageDataMemoryType;\r
///\r
/// Set by any of the library functions if they encounter an error.\r
///\r
- UINT32 ImageError;\r
+ UINT32 ImageError;\r
///\r
/// Set by PeCoffLoaderLoadImage() to indicate the size of FixupData that the caller must\r
/// allocate before calling PeCoffLoaderRelocateImage().\r
///\r
- UINTN FixupDataSize;\r
+ UINTN FixupDataSize;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the machine type stored in the PE/COFF header.\r
///\r
- UINT16 Machine;\r
+ UINT16 Machine;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to the subsystem type stored in the PE/COFF header.\r
///\r
- UINT16 ImageType;\r
+ UINT16 ImageType;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to TRUE if the PE/COFF image does not contain\r
/// relocation information.\r
///\r
- BOOLEAN RelocationsStripped;\r
+ BOOLEAN RelocationsStripped;\r
///\r
/// Set by PeCoffLoaderGetImageInfo() to TRUE if the image is a TE image.\r
/// For a definition of the TE Image format, see the Platform Initialization Pre-EFI\r
/// Initialization Core Interface Specification.\r
///\r
- BOOLEAN IsTeImage;\r
+ BOOLEAN IsTeImage;\r
///\r
/// Set by PeCoffLoaderLoadImage() to the HII resource offset\r
/// if the image contains a custom PE/COFF resource with the type 'HII'.\r
/// Otherwise, the entry remains to be 0.\r
///\r
- PHYSICAL_ADDRESS HiiResourceData;\r
+ PHYSICAL_ADDRESS HiiResourceData;\r
///\r
/// Private storage for implementation specific data.\r
///\r
- UINT64 Context;\r
+ UINT64 Context;\r
} PE_COFF_LOADER_IMAGE_CONTEXT;\r
\r
/**\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
);\r
\r
-\r
/**\r
Reads contents of a PE/COFF image from a buffer in system memory.\r
\r
RETURN_STATUS\r
EFIAPI\r
PeCoffLoaderImageReadFromMemory (\r
- IN VOID *FileHandle,\r
- IN UINTN FileOffset,\r
- IN OUT UINTN *ReadSize,\r
- OUT VOID *Buffer\r
+ IN VOID *FileHandle,\r
+ IN UINTN FileOffset,\r
+ IN OUT UINTN *ReadSize,\r
+ OUT VOID *Buffer\r
);\r
\r
-\r
/**\r
Reapply fixups on a fixed up PE32/PE32+ image to allow virtual calling at EFI\r
runtime.\r
VOID\r
EFIAPI\r
PeCoffLoaderRelocateImageForRuntime (\r
- IN PHYSICAL_ADDRESS ImageBase,\r
- IN PHYSICAL_ADDRESS VirtImageBase,\r
- IN UINTN ImageSize,\r
- IN VOID *RelocationData\r
+ IN PHYSICAL_ADDRESS ImageBase,\r
+ IN PHYSICAL_ADDRESS VirtImageBase,\r
+ IN UINTN ImageSize,\r
+ IN VOID *RelocationData\r
);\r
\r
/**\r
PeCoffLoaderUnloadImage (\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
);\r
+\r
#endif\r
**/\r
VOID\r
EFIAPI\r
-_ModuleEntryPoint(\r
+_ModuleEntryPoint (\r
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
);\r
VOID\r
EFIAPI\r
ProcessLibraryConstructorList (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
);\r
\r
-\r
/**\r
Autogenerated function that calls a set of module entry points.\r
\r
EFI_STATUS\r
EFIAPI\r
PeiServicesInstallPpi (\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesReInstallPpi (\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesLocatePpi (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN Instance,\r
- IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,\r
- IN OUT VOID **Ppi\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN Instance,\r
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,\r
+ IN OUT VOID **Ppi\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesGetBootMode (\r
- OUT EFI_BOOT_MODE *BootMode\r
+ OUT EFI_BOOT_MODE *BootMode\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesSetBootMode (\r
- IN EFI_BOOT_MODE BootMode\r
+ IN EFI_BOOT_MODE BootMode\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesGetHobList (\r
- OUT VOID **HobList\r
+ OUT VOID **HobList\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesCreateHob (\r
- IN UINT16 Type,\r
- IN UINT16 Length,\r
- OUT VOID **Hob\r
+ IN UINT16 Type,\r
+ IN UINT16 Length,\r
+ OUT VOID **Hob\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindNextVolume (\r
- IN UINTN Instance,\r
- IN OUT EFI_PEI_FV_HANDLE *VolumeHandle\r
+ IN UINTN Instance,\r
+ IN OUT EFI_PEI_FV_HANDLE *VolumeHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindNextFile (\r
- IN EFI_FV_FILETYPE SearchType,\r
- IN EFI_PEI_FV_HANDLE VolumeHandle,\r
- IN OUT EFI_PEI_FILE_HANDLE *FileHandle\r
+ IN EFI_FV_FILETYPE SearchType,\r
+ IN EFI_PEI_FV_HANDLE VolumeHandle,\r
+ IN OUT EFI_PEI_FILE_HANDLE *FileHandle\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindSectionData (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT VOID **SectionData\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT VOID **SectionData\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindSectionData3 (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT VOID **SectionData,\r
- OUT UINT32 *AuthenticationStatus\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT VOID **SectionData,\r
+ OUT UINT32 *AuthenticationStatus\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesInstallPeiMemory (\r
- IN EFI_PHYSICAL_ADDRESS MemoryBegin,\r
- IN UINT64 MemoryLength\r
+ IN EFI_PHYSICAL_ADDRESS MemoryBegin,\r
+ IN UINT64 MemoryLength\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesAllocatePages (\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT EFI_PHYSICAL_ADDRESS *Memory\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT EFI_PHYSICAL_ADDRESS *Memory\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFreePages (\r
- IN EFI_PHYSICAL_ADDRESS Memory,\r
- IN UINTN Pages\r
+ IN EFI_PHYSICAL_ADDRESS Memory,\r
+ IN UINTN Pages\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesAllocatePool (\r
- IN UINTN Size,\r
- OUT VOID **Buffer\r
+ IN UINTN Size,\r
+ OUT VOID **Buffer\r
);\r
\r
/**\r
VOID\r
);\r
\r
-\r
/**\r
This service is a wrapper for the PEI Service FfsFindByName(), except the pointer to the PEI Services\r
Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindFileByName (\r
- IN CONST EFI_GUID *FileName,\r
- IN CONST EFI_PEI_FV_HANDLE VolumeHandle,\r
- OUT EFI_PEI_FILE_HANDLE *FileHandle\r
+ IN CONST EFI_GUID *FileName,\r
+ IN CONST EFI_PEI_FV_HANDLE VolumeHandle,\r
+ OUT EFI_PEI_FILE_HANDLE *FileHandle\r
);\r
\r
-\r
/**\r
This service is a wrapper for the PEI Service FfsGetFileInfo(), except the pointer to the PEI Services\r
Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetFileInfo (\r
- IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT EFI_FV_FILE_INFO *FileInfo\r
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT EFI_FV_FILE_INFO *FileInfo\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetFileInfo2 (\r
- IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT EFI_FV_FILE_INFO2 *FileInfo\r
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT EFI_FV_FILE_INFO2 *FileInfo\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetVolumeInfo (\r
- IN EFI_PEI_FV_HANDLE VolumeHandle,\r
- OUT EFI_FV_INFO *VolumeInfo\r
+ IN EFI_PEI_FV_HANDLE VolumeHandle,\r
+ OUT EFI_FV_INFO *VolumeInfo\r
);\r
\r
-\r
/**\r
This service is a wrapper for the PEI Service RegisterForShadow(), except the pointer to the PEI Services\r
Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface\r
EFI_STATUS\r
EFIAPI\r
PeiServicesRegisterForShadow (\r
- IN EFI_PEI_FILE_HANDLE FileHandle\r
+ IN EFI_PEI_FILE_HANDLE FileHandle\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PeiServicesInstallFvInfoPpi (\r
- IN CONST EFI_GUID *FvFormat OPTIONAL,\r
- IN CONST VOID *FvInfo,\r
- IN UINT32 FvInfoSize,\r
- IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
- IN CONST EFI_GUID *ParentFileName OPTIONAL\r
+ IN CONST EFI_GUID *FvFormat OPTIONAL,\r
+ IN CONST VOID *FvInfo,\r
+ IN UINT32 FvInfoSize,\r
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
+ IN CONST EFI_GUID *ParentFileName OPTIONAL\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PeiServicesInstallFvInfo2Ppi (\r
- IN CONST EFI_GUID *FvFormat OPTIONAL,\r
- IN CONST VOID *FvInfo,\r
- IN UINT32 FvInfoSize,\r
- IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
- IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
- IN UINT32 AuthenticationStatus\r
+ IN CONST EFI_GUID *FvFormat OPTIONAL,\r
+ IN CONST VOID *FvInfo,\r
+ IN UINT32 FvInfoSize,\r
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
+ IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
+ IN UINT32 AuthenticationStatus\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PeiServicesResetSystem2 (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN VOID *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData OPTIONAL\r
);\r
\r
#endif\r
VOID\r
EFIAPI\r
SetPeiServicesTablePointer (\r
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer\r
);\r
\r
/**\r
);\r
\r
#endif\r
-\r
///\r
/// Declare the EFI/UEFI Specification Revision to which this driver is implemented\r
///\r
-extern CONST UINT32 _gPeimRevision;\r
-\r
+extern CONST UINT32 _gPeimRevision;\r
\r
/**\r
The entry point of PE/COFF Image for a PEIM.\r
EFI_STATUS\r
EFIAPI\r
_ModuleEntryPoint (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
);\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiMain (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
ProcessLibraryConstructorList (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
ProcessModuleEntryPointList (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
);\r
\r
#endif\r
//\r
// Public Progress Identifiers for Event Records.\r
//\r
-#define PERF_EVENT_ID 0x00\r
-\r
-#define MODULE_START_ID 0x01\r
-#define MODULE_END_ID 0x02\r
-#define MODULE_LOADIMAGE_START_ID 0x03\r
-#define MODULE_LOADIMAGE_END_ID 0x04\r
-#define MODULE_DB_START_ID 0x05\r
-#define MODULE_DB_END_ID 0x06\r
-#define MODULE_DB_SUPPORT_START_ID 0x07\r
-#define MODULE_DB_SUPPORT_END_ID 0x08\r
-#define MODULE_DB_STOP_START_ID 0x09\r
-#define MODULE_DB_STOP_END_ID 0x0A\r
-\r
-#define PERF_EVENTSIGNAL_START_ID 0x10\r
-#define PERF_EVENTSIGNAL_END_ID 0x11\r
-#define PERF_CALLBACK_START_ID 0x20\r
-#define PERF_CALLBACK_END_ID 0x21\r
-#define PERF_FUNCTION_START_ID 0x30\r
-#define PERF_FUNCTION_END_ID 0x31\r
-#define PERF_INMODULE_START_ID 0x40\r
-#define PERF_INMODULE_END_ID 0x41\r
-#define PERF_CROSSMODULE_START_ID 0x50\r
-#define PERF_CROSSMODULE_END_ID 0x51\r
+#define PERF_EVENT_ID 0x00\r
+\r
+#define MODULE_START_ID 0x01\r
+#define MODULE_END_ID 0x02\r
+#define MODULE_LOADIMAGE_START_ID 0x03\r
+#define MODULE_LOADIMAGE_END_ID 0x04\r
+#define MODULE_DB_START_ID 0x05\r
+#define MODULE_DB_END_ID 0x06\r
+#define MODULE_DB_SUPPORT_START_ID 0x07\r
+#define MODULE_DB_SUPPORT_END_ID 0x08\r
+#define MODULE_DB_STOP_START_ID 0x09\r
+#define MODULE_DB_STOP_END_ID 0x0A\r
+\r
+#define PERF_EVENTSIGNAL_START_ID 0x10\r
+#define PERF_EVENTSIGNAL_END_ID 0x11\r
+#define PERF_CALLBACK_START_ID 0x20\r
+#define PERF_CALLBACK_END_ID 0x21\r
+#define PERF_FUNCTION_START_ID 0x30\r
+#define PERF_FUNCTION_END_ID 0x31\r
+#define PERF_INMODULE_START_ID 0x40\r
+#define PERF_INMODULE_END_ID 0x41\r
+#define PERF_CROSSMODULE_START_ID 0x50\r
+#define PERF_CROSSMODULE_END_ID 0x51\r
\r
//\r
// Declare bits for PcdPerformanceLibraryPropertyMask and\r
// also used as the Type parameter of LogPerformanceMeasurementEnabled().\r
//\r
-#define PERF_CORE_START_IMAGE 0x0002\r
-#define PERF_CORE_LOAD_IMAGE 0x0004\r
-#define PERF_CORE_DB_SUPPORT 0x0008\r
-#define PERF_CORE_DB_START 0x0010\r
-#define PERF_CORE_DB_STOP 0x0020\r
+#define PERF_CORE_START_IMAGE 0x0002\r
+#define PERF_CORE_LOAD_IMAGE 0x0004\r
+#define PERF_CORE_DB_SUPPORT 0x0008\r
+#define PERF_CORE_DB_START 0x0010\r
+#define PERF_CORE_DB_STOP 0x0020\r
\r
-#define PERF_GENERAL_TYPE 0x0040\r
+#define PERF_GENERAL_TYPE 0x0040\r
\r
/**\r
Creates a record for the beginning of a performance measurement.\r
UINTN\r
EFIAPI\r
GetPerformanceMeasurement (\r
- IN UINTN LogEntryKey,\r
- OUT CONST VOID **Handle,\r
- OUT CONST CHAR8 **Token,\r
- OUT CONST CHAR8 **Module,\r
- OUT UINT64 *StartTimeStamp,\r
- OUT UINT64 *EndTimeStamp\r
+ IN UINTN LogEntryKey,\r
+ OUT CONST VOID **Handle,\r
+ OUT CONST CHAR8 **Token,\r
+ OUT CONST CHAR8 **Module,\r
+ OUT UINT64 *StartTimeStamp,\r
+ OUT UINT64 *EndTimeStamp\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
GetPerformanceMeasurementEx (\r
- IN UINTN LogEntryKey,\r
- OUT CONST VOID **Handle,\r
- OUT CONST CHAR8 **Token,\r
- OUT CONST CHAR8 **Module,\r
- OUT UINT64 *StartTimeStamp,\r
- OUT UINT64 *EndTimeStamp,\r
- OUT UINT32 *Identifier\r
+ IN UINTN LogEntryKey,\r
+ OUT CONST VOID **Handle,\r
+ OUT CONST CHAR8 **Token,\r
+ OUT CONST CHAR8 **Module,\r
+ OUT UINT64 *StartTimeStamp,\r
+ OUT UINT64 *EndTimeStamp,\r
+ OUT UINT32 *Identifier\r
);\r
\r
/**\r
VOID\r
);\r
\r
-\r
/**\r
Check whether the specified performance measurement can be logged.\r
\r
BOOLEAN\r
EFIAPI\r
LogPerformanceMeasurementEnabled (\r
- IN CONST UINTN Type\r
+ IN CONST UINTN Type\r
);\r
\r
/**\r
Otherwise, the source lines between PERF_CODE_BEGIN() and PERF_CODE_END() are not included in a module.\r
\r
**/\r
-#define PERF_CODE_END() __PerformanceCodeLocal = 0; __PerformanceCodeLocal++; } } while (FALSE)\r
+#define PERF_CODE_END() __PerformanceCodeLocal = 0; __PerformanceCodeLocal++; } } while (FALSE)\r
\r
/**\r
Macro that declares a section of performance measurement source code.\r
Expression \\r
PERF_CODE_END ()\r
\r
-\r
#endif\r
IN UINT32 Value\r
);\r
\r
-\r
/**\r
Sends a 32-bit value to a POST and associated ASCII string.\r
\r
IN CONST CHAR8 *Description OPTIONAL\r
);\r
\r
-\r
/**\r
Returns TRUE if POST Codes are enabled.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if POST code descriptions are enabled.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Sends a 32-bit value to a POST card.\r
\r
\r
@return Value The 32-bit value to write to the POST card.\r
**/\r
-#define POST_CODE_WITH_DESCRIPTION(Value,Description) \\r
+#define POST_CODE_WITH_DESCRIPTION(Value, Description) \\r
PostCodeEnabled() ? \\r
(PostCodeDescriptionEnabled() ? \\r
PostCodeWithDescription(Value,Description) : \\r
/// Flags bitmask values use in UnicodeValueToString() and\r
/// AsciiValueToString()\r
///\r
-#define LEFT_JUSTIFY 0x01\r
-#define COMMA_TYPE 0x08\r
-#define PREFIX_ZERO 0x20\r
-#define RADIX_HEX 0x80\r
+#define LEFT_JUSTIFY 0x01\r
+#define COMMA_TYPE 0x08\r
+#define PREFIX_ZERO 0x20\r
+#define RADIX_HEX 0x80\r
\r
/**\r
Produces a Null-terminated Unicode string in an output buffer based on\r
UINTN\r
EFIAPI\r
AsciiVSPrint (\r
- OUT CHAR8 *StartOfBuffer,\r
- IN UINTN BufferSize,\r
- IN CONST CHAR8 *FormatString,\r
- IN VA_LIST Marker\r
+ OUT CHAR8 *StartOfBuffer,\r
+ IN UINTN BufferSize,\r
+ IN CONST CHAR8 *FormatString,\r
+ IN VA_LIST Marker\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
AsciiBSPrint (\r
- OUT CHAR8 *StartOfBuffer,\r
- IN UINTN BufferSize,\r
- IN CONST CHAR8 *FormatString,\r
- IN BASE_LIST Marker\r
+ OUT CHAR8 *StartOfBuffer,\r
+ IN UINTN BufferSize,\r
+ IN CONST CHAR8 *FormatString,\r
+ IN BASE_LIST Marker\r
);\r
\r
/**\r
...\r
);\r
\r
-\r
/**\r
Converts a decimal value to a Null-terminated Ascii string.\r
\r
RETURN_STATUS\r
EFIAPI\r
AsciiValueToStringS (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN BufferSize,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
SPrintLength (\r
- IN CONST CHAR16 *FormatString,\r
+ IN CONST CHAR16 *FormatString,\r
IN VA_LIST Marker\r
);\r
\r
UINTN\r
EFIAPI\r
SPrintLengthAsciiFormat (\r
- IN CONST CHAR8 *FormatString,\r
- IN VA_LIST Marker\r
+ IN CONST CHAR8 *FormatString,\r
+ IN VA_LIST Marker\r
);\r
\r
#endif\r
BOOLEAN\r
EFIAPI\r
FilterBeforeIoRead (\r
- IN FILTER_IO_WIDTH Width,\r
- IN UINTN Address,\r
- IN OUT VOID *Buffer\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN OUT VOID *Buffer\r
);\r
\r
/**\r
IN UINTN Address,\r
IN VOID *Buffer\r
);\r
+\r
/**\r
Filter IO Write operation before wirte IO port.\r
It is used to filter IO operation.\r
IN VOID *Buffer\r
);\r
\r
- /**\r
- Trace IO Write operation after wirte IO port.\r
- It is used to trace IO operation.\r
+/**\r
+Trace IO Write operation after wirte IO port.\r
+It is used to trace IO operation.\r
\r
- @param[in] Width Signifies the width of the I/O operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Buffer The source buffer from which to BeforeWrite data.\r
+@param[in] Width Signifies the width of the I/O operation.\r
+@param[in] Address The base address of the I/O operation.\r
+@param[in] Buffer The source buffer from which to BeforeWrite data.\r
\r
**/\r
VOID\r
BOOLEAN\r
EFIAPI\r
FilterBeforeMsrRead (\r
- IN UINT32 Index,\r
- IN OUT UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN OUT UINT64 *Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FilterAfterMsrRead (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
FilterBeforeMsrWrite (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FilterAfterMsrWrite (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
);\r
\r
#endif // REGISTER_FILTER_LIB_H_\r
//\r
// Declare bits for PcdReportStatusCodePropertyMask\r
//\r
-#define REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED 0x00000001\r
-#define REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED 0x00000002\r
-#define REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED 0x00000004\r
+#define REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED 0x00000001\r
+#define REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED 0x00000002\r
+#define REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED 0x00000004\r
\r
/**\r
Converts a status code to an 8-bit POST code value.\r
OUT UINT8 *PostCode\r
);\r
\r
-\r
/**\r
Extracts ASSERT() information from a status code structure.\r
\r
OUT UINT32 *LineNumber\r
);\r
\r
-\r
/**\r
Extracts DEBUG() information from a status code structure.\r
\r
OUT CHAR8 **Format\r
);\r
\r
-\r
/**\r
Reports a status code.\r
\r
IN EFI_STATUS_CODE_VALUE Value\r
);\r
\r
-\r
/**\r
Reports a status code with a Device Path Protocol as the extended data.\r
\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
);\r
\r
-\r
/**\r
Reports a status code with an extended data buffer.\r
\r
IN UINTN ExtendedDataSize\r
);\r
\r
-\r
/**\r
Reports a status code with full parameters.\r
\r
IN UINTN ExtendedDataSize\r
);\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_PROGRESS_CODE are enabled\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_ERROR_CODE are enabled\r
\r
VOID\r
);\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_DEBUG_CODE are enabled\r
\r
VOID\r
);\r
\r
-\r
/**\r
Reports a status code with minimal parameters if the status code type is enabled.\r
\r
@retval EFI_UNSUPPORTED Report status code is not supported.\r
\r
**/\r
-#define REPORT_STATUS_CODE(Type,Value) \\r
+#define REPORT_STATUS_CODE(Type, Value) \\r
(ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \\r
ReportStatusCode(Type,Value) : \\r
(ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \\r
ReportStatusCode(Type,Value) : \\r
EFI_UNSUPPORTED\r
\r
-\r
/**\r
Reports a status code with a Device Path Protocol as the extended data if the\r
status code type is enabled.\r
is already in progress.\r
\r
**/\r
-#define REPORT_STATUS_CODE_WITH_DEVICE_PATH(Type,Value,DevicePathParameter) \\r
+#define REPORT_STATUS_CODE_WITH_DEVICE_PATH(Type, Value, DevicePathParameter) \\r
(ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \\r
ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \\r
(ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \\r
ReportStatusCodeWithDevicePath(Type,Value,DevicePathParameter) : \\r
EFI_UNSUPPORTED\r
\r
-\r
/**\r
Reports a status code with an extended data buffer if the status code type\r
is enabled.\r
is already in progress.\r
\r
**/\r
-#define REPORT_STATUS_CODE_WITH_EXTENDED_DATA(Type,Value,ExtendedData,ExtendedDataSize) \\r
+#define REPORT_STATUS_CODE_WITH_EXTENDED_DATA(Type, Value, ExtendedData, ExtendedDataSize) \\r
(ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \\r
ReportStatusCodeWithExtendedData(Type,Value,ExtendedData,ExtendedDataSize) : \\r
(ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \\r
is already in progress.\r
\r
**/\r
-#define REPORT_STATUS_CODE_EX(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) \\r
+#define REPORT_STATUS_CODE_EX(Type, Value, Instance, CallerId, ExtendedDataGuid, ExtendedData, ExtendedDataSize) \\r
(ReportProgressCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) ? \\r
ReportStatusCodeEx(Type,Value,Instance,CallerId,ExtendedDataGuid,ExtendedData,ExtendedDataSize) : \\r
(ReportErrorCodeEnabled() && ((Type) & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) ? \\r
RETURN_STATUS\r
EFIAPI\r
PublishSystemMemory (\r
- IN PHYSICAL_ADDRESS MemoryBegin,\r
- IN UINT64 MemoryLength\r
+ IN PHYSICAL_ADDRESS MemoryBegin,\r
+ IN UINT64 MemoryLength\r
);\r
\r
#endif\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber128 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
-#endif // __RNG_LIB_H__\r
+#endif // __RNG_LIB_H__\r
@return The encoded PCI address.\r
\r
**/\r
-#define S3_BOOT_SCRIPT_LIB_PCI_ADDRESS(Bus,Device,Function,Register) \\r
+#define S3_BOOT_SCRIPT_LIB_PCI_ADDRESS(Bus, Device, Function, Register) \\r
(UINT64) ( \\r
(((UINTN) Bus) << 24) | \\r
(((UINTN) Device) << 16) | \\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveDispatch (\r
- IN VOID *EntryPoint\r
+ IN VOID *EntryPoint\r
);\r
\r
/**\r
IN UINT32 InformationLength,\r
IN VOID *Information\r
);\r
+\r
/**\r
Adds a record for I/O reads the I/O location and continues when the exit criteria\r
is satisfied, or after a defined duration.\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveIoPoll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
IN VOID *Data,\r
IN VOID *DataMask,\r
- IN UINT64 Delay\r
+ IN UINT64 Delay\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciPoll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask,\r
- IN UINT64 Delay\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask,\r
+ IN UINT64 Delay\r
);\r
+\r
/**\r
Adds a record for PCI configuration space reads and continues when the exit criteria\r
is satisfied, or after a defined duration.\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePci2Poll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT16 Segment,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask,\r
- IN UINT64 Delay\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT16 Segment,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask,\r
+ IN UINT64 Delay\r
);\r
+\r
/**\r
Save ASCII string information specified by Buffer to boot script with opcode\r
EFI_BOOT_SCRIPT_INFORMATION_OPCODE.\r
@return the base address of the new copy of the boot script table.\r
\r
**/\r
-UINT8*\r
+UINT8 *\r
EFIAPI\r
S3BootScriptCloseTable (\r
VOID\r
S3BootScriptExecute (\r
VOID\r
);\r
+\r
/**\r
Move the last boot script entry to the position\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptMoveLastOpcode (\r
- IN BOOLEAN BeforeOrAfter,\r
- IN OUT VOID **Position OPTIONAL\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN OUT VOID **Position OPTIONAL\r
);\r
+\r
/**\r
Find a label within the boot script table and, if not present, optionally create it.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptLabel (\r
- IN BOOLEAN BeforeOrAfter,\r
- IN BOOLEAN CreateIfNotFound,\r
- IN OUT VOID **Position OPTIONAL,\r
- IN CONST CHAR8 *Label\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN BOOLEAN CreateIfNotFound,\r
+ IN OUT VOID **Position OPTIONAL,\r
+ IN CONST CHAR8 *Label\r
);\r
+\r
/**\r
Compare two positions in the boot script table and return their relative position.\r
@param Position1 The positions in the boot script table to compare\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptCompare (\r
- IN UINT8 *Position1,\r
- IN UINT8 *Position2,\r
- OUT UINTN *RelativePosition\r
+ IN UINT8 *Position1,\r
+ IN UINT8 *Position2,\r
+ OUT UINTN *RelativePosition\r
);\r
\r
#endif\r
UINT32\r
EFIAPI\r
S3MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
S3MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
S3MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
);\r
\r
/**\r
UINT64 *\r
EFIAPI\r
S3MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
);\r
\r
/**\r
UINT8 *\r
EFIAPI\r
S3MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
);\r
\r
/**\r
@return The encoded PCI address.\r
\r
**/\r
-#define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \\r
+#define S3_PCI_LIB_ADDRESS(Bus, Device, Function, Register) \\r
(((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r
\r
/**\r
#ifndef __S3_PCI_SEGMENT_LIB__\r
#define __S3_PCI_SEGMENT_LIB__\r
\r
-\r
/**\r
Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r
and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.\r
@return The address that is compatible with the PCI Segment Library functions.\r
\r
**/\r
-#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r
+#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \\r
((Segment != 0) ? \\r
( ((Register) & 0xfff) | \\r
(((Function) & 0x07) << 12) | \\r
UINT8\r
EFIAPI\r
S3PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
S3PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
S3PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
);\r
\r
#endif\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+\r
#ifndef __INT_SAFE_LIB_H__\r
#define __INT_SAFE_LIB_H__\r
\r
#define SafeIntnToChar16 SafeIntnToUint16\r
#define SafeUintnToChar16 SafeUintnToUint16\r
\r
-#define SafeChar16ToInt8 SafeUint16ToInt8\r
-#define SafeChar16ToUint8 SafeUint16ToUint8\r
-#define SafeChar16ToChar8 SafeUint16ToChar8\r
-#define SafeChar16ToInt16 SafeUint16ToInt16\r
+#define SafeChar16ToInt8 SafeUint16ToInt8\r
+#define SafeChar16ToUint8 SafeUint16ToUint8\r
+#define SafeChar16ToChar8 SafeUint16ToChar8\r
+#define SafeChar16ToInt16 SafeUint16ToInt16\r
\r
-#define SafeChar16Mult SafeUint16Mult\r
-#define SafeChar16Sub SafeUint16Sub\r
-#define SafeChar16Add SafeUint16Add\r
+#define SafeChar16Mult SafeUint16Mult\r
+#define SafeChar16Sub SafeUint16Sub\r
+#define SafeChar16Add SafeUint16Add\r
\r
//\r
// Conversion functions\r
RETURN_STATUS\r
EFIAPI\r
SafeInt16ToUint8 (\r
- IN INT16 Operand,\r
- OUT UINT8 *Result\r
+ IN INT16 Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SafeUint16ToUint8 (\r
- IN UINT16 Operand,\r
- OUT UINT8 *Result\r
+ IN UINT16 Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SafeInt32ToUint8 (\r
- IN INT32 Operand,\r
- OUT UINT8 *Result\r
+ IN INT32 Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
OUT UINT16 *Result\r
);\r
\r
-\r
/**\r
INT32 -> UINT32 conversion\r
\r
RETURN_STATUS\r
EFIAPI\r
SafeUint32ToUint8 (\r
- IN UINT32 Operand,\r
- OUT UINT8 *Result\r
+ IN UINT32 Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SafeIntnToUint8 (\r
- IN INTN Operand,\r
- OUT UINT8 *Result\r
+ IN INTN Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SafeUintnToUint8 (\r
- IN UINTN Operand,\r
- OUT UINT8 *Result\r
+ IN UINTN Operand,\r
+ OUT UINT8 *Result\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
SerialPortWrite (\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
);\r
\r
-\r
/**\r
Read data from serial device and save the datas in buffer.\r
\r
UINTN\r
EFIAPI\r
SerialPortRead (\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SerialPortSetControl (\r
- IN UINT32 Control\r
+ IN UINT32 Control\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SerialPortGetControl (\r
- OUT UINT32 *Control\r
+ OUT UINT32 *Control\r
);\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
SerialPortSetAttributes (\r
- IN OUT UINT64 *BaudRate,\r
- IN OUT UINT32 *ReceiveFifoDepth,\r
- IN OUT UINT32 *Timeout,\r
- IN OUT EFI_PARITY_TYPE *Parity,\r
- IN OUT UINT8 *DataBits,\r
- IN OUT EFI_STOP_BITS_TYPE *StopBits\r
+ IN OUT UINT64 *BaudRate,\r
+ IN OUT UINT32 *ReceiveFifoDepth,\r
+ IN OUT UINT32 *Timeout,\r
+ IN OUT EFI_PARITY_TYPE *Parity,\r
+ IN OUT UINT8 *DataBits,\r
+ IN OUT EFI_STOP_BITS_TYPE *StopBits\r
);\r
\r
#endif\r
@param Pec TRUE if Packet Error Checking is enabled. Otherwise FALSE.\r
\r
**/\r
-#define SMBUS_LIB_ADDRESS(SlaveAddress,Command,Length,Pec) \\r
+#define SMBUS_LIB_ADDRESS(SlaveAddress, Command, Length, Pec) \\r
( ((Pec) ? BIT22: 0) | \\r
(((SlaveAddress) & 0x7f) << 1) | \\r
(((Command) & 0xff) << 8) | \\r
\r
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC\r
**/\r
-#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)\r
+#define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress) (((SmBusAddress) >> 1) & 0x7f)\r
\r
/**\r
Macro that returns the SMBUS Command value from an SmBusAddress Parameter value.\r
\r
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC\r
**/\r
-#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)\r
+#define SMBUS_LIB_COMMAND(SmBusAddress) (((SmBusAddress) >> 8) & 0xff)\r
\r
/**\r
Macro that returns the SMBUS Data Length value from an SmBusAddress Parameter value.\r
\r
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC\r
**/\r
-#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)\r
+#define SMBUS_LIB_LENGTH(SmBusAddress) (((SmBusAddress) >> 16) & 0x3f)\r
\r
/**\r
Macro that returns the SMBUS PEC value from an SmBusAddress Parameter value.\r
\r
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC\r
**/\r
-#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))\r
+#define SMBUS_LIB_PEC(SmBusAddress) ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))\r
\r
/**\r
Macro that returns the set of reserved bits from an SmBusAddress Parameter value.\r
\r
@param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC\r
**/\r
-#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))\r
+#define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))\r
\r
/**\r
Executes an SMBUS quick read command.\r
VOID\r
EFIAPI\r
SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
);\r
\r
/**\r
OUT RETURN_STATUS *Status OPTIONAL\r
);\r
\r
-\r
#endif\r
EFI_STATUS\r
EFIAPI\r
SmiHandlerProfileRegisterHandler (\r
- IN EFI_GUID *HandlerGuid,\r
- IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
- IN PHYSICAL_ADDRESS CallerAddress,\r
- IN VOID *Context OPTIONAL,\r
- IN UINTN ContextSize OPTIONAL\r
+ IN EFI_GUID *HandlerGuid,\r
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
+ IN PHYSICAL_ADDRESS CallerAddress,\r
+ IN VOID *Context OPTIONAL,\r
+ IN UINTN ContextSize OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmiHandlerProfileUnregisterHandler (\r
- IN EFI_GUID *HandlerGuid,\r
- IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
- IN VOID *Context OPTIONAL,\r
- IN UINTN ContextSize OPTIONAL\r
+ IN EFI_GUID *HandlerGuid,\r
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
+ IN VOID *Context OPTIONAL,\r
+ IN UINTN ContextSize OPTIONAL\r
);\r
\r
#endif\r
#ifndef __SMM_LIB_H__\r
#define __SMM_LIB_H__\r
\r
-\r
/**\r
Triggers an SMI at boot time.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Triggers an SMI at run time.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Test if a boot time software SMI happened.\r
\r
VOID\r
);\r
\r
-\r
/**\r
Test if a run time software SMI happened.\r
\r
ClearSmi (\r
VOID\r
);\r
+\r
#endif\r
**/\r
typedef\r
VOID\r
-(EFIAPI *PERIODIC_SMI_LIBRARY_HANDLER) (\r
+(EFIAPI *PERIODIC_SMI_LIBRARY_HANDLER)(\r
IN CONST VOID *Context OPTIONAL,\r
IN UINT64 ElapsedTime\r
);\r
///\r
/// Cache pointer to the SMM Services Table\r
///\r
-extern EFI_SMM_SYSTEM_TABLE2 *gSmst;\r
+extern EFI_SMM_SYSTEM_TABLE2 *gSmst;\r
\r
/**\r
This function allows the caller to determine if the driver is executing in\r
/// Declare the PI Specification Revision that this driver requires to execute\r
/// correctly.\r
///\r
-extern CONST UINT32 _gMmRevision;\r
+extern CONST UINT32 _gMmRevision;\r
\r
///\r
/// Declare the number of unload handler in the image.\r
///\r
-extern CONST UINT8 _gDriverUnloadImageCount;\r
+extern CONST UINT8 _gDriverUnloadImageCount;\r
\r
/**\r
The entry point of PE/COFF Image for a Standalone MM Driver.\r
EFI_STATUS\r
EFIAPI\r
_ModuleEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
);\r
\r
-\r
/**\r
Auto generated function that calls the library constructors for all of the\r
module's dependent libraries.\r
VOID\r
EFIAPI\r
ProcessLibraryConstructorList (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
);\r
\r
-\r
/**\r
Auto generated function that calls the library descructors for all of the\r
module's dependent libraries.\r
VOID\r
EFIAPI\r
ProcessLibraryDestructorList (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
);\r
\r
-\r
/**\r
Auto generated function that calls a set of module entry points.\r
\r
EFI_STATUS\r
EFIAPI\r
ProcessModuleEntryPointList (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
);\r
\r
/**\r
///\r
/// Definitions for SPIN_LOCK\r
///\r
-typedef volatile UINTN SPIN_LOCK;\r
-\r
+typedef volatile UINTN SPIN_LOCK;\r
\r
/**\r
Retrieves the architecture-specific spin lock alignment requirements for\r
VOID\r
);\r
\r
-\r
/**\r
Initializes a spin lock to the released state and returns the spin lock.\r
\r
SPIN_LOCK *\r
EFIAPI\r
InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
+ OUT SPIN_LOCK *SpinLock\r
);\r
\r
-\r
/**\r
Waits until a spin lock can be placed in the acquired state.\r
\r
SPIN_LOCK *\r
EFIAPI\r
AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
);\r
\r
-\r
/**\r
Attempts to place a spin lock in the acquired state.\r
\r
BOOLEAN\r
EFIAPI\r
AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
);\r
\r
-\r
/**\r
Releases a spin lock.\r
\r
SPIN_LOCK *\r
EFIAPI\r
ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
);\r
\r
-\r
/**\r
Performs an atomic increment of a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InterlockedIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
);\r
\r
-\r
/**\r
Performs an atomic decrement of a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InterlockedDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 16-bit unsigned integer.\r
\r
UINT16\r
EFIAPI\r
InterlockedCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
InterlockedCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
UINT64\r
EFIAPI\r
InterlockedCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a pointer value.\r
\r
VOID *\r
EFIAPI\r
InterlockedCompareExchangePointer (\r
- IN OUT VOID * volatile *Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
+ IN OUT VOID *volatile *Value,\r
+ IN VOID *CompareValue,\r
+ IN VOID *ExchangeValue\r
);\r
\r
#endif\r
-\r
-\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
+ IN UINTN MicroSeconds\r
);\r
\r
/**\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
+ IN UINTN NanoSeconds\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue OPTIONAL,\r
- OUT UINT64 *EndValue OPTIONAL\r
+ OUT UINT64 *StartValue OPTIONAL,\r
+ OUT UINT64 *EndValue OPTIONAL\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
+ IN UINT64 Ticks\r
);\r
\r
#endif\r
///\r
/// Declare the EFI/UEFI Specification Revision to which this driver is implemented\r
///\r
-extern CONST UINT32 _gUefiDriverRevision;\r
-\r
+extern CONST UINT32 _gUefiDriverRevision;\r
\r
/**\r
Entry point to UEFI Application.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Invokes the library destructors for all dependent libraries and terminates\r
the UEFI Application.\r
IN EFI_STATUS Status\r
);\r
\r
-\r
/**\r
Autogenerated function that calls the library constructors for all of the module's\r
dependent libraries.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Autogenerated function that calls the library descructors for all of the module's\r
dependent libraries.\r
///\r
/// Cache the Image Handle\r
///\r
-extern EFI_HANDLE gImageHandle;\r
+extern EFI_HANDLE gImageHandle;\r
\r
///\r
/// Cache pointer to the EFI System Table\r
///\r
-extern EFI_SYSTEM_TABLE *gST;\r
+extern EFI_SYSTEM_TABLE *gST;\r
\r
///\r
/// Cache pointer to the EFI Boot Services Table\r
#define __MODULE_ENTRY_POINT_H__\r
\r
///\r
-///Declare the PI Specification Revision that this driver requires to execute correctly.\r
+/// Declare the PI Specification Revision that this driver requires to execute correctly.\r
///\r
-extern CONST UINT32 _gDxeRevision;\r
+extern CONST UINT32 _gDxeRevision;\r
\r
///\r
/// Declare the EFI/UEFI Specification Revision to which this driver is implemented\r
///\r
-extern CONST UINT32 _gUefiDriverRevision;\r
+extern CONST UINT32 _gUefiDriverRevision;\r
\r
///\r
/// Declare the number of unload handler in the image.\r
///\r
-extern CONST UINT8 _gDriverUnloadImageCount;\r
-\r
+extern CONST UINT8 _gDriverUnloadImageCount;\r
\r
/**\r
The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Invokes the library destructors for all dependent libraries and terminates the\r
DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.\r
IN EFI_STATUS Status\r
);\r
\r
-\r
/**\r
Autogenerated function that calls the library constructors for all of the module's\r
dependent libraries.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Autogenerated function that calls the library descructors for all of the module's\r
dependent libraries.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Autogenerated function that calls a set of module entry points.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
-\r
/**\r
Autogenerated function that calls a set of module unload handlers.\r
\r
/// Unicode String Table\r
///\r
typedef struct {\r
- CHAR8 *Language;\r
- CHAR16 *UnicodeString;\r
+ CHAR8 *Language;\r
+ CHAR16 *UnicodeString;\r
} EFI_UNICODE_STRING_TABLE;\r
\r
///\r
/// EFI Lock\r
///\r
typedef struct {\r
- EFI_TPL Tpl;\r
- EFI_TPL OwnerTpl;\r
- EFI_LOCK_STATE Lock;\r
+ EFI_TPL Tpl;\r
+ EFI_TPL OwnerTpl;\r
+ EFI_LOCK_STATE Lock;\r
} EFI_LOCK;\r
\r
/**\r
by Microseconds.\r
\r
**/\r
-#define EFI_TIMER_PERIOD_MICROSECONDS(Microseconds) MultU64x32((UINT64)(Microseconds), 10)\r
+#define EFI_TIMER_PERIOD_MICROSECONDS(Microseconds) MultU64x32((UINT64)(Microseconds), 10)\r
\r
/**\r
Macro that returns the number of 100 ns units for a specified number of milliseconds.\r
by Milliseconds.\r
\r
**/\r
-#define EFI_TIMER_PERIOD_MILLISECONDS(Milliseconds) MultU64x32((UINT64)(Milliseconds), 10000)\r
+#define EFI_TIMER_PERIOD_MILLISECONDS(Milliseconds) MultU64x32((UINT64)(Milliseconds), 10000)\r
\r
/**\r
Macro that returns the number of 100 ns units for a specified number of seconds.\r
by Seconds.\r
\r
**/\r
-#define EFI_TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)\r
+#define EFI_TIMER_PERIOD_SECONDS(Seconds) MultU64x32((UINT64)(Seconds), 10000000)\r
\r
/**\r
Macro that returns the a pointer to the next EFI_MEMORY_DESCRIPTOR in an array\r
**/\r
EFI_EVENT\r
EFIAPI\r
-EfiCreateProtocolNotifyEvent(\r
+EfiCreateProtocolNotifyEvent (\r
IN EFI_GUID *ProtocolGuid,\r
IN EFI_TPL NotifyTpl,\r
IN EFI_EVENT_NOTIFY NotifyFunction,\r
EFI_STATUS\r
EFIAPI\r
EfiEventGroupSignal (\r
- IN CONST EFI_GUID *EventGroup\r
+ IN CONST EFI_GUID *EventGroup\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
EfiEventEmptyFunction (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
);\r
\r
/**\r
EFIAPI\r
EfiInitializeLock (\r
IN OUT EFI_LOCK *Lock,\r
- IN EFI_TPL Priority\r
+ IN EFI_TPL Priority\r
);\r
\r
/**\r
#define EFI_INITIALIZE_LOCK_VARIABLE(Priority) \\r
{Priority, TPL_APPLICATION, EfiLockReleased }\r
\r
-\r
/**\r
Macro that calls DebugAssert() if an EFI_LOCK structure is not in the locked state.\r
\r
@param LockParameter A pointer to the lock to acquire.\r
\r
**/\r
-#if !defined(MDEPKG_NDEBUG)\r
- #define ASSERT_LOCKED(LockParameter) \\r
+#if !defined (MDEPKG_NDEBUG)\r
+#define ASSERT_LOCKED(LockParameter) \\r
do { \\r
if (DebugAssertEnabled ()) { \\r
ASSERT (LockParameter != NULL); \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT_LOCKED(LockParameter)\r
+#define ASSERT_LOCKED(LockParameter)\r
#endif\r
\r
-\r
/**\r
Acquires ownership of a lock.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiTestManagedDevice (\r
- IN CONST EFI_HANDLE ControllerHandle,\r
- IN CONST EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_GUID *ProtocolGuid\r
+ IN CONST EFI_HANDLE ControllerHandle,\r
+ IN CONST EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_GUID *ProtocolGuid\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiTestChildHandle (\r
- IN CONST EFI_HANDLE ControllerHandle,\r
- IN CONST EFI_HANDLE ChildHandle,\r
- IN CONST EFI_GUID *ProtocolGuid\r
+ IN CONST EFI_HANDLE ControllerHandle,\r
+ IN CONST EFI_HANDLE ChildHandle,\r
+ IN CONST EFI_GUID *ProtocolGuid\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
IsLanguageSupported (\r
- IN CONST CHAR8 *SupportedLanguages,\r
- IN CONST CHAR8 *TargetLanguage\r
+ IN CONST CHAR8 *SupportedLanguages,\r
+ IN CONST CHAR8 *TargetLanguage\r
);\r
\r
/**\r
IN EFI_UNICODE_STRING_TABLE *UnicodeStringTable\r
);\r
\r
-\r
/**\r
Returns the status whether get the variable success. The function retrieves\r
variable through the UEFI Runtime Service GetVariable(). The\r
EFI_STATUS\r
EFIAPI\r
GetEfiGlobalVariable2 (\r
- IN CONST CHAR16 *Name,\r
- OUT VOID **Value,\r
- OUT UINTN *Size OPTIONAL\r
+ IN CONST CHAR16 *Name,\r
+ OUT VOID **Value,\r
+ OUT UINTN *Size OPTIONAL\r
);\r
\r
/** Return the attributes of the variable.\r
**/\r
EFI_STATUS\r
EFIAPI\r
-GetVariable3(\r
- IN CONST CHAR16 *Name,\r
- IN CONST EFI_GUID *Guid,\r
- OUT VOID **Value,\r
- OUT UINTN *Size OPTIONAL,\r
- OUT UINT32 *Attr OPTIONAL\r
+GetVariable3 (\r
+ IN CONST CHAR16 *Name,\r
+ IN CONST EFI_GUID *Guid,\r
+ OUT VOID **Value,\r
+ OUT UINTN *Size OPTIONAL,\r
+ OUT UINT32 *Attr OPTIONAL\r
);\r
\r
/**\r
//\r
// Functions that abstract early Framework contamination of UEFI.\r
//\r
+\r
/**\r
Create, Signal, and Close the Ready to Boot event using EfiSignalEventReadyToBoot().\r
\r
...\r
);\r
\r
-\r
/**\r
Prints a formatted Unicode string to a graphics console device specified by\r
ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates.\r
UINTN\r
EFIAPI\r
PrintXY (\r
- IN UINTN PointX,\r
- IN UINTN PointY,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
- IN CONST CHAR16 *Format,\r
+ IN UINTN PointX,\r
+ IN UINTN PointY,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
+ IN CONST CHAR16 *Format,\r
...\r
);\r
\r
UINTN\r
EFIAPI\r
AsciiPrintXY (\r
- IN UINTN PointX,\r
- IN UINTN PointY,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
- IN CONST CHAR8 *Format,\r
+ IN UINTN PointX,\r
+ IN UINTN PointY,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
+ IN CONST CHAR8 *Format,\r
...\r
);\r
\r
-\r
/**\r
Installs and completes the initialization of a Driver Binding Protocol instance.\r
\r
IN EFI_HANDLE DriverBindingHandle\r
);\r
\r
-\r
/**\r
Uninstalls a Driver Binding Protocol instance.\r
\r
IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding\r
);\r
\r
-\r
/**\r
Installs and completes the initialization of a Driver Binding Protocol instance and\r
optionally installs the Component Name, Driver Configuration and Driver Diagnostics Protocols.\r
IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL\r
);\r
\r
-\r
/**\r
Uninstalls a Driver Binding Protocol instance and optionally uninstalls the\r
Component Name, Driver Configuration and Driver Diagnostics Protocols.\r
IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL\r
);\r
\r
-\r
/**\r
Installs Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiLibInstallDriverBindingComponentName2 (\r
- IN CONST EFI_HANDLE ImageHandle,\r
- IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
+ IN CONST EFI_HANDLE ImageHandle,\r
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
);\r
\r
-\r
/**\r
Uninstalls Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiLibUninstallDriverBindingComponentName2 (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
);\r
\r
-\r
/**\r
Installs Driver Binding Protocol with optional Component Name, Component Name 2, Driver\r
Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.\r
EFI_STATUS\r
EFIAPI\r
EfiLibInstallAllDriverProtocols2 (\r
- IN CONST EFI_HANDLE ImageHandle,\r
- IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
+ IN CONST EFI_HANDLE ImageHandle,\r
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
);\r
\r
-\r
/**\r
Uninstalls Driver Binding Protocol with optional Component Name, Component Name 2, Driver\r
Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.\r
EFI_STATUS\r
EFIAPI\r
EfiLibUninstallAllDriverProtocols2 (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
);\r
\r
-\r
/**\r
Appends a formatted Unicode string to a Null-terminated Unicode string\r
\r
@return Null-terminated Unicode string is that is the formatted\r
string appended to String.\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
CatVSPrint (\r
- IN CHAR16 *String OPTIONAL,\r
+ IN CHAR16 *String OPTIONAL,\r
IN CONST CHAR16 *FormatString,\r
IN VA_LIST Marker\r
);\r
CHAR16 *\r
EFIAPI\r
CatSPrint (\r
- IN CHAR16 *String OPTIONAL,\r
+ IN CHAR16 *String OPTIONAL,\r
IN CONST CHAR16 *FormatString,\r
...\r
);\r
EFI_ACPI_COMMON_HEADER *\r
EFIAPI\r
EfiLocateNextAcpiTable (\r
- IN UINT32 Signature,\r
- IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL\r
+ IN UINT32 Signature,\r
+ IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL\r
);\r
\r
/**\r
EFI_ACPI_COMMON_HEADER *\r
EFIAPI\r
EfiLocateFirstAcpiTable (\r
- IN UINT32 Signature\r
+ IN UINT32 Signature\r
);\r
\r
#endif\r
EFI_STATUS\r
EFIAPI\r
EfiGetTime (\r
- OUT EFI_TIME *Time,\r
- OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL\r
+ OUT EFI_TIME *Time,\r
+ OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiSetTime (\r
- IN EFI_TIME *Time\r
+ IN EFI_TIME *Time\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiGetWakeupTime (\r
- OUT BOOLEAN *Enabled,\r
- OUT BOOLEAN *Pending,\r
- OUT EFI_TIME *Time\r
+ OUT BOOLEAN *Enabled,\r
+ OUT BOOLEAN *Pending,\r
+ OUT EFI_TIME *Time\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiSetWakeupTime (\r
- IN BOOLEAN Enable,\r
- IN EFI_TIME *Time OPTIONAL\r
+ IN BOOLEAN Enable,\r
+ IN EFI_TIME *Time OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiGetVariable (\r
- IN CHAR16 *VariableName,\r
- IN EFI_GUID *VendorGuid,\r
- OUT UINT32 *Attributes OPTIONAL,\r
- IN OUT UINTN *DataSize,\r
- OUT VOID *Data\r
+ IN CHAR16 *VariableName,\r
+ IN EFI_GUID *VendorGuid,\r
+ OUT UINT32 *Attributes OPTIONAL,\r
+ IN OUT UINTN *DataSize,\r
+ OUT VOID *Data\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiGetNextVariableName (\r
- IN OUT UINTN *VariableNameSize,\r
- IN OUT CHAR16 *VariableName,\r
- IN OUT EFI_GUID *VendorGuid\r
+ IN OUT UINTN *VariableNameSize,\r
+ IN OUT CHAR16 *VariableName,\r
+ IN OUT EFI_GUID *VendorGuid\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiSetVariable (\r
- IN CHAR16 *VariableName,\r
- IN EFI_GUID *VendorGuid,\r
- IN UINT32 Attributes,\r
- IN UINTN DataSize,\r
- IN VOID *Data\r
+ IN CHAR16 *VariableName,\r
+ IN EFI_GUID *VendorGuid,\r
+ IN UINT32 Attributes,\r
+ IN UINTN DataSize,\r
+ IN VOID *Data\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiGetNextHighMonotonicCount (\r
- OUT UINT32 *HighCount\r
+ OUT UINT32 *HighCount\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
EfiResetSystem (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN VOID *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiConvertPointer (\r
- IN UINTN DebugDisposition,\r
- IN OUT VOID **Address\r
+ IN UINTN DebugDisposition,\r
+ IN OUT VOID **Address\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiConvertFunctionPointer (\r
- IN UINTN DebugDisposition,\r
- IN OUT VOID **Address\r
+ IN UINTN DebugDisposition,\r
+ IN OUT VOID **Address\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiSetVirtualAddressMap (\r
- IN UINTN MemoryMapSize,\r
- IN UINTN DescriptorSize,\r
- IN UINT32 DescriptorVersion,\r
- IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap\r
+ IN UINTN MemoryMapSize,\r
+ IN UINTN DescriptorSize,\r
+ IN UINT32 DescriptorVersion,\r
+ IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap\r
);\r
\r
-\r
/**\r
Convert the standard Lib double linked list to a virtual mapping.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiConvertList (\r
- IN UINTN DebugDisposition,\r
- IN OUT LIST_ENTRY *ListHead\r
+ IN UINTN DebugDisposition,\r
+ IN OUT LIST_ENTRY *ListHead\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EfiUpdateCapsule (\r
- IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
- IN UINTN CapsuleCount,\r
- IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL\r
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
+ IN UINTN CapsuleCount,\r
+ IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL\r
);\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service QueryCapsuleCapabilities().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiQueryCapsuleCapabilities (\r
- IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
- IN UINTN CapsuleCount,\r
- OUT UINT64 *MaximumCapsuleSize,\r
- OUT EFI_RESET_TYPE *ResetType\r
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
+ IN UINTN CapsuleCount,\r
+ OUT UINT64 *MaximumCapsuleSize,\r
+ OUT EFI_RESET_TYPE *ResetType\r
);\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service QueryVariableInfo().\r
\r
);\r
\r
#endif\r
-\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus\r
);\r
\r
-\r
/**\r
Execute Inquiry SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *InquiryDataBuffer OPTIONAL,\r
IN OUT UINT32 *InquiryDataLength,\r
IN BOOLEAN EnableVitalProductData\r
);\r
\r
-\r
/**\r
Execute Inquiry SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *InquiryDataBuffer OPTIONAL,\r
IN OUT UINT32 *InquiryDataLength,\r
IN BOOLEAN EnableVitalProductData,\r
IN UINT8 PageCode\r
);\r
\r
-\r
/**\r
Execute Mode Sense(10) SCSI command on a specific SCSI target.\r
\r
EFI_STATUS\r
EFIAPI\r
ScsiModeSense10Command (\r
- IN EFI_SCSI_IO_PROTOCOL *ScsiIo,\r
- IN UINT64 Timeout,\r
- IN OUT VOID *SenseData OPTIONAL,\r
- IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
- IN OUT VOID *DataBuffer OPTIONAL,\r
- IN OUT UINT32 *DataLength,\r
- IN UINT8 DBDField OPTIONAL,\r
- IN UINT8 PageControl,\r
- IN UINT8 PageCode\r
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,\r
+ IN UINT64 Timeout,\r
+ IN OUT VOID *SenseData OPTIONAL,\r
+ IN OUT UINT8 *SenseDataLength,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
+ IN OUT VOID *DataBuffer OPTIONAL,\r
+ IN OUT UINT32 *DataLength,\r
+ IN UINT8 DBDField OPTIONAL,\r
+ IN UINT8 PageControl,\r
+ IN UINT8 PageCode\r
);\r
\r
-\r
-\r
/**\r
Execute Request Sense SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus\r
);\r
\r
-\r
/**\r
Execute Read Capacity SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN BOOLEAN Pmi\r
);\r
\r
-\r
/**\r
Execute Read Capacity SCSI 16 command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN BOOLEAN Pmi\r
);\r
\r
-\r
/**\r
Execute Read(10) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN UINT32 SectorSize\r
);\r
\r
-\r
/**\r
Execute Write(10) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN UINT32 SectorSize\r
);\r
\r
-\r
/**\r
Execute Write(16) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN UINT32 SectorSize\r
);\r
\r
-\r
/**\r
Execute Security Protocol In SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN UINT8 SecurityProtocol,\r
IN UINT16 SecurityProtocolSpecific,\r
IN BOOLEAN Inc512,\r
IN UINTN DataLength,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
- OUT UINTN *TransferLength\r
+ OUT UINTN *TransferLength\r
);\r
\r
-\r
/**\r
Execute Security Protocol Out SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN UINT8 SecurityProtocol,\r
IN UINT16 SecurityProtocolSpecific,\r
IN BOOLEAN Inc512,\r
IN OUT VOID *DataBuffer OPTIONAL\r
);\r
\r
-\r
/**\r
Execute blocking/non-blocking Read(10) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
);\r
\r
-\r
/**\r
Execute blocking/non-blocking Write(10) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
);\r
\r
-\r
/**\r
Execute blocking/non-blocking Read(16) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
);\r
\r
-\r
/**\r
Execute blocking/non-blocking Write(16) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
\r
**/\r
\r
-\r
#ifndef __USB_DXE_LIB_H__\r
#define __USB_DXE_LIB_H__\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetHidDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor\r
);\r
\r
-\r
/**\r
Get the report descriptor of the specified USB HID interface.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetReportDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT16 DescriptorLength,\r
- OUT UINT8 *DescriptorBuffer\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT16 DescriptorLength,\r
+ OUT UINT8 *DescriptorBuffer\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetProtocolRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- OUT UINT8 *Protocol\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ OUT UINT8 *Protocol\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetProtocolRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 Protocol\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 Protocol\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetIdleRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 Duration\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 Duration\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetIdleRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- OUT UINT8 *Duration\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ OUT UINT8 *Duration\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetReportRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 ReportType,\r
- IN UINT16 ReportLen,\r
- IN UINT8 *Report\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 ReportType,\r
+ IN UINT16 ReportLen,\r
+ IN UINT8 *Report\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetReportRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 ReportType,\r
- IN UINT16 ReportLen,\r
- OUT UINT8 *Report\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 ReportType,\r
+ IN UINT16 ReportLen,\r
+ OUT UINT8 *Report\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Value,\r
- IN UINT16 Index,\r
- IN UINT16 DescriptorLength,\r
- OUT VOID *Descriptor,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Value,\r
+ IN UINT16 Index,\r
+ IN UINT16 DescriptorLength,\r
+ OUT VOID *Descriptor,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Value,\r
- IN UINT16 Index,\r
- IN UINT16 DescriptorLength,\r
- IN VOID *Descriptor,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Value,\r
+ IN UINT16 Index,\r
+ IN UINT16 DescriptorLength,\r
+ IN VOID *Descriptor,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetInterface (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Interface,\r
- OUT UINT16 *AlternateSetting,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Interface,\r
+ OUT UINT16 *AlternateSetting,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetInterface (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Interface,\r
- IN UINT16 AlternateSetting,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Interface,\r
+ IN UINT16 AlternateSetting,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetConfiguration (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- OUT UINT16 *ConfigurationValue,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ OUT UINT16 *ConfigurationValue,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetConfiguration (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 ConfigurationValue,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 ConfigurationValue,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbSetFeature (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Value,\r
- IN UINT16 Target,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Value,\r
+ IN UINT16 Target,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbClearFeature (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Value,\r
- IN UINT16 Target,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Value,\r
+ IN UINT16 Target,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetStatus (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Target,\r
- OUT UINT16 *DeviceStatus,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Target,\r
+ OUT UINT16 *DeviceStatus,\r
+ OUT UINT32 *Status\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbClearEndpointHalt (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Endpoint,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Endpoint,\r
+ OUT UINT32 *Status\r
);\r
\r
#endif\r
///\r
/// Unit Test Status\r
///\r
-typedef UINT32 UNIT_TEST_STATUS;\r
+typedef UINT32 UNIT_TEST_STATUS;\r
#define UNIT_TEST_PASSED (0)\r
#define UNIT_TEST_ERROR_PREREQUISITE_NOT_MET (1)\r
#define UNIT_TEST_ERROR_TEST_FAILED (2)\r
/// Unit Test Framework Handle\r
///\r
struct UNIT_TEST_FRAMEWORK_OBJECT;\r
-typedef struct UNIT_TEST_FRAMEWORK_OBJECT *UNIT_TEST_FRAMEWORK_HANDLE;\r
+typedef struct UNIT_TEST_FRAMEWORK_OBJECT *UNIT_TEST_FRAMEWORK_HANDLE;\r
\r
///\r
/// Unit Test Suite Handle\r
///\r
struct UNIT_TEST_SUITE_OBJECT;\r
-typedef struct UNIT_TEST_SUITE_OBJECT *UNIT_TEST_SUITE_HANDLE;\r
+typedef struct UNIT_TEST_SUITE_OBJECT *UNIT_TEST_SUITE_HANDLE;\r
\r
///\r
/// Unit Test Handle\r
///\r
struct UNIT_TEST_OBJECT;\r
-typedef struct UNIT_TEST_OBJECT *UNIT_TEST_HANDLE;\r
+typedef struct UNIT_TEST_OBJECT *UNIT_TEST_HANDLE;\r
\r
///\r
/// Unit Test Context\r
///\r
-typedef VOID* UNIT_TEST_CONTEXT;\r
+typedef VOID *UNIT_TEST_CONTEXT;\r
\r
/**\r
The prototype for a single UnitTest case function.\r
EFI_STATUS\r
EFIAPI\r
SaveFrameworkState (\r
- IN UNIT_TEST_CONTEXT ContextToSave OPTIONAL,\r
- IN UINTN ContextToSaveSize\r
+ IN UNIT_TEST_CONTEXT ContextToSave OPTIONAL,\r
+ IN UINTN ContextToSaveSize\r
);\r
\r
/**\r
#if defined (EDKII_UNIT_TEST_FRAMEWORK_ENABLED)\r
#include <Library/BaseLib.h>\r
\r
- ///\r
- /// Pointer to jump buffer used with SetJump()/LongJump() to test if a\r
- /// function under test generates an expected ASSERT() condition.\r
- ///\r
- extern BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer;\r
+///\r
+/// Pointer to jump buffer used with SetJump()/LongJump() to test if a\r
+/// function under test generates an expected ASSERT() condition.\r
+///\r
+extern BASE_LIBRARY_JUMP_BUFFER *gUnitTestExpectAssertFailureJumpBuffer;\r
\r
- #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) \\r
+#define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) \\r
do { \\r
UNIT_TEST_STATUS UnitTestJumpStatus; \\r
BASE_LIBRARY_JUMP_BUFFER UnitTestJumpBuffer; \\r
} \\r
} while (FALSE)\r
#else\r
- #define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) FunctionCall;\r
+#define UT_EXPECT_ASSERT_FAILURE(FunctionCall, Status) FunctionCall;\r
#endif\r
\r
/**\r
///\r
/// EFI boot mode\r
///\r
-typedef UINT32 EFI_BOOT_MODE;\r
+typedef UINT32 EFI_BOOT_MODE;\r
\r
//\r
// 0x21 - 0xf..f are reserved.\r
//\r
-#define BOOT_WITH_FULL_CONFIGURATION 0x00\r
-#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01\r
-#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02\r
-#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03\r
-#define BOOT_WITH_DEFAULT_SETTINGS 0x04\r
-#define BOOT_ON_S4_RESUME 0x05\r
-#define BOOT_ON_S5_RESUME 0x06\r
-#define BOOT_WITH_MFG_MODE_SETTINGS 0x07\r
-#define BOOT_ON_S2_RESUME 0x10\r
-#define BOOT_ON_S3_RESUME 0x11\r
-#define BOOT_ON_FLASH_UPDATE 0x12\r
-#define BOOT_IN_RECOVERY_MODE 0x20\r
+#define BOOT_WITH_FULL_CONFIGURATION 0x00\r
+#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01\r
+#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02\r
+#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03\r
+#define BOOT_WITH_DEFAULT_SETTINGS 0x04\r
+#define BOOT_ON_S4_RESUME 0x05\r
+#define BOOT_ON_S5_RESUME 0x06\r
+#define BOOT_WITH_MFG_MODE_SETTINGS 0x07\r
+#define BOOT_ON_S2_RESUME 0x10\r
+#define BOOT_ON_S3_RESUME 0x11\r
+#define BOOT_ON_FLASH_UPDATE 0x12\r
+#define BOOT_IN_RECOVERY_MODE 0x20\r
\r
#endif\r
PI Version 1.0\r
\r
**/\r
+\r
#ifndef __PI_DEPENDENCY_H__\r
#define __PI_DEPENDENCY_H__\r
\r
/// If present, this must be the first and only opcode,\r
/// EFI_DEP_BEFORE may be used by DXE and SMM drivers.\r
///\r
-#define EFI_DEP_BEFORE 0x00\r
+#define EFI_DEP_BEFORE 0x00\r
\r
///\r
/// If present, this must be the first and only opcode,\r
/// EFI_DEP_AFTER may be used by DXE and SMM drivers.\r
///\r
-#define EFI_DEP_AFTER 0x01\r
-\r
-#define EFI_DEP_PUSH 0x02\r
-#define EFI_DEP_AND 0x03\r
-#define EFI_DEP_OR 0x04\r
-#define EFI_DEP_NOT 0x05\r
-#define EFI_DEP_TRUE 0x06\r
-#define EFI_DEP_FALSE 0x07\r
-#define EFI_DEP_END 0x08\r
+#define EFI_DEP_AFTER 0x01\r
\r
+#define EFI_DEP_PUSH 0x02\r
+#define EFI_DEP_AND 0x03\r
+#define EFI_DEP_OR 0x04\r
+#define EFI_DEP_NOT 0x05\r
+#define EFI_DEP_TRUE 0x06\r
+#define EFI_DEP_FALSE 0x07\r
+#define EFI_DEP_END 0x08\r
\r
///\r
/// If present, this must be the first opcode,\r
/// EFI_DEP_SOR is only used by DXE driver.\r
///\r
-#define EFI_DEP_SOR 0x09\r
+#define EFI_DEP_SOR 0x09\r
\r
#endif\r
/// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function\r
/// description in the UEFI 2.0 specification.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
\r
///\r
/// The number of bytes in the memory region.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
\r
///\r
/// The bit mask of attributes that the memory region is capable of supporting. The bit\r
/// mask of available attributes is defined in the GetMemoryMap() function description\r
/// in the UEFI 2.0 specification.\r
///\r
- UINT64 Capabilities;\r
+ UINT64 Capabilities;\r
///\r
/// The bit mask of attributes that the memory region is currently using. The bit mask of\r
/// available attributes is defined in GetMemoryMap().\r
///\r
- UINT64 Attributes;\r
+ UINT64 Attributes;\r
///\r
/// Type of the memory region. Type EFI_GCD_MEMORY_TYPE is defined in the\r
/// AddMemorySpace() function description.\r
///\r
- EFI_GCD_MEMORY_TYPE GcdMemoryType;\r
+ EFI_GCD_MEMORY_TYPE GcdMemoryType;\r
\r
///\r
/// The image handle of the agent that allocated the memory resource described by\r
/// resource is not currently allocated. Type EFI_HANDLE is defined in\r
/// InstallProtocolInterface() in the UEFI 2.0 specification.\r
///\r
- EFI_HANDLE ImageHandle;\r
+ EFI_HANDLE ImageHandle;\r
\r
///\r
/// The device handle for which the memory resource has been allocated. If\r
/// described by a device handle. Type EFI_HANDLE is defined in\r
/// InstallProtocolInterface() in the UEFI 2.0 specification.\r
///\r
- EFI_HANDLE DeviceHandle;\r
+ EFI_HANDLE DeviceHandle;\r
} EFI_GCD_MEMORY_SPACE_DESCRIPTOR;\r
\r
///\r
/// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function\r
/// description in the UEFI 2.0 specification.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
\r
///\r
/// Number of bytes in the I/O region.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
\r
///\r
/// Type of the I/O region. Type EFI_GCD_IO_TYPE is defined in the\r
/// AddIoSpace() function description.\r
///\r
- EFI_GCD_IO_TYPE GcdIoType;\r
+ EFI_GCD_IO_TYPE GcdIoType;\r
\r
///\r
/// The image handle of the agent that allocated the I/O resource described by\r
/// resource is not currently allocated. Type EFI_HANDLE is defined in\r
/// InstallProtocolInterface() in the UEFI 2.0 specification.\r
///\r
- EFI_HANDLE ImageHandle;\r
+ EFI_HANDLE ImageHandle;\r
\r
///\r
/// The device handle for which the I/O resource has been allocated. If ImageHandle\r
/// Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI\r
/// 2.0 specification.\r
///\r
- EFI_HANDLE DeviceHandle;\r
+ EFI_HANDLE DeviceHandle;\r
} EFI_GCD_IO_SPACE_DESCRIPTOR;\r
\r
-\r
/**\r
Adds reserved memory, system memory, or memory-mapped I/O resources to the\r
global coherency domain of the processor.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SET_MEMORY_SPACE_CAPABILITIES) (\r
+(EFIAPI *EFI_SET_MEMORY_SPACE_CAPABILITIES)(\r
IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
IN UINT64 Length,\r
IN UINT64 Capabilities\r
OUT EFI_GCD_IO_SPACE_DESCRIPTOR **IoSpaceMap\r
);\r
\r
-\r
-\r
/**\r
Loads and executed DXE drivers from firmware volumes.\r
\r
/// The table header for the DXE Services Table.\r
/// This header contains the DXE_SERVICES_SIGNATURE and DXE_SERVICES_REVISION values.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
\r
//\r
// Global Coherency Domain Services\r
//\r
- EFI_ADD_MEMORY_SPACE AddMemorySpace;\r
- EFI_ALLOCATE_MEMORY_SPACE AllocateMemorySpace;\r
- EFI_FREE_MEMORY_SPACE FreeMemorySpace;\r
- EFI_REMOVE_MEMORY_SPACE RemoveMemorySpace;\r
- EFI_GET_MEMORY_SPACE_DESCRIPTOR GetMemorySpaceDescriptor;\r
- EFI_SET_MEMORY_SPACE_ATTRIBUTES SetMemorySpaceAttributes;\r
- EFI_GET_MEMORY_SPACE_MAP GetMemorySpaceMap;\r
- EFI_ADD_IO_SPACE AddIoSpace;\r
- EFI_ALLOCATE_IO_SPACE AllocateIoSpace;\r
- EFI_FREE_IO_SPACE FreeIoSpace;\r
- EFI_REMOVE_IO_SPACE RemoveIoSpace;\r
- EFI_GET_IO_SPACE_DESCRIPTOR GetIoSpaceDescriptor;\r
- EFI_GET_IO_SPACE_MAP GetIoSpaceMap;\r
+ EFI_ADD_MEMORY_SPACE AddMemorySpace;\r
+ EFI_ALLOCATE_MEMORY_SPACE AllocateMemorySpace;\r
+ EFI_FREE_MEMORY_SPACE FreeMemorySpace;\r
+ EFI_REMOVE_MEMORY_SPACE RemoveMemorySpace;\r
+ EFI_GET_MEMORY_SPACE_DESCRIPTOR GetMemorySpaceDescriptor;\r
+ EFI_SET_MEMORY_SPACE_ATTRIBUTES SetMemorySpaceAttributes;\r
+ EFI_GET_MEMORY_SPACE_MAP GetMemorySpaceMap;\r
+ EFI_ADD_IO_SPACE AddIoSpace;\r
+ EFI_ALLOCATE_IO_SPACE AllocateIoSpace;\r
+ EFI_FREE_IO_SPACE FreeIoSpace;\r
+ EFI_REMOVE_IO_SPACE RemoveIoSpace;\r
+ EFI_GET_IO_SPACE_DESCRIPTOR GetIoSpaceDescriptor;\r
+ EFI_GET_IO_SPACE_MAP GetIoSpaceMap;\r
\r
//\r
// Dispatcher Services\r
//\r
- EFI_DISPATCH Dispatch;\r
- EFI_SCHEDULE Schedule;\r
- EFI_TRUST Trust;\r
+ EFI_DISPATCH Dispatch;\r
+ EFI_SCHEDULE Schedule;\r
+ EFI_TRUST Trust;\r
//\r
// Service to process a single firmware volume found in a capsule\r
//\r
- EFI_PROCESS_FIRMWARE_VOLUME ProcessFirmwareVolume;\r
+ EFI_PROCESS_FIRMWARE_VOLUME ProcessFirmwareVolume;\r
//\r
// Extensions to Global Coherency Domain Services\r
//\r
- EFI_SET_MEMORY_SPACE_CAPABILITIES SetMemorySpaceCapabilities;\r
+ EFI_SET_MEMORY_SPACE_CAPABILITIES SetMemorySpaceCapabilities;\r
} DXE_SERVICES;\r
\r
typedef DXE_SERVICES EFI_DXE_SERVICES;\r
\r
**/\r
\r
-\r
#ifndef __PI_FIRMWARE_FILE_H__\r
#define __PI_FIRMWARE_FILE_H__\r
\r
/// header. The State and IntegrityCheck.Checksum.File fields are assumed\r
/// to be zero and the checksum is calculated such that the entire header sums to zero.\r
///\r
- UINT8 Header;\r
+ UINT8 Header;\r
///\r
/// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes\r
/// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit\r
/// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the\r
/// EFI_FILE_DATA_VALID bit is set in the State field.\r
///\r
- UINT8 File;\r
+ UINT8 File;\r
} Checksum;\r
///\r
/// This is the full 16 bits of the IntegrityCheck field.\r
///\r
#define FFS_FIXED_CHECKSUM 0xAA\r
\r
-typedef UINT8 EFI_FV_FILETYPE;\r
-typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;\r
-typedef UINT8 EFI_FFS_FILE_STATE;\r
+typedef UINT8 EFI_FV_FILETYPE;\r
+typedef UINT8 EFI_FFS_FILE_ATTRIBUTES;\r
+typedef UINT8 EFI_FFS_FILE_STATE;\r
\r
///\r
/// File Types Definitions\r
///\r
-#define EFI_FV_FILETYPE_ALL 0x00\r
-#define EFI_FV_FILETYPE_RAW 0x01\r
-#define EFI_FV_FILETYPE_FREEFORM 0x02\r
-#define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
-#define EFI_FV_FILETYPE_PEI_CORE 0x04\r
-#define EFI_FV_FILETYPE_DXE_CORE 0x05\r
-#define EFI_FV_FILETYPE_PEIM 0x06\r
-#define EFI_FV_FILETYPE_DRIVER 0x07\r
-#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08\r
-#define EFI_FV_FILETYPE_APPLICATION 0x09\r
-#define EFI_FV_FILETYPE_MM 0x0A\r
-#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM\r
-#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B\r
-#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C\r
-#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE\r
-#define EFI_FV_FILETYPE_MM_CORE 0x0D\r
-#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE\r
-#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E\r
-#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F\r
-#define EFI_FV_FILETYPE_OEM_MIN 0xc0\r
-#define EFI_FV_FILETYPE_OEM_MAX 0xdf\r
-#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0\r
-#define EFI_FV_FILETYPE_DEBUG_MAX 0xef\r
-#define EFI_FV_FILETYPE_FFS_MIN 0xf0\r
-#define EFI_FV_FILETYPE_FFS_MAX 0xff\r
-#define EFI_FV_FILETYPE_FFS_PAD 0xf0\r
+#define EFI_FV_FILETYPE_ALL 0x00\r
+#define EFI_FV_FILETYPE_RAW 0x01\r
+#define EFI_FV_FILETYPE_FREEFORM 0x02\r
+#define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
+#define EFI_FV_FILETYPE_PEI_CORE 0x04\r
+#define EFI_FV_FILETYPE_DXE_CORE 0x05\r
+#define EFI_FV_FILETYPE_PEIM 0x06\r
+#define EFI_FV_FILETYPE_DRIVER 0x07\r
+#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08\r
+#define EFI_FV_FILETYPE_APPLICATION 0x09\r
+#define EFI_FV_FILETYPE_MM 0x0A\r
+#define EFI_FV_FILETYPE_SMM EFI_FV_FILETYPE_MM\r
+#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B\r
+#define EFI_FV_FILETYPE_COMBINED_MM_DXE 0x0C\r
+#define EFI_FV_FILETYPE_COMBINED_SMM_DXE EFI_FV_FILETYPE_COMBINED_MM_DXE\r
+#define EFI_FV_FILETYPE_MM_CORE 0x0D\r
+#define EFI_FV_FILETYPE_SMM_CORE EFI_FV_FILETYPE_MM_CORE\r
+#define EFI_FV_FILETYPE_MM_STANDALONE 0x0E\r
+#define EFI_FV_FILETYPE_MM_CORE_STANDALONE 0x0F\r
+#define EFI_FV_FILETYPE_OEM_MIN 0xc0\r
+#define EFI_FV_FILETYPE_OEM_MAX 0xdf\r
+#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0\r
+#define EFI_FV_FILETYPE_DEBUG_MAX 0xef\r
+#define EFI_FV_FILETYPE_FFS_MIN 0xf0\r
+#define EFI_FV_FILETYPE_FFS_MAX 0xff\r
+#define EFI_FV_FILETYPE_FFS_PAD 0xf0\r
///\r
/// FFS File Attributes.\r
///\r
-#define FFS_ATTRIB_LARGE_FILE 0x01\r
-#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02\r
-#define FFS_ATTRIB_FIXED 0x04\r
-#define FFS_ATTRIB_DATA_ALIGNMENT 0x38\r
-#define FFS_ATTRIB_CHECKSUM 0x40\r
+#define FFS_ATTRIB_LARGE_FILE 0x01\r
+#define FFS_ATTRIB_DATA_ALIGNMENT_2 0x02\r
+#define FFS_ATTRIB_FIXED 0x04\r
+#define FFS_ATTRIB_DATA_ALIGNMENT 0x38\r
+#define FFS_ATTRIB_CHECKSUM 0x40\r
\r
///\r
/// FFS File State Bits.\r
#define EFI_FILE_DELETED 0x10\r
#define EFI_FILE_HEADER_INVALID 0x20\r
\r
-\r
///\r
/// Each file begins with the header that describe the\r
/// contents and state of the files.\r
///\r
/// This GUID is the file name. It is used to uniquely identify the file.\r
///\r
- EFI_GUID Name;\r
+ EFI_GUID Name;\r
///\r
/// Used to verify the integrity of the file.\r
///\r
- EFI_FFS_INTEGRITY_CHECK IntegrityCheck;\r
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;\r
///\r
/// Identifies the type of file.\r
///\r
- EFI_FV_FILETYPE Type;\r
+ EFI_FV_FILETYPE Type;\r
///\r
/// Declares various file attribute bits.\r
///\r
- EFI_FFS_FILE_ATTRIBUTES Attributes;\r
+ EFI_FFS_FILE_ATTRIBUTES Attributes;\r
///\r
/// The length of the file in bytes, including the FFS header.\r
///\r
- UINT8 Size[3];\r
+ UINT8 Size[3];\r
///\r
/// Used to track the state of the file throughout the life of the file from creation to deletion.\r
///\r
- EFI_FFS_FILE_STATE State;\r
+ EFI_FFS_FILE_STATE State;\r
} EFI_FFS_FILE_HEADER;\r
\r
typedef struct {\r
/// one instance of a file with the file name GUID of Name in any given firmware\r
/// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD.\r
///\r
- EFI_GUID Name;\r
+ EFI_GUID Name;\r
\r
///\r
/// Used to verify the integrity of the file.\r
///\r
- EFI_FFS_INTEGRITY_CHECK IntegrityCheck;\r
+ EFI_FFS_INTEGRITY_CHECK IntegrityCheck;\r
\r
///\r
/// Identifies the type of file.\r
///\r
- EFI_FV_FILETYPE Type;\r
+ EFI_FV_FILETYPE Type;\r
\r
///\r
/// Declares various file attribute bits.\r
///\r
- EFI_FFS_FILE_ATTRIBUTES Attributes;\r
+ EFI_FFS_FILE_ATTRIBUTES Attributes;\r
\r
///\r
/// The length of the file in bytes, including the FFS header.\r
/// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is\r
/// located at the next 8-byte aligned firmware volume offset following the last byte of the file F.\r
///\r
- UINT8 Size[3];\r
+ UINT8 Size[3];\r
\r
///\r
/// Used to track the state of the file throughout the life of the file from creation to deletion.\r
///\r
- EFI_FFS_FILE_STATE State;\r
+ EFI_FFS_FILE_STATE State;\r
\r
///\r
/// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero.\r
/// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used.\r
///\r
- UINT64 ExtendedSize;\r
+ UINT64 ExtendedSize;\r
} EFI_FFS_FILE_HEADER2;\r
\r
#define IS_FFS_FILE2(FfsFileHeaderPtr) \\r
/// FFS_FILE_SIZE() function-like macro below must not have side effects:\r
/// FfsFileHeaderPtr is evaluated multiple times.\r
///\r
-#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) ( \\r
+#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) (\\r
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[0] ) | \\r
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[1] << 8) | \\r
(((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[2] << 16)))\r
/// Pseudo type. It is used as a wild card when retrieving sections.\r
/// The section type EFI_SECTION_ALL matches all section types.\r
///\r
-#define EFI_SECTION_ALL 0x00\r
+#define EFI_SECTION_ALL 0x00\r
\r
///\r
/// Encapsulation section Type values.\r
///\r
-#define EFI_SECTION_COMPRESSION 0x01\r
+#define EFI_SECTION_COMPRESSION 0x01\r
\r
-#define EFI_SECTION_GUID_DEFINED 0x02\r
+#define EFI_SECTION_GUID_DEFINED 0x02\r
\r
-#define EFI_SECTION_DISPOSABLE 0x03\r
+#define EFI_SECTION_DISPOSABLE 0x03\r
\r
///\r
/// Leaf section Type values.\r
///\r
-#define EFI_SECTION_PE32 0x10\r
-#define EFI_SECTION_PIC 0x11\r
-#define EFI_SECTION_TE 0x12\r
-#define EFI_SECTION_DXE_DEPEX 0x13\r
-#define EFI_SECTION_VERSION 0x14\r
-#define EFI_SECTION_USER_INTERFACE 0x15\r
-#define EFI_SECTION_COMPATIBILITY16 0x16\r
-#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17\r
-#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18\r
-#define EFI_SECTION_RAW 0x19\r
-#define EFI_SECTION_PEI_DEPEX 0x1B\r
-#define EFI_SECTION_MM_DEPEX 0x1C\r
-#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX\r
+#define EFI_SECTION_PE32 0x10\r
+#define EFI_SECTION_PIC 0x11\r
+#define EFI_SECTION_TE 0x12\r
+#define EFI_SECTION_DXE_DEPEX 0x13\r
+#define EFI_SECTION_VERSION 0x14\r
+#define EFI_SECTION_USER_INTERFACE 0x15\r
+#define EFI_SECTION_COMPATIBILITY16 0x16\r
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17\r
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18\r
+#define EFI_SECTION_RAW 0x19\r
+#define EFI_SECTION_PEI_DEPEX 0x1B\r
+#define EFI_SECTION_MM_DEPEX 0x1C\r
+#define EFI_SECTION_SMM_DEPEX EFI_SECTION_MM_DEPEX\r
\r
///\r
/// Common section header.\r
/// A 24-bit unsigned integer that contains the total size of the section in bytes,\r
/// including the EFI_COMMON_SECTION_HEADER.\r
///\r
- UINT8 Size[3];\r
- EFI_SECTION_TYPE Type;\r
+ UINT8 Size[3];\r
+ EFI_SECTION_TYPE Type;\r
///\r
/// Declares the section type.\r
///\r
/// A 24-bit unsigned integer that contains the total size of the section in bytes,\r
/// including the EFI_COMMON_SECTION_HEADER.\r
///\r
- UINT8 Size[3];\r
+ UINT8 Size[3];\r
\r
- EFI_SECTION_TYPE Type;\r
+ EFI_SECTION_TYPE Type;\r
\r
///\r
/// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If\r
/// Size is not equal to 0xFFFFFF, then this field does not exist.\r
///\r
- UINT32 ExtendedSize;\r
+ UINT32 ExtendedSize;\r
} EFI_COMMON_SECTION_HEADER2;\r
\r
///\r
///\r
/// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION.\r
///\r
- EFI_COMMON_SECTION_HEADER CommonHeader;\r
+ EFI_COMMON_SECTION_HEADER CommonHeader;\r
///\r
/// The UINT32 that indicates the size of the section data after decompression.\r
///\r
- UINT32 UncompressedLength;\r
+ UINT32 UncompressedLength;\r
///\r
/// Indicates which compression algorithm is used.\r
///\r
- UINT8 CompressionType;\r
+ UINT8 CompressionType;\r
} EFI_COMPRESSION_SECTION;\r
\r
typedef struct {\r
/// order to conserve space. The contents of this section are implementation specific, but might contain\r
/// debug data or detailed integration instructions.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2;\r
\r
///\r
/// The leaf section which could be used to determine the dispatch order of DXEs.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2;\r
\r
///\r
/// The leaf section which contains a PI FV.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2;\r
\r
///\r
/// The leaf section which contains a single GUID.\r
///\r
/// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID.\r
///\r
- EFI_COMMON_SECTION_HEADER CommonHeader;\r
+ EFI_COMMON_SECTION_HEADER CommonHeader;\r
///\r
/// This GUID is defined by the creator of the file. It is a vendor-defined file type.\r
///\r
- EFI_GUID SubTypeGuid;\r
+ EFI_GUID SubTypeGuid;\r
} EFI_FREEFORM_SUBTYPE_GUID_SECTION;\r
\r
typedef struct {\r
///\r
/// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED.\r
///\r
- EFI_COMMON_SECTION_HEADER CommonHeader;\r
+ EFI_COMMON_SECTION_HEADER CommonHeader;\r
///\r
/// The GUID that defines the format of the data that follows. It is a vendor-defined section type.\r
///\r
- EFI_GUID SectionDefinitionGuid;\r
+ EFI_GUID SectionDefinitionGuid;\r
///\r
/// Contains the offset in bytes from the beginning of the common header to the first byte of the data.\r
///\r
- UINT16 DataOffset;\r
+ UINT16 DataOffset;\r
///\r
/// The bit field that declares some specific characteristics of the section contents.\r
///\r
- UINT16 Attributes;\r
+ UINT16 Attributes;\r
} EFI_GUID_DEFINED_SECTION;\r
\r
typedef struct {\r
///\r
/// The leaf section which contains PE32+ image.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2;\r
\r
///\r
/// The leaf section used to determine the dispatch order of PEIMs.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2;\r
\r
///\r
/// A leaf section type that contains a position-independent-code (PIC) image.\r
/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must\r
/// be used if the section is 16MB or larger.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2;\r
\r
///\r
/// The leaf section which constains the position-independent-code image.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2;\r
\r
///\r
/// The leaf section which contains an array of zero or more bytes.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;\r
-typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2;\r
\r
///\r
/// The SMM dependency expression section is a leaf section that contains a dependency expression that\r
/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol\r
/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger.\r
///\r
-typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;\r
+typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION;\r
typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2;\r
\r
///\r
/// is human readable file name.\r
///\r
typedef struct {\r
- EFI_COMMON_SECTION_HEADER CommonHeader;\r
+ EFI_COMMON_SECTION_HEADER CommonHeader;\r
\r
///\r
/// Array of unicode string.\r
///\r
- CHAR16 FileNameString[1];\r
+ CHAR16 FileNameString[1];\r
} EFI_USER_INTERFACE_SECTION;\r
\r
typedef struct {\r
/// an optional unicode string that represents the file revision.\r
///\r
typedef struct {\r
- EFI_COMMON_SECTION_HEADER CommonHeader;\r
- UINT16 BuildNumber;\r
+ EFI_COMMON_SECTION_HEADER CommonHeader;\r
+ UINT16 BuildNumber;\r
\r
///\r
/// Array of unicode string.\r
///\r
- CHAR16 VersionString[1];\r
+ CHAR16 VersionString[1];\r
} EFI_VERSION_SECTION;\r
\r
typedef struct {\r
/// and IS_SECTION2() function-like macros below must not have side effects:\r
/// SectionHeaderPtr is evaluated multiple times.\r
///\r
-#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) ( \\r
+#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) (\\r
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[0] ) | \\r
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[1] << 8) | \\r
(((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[2] << 16)))\r
#pragma pack()\r
\r
#endif\r
-\r
///\r
/// EFI_FV_FILE_ATTRIBUTES\r
///\r
-typedef UINT32 EFI_FV_FILE_ATTRIBUTES;\r
+typedef UINT32 EFI_FV_FILE_ATTRIBUTES;\r
\r
//\r
// Value of EFI_FV_FILE_ATTRIBUTES.\r
///\r
/// type of EFI FVB attribute\r
///\r
-typedef UINT32 EFI_FVB_ATTRIBUTES_2;\r
+typedef UINT32 EFI_FVB_ATTRIBUTES_2;\r
\r
//\r
// Attributes bit definitions\r
//\r
-#define EFI_FVB2_READ_DISABLED_CAP 0x00000001\r
-#define EFI_FVB2_READ_ENABLED_CAP 0x00000002\r
-#define EFI_FVB2_READ_STATUS 0x00000004\r
-#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008\r
-#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010\r
-#define EFI_FVB2_WRITE_STATUS 0x00000020\r
-#define EFI_FVB2_LOCK_CAP 0x00000040\r
-#define EFI_FVB2_LOCK_STATUS 0x00000080\r
-#define EFI_FVB2_STICKY_WRITE 0x00000200\r
-#define EFI_FVB2_MEMORY_MAPPED 0x00000400\r
-#define EFI_FVB2_ERASE_POLARITY 0x00000800\r
-#define EFI_FVB2_READ_LOCK_CAP 0x00001000\r
-#define EFI_FVB2_READ_LOCK_STATUS 0x00002000\r
-#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000\r
-#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000\r
-#define EFI_FVB2_ALIGNMENT 0x001F0000\r
-#define EFI_FVB2_ALIGNMENT_1 0x00000000\r
-#define EFI_FVB2_ALIGNMENT_2 0x00010000\r
-#define EFI_FVB2_ALIGNMENT_4 0x00020000\r
-#define EFI_FVB2_ALIGNMENT_8 0x00030000\r
-#define EFI_FVB2_ALIGNMENT_16 0x00040000\r
-#define EFI_FVB2_ALIGNMENT_32 0x00050000\r
-#define EFI_FVB2_ALIGNMENT_64 0x00060000\r
-#define EFI_FVB2_ALIGNMENT_128 0x00070000\r
-#define EFI_FVB2_ALIGNMENT_256 0x00080000\r
-#define EFI_FVB2_ALIGNMENT_512 0x00090000\r
-#define EFI_FVB2_ALIGNMENT_1K 0x000A0000\r
-#define EFI_FVB2_ALIGNMENT_2K 0x000B0000\r
-#define EFI_FVB2_ALIGNMENT_4K 0x000C0000\r
-#define EFI_FVB2_ALIGNMENT_8K 0x000D0000\r
-#define EFI_FVB2_ALIGNMENT_16K 0x000E0000\r
-#define EFI_FVB2_ALIGNMENT_32K 0x000F0000\r
-#define EFI_FVB2_ALIGNMENT_64K 0x00100000\r
-#define EFI_FVB2_ALIGNMENT_128K 0x00110000\r
-#define EFI_FVB2_ALIGNMENT_256K 0x00120000\r
-#define EFI_FVB2_ALIGNMENT_512K 0x00130000\r
-#define EFI_FVB2_ALIGNMENT_1M 0x00140000\r
-#define EFI_FVB2_ALIGNMENT_2M 0x00150000\r
-#define EFI_FVB2_ALIGNMENT_4M 0x00160000\r
-#define EFI_FVB2_ALIGNMENT_8M 0x00170000\r
-#define EFI_FVB2_ALIGNMENT_16M 0x00180000\r
-#define EFI_FVB2_ALIGNMENT_32M 0x00190000\r
-#define EFI_FVB2_ALIGNMENT_64M 0x001A0000\r
-#define EFI_FVB2_ALIGNMENT_128M 0x001B0000\r
-#define EFI_FVB2_ALIGNMENT_256M 0x001C0000\r
-#define EFI_FVB2_ALIGNMENT_512M 0x001D0000\r
-#define EFI_FVB2_ALIGNMENT_1G 0x001E0000\r
-#define EFI_FVB2_ALIGNMENT_2G 0x001F0000\r
-#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000\r
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001\r
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002\r
+#define EFI_FVB2_READ_STATUS 0x00000004\r
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008\r
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010\r
+#define EFI_FVB2_WRITE_STATUS 0x00000020\r
+#define EFI_FVB2_LOCK_CAP 0x00000040\r
+#define EFI_FVB2_LOCK_STATUS 0x00000080\r
+#define EFI_FVB2_STICKY_WRITE 0x00000200\r
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400\r
+#define EFI_FVB2_ERASE_POLARITY 0x00000800\r
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000\r
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000\r
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000\r
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000\r
+#define EFI_FVB2_ALIGNMENT 0x001F0000\r
+#define EFI_FVB2_ALIGNMENT_1 0x00000000\r
+#define EFI_FVB2_ALIGNMENT_2 0x00010000\r
+#define EFI_FVB2_ALIGNMENT_4 0x00020000\r
+#define EFI_FVB2_ALIGNMENT_8 0x00030000\r
+#define EFI_FVB2_ALIGNMENT_16 0x00040000\r
+#define EFI_FVB2_ALIGNMENT_32 0x00050000\r
+#define EFI_FVB2_ALIGNMENT_64 0x00060000\r
+#define EFI_FVB2_ALIGNMENT_128 0x00070000\r
+#define EFI_FVB2_ALIGNMENT_256 0x00080000\r
+#define EFI_FVB2_ALIGNMENT_512 0x00090000\r
+#define EFI_FVB2_ALIGNMENT_1K 0x000A0000\r
+#define EFI_FVB2_ALIGNMENT_2K 0x000B0000\r
+#define EFI_FVB2_ALIGNMENT_4K 0x000C0000\r
+#define EFI_FVB2_ALIGNMENT_8K 0x000D0000\r
+#define EFI_FVB2_ALIGNMENT_16K 0x000E0000\r
+#define EFI_FVB2_ALIGNMENT_32K 0x000F0000\r
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000\r
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000\r
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000\r
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000\r
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000\r
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000\r
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000\r
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000\r
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000\r
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000\r
+#define EFI_FVB2_ALIGNMENT_64M 0x001A0000\r
+#define EFI_FVB2_ALIGNMENT_128M 0x001B0000\r
+#define EFI_FVB2_ALIGNMENT_256M 0x001C0000\r
+#define EFI_FVB2_ALIGNMENT_512M 0x001D0000\r
+#define EFI_FVB2_ALIGNMENT_1G 0x001E0000\r
+#define EFI_FVB2_ALIGNMENT_2G 0x001F0000\r
+#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000\r
\r
typedef struct {\r
///\r
/// The number of sequential blocks which are of the same size.\r
///\r
- UINT32 NumBlocks;\r
+ UINT32 NumBlocks;\r
///\r
/// The size of the blocks.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
} EFI_FV_BLOCK_MAP_ENTRY;\r
\r
///\r
EFI_FV_BLOCK_MAP_ENTRY BlockMap[1];\r
} EFI_FIRMWARE_VOLUME_HEADER;\r
\r
-#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')\r
+#define EFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H')\r
\r
///\r
/// Firmware Volume Header Revision definition\r
///\r
/// Firmware volume name.\r
///\r
- EFI_GUID FvName;\r
+ EFI_GUID FvName;\r
///\r
/// Size of the rest of the extension header, including this structure.\r
///\r
- UINT32 ExtHeaderSize;\r
+ UINT32 ExtHeaderSize;\r
} EFI_FIRMWARE_VOLUME_EXT_HEADER;\r
\r
///\r
///\r
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.\r
///\r
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
///\r
/// A bit mask, one bit for each file type between 0xC0 (bit 0) and 0xDF (bit 31). If a bit\r
/// is '1', then the GUID entry exists in Types. If a bit is '0' then no GUID entry exists in Types.\r
///\r
- UINT32 TypeMask;\r
+ UINT32 TypeMask;\r
///\r
/// An array of GUIDs, each GUID representing an OEM file type.\r
///\r
///\r
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_OEM_TYPE;\r
\r
-#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002\r
+#define EFI_FV_EXT_TYPE_GUID_TYPE 0x0002\r
\r
///\r
/// This extension header EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE provides a vendor specific\r
///\r
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_OEM_TYPE.\r
///\r
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
///\r
/// Vendor-specific GUID.\r
///\r
- EFI_GUID FormatType;\r
+ EFI_GUID FormatType;\r
///\r
/// An arry of bytes of length Length.\r
///\r
///\r
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;\r
\r
-#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03\r
+#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03\r
\r
///\r
/// The EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find\r
///\r
/// Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE.\r
///\r
- EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
+ EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr;\r
///\r
/// The number of bytes of the FV that are in uses. The remaining\r
/// EFI_FIRMWARE_VOLUME_HEADER FvLength minus UsedSize bytes in\r
/// the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY.\r
///\r
- UINT32 UsedSize;\r
+ UINT32 UsedSize;\r
} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE;\r
\r
#endif\r
UINT32 Reserved;\r
} EFI_HOB_GENERIC_HEADER;\r
\r
-\r
///\r
/// Value of version in EFI_HOB_HANDOFF_INFO_TABLE.\r
///\r
-#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009\r
+#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009\r
\r
///\r
/// Contains general state information used by the HOB producer phase.\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_HANDOFF.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// The version number pertaining to the PHIT HOB definition.\r
/// This value is four bytes in length to provide an 8-byte aligned entry\r
/// when it is combined with the 4-byte BootMode.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// The system boot mode as determined during the HOB producer phase.\r
///\r
- EFI_BOOT_MODE BootMode;\r
+ EFI_BOOT_MODE BootMode;\r
///\r
/// The highest address location of memory that is allocated for use by the HOB producer\r
/// phase. This address must be 4-KB aligned to meet page restrictions of UEFI.\r
///\r
- EFI_PHYSICAL_ADDRESS EfiMemoryTop;\r
+ EFI_PHYSICAL_ADDRESS EfiMemoryTop;\r
///\r
/// The lowest address location of memory that is allocated for use by the HOB producer phase.\r
///\r
- EFI_PHYSICAL_ADDRESS EfiMemoryBottom;\r
+ EFI_PHYSICAL_ADDRESS EfiMemoryBottom;\r
///\r
/// The highest address location of free memory that is currently available\r
/// for use by the HOB producer phase.\r
///\r
- EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;\r
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;\r
///\r
/// The lowest address location of free memory that is available for use by the HOB producer phase.\r
///\r
- EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;\r
+ EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;\r
///\r
/// The end of the HOB list.\r
///\r
- EFI_PHYSICAL_ADDRESS EfiEndOfHobList;\r
+ EFI_PHYSICAL_ADDRESS EfiEndOfHobList;\r
} EFI_HOB_HANDOFF_INFO_TABLE;\r
\r
///\r
/// Type EFI_GUID is defined in InstallProtocolInterface() in the UEFI 2.0\r
/// specification.\r
///\r
- EFI_GUID Name;\r
+ EFI_GUID Name;\r
\r
///\r
/// The base address of memory allocated by this HOB. Type\r
/// EFI_PHYSICAL_ADDRESS is defined in AllocatePages() in the UEFI 2.0\r
/// specification.\r
///\r
- EFI_PHYSICAL_ADDRESS MemoryBaseAddress;\r
+ EFI_PHYSICAL_ADDRESS MemoryBaseAddress;\r
\r
///\r
/// The length in bytes of memory allocated by this HOB.\r
///\r
- UINT64 MemoryLength;\r
+ UINT64 MemoryLength;\r
\r
///\r
/// Defines the type of memory allocated by this HOB. The memory type definition\r
/// follows the EFI_MEMORY_TYPE definition. Type EFI_MEMORY_TYPE is defined\r
/// in AllocatePages() in the UEFI 2.0 specification.\r
///\r
- EFI_MEMORY_TYPE MemoryType;\r
+ EFI_MEMORY_TYPE MemoryType;\r
\r
///\r
/// Padding for Itanium processor family\r
///\r
- UINT8 Reserved[4];\r
+ UINT8 Reserved[4];\r
} EFI_HOB_MEMORY_ALLOCATION_HEADER;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the\r
/// various attributes of the logical memory allocation.\r
///\r
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
//\r
// Additional data pertaining to the "Name" Guid memory\r
// may go here.\r
//\r
} EFI_HOB_MEMORY_ALLOCATION;\r
\r
-\r
///\r
/// Describes the memory stack that is produced by the HOB producer\r
/// phase and upon which all post-memory-installed executable\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the\r
/// various attributes of the logical memory allocation.\r
///\r
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
} EFI_HOB_MEMORY_ALLOCATION_STACK;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the\r
/// various attributes of the logical memory allocation.\r
///\r
- EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
+ EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor;\r
} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_ALLOCATION.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// An instance of the EFI_HOB_MEMORY_ALLOCATION_HEADER that describes the\r
/// various attributes of the logical memory allocation.\r
///\r
- EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;\r
+ EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader;\r
///\r
/// The GUID specifying the values of the firmware file system name\r
/// that contains the HOB consumer phase component.\r
///\r
- EFI_GUID ModuleName;\r
+ EFI_GUID ModuleName;\r
///\r
/// The address of the memory-mapped firmware volume\r
/// that contains the HOB consumer phase firmware file.\r
///\r
- EFI_PHYSICAL_ADDRESS EntryPoint;\r
+ EFI_PHYSICAL_ADDRESS EntryPoint;\r
} EFI_HOB_MEMORY_ALLOCATION_MODULE;\r
\r
///\r
//\r
// The following attributes are used to describe settings\r
//\r
-#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001\r
-#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002\r
-#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004\r
-#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080\r
+#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001\r
+#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002\r
+#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004\r
+#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080\r
//\r
// This is typically used as memory cacheability attribute today.\r
// NOTE: Since PI spec 1.4, please use EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED\r
// means Memory cacheability attribute: The memory supports being programmed with\r
// a writeprotected cacheable attribute.\r
//\r
-#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100\r
-#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200\r
-#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000\r
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100\r
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200\r
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTENT 0x00800000\r
//\r
// The rest of the attributes are used to describe capabilities\r
//\r
// writes, and EFI_RESOURCE_ATTRIBUTE_WRITE_PROTEC TABLE means Memory cacheability attribute:\r
// The memory supports being programmed with a writeprotected cacheable attribute.\r
//\r
-#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000\r
-#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000\r
-#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000\r
+#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000\r
+#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000\r
+#define EFI_RESOURCE_ATTRIBUTE_PERSISTABLE 0x01000000\r
\r
-#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000\r
-#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000\r
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTED 0x00040000\r
+#define EFI_RESOURCE_ATTRIBUTE_READ_ONLY_PROTECTABLE 0x00080000\r
\r
//\r
// Physical memory relative reliability attribute. This\r
// memory in the system. If all memory has the same\r
// reliability, then this bit is not used.\r
//\r
-#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000\r
+#define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000\r
\r
///\r
/// Describes the resource properties of all fixed,\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_RESOURCE_DESCRIPTOR.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// A GUID representing the owner of the resource. This GUID is used by HOB\r
/// consumer phase components to correlate device ownership of a resource.\r
///\r
- EFI_GUID Owner;\r
+ EFI_GUID Owner;\r
///\r
/// The resource type enumeration as defined by EFI_RESOURCE_TYPE.\r
///\r
- EFI_RESOURCE_TYPE ResourceType;\r
+ EFI_RESOURCE_TYPE ResourceType;\r
///\r
/// Resource attributes as defined by EFI_RESOURCE_ATTRIBUTE_TYPE.\r
///\r
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;\r
///\r
/// The physical start address of the resource region.\r
///\r
- EFI_PHYSICAL_ADDRESS PhysicalStart;\r
+ EFI_PHYSICAL_ADDRESS PhysicalStart;\r
///\r
/// The number of bytes of the resource region.\r
///\r
- UINT64 ResourceLength;\r
+ UINT64 ResourceLength;\r
} EFI_HOB_RESOURCE_DESCRIPTOR;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_GUID_EXTENSION.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// A GUID that defines the contents of this HOB.\r
///\r
- EFI_GUID Name;\r
+ EFI_GUID Name;\r
//\r
// Guid specific data goes here\r
//\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// The physical memory-mapped base address of the firmware volume.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
///\r
/// The length in bytes of the firmware volume.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
} EFI_HOB_FIRMWARE_VOLUME;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV2.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// The physical memory-mapped base address of the firmware volume.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
///\r
/// The length in bytes of the firmware volume.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
///\r
/// The name of the firmware volume.\r
///\r
- EFI_GUID FvName;\r
+ EFI_GUID FvName;\r
///\r
/// The name of the firmware file that contained this firmware volume.\r
///\r
- EFI_GUID FileName;\r
+ EFI_GUID FileName;\r
} EFI_HOB_FIRMWARE_VOLUME2;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// The physical memory-mapped base address of the firmware volume.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
///\r
/// The length in bytes of the firmware volume.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
///\r
/// The authentication status.\r
///\r
- UINT32 AuthenticationStatus;\r
+ UINT32 AuthenticationStatus;\r
///\r
/// TRUE if the FV was extracted as a file within another firmware volume.\r
/// FALSE otherwise.\r
///\r
- BOOLEAN ExtractedFv;\r
+ BOOLEAN ExtractedFv;\r
///\r
/// The name of the firmware volume.\r
/// Valid only if IsExtractedFv is TRUE.\r
///\r
- EFI_GUID FvName;\r
+ EFI_GUID FvName;\r
///\r
/// The name of the firmware file that contained this firmware volume.\r
/// Valid only if IsExtractedFv is TRUE.\r
///\r
- EFI_GUID FileName;\r
+ EFI_GUID FileName;\r
} EFI_HOB_FIRMWARE_VOLUME3;\r
\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_CPU.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
///\r
/// Identifies the maximum physical memory addressability of the processor.\r
///\r
- UINT8 SizeOfMemorySpace;\r
+ UINT8 SizeOfMemorySpace;\r
///\r
/// Identifies the maximum physical I/O addressability of the processor.\r
///\r
- UINT8 SizeOfIoSpace;\r
+ UINT8 SizeOfIoSpace;\r
///\r
/// This field will always be set to zero.\r
///\r
- UINT8 Reserved[6];\r
+ UINT8 Reserved[6];\r
} EFI_HOB_CPU;\r
\r
-\r
///\r
/// Describes pool memory allocations.\r
///\r
///\r
/// The HOB generic header. Header.HobType = EFI_HOB_TYPE_MEMORY_POOL.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
} EFI_HOB_MEMORY_POOL;\r
\r
///\r
///\r
/// The HOB generic header where Header.HobType = EFI_HOB_TYPE_UEFI_CAPSULE.\r
///\r
- EFI_HOB_GENERIC_HEADER Header;\r
+ EFI_HOB_GENERIC_HEADER Header;\r
\r
///\r
/// The physical memory-mapped base address of an UEFI capsule. This value is set to\r
/// point to the base of the contiguous memory of the UEFI capsule.\r
/// The length of the contiguous memory in bytes.\r
///\r
- EFI_PHYSICAL_ADDRESS BaseAddress;\r
- UINT64 Length;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ UINT64 Length;\r
} EFI_HOB_UEFI_CAPSULE;\r
\r
///\r
/// Union of all the possible HOB Types.\r
///\r
typedef union {\r
- EFI_HOB_GENERIC_HEADER *Header;\r
- EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;\r
- EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;\r
- EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;\r
- EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;\r
- EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;\r
- EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;\r
- EFI_HOB_GUID_TYPE *Guid;\r
- EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;\r
- EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;\r
- EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;\r
- EFI_HOB_CPU *Cpu;\r
- EFI_HOB_MEMORY_POOL *Pool;\r
- EFI_HOB_UEFI_CAPSULE *Capsule;\r
- UINT8 *Raw;\r
+ EFI_HOB_GENERIC_HEADER *Header;\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable;\r
+ EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation;\r
+ EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore;\r
+ EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack;\r
+ EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule;\r
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor;\r
+ EFI_HOB_GUID_TYPE *Guid;\r
+ EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume;\r
+ EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2;\r
+ EFI_HOB_FIRMWARE_VOLUME3 *FirmwareVolume3;\r
+ EFI_HOB_CPU *Cpu;\r
+ EFI_HOB_MEMORY_POOL *Pool;\r
+ EFI_HOB_UEFI_CAPSULE *Capsule;\r
+ UINT8 *Raw;\r
} EFI_PEI_HOB_POINTERS;\r
\r
-\r
#endif\r
/// I2C protocol stack to address the duplicated address space between 0\r
// and 127 in 10-bit mode.\r
///\r
-#define I2C_ADDRESSING_10_BIT 0x80000000\r
+#define I2C_ADDRESSING_10_BIT 0x80000000\r
\r
///\r
/// I2C controller capabilities\r
///\r
/// Length of this data structure in bytes\r
///\r
- UINT32 StructureSizeInBytes;\r
+ UINT32 StructureSizeInBytes;\r
\r
///\r
/// The maximum number of bytes the I2C host controller is able to\r
/// receive from the I2C bus.\r
///\r
- UINT32 MaximumReceiveBytes;\r
+ UINT32 MaximumReceiveBytes;\r
\r
///\r
/// The maximum number of bytes the I2C host controller is able to send\r
/// on the I2C bus.\r
///\r
- UINT32 MaximumTransmitBytes;\r
+ UINT32 MaximumTransmitBytes;\r
\r
///\r
/// The maximum number of bytes in the I2C bus transaction.\r
///\r
- UINT32 MaximumTotalBytes;\r
+ UINT32 MaximumTotalBytes;\r
} EFI_I2C_CONTROLLER_CAPABILITIES;\r
\r
///\r
/// combines both the manufacture name and the I2C part number into\r
/// a single value specified as a GUID.\r
///\r
- CONST EFI_GUID *DeviceGuid;\r
+ CONST EFI_GUID *DeviceGuid;\r
\r
///\r
/// Unique ID of the I2C part within the system\r
///\r
- UINT32 DeviceIndex;\r
+ UINT32 DeviceIndex;\r
\r
///\r
/// Hardware revision - ACPI _HRV value. See the Advanced\r
/// http://www.acpi.info/spec.htm\r
/// http://msdn.microsoft.com/en-us/library/windows/hardware/jj131711(v=vs.85).aspx\r
///\r
- UINT32 HardwareRevision;\r
+ UINT32 HardwareRevision;\r
\r
///\r
/// I2C bus configuration for the I2C device\r
///\r
- UINT32 I2cBusConfiguration;\r
+ UINT32 I2cBusConfiguration;\r
\r
///\r
/// Number of slave addresses for the I2C device.\r
///\r
- UINT32 SlaveAddressCount;\r
+ UINT32 SlaveAddressCount;\r
\r
///\r
/// Pointer to the array of slave addresses for the I2C device.\r
///\r
- CONST UINT32 *SlaveAddressArray;\r
+ CONST UINT32 *SlaveAddressArray;\r
} EFI_I2C_DEVICE;\r
\r
///\r
/// Define the I2C flags\r
///\r
/// I2C read operation when set\r
-#define I2C_FLAG_READ 0x00000001\r
+#define I2C_FLAG_READ 0x00000001\r
\r
///\r
/// Define the flags for SMBus operation\r
///\r
\r
/// SMBus operation\r
-#define I2C_FLAG_SMBUS_OPERATION 0x00010000\r
+#define I2C_FLAG_SMBUS_OPERATION 0x00010000\r
\r
/// SMBus block operation\r
/// The flag I2C_FLAG_SMBUS_BLOCK causes the I2C master protocol to update\r
/// of LengthInBytes is to be read from the device. The first byte\r
/// read contains the number of bytes remaining to be read, plus an\r
/// optional PEC value.\r
-#define I2C_FLAG_SMBUS_BLOCK 0x00020000\r
+#define I2C_FLAG_SMBUS_BLOCK 0x00020000\r
\r
/// SMBus process call operation\r
-#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000\r
+#define I2C_FLAG_SMBUS_PROCESS_CALL 0x00040000\r
\r
/// SMBus use packet error code (PEC)\r
/// Note that the I2C master protocol may clear the I2C_FLAG_SMBUS_PEC bit\r
/// to indicate that the PEC value was checked by the hardware and is\r
/// not appended to the returned read data.\r
///\r
-#define I2C_FLAG_SMBUS_PEC 0x00080000\r
+#define I2C_FLAG_SMBUS_PEC 0x00080000\r
\r
-//----------------------------------------------------------------------\r
+// ----------------------------------------------------------------------\r
///\r
/// QuickRead: OperationCount=1,\r
/// LengthInBytes=0, Flags=I2C_FLAG_READ\r
/// | I2C_FLAG_SMBUS_PEC\r
/// LengthInBytes=34, Flags=I2C_FLAG_READ\r
///\r
-//----------------------------------------------------------------------\r
+// ----------------------------------------------------------------------\r
\r
///\r
/// I2C device operation\r
///\r
/// Flags to qualify the I2C operation.\r
///\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
///\r
/// Number of bytes to send to or receive from the I2C device. A ping\r
/// (address only byte/bytes) is indicated by setting the LengthInBytes\r
/// to zero.\r
///\r
- UINT32 LengthInBytes;\r
+ UINT32 LengthInBytes;\r
\r
///\r
/// Pointer to a buffer containing the data to send or to receive from\r
/// the I2C device. The Buffer must be at least LengthInBytes in size.\r
///\r
- UINT8 *Buffer;\r
+ UINT8 *Buffer;\r
} EFI_I2C_OPERATION;\r
\r
///\r
///\r
/// Number of elements in the operation array\r
///\r
- UINTN OperationCount;\r
+ UINTN OperationCount;\r
\r
///\r
/// Description of the I2C operation\r
///\r
- EFI_I2C_OPERATION Operation [1];\r
+ EFI_I2C_OPERATION Operation[1];\r
} EFI_I2C_REQUEST_PACKET;\r
\r
-#endif // __PI_I2C_H__\r
+#endif // __PI_I2C_H__\r
#include <Pi/PiMultiPhase.h>\r
#include <Protocol/MmCpuIo.h>\r
\r
-typedef struct _EFI_MM_SYSTEM_TABLE EFI_MM_SYSTEM_TABLE;\r
+typedef struct _EFI_MM_SYSTEM_TABLE EFI_MM_SYSTEM_TABLE;\r
\r
///\r
/// The Management Mode System Table (MMST) signature\r
///\r
-#define MM_MMST_SIGNATURE SIGNATURE_32 ('S', 'M', 'S', 'T')\r
+#define MM_MMST_SIGNATURE SIGNATURE_32 ('S', 'M', 'S', 'T')\r
///\r
/// The Management Mode System Table (MMST) revision is 1.6\r
///\r
#define MM_SPECIFICATION_MAJOR_REVISION 1\r
#define MM_SPECIFICATION_MINOR_REVISION 60\r
-#define EFI_MM_SYSTEM_TABLE_REVISION ((MM_SPECIFICATION_MAJOR_REVISION<<16) | (MM_SPECIFICATION_MINOR_REVISION))\r
+#define EFI_MM_SYSTEM_TABLE_REVISION ((MM_SPECIFICATION_MAJOR_REVISION<<16) | (MM_SPECIFICATION_MINOR_REVISION))\r
\r
/**\r
Adds, updates, or removes a configuration table entry from the Management Mode System Table.\r
/// Processor information and functionality needed by MM Foundation.\r
///\r
typedef struct _EFI_MM_ENTRY_CONTEXT {\r
- EFI_MM_STARTUP_THIS_AP MmStartupThisAp;\r
+ EFI_MM_STARTUP_THIS_AP MmStartupThisAp;\r
///\r
/// A number between zero and the NumberOfCpus field. This field designates which\r
/// processor is executing the MM Foundation.\r
///\r
- UINTN CurrentlyExecutingCpu;\r
+ UINTN CurrentlyExecutingCpu;\r
///\r
/// The number of possible processors in the platform. This is a 1 based\r
/// counter. This does not indicate the number of processors that entered MM.\r
///\r
- UINTN NumberOfCpus;\r
+ UINTN NumberOfCpus;\r
///\r
/// Points to an array, where each element describes the number of bytes in the\r
/// corresponding save state specified by CpuSaveState. There are always\r
/// NumberOfCpus entries in the array.\r
///\r
- UINTN *CpuSaveStateSize;\r
+ UINTN *CpuSaveStateSize;\r
///\r
/// Points to an array, where each element is a pointer to a CPU save state. The\r
/// corresponding element in CpuSaveStateSize specifies the number of bytes in the\r
/// save state area. There are always NumberOfCpus entries in the array.\r
///\r
- VOID **CpuSaveState;\r
+ VOID **CpuSaveState;\r
} EFI_MM_ENTRY_CONTEXT;\r
\r
/**\r
///\r
/// The table header for the SMST.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
///\r
/// A pointer to a NULL-terminated Unicode string containing the vendor name.\r
/// It is permissible for this pointer to be NULL.\r
///\r
- CHAR16 *MmFirmwareVendor;\r
+ CHAR16 *MmFirmwareVendor;\r
///\r
/// The particular revision of the firmware.\r
///\r
- UINT32 MmFirmwareRevision;\r
+ UINT32 MmFirmwareRevision;\r
\r
- EFI_MM_INSTALL_CONFIGURATION_TABLE MmInstallConfigurationTable;\r
+ EFI_MM_INSTALL_CONFIGURATION_TABLE MmInstallConfigurationTable;\r
\r
///\r
/// I/O Service\r
///\r
- EFI_MM_CPU_IO_PROTOCOL MmIo;\r
+ EFI_MM_CPU_IO_PROTOCOL MmIo;\r
\r
///\r
/// Runtime memory services\r
///\r
- EFI_ALLOCATE_POOL MmAllocatePool;\r
- EFI_FREE_POOL MmFreePool;\r
- EFI_ALLOCATE_PAGES MmAllocatePages;\r
- EFI_FREE_PAGES MmFreePages;\r
+ EFI_ALLOCATE_POOL MmAllocatePool;\r
+ EFI_FREE_POOL MmFreePool;\r
+ EFI_ALLOCATE_PAGES MmAllocatePages;\r
+ EFI_FREE_PAGES MmFreePages;\r
\r
///\r
/// MP service\r
///\r
- EFI_MM_STARTUP_THIS_AP MmStartupThisAp;\r
+ EFI_MM_STARTUP_THIS_AP MmStartupThisAp;\r
\r
///\r
/// CPU information records\r
/// A number between zero and and the NumberOfCpus field. This field designates\r
/// which processor is executing the MM infrastructure.\r
///\r
- UINTN CurrentlyExecutingCpu;\r
+ UINTN CurrentlyExecutingCpu;\r
///\r
/// The number of possible processors in the platform. This is a 1 based counter.\r
///\r
- UINTN NumberOfCpus;\r
+ UINTN NumberOfCpus;\r
///\r
/// Points to an array, where each element describes the number of bytes in the\r
/// corresponding save state specified by CpuSaveState. There are always\r
/// NumberOfCpus entries in the array.\r
///\r
- UINTN *CpuSaveStateSize;\r
+ UINTN *CpuSaveStateSize;\r
///\r
/// Points to an array, where each element is a pointer to a CPU save state. The\r
/// corresponding element in CpuSaveStateSize specifies the number of bytes in the\r
/// save state area. There are always NumberOfCpus entries in the array.\r
///\r
- VOID **CpuSaveState;\r
+ VOID **CpuSaveState;\r
\r
///\r
/// Extensibility table\r
///\r
/// The number of UEFI Configuration Tables in the buffer MmConfigurationTable.\r
///\r
- UINTN NumberOfTableEntries;\r
+ UINTN NumberOfTableEntries;\r
///\r
/// A pointer to the UEFI Configuration Tables. The number of entries in the table is\r
/// NumberOfTableEntries.\r
///\r
- EFI_CONFIGURATION_TABLE *MmConfigurationTable;\r
+ EFI_CONFIGURATION_TABLE *MmConfigurationTable;\r
\r
///\r
/// Protocol services\r
///\r
- EFI_INSTALL_PROTOCOL_INTERFACE MmInstallProtocolInterface;\r
- EFI_UNINSTALL_PROTOCOL_INTERFACE MmUninstallProtocolInterface;\r
- EFI_HANDLE_PROTOCOL MmHandleProtocol;\r
- EFI_MM_REGISTER_PROTOCOL_NOTIFY MmRegisterProtocolNotify;\r
- EFI_LOCATE_HANDLE MmLocateHandle;\r
- EFI_LOCATE_PROTOCOL MmLocateProtocol;\r
+ EFI_INSTALL_PROTOCOL_INTERFACE MmInstallProtocolInterface;\r
+ EFI_UNINSTALL_PROTOCOL_INTERFACE MmUninstallProtocolInterface;\r
+ EFI_HANDLE_PROTOCOL MmHandleProtocol;\r
+ EFI_MM_REGISTER_PROTOCOL_NOTIFY MmRegisterProtocolNotify;\r
+ EFI_LOCATE_HANDLE MmLocateHandle;\r
+ EFI_LOCATE_PROTOCOL MmLocateProtocol;\r
\r
///\r
/// MMI Management functions\r
///\r
- EFI_MM_INTERRUPT_MANAGE MmiManage;\r
- EFI_MM_INTERRUPT_REGISTER MmiHandlerRegister;\r
- EFI_MM_INTERRUPT_UNREGISTER MmiHandlerUnRegister;\r
+ EFI_MM_INTERRUPT_MANAGE MmiManage;\r
+ EFI_MM_INTERRUPT_REGISTER MmiHandlerRegister;\r
+ EFI_MM_INTERRUPT_UNREGISTER MmiHandlerUnRegister;\r
};\r
\r
#endif\r
/// If this value is returned by an API, it means the capability is not yet\r
/// installed/available/ready to use.\r
///\r
-#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)\r
+#define EFI_NOT_AVAILABLE_YET DXE_ERROR (2)\r
\r
///\r
/// Success and warning codes reserved for use by PI.\r
/// Supported 32-bit range is 0x20000000-0x3fffffff.\r
/// Supported 64-bit range is 0x2000000000000000-0x3fffffffffffffff.\r
///\r
-#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))\r
+#define PI_ENCODE_WARNING(a) ((MAX_BIT >> 2) | (a))\r
\r
///\r
/// Error codes reserved for use by PI.\r
/// Supported 32-bit range is 0xa0000000-0xbfffffff.\r
/// Supported 64-bit range is 0xa000000000000000-0xbfffffffffffffff.\r
///\r
-#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))\r
+#define PI_ENCODE_ERROR(a) (MAX_BIT | (MAX_BIT >> 2) | (a))\r
\r
///\r
/// Return status codes defined in SMM CIS.\r
///\r
-#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)\r
+#define EFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0)\r
\r
#define EFI_WARN_INTERRUPT_SOURCE_PENDING PI_ENCODE_WARNING (0)\r
#define EFI_WARN_INTERRUPT_SOURCE_QUIESCED PI_ENCODE_WARNING (1)\r
/// 1010 Image was signed, the signature was tested, and the signature failed the authentication test.\r
///\r
///@{\r
-#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01\r
-#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02\r
-#define EFI_AUTH_STATUS_NOT_TESTED 0x04\r
-#define EFI_AUTH_STATUS_TEST_FAILED 0x08\r
-#define EFI_AUTH_STATUS_ALL 0x0f\r
+#define EFI_AUTH_STATUS_PLATFORM_OVERRIDE 0x01\r
+#define EFI_AUTH_STATUS_IMAGE_SIGNED 0x02\r
+#define EFI_AUTH_STATUS_NOT_TESTED 0x04\r
+#define EFI_AUTH_STATUS_TEST_FAILED 0x08\r
+#define EFI_AUTH_STATUS_ALL 0x0f\r
///@}\r
\r
///\r
/// MMRAM states and capabilities\r
///\r
-#define EFI_MMRAM_OPEN 0x00000001\r
-#define EFI_MMRAM_CLOSED 0x00000002\r
-#define EFI_MMRAM_LOCKED 0x00000004\r
-#define EFI_CACHEABLE 0x00000008\r
-#define EFI_ALLOCATED 0x00000010\r
-#define EFI_NEEDS_TESTING 0x00000020\r
-#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040\r
+#define EFI_MMRAM_OPEN 0x00000001\r
+#define EFI_MMRAM_CLOSED 0x00000002\r
+#define EFI_MMRAM_LOCKED 0x00000004\r
+#define EFI_CACHEABLE 0x00000008\r
+#define EFI_ALLOCATED 0x00000010\r
+#define EFI_NEEDS_TESTING 0x00000020\r
+#define EFI_NEEDS_ECC_INITIALIZATION 0x00000040\r
\r
-#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN\r
-#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED\r
-#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED\r
+#define EFI_SMRAM_OPEN EFI_MMRAM_OPEN\r
+#define EFI_SMRAM_CLOSED EFI_MMRAM_CLOSED\r
+#define EFI_SMRAM_LOCKED EFI_MMRAM_LOCKED\r
\r
///\r
/// Structure describing a MMRAM region and its accessibility attributes.\r
/// the same as seen by I/O-based agents, for example, but it may not be the address seen\r
/// by the processors.\r
///\r
- EFI_PHYSICAL_ADDRESS PhysicalStart;\r
+ EFI_PHYSICAL_ADDRESS PhysicalStart;\r
///\r
/// Designates the address of the MMRAM, as seen by software executing on the\r
/// processors. This address may or may not match PhysicalStart.\r
///\r
- EFI_PHYSICAL_ADDRESS CpuStart;\r
+ EFI_PHYSICAL_ADDRESS CpuStart;\r
///\r
/// Describes the number of bytes in the MMRAM region.\r
///\r
- UINT64 PhysicalSize;\r
+ UINT64 PhysicalSize;\r
///\r
/// Describes the accessibility attributes of the MMRAM. These attributes include the\r
/// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical\r
/// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC\r
/// initialization).\r
///\r
- UINT64 RegionState;\r
+ UINT64 RegionState;\r
} EFI_MMRAM_DESCRIPTOR;\r
\r
-typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;\r
+typedef EFI_MMRAM_DESCRIPTOR EFI_SMRAM_DESCRIPTOR;\r
\r
///\r
/// Structure describing a MMRAM region which cannot be used for the MMRAM heap.\r
/// The returned information associated with the requested TokenNumber. If\r
/// TokenNumber is 0, then PcdType is set to EFI_PCD_TYPE_8.\r
///\r
- EFI_PCD_TYPE PcdType;\r
+ EFI_PCD_TYPE PcdType;\r
///\r
/// The size of the data in bytes associated with the TokenNumber specified. If\r
/// TokenNumber is 0, then PcdSize is set 0.\r
///\r
- UINTN PcdSize;\r
+ UINTN PcdSize;\r
///\r
/// The null-terminated ASCII string associated with a given token. If the\r
/// TokenNumber specified was 0, then this field corresponds to the null-terminated\r
/// ASCII string associated with the token's namespace Guid. If NULL, there is no\r
/// name associated with this request.\r
///\r
- CHAR8 *PcdName;\r
+ CHAR8 *PcdName;\r
} EFI_PCD_INFO;\r
\r
/**\r
EFI_STATUS\r
(EFIAPI *EFI_AP_PROCEDURE2)(\r
IN VOID *ProcedureArgument\r
-);\r
+ );\r
\r
#endif\r
///\r
/// The handles of EFI FV.\r
///\r
-typedef VOID *EFI_PEI_FV_HANDLE;\r
+typedef VOID *EFI_PEI_FV_HANDLE;\r
\r
///\r
/// The handles of EFI FFS.\r
///\r
-typedef VOID *EFI_PEI_FILE_HANDLE;\r
+typedef VOID *EFI_PEI_FILE_HANDLE;\r
\r
///\r
/// Declare the forward reference data structure for EFI_PEI_SERVICE.\r
///\r
-typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES;\r
+typedef struct _EFI_PEI_SERVICES EFI_PEI_SERVICES;\r
\r
///\r
/// Declare the forward reference data structure for EFI_PEI_NOTIFY_DESCRIPTOR.\r
///\r
typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;\r
\r
-\r
#include <Ppi/CpuIo.h>\r
#include <Ppi/PciCfg2.h>\r
\r
-\r
/**\r
The PEI Dispatcher will invoke each PEIM one time. During this pass, the PEI\r
Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header.\r
/// This field is a set of flags describing the characteristics of this imported table entry.\r
/// All flags are defined as EFI_PEI_PPI_DESCRIPTOR_***, which can also be combined into one.\r
///\r
- UINTN Flags;\r
+ UINTN Flags;\r
///\r
/// The address of the EFI_GUID that names the interface.\r
///\r
- EFI_GUID *Guid;\r
+ EFI_GUID *Guid;\r
///\r
/// A pointer to the PPI. It contains the information necessary to install a service.\r
///\r
- VOID *Ppi;\r
+ VOID *Ppi;\r
} EFI_PEI_PPI_DESCRIPTOR;\r
\r
///\r
///\r
/// Details if the type of notification are callback or dispatch.\r
///\r
- UINTN Flags;\r
+ UINTN Flags;\r
///\r
/// The address of the EFI_GUID that names the interface.\r
///\r
- EFI_GUID *Guid;\r
+ EFI_GUID *Guid;\r
///\r
/// Address of the notification callback function itself within the PEIM.\r
///\r
- EFI_PEIM_NOTIFY_ENTRY_POINT Notify;\r
+ EFI_PEIM_NOTIFY_ENTRY_POINT Notify;\r
};\r
\r
///\r
///\r
/// The typedef structure of the notification descriptor.\r
///\r
- EFI_PEI_NOTIFY_DESCRIPTOR Notify;\r
+ EFI_PEI_NOTIFY_DESCRIPTOR Notify;\r
///\r
/// The typedef structure of the PPI descriptor.\r
///\r
- EFI_PEI_PPI_DESCRIPTOR Ppi;\r
+ EFI_PEI_PPI_DESCRIPTOR Ppi;\r
} EFI_PEI_DESCRIPTOR;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_FREE_PAGES) (\r
+(EFIAPI *EFI_PEI_FREE_PAGES)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PHYSICAL_ADDRESS Memory,\r
IN UINTN Pages\r
**/\r
typedef\r
VOID\r
-(EFIAPI *EFI_PEI_RESET2_SYSTEM) (\r
+(EFIAPI *EFI_PEI_RESET2_SYSTEM)(\r
IN EFI_RESET_TYPE ResetType,\r
IN EFI_STATUS ResetStatus,\r
IN UINTN DataSize,\r
///\r
/// Name of the file.\r
///\r
- EFI_GUID FileName;\r
+ EFI_GUID FileName;\r
///\r
/// File type.\r
///\r
- EFI_FV_FILETYPE FileType;\r
+ EFI_FV_FILETYPE FileType;\r
///\r
/// Attributes of the file.\r
///\r
- EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
///\r
/// Points to the file's data (not the header).\r
/// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED\r
/// is zero.\r
///\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
///\r
/// Size of the file's data.\r
///\r
- UINT32 BufferSize;\r
+ UINT32 BufferSize;\r
} EFI_FV_FILE_INFO;\r
\r
///\r
///\r
/// Name of the file.\r
///\r
- EFI_GUID FileName;\r
+ EFI_GUID FileName;\r
///\r
/// File type.\r
///\r
- EFI_FV_FILETYPE FileType;\r
+ EFI_FV_FILETYPE FileType;\r
///\r
/// Attributes of the file.\r
///\r
- EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
///\r
/// Points to the file's data (not the header).\r
/// Not valid if EFI_FV_FILE_ATTRIB_MEMORY_MAPPED\r
/// is zero.\r
///\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
///\r
/// Size of the file's data.\r
///\r
- UINT32 BufferSize;\r
+ UINT32 BufferSize;\r
///\r
/// Authentication status for this file.\r
///\r
- UINT32 AuthenticationStatus;\r
+ UINT32 AuthenticationStatus;\r
} EFI_FV_FILE_INFO2;\r
\r
/**\r
///\r
/// Attributes of the firmware volume.\r
///\r
- EFI_FVB_ATTRIBUTES_2 FvAttributes;\r
+ EFI_FVB_ATTRIBUTES_2 FvAttributes;\r
///\r
/// Format of the firmware volume.\r
///\r
- EFI_GUID FvFormat;\r
+ EFI_GUID FvFormat;\r
///\r
/// Name of the firmware volume.\r
///\r
- EFI_GUID FvName;\r
+ EFI_GUID FvName;\r
///\r
/// Points to the first byte of the firmware\r
/// volume, if bit EFI_FVB_MEMORY_MAPPED is\r
/// set in FvAttributes.\r
///\r
- VOID *FvStart;\r
+ VOID *FvStart;\r
///\r
/// Size of the firmware volume.\r
///\r
- UINT64 FvSize;\r
+ UINT64 FvSize;\r
} EFI_FV_INFO;\r
\r
/**\r
IN EFI_PEI_FILE_HANDLE FileHandle\r
);\r
\r
-\r
//\r
// PEI Specification Revision information\r
//\r
/// #define ((PEI_SPECIFICATION_MAJOR_REVISION<<16) |(PEI_SPECIFICATION_MINOR_REVISION))\r
/// and it should be as follows:\r
///\r
-#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))\r
+#define PEI_SERVICES_REVISION ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))\r
\r
///\r
/// EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI\r
///\r
/// The table header for the PEI Services Table.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
\r
//\r
// PPI Functions\r
//\r
- EFI_PEI_INSTALL_PPI InstallPpi;\r
- EFI_PEI_REINSTALL_PPI ReInstallPpi;\r
- EFI_PEI_LOCATE_PPI LocatePpi;\r
- EFI_PEI_NOTIFY_PPI NotifyPpi;\r
+ EFI_PEI_INSTALL_PPI InstallPpi;\r
+ EFI_PEI_REINSTALL_PPI ReInstallPpi;\r
+ EFI_PEI_LOCATE_PPI LocatePpi;\r
+ EFI_PEI_NOTIFY_PPI NotifyPpi;\r
\r
//\r
// Boot Mode Functions\r
//\r
- EFI_PEI_GET_BOOT_MODE GetBootMode;\r
- EFI_PEI_SET_BOOT_MODE SetBootMode;\r
+ EFI_PEI_GET_BOOT_MODE GetBootMode;\r
+ EFI_PEI_SET_BOOT_MODE SetBootMode;\r
\r
//\r
// HOB Functions\r
//\r
- EFI_PEI_GET_HOB_LIST GetHobList;\r
- EFI_PEI_CREATE_HOB CreateHob;\r
+ EFI_PEI_GET_HOB_LIST GetHobList;\r
+ EFI_PEI_CREATE_HOB CreateHob;\r
\r
//\r
// Firmware Volume Functions\r
//\r
- EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;\r
- EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;\r
- EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;\r
+ EFI_PEI_FFS_FIND_NEXT_VOLUME2 FfsFindNextVolume;\r
+ EFI_PEI_FFS_FIND_NEXT_FILE2 FfsFindNextFile;\r
+ EFI_PEI_FFS_FIND_SECTION_DATA2 FfsFindSectionData;\r
\r
//\r
// PEI Memory Functions\r
//\r
- EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;\r
- EFI_PEI_ALLOCATE_PAGES AllocatePages;\r
- EFI_PEI_ALLOCATE_POOL AllocatePool;\r
- EFI_PEI_COPY_MEM CopyMem;\r
- EFI_PEI_SET_MEM SetMem;\r
+ EFI_PEI_INSTALL_PEI_MEMORY InstallPeiMemory;\r
+ EFI_PEI_ALLOCATE_PAGES AllocatePages;\r
+ EFI_PEI_ALLOCATE_POOL AllocatePool;\r
+ EFI_PEI_COPY_MEM CopyMem;\r
+ EFI_PEI_SET_MEM SetMem;\r
\r
//\r
// Status Code\r
//\r
- EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;\r
+ EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;\r
\r
//\r
// Reset\r
//\r
- EFI_PEI_RESET_SYSTEM ResetSystem;\r
+ EFI_PEI_RESET_SYSTEM ResetSystem;\r
\r
//\r
// (the following interfaces are installed by publishing PEIM)\r
// I/O Abstractions\r
//\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
- EFI_PEI_PCI_CFG2_PPI *PciCfg;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ EFI_PEI_PCI_CFG2_PPI *PciCfg;\r
\r
//\r
// Future Installed Services\r
//\r
- EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;\r
- EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;\r
- EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;\r
- EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;\r
- EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;\r
- EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;\r
- EFI_PEI_RESET2_SYSTEM ResetSystem2;\r
- EFI_PEI_FREE_PAGES FreePages;\r
+ EFI_PEI_FFS_FIND_BY_NAME FfsFindFileByName;\r
+ EFI_PEI_FFS_GET_FILE_INFO FfsGetFileInfo;\r
+ EFI_PEI_FFS_GET_VOLUME_INFO FfsGetVolumeInfo;\r
+ EFI_PEI_REGISTER_FOR_SHADOW RegisterForShadow;\r
+ EFI_PEI_FFS_FIND_SECTION_DATA3 FindSectionData3;\r
+ EFI_PEI_FFS_GET_FILE_INFO2 FfsGetFileInfo2;\r
+ EFI_PEI_RESET2_SYSTEM ResetSystem2;\r
+ EFI_PEI_FREE_PAGES FreePages;\r
};\r
\r
-\r
///\r
/// EFI_SEC_PEI_HAND_OFF structure holds information about\r
/// PEI core's operating environment, such as the size of location of\r
///\r
/// Size of the data structure.\r
///\r
- UINT16 DataSize;\r
+ UINT16 DataSize;\r
\r
///\r
/// Points to the first byte of the boot firmware volume,\r
/// which the PEI Dispatcher should search for\r
/// PEI modules.\r
///\r
- VOID *BootFirmwareVolumeBase;\r
+ VOID *BootFirmwareVolumeBase;\r
\r
///\r
/// Size of the boot firmware volume, in bytes.\r
///\r
- UINTN BootFirmwareVolumeSize;\r
+ UINTN BootFirmwareVolumeSize;\r
\r
///\r
/// Points to the first byte of the temporary RAM.\r
///\r
- VOID *TemporaryRamBase;\r
+ VOID *TemporaryRamBase;\r
\r
///\r
/// Size of the temporary RAM, in bytes.\r
///\r
- UINTN TemporaryRamSize;\r
+ UINTN TemporaryRamSize;\r
\r
///\r
/// Points to the first byte of the temporary RAM\r
/// overlap with the area reported by StackBase and\r
/// StackSize.\r
///\r
- VOID *PeiTemporaryRamBase;\r
+ VOID *PeiTemporaryRamBase;\r
\r
///\r
/// The size of the available temporary RAM available for\r
/// use by the PEI Foundation, in bytes.\r
///\r
- UINTN PeiTemporaryRamSize;\r
+ UINTN PeiTemporaryRamSize;\r
\r
///\r
/// Points to the first byte of the stack.\r
/// TemporaryRamBase and TemporaryRamSize\r
/// or may be an entirely separate area.\r
///\r
- VOID *StackBase;\r
+ VOID *StackBase;\r
\r
///\r
/// Size of the stack, in bytes.\r
///\r
- UINTN StackSize;\r
+ UINTN StackSize;\r
} EFI_SEC_PEI_HAND_OFF;\r
\r
-\r
/**\r
The entry point of PEI Foundation.\r
\r
(EFIAPI *EFI_PEI_CORE_ENTRY_POINT)(\r
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
-);\r
+ );\r
\r
#endif\r
#ifndef _PI_S3_BOOT_SCRIPT_H_\r
#define _PI_S3_BOOT_SCRIPT_H_\r
\r
-//*******************************************\r
+// *******************************************\r
// EFI Boot Script Opcode definitions\r
-//*******************************************\r
-#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00\r
-#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01\r
-#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02\r
-#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05\r
-#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06\r
-#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07\r
-#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08\r
-#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09\r
-#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C\r
-#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D\r
-#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F\r
-#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10\r
+// *******************************************\r
+#define EFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00\r
+#define EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE 0x01\r
+#define EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE 0x02\r
+#define EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE 0x03\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE 0x04\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE 0x05\r
+#define EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE 0x06\r
+#define EFI_BOOT_SCRIPT_STALL_OPCODE 0x07\r
+#define EFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08\r
+#define EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE 0x09\r
+#define EFI_BOOT_SCRIPT_INFORMATION_OPCODE 0x0A\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE 0x0B\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE 0x0C\r
+#define EFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D\r
+#define EFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE 0x0F\r
+#define EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE 0x10\r
\r
-//*******************************************\r
+// *******************************************\r
// EFI_BOOT_SCRIPT_WIDTH\r
-//*******************************************\r
+// *******************************************\r
typedef enum {\r
EfiBootScriptWidthUint8,\r
EfiBootScriptWidthUint16,\r
#include <Pi/PiMmCis.h>\r
#include <Protocol/SmmCpuIo2.h>\r
\r
-typedef struct _EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2;\r
+typedef struct _EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2;\r
//\r
// Define new MM related definition introduced by PI 1.5.\r
//\r
IN UINTN TableSize\r
);\r
\r
-typedef EFI_MM_STARTUP_THIS_AP EFI_SMM_STARTUP_THIS_AP;\r
-typedef EFI_MM_NOTIFY_FN EFI_SMM_NOTIFY_FN;\r
-typedef EFI_MM_REGISTER_PROTOCOL_NOTIFY EFI_SMM_REGISTER_PROTOCOL_NOTIFY;\r
-typedef EFI_MM_INTERRUPT_MANAGE EFI_SMM_INTERRUPT_MANAGE;\r
-typedef EFI_MM_HANDLER_ENTRY_POINT EFI_SMM_HANDLER_ENTRY_POINT2;\r
-typedef EFI_MM_INTERRUPT_REGISTER EFI_SMM_INTERRUPT_REGISTER;\r
-typedef EFI_MM_INTERRUPT_UNREGISTER EFI_SMM_INTERRUPT_UNREGISTER;\r
+typedef EFI_MM_STARTUP_THIS_AP EFI_SMM_STARTUP_THIS_AP;\r
+typedef EFI_MM_NOTIFY_FN EFI_SMM_NOTIFY_FN;\r
+typedef EFI_MM_REGISTER_PROTOCOL_NOTIFY EFI_SMM_REGISTER_PROTOCOL_NOTIFY;\r
+typedef EFI_MM_INTERRUPT_MANAGE EFI_SMM_INTERRUPT_MANAGE;\r
+typedef EFI_MM_HANDLER_ENTRY_POINT EFI_SMM_HANDLER_ENTRY_POINT2;\r
+typedef EFI_MM_INTERRUPT_REGISTER EFI_SMM_INTERRUPT_REGISTER;\r
+typedef EFI_MM_INTERRUPT_UNREGISTER EFI_SMM_INTERRUPT_UNREGISTER;\r
\r
///\r
/// Processor information and functionality needed by SMM Foundation.\r
///\r
typedef struct _EFI_SMM_ENTRY_CONTEXT {\r
- EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;\r
+ EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;\r
///\r
/// A number between zero and the NumberOfCpus field. This field designates which\r
/// processor is executing the SMM Foundation.\r
///\r
- UINTN CurrentlyExecutingCpu;\r
+ UINTN CurrentlyExecutingCpu;\r
///\r
/// The number of possible processors in the platform. This is a 1 based\r
/// counter. This does not indicate the number of processors that entered SMM.\r
///\r
- UINTN NumberOfCpus;\r
+ UINTN NumberOfCpus;\r
///\r
/// Points to an array, where each element describes the number of bytes in the\r
/// corresponding save state specified by CpuSaveState. There are always\r
/// NumberOfCpus entries in the array.\r
///\r
- UINTN *CpuSaveStateSize;\r
+ UINTN *CpuSaveStateSize;\r
///\r
/// Points to an array, where each element is a pointer to a CPU save state. The\r
/// corresponding element in CpuSaveStateSize specifies the number of bytes in the\r
/// save state area. There are always NumberOfCpus entries in the array.\r
///\r
- VOID **CpuSaveState;\r
+ VOID **CpuSaveState;\r
} EFI_SMM_ENTRY_CONTEXT;\r
\r
/**\r
///\r
/// The table header for the SMST.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
///\r
/// A pointer to a NULL-terminated Unicode string containing the vendor name.\r
/// It is permissible for this pointer to be NULL.\r
///\r
- CHAR16 *SmmFirmwareVendor;\r
+ CHAR16 *SmmFirmwareVendor;\r
///\r
/// The particular revision of the firmware.\r
///\r
- UINT32 SmmFirmwareRevision;\r
+ UINT32 SmmFirmwareRevision;\r
\r
- EFI_SMM_INSTALL_CONFIGURATION_TABLE2 SmmInstallConfigurationTable;\r
+ EFI_SMM_INSTALL_CONFIGURATION_TABLE2 SmmInstallConfigurationTable;\r
\r
///\r
/// I/O Service\r
///\r
- EFI_SMM_CPU_IO2_PROTOCOL SmmIo;\r
+ EFI_SMM_CPU_IO2_PROTOCOL SmmIo;\r
\r
///\r
/// Runtime memory services\r
///\r
- EFI_ALLOCATE_POOL SmmAllocatePool;\r
- EFI_FREE_POOL SmmFreePool;\r
- EFI_ALLOCATE_PAGES SmmAllocatePages;\r
- EFI_FREE_PAGES SmmFreePages;\r
+ EFI_ALLOCATE_POOL SmmAllocatePool;\r
+ EFI_FREE_POOL SmmFreePool;\r
+ EFI_ALLOCATE_PAGES SmmAllocatePages;\r
+ EFI_FREE_PAGES SmmFreePages;\r
\r
///\r
/// MP service\r
///\r
- EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;\r
+ EFI_SMM_STARTUP_THIS_AP SmmStartupThisAp;\r
\r
///\r
/// CPU information records\r
/// A number between zero and and the NumberOfCpus field. This field designates\r
/// which processor is executing the SMM infrastructure.\r
///\r
- UINTN CurrentlyExecutingCpu;\r
+ UINTN CurrentlyExecutingCpu;\r
///\r
/// The number of possible processors in the platform. This is a 1 based counter.\r
///\r
- UINTN NumberOfCpus;\r
+ UINTN NumberOfCpus;\r
///\r
/// Points to an array, where each element describes the number of bytes in the\r
/// corresponding save state specified by CpuSaveState. There are always\r
/// NumberOfCpus entries in the array.\r
///\r
- UINTN *CpuSaveStateSize;\r
+ UINTN *CpuSaveStateSize;\r
///\r
/// Points to an array, where each element is a pointer to a CPU save state. The\r
/// corresponding element in CpuSaveStateSize specifies the number of bytes in the\r
/// save state area. There are always NumberOfCpus entries in the array.\r
///\r
- VOID **CpuSaveState;\r
+ VOID **CpuSaveState;\r
\r
///\r
/// Extensibility table\r
///\r
/// The number of UEFI Configuration Tables in the buffer SmmConfigurationTable.\r
///\r
- UINTN NumberOfTableEntries;\r
+ UINTN NumberOfTableEntries;\r
///\r
/// A pointer to the UEFI Configuration Tables. The number of entries in the table is\r
/// NumberOfTableEntries.\r
///\r
- EFI_CONFIGURATION_TABLE *SmmConfigurationTable;\r
+ EFI_CONFIGURATION_TABLE *SmmConfigurationTable;\r
\r
///\r
/// Protocol services\r
///\r
- EFI_INSTALL_PROTOCOL_INTERFACE SmmInstallProtocolInterface;\r
- EFI_UNINSTALL_PROTOCOL_INTERFACE SmmUninstallProtocolInterface;\r
- EFI_HANDLE_PROTOCOL SmmHandleProtocol;\r
- EFI_SMM_REGISTER_PROTOCOL_NOTIFY SmmRegisterProtocolNotify;\r
- EFI_LOCATE_HANDLE SmmLocateHandle;\r
- EFI_LOCATE_PROTOCOL SmmLocateProtocol;\r
+ EFI_INSTALL_PROTOCOL_INTERFACE SmmInstallProtocolInterface;\r
+ EFI_UNINSTALL_PROTOCOL_INTERFACE SmmUninstallProtocolInterface;\r
+ EFI_HANDLE_PROTOCOL SmmHandleProtocol;\r
+ EFI_SMM_REGISTER_PROTOCOL_NOTIFY SmmRegisterProtocolNotify;\r
+ EFI_LOCATE_HANDLE SmmLocateHandle;\r
+ EFI_LOCATE_PROTOCOL SmmLocateProtocol;\r
\r
///\r
/// SMI Management functions\r
///\r
- EFI_SMM_INTERRUPT_MANAGE SmiManage;\r
- EFI_SMM_INTERRUPT_REGISTER SmiHandlerRegister;\r
- EFI_SMM_INTERRUPT_UNREGISTER SmiHandlerUnRegister;\r
+ EFI_SMM_INTERRUPT_MANAGE SmiManage;\r
+ EFI_SMM_INTERRUPT_REGISTER SmiHandlerRegister;\r
+ EFI_SMM_INTERRUPT_UNREGISTER SmiHandlerUnRegister;\r
};\r
\r
#endif\r
///\r
/// Status Code Type Definition.\r
///\r
-typedef UINT32 EFI_STATUS_CODE_TYPE;\r
+typedef UINT32 EFI_STATUS_CODE_TYPE;\r
\r
///\r
/// A Status Code Type is made up of the code type and severity.\r
/// reserved for use by this specification.\r
///\r
///@{\r
-#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF\r
-#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000\r
-#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00\r
+#define EFI_STATUS_CODE_TYPE_MASK 0x000000FF\r
+#define EFI_STATUS_CODE_SEVERITY_MASK 0xFF000000\r
+#define EFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00\r
///@}\r
\r
///\r
/// this specification.\r
///\r
///@{\r
-#define EFI_PROGRESS_CODE 0x00000001\r
-#define EFI_ERROR_CODE 0x00000002\r
-#define EFI_DEBUG_CODE 0x00000003\r
+#define EFI_PROGRESS_CODE 0x00000001\r
+#define EFI_ERROR_CODE 0x00000002\r
+#define EFI_DEBUG_CODE 0x00000003\r
///@}\r
\r
///\r
/// the bad data could be consumed by other drivers.\r
///\r
///@{\r
-#define EFI_ERROR_MINOR 0x40000000\r
-#define EFI_ERROR_MAJOR 0x80000000\r
-#define EFI_ERROR_UNRECOVERED 0x90000000\r
-#define EFI_ERROR_UNCONTAINED 0xa0000000\r
+#define EFI_ERROR_MINOR 0x40000000\r
+#define EFI_ERROR_MAJOR 0x80000000\r
+#define EFI_ERROR_UNRECOVERED 0x90000000\r
+#define EFI_ERROR_UNCONTAINED 0xa0000000\r
///@}\r
\r
///\r
///\r
/// The size of the structure. This is specified to enable future expansion.\r
///\r
- UINT16 HeaderSize;\r
+ UINT16 HeaderSize;\r
///\r
/// The size of the data in bytes. This does not include the size of the header structure.\r
///\r
- UINT16 Size;\r
+ UINT16 Size;\r
///\r
/// The GUID defining the type of the data.\r
///\r
- EFI_GUID Type;\r
+ EFI_GUID Type;\r
} EFI_STATUS_CODE_DATA;\r
\r
///\r
/// - 0x1000-0x7FFF Subclass Specific.\r
/// - 0x8000-0xFFFF OEM specific.\r
///@{\r
-#define EFI_SUBCLASS_SPECIFIC 0x1000\r
-#define EFI_OEM_SPECIFIC 0x8000\r
+#define EFI_SUBCLASS_SPECIFIC 0x1000\r
+#define EFI_OEM_SPECIFIC 0x8000\r
///@}\r
\r
///\r
/// Values of 128-255 are reserved for OEM use.\r
///\r
///@{\r
-#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000)\r
-#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000)\r
-#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000)\r
-#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000)\r
-#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000)\r
-#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000)\r
-#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000)\r
+#define EFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000)\r
+#define EFI_COMPUTING_UNIT_HOST_PROCESSOR (EFI_COMPUTING_UNIT | 0x00010000)\r
+#define EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR (EFI_COMPUTING_UNIT | 0x00020000)\r
+#define EFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000)\r
+#define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000)\r
+#define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000)\r
+#define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000)\r
///@}\r
\r
///\r
///\r
/// Computing Unit Host Processor Subclass Progress Code definitions.\r
///@{\r
-#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
-#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
-#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
-#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
-#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
+#define EFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_CU_HP_PC_MEMORY_CONTROLLER_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
+#define EFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
///@}\r
\r
//\r
/// Computing Unit Cache Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
///@}\r
\r
///\r
///\r
/// South Bridge initialization prior to memory detection.\r
///\r
-#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)\r
+#define EFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000)\r
\r
///\r
/// North Bridge initialization prior to memory detection.\r
///\r
-#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)\r
+#define EFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001)\r
\r
///\r
/// South Bridge initialization after memory detection.\r
///\r
-#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)\r
+#define EFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002)\r
\r
///\r
/// North Bridge initialization after memory detection.\r
///\r
-#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)\r
+#define EFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003)\r
\r
///\r
/// PCI Host Bridge DXE initialization.\r
///\r
-#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)\r
+#define EFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004)\r
\r
///\r
/// North Bridge DXE initialization.\r
///\r
-#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)\r
+#define EFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005)\r
\r
///\r
/// North Bridge specific SMM initialization in DXE.\r
///\r
-#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)\r
+#define EFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006)\r
\r
///\r
/// Initialization of the South Bridge specific UEFI Runtime Services.\r
///\r
-#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)\r
+#define EFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007)\r
\r
///\r
/// South Bridge DXE initialization\r
///\r
-#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)\r
+#define EFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008)\r
\r
///\r
/// South Bridge specific SMM initialization in DXE.\r
///\r
-#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)\r
+#define EFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009)\r
\r
///\r
/// Initialization of the South Bridge devices.\r
/// Computing Unit Firmware Processor Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
///@}\r
\r
//\r
/// Computing Unit Cache Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
///@}\r
\r
///\r
/// Computing Unit Memory Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
-#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
-#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
-#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
-#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
-#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
-#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A)\r
+#define EFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
+#define EFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
+#define EFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
+#define EFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A)\r
///@}\r
\r
///\r
/// Peripheral Class Serial Port Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_P_SERIAL_PORT_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
///@}\r
\r
//\r
/// Peripheral Class Keyboard Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
///@}\r
\r
///\r
/// Peripheral Class Mouse Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
///@}\r
\r
//\r
/// These are shared by all subclasses.\r
///\r
///@{\r
-#define EFI_IOB_PC_INIT 0x00000000\r
-#define EFI_IOB_PC_RESET 0x00000001\r
-#define EFI_IOB_PC_DISABLE 0x00000002\r
-#define EFI_IOB_PC_DETECT 0x00000003\r
-#define EFI_IOB_PC_ENABLE 0x00000004\r
-#define EFI_IOB_PC_RECONFIG 0x00000005\r
-#define EFI_IOB_PC_HOTPLUG 0x00000006\r
+#define EFI_IOB_PC_INIT 0x00000000\r
+#define EFI_IOB_PC_RESET 0x00000001\r
+#define EFI_IOB_PC_DISABLE 0x00000002\r
+#define EFI_IOB_PC_DETECT 0x00000003\r
+#define EFI_IOB_PC_ENABLE 0x00000004\r
+#define EFI_IOB_PC_RECONFIG 0x00000005\r
+#define EFI_IOB_PC_HOTPLUG 0x00000006\r
///@}\r
\r
//\r
/// IO Bus Class PCI Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
///@}\r
\r
//\r
/// Software Class SEC Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
///@}\r
\r
///\r
/// Software Class DXE BS Driver Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
-#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
-#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
-#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
-#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
-#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
+#define EFI_SW_DXE_BS_PC_LEGACY_OPROM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
+#define EFI_SW_DXE_BS_PC_CONFIG_RESET (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
+#define EFI_SW_DXE_BS_PC_CSM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
///@}\r
\r
//\r
/// Software Class PEI Module Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
-#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
-#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
-#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
-#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
-#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
+#define EFI_SW_PEI_EC_NO_RECOVERY_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_PEI_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_PEI_EC_S3_RESUME_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_PEI_EC_S3_BOOT_SCRIPT_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
+#define EFI_SW_PEI_EC_S3_RESUME_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
+#define EFI_SW_PEI_EC_INVALID_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x00000009)\r
///@}\r
\r
///\r
/// Software Class DXE Foundation Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
///@}\r
\r
-\r
///\r
/// Software Class DXE Boot Service Driver Subclass Error Code definitions.\r
///\r
/// Software Class EFI DXE Service Subclass Error Code definitions.\r
///\r
///@{\r
-#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
-#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_SW_DXE_BS_PC_BEGIN_CONNECTING_DRIVERS (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_DXE_BS_PC_VERIFYING_PASSWORD (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
///@}\r
\r
///\r
/// Software Class DXE RT Driver Subclass Progress Code definitions.\r
///\r
///@{\r
-#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
-#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
-#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
-#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
-#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
-#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_SW_DXE_RT_PC_S0 (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_DXE_RT_PC_S1 (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_DXE_RT_PC_S2 (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_DXE_RT_PC_S3 (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_DXE_RT_PC_S4 (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_SW_DXE_RT_PC_S5 (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
///@}\r
\r
///\r
/// definitions in the EFI specification.\r
///\r
///@{\r
-#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR\r
-#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG\r
-#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI\r
-#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT\r
-#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW\r
-#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND\r
-#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE\r
-#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT\r
-#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS\r
-#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT\r
-#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT\r
-#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT\r
-#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT\r
-#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR\r
-#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK\r
-#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK\r
-#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD\r
+#define EFI_SW_EC_X64_DIVIDE_ERROR EXCEPT_X64_DIVIDE_ERROR\r
+#define EFI_SW_EC_X64_DEBUG EXCEPT_X64_DEBUG\r
+#define EFI_SW_EC_X64_NMI EXCEPT_X64_NMI\r
+#define EFI_SW_EC_X64_BREAKPOINT EXCEPT_X64_BREAKPOINT\r
+#define EFI_SW_EC_X64_OVERFLOW EXCEPT_X64_OVERFLOW\r
+#define EFI_SW_EC_X64_BOUND EXCEPT_X64_BOUND\r
+#define EFI_SW_EC_X64_INVALID_OPCODE EXCEPT_X64_INVALID_OPCODE\r
+#define EFI_SW_EC_X64_DOUBLE_FAULT EXCEPT_X64_DOUBLE_FAULT\r
+#define EFI_SW_EC_X64_INVALID_TSS EXCEPT_X64_INVALID_TSS\r
+#define EFI_SW_EC_X64_SEG_NOT_PRESENT EXCEPT_X64_SEG_NOT_PRESENT\r
+#define EFI_SW_EC_X64_STACK_FAULT EXCEPT_X64_STACK_FAULT\r
+#define EFI_SW_EC_X64_GP_FAULT EXCEPT_X64_GP_FAULT\r
+#define EFI_SW_EC_X64_PAGE_FAULT EXCEPT_X64_PAGE_FAULT\r
+#define EFI_SW_EC_X64_FP_ERROR EXCEPT_X64_FP_ERROR\r
+#define EFI_SW_EC_X64_ALIGNMENT_CHECK EXCEPT_X64_ALIGNMENT_CHECK\r
+#define EFI_SW_EC_X64_MACHINE_CHECK EXCEPT_X64_MACHINE_CHECK\r
+#define EFI_SW_EC_X64_SIMD EXCEPT_X64_SIMD\r
///@}\r
\r
///\r
/// definitions in the EFI specification.\r
///\r
///@{\r
-#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET\r
-#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION\r
-#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT\r
-#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT\r
-#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT\r
-#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED\r
-#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ\r
-#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ\r
+#define EFI_SW_EC_ARM_RESET EXCEPT_ARM_RESET\r
+#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION EXCEPT_ARM_UNDEFINED_INSTRUCTION\r
+#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT EXCEPT_ARM_SOFTWARE_INTERRUPT\r
+#define EFI_SW_EC_ARM_PREFETCH_ABORT EXCEPT_ARM_PREFETCH_ABORT\r
+#define EFI_SW_EC_ARM_DATA_ABORT EXCEPT_ARM_DATA_ABORT\r
+#define EFI_SW_EC_ARM_RESERVED EXCEPT_ARM_RESERVED\r
+#define EFI_SW_EC_ARM_IRQ EXCEPT_ARM_IRQ\r
+#define EFI_SW_EC_ARM_FIQ EXCEPT_ARM_FIQ\r
///@}\r
\r
#endif\r
#include <Pi/PiDxeCis.h>\r
\r
#endif\r
-\r
#include <Pi/PiMmCis.h>\r
\r
#endif\r
-\r
#include <Pi/PiPeiCis.h>\r
\r
#endif\r
-\r
#include <Pi/PiSmmCis.h>\r
\r
#endif\r
-\r
///\r
/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI.\r
///\r
-typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI;\r
+typedef struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI EFI_PEI_RECOVERY_BLOCK_IO_PPI;\r
\r
///\r
/// All blocks on the recovery device are addressed with a 64-bit Logical Block Address (LBA).\r
///\r
-typedef UINT64 EFI_PEI_LBA;\r
+typedef UINT64 EFI_PEI_LBA;\r
\r
///\r
/// EFI_PEI_BLOCK_DEVICE_TYPE\r
///\r
typedef enum {\r
- LegacyFloppy = 0, ///< The recovery device is a floppy.\r
- IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM\r
- IdeLS120 = 2, ///< The recovery device is an IDE LS-120\r
- UsbMassStorage= 3, ///< The recovery device is a USB Mass Storage device\r
- SD = 4, ///< The recovery device is a Secure Digital device\r
- EMMC = 5, ///< The recovery device is a eMMC device\r
- UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device\r
+ LegacyFloppy = 0, ///< The recovery device is a floppy.\r
+ IdeCDROM = 1, ///< The recovery device is an IDE CD-ROM\r
+ IdeLS120 = 2, ///< The recovery device is an IDE LS-120\r
+ UsbMassStorage = 3, ///< The recovery device is a USB Mass Storage device\r
+ SD = 4, ///< The recovery device is a Secure Digital device\r
+ EMMC = 5, ///< The recovery device is a eMMC device\r
+ UfsDevice = 6, ///< The recovery device is a Universal Flash Storage device\r
MaxDeviceType\r
} EFI_PEI_BLOCK_DEVICE_TYPE;\r
\r
///\r
/// The type of media device being referenced by DeviceIndex.\r
///\r
- EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;\r
+ EFI_PEI_BLOCK_DEVICE_TYPE DeviceType;\r
///\r
/// A flag that indicates if media is present. This flag is always set for\r
/// nonremovable media devices.\r
///\r
- BOOLEAN MediaPresent;\r
+ BOOLEAN MediaPresent;\r
///\r
/// The last logical block that the device supports.\r
///\r
- UINTN LastBlock;\r
+ UINTN LastBlock;\r
///\r
/// The size of a logical block in bytes.\r
///\r
- UINTN BlockSize;\r
+ UINTN BlockSize;\r
} EFI_PEI_BLOCK_IO_MEDIA;\r
\r
/**\r
///\r
/// Gets the number of block I/O devices that the specific block driver manages.\r
///\r
- EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;\r
+ EFI_PEI_GET_NUMBER_BLOCK_DEVICES GetNumberOfBlockDevices;\r
\r
///\r
/// Gets the specified media information.\r
///\r
- EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;\r
+ EFI_PEI_GET_DEVICE_MEDIA_INFORMATION GetBlockDeviceMediaInfo;\r
\r
///\r
/// Reads the requested number of blocks from the specified block device.\r
///\r
- EFI_PEI_READ_BLOCKS ReadBlocks;\r
+ EFI_PEI_READ_BLOCKS ReadBlocks;\r
};\r
\r
-extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid;\r
+extern EFI_GUID gEfiPeiVirtualBlockIoPpiGuid;\r
\r
#endif\r
///\r
/// The forward declaration for EFI_PEI_RECOVERY_BLOCK_IO_PPI.\r
///\r
-typedef struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI EFI_PEI_RECOVERY_BLOCK_IO2_PPI;\r
+typedef struct _EFI_PEI_RECOVERY_BLOCK_IO2_PPI EFI_PEI_RECOVERY_BLOCK_IO2_PPI;\r
\r
-#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION 0x00010000\r
+#define EFI_PEI_RECOVERY_BLOCK_IO2_PPI_REVISION 0x00010000\r
\r
typedef struct {\r
///\r
/// When more than one sub-type is associated with the interface, sub-type with\r
/// the smallest number must be used.\r
///\r
- UINT8 InterfaceType;\r
+ UINT8 InterfaceType;\r
///\r
/// A flag that indicates if media is removable.\r
///\r
- BOOLEAN RemovableMedia;\r
+ BOOLEAN RemovableMedia;\r
///\r
/// A flag that indicates if media is present. This flag is always set for\r
/// non-removable media devices.\r
///\r
- BOOLEAN MediaPresent;\r
+ BOOLEAN MediaPresent;\r
///\r
/// A flag that indicates if media is read-only.\r
///\r
- BOOLEAN ReadOnly;\r
+ BOOLEAN ReadOnly;\r
///\r
/// The size of a logical block in bytes.\r
///\r
- UINT32 BlockSize;\r
+ UINT32 BlockSize;\r
///\r
/// The last logical block that the device supports.\r
///\r
- EFI_PEI_LBA LastBlock;\r
+ EFI_PEI_LBA LastBlock;\r
} EFI_PEI_BLOCK_IO2_MEDIA;\r
\r
/**\r
/// The revision to which the interface adheres.\r
/// All future revisions must be backwards compatible.\r
///\r
- UINT64 Revision;\r
+ UINT64 Revision;\r
///\r
/// Gets the number of block I/O devices that the specific block driver manages.\r
///\r
- EFI_PEI_GET_NUMBER_BLOCK_DEVICES2 GetNumberOfBlockDevices;\r
+ EFI_PEI_GET_NUMBER_BLOCK_DEVICES2 GetNumberOfBlockDevices;\r
\r
///\r
/// Gets the specified media information.\r
///\r
- EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2 GetBlockDeviceMediaInfo;\r
+ EFI_PEI_GET_DEVICE_MEDIA_INFORMATION2 GetBlockDeviceMediaInfo;\r
\r
///\r
/// Reads the requested number of blocks from the specified block device.\r
///\r
- EFI_PEI_READ_BLOCKS2 ReadBlocks;\r
+ EFI_PEI_READ_BLOCKS2 ReadBlocks;\r
};\r
\r
-extern EFI_GUID gEfiPeiVirtualBlockIo2PpiGuid;\r
+extern EFI_GUID gEfiPeiVirtualBlockIo2PpiGuid;\r
\r
#endif\r
0x17ee496a, 0xd8e4, 0x4b9a, {0x94, 0xd1, 0xce, 0x82, 0x72, 0x30, 0x8, 0x50 } \\r
}\r
\r
-\r
-extern EFI_GUID gEfiPeiBootInRecoveryModePpiGuid;\r
+extern EFI_GUID gEfiPeiBootInRecoveryModePpiGuid;\r
\r
#endif\r
/// processing, and once memory is available, create a HOB for the capsule.\r
///\r
struct _EFI_PEI_CAPSULE_PPI {\r
- EFI_PEI_CAPSULE_COALESCE Coalesce;\r
- EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;\r
- EFI_PEI_CAPSULE_CREATE_STATE CreateState;\r
+ EFI_PEI_CAPSULE_COALESCE Coalesce;\r
+ EFI_PEI_CAPSULE_CHECK_CAPSULE_UPDATE CheckCapsuleUpdate;\r
+ EFI_PEI_CAPSULE_CREATE_STATE CreateState;\r
};\r
\r
///\r
/// Keep name backwards compatible before PI Version 1.4\r
///\r
-extern EFI_GUID gPeiCapsulePpiGuid;\r
+extern EFI_GUID gPeiCapsulePpiGuid;\r
\r
-extern EFI_GUID gEfiPeiCapsulePpiGuid;\r
+extern EFI_GUID gEfiPeiCapsulePpiGuid;\r
\r
#endif // #ifndef _PEI_CAPSULE_PPI_H_\r
#define EFI_PEI_CPU_IO_PPI_INSTALLED_GUID \\r
{ 0xe6af1f7b, 0xfc3f, 0x46da, {0xa8, 0x28, 0xa3, 0xb4, 0x57, 0xa4, 0x42, 0x82 } }\r
\r
-typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI;\r
+typedef struct _EFI_PEI_CPU_IO_PPI EFI_PEI_CPU_IO_PPI;\r
\r
///\r
/// EFI_PEI_CPU_IO_PPI_WIDTH.\r
///\r
/// This service provides the various modalities of memory and I/O read.\r
///\r
- EFI_PEI_CPU_IO_PPI_IO_MEM Read;\r
+ EFI_PEI_CPU_IO_PPI_IO_MEM Read;\r
///\r
/// This service provides the various modalities of memory and I/O write.\r
///\r
- EFI_PEI_CPU_IO_PPI_IO_MEM Write;\r
+ EFI_PEI_CPU_IO_PPI_IO_MEM Write;\r
} EFI_PEI_CPU_IO_PPI_ACCESS;\r
\r
/**\r
///\r
/// Collection of memory-access services.\r
///\r
- EFI_PEI_CPU_IO_PPI_ACCESS Mem;\r
+ EFI_PEI_CPU_IO_PPI_ACCESS Mem;\r
///\r
/// Collection of I/O-access services.\r
///\r
- EFI_PEI_CPU_IO_PPI_ACCESS Io;\r
-\r
- EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;\r
- EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;\r
- EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;\r
- EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;\r
-\r
- EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;\r
- EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;\r
- EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;\r
- EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;\r
-\r
- EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;\r
- EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;\r
- EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;\r
- EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;\r
-\r
- EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;\r
- EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;\r
- EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;\r
- EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;\r
+ EFI_PEI_CPU_IO_PPI_ACCESS Io;\r
+\r
+ EFI_PEI_CPU_IO_PPI_IO_READ8 IoRead8;\r
+ EFI_PEI_CPU_IO_PPI_IO_READ16 IoRead16;\r
+ EFI_PEI_CPU_IO_PPI_IO_READ32 IoRead32;\r
+ EFI_PEI_CPU_IO_PPI_IO_READ64 IoRead64;\r
+\r
+ EFI_PEI_CPU_IO_PPI_IO_WRITE8 IoWrite8;\r
+ EFI_PEI_CPU_IO_PPI_IO_WRITE16 IoWrite16;\r
+ EFI_PEI_CPU_IO_PPI_IO_WRITE32 IoWrite32;\r
+ EFI_PEI_CPU_IO_PPI_IO_WRITE64 IoWrite64;\r
+\r
+ EFI_PEI_CPU_IO_PPI_MEM_READ8 MemRead8;\r
+ EFI_PEI_CPU_IO_PPI_MEM_READ16 MemRead16;\r
+ EFI_PEI_CPU_IO_PPI_MEM_READ32 MemRead32;\r
+ EFI_PEI_CPU_IO_PPI_MEM_READ64 MemRead64;\r
+\r
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE8 MemWrite8;\r
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE16 MemWrite16;\r
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE32 MemWrite32;\r
+ EFI_PEI_CPU_IO_PPI_MEM_WRITE64 MemWrite64;\r
};\r
\r
-extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid;\r
+extern EFI_GUID gEfiPeiCpuIoPpiInstalledGuid;\r
\r
#endif\r
#define EFI_PEI_DECOMPRESS_PPI_GUID \\r
{ 0x1a36e4e7, 0xfab6, 0x476a, { 0x8e, 0x75, 0x69, 0x5a, 0x5, 0x76, 0xfd, 0xd7 } }\r
\r
-typedef struct _EFI_PEI_DECOMPRESS_PPI EFI_PEI_DECOMPRESS_PPI;\r
+typedef struct _EFI_PEI_DECOMPRESS_PPI EFI_PEI_DECOMPRESS_PPI;\r
\r
/**\r
Decompress a single compression section in a firmware file.\r
IN CONST EFI_COMPRESSION_SECTION *InputSection,\r
OUT VOID **OutputBuffer,\r
OUT UINTN *OutputSize\r
-);\r
-\r
+ );\r
\r
///\r
/// This PPI's single member function decompresses a compression\r
/// compression sections will be ignored.\r
///\r
struct _EFI_PEI_DECOMPRESS_PPI {\r
- EFI_PEI_DECOMPRESS_DECOMPRESS Decompress;\r
+ EFI_PEI_DECOMPRESS_DECOMPRESS Decompress;\r
};\r
\r
-\r
-extern EFI_GUID gEfiPeiDecompressPpiGuid;\r
+extern EFI_GUID gEfiPeiDecompressPpiGuid;\r
\r
#endif\r
0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6} } \\r
}\r
\r
-\r
/**\r
Delayed Dispatch function. This routine is called sometime after the required\r
delay. Upon return, if NewDelay is 0, the function is unregistered. If NewDelay\r
\r
typedef\r
VOID\r
-(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION) (\r
+(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION)(\r
IN OUT UINT64 *Context,\r
- OUT UINT32 *NewDelay\r
+ OUT UINT32 *NewDelay\r
);\r
\r
-\r
///\r
/// The forward declaration for EFI_DELAYED_DISPATCH_PPI\r
///\r
\r
-typedef struct _EFI_DELAYED_DISPATCH_PPI EFI_DELAYED_DISPATCH_PPI;\r
-\r
+typedef struct _EFI_DELAYED_DISPATCH_PPI EFI_DELAYED_DISPATCH_PPI;\r
\r
/**\r
Register a callback to be called after a minimum delay has occurred.\r
OUT UINT32 Delay\r
);\r
\r
-\r
///\r
/// This PPI is a pointer to the Delayed Dispatch Service.\r
/// This service will be published by the Pei Foundation. The PEI Foundation\r
/// execution.\r
///\r
struct _EFI_DELAYED_DISPATCH_PPI {\r
- EFI_DELAYED_DISPATCH_REGISTER Register;\r
+ EFI_DELAYED_DISPATCH_REGISTER Register;\r
};\r
\r
-\r
-extern EFI_GUID gEfiPeiDelayedDispatchPpiGuid;\r
+extern EFI_GUID gEfiPeiDelayedDispatchPpiGuid;\r
\r
#endif\r
/// regardless of the underlying device(s).\r
///\r
struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI {\r
- EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules; ///< Returns the number of DXE capsules residing on the device.\r
- EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo; ///< Returns the size and type of the requested recovery capsule.\r
- EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE capsule from some media into memory.\r
+ EFI_PEI_DEVICE_GET_NUMBER_RECOVERY_CAPSULE GetNumberRecoveryCapsules; ///< Returns the number of DXE capsules residing on the device.\r
+ EFI_PEI_DEVICE_GET_RECOVERY_CAPSULE_INFO GetRecoveryCapsuleInfo; ///< Returns the size and type of the requested recovery capsule.\r
+ EFI_PEI_DEVICE_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE capsule from some media into memory.\r
};\r
\r
-extern EFI_GUID gEfiPeiDeviceRecoveryModulePpiGuid;\r
+extern EFI_GUID gEfiPeiDeviceRecoveryModulePpiGuid;\r
\r
-#endif /* _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ */\r
+#endif /* _PEI_DEVICE_RECOVERY_MODULE_PPI_H_ */\r
/// The DXE IPL PPI may use PEI services to locate and load the DXE Foundation.\r
///\r
struct _EFI_DXE_IPL_PPI {\r
- EFI_DXE_IPL_ENTRY Entry;\r
+ EFI_DXE_IPL_ENTRY Entry;\r
};\r
\r
-extern EFI_GUID gEfiDxeIplPpiGuid;\r
+extern EFI_GUID gEfiDxeIplPpiGuid;\r
\r
#endif\r
0x605EA650, 0xC65C, 0x42e1, {0xBA, 0x80, 0x91, 0xA5, 0x2A, 0xB6, 0x18, 0xC6 } \\r
}\r
\r
-extern EFI_GUID gEfiEndOfPeiSignalPpiGuid;\r
+extern EFI_GUID gEfiEndOfPeiSignalPpiGuid;\r
\r
#endif\r
/// The FV format can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined\r
/// format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is the PI Firmware Volume format.\r
///\r
-typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI EFI_PEI_FIRMWARE_VOLUME_PPI;\r
-\r
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI EFI_PEI_FIRMWARE_VOLUME_PPI;\r
\r
/**\r
Process a firmware volume and create a volume handle.\r
IN VOID *Buffer,\r
IN UINTN BufferSize,\r
OUT EFI_PEI_FV_HANDLE *FvHandle\r
-);\r
+ );\r
\r
/**\r
Finds the next file of the specified type.\r
IN EFI_FV_FILETYPE SearchType,\r
IN EFI_PEI_FV_HANDLE FvHandle,\r
IN OUT EFI_PEI_FILE_HANDLE *FileHandle\r
-);\r
-\r
+ );\r
\r
/**\r
Find a file within a volume by its name.\r
IN CONST EFI_GUID *FileName,\r
IN EFI_PEI_FV_HANDLE *FvHandle,\r
OUT EFI_PEI_FILE_HANDLE *FileHandle\r
-);\r
-\r
+ );\r
\r
/**\r
Returns information about a specific file.\r
IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,\r
IN EFI_PEI_FILE_HANDLE FileHandle,\r
OUT EFI_FV_FILE_INFO *FileInfo\r
-);\r
+ );\r
\r
/**\r
Returns information about a specific file.\r
IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,\r
IN EFI_PEI_FILE_HANDLE FileHandle,\r
OUT EFI_FV_FILE_INFO2 *FileInfo\r
-);\r
+ );\r
\r
/**\r
This function returns information about the firmware volume.\r
IN CONST EFI_PEI_FIRMWARE_VOLUME_PPI *This,\r
IN EFI_PEI_FV_HANDLE FvHandle,\r
OUT EFI_FV_INFO *VolumeInfo\r
-);\r
+ );\r
\r
/**\r
Find the next matching section in the firmware file.\r
IN EFI_SECTION_TYPE SearchType,\r
IN EFI_PEI_FILE_HANDLE FileHandle,\r
OUT VOID **SectionData\r
-);\r
+ );\r
\r
/**\r
Find the next matching section in the firmware file.\r
IN EFI_PEI_FILE_HANDLE FileHandle,\r
OUT VOID **SectionData,\r
OUT UINT32 *AuthenticationStatus\r
-);\r
+ );\r
\r
-#define EFI_PEI_FIRMWARE_VOLUME_PPI_SIGNATURE SIGNATURE_32 ('P', 'F', 'V', 'P')\r
-#define EFI_PEI_FIRMWARE_VOLUME_PPI_REVISION 0x00010030\r
+#define EFI_PEI_FIRMWARE_VOLUME_PPI_SIGNATURE SIGNATURE_32 ('P', 'F', 'V', 'P')\r
+#define EFI_PEI_FIRMWARE_VOLUME_PPI_REVISION 0x00010030\r
\r
///\r
/// This PPI provides functions for accessing a memory-mapped firmware volume of a specific format.\r
///\r
struct _EFI_PEI_FIRMWARE_VOLUME_PPI {\r
- EFI_PEI_FV_PROCESS_FV ProcessVolume;\r
- EFI_PEI_FV_FIND_FILE_TYPE FindFileByType;\r
- EFI_PEI_FV_FIND_FILE_NAME FindFileByName;\r
- EFI_PEI_FV_GET_FILE_INFO GetFileInfo;\r
- EFI_PEI_FV_GET_INFO GetVolumeInfo;\r
- EFI_PEI_FV_FIND_SECTION FindSectionByType;\r
- EFI_PEI_FV_GET_FILE_INFO2 GetFileInfo2;\r
- EFI_PEI_FV_FIND_SECTION2 FindSectionByType2;\r
+ EFI_PEI_FV_PROCESS_FV ProcessVolume;\r
+ EFI_PEI_FV_FIND_FILE_TYPE FindFileByType;\r
+ EFI_PEI_FV_FIND_FILE_NAME FindFileByName;\r
+ EFI_PEI_FV_GET_FILE_INFO GetFileInfo;\r
+ EFI_PEI_FV_GET_INFO GetVolumeInfo;\r
+ EFI_PEI_FV_FIND_SECTION FindSectionByType;\r
+ EFI_PEI_FV_GET_FILE_INFO2 GetFileInfo2;\r
+ EFI_PEI_FV_FIND_SECTION2 FindSectionByType2;\r
///\r
/// Signature is used to keep backward-compatibility, set to {'P','F','V','P'}.\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Revision for further extension.\r
///\r
- UINT32 Revision;\r
+ UINT32 Revision;\r
};\r
\r
-extern EFI_GUID gEfiPeiFirmwareVolumePpiGuid;\r
+extern EFI_GUID gEfiPeiFirmwareVolumePpiGuid;\r
\r
#endif\r
#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO_H__\r
#define __EFI_PEI_FIRMWARE_VOLUME_INFO_H__\r
\r
-\r
-\r
#define EFI_PEI_FIRMWARE_VOLUME_INFO_PPI_GUID \\r
{ 0x49edb1c1, 0xbf21, 0x4761, { 0xbb, 0x12, 0xeb, 0x0, 0x31, 0xaa, 0xbb, 0x39 } }\r
\r
-typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI EFI_PEI_FIRMWARE_VOLUME_INFO_PPI;\r
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI EFI_PEI_FIRMWARE_VOLUME_INFO_PPI;\r
\r
///\r
/// This PPI describes the location and format of a firmware volume.\r
///\r
/// Unique identifier of the format of the memory-mapped firmware volume.\r
///\r
- EFI_GUID FvFormat;\r
+ EFI_GUID FvFormat;\r
///\r
/// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process\r
/// the volume. The format of this buffer is specific to the FvFormat.\r
/// For memory-mapped firmware volumes, this typically points to the first byte\r
/// of the firmware volume.\r
///\r
- VOID *FvInfo;\r
+ VOID *FvInfo;\r
///\r
/// Size of the data provided by FvInfo. For memory-mapped firmware volumes,\r
/// this is typically the size of the firmware volume.\r
///\r
- UINT32 FvInfoSize;\r
+ UINT32 FvInfoSize;\r
///\r
/// If the firmware volume originally came from a firmware file, then these\r
/// point to the parent firmware volume name and firmware volume file.\r
/// If it did not originally come from a firmware file, these should be NULL.\r
///\r
- EFI_GUID *ParentFvName;\r
+ EFI_GUID *ParentFvName;\r
///\r
/// If the firmware volume originally came from a firmware file, then these\r
/// point to the parent firmware volume name and firmware volume file.\r
/// If it did not originally come from a firmware file, these should be NULL.\r
///\r
- EFI_GUID *ParentFileName;\r
+ EFI_GUID *ParentFileName;\r
};\r
\r
-extern EFI_GUID gEfiPeiFirmwareVolumeInfoPpiGuid;\r
+extern EFI_GUID gEfiPeiFirmwareVolumeInfoPpiGuid;\r
\r
#endif\r
-\r
#ifndef __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__\r
#define __EFI_PEI_FIRMWARE_VOLUME_INFO2_H__\r
\r
-\r
-\r
#define EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI_GUID \\r
{ 0xea7ca24b, 0xded5, 0x4dad, { 0xa3, 0x89, 0xbf, 0x82, 0x7e, 0x8f, 0x9b, 0x38 } }\r
\r
-typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI;\r
+typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI;\r
\r
///\r
/// This PPI describes the location and format of a firmware volume.\r
///\r
/// Unique identifier of the format of the memory-mapped firmware volume.\r
///\r
- EFI_GUID FvFormat;\r
+ EFI_GUID FvFormat;\r
///\r
/// Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process\r
/// the volume. The format of this buffer is specific to the FvFormat.\r
/// For memory-mapped firmware volumes, this typically points to the first byte\r
/// of the firmware volume.\r
///\r
- VOID *FvInfo;\r
+ VOID *FvInfo;\r
///\r
/// Size of the data provided by FvInfo. For memory-mapped firmware volumes,\r
/// this is typically the size of the firmware volume.\r
///\r
- UINT32 FvInfoSize;\r
+ UINT32 FvInfoSize;\r
///\r
/// If the firmware volume originally came from a firmware file, then these\r
/// point to the parent firmware volume name and firmware volume file.\r
/// If it did not originally come from a firmware file, these should be NULL.\r
///\r
- EFI_GUID *ParentFvName;\r
+ EFI_GUID *ParentFvName;\r
///\r
/// If the firmware volume originally came from a firmware file, then these\r
/// point to the parent firmware volume name and firmware volume file.\r
/// If it did not originally come from a firmware file, these should be NULL.\r
///\r
- EFI_GUID *ParentFileName;\r
+ EFI_GUID *ParentFileName;\r
///\r
/// Authentication Status.\r
///\r
- UINT32 AuthenticationStatus;\r
+ UINT32 AuthenticationStatus;\r
};\r
\r
-extern EFI_GUID gEfiPeiFirmwareVolumeInfo2PpiGuid;\r
+extern EFI_GUID gEfiPeiFirmwareVolumeInfo2PpiGuid;\r
\r
#endif\r
-\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_GRAPHICS_INIT) (\r
+(EFIAPI *EFI_PEI_GRAPHICS_INIT)(\r
IN VOID *GraphicsPolicyPtr\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_GRAPHICS_GET_MODE) (\r
+(EFIAPI *EFI_PEI_GRAPHICS_GET_MODE)(\r
IN OUT EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode\r
);\r
\r
/// firmware modules.\r
///\r
struct _EFI_PEI_GRAPHICS_PPI {\r
- EFI_PEI_GRAPHICS_INIT GraphicsPpiInit;\r
- EFI_PEI_GRAPHICS_GET_MODE GraphicsPpiGetMode;\r
+ EFI_PEI_GRAPHICS_INIT GraphicsPpiInit;\r
+ EFI_PEI_GRAPHICS_GET_MODE GraphicsPpiGetMode;\r
};\r
\r
-extern EFI_GUID gEfiPeiGraphicsPpiGuid;\r
+extern EFI_GUID gEfiPeiGraphicsPpiGuid;\r
\r
#endif\r
// that it is intended to process.\r
//\r
\r
-\r
-typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI;\r
-\r
+typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI;\r
\r
/**\r
Processes the input section and returns the data contained therein\r
OUT VOID **OutputBuffer,\r
OUT UINTN *OutputSize,\r
OUT UINT32 *AuthenticationStatus\r
-);\r
+ );\r
\r
///\r
/// If a GUID-defined section is encountered when doing section extraction,\r
/// therein.\r
///\r
struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI {\r
- EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection;\r
+ EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection;\r
};\r
\r
-\r
-\r
#endif\r
-\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY) (\r
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY)(\r
IN EFI_PEI_I2C_MASTER_PPI *This,\r
IN UINTN *BusClockHertz\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET) (\r
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET)(\r
IN CONST EFI_PEI_I2C_MASTER_PPI *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST) (\r
+(EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST)(\r
IN CONST EFI_PEI_I2C_MASTER_PPI *This,\r
IN UINTN SlaveAddress,\r
IN EFI_I2C_REQUEST_PACKET *RequestPacket\r
/// using the current state of any switches or multiplexers in the I2C bus.\r
///\r
struct _EFI_PEI_I2C_MASTER_PPI {\r
- EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;\r
- EFI_PEI_I2C_MASTER_PPI_RESET Reset;\r
- EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;\r
- CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
- EFI_GUID Identifier;\r
+ EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;\r
+ EFI_PEI_I2C_MASTER_PPI_RESET Reset;\r
+ EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;\r
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
+ EFI_GUID Identifier;\r
};\r
\r
-extern EFI_GUID gEfiPeiI2cMasterPpiGuid;\r
+extern EFI_GUID gEfiPeiI2cMasterPpiGuid;\r
\r
#endif\r
0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58} \\r
}\r
\r
-typedef struct _EFI_ISA_HC_PPI EFI_ISA_HC_PPI;\r
-typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI;\r
+typedef struct _EFI_ISA_HC_PPI EFI_ISA_HC_PPI;\r
+typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI;\r
\r
/**\r
Open I/O aperture.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_ISA_HC_OPEN_IO) (\r
+(EFIAPI *EFI_PEI_ISA_HC_OPEN_IO)(\r
IN CONST EFI_ISA_HC_PPI *This,\r
IN UINT16 IoAddress,\r
IN UINT16 IoLength,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO) (\r
+(EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO)(\r
IN CONST EFI_ISA_HC_PPI *This,\r
IN UINT64 IoApertureHandle\r
);\r
///\r
/// An unsigned integer that specifies the version of the PPI structure.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// The address of the ISA/LPC Bridge device.\r
/// For PCI, this is the segment, bus, device and function of the a ISA/LPC\r
/// Bits 24-31 - Bus Type\r
/// If bits 24-31 are 0xff, then the definition is platform-specific.\r
///\r
- UINT32 Address;\r
+ UINT32 Address;\r
///\r
/// Opens an aperture on a positive-decode ISA Host Controller.\r
///\r
- EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture;\r
+ EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture;\r
///\r
/// Closes an aperture on a positive-decode ISA Host Controller.\r
///\r
- EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture;\r
+ EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture;\r
};\r
\r
-extern EFI_GUID gEfiIsaHcPpiGuid;\r
+extern EFI_GUID gEfiIsaHcPpiGuid;\r
\r
#endif\r
#define EFI_PEI_LOAD_FILE_PPI_GUID \\r
{ 0xb9e0abfe, 0x5979, 0x4914, { 0x97, 0x7f, 0x6d, 0xee, 0x78, 0xc2, 0x78, 0xa6 } }\r
\r
-\r
typedef struct _EFI_PEI_LOAD_FILE_PPI EFI_PEI_LOAD_FILE_PPI;\r
\r
/**\r
OUT UINT64 *ImageSize,\r
OUT EFI_PHYSICAL_ADDRESS *EntryPoint,\r
OUT UINT32 *AuthenticationState\r
-);\r
+ );\r
\r
///\r
/// This PPI is a pointer to the Load File service.\r
/// will use this service to launch the known PEI module images.\r
///\r
struct _EFI_PEI_LOAD_FILE_PPI {\r
- EFI_PEI_LOAD_FILE LoadFile;\r
+ EFI_PEI_LOAD_FILE LoadFile;\r
};\r
\r
-extern EFI_GUID gEfiPeiLoadFilePpiGuid;\r
+extern EFI_GUID gEfiPeiLoadFilePpiGuid;\r
\r
#endif\r
#define EFI_PEI_LOADED_IMAGE_PPI_GUID \\r
{ 0xc1fcd448, 0x6300, 0x4458, { 0xb8, 0x64, 0x28, 0xdf, 0x1, 0x53, 0x64, 0xbc } }\r
\r
-\r
-typedef struct _EFI_PEI_LOADED_IMAGE_PPI EFI_PEI_LOADED_IMAGE_PPI;\r
+typedef struct _EFI_PEI_LOADED_IMAGE_PPI EFI_PEI_LOADED_IMAGE_PPI;\r
\r
///\r
/// This interface is installed by the PEI Dispatcher after the image has been\r
///\r
/// Address of the image at the address where it will be executed.\r
///\r
- EFI_PHYSICAL_ADDRESS ImageAddress;\r
+ EFI_PHYSICAL_ADDRESS ImageAddress;\r
///\r
/// Size of the image as it will be executed.\r
///\r
- UINT64 ImageSize;\r
+ UINT64 ImageSize;\r
///\r
/// File handle from which the image was loaded.\r
/// Can be NULL, indicating the image was not loaded from a handle.\r
///\r
- EFI_PEI_FILE_HANDLE FileHandle;\r
+ EFI_PEI_FILE_HANDLE FileHandle;\r
};\r
\r
-\r
-extern EFI_GUID gEfiPeiLoadedImagePpiGuid;\r
+extern EFI_GUID gEfiPeiLoadedImagePpiGuid;\r
\r
#endif\r
0x7408d748, 0xfc8c, 0x4ee6, {0x92, 0x88, 0xc4, 0xbe, 0xc0, 0x92, 0xa4, 0x10 } \\r
}\r
\r
-extern EFI_GUID gEfiPeiMasterBootModePpiGuid;\r
+extern EFI_GUID gEfiPeiMasterBootModePpiGuid;\r
\r
#endif\r
0xf894643d, 0xc449, 0x42d1, {0x8e, 0xa8, 0x85, 0xbd, 0xd8, 0xc6, 0x5b, 0xde } \\r
}\r
\r
-extern EFI_GUID gEfiPeiMemoryDiscoveredPpiGuid;\r
+extern EFI_GUID gEfiPeiMemoryDiscoveredPpiGuid;\r
\r
#endif\r
#define EFI_PEI_MM_ACCESS_PPI_GUID \\r
{ 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}\r
\r
-typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI;\r
+typedef struct _EFI_PEI_MM_ACCESS_PPI EFI_PEI_MM_ACCESS_PPI;\r
\r
/**\r
Opens the MMRAM area to be accessible by a PEIM.\r
/// memory controller would publish this PPI.\r
///\r
struct _EFI_PEI_MM_ACCESS_PPI {\r
- EFI_PEI_MM_OPEN Open;\r
- EFI_PEI_MM_CLOSE Close;\r
- EFI_PEI_MM_LOCK Lock;\r
- EFI_PEI_MM_CAPABILITIES GetCapabilities;\r
- BOOLEAN LockState;\r
- BOOLEAN OpenState;\r
+ EFI_PEI_MM_OPEN Open;\r
+ EFI_PEI_MM_CLOSE Close;\r
+ EFI_PEI_MM_LOCK Lock;\r
+ EFI_PEI_MM_CAPABILITIES GetCapabilities;\r
+ BOOLEAN LockState;\r
+ BOOLEAN OpenState;\r
};\r
\r
-extern EFI_GUID gEfiPeiMmAccessPpiGuid;\r
+extern EFI_GUID gEfiPeiMmAccessPpiGuid;\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef MM_COMMUNICATION_PPI_H_\r
#define MM_COMMUNICATION_PPI_H_\r
\r
0xae933e1c, 0xcc47, 0x4e38, { 0x8f, 0xe, 0xe2, 0xf6, 0x1d, 0x26, 0x5, 0xdf } \\r
}\r
\r
-typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI;\r
+typedef struct _EFI_PEI_MM_COMMUNICATION_PPI EFI_PEI_MM_COMMUNICATION_PPI;\r
\r
/**\r
Communicates with a registered handler.\r
/// MMI handler.\r
///\r
struct _EFI_PEI_MM_COMMUNICATION_PPI {\r
- EFI_PEI_MM_COMMUNICATE Communicate;\r
+ EFI_PEI_MM_COMMUNICATE Communicate;\r
};\r
\r
-extern EFI_GUID gEfiPeiMmCommunicationPpiGuid;\r
+extern EFI_GUID gEfiPeiMmCommunicationPpiGuid;\r
\r
#endif\r
0xc109319, 0xc149, 0x450e, { 0xa3, 0xe3, 0xb9, 0xba, 0xdd, 0x9d, 0xc3, 0xa4 } \\r
}\r
\r
-typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI;\r
+typedef struct _EFI_PEI_MM_CONFIGURATION_PPI EFI_PEI_MM_CONFIGURATION_PPI;\r
\r
/**\r
This function registers the MM Foundation entry point with the processor code. This entry point will be\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY) (\r
+(EFIAPI *EFI_PEI_MM_REGISTER_MM_ENTRY)(\r
IN CONST EFI_PEI_MM_CONFIGURATION_PPI *This,\r
IN EFI_MM_ENTRY_POINT MmEntryPoint\r
);\r
/// MM entry vector code.\r
///\r
struct _EFI_PEI_MM_CONFIGURATION_PPI {\r
- EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;\r
- EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry;\r
+ EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;\r
+ EFI_PEI_MM_REGISTER_MM_ENTRY RegisterMmEntry;\r
};\r
\r
-extern EFI_GUID gEfiPeiMmConfigurationPpi;\r
+extern EFI_GUID gEfiPeiMmConfigurationPpi;\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _MM_CONTROL_PPI_H_\r
#define _MM_CONTROL_PPI_H_\r
\r
#define EFI_PEI_MM_CONTROL_PPI_GUID \\r
{ 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }\r
\r
-typedef struct _EFI_PEI_MM_CONTROL_PPI EFI_PEI_MM_CONTROL_PPI;\r
+typedef struct _EFI_PEI_MM_CONTROL_PPI EFI_PEI_MM_CONTROL_PPI;\r
\r
/**\r
Invokes PPI activation from the PI PEI environment.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MM_ACTIVATE) (\r
+(EFIAPI *EFI_PEI_MM_ACTIVATE)(\r
IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_MM_CONTROL_PPI * This,\r
+ IN EFI_PEI_MM_CONTROL_PPI *This,\r
IN OUT INT8 *ArgumentBuffer OPTIONAL,\r
IN OUT UINTN *ArgumentBufferSize OPTIONAL,\r
IN BOOLEAN Periodic OPTIONAL,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MM_DEACTIVATE) (\r
+(EFIAPI *EFI_PEI_MM_DEACTIVATE)(\r
IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_MM_CONTROL_PPI * This,\r
+ IN EFI_PEI_MM_CONTROL_PPI *This,\r
IN BOOLEAN Periodic OPTIONAL\r
);\r
\r
/// generate the MMI. Also, the hardware optionally supports the periodic generation of these signals.\r
///\r
struct _EFI_PEI_MM_CONTROL_PPI {\r
- EFI_PEI_MM_ACTIVATE Trigger;\r
- EFI_PEI_MM_DEACTIVATE Clear;\r
+ EFI_PEI_MM_ACTIVATE Trigger;\r
+ EFI_PEI_MM_DEACTIVATE Clear;\r
};\r
\r
-extern EFI_GUID gEfiPeiMmControlPpiGuid;\r
+extern EFI_GUID gEfiPeiMmControlPpiGuid;\r
\r
#endif\r
0xee16160a, 0xe8be, 0x47a6, { 0x82, 0xa, 0xc6, 0x90, 0xd, 0xb0, 0x25, 0xa } \\r
}\r
\r
-typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI ;\r
+typedef struct _EFI_PEI_MP_SERVICES_PPI EFI_PEI_MP_SERVICES_PPI;\r
\r
/**\r
Get the number of CPU's.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
OUT UINTN *NumberOfProcessors,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
IN UINTN ProcessorNumber,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_ALL_APS)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
IN EFI_AP_PROCEDURE Procedure,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_STARTUP_THIS_AP)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
IN EFI_AP_PROCEDURE Procedure,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_SWITCH_BSP)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
IN UINTN ProcessorNumber,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_ENABLEDISABLEAP)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
IN UINTN ProcessorNumber,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI) (\r
+(EFIAPI *EFI_PEI_MP_SERVICES_WHOAMI)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PEI_MP_SERVICES_PPI *This,\r
OUT UINTN *ProcessorNumber\r
/// handling multiprocessor support.\r
///\r
struct _EFI_PEI_MP_SERVICES_PPI {\r
- EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
- EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;\r
- EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;\r
- EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;\r
- EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;\r
- EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;\r
- EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;\r
+ EFI_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
+ EFI_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;\r
+ EFI_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;\r
+ EFI_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;\r
+ EFI_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;\r
+ EFI_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;\r
+ EFI_PEI_MP_SERVICES_WHOAMI WhoAmI;\r
};\r
\r
-extern EFI_GUID gEfiPeiMpServicesPpiGuid;\r
+extern EFI_GUID gEfiPeiMpServicesPpiGuid;\r
\r
#endif\r
#define PCD_PPI_GUID \\r
{ 0x6e81c58, 0x4ad7, 0x44bc, { 0x83, 0x90, 0xf1, 0x2, 0x65, 0xf7, 0x24, 0x80 } }\r
\r
-#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
-\r
+#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
\r
/**\r
Sets the SKU value for subsequent calls to set or get PCD token values.\r
IN UINTN SkuId\r
);\r
\r
-\r
-\r
/**\r
Retrieves an 8-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 16-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 32-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 64-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a pointer to a value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a Boolean value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the size of the value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves an 8-bit value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 16-bit value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 32-bit value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 64-bit value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a pointer to a value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves an Boolean value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the size of the value for a given PCD token and token space.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Sets an 8-bit value for a given PCD token.\r
\r
IN UINT8 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 16-bit value for a given PCD token.\r
\r
IN UINT16 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 32-bit value for a given PCD token.\r
\r
IN UINT32 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 64-bit value for a given PCD token.\r
\r
IN BOOLEAN Value\r
);\r
\r
-\r
-\r
/**\r
Sets an 8-bit value for a given PCD token.\r
\r
IN UINT8 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 16-bit value for a given PCD token.\r
\r
IN UINT16 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 32-bit value for a given PCD token.\r
\r
IN UINT32 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 64-bit value for a given PCD token.\r
\r
IN UINT64 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a value of a specified size for a given PCD token.\r
\r
IN BOOLEAN Value\r
);\r
\r
-\r
-\r
/**\r
Callback on SET function prototype definition.\r
\r
IN UINTN TokenDataSize\r
);\r
\r
-\r
-\r
/**\r
Specifies a function to be called anytime the value of a designated token is changed.\r
\r
IN PCD_PPI_CALLBACK CallBackFunction\r
);\r
\r
-\r
-\r
/**\r
Cancels a previously set callback function for a particular PCD token number.\r
\r
IN PCD_PPI_CALLBACK CallBackFunction\r
);\r
\r
-\r
-\r
/**\r
Retrieves the next valid token number in a given namespace.\r
\r
IN OUT UINTN *TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the next valid PCD token namespace for a given namespace.\r
\r
IN OUT CONST EFI_GUID **Guid\r
);\r
\r
-\r
-\r
///\r
/// This service abstracts the ability to set/get Platform Configuration Database (PCD).\r
///\r
typedef struct {\r
- PCD_PPI_SET_SKU SetSku;\r
-\r
- PCD_PPI_GET8 Get8;\r
- PCD_PPI_GET16 Get16;\r
- PCD_PPI_GET32 Get32;\r
- PCD_PPI_GET64 Get64;\r
- PCD_PPI_GET_POINTER GetPtr;\r
- PCD_PPI_GET_BOOLEAN GetBool;\r
- PCD_PPI_GET_SIZE GetSize;\r
-\r
- PCD_PPI_GET_EX_8 Get8Ex;\r
- PCD_PPI_GET_EX_16 Get16Ex;\r
- PCD_PPI_GET_EX_32 Get32Ex;\r
- PCD_PPI_GET_EX_64 Get64Ex;\r
- PCD_PPI_GET_EX_POINTER GetPtrEx;\r
- PCD_PPI_GET_EX_BOOLEAN GetBoolEx;\r
- PCD_PPI_GET_EX_SIZE GetSizeEx;\r
-\r
- PCD_PPI_SET8 Set8;\r
- PCD_PPI_SET16 Set16;\r
- PCD_PPI_SET32 Set32;\r
- PCD_PPI_SET64 Set64;\r
- PCD_PPI_SET_POINTER SetPtr;\r
- PCD_PPI_SET_BOOLEAN SetBool;\r
-\r
- PCD_PPI_SET_EX_8 Set8Ex;\r
- PCD_PPI_SET_EX_16 Set16Ex;\r
- PCD_PPI_SET_EX_32 Set32Ex;\r
- PCD_PPI_SET_EX_64 Set64Ex;\r
- PCD_PPI_SET_EX_POINTER SetPtrEx;\r
- PCD_PPI_SET_EX_BOOLEAN SetBoolEx;\r
-\r
- PCD_PPI_CALLBACK_ONSET CallbackOnSet;\r
- PCD_PPI_CANCEL_CALLBACK CancelCallback;\r
- PCD_PPI_GET_NEXT_TOKEN GetNextToken;\r
- PCD_PPI_GET_NEXT_TOKENSPACE GetNextTokenSpace;\r
+ PCD_PPI_SET_SKU SetSku;\r
+\r
+ PCD_PPI_GET8 Get8;\r
+ PCD_PPI_GET16 Get16;\r
+ PCD_PPI_GET32 Get32;\r
+ PCD_PPI_GET64 Get64;\r
+ PCD_PPI_GET_POINTER GetPtr;\r
+ PCD_PPI_GET_BOOLEAN GetBool;\r
+ PCD_PPI_GET_SIZE GetSize;\r
+\r
+ PCD_PPI_GET_EX_8 Get8Ex;\r
+ PCD_PPI_GET_EX_16 Get16Ex;\r
+ PCD_PPI_GET_EX_32 Get32Ex;\r
+ PCD_PPI_GET_EX_64 Get64Ex;\r
+ PCD_PPI_GET_EX_POINTER GetPtrEx;\r
+ PCD_PPI_GET_EX_BOOLEAN GetBoolEx;\r
+ PCD_PPI_GET_EX_SIZE GetSizeEx;\r
+\r
+ PCD_PPI_SET8 Set8;\r
+ PCD_PPI_SET16 Set16;\r
+ PCD_PPI_SET32 Set32;\r
+ PCD_PPI_SET64 Set64;\r
+ PCD_PPI_SET_POINTER SetPtr;\r
+ PCD_PPI_SET_BOOLEAN SetBool;\r
+\r
+ PCD_PPI_SET_EX_8 Set8Ex;\r
+ PCD_PPI_SET_EX_16 Set16Ex;\r
+ PCD_PPI_SET_EX_32 Set32Ex;\r
+ PCD_PPI_SET_EX_64 Set64Ex;\r
+ PCD_PPI_SET_EX_POINTER SetPtrEx;\r
+ PCD_PPI_SET_EX_BOOLEAN SetBoolEx;\r
+\r
+ PCD_PPI_CALLBACK_ONSET CallbackOnSet;\r
+ PCD_PPI_CANCEL_CALLBACK CancelCallback;\r
+ PCD_PPI_GET_NEXT_TOKEN GetNextToken;\r
+ PCD_PPI_GET_NEXT_TOKENSPACE GetNextTokenSpace;\r
} PCD_PPI;\r
\r
-\r
-extern EFI_GUID gPcdPpiGuid;\r
+extern EFI_GUID gPcdPpiGuid;\r
\r
#endif\r
#ifndef __PCD_INFO_PPI_H__\r
#define __PCD_INFO_PPI_H__\r
\r
-extern EFI_GUID gGetPcdInfoPpiGuid;\r
+extern EFI_GUID gGetPcdInfoPpiGuid;\r
\r
#define GET_PCD_INFO_PPI_GUID \\r
{ 0x4d8b155b, 0xc059, 0x4c8f, { 0x89, 0x26, 0x6, 0xfd, 0x43, 0x31, 0xdb, 0x8a } }\r
///\r
/// The forward declaration for GET_PCD_INFO_PPI.\r
///\r
-typedef struct _GET_PCD_INFO_PPI GET_PCD_INFO_PPI;\r
+typedef struct _GET_PCD_INFO_PPI GET_PCD_INFO_PPI;\r
\r
/**\r
Retrieve additional information associated with a PCD token in the default token space.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *GET_PCD_INFO_PPI_GET_INFO) (\r
+(EFIAPI *GET_PCD_INFO_PPI_GET_INFO)(\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve additional information associated with a PCD token.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *GET_PCD_INFO_PPI_GET_INFO_EX) (\r
+(EFIAPI *GET_PCD_INFO_PPI_GET_INFO_EX)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve the currently set SKU Id.\r
**/\r
typedef\r
UINTN\r
-(EFIAPI *GET_PCD_INFO_PPI_GET_SKU) (\r
+(EFIAPI *GET_PCD_INFO_PPI_GET_SKU)(\r
VOID\r
-);\r
+ );\r
\r
///\r
/// This is the PCD service to use when querying for some additional data that can be contained in the\r
///\r
/// Retrieve additional information associated with a PCD.\r
///\r
- GET_PCD_INFO_PPI_GET_INFO GetInfo;\r
- GET_PCD_INFO_PPI_GET_INFO_EX GetInfoEx;\r
+ GET_PCD_INFO_PPI_GET_INFO GetInfo;\r
+ GET_PCD_INFO_PPI_GET_INFO_EX GetInfoEx;\r
///\r
/// Retrieve the currently set SKU Id.\r
///\r
- GET_PCD_INFO_PPI_GET_SKU GetSku;\r
+ GET_PCD_INFO_PPI_GET_SKU GetSku;\r
};\r
\r
#endif\r
-\r
#define EFI_PEI_PCI_CFG2_PPI_GUID \\r
{ 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r
\r
-typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r
+typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r
\r
-#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r
+#define EFI_PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) \\r
(UINT64) ( \\r
(((UINTN) bus) << 24) | \\r
(((UINTN) dev) << 16) | \\r
///\r
/// 8-bit access\r
///\r
- EfiPeiPciCfgWidthUint8 = 0,\r
+ EfiPeiPciCfgWidthUint8 = 0,\r
///\r
/// 16-bit access\r
///\r
/// 8-bit register offset within the PCI configuration space for a given device's function\r
/// space.\r
///\r
- UINT8 Register;\r
+ UINT8 Register;\r
///\r
/// Only the 3 least-significant bits are used to encode one of 8 possible functions within a\r
/// given device.\r
///\r
- UINT8 Function;\r
+ UINT8 Function;\r
///\r
/// Only the 5 least-significant bits are used to encode one of 32 possible devices.\r
///\r
- UINT8 Device;\r
+ UINT8 Device;\r
///\r
/// 8-bit value to encode between 0 and 255 buses.\r
///\r
- UINT8 Bus;\r
+ UINT8 Bus;\r
///\r
/// Register number in PCI configuration space. If this field is zero, then Register is used\r
/// for the register number. If this field is non-zero, then Register is ignored and this field\r
/// is used for the register number.\r
///\r
- UINT32 ExtendedRegister;\r
+ UINT32 ExtendedRegister;\r
} EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r
\r
/**\r
IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
IN UINT64 Address,\r
IN OUT VOID *Buffer\r
-);\r
-\r
+ );\r
\r
/**\r
Performs a read-modify-write operation on the contents\r
IN UINT64 Address,\r
IN VOID *SetBits,\r
IN VOID *ClearBits\r
-);\r
+ );\r
\r
///\r
/// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r
/// controllers behind a PCI root bridge controller.\r
///\r
struct _EFI_PEI_PCI_CFG2_PPI {\r
- EFI_PEI_PCI_CFG2_PPI_IO Read;\r
- EFI_PEI_PCI_CFG2_PPI_IO Write;\r
- EFI_PEI_PCI_CFG2_PPI_RW Modify;\r
+ EFI_PEI_PCI_CFG2_PPI_IO Read;\r
+ EFI_PEI_PCI_CFG2_PPI_IO Write;\r
+ EFI_PEI_PCI_CFG2_PPI_RW Modify;\r
///\r
/// The PCI bus segment which the specified functions will access.\r
///\r
- UINT16 Segment;\r
+ UINT16 Segment;\r
};\r
\r
-\r
-extern EFI_GUID gEfiPciCfg2PpiGuid;\r
+extern EFI_GUID gEfiPciCfg2PpiGuid;\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef _EFI_PEI_CORE_FV_LOCATION_H_\r
#define _EFI_PEI_CORE_FV_LOCATION_H_\r
\r
VOID *PeiCoreFvLocation;\r
} EFI_PEI_CORE_FV_LOCATION_PPI;\r
\r
-extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;\r
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;\r
\r
#endif // _EFI_PEI_CORE_FV_LOCATION_H_\r
#ifndef __PI_PCD_PPI_H__\r
#define __PI_PCD_PPI_H__\r
\r
-extern EFI_GUID gEfiPeiPcdPpiGuid;\r
+extern EFI_GUID gEfiPeiPcdPpiGuid;\r
\r
#define EFI_PEI_PCD_PPI_GUID \\r
{ 0x1f34d25, 0x4de2, 0x23ad, { 0x3f, 0xf3, 0x36, 0x35, 0x3f, 0xf3, 0x23, 0xf1 } }\r
\r
-#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
+#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
\r
/**\r
SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. SetSku() is\r
VOID\r
(EFIAPI *EFI_PEI_PCD_PPI_SET_SKU)(\r
IN UINTN SkuId\r
-);\r
+ );\r
\r
/**\r
Retrieves the current byte-sized value for a PCD token number. If the TokenNumber is invalid,\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_8)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current word-sized value for a PCD token number. If the TokenNumber is invalid,\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_16)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current 32-bit value for a PCD token number. If the TokenNumber is invalid, the\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_32)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current 64-bit value for a PCD token number. If the TokenNumber is invalid, the\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_64)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current pointer to the value for a PCD token number. There should not be any\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_POINTER)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current Boolean-sized value for a PCD token number. If the TokenNumber is\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_BOOLEAN)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_SIZE)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Sets an 8-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT8 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 16-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT16 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 32-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT32 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 64-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT64 Value\r
-);\r
+ );\r
\r
/**\r
Sets a value of the specified size for a given PCD token.\r
IN UINTN TokenNumber,\r
IN OUT UINTN *SizeOfValue,\r
IN VOID *Buffer\r
-);\r
+ );\r
\r
/**\r
Sets a Boolean value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN BOOLEAN Value\r
-);\r
+ );\r
\r
typedef\r
VOID\r
IN UINTN CallBackToken,\r
IN OUT VOID *TokenData,\r
IN UINTN TokenDatSize\r
-);\r
+ );\r
\r
/**\r
Specifies a function to be called anytime the value of a designated token is changed.\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN CallBackToken,\r
IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction\r
-);\r
+ );\r
\r
/**\r
Cancels a previously set callback function for a particular PCD token number.\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN CallBackToken,\r
IN EFI_PEI_PCD_PPI_CALLBACK CallBackFunction\r
-);\r
+ );\r
\r
/**\r
Retrieves the next valid PCD token for a given namespace.\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN)(\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN *TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the next valid PCD token namespace for a given namespace.\r
EFI_STATUS\r
(EFIAPI *EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE)(\r
IN OUT CONST EFI_GUID **Guid\r
-);\r
+ );\r
\r
typedef struct {\r
- EFI_PEI_PCD_PPI_SET_SKU SetSku;\r
- EFI_PEI_PCD_PPI_GET_8 Get8;\r
- EFI_PEI_PCD_PPI_GET_16 Get16;\r
- EFI_PEI_PCD_PPI_GET_32 Get32;\r
- EFI_PEI_PCD_PPI_GET_64 Get64;\r
- EFI_PEI_PCD_PPI_GET_POINTER GetPtr;\r
- EFI_PEI_PCD_PPI_GET_BOOLEAN GetBool;\r
- EFI_PEI_PCD_PPI_GET_SIZE GetSize;\r
- EFI_PEI_PCD_PPI_SET_8 Set8;\r
- EFI_PEI_PCD_PPI_SET_16 Set16;\r
- EFI_PEI_PCD_PPI_SET_32 Set32;\r
- EFI_PEI_PCD_PPI_SET_64 Set64;\r
- EFI_PEI_PCD_PPI_SET_POINTER SetPtr;\r
- EFI_PEI_PCD_PPI_SET_BOOLEAN SetBool;\r
- EFI_PEI_PCD_PPI_CALLBACK_ON_SET CallbackOnSet;\r
- EFI_PEI_PCD_PPI_CANCEL_CALLBACK CancelCallback;\r
- EFI_PEI_PCD_PPI_GET_NEXT_TOKEN GetNextToken;\r
- EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;\r
+ EFI_PEI_PCD_PPI_SET_SKU SetSku;\r
+ EFI_PEI_PCD_PPI_GET_8 Get8;\r
+ EFI_PEI_PCD_PPI_GET_16 Get16;\r
+ EFI_PEI_PCD_PPI_GET_32 Get32;\r
+ EFI_PEI_PCD_PPI_GET_64 Get64;\r
+ EFI_PEI_PCD_PPI_GET_POINTER GetPtr;\r
+ EFI_PEI_PCD_PPI_GET_BOOLEAN GetBool;\r
+ EFI_PEI_PCD_PPI_GET_SIZE GetSize;\r
+ EFI_PEI_PCD_PPI_SET_8 Set8;\r
+ EFI_PEI_PCD_PPI_SET_16 Set16;\r
+ EFI_PEI_PCD_PPI_SET_32 Set32;\r
+ EFI_PEI_PCD_PPI_SET_64 Set64;\r
+ EFI_PEI_PCD_PPI_SET_POINTER SetPtr;\r
+ EFI_PEI_PCD_PPI_SET_BOOLEAN SetBool;\r
+ EFI_PEI_PCD_PPI_CALLBACK_ON_SET CallbackOnSet;\r
+ EFI_PEI_PCD_PPI_CANCEL_CALLBACK CancelCallback;\r
+ EFI_PEI_PCD_PPI_GET_NEXT_TOKEN GetNextToken;\r
+ EFI_PEI_PCD_PPI_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;\r
} EFI_PEI_PCD_PPI;\r
\r
#endif\r
#ifndef __PI_PCD_INFO_PPI_H__\r
#define __PI_PCD_INFO_PPI_H__\r
\r
-extern EFI_GUID gEfiGetPcdInfoPpiGuid;\r
+extern EFI_GUID gEfiGetPcdInfoPpiGuid;\r
\r
#define EFI_GET_PCD_INFO_PPI_GUID \\r
{ 0xa60c6b59, 0xe459, 0x425d, { 0x9c, 0x69, 0xb, 0xcc, 0x9c, 0xb2, 0x7d, 0x81 } }\r
///\r
/// The forward declaration for EFI_GET_PCD_INFO_PPI.\r
///\r
-typedef struct _EFI_GET_PCD_INFO_PPI EFI_GET_PCD_INFO_PPI;\r
+typedef struct _EFI_GET_PCD_INFO_PPI EFI_GET_PCD_INFO_PPI;\r
\r
/**\r
Retrieve additional information associated with a PCD token.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_INFO) (\r
+(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_INFO)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve the currently set SKU Id.\r
**/\r
typedef\r
UINTN\r
-(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_SKU) (\r
+(EFIAPI *EFI_GET_PCD_INFO_PPI_GET_SKU)(\r
VOID\r
-);\r
+ );\r
\r
///\r
/// This is the PCD service to use when querying for some additional data that can be contained in the\r
///\r
/// Retrieve additional information associated with a PCD.\r
///\r
- EFI_GET_PCD_INFO_PPI_GET_INFO GetInfo;\r
+ EFI_GET_PCD_INFO_PPI_GET_INFO GetInfo;\r
///\r
/// Retrieve the currently set SKU Id.\r
///\r
- EFI_GET_PCD_INFO_PPI_GET_SKU GetSku;\r
+ EFI_GET_PCD_INFO_PPI_GET_SKU GetSku;\r
};\r
\r
#endif\r
-\r
#define EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID \\r
{ 0x2ab86ef5, 0xecb5, 0x4134, { 0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4 } }\r
\r
-\r
-typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI EFI_PEI_READ_ONLY_VARIABLE2_PPI;\r
+typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI EFI_PEI_READ_ONLY_VARIABLE2_PPI;\r
\r
/**\r
This service retrieves a variable's value using its name and GUID.\r
OUT VOID *Data OPTIONAL\r
);\r
\r
-\r
/**\r
Return the next variable name and GUID.\r
\r
/// variable services.\r
///\r
struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI {\r
- EFI_PEI_GET_VARIABLE2 GetVariable;\r
- EFI_PEI_GET_NEXT_VARIABLE_NAME2 NextVariableName;\r
+ EFI_PEI_GET_VARIABLE2 GetVariable;\r
+ EFI_PEI_GET_NEXT_VARIABLE_NAME2 NextVariableName;\r
};\r
\r
-extern EFI_GUID gEfiPeiReadOnlyVariable2PpiGuid;\r
+extern EFI_GUID gEfiPeiReadOnlyVariable2PpiGuid;\r
\r
#endif\r
/// Finds and loads the recovery files.\r
///\r
struct _EFI_PEI_RECOVERY_MODULE_PPI {\r
- EFI_PEI_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE binary capsule into memory.\r
+ EFI_PEI_LOAD_RECOVERY_CAPSULE LoadRecoveryCapsule; ///< Loads a DXE binary capsule into memory.\r
};\r
\r
-extern EFI_GUID gEfiPeiRecoveryModulePpiGuid;\r
+extern EFI_GUID gEfiPeiRecoveryModulePpiGuid;\r
\r
#endif\r
IN UINT32 Instance,\r
IN CONST EFI_GUID *CallerId,\r
IN CONST EFI_STATUS_CODE_DATA *Data\r
-);\r
+ );\r
\r
/**\r
Register the callback function for ReportStatusCode() notification.\r
EFI_STATUS\r
(EFIAPI *EFI_PEI_RSC_HANDLER_REGISTER)(\r
IN EFI_PEI_RSC_HANDLER_CALLBACK Callback\r
-);\r
+ );\r
\r
/**\r
Remove a previously registered callback function from the notification list.\r
EFI_STATUS\r
(EFIAPI *EFI_PEI_RSC_HANDLER_UNREGISTER)(\r
IN EFI_PEI_RSC_HANDLER_CALLBACK Callback\r
-);\r
+ );\r
\r
typedef struct _EFI_PEI_RSC_HANDLER_PPI {\r
- EFI_PEI_RSC_HANDLER_REGISTER Register;\r
- EFI_PEI_RSC_HANDLER_UNREGISTER Unregister;\r
+ EFI_PEI_RSC_HANDLER_REGISTER Register;\r
+ EFI_PEI_RSC_HANDLER_UNREGISTER Unregister;\r
} EFI_PEI_RSC_HANDLER_PPI;\r
\r
-extern EFI_GUID gEfiPeiRscHandlerPpiGuid;\r
+extern EFI_GUID gEfiPeiRscHandlerPpiGuid;\r
\r
#endif // __REPORT_STATUS_CODE_HANDLER_PPI_H__\r
/// This PPI provides provide a simple reset service.\r
///\r
typedef struct {\r
- EFI_PEI_RESET_SYSTEM ResetSystem;\r
+ EFI_PEI_RESET_SYSTEM ResetSystem;\r
} EFI_PEI_RESET_PPI;\r
\r
-extern EFI_GUID gEfiPeiResetPpiGuid;\r
+extern EFI_GUID gEfiPeiResetPpiGuid;\r
\r
#endif\r
/// This PPI provides provide a simple reset service.\r
///\r
typedef struct _EFI_PEI_RESET2_PPI {\r
- EFI_PEI_RESET2_SYSTEM ResetSystem;\r
+ EFI_PEI_RESET2_SYSTEM ResetSystem;\r
} EFI_PEI_RESET2_PPI;\r
\r
-extern EFI_GUID gEfiPeiReset2PpiGuid;\r
+extern EFI_GUID gEfiPeiReset2PpiGuid;\r
\r
#endif\r
///\r
/// Forward declaration for EFI_PEI_S3_RESUME_PPI\r
///\r
-typedef struct _EFI_PEI_S3_RESUME2_PPI EFI_PEI_S3_RESUME2_PPI;\r
+typedef struct _EFI_PEI_S3_RESUME2_PPI EFI_PEI_S3_RESUME2_PPI;\r
\r
/**\r
Restores the platform to its preboot configuration for an S3 resume and\r
/// Restores the platform to its preboot configuration for an S3 resume and\r
/// jumps to the OS waking vector.\r
///\r
- EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2 S3RestoreConfig2;\r
+ EFI_PEI_S3_RESUME_PPI_RESTORE_CONFIG2 S3RestoreConfig2;\r
};\r
\r
-extern EFI_GUID gEfiPeiS3Resume2PpiGuid;\r
+extern EFI_GUID gEfiPeiS3Resume2PpiGuid;\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SEC_HOB_DATA_GET) (\r
+(EFIAPI *EFI_SEC_HOB_DATA_GET)(\r
IN CONST EFI_SEC_HOB_DATA_PPI *This,\r
OUT EFI_HOB_GENERIC_HEADER **HobList\r
-);\r
+ );\r
\r
///\r
/// This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.\r
///\r
struct _EFI_SEC_HOB_DATA_PPI {\r
- EFI_SEC_HOB_DATA_GET GetHobs;\r
+ EFI_SEC_HOB_DATA_GET GetHobs;\r
};\r
\r
-extern EFI_GUID gEfiSecHobDataPpiGuid;\r
+extern EFI_GUID gEfiSecHobDataPpiGuid;\r
\r
#endif\r
\r
typedef struct _EFI_SEC_PLATFORM_INFORMATION_PPI EFI_SEC_PLATFORM_INFORMATION_PPI;\r
\r
-\r
///\r
/// EFI_HEALTH_FLAGS\r
/// Contains information generated by microcode, hardware, and/or the Itanium\r
///\r
/// A 2-bit field indicating self-test state after reset.\r
///\r
- UINT32 Status : 2;\r
+ UINT32 Status : 2;\r
///\r
/// A 1-bit field indicating whether testing has occurred.\r
/// If this field is zero, the processor has not been tested,\r
/// and no further fields in the self-test State parameter are valid.\r
///\r
- UINT32 Tested : 1;\r
+ UINT32 Tested : 1;\r
///\r
/// Reserved 13 bits.\r
///\r
- UINT32 Reserved1 :13;\r
+ UINT32 Reserved1 : 13;\r
///\r
/// A 1-bit field. If set to 1, this indicates that virtual\r
/// memory features are not available.\r
///\r
- UINT32 VirtualMemoryUnavailable : 1;\r
+ UINT32 VirtualMemoryUnavailable : 1;\r
///\r
/// A 1-bit field. If set to 1, this indicates that IA-32 execution\r
/// is not available.\r
///\r
- UINT32 Ia32ExecutionUnavailable : 1;\r
+ UINT32 Ia32ExecutionUnavailable : 1;\r
///\r
/// A 1-bit field. If set to 1, this indicates that the floating\r
/// point unit is not available.\r
///\r
- UINT32 FloatingPointUnavailable : 1;\r
+ UINT32 FloatingPointUnavailable : 1;\r
///\r
/// A 1-bit field. If set to 1, this indicates miscellaneous\r
/// functional failure other than vm, ia, or fp.\r
/// performance restricted or functionally restricted.\r
/// The value returned is implementation dependent.\r
///\r
- UINT32 MiscFeaturesUnavailable : 1;\r
+ UINT32 MiscFeaturesUnavailable : 1;\r
///\r
/// Reserved 12 bits.\r
///\r
- UINT32 Reserved2 :12;\r
+ UINT32 Reserved2 : 12;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} EFI_HEALTH_FLAGS;\r
\r
-#define NORMAL_BOOT_CALL 0x0\r
-#define RECOVERY_CHECK_CALL 0x3\r
+#define NORMAL_BOOT_CALL 0x0\r
+#define RECOVERY_CHECK_CALL 0x3\r
\r
typedef EFI_HEALTH_FLAGS X64_HANDOFF_STATUS;\r
typedef EFI_HEALTH_FLAGS IA32_HANDOFF_STATUS;\r
/// SALE_ENTRY state : 3 = Recovery_Check\r
/// and 0 = RESET or Normal_Boot phase.\r
///\r
- UINT8 BootPhase;\r
+ UINT8 BootPhase;\r
///\r
/// Firmware status on entry to SALE.\r
///\r
- UINT8 FWStatus;\r
- UINT16 Reserved1;\r
- UINT32 Reserved2;\r
+ UINT8 FWStatus;\r
+ UINT16 Reserved1;\r
+ UINT32 Reserved2;\r
///\r
/// Geographically significant unique processor ID assigned by PAL.\r
///\r
- UINT16 ProcId;\r
- UINT16 Reserved3;\r
- UINT8 IdMask;\r
- UINT8 EidMask;\r
- UINT16 Reserved4;\r
+ UINT16 ProcId;\r
+ UINT16 Reserved3;\r
+ UINT8 IdMask;\r
+ UINT8 EidMask;\r
+ UINT16 Reserved4;\r
///\r
/// Address to make PAL calls.\r
///\r
- UINT64 PalCallAddress;\r
+ UINT64 PalCallAddress;\r
///\r
/// If the entry state is RECOVERY_CHECK, this contains the PAL_RESET\r
/// return address, and if entry state is RESET, this contains\r
/// address for PAL_authentication call.\r
///\r
- UINT64 PalSpecialAddress;\r
+ UINT64 PalSpecialAddress;\r
///\r
/// GR35 from PALE_EXIT state.\r
///\r
- UINT64 SelfTestStatus;\r
+ UINT64 SelfTestStatus;\r
///\r
/// GR37 from PALE_EXIT state.\r
///\r
- UINT64 SelfTestControl;\r
- UINT64 MemoryBufferRequired;\r
+ UINT64 SelfTestControl;\r
+ UINT64 MemoryBufferRequired;\r
} ITANIUM_HANDOFF_STATUS;\r
\r
///\r
/// EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
///\r
typedef union {\r
- IA32_HANDOFF_STATUS IA32HealthFlags;\r
- X64_HANDOFF_STATUS x64HealthFlags;\r
- ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;\r
+ IA32_HANDOFF_STATUS IA32HealthFlags;\r
+ X64_HANDOFF_STATUS x64HealthFlags;\r
+ ITANIUM_HANDOFF_STATUS ItaniumHealthFlags;\r
} EFI_SEC_PLATFORM_INFORMATION_RECORD;\r
\r
/**\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN OUT UINT64 *StructureSize,\r
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
-);\r
-\r
+ );\r
\r
///\r
/// This service abstracts platform-specific information. It is necessary\r
/// discover where to begin dispatching PEIMs.\r
///\r
struct _EFI_SEC_PLATFORM_INFORMATION_PPI {\r
- EFI_SEC_PLATFORM_INFORMATION PlatformInformation;\r
+ EFI_SEC_PLATFORM_INFORMATION PlatformInformation;\r
};\r
\r
-\r
-extern EFI_GUID gEfiSecPlatformInformationPpiGuid;\r
+extern EFI_GUID gEfiSecPlatformInformationPpiGuid;\r
\r
#endif\r
/// EFI_SEC_PLATFORM_INFORMATION_CPU.\r
///\r
typedef struct {\r
- UINT32 CpuLocation;\r
- EFI_SEC_PLATFORM_INFORMATION_RECORD InfoRecord;\r
+ UINT32 CpuLocation;\r
+ EFI_SEC_PLATFORM_INFORMATION_RECORD InfoRecord;\r
} EFI_SEC_PLATFORM_INFORMATION_CPU;\r
\r
///\r
///\r
/// The CPU location would be the local APIC ID\r
///\r
- UINT32 NumberOfCpus;\r
- EFI_SEC_PLATFORM_INFORMATION_CPU CpuInstance[1];\r
+ UINT32 NumberOfCpus;\r
+ EFI_SEC_PLATFORM_INFORMATION_CPU CpuInstance[1];\r
} EFI_SEC_PLATFORM_INFORMATION_RECORD2;\r
\r
/**\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN OUT UINT64 *StructureSize,\r
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
-);\r
+ );\r
\r
///\r
/// This service abstracts platform-specific information for many CPU's.\r
/// implementations that synchronize some, if not all CPU's in the SEC phase.\r
///\r
struct _EFI_SEC_PLATFORM_INFORMATION2_PPI {\r
- EFI_SEC_PLATFORM_INFORMATION2 PlatformInformation2;\r
+ EFI_SEC_PLATFORM_INFORMATION2 PlatformInformation2;\r
};\r
\r
-extern EFI_GUID gEfiSecPlatformInformation2PpiGuid;\r
+extern EFI_GUID gEfiSecPlatformInformation2PpiGuid;\r
\r
#endif\r
#define EFI_PEI_SECURITY2_PPI_GUID \\r
{ 0xdcd0be23, 0x9586, 0x40f4, { 0xb6, 0x43, 0x6, 0x52, 0x2c, 0xed, 0x4e, 0xde } }\r
\r
-\r
-typedef struct _EFI_PEI_SECURITY2_PPI EFI_PEI_SECURITY2_PPI;\r
+typedef struct _EFI_PEI_SECURITY2_PPI EFI_PEI_SECURITY2_PPI;\r
\r
/**\r
Allows the platform builder to implement a security policy\r
IN EFI_PEI_FV_HANDLE FvHandle,\r
IN EFI_PEI_FILE_HANDLE FileHandle,\r
IN OUT BOOLEAN *DeferExecution\r
-);\r
+ );\r
\r
///\r
/// This PPI is a means by which the platform builder can indicate\r
/// trusted.\r
///\r
struct _EFI_PEI_SECURITY2_PPI {\r
- EFI_PEI_SECURITY_AUTHENTICATION_STATE AuthenticationState;\r
+ EFI_PEI_SECURITY_AUTHENTICATION_STATE AuthenticationState;\r
};\r
\r
-\r
-extern EFI_GUID gEfiPeiSecurity2PpiGuid;\r
+extern EFI_GUID gEfiPeiSecurity2PpiGuid;\r
\r
#endif\r
#define EFI_PEI_SMBUS2_PPI_GUID \\r
{ 0x9ca93627, 0xb65b, 0x4324, { 0xa2, 0x2, 0xc0, 0xb4, 0x61, 0x76, 0x45, 0x43 } }\r
\r
-\r
typedef struct _EFI_PEI_SMBUS2_PPI EFI_PEI_SMBUS2_PPI;\r
\r
/**\r
IN BOOLEAN PecCheck,\r
IN OUT UINTN *Length,\r
IN OUT VOID *Buffer\r
-);\r
+ );\r
\r
/**\r
The ArpDevice() function enumerates the entire bus or enumerates a specific\r
IN BOOLEAN ArpAll,\r
IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL,\r
IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL\r
-);\r
+ );\r
\r
/**\r
The GetArpMap() function returns the mapping of all the SMBus devices\r
IN CONST EFI_PEI_SMBUS2_PPI *This,\r
IN OUT UINTN *Length,\r
IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap\r
-);\r
+ );\r
\r
/**\r
CallBack function can be registered in EFI_PEI_SMBUS2_PPI_NOTIFY.\r
IN CONST EFI_PEI_SMBUS2_PPI *SmbusPpi,\r
IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,\r
IN UINTN Data\r
-);\r
+ );\r
\r
/**\r
The Notify() function registers all the callback functions to allow the\r
IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,\r
IN UINTN Data,\r
IN EFI_PEI_SMBUS_NOTIFY2_FUNCTION NotifyFunction\r
-);\r
+ );\r
\r
///\r
/// Provides the basic I/O interfaces that a PEIM uses to access\r
/// its SMBus controller and the slave devices attached to it.\r
///\r
struct _EFI_PEI_SMBUS2_PPI {\r
- EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION Execute;\r
- EFI_PEI_SMBUS2_PPI_ARP_DEVICE ArpDevice;\r
- EFI_PEI_SMBUS2_PPI_GET_ARP_MAP GetArpMap;\r
- EFI_PEI_SMBUS2_PPI_NOTIFY Notify;\r
+ EFI_PEI_SMBUS2_PPI_EXECUTE_OPERATION Execute;\r
+ EFI_PEI_SMBUS2_PPI_ARP_DEVICE ArpDevice;\r
+ EFI_PEI_SMBUS2_PPI_GET_ARP_MAP GetArpMap;\r
+ EFI_PEI_SMBUS2_PPI_NOTIFY Notify;\r
///\r
/// Identifier which uniquely identifies this SMBus controller in a system.\r
///\r
- EFI_GUID Identifier;\r
+ EFI_GUID Identifier;\r
};\r
\r
-extern EFI_GUID gEfiPeiSmbus2PpiGuid;\r
+extern EFI_GUID gEfiPeiSmbus2PpiGuid;\r
\r
#endif\r
///\r
/// The resolution in microseconds of the stall services.\r
///\r
- UINTN Resolution;\r
+ UINTN Resolution;\r
\r
- EFI_PEI_STALL Stall;\r
+ EFI_PEI_STALL Stall;\r
};\r
\r
-extern EFI_GUID gEfiPeiStallPpiGuid;\r
+extern EFI_GUID gEfiPeiStallPpiGuid;\r
\r
#endif\r
/// There can be only one instance of this service in the system.\r
///\r
typedef struct {\r
- EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;\r
+ EFI_PEI_REPORT_STATUS_CODE ReportStatusCode;\r
} EFI_PEI_PROGRESS_CODE_PPI;\r
\r
-extern EFI_GUID gEfiPeiStatusCodePpiGuid;\r
+extern EFI_GUID gEfiPeiStatusCodePpiGuid;\r
\r
#endif\r
0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22} \\r
}\r
\r
-typedef struct _EFI_SIO_PPI EFI_SIO_PPI;\r
-typedef struct _EFI_SIO_PPI *PEFI_SIO_PPI;\r
+typedef struct _EFI_SIO_PPI EFI_SIO_PPI;\r
+typedef struct _EFI_SIO_PPI *PEFI_SIO_PPI;\r
\r
typedef UINT16 EFI_SIO_REGISTER;\r
-#define EFI_SIO_REG(ldn,reg) (EFI_SIO_REGISTER) (((ldn) << 8) | reg)\r
-#define EFI_SIO_LDN_GLOBAL 0xFF\r
+#define EFI_SIO_REG(ldn, reg) (EFI_SIO_REGISTER) (((ldn) << 8) | reg)\r
+#define EFI_SIO_LDN_GLOBAL 0xFF\r
\r
/**\r
Read a Super I/O register.\r
///\r
/// Specifies the end of the information list.\r
///\r
-#define EFI_ACPI_PNP_HID_END EFI_PNP_ID (0x0000)\r
+#define EFI_ACPI_PNP_HID_END EFI_PNP_ID (0x0000)\r
\r
-typedef UINT32 EFI_ACPI_HID;\r
-typedef UINT32 EFI_ACPI_UID;\r
+typedef UINT32 EFI_ACPI_HID;\r
+typedef UINT32 EFI_ACPI_UID;\r
#pragma pack(1)\r
typedef struct _EFI_SIO_INFO {\r
- EFI_ACPI_HID Hid;\r
- EFI_ACPI_UID Uid;\r
- UINT8 Ldn;\r
+ EFI_ACPI_HID Hid;\r
+ EFI_ACPI_UID Uid;\r
+ UINT8 Ldn;\r
} EFI_SIO_INFO, *PEFI_SIO_INFO;\r
#pragma pack()\r
\r
///\r
/// This function reads a register's value from the Super I/O controller.\r
///\r
- EFI_PEI_SIO_REGISTER_READ Read;\r
+ EFI_PEI_SIO_REGISTER_READ Read;\r
///\r
/// This function writes a value to a register in the Super I/O controller.\r
///\r
- EFI_PEI_SIO_REGISTER_WRITE Write;\r
+ EFI_PEI_SIO_REGISTER_WRITE Write;\r
///\r
/// This function modifies zero or more registers in the Super I/O controller\r
/// using a table.\r
///\r
- EFI_PEI_SIO_REGISTER_MODIFY Modify;\r
+ EFI_PEI_SIO_REGISTER_MODIFY Modify;\r
///\r
/// This GUID uniquely identifies the Super I/O controller.\r
///\r
- EFI_GUID SioGuid;\r
+ EFI_GUID SioGuid;\r
///\r
/// This pointer is to an array which maps EISA identifiers to logical devices numbers.\r
///\r
- PEFI_SIO_INFO Info;\r
+ PEFI_SIO_INFO Info;\r
};\r
\r
-extern EFI_GUID gEfiSioPpiGuid;\r
+extern EFI_GUID gEfiSioPpiGuid;\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_PEI_TEMPORARY_RAM_DONE) (\r
+(EFIAPI *EFI_PEI_TEMPORARY_RAM_DONE)(\r
VOID\r
);\r
\r
/// Permanent RAM to be enabled and accessed at the same time with no side effects.\r
///\r
typedef struct _EFI_PEI_TEMPORARY_RAM_DONE_PPI {\r
- EFI_PEI_TEMPORARY_RAM_DONE TemporaryRamDone;\r
+ EFI_PEI_TEMPORARY_RAM_DONE TemporaryRamDone;\r
} EFI_PEI_TEMPORARY_RAM_DONE_PPI;\r
\r
-extern EFI_GUID gEfiTemporaryRamDonePpiGuid;\r
+extern EFI_GUID gEfiTemporaryRamDonePpiGuid;\r
\r
#endif\r
#define EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI_GUID \\r
{ 0xdbe23aa9, 0xa345, 0x4b97, {0x85, 0xb6, 0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }\r
\r
-\r
/**\r
This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
permanent memory.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * TEMPORARY_RAM_MIGRATION)(\r
+(EFIAPI *TEMPORARY_RAM_MIGRATION)(\r
IN CONST EFI_PEI_SERVICES **PeiServices,\r
IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
IN UINTN CopySize\r
-);\r
+ );\r
\r
///\r
/// This service abstracts the ability to migrate contents of the platform early memory store.\r
/// This PPI was optional.\r
///\r
typedef struct {\r
- TEMPORARY_RAM_MIGRATION TemporaryRamMigration;\r
+ TEMPORARY_RAM_MIGRATION TemporaryRamMigration;\r
} EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI;\r
\r
-extern EFI_GUID gEfiTemporaryRamSupportPpiGuid;\r
+extern EFI_GUID gEfiTemporaryRamSupportPpiGuid;\r
\r
#endif\r
///\r
/// Vector Handoff Info Attributes\r
///@{\r
-#define EFI_VECTOR_HANDOFF_DO_NOT_HOOK 0x00000000\r
-#define EFI_VECTOR_HANDOFF_HOOK_BEFORE 0x00000001\r
-#define EFI_VECTOR_HANDOFF_HOOK_AFTER 0x00000002\r
-#define EFI_VECTOR_HANDOFF_LAST_ENTRY 0x80000000\r
+#define EFI_VECTOR_HANDOFF_DO_NOT_HOOK 0x00000000\r
+#define EFI_VECTOR_HANDOFF_HOOK_BEFORE 0x00000001\r
+#define EFI_VECTOR_HANDOFF_HOOK_AFTER 0x00000002\r
+#define EFI_VECTOR_HANDOFF_LAST_ENTRY 0x80000000\r
///@}\r
\r
///\r
//\r
// The interrupt or exception vector that is in use and must be preserved.\r
//\r
- UINT32 VectorNumber;\r
+ UINT32 VectorNumber;\r
//\r
// A bitmask that describes the attributes of the interrupt or exception vector.\r
//\r
- UINT32 Attribute;\r
+ UINT32 Attribute;\r
//\r
// The GUID identifies the party who created the entry. For the\r
// EFI_VECTOR_HANDOFF_DO_NOT_HOOK case, this establishes the single owner.\r
//\r
- EFI_GUID Owner;\r
+ EFI_GUID Owner;\r
} EFI_VECTOR_HANDOFF_INFO;\r
\r
///\r
//\r
// Pointer to an array of interrupt and /or exception vectors.\r
//\r
- EFI_VECTOR_HANDOFF_INFO *Info;\r
+ EFI_VECTOR_HANDOFF_INFO *Info;\r
} EFI_PEI_VECTOR_HANDOFF_INFO_PPI;\r
\r
-extern EFI_GUID gEfiVectorHandoffInfoPpiGuid;\r
+extern EFI_GUID gEfiVectorHandoffInfoPpiGuid;\r
\r
#endif\r
#ifndef __ABSOLUTE_POINTER_H__\r
#define __ABSOLUTE_POINTER_H__\r
\r
-\r
#define EFI_ABSOLUTE_POINTER_PROTOCOL_GUID \\r
{ 0x8D59D32B, 0xC655, 0x4AE9, { 0x9B, 0x15, 0xF2, 0x59, 0x04, 0x99, 0x2A, 0x43 } }\r
\r
-\r
typedef struct _EFI_ABSOLUTE_POINTER_PROTOCOL EFI_ABSOLUTE_POINTER_PROTOCOL;\r
\r
-\r
-//*******************************************************\r
+// *******************************************************\r
// EFI_ABSOLUTE_POINTER_MODE\r
-//*******************************************************\r
-\r
+// *******************************************************\r
\r
/**\r
The following data values in the EFI_ABSOLUTE_POINTER_MODE\r
interface functions.\r
**/\r
typedef struct {\r
- UINT64 AbsoluteMinX; ///< The Absolute Minimum of the device on the x-axis\r
- UINT64 AbsoluteMinY; ///< The Absolute Minimum of the device on the y axis.\r
- UINT64 AbsoluteMinZ; ///< The Absolute Minimum of the device on the z-axis\r
- UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the\r
- ///< AbsoluteMinX is 0, then the pointer device does not support a xaxis\r
- UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the\r
- ///< AbsoluteMinX is 0, then the pointer device does not support a yaxis.\r
- UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the\r
- ///< AbsoluteMinX is 0, then the pointer device does not support a zaxis\r
- UINT32 Attributes; ///< The following bits are set as needed (or'd together) to indicate the\r
- ///< capabilities of the device supported. The remaining bits are undefined\r
- ///< and should be 0\r
+ UINT64 AbsoluteMinX; ///< The Absolute Minimum of the device on the x-axis\r
+ UINT64 AbsoluteMinY; ///< The Absolute Minimum of the device on the y axis.\r
+ UINT64 AbsoluteMinZ; ///< The Absolute Minimum of the device on the z-axis\r
+ UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the\r
+ ///< AbsoluteMinX is 0, then the pointer device does not support a xaxis\r
+ UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the\r
+ ///< AbsoluteMinX is 0, then the pointer device does not support a yaxis.\r
+ UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the\r
+ ///< AbsoluteMinX is 0, then the pointer device does not support a zaxis\r
+ UINT32 Attributes; ///< The following bits are set as needed (or'd together) to indicate the\r
+ ///< capabilities of the device supported. The remaining bits are undefined\r
+ ///< and should be 0\r
} EFI_ABSOLUTE_POINTER_MODE;\r
\r
///\r
/// If set, indicates this device supports an alternate button input.\r
///\r
-#define EFI_ABSP_SupportsAltActive 0x00000001\r
+#define EFI_ABSP_SupportsAltActive 0x00000001\r
\r
///\r
/// If set, indicates this device returns pressure data in parameter CurrentZ.\r
///\r
#define EFI_ABSP_SupportsPressureAsZ 0x00000002\r
\r
-\r
/**\r
This function resets the pointer device hardware. As part of\r
initialization process, the firmware/device will make a quick\r
(EFIAPI *EFI_ABSOLUTE_POINTER_RESET)(\r
IN EFI_ABSOLUTE_POINTER_PROTOCOL *This,\r
IN BOOLEAN ExtendedVerification\r
-);\r
+ );\r
\r
///\r
/// This bit is set if the touch sensor is active.\r
///\r
/// This bit is set if the alt sensor, such as pen-side button, is active\r
///\r
-#define EFI_ABS_AltActive 0x00000002\r
-\r
+#define EFI_ABS_AltActive 0x00000002\r
\r
/**\r
Definition of EFI_ABSOLUTE_POINTER_STATE.\r
/// both 0, then this pointer device does not support an x-axis, and this field\r
/// must be ignored.\r
///\r
- UINT64 CurrentX;\r
+ UINT64 CurrentX;\r
\r
///\r
/// The unsigned position of the activation on the y axis. If the AboluteMinY\r
/// both 0, then this pointer device does not support an y-axis, and this field\r
/// must be ignored.\r
///\r
- UINT64 CurrentY;\r
+ UINT64 CurrentY;\r
\r
///\r
/// The unsigned position of the activation on the z axis, or the pressure\r
/// EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device\r
/// does not support an z-axis, and this field must be ignored.\r
///\r
- UINT64 CurrentZ;\r
+ UINT64 CurrentZ;\r
\r
///\r
/// Bits are set to 1 in this structure item to indicate that device buttons are\r
/// active.\r
///\r
- UINT32 ActiveButtons;\r
+ UINT32 ActiveButtons;\r
} EFI_ABSOLUTE_POINTER_STATE;\r
\r
/**\r
(EFIAPI *EFI_ABSOLUTE_POINTER_GET_STATE)(\r
IN EFI_ABSOLUTE_POINTER_PROTOCOL *This,\r
OUT EFI_ABSOLUTE_POINTER_STATE *State\r
-);\r
-\r
+ );\r
\r
///\r
/// The EFI_ABSOLUTE_POINTER_PROTOCOL provides a set of services\r
/// device. The service also provides certain data items describing the device.\r
///\r
struct _EFI_ABSOLUTE_POINTER_PROTOCOL {\r
- EFI_ABSOLUTE_POINTER_RESET Reset;\r
- EFI_ABSOLUTE_POINTER_GET_STATE GetState;\r
+ EFI_ABSOLUTE_POINTER_RESET Reset;\r
+ EFI_ABSOLUTE_POINTER_GET_STATE GetState;\r
///\r
/// Event to use with WaitForEvent() to wait for input from the pointer device.\r
///\r
- EFI_EVENT WaitForInput;\r
+ EFI_EVENT WaitForInput;\r
///\r
/// Pointer to EFI_ABSOLUTE_POINTER_MODE data.\r
///\r
- EFI_ABSOLUTE_POINTER_MODE *Mode;\r
+ EFI_ABSOLUTE_POINTER_MODE *Mode;\r
};\r
\r
-\r
-extern EFI_GUID gEfiAbsolutePointerProtocolGuid;\r
-\r
+extern EFI_GUID gEfiAbsolutePointerProtocolGuid;\r
\r
#endif\r
-\r
typedef UINT32 EFI_ACPI_TABLE_VERSION;\r
typedef VOID *EFI_ACPI_HANDLE;\r
\r
-#define EFI_ACPI_TABLE_VERSION_NONE (1 << 0)\r
-#define EFI_ACPI_TABLE_VERSION_1_0B (1 << 1)\r
-#define EFI_ACPI_TABLE_VERSION_2_0 (1 << 2)\r
-#define EFI_ACPI_TABLE_VERSION_3_0 (1 << 3)\r
-#define EFI_ACPI_TABLE_VERSION_4_0 (1 << 4)\r
-#define EFI_ACPI_TABLE_VERSION_5_0 (1 << 5)\r
+#define EFI_ACPI_TABLE_VERSION_NONE (1 << 0)\r
+#define EFI_ACPI_TABLE_VERSION_1_0B (1 << 1)\r
+#define EFI_ACPI_TABLE_VERSION_2_0 (1 << 2)\r
+#define EFI_ACPI_TABLE_VERSION_3_0 (1 << 3)\r
+#define EFI_ACPI_TABLE_VERSION_4_0 (1 << 4)\r
+#define EFI_ACPI_TABLE_VERSION_5_0 (1 << 5)\r
\r
typedef UINT32 EFI_ACPI_DATA_TYPE;\r
#define EFI_ACPI_DATA_TYPE_NONE 0\r
IN EFI_ACPI_SDT_HEADER *Table, ///< A pointer to the ACPI table header.\r
IN EFI_ACPI_TABLE_VERSION Version, ///< The ACPI table's version.\r
IN UINTN TableKey ///< The table key for this ACPI table.\r
-);\r
+ );\r
\r
/**\r
Returns a requested ACPI table.\r
OUT EFI_ACPI_SDT_HEADER **Table,\r
OUT EFI_ACPI_TABLE_VERSION *Version,\r
OUT UINTN *TableKey\r
-);\r
+ );\r
\r
/**\r
Register or unregister a callback when an ACPI table is installed.\r
(EFIAPI *EFI_ACPI_REGISTER_NOTIFY)(\r
IN BOOLEAN Register,\r
IN EFI_ACPI_NOTIFICATION_FN Notification\r
-);\r
+ );\r
\r
/**\r
Create a handle from an ACPI opcode\r
(EFIAPI *EFI_ACPI_OPEN)(\r
IN VOID *Buffer,\r
OUT EFI_ACPI_HANDLE *Handle\r
-);\r
+ );\r
\r
/**\r
Create a handle for the first ACPI opcode in an ACPI system description table.\r
(EFIAPI *EFI_ACPI_OPEN_SDT)(\r
IN UINTN TableKey,\r
OUT EFI_ACPI_HANDLE *Handle\r
-);\r
+ );\r
\r
/**\r
Close an ACPI handle.\r
EFI_STATUS\r
(EFIAPI *EFI_ACPI_CLOSE)(\r
IN EFI_ACPI_HANDLE Handle\r
-);\r
+ );\r
\r
/**\r
Return the child ACPI objects.\r
(EFIAPI *EFI_ACPI_GET_CHILD)(\r
IN EFI_ACPI_HANDLE ParentHandle,\r
IN OUT EFI_ACPI_HANDLE *Handle\r
-);\r
+ );\r
\r
/**\r
Retrieve information about an ACPI object.\r
OUT EFI_ACPI_DATA_TYPE *DataType,\r
OUT CONST VOID **Data,\r
OUT UINTN *DataSize\r
-);\r
+ );\r
\r
/**\r
Change information about an ACPI object.\r
IN UINTN Index,\r
IN CONST VOID *Data,\r
IN UINTN DataSize\r
-);\r
+ );\r
\r
/**\r
Returns the handle of the ACPI object representing the specified ACPI path\r
IN EFI_ACPI_HANDLE HandleIn,\r
IN VOID *AcpiPath,\r
OUT EFI_ACPI_HANDLE *HandleOut\r
-);\r
+ );\r
\r
typedef struct _EFI_ACPI_SDT_PROTOCOL {\r
///\r
/// A bit map containing all the ACPI versions supported by this protocol.\r
///\r
- EFI_ACPI_TABLE_VERSION AcpiVersion;\r
- EFI_ACPI_GET_ACPI_TABLE2 GetAcpiTable;\r
- EFI_ACPI_REGISTER_NOTIFY RegisterNotify;\r
- EFI_ACPI_OPEN Open;\r
- EFI_ACPI_OPEN_SDT OpenSdt;\r
- EFI_ACPI_CLOSE Close;\r
- EFI_ACPI_GET_CHILD GetChild;\r
- EFI_ACPI_GET_OPTION GetOption;\r
- EFI_ACPI_SET_OPTION SetOption;\r
- EFI_ACPI_FIND_PATH FindPath;\r
+ EFI_ACPI_TABLE_VERSION AcpiVersion;\r
+ EFI_ACPI_GET_ACPI_TABLE2 GetAcpiTable;\r
+ EFI_ACPI_REGISTER_NOTIFY RegisterNotify;\r
+ EFI_ACPI_OPEN Open;\r
+ EFI_ACPI_OPEN_SDT OpenSdt;\r
+ EFI_ACPI_CLOSE Close;\r
+ EFI_ACPI_GET_CHILD GetChild;\r
+ EFI_ACPI_GET_OPTION GetOption;\r
+ EFI_ACPI_SET_OPTION SetOption;\r
+ EFI_ACPI_FIND_PATH FindPath;\r
} EFI_ACPI_SDT_PROTOCOL;\r
\r
-extern EFI_GUID gEfiAcpiSdtProtocolGuid;\r
+extern EFI_GUID gEfiAcpiSdtProtocolGuid;\r
\r
#endif // __ACPI_SYSTEM_DESCRIPTION_TABLE_H___\r
#define EFI_ACPI_TABLE_PROTOCOL_GUID \\r
{ 0xffe06bdd, 0x6107, 0x46a6, { 0x7b, 0xb2, 0x5a, 0x9c, 0x7e, 0xc5, 0x27, 0x5c }}\r
\r
-\r
typedef struct _EFI_ACPI_TABLE_PROTOCOL EFI_ACPI_TABLE_PROTOCOL;\r
\r
/**\r
IN VOID *AcpiTableBuffer,\r
IN UINTN AcpiTableBufferSize,\r
OUT UINTN *TableKey\r
-);\r
-\r
+ );\r
\r
/**\r
\r
(EFIAPI *EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE)(\r
IN EFI_ACPI_TABLE_PROTOCOL *This,\r
IN UINTN TableKey\r
-);\r
+ );\r
\r
///\r
/// The EFI_ACPI_TABLE_PROTOCOL provides the ability for a component\r
/// to install and uninstall ACPI tables from a platform.\r
///\r
struct _EFI_ACPI_TABLE_PROTOCOL {\r
- EFI_ACPI_TABLE_INSTALL_ACPI_TABLE InstallAcpiTable;\r
- EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE UninstallAcpiTable;\r
+ EFI_ACPI_TABLE_INSTALL_ACPI_TABLE InstallAcpiTable;\r
+ EFI_ACPI_TABLE_UNINSTALL_ACPI_TABLE UninstallAcpiTable;\r
};\r
\r
-extern EFI_GUID gEfiAcpiTableProtocolGuid;\r
+extern EFI_GUID gEfiAcpiTableProtocolGuid;\r
\r
#endif\r
-\r
#ifndef __EFI_ADAPTER_INFORMATION_PROTOCOL_H__\r
#define __EFI_ADAPTER_INFORMATION_PROTOCOL_H__\r
\r
-\r
#define EFI_ADAPTER_INFORMATION_PROTOCOL_GUID \\r
{ \\r
0xE5DD1403, 0xD622, 0xC24E, {0x84, 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 } \\r
0x8484472f, 0x71ec, 0x411a, { 0xb3, 0x9c, 0x62, 0xcd, 0x94, 0xd9, 0x91, 0x6e } \\r
}\r
\r
-\r
typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL EFI_ADAPTER_INFORMATION_PROTOCOL;\r
\r
///\r
/// There was media attached to the network adapter, but it was removed and reattached. EFI_NO_MEDIA: There is\r
/// not any media attached to the network.\r
///\r
- EFI_STATUS MediaState;\r
+ EFI_STATUS MediaState;\r
} EFI_ADAPTER_INFO_MEDIA_STATE;\r
\r
///\r
/// 2: Ethernet Wireless Network Adapter\r
/// 3~255: Reserved\r
///\r
- UINT8 MediaType;\r
+ UINT8 MediaType;\r
} EFI_ADAPTER_INFO_MEDIA_TYPE;\r
\r
///\r
///\r
/// TRUE if the adapter supports booting from iSCSI IPv4 targets.\r
///\r
- BOOLEAN iScsiIpv4BootCapablity;\r
+ BOOLEAN iScsiIpv4BootCapablity;\r
///\r
/// TRUE if the adapter supports booting from iSCSI IPv6 targets.\r
///\r
- BOOLEAN iScsiIpv6BootCapablity;\r
+ BOOLEAN iScsiIpv6BootCapablity;\r
///\r
/// TRUE if the adapter supports booting from FCoE targets.\r
///\r
- BOOLEAN FCoeBootCapablity;\r
+ BOOLEAN FCoeBootCapablity;\r
///\r
/// TRUE if the adapter supports an offload engine (such as TCP\r
/// Offload Engine (TOE)) for its iSCSI or FCoE boot operations.\r
///\r
- BOOLEAN OffloadCapability;\r
+ BOOLEAN OffloadCapability;\r
///\r
/// TRUE if the adapter supports multipath I/O (MPIO) for its iSCSI\r
/// boot operations.\r
///\r
- BOOLEAN iScsiMpioCapability;\r
+ BOOLEAN iScsiMpioCapability;\r
///\r
/// TRUE if the adapter is currently configured to boot from iSCSI\r
/// IPv4 targets.\r
///\r
- BOOLEAN iScsiIpv4Boot;\r
+ BOOLEAN iScsiIpv4Boot;\r
///\r
/// TRUE if the adapter is currently configured to boot from iSCSI\r
/// IPv6 targets.\r
///\r
- BOOLEAN iScsiIpv6Boot;\r
+ BOOLEAN iScsiIpv6Boot;\r
///\r
/// TRUE if the adapter is currently configured to boot from FCoE targets.\r
///\r
- BOOLEAN FCoeBoot;\r
+ BOOLEAN FCoeBoot;\r
} EFI_ADAPTER_INFO_NETWORK_BOOT;\r
\r
///\r
/// Returns the SAN MAC address for the adapter.For adapters that support today's 802.3 ethernet\r
/// networking and Fibre-Channel Over Ethernet (FCOE), this conveys the FCOE SAN MAC address from the adapter.\r
///\r
- EFI_MAC_ADDRESS SanMacAddress;\r
+ EFI_MAC_ADDRESS SanMacAddress;\r
} EFI_ADAPTER_INFO_SAN_MAC_ADDRESS;\r
\r
///\r
///\r
/// Returns capability of UNDI to support IPv6 traffic.\r
///\r
- BOOLEAN Ipv6Support;\r
+ BOOLEAN Ipv6Support;\r
} EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT;\r
\r
/**\r
/// - Gets a list of supported information types for this instance of the protocol.\r
///\r
struct _EFI_ADAPTER_INFORMATION_PROTOCOL {\r
- EFI_ADAPTER_INFO_GET_INFO GetInformation;\r
- EFI_ADAPTER_INFO_SET_INFO SetInformation;\r
- EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES GetSupportedTypes;\r
+ EFI_ADAPTER_INFO_GET_INFO GetInformation;\r
+ EFI_ADAPTER_INFO_SET_INFO SetInformation;\r
+ EFI_ADAPTER_INFO_GET_SUPPORTED_TYPES GetSupportedTypes;\r
};\r
\r
-extern EFI_GUID gEfiAdapterInformationProtocolGuid;\r
+extern EFI_GUID gEfiAdapterInformationProtocolGuid;\r
\r
-extern EFI_GUID gEfiAdapterInfoMediaStateGuid;\r
+extern EFI_GUID gEfiAdapterInfoMediaStateGuid;\r
\r
-extern EFI_GUID gEfiAdapterInfoNetworkBootGuid;\r
+extern EFI_GUID gEfiAdapterInfoNetworkBootGuid;\r
\r
-extern EFI_GUID gEfiAdapterInfoSanMacAddressGuid;\r
+extern EFI_GUID gEfiAdapterInfoSanMacAddressGuid;\r
\r
-extern EFI_GUID gEfiAdapterInfoUndiIpv6SupportGuid;\r
+extern EFI_GUID gEfiAdapterInfoUndiIpv6SupportGuid;\r
\r
#endif\r
///\r
/// Length in bytes of this entry.\r
///\r
- UINT32 Size;\r
+ UINT32 Size;\r
\r
///\r
/// Set to TRUE if this entry is a "deny" entry.\r
/// Set to FALSE if this entry is a "normal" entry.\r
///\r
- BOOLEAN DenyFlag;\r
+ BOOLEAN DenyFlag;\r
\r
///\r
/// Set to TRUE if this entry will not time out.\r
/// Set to FALSE if this entry will time out.\r
///\r
- BOOLEAN StaticFlag;\r
+ BOOLEAN StaticFlag;\r
\r
///\r
/// 16-bit ARP hardware identifier number.\r
///\r
- UINT16 HwAddressType;\r
+ UINT16 HwAddressType;\r
\r
///\r
/// 16-bit protocol type number.\r
///\r
- UINT16 SwAddressType;\r
+ UINT16 SwAddressType;\r
\r
///\r
/// The length of the hardware address.\r
///\r
- UINT8 HwAddressLength;\r
+ UINT8 HwAddressLength;\r
\r
///\r
/// The length of the protocol address.\r
///\r
- UINT8 SwAddressLength;\r
+ UINT8 SwAddressLength;\r
} EFI_ARP_FIND_DATA;\r
\r
typedef struct {\r
///\r
/// 16-bit protocol type number in host byte order.\r
///\r
- UINT16 SwAddressType;\r
+ UINT16 SwAddressType;\r
\r
///\r
/// The length in bytes of the station's protocol address to register.\r
///\r
- UINT8 SwAddressLength;\r
+ UINT8 SwAddressLength;\r
\r
///\r
/// The pointer to the first byte of the protocol address to register. For\r
/// StationAddress points to the first byte of this station's IP\r
/// address stored in network byte order.\r
///\r
- VOID *StationAddress;\r
+ VOID *StationAddress;\r
\r
///\r
/// The timeout value in 100-ns units that is associated with each\r
/// new dynamic ARP cache entry. If it is set to zero, the value is\r
/// implementation-specific.\r
///\r
- UINT32 EntryTimeOut;\r
+ UINT32 EntryTimeOut;\r
\r
///\r
/// The number of retries before a MAC address is resolved. If it is\r
/// set to zero, the value is implementation-specific.\r
///\r
- UINT32 RetryCount;\r
+ UINT32 RetryCount;\r
\r
///\r
/// The timeout value in 100-ns units that is used to wait for the ARP\r
/// reply packet or the timeout value between two retries. Set to zero\r
/// to use implementation-specific value.\r
///\r
- UINT32 RetryTimeOut;\r
+ UINT32 RetryTimeOut;\r
} EFI_ARP_CONFIG_DATA;\r
\r
-\r
/**\r
This function is used to assign a station address to the ARP cache for this instance\r
of the ARP driver.\r
IN BOOLEAN Refresh\r
);\r
\r
-\r
/**\r
This function removes specified ARP cache entries.\r
\r
/// network hardware addresses.\r
///\r
struct _EFI_ARP_PROTOCOL {\r
- EFI_ARP_CONFIGURE Configure;\r
- EFI_ARP_ADD Add;\r
- EFI_ARP_FIND Find;\r
- EFI_ARP_DELETE Delete;\r
- EFI_ARP_FLUSH Flush;\r
- EFI_ARP_REQUEST Request;\r
- EFI_ARP_CANCEL Cancel;\r
+ EFI_ARP_CONFIGURE Configure;\r
+ EFI_ARP_ADD Add;\r
+ EFI_ARP_FIND Find;\r
+ EFI_ARP_DELETE Delete;\r
+ EFI_ARP_FLUSH Flush;\r
+ EFI_ARP_REQUEST Request;\r
+ EFI_ARP_CANCEL Cancel;\r
};\r
\r
-\r
-extern EFI_GUID gEfiArpServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiArpProtocolGuid;\r
+extern EFI_GUID gEfiArpServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiArpProtocolGuid;\r
\r
#endif\r
typedef struct _EFI_ATA_PASS_THRU_PROTOCOL EFI_ATA_PASS_THRU_PROTOCOL;\r
\r
typedef struct {\r
- UINT32 Attributes;\r
- UINT32 IoAlign;\r
+ UINT32 Attributes;\r
+ UINT32 IoAlign;\r
} EFI_ATA_PASS_THRU_MODE;\r
\r
///\r
/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for physical\r
/// devices on the ATA controller.\r
///\r
-#define EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
///\r
/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface is for logical\r
/// devices on the ATA controller.\r
///\r
-#define EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
///\r
/// If this bit is set, then the EFI_ATA_PASS_THRU_PROTOCOL interface supports non blocking\r
/// I/O. Every EFI_ATA_PASS_THRU_PROTOCOL must support blocking I/O. The support of non-blocking\r
/// I/O is optional.\r
///\r
-#define EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
+#define EFI_ATA_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
\r
typedef struct _EFI_ATA_COMMAND_BLOCK {\r
- UINT8 Reserved1[2];\r
- UINT8 AtaCommand;\r
- UINT8 AtaFeatures;\r
- UINT8 AtaSectorNumber;\r
- UINT8 AtaCylinderLow;\r
- UINT8 AtaCylinderHigh;\r
- UINT8 AtaDeviceHead;\r
- UINT8 AtaSectorNumberExp;\r
- UINT8 AtaCylinderLowExp;\r
- UINT8 AtaCylinderHighExp;\r
- UINT8 AtaFeaturesExp;\r
- UINT8 AtaSectorCount;\r
- UINT8 AtaSectorCountExp;\r
- UINT8 Reserved2[6];\r
+ UINT8 Reserved1[2];\r
+ UINT8 AtaCommand;\r
+ UINT8 AtaFeatures;\r
+ UINT8 AtaSectorNumber;\r
+ UINT8 AtaCylinderLow;\r
+ UINT8 AtaCylinderHigh;\r
+ UINT8 AtaDeviceHead;\r
+ UINT8 AtaSectorNumberExp;\r
+ UINT8 AtaCylinderLowExp;\r
+ UINT8 AtaCylinderHighExp;\r
+ UINT8 AtaFeaturesExp;\r
+ UINT8 AtaSectorCount;\r
+ UINT8 AtaSectorCountExp;\r
+ UINT8 Reserved2[6];\r
} EFI_ATA_COMMAND_BLOCK;\r
\r
typedef struct _EFI_ATA_STATUS_BLOCK {\r
- UINT8 Reserved1[2];\r
- UINT8 AtaStatus;\r
- UINT8 AtaError;\r
- UINT8 AtaSectorNumber;\r
- UINT8 AtaCylinderLow;\r
- UINT8 AtaCylinderHigh;\r
- UINT8 AtaDeviceHead;\r
- UINT8 AtaSectorNumberExp;\r
- UINT8 AtaCylinderLowExp;\r
- UINT8 AtaCylinderHighExp;\r
- UINT8 Reserved2;\r
- UINT8 AtaSectorCount;\r
- UINT8 AtaSectorCountExp;\r
- UINT8 Reserved3[6];\r
+ UINT8 Reserved1[2];\r
+ UINT8 AtaStatus;\r
+ UINT8 AtaError;\r
+ UINT8 AtaSectorNumber;\r
+ UINT8 AtaCylinderLow;\r
+ UINT8 AtaCylinderHigh;\r
+ UINT8 AtaDeviceHead;\r
+ UINT8 AtaSectorNumberExp;\r
+ UINT8 AtaCylinderLowExp;\r
+ UINT8 AtaCylinderHighExp;\r
+ UINT8 Reserved2;\r
+ UINT8 AtaSectorCount;\r
+ UINT8 AtaSectorCountExp;\r
+ UINT8 Reserved3[6];\r
} EFI_ATA_STATUS_BLOCK;\r
\r
typedef UINT8 EFI_ATA_PASS_THRU_CMD_PROTOCOL;\r
\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET 0x00\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET 0x01\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA 0x02\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN 0x04\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT 0x05\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_DMA 0x06\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED 0x07\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC 0x08\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET 0x09\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN 0x0A\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT 0x0B\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_FPDMA 0x0C\r
-#define EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE 0xFF\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_HARDWARE_RESET 0x00\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_SOFTWARE_RESET 0x01\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_ATA_NON_DATA 0x02\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_IN 0x04\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_PIO_DATA_OUT 0x05\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_DMA 0x06\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_DMA_QUEUED 0x07\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_DIAGNOSTIC 0x08\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_DEVICE_RESET 0x09\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_IN 0x0A\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_UDMA_DATA_OUT 0x0B\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_FPDMA 0x0C\r
+#define EFI_ATA_PASS_THRU_PROTOCOL_RETURN_RESPONSE 0xFF\r
\r
typedef UINT8 EFI_ATA_PASS_THRU_LENGTH;\r
\r
-#define EFI_ATA_PASS_THRU_LENGTH_BYTES 0x80\r
+#define EFI_ATA_PASS_THRU_LENGTH_BYTES 0x80\r
\r
+#define EFI_ATA_PASS_THRU_LENGTH_MASK 0x70\r
+#define EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER 0x00\r
+#define EFI_ATA_PASS_THRU_LENGTH_FEATURES 0x10\r
+#define EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT 0x20\r
+#define EFI_ATA_PASS_THRU_LENGTH_TPSIU 0x30\r
\r
-#define EFI_ATA_PASS_THRU_LENGTH_MASK 0x70\r
-#define EFI_ATA_PASS_THRU_LENGTH_NO_DATA_TRANSFER 0x00\r
-#define EFI_ATA_PASS_THRU_LENGTH_FEATURES 0x10\r
-#define EFI_ATA_PASS_THRU_LENGTH_SECTOR_COUNT 0x20\r
-#define EFI_ATA_PASS_THRU_LENGTH_TPSIU 0x30\r
-\r
-#define EFI_ATA_PASS_THRU_LENGTH_COUNT 0x0F\r
+#define EFI_ATA_PASS_THRU_LENGTH_COUNT 0x0F\r
\r
typedef struct {\r
///\r
/// command. It must be aligned to the boundary specified in the IoAlign field\r
/// in the EFI_ATA_PASS_THRU_MODE structure.\r
///\r
- EFI_ATA_STATUS_BLOCK *Asb;\r
+ EFI_ATA_STATUS_BLOCK *Asb;\r
///\r
/// A pointer to buffer that contains the Command Data Block to send to the ATA\r
/// device specified by Port and PortMultiplierPort.\r
///\r
- EFI_ATA_COMMAND_BLOCK *Acb;\r
+ EFI_ATA_COMMAND_BLOCK *Acb;\r
///\r
/// The timeout, in 100 ns units, to use for the execution of this ATA command.\r
/// A Timeout value of 0 means that this function will wait indefinitely for the\r
/// will return EFI_TIMEOUT if the time required to execute the ATA command is\r
/// greater than Timeout.\r
///\r
- UINT64 Timeout;\r
+ UINT64 Timeout;\r
///\r
/// A pointer to the data buffer to transfer between the ATA controller and the\r
/// ATA device for read and bidirectional commands. For all write and non data\r
/// If this field is not NULL, then it must be aligned on the boundary specified\r
/// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure.\r
///\r
- VOID *InDataBuffer;\r
+ VOID *InDataBuffer;\r
///\r
/// A pointer to the data buffer to transfer between the ATA controller and the\r
/// ATA device for write or bidirectional commands. For all read and non data\r
/// If this field is not NULL, then it must be aligned on the boundary specified\r
/// by the IoAlign field in the EFI_ATA_PASS_THRU_MODE structure.\r
///\r
- VOID *OutDataBuffer;\r
+ VOID *OutDataBuffer;\r
///\r
/// On input, the size, in bytes, of InDataBuffer. On output, the number of bytes\r
/// transferred between the ATA controller and the ATA device. If InTransferLength\r
/// InTransferLength will be updated to contain the number of bytes that the ATA\r
/// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.\r
///\r
- UINT32 InTransferLength;\r
+ UINT32 InTransferLength;\r
///\r
/// On Input, the size, in bytes of OutDataBuffer. On Output, the Number of bytes\r
/// transferred between ATA Controller and the ATA device. If OutTransferLength is\r
/// OutTransferLength will be updated to contain the number of bytes that the ATA\r
/// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.\r
///\r
- UINT32 OutTransferLength;\r
+ UINT32 OutTransferLength;\r
///\r
/// Specifies the protocol used when the ATA device executes the command.\r
///\r
- EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol;\r
+ EFI_ATA_PASS_THRU_CMD_PROTOCOL Protocol;\r
///\r
/// Specifies the way in which the ATA command length is encoded.\r
///\r
- EFI_ATA_PASS_THRU_LENGTH Length;\r
+ EFI_ATA_PASS_THRU_LENGTH Length;\r
} EFI_ATA_PASS_THRU_COMMAND_PACKET;\r
\r
-\r
/**\r
Sends an ATA command to an ATA device that is attached to the ATA controller. This function\r
supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,\r
);\r
\r
struct _EFI_ATA_PASS_THRU_PROTOCOL {\r
- EFI_ATA_PASS_THRU_MODE *Mode;\r
- EFI_ATA_PASS_THRU_PASSTHRU PassThru;\r
- EFI_ATA_PASS_THRU_GET_NEXT_PORT GetNextPort;\r
- EFI_ATA_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;\r
- EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
- EFI_ATA_PASS_THRU_GET_DEVICE GetDevice;\r
- EFI_ATA_PASS_THRU_RESET_PORT ResetPort;\r
- EFI_ATA_PASS_THRU_RESET_DEVICE ResetDevice;\r
+ EFI_ATA_PASS_THRU_MODE *Mode;\r
+ EFI_ATA_PASS_THRU_PASSTHRU PassThru;\r
+ EFI_ATA_PASS_THRU_GET_NEXT_PORT GetNextPort;\r
+ EFI_ATA_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;\r
+ EFI_ATA_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
+ EFI_ATA_PASS_THRU_GET_DEVICE GetDevice;\r
+ EFI_ATA_PASS_THRU_RESET_PORT ResetPort;\r
+ EFI_ATA_PASS_THRU_RESET_DEVICE ResetDevice;\r
};\r
\r
-extern EFI_GUID gEfiAtaPassThruProtocolGuid;\r
+extern EFI_GUID gEfiAtaPassThruProtocolGuid;\r
\r
#endif\r
///\r
/// Authentication Type GUID.\r
///\r
- EFI_GUID Guid;\r
+ EFI_GUID Guid;\r
\r
///\r
/// Length of this structure in bytes.\r
///\r
- UINT16 Length;\r
+ UINT16 Length;\r
} AUTH_NODE_HEADER;\r
\r
typedef struct {\r
- AUTH_NODE_HEADER Header;\r
+ AUTH_NODE_HEADER Header;\r
\r
///\r
/// RADIUS Server IPv4 or IPv6 Address.\r
///\r
- UINT8 RadiusIpAddr[16]; ///< IPv4 or IPv6 address.\r
+ UINT8 RadiusIpAddr[16]; ///< IPv4 or IPv6 address.\r
\r
///\r
/// Reserved for future use.\r
///\r
- UINT16 Reserved;\r
+ UINT16 Reserved;\r
\r
///\r
/// Network Access Server IPv4 or IPv6 Address (OPTIONAL).\r
///\r
- UINT8 NasIpAddr[16]; ///< IPv4 or IPv6 address.\r
+ UINT8 NasIpAddr[16]; ///< IPv4 or IPv6 address.\r
\r
///\r
/// Network Access Server Secret Length in bytes (OPTIONAL).\r
///\r
- UINT16 NasSecretLength;\r
+ UINT16 NasSecretLength;\r
\r
///\r
/// Network Access Server Secret (OPTIONAL).\r
///\r
- UINT8 NasSecret[1];\r
+ UINT8 NasSecret[1];\r
\r
///\r
/// CHAP Initiator Secret Length in bytes on offset NasSecret + NasSecretLength.\r
} CHAP_RADIUS_AUTH_NODE;\r
\r
typedef struct {\r
- AUTH_NODE_HEADER Header;\r
+ AUTH_NODE_HEADER Header;\r
\r
///\r
/// Reserved for future use.\r
///\r
- UINT16 Reserved;\r
+ UINT16 Reserved;\r
\r
///\r
/// User Secret Length in bytes.\r
///\r
- UINT16 UserSecretLength;\r
+ UINT16 UserSecretLength;\r
\r
///\r
/// User Secret.\r
///\r
- UINT8 UserSecret[1];\r
+ UINT8 UserSecret[1];\r
\r
///\r
/// User Name Length in bytes on offset UserSecret + UserSecretLength.\r
/// information associated with the physical or logical device.\r
///\r
struct _EFI_AUTHENTICATION_INFO_PROTOCOL {\r
- EFI_AUTHENTICATION_INFO_PROTOCOL_GET Get;\r
- EFI_AUTHENTICATION_INFO_PROTOCOL_SET Set;\r
+ EFI_AUTHENTICATION_INFO_PROTOCOL_GET Get;\r
+ EFI_AUTHENTICATION_INFO_PROTOCOL_SET Set;\r
};\r
\r
-extern EFI_GUID gEfiAuthenticationInfoProtocolGuid;\r
-extern EFI_GUID gEfiAuthenticationChapRadiusGuid;\r
-extern EFI_GUID gEfiAuthenticationChapLocalGuid;\r
+extern EFI_GUID gEfiAuthenticationInfoProtocolGuid;\r
+extern EFI_GUID gEfiAuthenticationChapRadiusGuid;\r
+extern EFI_GUID gEfiAuthenticationChapLocalGuid;\r
\r
#endif\r
///\r
/// Declare forward reference for the BDS Architectural Protocol\r
///\r
-typedef struct _EFI_BDS_ARCH_PROTOCOL EFI_BDS_ARCH_PROTOCOL;\r
+typedef struct _EFI_BDS_ARCH_PROTOCOL EFI_BDS_ARCH_PROTOCOL;\r
\r
/**\r
This function uses policy data from the platform to determine what operating\r
/// the boot device can be used to load and invoke an OS or a system utility.\r
///\r
struct _EFI_BDS_ARCH_PROTOCOL {\r
- EFI_BDS_ENTRY Entry;\r
+ EFI_BDS_ENTRY Entry;\r
};\r
\r
-extern EFI_GUID gEfiBdsArchProtocolGuid;\r
+extern EFI_GUID gEfiBdsArchProtocolGuid;\r
\r
#endif\r
0xedd35e31, 0x7b9, 0x11d2, { 0x83,0xa3,0x0,0xa0,0xc9,0x1f,0xad,0xcf } \\r
}\r
\r
-\r
-\r
-typedef struct _EFI_BIS_PROTOCOL EFI_BIS_PROTOCOL;\r
-\r
+typedef struct _EFI_BIS_PROTOCOL EFI_BIS_PROTOCOL;\r
\r
//\r
// Basic types\r
//\r
-typedef VOID *BIS_APPLICATION_HANDLE;\r
-typedef UINT16 BIS_ALG_ID;\r
-typedef UINT32 BIS_CERT_ID;\r
+typedef VOID *BIS_APPLICATION_HANDLE;\r
+typedef UINT16 BIS_ALG_ID;\r
+typedef UINT32 BIS_CERT_ID;\r
\r
///\r
/// EFI_BIS_DATA instances obtained from BIS must be freed by calling Free( ).\r
///\r
typedef struct {\r
- UINT32 Length; ///< The length of Data in 8 bit bytes.\r
- UINT8 *Data; ///< 32 Bit Flat Address of data.\r
+ UINT32 Length; ///< The length of Data in 8 bit bytes.\r
+ UINT8 *Data; ///< 32 Bit Flat Address of data.\r
} EFI_BIS_DATA;\r
\r
///\r
/// EFI_BIS_VERSION type.\r
///\r
typedef struct {\r
- UINT32 Major; ///< The major BIS version number.\r
- UINT32 Minor; ///< A minor BIS version number.\r
+ UINT32 Major; ///< The major BIS version number.\r
+ UINT32 Minor; ///< A minor BIS version number.\r
} EFI_BIS_VERSION;\r
\r
//\r
// and to interpret results of Initialize.\r
// ----------------------------------------------------//\r
//\r
-#define BIS_CURRENT_VERSION_MAJOR BIS_VERSION_1\r
-#define BIS_VERSION_1 1\r
+#define BIS_CURRENT_VERSION_MAJOR BIS_VERSION_1\r
+#define BIS_VERSION_1 1\r
\r
///\r
/// EFI_BIS_SIGNATURE_INFO type.\r
///\r
typedef struct {\r
- BIS_CERT_ID CertificateID; ///< Truncated hash of platform Boot Object\r
- BIS_ALG_ID AlgorithmID; ///< A signature algorithm number.\r
- UINT16 KeyLength; ///< The length of alg. keys in bits.\r
+ BIS_CERT_ID CertificateID; ///< Truncated hash of platform Boot Object\r
+ BIS_ALG_ID AlgorithmID; ///< A signature algorithm number.\r
+ UINT16 KeyLength; ///< The length of alg. keys in bits.\r
} EFI_BIS_SIGNATURE_INFO;\r
\r
///\r
/// The exact numeric values come from the\r
/// "Common Data Security Architecture (CDSA) Specification".\r
///\r
-#define BIS_ALG_DSA (41) // CSSM_ALGID_DSA\r
-#define BIS_ALG_RSA_MD5 (42) // CSSM_ALGID_MD5_WITH_RSA\r
+#define BIS_ALG_DSA (41) // CSSM_ALGID_DSA\r
+#define BIS_ALG_RSA_MD5 (42) // CSSM_ALGID_MD5_WITH_RSA\r
///\r
/// values for EFI_BIS_SIGNATURE_INFO.CertificateId.\r
///\r
-#define BIS_CERT_ID_DSA BIS_ALG_DSA // CSSM_ALGID_DSA\r
-#define BIS_CERT_ID_RSA_MD5 BIS_ALG_RSA_MD5 // CSSM_ALGID_MD5_WITH_RSA\r
+#define BIS_CERT_ID_DSA BIS_ALG_DSA // CSSM_ALGID_DSA\r
+#define BIS_CERT_ID_RSA_MD5 BIS_ALG_RSA_MD5 // CSSM_ALGID_MD5_WITH_RSA\r
///\r
/// The mask value that gets applied to the truncated hash of a\r
/// platform Boot Object Authorization Certificate to create the certificateID.\r
/// elements are contained in a EFI_BIS_DATA struct pointed to\r
/// by the provided EFI_BIS_DATA*.\r
///\r
-#define BIS_GET_SIGINFO_COUNT(BisDataPtr) ((BisDataPtr)->Length / sizeof (EFI_BIS_SIGNATURE_INFO))\r
+#define BIS_GET_SIGINFO_COUNT(BisDataPtr) ((BisDataPtr)->Length / sizeof (EFI_BIS_SIGNATURE_INFO))\r
\r
///\r
/// BIS_GET_SIGINFO_ARRAY - produces a EFI_BIS_SIGNATURE_INFO*\r
/// from a given EFI_BIS_DATA*.\r
///\r
-#define BIS_GET_SIGINFO_ARRAY(BisDataPtr) ((EFI_BIS_SIGNATURE_INFO *) (BisDataPtr)->Data)\r
+#define BIS_GET_SIGINFO_ARRAY(BisDataPtr) ((EFI_BIS_SIGNATURE_INFO *) (BisDataPtr)->Data)\r
\r
///\r
/// Support an old name for backward compatibility.\r
/// certificate for the purpose of an integrity and authorization check.\r
///\r
struct _EFI_BIS_PROTOCOL {\r
- EFI_BIS_INITIALIZE Initialize;\r
- EFI_BIS_SHUTDOWN Shutdown;\r
- EFI_BIS_FREE Free;\r
- EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE GetBootObjectAuthorizationCertificate;\r
- EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG GetBootObjectAuthorizationCheckFlag;\r
- EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN GetBootObjectAuthorizationUpdateToken;\r
- EFI_BIS_GET_SIGNATURE_INFO GetSignatureInfo;\r
- EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION UpdateBootObjectAuthorization;\r
- EFI_BIS_VERIFY_BOOT_OBJECT VerifyBootObject;\r
- EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL VerifyObjectWithCredential;\r
+ EFI_BIS_INITIALIZE Initialize;\r
+ EFI_BIS_SHUTDOWN Shutdown;\r
+ EFI_BIS_FREE Free;\r
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE GetBootObjectAuthorizationCertificate;\r
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG GetBootObjectAuthorizationCheckFlag;\r
+ EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN GetBootObjectAuthorizationUpdateToken;\r
+ EFI_BIS_GET_SIGNATURE_INFO GetSignatureInfo;\r
+ EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION UpdateBootObjectAuthorization;\r
+ EFI_BIS_VERIFY_BOOT_OBJECT VerifyBootObject;\r
+ EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL VerifyObjectWithCredential;\r
};\r
\r
-extern EFI_GUID gEfiBisProtocolGuid;\r
-extern EFI_GUID gBootObjectAuthorizationParmsetGuid;\r
+extern EFI_GUID gEfiBisProtocolGuid;\r
+extern EFI_GUID gBootObjectAuthorizationParmsetGuid;\r
\r
#endif\r
0x964e5b21, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \\r
}\r
\r
-typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL;\r
+typedef struct _EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL;\r
\r
///\r
/// Protocol GUID name defined in EFI1.1.\r
///\r
-#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID\r
+#define BLOCK_IO_PROTOCOL EFI_BLOCK_IO_PROTOCOL_GUID\r
\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO;\r
+typedef EFI_BLOCK_IO_PROTOCOL EFI_BLOCK_IO;\r
\r
/**\r
Reset the Block Device.\r
///\r
/// The curent media Id. If the media changes, this value is changed.\r
///\r
- UINT32 MediaId;\r
+ UINT32 MediaId;\r
\r
///\r
/// TRUE if the media is removable; otherwise, FALSE.\r
///\r
- BOOLEAN RemovableMedia;\r
+ BOOLEAN RemovableMedia;\r
\r
///\r
/// TRUE if there is a media currently present in the device;\r
/// othersise, FALSE. THis field shows the media present status\r
/// as of the most recent ReadBlocks() or WriteBlocks() call.\r
///\r
- BOOLEAN MediaPresent;\r
+ BOOLEAN MediaPresent;\r
\r
///\r
/// TRUE if LBA 0 is the first block of a partition; otherwise\r
/// FALSE. For media with only one partition this would be TRUE.\r
///\r
- BOOLEAN LogicalPartition;\r
+ BOOLEAN LogicalPartition;\r
\r
///\r
/// TRUE if the media is marked read-only otherwise, FALSE.\r
/// This field shows the read-only status as of the most recent WriteBlocks () call.\r
///\r
- BOOLEAN ReadOnly;\r
+ BOOLEAN ReadOnly;\r
\r
///\r
/// TRUE if the WriteBlock () function caches write data.\r
///\r
- BOOLEAN WriteCaching;\r
+ BOOLEAN WriteCaching;\r
\r
///\r
/// The intrinsic block size of the device. If the media changes, then\r
/// this field is updated.\r
///\r
- UINT32 BlockSize;\r
+ UINT32 BlockSize;\r
\r
///\r
/// Supplies the alignment requirement for any buffer to read or write block(s).\r
///\r
- UINT32 IoAlign;\r
+ UINT32 IoAlign;\r
\r
///\r
/// The last logical block address on the device.\r
/// If the media changes, then this field is updated.\r
///\r
- EFI_LBA LastBlock;\r
+ EFI_LBA LastBlock;\r
\r
///\r
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to\r
/// a physical block boundary.\r
///\r
- EFI_LBA LowestAlignedLba;\r
+ EFI_LBA LowestAlignedLba;\r
\r
///\r
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
/// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks\r
/// per physical block.\r
///\r
- UINT32 LogicalBlocksPerPhysicalBlock;\r
+ UINT32 LogicalBlocksPerPhysicalBlock;\r
\r
///\r
/// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
/// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length\r
/// granularity as a number of logical blocks.\r
///\r
- UINT32 OptimalTransferLengthGranularity;\r
+ UINT32 OptimalTransferLengthGranularity;\r
} EFI_BLOCK_IO_MEDIA;\r
\r
-#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000\r
-#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001\r
-#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION 0x00010000\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x0002001F\r
\r
///\r
/// Revision defined in EFI1.1.\r
///\r
-#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION\r
+#define EFI_BLOCK_IO_INTERFACE_REVISION EFI_BLOCK_IO_PROTOCOL_REVISION\r
\r
///\r
/// This protocol provides control over block devices.\r
/// revisions must be backwards compatible. If a future version is not\r
/// back wards compatible, it is not the same GUID.\r
///\r
- UINT64 Revision;\r
+ UINT64 Revision;\r
///\r
/// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.\r
///\r
- EFI_BLOCK_IO_MEDIA *Media;\r
-\r
- EFI_BLOCK_RESET Reset;\r
- EFI_BLOCK_READ ReadBlocks;\r
- EFI_BLOCK_WRITE WriteBlocks;\r
- EFI_BLOCK_FLUSH FlushBlocks;\r
+ EFI_BLOCK_IO_MEDIA *Media;\r
\r
+ EFI_BLOCK_RESET Reset;\r
+ EFI_BLOCK_READ ReadBlocks;\r
+ EFI_BLOCK_WRITE WriteBlocks;\r
+ EFI_BLOCK_FLUSH FlushBlocks;\r
};\r
\r
-extern EFI_GUID gEfiBlockIoProtocolGuid;\r
+extern EFI_GUID gEfiBlockIoProtocolGuid;\r
\r
#endif\r
0xa77b2472, 0xe282, 0x4e9f, {0xa2, 0x45, 0xc2, 0xc0, 0xe2, 0x7b, 0xbc, 0xc1} \\r
}\r
\r
-typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL;\r
+typedef struct _EFI_BLOCK_IO2_PROTOCOL EFI_BLOCK_IO2_PROTOCOL;\r
\r
/**\r
The struct of Block IO2 Token.\r
**/\r
typedef struct {\r
-\r
///\r
/// If Event is NULL, then blocking I/O is performed.If Event is not NULL and\r
/// non-blocking I/O is supported, then non-blocking I/O is performed, and\r
/// Event will be signaled when the read request is completed.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
\r
///\r
/// Defines whether or not the signaled event encountered an error.\r
///\r
- EFI_STATUS TransactionStatus;\r
+ EFI_STATUS TransactionStatus;\r
} EFI_BLOCK_IO2_TOKEN;\r
\r
-\r
/**\r
Reset the block device hardware.\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_RESET_EX) (\r
+(EFIAPI *EFI_BLOCK_RESET_EX)(\r
IN EFI_BLOCK_IO2_PROTOCOL *This,\r
IN BOOLEAN ExtendedVerification\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_READ_EX) (\r
+(EFIAPI *EFI_BLOCK_READ_EX)(\r
IN EFI_BLOCK_IO2_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN EFI_LBA LBA,\r
IN OUT EFI_BLOCK_IO2_TOKEN *Token,\r
IN UINTN BufferSize,\r
- OUT VOID *Buffer\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_WRITE_EX) (\r
+(EFIAPI *EFI_BLOCK_WRITE_EX)(\r
IN EFI_BLOCK_IO2_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN EFI_LBA LBA,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_FLUSH_EX) (\r
+(EFIAPI *EFI_BLOCK_FLUSH_EX)(\r
IN EFI_BLOCK_IO2_PROTOCOL *This,\r
IN OUT EFI_BLOCK_IO2_TOKEN *Token\r
);\r
/// A pointer to the EFI_BLOCK_IO_MEDIA data for this device.\r
/// Type EFI_BLOCK_IO_MEDIA is defined in BlockIo.h.\r
///\r
- EFI_BLOCK_IO_MEDIA *Media;\r
+ EFI_BLOCK_IO_MEDIA *Media;\r
\r
- EFI_BLOCK_RESET_EX Reset;\r
- EFI_BLOCK_READ_EX ReadBlocksEx;\r
- EFI_BLOCK_WRITE_EX WriteBlocksEx;\r
- EFI_BLOCK_FLUSH_EX FlushBlocksEx;\r
+ EFI_BLOCK_RESET_EX Reset;\r
+ EFI_BLOCK_READ_EX ReadBlocksEx;\r
+ EFI_BLOCK_WRITE_EX WriteBlocksEx;\r
+ EFI_BLOCK_FLUSH_EX FlushBlocksEx;\r
};\r
\r
-extern EFI_GUID gEfiBlockIo2ProtocolGuid;\r
+extern EFI_GUID gEfiBlockIo2ProtocolGuid;\r
\r
#endif\r
-\r
0xa00490ba, 0x3f1a, 0x4b4c, {0xab, 0x90, 0x4f, 0xa9, 0x97, 0x26, 0xa1, 0xe8} \\r
}\r
\r
-typedef struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL EFI_BLOCK_IO_CRYPTO_PROTOCOL;\r
+typedef struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL EFI_BLOCK_IO_CRYPTO_PROTOCOL;\r
\r
///\r
/// The struct of Block I/O Crypto Token.\r
// Event will be signaled when the read request is completed and data was\r
// decrypted (when Index was specified).\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
//\r
// Defines whether or not the signaled event encountered an error.\r
//\r
- EFI_STATUS TransactionStatus;\r
+ EFI_STATUS TransactionStatus;\r
} EFI_BLOCK_IO_CRYPTO_TOKEN;\r
\r
typedef struct {\r
//\r
// GUID of the algorithm.\r
//\r
- EFI_GUID Algorithm;\r
+ EFI_GUID Algorithm;\r
//\r
// Specifies KeySizein bits used with this Algorithm.\r
//\r
- UINT64 KeySize;\r
+ UINT64 KeySize;\r
//\r
// Specifies bitmask of block sizes supported by this algorithm.\r
// Bit j being set means that 2^j bytes crypto block size is supported.\r
//\r
- UINT64 CryptoBlockSizeBitMask;\r
+ UINT64 CryptoBlockSizeBitMask;\r
} EFI_BLOCK_IO_CRYPTO_CAPABILITY;\r
\r
///\r
/// the Inline Cryptographic Interface.\r
///\r
typedef struct {\r
- UINT64 InputSize;\r
+ UINT64 InputSize;\r
} EFI_BLOCK_IO_CRYPTO_IV_INPUT;\r
\r
#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_XTS \\r
0x2f87ba6a, 0x5c04, 0x4385, {0xa7, 0x80, 0xf3, 0xbf, 0x78, 0xa9, 0x7b, 0xec} \\r
}\r
\r
-extern EFI_GUID gEfiBlockIoCryptoAlgoAesXtsGuid;\r
+extern EFI_GUID gEfiBlockIoCryptoAlgoAesXtsGuid;\r
\r
typedef struct {\r
- EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;\r
- UINT64 CryptoBlockNumber;\r
- UINT64 CryptoBlockByteSize;\r
+ EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;\r
+ UINT64 CryptoBlockNumber;\r
+ UINT64 CryptoBlockByteSize;\r
} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_XTS;\r
\r
#define EFI_BLOCK_IO_CRYPTO_ALGO_GUID_AES_CBC_MICROSOFT_BITLOCKER \\r
0x689e4c62, 0x70bf, 0x4cf3, {0x88, 0xbb, 0x33, 0xb3, 0x18, 0x26, 0x86, 0x70} \\r
}\r
\r
-extern EFI_GUID gEfiBlockIoCryptoAlgoAesCbcMsBitlockerGuid;\r
+extern EFI_GUID gEfiBlockIoCryptoAlgoAesCbcMsBitlockerGuid;\r
\r
typedef struct {\r
- EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;\r
- UINT64 CryptoBlockByteOffset;\r
- UINT64 CryptoBlockByteSize;\r
+ EFI_BLOCK_IO_CRYPTO_IV_INPUT Header;\r
+ UINT64 CryptoBlockByteOffset;\r
+ UINT64 CryptoBlockByteSize;\r
} EFI_BLOCK_IO_CRYPTO_IV_INPUT_AES_CBC_MICROSOFT_BITLOCKER;\r
\r
-#define EFI_BLOCK_IO_CRYPTO_INDEX_ANY 0xFFFFFFFFFFFFFFFF\r
+#define EFI_BLOCK_IO_CRYPTO_INDEX_ANY 0xFFFFFFFFFFFFFFFF\r
\r
typedef struct {\r
//\r
// Is inline cryptographic capability supported on this device.\r
//\r
- BOOLEAN Supported;\r
+ BOOLEAN Supported;\r
//\r
// Maximum number of keys that can be configured at the same time.\r
//\r
- UINT64 KeyCount;\r
+ UINT64 KeyCount;\r
//\r
// Number of supported capabilities.\r
//\r
- UINT64 CapabilityCount;\r
+ UINT64 CapabilityCount;\r
//\r
// Array of supported capabilities.\r
//\r
- EFI_BLOCK_IO_CRYPTO_CAPABILITY Capabilities[1];\r
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capabilities[1];\r
} EFI_BLOCK_IO_CRYPTO_CAPABILITIES;\r
\r
typedef struct {\r
// Configuration table index. A special Index EFI_BLOCK_IO_CRYPTO_INDEX_ANY can be\r
// used to set any available entry in the configuration table.\r
//\r
- UINT64 Index;\r
+ UINT64 Index;\r
//\r
// Identifies the owner of the configuration table entry. Entry can also be used\r
// with the Nil value to clear key from the configuration table index.\r
//\r
- EFI_GUID KeyOwnerGuid;\r
+ EFI_GUID KeyOwnerGuid;\r
//\r
// A supported capability to be used. The CryptoBlockSizeBitMask field of the\r
// structure should have only one bit set from the supported mask.\r
//\r
- EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;\r
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;\r
//\r
// Pointer to the key. The size of the key is defined by the KeySize field of\r
// the capability specified by the Capability parameter.\r
//\r
- VOID *CryptoKey;\r
+ VOID *CryptoKey;\r
} EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY;\r
\r
typedef struct {\r
//\r
// Configuration table index.\r
//\r
- UINT64 Index;\r
+ UINT64 Index;\r
//\r
// Identifies the current owner of the entry.\r
//\r
- EFI_GUID KeyOwnerGuid;\r
+ EFI_GUID KeyOwnerGuid;\r
//\r
// The capability to be used. The CryptoBlockSizeBitMask field of the structure\r
// has only one bit set from the supported mask.\r
//\r
- EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;\r
+ EFI_BLOCK_IO_CRYPTO_CAPABILITY Capability;\r
} EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_RESET) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_RESET)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN BOOLEAN ExtendedVerification\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
- OUT EFI_BLOCK_IO_CRYPTO_CAPABILITIES *Capabilities\r
+ OUT EFI_BLOCK_IO_CRYPTO_CAPABILITIES *Capabilities\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN UINT64 ConfigurationCount,\r
IN EFI_BLOCK_IO_CRYPTO_CONFIGURATION_TABLE_ENTRY *ConfigurationTable,\r
- OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ResultingTable OPTIONAL\r
+ OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ResultingTable OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN UINT64 StartIndex,\r
IN UINT64 ConfigurationCount,\r
IN EFI_GUID *KeyOwnerGuid OPTIONAL,\r
- OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ConfigurationTable\r
-);\r
+ OUT EFI_BLOCK_IO_CRYPTO_RESPONSE_CONFIGURATION_ENTRY *ConfigurationTable\r
+ );\r
\r
/**\r
Reads the requested number of blocks from the device and optionally decrypts\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_READ_EXTENDED) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_READ_EXTENDED)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN EFI_LBA LBA,\r
IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token,\r
IN UINT64 BufferSize,\r
- OUT VOID *Buffer,\r
+ OUT VOID *Buffer,\r
IN UINT64 *Index OPTIONAL,\r
IN VOID *CryptoIvInput OPTIONAL\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN EFI_LBA LBA,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_IO_CRYPTO_FLUSH) (\r
+(EFIAPI *EFI_BLOCK_IO_CRYPTO_FLUSH)(\r
IN EFI_BLOCK_IO_CRYPTO_PROTOCOL *This,\r
IN OUT EFI_BLOCK_IO_CRYPTO_TOKEN *Token\r
);\r
/// drivers and applications to perform block encryption on a storage device, such as UFS.\r
///\r
struct _EFI_BLOCK_IO_CRYPTO_PROTOCOL {\r
- EFI_BLOCK_IO_MEDIA *Media;\r
- EFI_BLOCK_IO_CRYPTO_RESET Reset;\r
- EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES GetCapabilities;\r
- EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION SetConfiguration;\r
- EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION GetConfiguration;\r
- EFI_BLOCK_IO_CRYPTO_READ_EXTENDED ReadExtended;\r
- EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED WriteExtended;\r
- EFI_BLOCK_IO_CRYPTO_FLUSH FlushBlocks;\r
+ EFI_BLOCK_IO_MEDIA *Media;\r
+ EFI_BLOCK_IO_CRYPTO_RESET Reset;\r
+ EFI_BLOCK_IO_CRYPTO_GET_CAPABILITIES GetCapabilities;\r
+ EFI_BLOCK_IO_CRYPTO_SET_CONFIGURATION SetConfiguration;\r
+ EFI_BLOCK_IO_CRYPTO_GET_CONFIGURATION GetConfiguration;\r
+ EFI_BLOCK_IO_CRYPTO_READ_EXTENDED ReadExtended;\r
+ EFI_BLOCK_IO_CRYPTO_WRITE_EXTENDED WriteExtended;\r
+ EFI_BLOCK_IO_CRYPTO_FLUSH FlushBlocks;\r
};\r
\r
-extern EFI_GUID gEfiBlockIoCryptoProtocolGuid;\r
+extern EFI_GUID gEfiBlockIoCryptoProtocolGuid;\r
\r
#endif\r
-\r
// Bluetooth UUID\r
//\r
typedef struct {\r
- UINT8 Length;\r
+ UINT8 Length;\r
union {\r
- UINT16 Uuid16;\r
- UINT32 Uuid32;\r
- UINT8 Uuid128[16];\r
+ UINT16 Uuid16;\r
+ UINT32 Uuid32;\r
+ UINT8 Uuid128[16];\r
} Data;\r
} EFI_BLUETOOTH_UUID;\r
\r
-\r
#define UUID_16BIT_TYPE_LEN 2\r
#define UUID_32BIT_TYPE_LEN 4\r
#define UUID_128BIT_TYPE_LEN 16\r
\r
-#define BLUETOOTH_IS_ATTRIBUTE_OF_TYPE(a,t) ((a)->Type.Length == UUID_16BIT_TYPE_LEN && (a)->Type.Data.Uuid16 == (t))\r
+#define BLUETOOTH_IS_ATTRIBUTE_OF_TYPE(a, t) ((a)->Type.Length == UUID_16BIT_TYPE_LEN && (a)->Type.Data.Uuid16 == (t))\r
\r
//\r
// Bluetooth Attribute Permission\r
//\r
typedef union {\r
struct {\r
- UINT16 Readable : 1;\r
- UINT16 ReadEncryption : 1;\r
- UINT16 ReadAuthentication : 1;\r
- UINT16 ReadAuthorization : 1;\r
- UINT16 ReadKeySize : 5;\r
- UINT16 Reserved1 : 7;\r
- UINT16 Writeable : 1;\r
- UINT16 WriteEncryption : 1;\r
- UINT16 WriteAuthentication : 1;\r
- UINT16 WriteAuthorization : 1;\r
- UINT16 WriteKeySize : 5;\r
- UINT16 Reserved2 : 7;\r
+ UINT16 Readable : 1;\r
+ UINT16 ReadEncryption : 1;\r
+ UINT16 ReadAuthentication : 1;\r
+ UINT16 ReadAuthorization : 1;\r
+ UINT16 ReadKeySize : 5;\r
+ UINT16 Reserved1 : 7;\r
+ UINT16 Writeable : 1;\r
+ UINT16 WriteEncryption : 1;\r
+ UINT16 WriteAuthentication : 1;\r
+ UINT16 WriteAuthorization : 1;\r
+ UINT16 WriteKeySize : 5;\r
+ UINT16 Reserved2 : 7;\r
} Permission;\r
- UINT32 Data32;\r
+ UINT32 Data32;\r
} EFI_BLUETOOTH_ATTRIBUTE_PERMISSION;\r
\r
typedef struct {\r
- EFI_BLUETOOTH_UUID Type;\r
- UINT16 Length;\r
- UINT16 AttributeHandle;\r
- EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission;\r
+ EFI_BLUETOOTH_UUID Type;\r
+ UINT16 Length;\r
+ UINT16 AttributeHandle;\r
+ EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission;\r
} EFI_BLUETOOTH_ATTRIBUTE_HEADER;\r
\r
typedef struct {\r
- EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
- UINT16 EndGroupHandle;\r
- EFI_BLUETOOTH_UUID ServiceUuid;\r
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
+ UINT16 EndGroupHandle;\r
+ EFI_BLUETOOTH_UUID ServiceUuid;\r
} EFI_BLUETOOTH_GATT_PRIMARY_SERVICE_INFO;\r
\r
typedef struct {\r
- EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
- UINT16 StartGroupHandle;\r
- UINT16 EndGroupHandle;\r
- EFI_BLUETOOTH_UUID ServiceUuid;\r
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
+ UINT16 StartGroupHandle;\r
+ UINT16 EndGroupHandle;\r
+ EFI_BLUETOOTH_UUID ServiceUuid;\r
} EFI_BLUETOOTH_GATT_INCLUDE_SERVICE_INFO;\r
\r
typedef struct {\r
- EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
- UINT8 CharacteristicProperties;\r
- UINT16 CharacteristicValueHandle;\r
- EFI_BLUETOOTH_UUID CharacteristicUuid;\r
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
+ UINT8 CharacteristicProperties;\r
+ UINT16 CharacteristicValueHandle;\r
+ EFI_BLUETOOTH_UUID CharacteristicUuid;\r
} EFI_BLUETOOTH_GATT_CHARACTERISTIC_INFO;\r
\r
typedef struct {\r
- EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
- EFI_BLUETOOTH_UUID CharacteristicDescriptorUuid;\r
+ EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;\r
+ EFI_BLUETOOTH_UUID CharacteristicDescriptorUuid;\r
} EFI_BLUETOOTH_GATT_CHARACTERISTIC_DESCRIPTOR_INFO;\r
\r
#pragma pack()\r
\r
typedef struct {\r
- UINT16 AttributeHandle;\r
+ UINT16 AttributeHandle;\r
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION;\r
\r
typedef struct {\r
- UINT16 AttributeHandle;\r
+ UINT16 AttributeHandle;\r
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION;\r
\r
typedef struct {\r
- UINT32 Version;\r
- UINT8 AttributeOpCode;\r
+ UINT32 Version;\r
+ UINT8 AttributeOpCode;\r
union {\r
- EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION Notification;\r
- EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION Indication;\r
+ EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION Notification;\r
+ EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION Indication;\r
} Parameter;\r
} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER;\r
\r
typedef struct {\r
- UINT32 Version;\r
- BLUETOOTH_LE_ADDRESS BD_ADDR;\r
- BLUETOOTH_LE_ADDRESS DirectAddress;\r
- UINT8 RSSI;\r
- UINTN AdvertisementDataSize;\r
- VOID *AdvertisementData;\r
+ UINT32 Version;\r
+ BLUETOOTH_LE_ADDRESS BD_ADDR;\r
+ BLUETOOTH_LE_ADDRESS DirectAddress;\r
+ UINT8 RSSI;\r
+ UINTN AdvertisementDataSize;\r
+ VOID *AdvertisementData;\r
} EFI_BLUETOOTH_LE_DEVICE_INFO;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION) (\r
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION)(\r
IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,\r
IN VOID *Data,\r
IN UINTN DataLength,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST) (\r
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST)(\r
IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,\r
IN VOID *Data,\r
IN UINTN DataLength,\r
);\r
\r
struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL {\r
- EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST SendRequest;\r
- EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION RegisterForServerNotification;\r
- EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO GetServiceInfo;\r
- EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO GetDeviceInfo;\r
+ EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST SendRequest;\r
+ EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION RegisterForServerNotification;\r
+ EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO GetServiceInfo;\r
+ EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO GetDeviceInfo;\r
};\r
\r
-\r
-extern EFI_GUID gEfiBluetoothAttributeProtocolGuid;\r
-extern EFI_GUID gEfiBluetoothAttributeServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothAttributeProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothAttributeServiceBindingProtocolGuid;\r
\r
#endif\r
-\r
\r
typedef struct _EFI_BLUETOOTH_CONFIG_PROTOCOL EFI_BLUETOOTH_CONFIG_PROTOCOL;\r
\r
-typedef UINT32 EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE;\r
-#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_CONNECTED 0x1\r
-#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_PAIRED 0x2\r
+typedef UINT32 EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE;\r
+#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_CONNECTED 0x1\r
+#define EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_PAIRED 0x2\r
\r
///\r
/// EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION\r
///\r
/// 48bit Bluetooth device address.\r
///\r
- BLUETOOTH_ADDRESS BDAddr;\r
+ BLUETOOTH_ADDRESS BDAddr;\r
///\r
/// State of the remote deive\r
///\r
- UINT8 RemoteDeviceState;\r
+ UINT8 RemoteDeviceState;\r
///\r
/// Bluetooth ClassOfDevice. See Bluetooth specification for detail.\r
///\r
- BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;\r
+ BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;\r
///\r
/// Remote device name\r
///\r
- UINT8 RemoteDeviceName[BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE];\r
+ UINT8 RemoteDeviceName[BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE];\r
} EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION;\r
\r
///\r
///\r
EfiBluetoothConfigDataTypeAvailableDeviceList,\r
EfiBluetoothConfigDataTypeRandomAddress, /* Relevant for LE*/\r
- EfiBluetoothConfigDataTypeRSSI, /* Relevant for LE*/\r
+ EfiBluetoothConfigDataTypeRSSI, /* Relevant for LE*/\r
///\r
/// Advertisement report. Data structure is UNIT8[].\r
///\r
EfiBluetoothConfigDataTypeAdvertisementData, /* Relevant for LE*/\r
- EfiBluetoothConfigDataTypeIoCapability, /* Relevant for LE*/\r
- EfiBluetoothConfigDataTypeOOBDataFlag, /* Relevant for LE*/\r
+ EfiBluetoothConfigDataTypeIoCapability, /* Relevant for LE*/\r
+ EfiBluetoothConfigDataTypeOOBDataFlag, /* Relevant for LE*/\r
///\r
/// KeyType of Authentication Requirements flag of local\r
/// device as UINT8, indicating requested security properties.\r
/// See Bluetooth specification 3.H.3.5.1. BIT0: MITM, BIT1:SC.\r
///\r
- EfiBluetoothConfigDataTypeKeyType, /* Relevant for LE*/\r
+ EfiBluetoothConfigDataTypeKeyType, /* Relevant for LE*/\r
EfiBluetoothConfigDataTypeEncKeySize, /* Relevant for LE*/\r
EfiBluetoothConfigDataTypeMax,\r
} EFI_BLUETOOTH_CONFIG_DATA_TYPE;\r
EfiBluetoothConnCallbackTypeEncrypted\r
} EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE;\r
\r
-\r
/**\r
Initialize Bluetooth host controller and local device.\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION) (\r
+(EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION)(\r
IN EFI_BLUETOOTH_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION *CallbackInfo\r
/// This protocol abstracts user interface configuration for Bluetooth device.\r
///\r
struct _EFI_BLUETOOTH_CONFIG_PROTOCOL {\r
- EFI_BLUETOOTH_CONFIG_INIT Init;\r
- EFI_BLUETOOTH_CONFIG_SCAN Scan;\r
- EFI_BLUETOOTH_CONFIG_CONNECT Connect;\r
- EFI_BLUETOOTH_CONFIG_DISCONNECT Disconnect;\r
- EFI_BLUETOOTH_CONFIG_GET_DATA GetData;\r
- EFI_BLUETOOTH_CONFIG_SET_DATA SetData;\r
- EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA GetRemoteData;\r
- EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK RegisterPinCallback;\r
- EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK RegisterGetLinkKeyCallback;\r
- EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK RegisterSetLinkKeyCallback;\r
- EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;\r
+ EFI_BLUETOOTH_CONFIG_INIT Init;\r
+ EFI_BLUETOOTH_CONFIG_SCAN Scan;\r
+ EFI_BLUETOOTH_CONFIG_CONNECT Connect;\r
+ EFI_BLUETOOTH_CONFIG_DISCONNECT Disconnect;\r
+ EFI_BLUETOOTH_CONFIG_GET_DATA GetData;\r
+ EFI_BLUETOOTH_CONFIG_SET_DATA SetData;\r
+ EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA GetRemoteData;\r
+ EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK RegisterPinCallback;\r
+ EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK RegisterGetLinkKeyCallback;\r
+ EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK RegisterSetLinkKeyCallback;\r
+ EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;\r
};\r
\r
-extern EFI_GUID gEfiBluetoothConfigProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothConfigProtocolGuid;\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK)(\r
IN VOID *Data,\r
IN UINTN DataLength,\r
IN VOID *Context\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT) (\r
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT)(\r
IN EFI_BLUETOOTH_HC_PROTOCOL *This,\r
IN BOOLEAN IsNewTransfer,\r
IN UINTN PollingInterval,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA)(\r
IN EFI_BLUETOOTH_HC_PROTOCOL *This,\r
IN BOOLEAN IsNewTransfer,\r
IN UINTN PollingInterval,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA)(\r
IN EFI_BLUETOOTH_HC_PROTOCOL *This,\r
IN BOOLEAN IsNewTransfer,\r
IN UINTN PollingInterval,\r
//\r
// Send HCI command packet.\r
//\r
- EFI_BLUETOOTH_HC_SEND_COMMAND SendCommand;\r
+ EFI_BLUETOOTH_HC_SEND_COMMAND SendCommand;\r
//\r
// Receive HCI event packets.\r
//\r
- EFI_BLUETOOTH_HC_RECEIVE_EVENT ReceiveEvent;\r
+ EFI_BLUETOOTH_HC_RECEIVE_EVENT ReceiveEvent;\r
//\r
// Non-blocking receive HCI event packets.\r
//\r
- EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT AsyncReceiveEvent;\r
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT AsyncReceiveEvent;\r
//\r
// Send HCI ACL (asynchronous connection-oriented) data packets.\r
//\r
- EFI_BLUETOOTH_HC_SEND_ACL_DATA SendACLData;\r
+ EFI_BLUETOOTH_HC_SEND_ACL_DATA SendACLData;\r
//\r
// Receive HCI ACL data packets.\r
//\r
- EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA ReceiveACLData;\r
+ EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA ReceiveACLData;\r
//\r
// Non-blocking receive HCI ACL data packets.\r
//\r
- EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA AsyncReceiveACLData;\r
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA AsyncReceiveACLData;\r
//\r
// Send HCI synchronous (SCO and eSCO) data packets.\r
//\r
- EFI_BLUETOOTH_HC_SEND_SCO_DATA SendSCOData;\r
+ EFI_BLUETOOTH_HC_SEND_SCO_DATA SendSCOData;\r
//\r
// Receive HCI synchronous data packets.\r
//\r
- EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA ReceiveSCOData;\r
+ EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA ReceiveSCOData;\r
//\r
// Non-blocking receive HCI synchronous data packets.\r
//\r
- EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA AsyncReceiveSCOData;\r
+ EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA AsyncReceiveSCOData;\r
};\r
\r
-extern EFI_GUID gEfiBluetoothHcProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothHcProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// The version of the structure\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// 48bit Bluetooth device address.\r
///\r
- BLUETOOTH_ADDRESS BD_ADDR;\r
+ BLUETOOTH_ADDRESS BD_ADDR;\r
///\r
/// Bluetooth PageScanRepetitionMode. See Bluetooth specification for detail.\r
///\r
- UINT8 PageScanRepetitionMode;\r
+ UINT8 PageScanRepetitionMode;\r
///\r
/// Bluetooth ClassOfDevice. See Bluetooth specification for detail.\r
///\r
- BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;\r
+ BLUETOOTH_CLASS_OF_DEVICE ClassOfDevice;\r
///\r
/// Bluetooth CloseOffset. See Bluetooth specification for detail.\r
///\r
- UINT16 ClockOffset;\r
+ UINT16 ClockOffset;\r
///\r
/// Bluetooth RSSI. See Bluetooth specification for detail.\r
///\r
- UINT8 RSSI;\r
+ UINT8 RSSI;\r
///\r
/// Bluetooth ExtendedInquiryResponse. See Bluetooth specification for detail.\r
///\r
- UINT8 ExtendedInquiryResponse[240];\r
+ UINT8 ExtendedInquiryResponse[240];\r
} EFI_BLUETOOTH_DEVICE_INFO;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_IO_ASYNC_FUNC_CALLBACK)(\r
IN UINT16 ChannelID,\r
IN VOID *Data,\r
IN UINTN DataLength,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK)(\r
IN VOID *Data,\r
IN UINTN DataLength,\r
IN VOID *Context\r
IN EFI_BLUETOOTH_IO_PROTOCOL *This,\r
IN EFI_HANDLE Handle,\r
IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK Callback,\r
- IN VOID* Context\r
+ IN VOID *Context\r
);\r
\r
/**\r
EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE L2CapRegisterService;\r
};\r
\r
-extern EFI_GUID gEfiBluetoothIoServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiBluetoothIoProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothIoServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothIoProtocolGuid;\r
\r
#endif\r
/// structure as defined here. Future version of this specification may extend this data structure in a\r
/// backward compatible way and increase the value of Version.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// Passive scanning or active scanning. See Bluetooth specification.\r
///\r
- UINT8 ScanType;\r
+ UINT8 ScanType;\r
///\r
/// Recommended scan interval to be used while performing scan.\r
///\r
- UINT16 ScanInterval;\r
+ UINT16 ScanInterval;\r
///\r
/// Recommended scan window to be used while performing a scan.\r
///\r
- UINT16 ScanWindow;\r
+ UINT16 ScanWindow;\r
///\r
/// Recommended scanning filter policy to be used while performing a scan.\r
///\r
- UINT8 ScanningFilterPolicy;\r
+ UINT8 ScanningFilterPolicy;\r
///\r
/// This is one byte flag to serve as a filter to remove unneeded scan\r
/// result. For example, set BIT0 means scan in LE Limited Discoverable\r
/// Mode. Set BIT1 means scan in LE General Discoverable Mode.\r
///\r
- UINT8 AdvertisementFlagFilter;\r
+ UINT8 AdvertisementFlagFilter;\r
} EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER;\r
\r
-typedef struct{\r
- BLUETOOTH_LE_ADDRESS BDAddr;\r
- BLUETOOTH_LE_ADDRESS DirectAddress;\r
- UINT8 RemoteDeviceState;\r
- INT8 RSSI;\r
- UINTN AdvertisementDataSize;\r
- VOID *AdvertisementData;\r
+typedef struct {\r
+ BLUETOOTH_LE_ADDRESS BDAddr;\r
+ BLUETOOTH_LE_ADDRESS DirectAddress;\r
+ UINT8 RemoteDeviceState;\r
+ INT8 RSSI;\r
+ UINTN AdvertisementDataSize;\r
+ VOID *AdvertisementData;\r
} EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION *CallbackInfo\r
/// extend this data structure in a backward compatible way and\r
/// increase the value of Version.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// Recommended scan interval to be used while performing scan before connect.\r
///\r
- UINT16 ScanInterval;\r
+ UINT16 ScanInterval;\r
///\r
/// Recommended scan window to be used while performing a connection\r
///\r
- UINT16 ScanWindow;\r
+ UINT16 ScanWindow;\r
///\r
/// Minimum allowed connection interval. Shall be less than or equal to ConnIntervalMax.\r
///\r
- UINT16 ConnIntervalMin;\r
+ UINT16 ConnIntervalMin;\r
///\r
/// Maximum allowed connection interval. Shall be greater than or equal to ConnIntervalMin.\r
///\r
- UINT16 ConnIntervalMax;\r
+ UINT16 ConnIntervalMax;\r
///\r
/// Slave latency for the connection in number of connection events.\r
///\r
- UINT16 ConnLatency;\r
+ UINT16 ConnLatency;\r
///\r
/// Link supervision timeout for the connection.\r
///\r
- UINT16 SupervisionTimeout;\r
+ UINT16 SupervisionTimeout;\r
} EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,\r
IN OUT UINTN *DataSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,\r
IN UINTN DataSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_CONFIG_DATA_TYPE DataType,\r
IN BLUETOOTH_LE_ADDRESS *BDAddr,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN BLUETOOTH_LE_ADDRESS *BDAddr,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_LE_SMP_CALLBACK Callback,\r
IN VOID *Context\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN BLUETOOTH_LE_ADDRESS *BDAddr,\r
IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE EventDataType,\r
\r
typedef enum {\r
// For local device only\r
- EfiBluetoothSmpLocalIR, /* If Key hierarchy is supported */\r
- EfiBluetoothSmpLocalER, /* If Key hierarchy is supported */\r
+ EfiBluetoothSmpLocalIR, /* If Key hierarchy is supported */\r
+ EfiBluetoothSmpLocalER, /* If Key hierarchy is supported */\r
EfiBluetoothSmpLocalDHK, /* If Key hierarchy is supported. OPTIONAL */\r
// For peer specific\r
EfiBluetoothSmpKeysDistributed = 0x1000,\r
EfiBluetoothSmpPeerRand,\r
EfiBluetoothSmpPeerEDIV,\r
EfiBluetoothSmpPeerSignCounter,\r
- EfiBluetoothSmpLocalLTK, /* If Key hierarchy not supported */\r
- EfiBluetoothSmpLocalIRK, /* If Key hierarchy not supported */\r
+ EfiBluetoothSmpLocalLTK, /* If Key hierarchy not supported */\r
+ EfiBluetoothSmpLocalIRK, /* If Key hierarchy not supported */\r
EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not supported */\r
EfiBluetoothSmpLocalSignCounter,\r
EfiBluetoothSmpLocalDIV,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN BLUETOOTH_LE_ADDRESS *BDAddr,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK Callback,\r
IN VOID *Context\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN BLUETOOTH_LE_ADDRESS *BDAddr,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK Callback,\r
IN VOID *Context\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN VOID *Context,\r
IN EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE CallbackType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK) (\r
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK)(\r
IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL *This,\r
IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK Callback,\r
IN VOID *Context\r
/// This protocol abstracts user interface configuration for BluetoothLe device.\r
///\r
struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL {\r
- EFI_BLUETOOTH_LE_CONFIG_INIT Init;\r
- EFI_BLUETOOTH_LE_CONFIG_SCAN Scan;\r
- EFI_BLUETOOTH_LE_CONFIG_CONNECT Connect;\r
- EFI_BLUETOOTH_LE_CONFIG_DISCONNECT Disconnect;\r
- EFI_BLUETOOTH_LE_CONFIG_GET_DATA GetData;\r
- EFI_BLUETOOTH_LE_CONFIG_SET_DATA SetData;\r
- EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA GetRemoteData;\r
- EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK RegisterSmpAuthCallback;\r
- EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA SendSmpAuthData;\r
- EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK RegisterSmpGetDataCallback;\r
- EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK RegisterSmpSetDataCallback;\r
- EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;\r
+ EFI_BLUETOOTH_LE_CONFIG_INIT Init;\r
+ EFI_BLUETOOTH_LE_CONFIG_SCAN Scan;\r
+ EFI_BLUETOOTH_LE_CONFIG_CONNECT Connect;\r
+ EFI_BLUETOOTH_LE_CONFIG_DISCONNECT Disconnect;\r
+ EFI_BLUETOOTH_LE_CONFIG_GET_DATA GetData;\r
+ EFI_BLUETOOTH_LE_CONFIG_SET_DATA SetData;\r
+ EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA GetRemoteData;\r
+ EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK RegisterSmpAuthCallback;\r
+ EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA SendSmpAuthData;\r
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK RegisterSmpGetDataCallback;\r
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK RegisterSmpSetDataCallback;\r
+ EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;\r
};\r
\r
-extern EFI_GUID gEfiBluetoothLeConfigProtocolGuid;\r
+extern EFI_GUID gEfiBluetoothLeConfigProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCOL;\r
\r
-#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000\r
+#define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000\r
\r
/**\r
Connect a device path following the platforms EFI Boot Manager policy.\r
);\r
\r
struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL {\r
- UINT64 Revision;\r
- EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH ConnectDevicePath;\r
- EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS ConnectDeviceClass;\r
+ UINT64 Revision;\r
+ EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_PATH ConnectDevicePath;\r
+ EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS ConnectDeviceClass;\r
};\r
\r
-extern EFI_GUID gEfiBootManagerPolicyProtocolGuid;\r
+extern EFI_GUID gEfiBootManagerPolicyProtocolGuid;\r
\r
-extern EFI_GUID gEfiBootManagerPolicyConsoleGuid;\r
-extern EFI_GUID gEfiBootManagerPolicyNetworkGuid;\r
-extern EFI_GUID gEfiBootManagerPolicyConnectAllGuid;\r
+extern EFI_GUID gEfiBootManagerPolicyConsoleGuid;\r
+extern EFI_GUID gEfiBootManagerPolicyNetworkGuid;\r
+extern EFI_GUID gEfiBootManagerPolicyConnectAllGuid;\r
\r
#endif\r
0x3bc1b285, 0x8a15, 0x4a82, {0xaa, 0xbf, 0x4d, 0x7d, 0x13, 0xfb, 0x32, 0x65 } \\r
}\r
\r
-typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL;\r
+typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL;\r
\r
//\r
// Prototypes for the Bus Specific Driver Override Protocol\r
/// drivers to controllers.\r
///\r
struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL {\r
- EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER GetDriver;\r
+ EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_GET_DRIVER GetDriver;\r
};\r
\r
-extern EFI_GUID gEfiBusSpecificDriverOverrideProtocolGuid;\r
+extern EFI_GUID gEfiBusSpecificDriverOverrideProtocolGuid;\r
\r
#endif\r
#define EFI_CAPSULE_ARCH_PROTOCOL_GUID \\r
{ 0x5053697e, 0x2cbc, 0x4819, {0x90, 0xd9, 0x05, 0x80, 0xde, 0xee, 0x57, 0x54 }}\r
\r
-extern EFI_GUID gEfiCapsuleArchProtocolGuid;\r
+extern EFI_GUID gEfiCapsuleArchProtocolGuid;\r
\r
#endif\r
0x107a772c, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_COMPONENT_NAME_PROTOCOL EFI_COMPONENT_NAME_PROTOCOL;\r
-\r
+typedef struct _EFI_COMPONENT_NAME_PROTOCOL EFI_COMPONENT_NAME_PROTOCOL;\r
\r
/**\r
Retrieves a Unicode string that is the user-readable name of the EFI Driver.\r
OUT CHAR16 **DriverName\r
);\r
\r
-\r
/**\r
Retrieves a Unicode string that is the user readable name of the controller\r
that is being managed by an EFI Driver.\r
/// and controllers managed by UEFI Drivers.\r
///\r
struct _EFI_COMPONENT_NAME_PROTOCOL {\r
- EFI_COMPONENT_NAME_GET_DRIVER_NAME GetDriverName;\r
- EFI_COMPONENT_NAME_GET_CONTROLLER_NAME GetControllerName;\r
+ EFI_COMPONENT_NAME_GET_DRIVER_NAME GetDriverName;\r
+ EFI_COMPONENT_NAME_GET_CONTROLLER_NAME GetControllerName;\r
///\r
/// A Null-terminated ASCII string that contains one or more\r
/// ISO 639-2 language codes. This is the list of language codes\r
/// that this protocol supports.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiComponentNameProtocolGuid;\r
+extern EFI_GUID gEfiComponentNameProtocolGuid;\r
\r
#endif\r
#define EFI_COMPONENT_NAME2_PROTOCOL_GUID \\r
{0x6a7a5cff, 0xe8d9, 0x4f70, { 0xba, 0xda, 0x75, 0xab, 0x30, 0x25, 0xce, 0x14 } }\r
\r
-typedef struct _EFI_COMPONENT_NAME2_PROTOCOL EFI_COMPONENT_NAME2_PROTOCOL;\r
-\r
+typedef struct _EFI_COMPONENT_NAME2_PROTOCOL EFI_COMPONENT_NAME2_PROTOCOL;\r
\r
/**\r
Retrieves a string that is the user readable name of\r
OUT CHAR16 **DriverName\r
);\r
\r
-\r
/**\r
Retrieves a string that is the user readable name of\r
the controller that is being managed by an EFI Driver.\r
/// and controllers managed by UEFI Drivers.\r
///\r
struct _EFI_COMPONENT_NAME2_PROTOCOL {\r
- EFI_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName;\r
- EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName;\r
+ EFI_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName;\r
+ EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName;\r
\r
///\r
/// A Null-terminated ASCII string array that contains one or more\r
/// driver is up to the driver writer. SupportedLanguages is\r
/// specified in RFC 4646 format.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiComponentName2ProtocolGuid;\r
+extern EFI_GUID gEfiComponentName2ProtocolGuid;\r
\r
#endif\r
#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
{ 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
\r
-typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
+typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
\r
///\r
/// The type of flush operation\r
IN EFI_CPU_FLUSH_TYPE FlushType\r
);\r
\r
-\r
/**\r
This function enables interrupt processing by the processor.\r
\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
-\r
/**\r
This function disables interrupt processing by the processor.\r
\r
IN EFI_CPU_ARCH_PROTOCOL *This\r
);\r
\r
-\r
/**\r
This function retrieves the processor's current interrupt state a returns it in\r
State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
OUT BOOLEAN *State\r
);\r
\r
-\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
processor will be reset, and control will not be returned to the caller. If InitType is\r
IN EFI_CPU_INIT_TYPE InitType\r
);\r
\r
-\r
/**\r
This function registers and enables the handler specified by InterruptHandler for a processor\r
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
);\r
\r
-\r
/**\r
This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
\r
OUT UINT64 *TimerPeriod OPTIONAL\r
);\r
\r
-\r
/**\r
This function modifies the attributes for the memory region specified by BaseAddress and\r
Length from their current attributes to the attributes specified by Attributes.\r
IN UINT64 Attributes\r
);\r
\r
-\r
///\r
/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
/// determining the processor frequency.\r
///\r
struct _EFI_CPU_ARCH_PROTOCOL {\r
- EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
- EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
- EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
- EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
- EFI_CPU_INIT Init;\r
- EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
- EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
- EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
+ EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
+ EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
+ EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
+ EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
+ EFI_CPU_INIT Init;\r
+ EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
+ EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
+ EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
///\r
/// The number of timers that are available in a processor. The value in this\r
/// field is a constant that must not be modified after the CPU Architectural\r
/// Protocol is installed. All consumers must treat this as a read-only field.\r
///\r
- UINT32 NumberOfTimers;\r
+ UINT32 NumberOfTimers;\r
///\r
/// The size, in bytes, of the alignment required for DMA buffer allocations.\r
/// This is typically the size of the largest data cache line in the platform.\r
/// CPU Architectural Protocol is installed. All consumers must treat this as\r
/// a read-only field.\r
///\r
- UINT32 DmaBufferAlignment;\r
+ UINT32 DmaBufferAlignment;\r
};\r
\r
-extern EFI_GUID gEfiCpuArchProtocolGuid;\r
+extern EFI_GUID gEfiCpuArchProtocolGuid;\r
\r
#endif\r
///\r
/// This service provides the various modalities of memory and I/O read.\r
///\r
- EFI_CPU_IO_PROTOCOL_IO_MEM Read;\r
+ EFI_CPU_IO_PROTOCOL_IO_MEM Read;\r
///\r
/// This service provides the various modalities of memory and I/O write.\r
///\r
- EFI_CPU_IO_PROTOCOL_IO_MEM Write;\r
+ EFI_CPU_IO_PROTOCOL_IO_MEM Write;\r
} EFI_CPU_IO_PROTOCOL_ACCESS;\r
\r
///\r
///\r
/// Enables a driver to access memory-mapped registers in the EFI system memory space.\r
///\r
- EFI_CPU_IO_PROTOCOL_ACCESS Mem;\r
+ EFI_CPU_IO_PROTOCOL_ACCESS Mem;\r
///\r
/// Enables a driver to access registers in the EFI CPU I/O space.\r
///\r
- EFI_CPU_IO_PROTOCOL_ACCESS Io;\r
+ EFI_CPU_IO_PROTOCOL_ACCESS Io;\r
};\r
\r
-extern EFI_GUID gEfiCpuIo2ProtocolGuid;\r
+extern EFI_GUID gEfiCpuIo2ProtocolGuid;\r
\r
#endif\r
#ifndef __DEBUG_PORT_H__\r
#define __DEBUG_PORT_H__\r
\r
-\r
///\r
/// DebugPortIo protocol {EBA4E8D2-3858-41EC-A281-2647BA9660D0}\r
///\r
0xEBA4E8D2, 0x3858, 0x41EC, {0xA2, 0x81, 0x26, 0x47, 0xBA, 0x96, 0x60, 0xD0 } \\r
}\r
\r
-extern EFI_GUID gEfiDebugPortProtocolGuid;\r
+extern EFI_GUID gEfiDebugPortProtocolGuid;\r
\r
typedef struct _EFI_DEBUGPORT_PROTOCOL EFI_DEBUGPORT_PROTOCOL;\r
\r
/// This protocol provides the communication link between the debug agent and the remote host.\r
///\r
struct _EFI_DEBUGPORT_PROTOCOL {\r
- EFI_DEBUGPORT_RESET Reset;\r
- EFI_DEBUGPORT_WRITE Write;\r
- EFI_DEBUGPORT_READ Read;\r
- EFI_DEBUGPORT_POLL Poll;\r
+ EFI_DEBUGPORT_RESET Reset;\r
+ EFI_DEBUGPORT_WRITE Write;\r
+ EFI_DEBUGPORT_READ Read;\r
+ EFI_DEBUGPORT_POLL Poll;\r
};\r
\r
//\r
// DEBUGPORT variable definitions...\r
//\r
-#define EFI_DEBUGPORT_VARIABLE_NAME L"DEBUGPORT"\r
-#define EFI_DEBUGPORT_VARIABLE_GUID EFI_DEBUGPORT_PROTOCOL_GUID\r
+#define EFI_DEBUGPORT_VARIABLE_NAME L"DEBUGPORT"\r
+#define EFI_DEBUGPORT_VARIABLE_GUID EFI_DEBUGPORT_PROTOCOL_GUID\r
\r
extern EFI_GUID gEfiDebugPortVariableGuid;\r
\r
//\r
// DebugPort device path definitions...\r
//\r
-#define DEVICE_PATH_MESSAGING_DEBUGPORT EFI_DEBUGPORT_PROTOCOL_GUID\r
+#define DEVICE_PATH_MESSAGING_DEBUGPORT EFI_DEBUGPORT_PROTOCOL_GUID\r
\r
extern EFI_GUID gEfiDebugPortDevicePathGuid;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- EFI_GUID Guid;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_GUID Guid;\r
} DEBUGPORT_DEVICE_PATH;\r
\r
#endif\r
/// Processor exception to be hooked.\r
/// All exception types for IA32, X64, Itanium and EBC processors are defined.\r
///\r
-typedef INTN EFI_EXCEPTION_TYPE;\r
+typedef INTN EFI_EXCEPTION_TYPE;\r
\r
///\r
/// IA-32 processor exception types.\r
///\r
-#define EXCEPT_IA32_DIVIDE_ERROR 0\r
-#define EXCEPT_IA32_DEBUG 1\r
-#define EXCEPT_IA32_NMI 2\r
-#define EXCEPT_IA32_BREAKPOINT 3\r
-#define EXCEPT_IA32_OVERFLOW 4\r
-#define EXCEPT_IA32_BOUND 5\r
-#define EXCEPT_IA32_INVALID_OPCODE 6\r
-#define EXCEPT_IA32_DOUBLE_FAULT 8\r
-#define EXCEPT_IA32_INVALID_TSS 10\r
-#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
-#define EXCEPT_IA32_STACK_FAULT 12\r
-#define EXCEPT_IA32_GP_FAULT 13\r
-#define EXCEPT_IA32_PAGE_FAULT 14\r
-#define EXCEPT_IA32_FP_ERROR 16\r
-#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
-#define EXCEPT_IA32_MACHINE_CHECK 18\r
-#define EXCEPT_IA32_SIMD 19\r
+#define EXCEPT_IA32_DIVIDE_ERROR 0\r
+#define EXCEPT_IA32_DEBUG 1\r
+#define EXCEPT_IA32_NMI 2\r
+#define EXCEPT_IA32_BREAKPOINT 3\r
+#define EXCEPT_IA32_OVERFLOW 4\r
+#define EXCEPT_IA32_BOUND 5\r
+#define EXCEPT_IA32_INVALID_OPCODE 6\r
+#define EXCEPT_IA32_DOUBLE_FAULT 8\r
+#define EXCEPT_IA32_INVALID_TSS 10\r
+#define EXCEPT_IA32_SEG_NOT_PRESENT 11\r
+#define EXCEPT_IA32_STACK_FAULT 12\r
+#define EXCEPT_IA32_GP_FAULT 13\r
+#define EXCEPT_IA32_PAGE_FAULT 14\r
+#define EXCEPT_IA32_FP_ERROR 16\r
+#define EXCEPT_IA32_ALIGNMENT_CHECK 17\r
+#define EXCEPT_IA32_MACHINE_CHECK 18\r
+#define EXCEPT_IA32_SIMD 19\r
\r
///\r
/// FXSAVE_STATE.\r
/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
- UINT16 Fcw;\r
- UINT16 Fsw;\r
- UINT16 Ftw;\r
- UINT16 Opcode;\r
- UINT32 Eip;\r
- UINT16 Cs;\r
- UINT16 Reserved1;\r
- UINT32 DataOffset;\r
- UINT16 Ds;\r
- UINT8 Reserved2[10];\r
- UINT8 St0Mm0[10], Reserved3[6];\r
- UINT8 St1Mm1[10], Reserved4[6];\r
- UINT8 St2Mm2[10], Reserved5[6];\r
- UINT8 St3Mm3[10], Reserved6[6];\r
- UINT8 St4Mm4[10], Reserved7[6];\r
- UINT8 St5Mm5[10], Reserved8[6];\r
- UINT8 St6Mm6[10], Reserved9[6];\r
- UINT8 St7Mm7[10], Reserved10[6];\r
- UINT8 Xmm0[16];\r
- UINT8 Xmm1[16];\r
- UINT8 Xmm2[16];\r
- UINT8 Xmm3[16];\r
- UINT8 Xmm4[16];\r
- UINT8 Xmm5[16];\r
- UINT8 Xmm6[16];\r
- UINT8 Xmm7[16];\r
- UINT8 Reserved11[14 * 16];\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT32 Eip;\r
+ UINT16 Cs;\r
+ UINT16 Reserved1;\r
+ UINT32 DataOffset;\r
+ UINT16 Ds;\r
+ UINT8 Reserved2[10];\r
+ UINT8 St0Mm0[10], Reserved3[6];\r
+ UINT8 St1Mm1[10], Reserved4[6];\r
+ UINT8 St2Mm2[10], Reserved5[6];\r
+ UINT8 St3Mm3[10], Reserved6[6];\r
+ UINT8 St4Mm4[10], Reserved7[6];\r
+ UINT8 St5Mm5[10], Reserved8[6];\r
+ UINT8 St6Mm6[10], Reserved9[6];\r
+ UINT8 St7Mm7[10], Reserved10[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
+ UINT8 Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_IA32;\r
\r
///\r
/// IA-32 processor context definition.\r
///\r
typedef struct {\r
- UINT32 ExceptionData;\r
- EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
- UINT32 Dr0;\r
- UINT32 Dr1;\r
- UINT32 Dr2;\r
- UINT32 Dr3;\r
- UINT32 Dr6;\r
- UINT32 Dr7;\r
- UINT32 Cr0;\r
- UINT32 Cr1; /* Reserved */\r
- UINT32 Cr2;\r
- UINT32 Cr3;\r
- UINT32 Cr4;\r
- UINT32 Eflags;\r
- UINT32 Ldtr;\r
- UINT32 Tr;\r
- UINT32 Gdtr[2];\r
- UINT32 Idtr[2];\r
- UINT32 Eip;\r
- UINT32 Gs;\r
- UINT32 Fs;\r
- UINT32 Es;\r
- UINT32 Ds;\r
- UINT32 Cs;\r
- UINT32 Ss;\r
- UINT32 Edi;\r
- UINT32 Esi;\r
- UINT32 Ebp;\r
- UINT32 Esp;\r
- UINT32 Ebx;\r
- UINT32 Edx;\r
- UINT32 Ecx;\r
- UINT32 Eax;\r
+ UINT32 ExceptionData;\r
+ EFI_FX_SAVE_STATE_IA32 FxSaveState;\r
+ UINT32 Dr0;\r
+ UINT32 Dr1;\r
+ UINT32 Dr2;\r
+ UINT32 Dr3;\r
+ UINT32 Dr6;\r
+ UINT32 Dr7;\r
+ UINT32 Cr0;\r
+ UINT32 Cr1; /* Reserved */\r
+ UINT32 Cr2;\r
+ UINT32 Cr3;\r
+ UINT32 Cr4;\r
+ UINT32 Eflags;\r
+ UINT32 Ldtr;\r
+ UINT32 Tr;\r
+ UINT32 Gdtr[2];\r
+ UINT32 Idtr[2];\r
+ UINT32 Eip;\r
+ UINT32 Gs;\r
+ UINT32 Fs;\r
+ UINT32 Es;\r
+ UINT32 Ds;\r
+ UINT32 Cs;\r
+ UINT32 Ss;\r
+ UINT32 Edi;\r
+ UINT32 Esi;\r
+ UINT32 Ebp;\r
+ UINT32 Esp;\r
+ UINT32 Ebx;\r
+ UINT32 Edx;\r
+ UINT32 Ecx;\r
+ UINT32 Eax;\r
} EFI_SYSTEM_CONTEXT_IA32;\r
\r
///\r
/// x64 processor exception types.\r
///\r
-#define EXCEPT_X64_DIVIDE_ERROR 0\r
-#define EXCEPT_X64_DEBUG 1\r
-#define EXCEPT_X64_NMI 2\r
-#define EXCEPT_X64_BREAKPOINT 3\r
-#define EXCEPT_X64_OVERFLOW 4\r
-#define EXCEPT_X64_BOUND 5\r
-#define EXCEPT_X64_INVALID_OPCODE 6\r
-#define EXCEPT_X64_DOUBLE_FAULT 8\r
-#define EXCEPT_X64_INVALID_TSS 10\r
-#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
-#define EXCEPT_X64_STACK_FAULT 12\r
-#define EXCEPT_X64_GP_FAULT 13\r
-#define EXCEPT_X64_PAGE_FAULT 14\r
-#define EXCEPT_X64_FP_ERROR 16\r
-#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
-#define EXCEPT_X64_MACHINE_CHECK 18\r
-#define EXCEPT_X64_SIMD 19\r
+#define EXCEPT_X64_DIVIDE_ERROR 0\r
+#define EXCEPT_X64_DEBUG 1\r
+#define EXCEPT_X64_NMI 2\r
+#define EXCEPT_X64_BREAKPOINT 3\r
+#define EXCEPT_X64_OVERFLOW 4\r
+#define EXCEPT_X64_BOUND 5\r
+#define EXCEPT_X64_INVALID_OPCODE 6\r
+#define EXCEPT_X64_DOUBLE_FAULT 8\r
+#define EXCEPT_X64_INVALID_TSS 10\r
+#define EXCEPT_X64_SEG_NOT_PRESENT 11\r
+#define EXCEPT_X64_STACK_FAULT 12\r
+#define EXCEPT_X64_GP_FAULT 13\r
+#define EXCEPT_X64_PAGE_FAULT 14\r
+#define EXCEPT_X64_FP_ERROR 16\r
+#define EXCEPT_X64_ALIGNMENT_CHECK 17\r
+#define EXCEPT_X64_MACHINE_CHECK 18\r
+#define EXCEPT_X64_SIMD 19\r
\r
///\r
/// FXSAVE_STATE.\r
/// FP / MMX / XMM registers (see fxrstor instruction definition).\r
///\r
typedef struct {\r
- UINT16 Fcw;\r
- UINT16 Fsw;\r
- UINT16 Ftw;\r
- UINT16 Opcode;\r
- UINT64 Rip;\r
- UINT64 DataOffset;\r
- UINT8 Reserved1[8];\r
- UINT8 St0Mm0[10], Reserved2[6];\r
- UINT8 St1Mm1[10], Reserved3[6];\r
- UINT8 St2Mm2[10], Reserved4[6];\r
- UINT8 St3Mm3[10], Reserved5[6];\r
- UINT8 St4Mm4[10], Reserved6[6];\r
- UINT8 St5Mm5[10], Reserved7[6];\r
- UINT8 St6Mm6[10], Reserved8[6];\r
- UINT8 St7Mm7[10], Reserved9[6];\r
- UINT8 Xmm0[16];\r
- UINT8 Xmm1[16];\r
- UINT8 Xmm2[16];\r
- UINT8 Xmm3[16];\r
- UINT8 Xmm4[16];\r
- UINT8 Xmm5[16];\r
- UINT8 Xmm6[16];\r
- UINT8 Xmm7[16];\r
+ UINT16 Fcw;\r
+ UINT16 Fsw;\r
+ UINT16 Ftw;\r
+ UINT16 Opcode;\r
+ UINT64 Rip;\r
+ UINT64 DataOffset;\r
+ UINT8 Reserved1[8];\r
+ UINT8 St0Mm0[10], Reserved2[6];\r
+ UINT8 St1Mm1[10], Reserved3[6];\r
+ UINT8 St2Mm2[10], Reserved4[6];\r
+ UINT8 St3Mm3[10], Reserved5[6];\r
+ UINT8 St4Mm4[10], Reserved6[6];\r
+ UINT8 St5Mm5[10], Reserved7[6];\r
+ UINT8 St6Mm6[10], Reserved8[6];\r
+ UINT8 St7Mm7[10], Reserved9[6];\r
+ UINT8 Xmm0[16];\r
+ UINT8 Xmm1[16];\r
+ UINT8 Xmm2[16];\r
+ UINT8 Xmm3[16];\r
+ UINT8 Xmm4[16];\r
+ UINT8 Xmm5[16];\r
+ UINT8 Xmm6[16];\r
+ UINT8 Xmm7[16];\r
//\r
// NOTE: UEFI 2.0 spec definition as follows.\r
//\r
- UINT8 Reserved11[14 * 16];\r
+ UINT8 Reserved11[14 * 16];\r
} EFI_FX_SAVE_STATE_X64;\r
\r
///\r
/// x64 processor context definition.\r
///\r
typedef struct {\r
- UINT64 ExceptionData;\r
- EFI_FX_SAVE_STATE_X64 FxSaveState;\r
- UINT64 Dr0;\r
- UINT64 Dr1;\r
- UINT64 Dr2;\r
- UINT64 Dr3;\r
- UINT64 Dr6;\r
- UINT64 Dr7;\r
- UINT64 Cr0;\r
- UINT64 Cr1; /* Reserved */\r
- UINT64 Cr2;\r
- UINT64 Cr3;\r
- UINT64 Cr4;\r
- UINT64 Cr8;\r
- UINT64 Rflags;\r
- UINT64 Ldtr;\r
- UINT64 Tr;\r
- UINT64 Gdtr[2];\r
- UINT64 Idtr[2];\r
- UINT64 Rip;\r
- UINT64 Gs;\r
- UINT64 Fs;\r
- UINT64 Es;\r
- UINT64 Ds;\r
- UINT64 Cs;\r
- UINT64 Ss;\r
- UINT64 Rdi;\r
- UINT64 Rsi;\r
- UINT64 Rbp;\r
- UINT64 Rsp;\r
- UINT64 Rbx;\r
- UINT64 Rdx;\r
- UINT64 Rcx;\r
- UINT64 Rax;\r
- UINT64 R8;\r
- UINT64 R9;\r
- UINT64 R10;\r
- UINT64 R11;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
+ UINT64 ExceptionData;\r
+ EFI_FX_SAVE_STATE_X64 FxSaveState;\r
+ UINT64 Dr0;\r
+ UINT64 Dr1;\r
+ UINT64 Dr2;\r
+ UINT64 Dr3;\r
+ UINT64 Dr6;\r
+ UINT64 Dr7;\r
+ UINT64 Cr0;\r
+ UINT64 Cr1; /* Reserved */\r
+ UINT64 Cr2;\r
+ UINT64 Cr3;\r
+ UINT64 Cr4;\r
+ UINT64 Cr8;\r
+ UINT64 Rflags;\r
+ UINT64 Ldtr;\r
+ UINT64 Tr;\r
+ UINT64 Gdtr[2];\r
+ UINT64 Idtr[2];\r
+ UINT64 Rip;\r
+ UINT64 Gs;\r
+ UINT64 Fs;\r
+ UINT64 Es;\r
+ UINT64 Ds;\r
+ UINT64 Cs;\r
+ UINT64 Ss;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rsp;\r
+ UINT64 Rbx;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rax;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
} EFI_SYSTEM_CONTEXT_X64;\r
\r
///\r
/// Itanium Processor Family Exception types.\r
///\r
-#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
-#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
-#define EXCEPT_IPF_DATA_TLB 2\r
-#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
-#define EXCEPT_IPF_ALT_DATA_TLB 4\r
-#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
-#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
-#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
-#define EXCEPT_IPF_DIRTY_BIT 8\r
-#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
-#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
-#define EXCEPT_IPF_BREAKPOINT 11\r
-#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
+#define EXCEPT_IPF_VHTP_TRANSLATION 0\r
+#define EXCEPT_IPF_INSTRUCTION_TLB 1\r
+#define EXCEPT_IPF_DATA_TLB 2\r
+#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r
+#define EXCEPT_IPF_ALT_DATA_TLB 4\r
+#define EXCEPT_IPF_DATA_NESTED_TLB 5\r
+#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r
+#define EXCEPT_IPF_DATA_KEY_MISSED 7\r
+#define EXCEPT_IPF_DIRTY_BIT 8\r
+#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r
+#define EXCEPT_IPF_DATA_ACCESS_BIT 10\r
+#define EXCEPT_IPF_BREAKPOINT 11\r
+#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r
//\r
// 13 - 19 reserved\r
//\r
//\r
// 37 - 44 reserved\r
//\r
-#define EXCEPT_IPF_IA32_EXCEPTION 45\r
-#define EXCEPT_IPF_IA32_INTERCEPT 46\r
-#define EXCEPT_IPF_IA32_INTERRUPT 47\r
+#define EXCEPT_IPF_IA32_EXCEPTION 45\r
+#define EXCEPT_IPF_IA32_INTERCEPT 46\r
+#define EXCEPT_IPF_IA32_INTERRUPT 47\r
\r
///\r
/// IPF processor context definition.\r
// The first reserved field is necessary to preserve alignment for the correct\r
// bits in UNAT and to insure F2 is 16 byte aligned.\r
//\r
- UINT64 Reserved;\r
- UINT64 R1;\r
- UINT64 R2;\r
- UINT64 R3;\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 R8;\r
- UINT64 R9;\r
- UINT64 R10;\r
- UINT64 R11;\r
- UINT64 R12;\r
- UINT64 R13;\r
- UINT64 R14;\r
- UINT64 R15;\r
- UINT64 R16;\r
- UINT64 R17;\r
- UINT64 R18;\r
- UINT64 R19;\r
- UINT64 R20;\r
- UINT64 R21;\r
- UINT64 R22;\r
- UINT64 R23;\r
- UINT64 R24;\r
- UINT64 R25;\r
- UINT64 R26;\r
- UINT64 R27;\r
- UINT64 R28;\r
- UINT64 R29;\r
- UINT64 R30;\r
- UINT64 R31;\r
-\r
- UINT64 F2[2];\r
- UINT64 F3[2];\r
- UINT64 F4[2];\r
- UINT64 F5[2];\r
- UINT64 F6[2];\r
- UINT64 F7[2];\r
- UINT64 F8[2];\r
- UINT64 F9[2];\r
- UINT64 F10[2];\r
- UINT64 F11[2];\r
- UINT64 F12[2];\r
- UINT64 F13[2];\r
- UINT64 F14[2];\r
- UINT64 F15[2];\r
- UINT64 F16[2];\r
- UINT64 F17[2];\r
- UINT64 F18[2];\r
- UINT64 F19[2];\r
- UINT64 F20[2];\r
- UINT64 F21[2];\r
- UINT64 F22[2];\r
- UINT64 F23[2];\r
- UINT64 F24[2];\r
- UINT64 F25[2];\r
- UINT64 F26[2];\r
- UINT64 F27[2];\r
- UINT64 F28[2];\r
- UINT64 F29[2];\r
- UINT64 F30[2];\r
- UINT64 F31[2];\r
-\r
- UINT64 Pr;\r
-\r
- UINT64 B0;\r
- UINT64 B1;\r
- UINT64 B2;\r
- UINT64 B3;\r
- UINT64 B4;\r
- UINT64 B5;\r
- UINT64 B6;\r
- UINT64 B7;\r
+ UINT64 Reserved;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 R8;\r
+ UINT64 R9;\r
+ UINT64 R10;\r
+ UINT64 R11;\r
+ UINT64 R12;\r
+ UINT64 R13;\r
+ UINT64 R14;\r
+ UINT64 R15;\r
+ UINT64 R16;\r
+ UINT64 R17;\r
+ UINT64 R18;\r
+ UINT64 R19;\r
+ UINT64 R20;\r
+ UINT64 R21;\r
+ UINT64 R22;\r
+ UINT64 R23;\r
+ UINT64 R24;\r
+ UINT64 R25;\r
+ UINT64 R26;\r
+ UINT64 R27;\r
+ UINT64 R28;\r
+ UINT64 R29;\r
+ UINT64 R30;\r
+ UINT64 R31;\r
+\r
+ UINT64 F2[2];\r
+ UINT64 F3[2];\r
+ UINT64 F4[2];\r
+ UINT64 F5[2];\r
+ UINT64 F6[2];\r
+ UINT64 F7[2];\r
+ UINT64 F8[2];\r
+ UINT64 F9[2];\r
+ UINT64 F10[2];\r
+ UINT64 F11[2];\r
+ UINT64 F12[2];\r
+ UINT64 F13[2];\r
+ UINT64 F14[2];\r
+ UINT64 F15[2];\r
+ UINT64 F16[2];\r
+ UINT64 F17[2];\r
+ UINT64 F18[2];\r
+ UINT64 F19[2];\r
+ UINT64 F20[2];\r
+ UINT64 F21[2];\r
+ UINT64 F22[2];\r
+ UINT64 F23[2];\r
+ UINT64 F24[2];\r
+ UINT64 F25[2];\r
+ UINT64 F26[2];\r
+ UINT64 F27[2];\r
+ UINT64 F28[2];\r
+ UINT64 F29[2];\r
+ UINT64 F30[2];\r
+ UINT64 F31[2];\r
+\r
+ UINT64 Pr;\r
+\r
+ UINT64 B0;\r
+ UINT64 B1;\r
+ UINT64 B2;\r
+ UINT64 B3;\r
+ UINT64 B4;\r
+ UINT64 B5;\r
+ UINT64 B6;\r
+ UINT64 B7;\r
\r
//\r
// application registers\r
//\r
- UINT64 ArRsc;\r
- UINT64 ArBsp;\r
- UINT64 ArBspstore;\r
- UINT64 ArRnat;\r
+ UINT64 ArRsc;\r
+ UINT64 ArBsp;\r
+ UINT64 ArBspstore;\r
+ UINT64 ArRnat;\r
\r
- UINT64 ArFcr;\r
+ UINT64 ArFcr;\r
\r
- UINT64 ArEflag;\r
- UINT64 ArCsd;\r
- UINT64 ArSsd;\r
- UINT64 ArCflg;\r
- UINT64 ArFsr;\r
- UINT64 ArFir;\r
- UINT64 ArFdr;\r
+ UINT64 ArEflag;\r
+ UINT64 ArCsd;\r
+ UINT64 ArSsd;\r
+ UINT64 ArCflg;\r
+ UINT64 ArFsr;\r
+ UINT64 ArFir;\r
+ UINT64 ArFdr;\r
\r
- UINT64 ArCcv;\r
+ UINT64 ArCcv;\r
\r
- UINT64 ArUnat;\r
+ UINT64 ArUnat;\r
\r
- UINT64 ArFpsr;\r
+ UINT64 ArFpsr;\r
\r
- UINT64 ArPfs;\r
- UINT64 ArLc;\r
- UINT64 ArEc;\r
+ UINT64 ArPfs;\r
+ UINT64 ArLc;\r
+ UINT64 ArEc;\r
\r
//\r
// control registers\r
//\r
- UINT64 CrDcr;\r
- UINT64 CrItm;\r
- UINT64 CrIva;\r
- UINT64 CrPta;\r
- UINT64 CrIpsr;\r
- UINT64 CrIsr;\r
- UINT64 CrIip;\r
- UINT64 CrIfa;\r
- UINT64 CrItir;\r
- UINT64 CrIipa;\r
- UINT64 CrIfs;\r
- UINT64 CrIim;\r
- UINT64 CrIha;\r
+ UINT64 CrDcr;\r
+ UINT64 CrItm;\r
+ UINT64 CrIva;\r
+ UINT64 CrPta;\r
+ UINT64 CrIpsr;\r
+ UINT64 CrIsr;\r
+ UINT64 CrIip;\r
+ UINT64 CrIfa;\r
+ UINT64 CrItir;\r
+ UINT64 CrIipa;\r
+ UINT64 CrIfs;\r
+ UINT64 CrIim;\r
+ UINT64 CrIha;\r
\r
//\r
// debug registers\r
//\r
- UINT64 Dbr0;\r
- UINT64 Dbr1;\r
- UINT64 Dbr2;\r
- UINT64 Dbr3;\r
- UINT64 Dbr4;\r
- UINT64 Dbr5;\r
- UINT64 Dbr6;\r
- UINT64 Dbr7;\r
-\r
- UINT64 Ibr0;\r
- UINT64 Ibr1;\r
- UINT64 Ibr2;\r
- UINT64 Ibr3;\r
- UINT64 Ibr4;\r
- UINT64 Ibr5;\r
- UINT64 Ibr6;\r
- UINT64 Ibr7;\r
+ UINT64 Dbr0;\r
+ UINT64 Dbr1;\r
+ UINT64 Dbr2;\r
+ UINT64 Dbr3;\r
+ UINT64 Dbr4;\r
+ UINT64 Dbr5;\r
+ UINT64 Dbr6;\r
+ UINT64 Dbr7;\r
+\r
+ UINT64 Ibr0;\r
+ UINT64 Ibr1;\r
+ UINT64 Ibr2;\r
+ UINT64 Ibr3;\r
+ UINT64 Ibr4;\r
+ UINT64 Ibr5;\r
+ UINT64 Ibr6;\r
+ UINT64 Ibr7;\r
\r
//\r
// virtual registers - nat bits for R1-R31\r
//\r
- UINT64 IntNat;\r
-\r
+ UINT64 IntNat;\r
} EFI_SYSTEM_CONTEXT_IPF;\r
\r
///\r
/// EBC processor exception types.\r
///\r
-#define EXCEPT_EBC_UNDEFINED 0\r
-#define EXCEPT_EBC_DIVIDE_ERROR 1\r
-#define EXCEPT_EBC_DEBUG 2\r
-#define EXCEPT_EBC_BREAKPOINT 3\r
-#define EXCEPT_EBC_OVERFLOW 4\r
-#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
-#define EXCEPT_EBC_STACK_FAULT 6\r
-#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
-#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
-#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
-#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
+#define EXCEPT_EBC_UNDEFINED 0\r
+#define EXCEPT_EBC_DIVIDE_ERROR 1\r
+#define EXCEPT_EBC_DEBUG 2\r
+#define EXCEPT_EBC_BREAKPOINT 3\r
+#define EXCEPT_EBC_OVERFLOW 4\r
+#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r
+#define EXCEPT_EBC_STACK_FAULT 6\r
+#define EXCEPT_EBC_ALIGNMENT_CHECK 7\r
+#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r
+#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r
+#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r
///\r
/// For coding convenience, define the maximum valid EBC exception.\r
///\r
-#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
+#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r
\r
///\r
/// EBC processor context definition.\r
///\r
typedef struct {\r
- UINT64 R0;\r
- UINT64 R1;\r
- UINT64 R2;\r
- UINT64 R3;\r
- UINT64 R4;\r
- UINT64 R5;\r
- UINT64 R6;\r
- UINT64 R7;\r
- UINT64 Flags;\r
- UINT64 ControlFlags;\r
- UINT64 Ip;\r
+ UINT64 R0;\r
+ UINT64 R1;\r
+ UINT64 R2;\r
+ UINT64 R3;\r
+ UINT64 R4;\r
+ UINT64 R5;\r
+ UINT64 R6;\r
+ UINT64 R7;\r
+ UINT64 Flags;\r
+ UINT64 ControlFlags;\r
+ UINT64 Ip;\r
} EFI_SYSTEM_CONTEXT_EBC;\r
\r
-\r
-\r
///\r
/// ARM processor exception types.\r
///\r
-#define EXCEPT_ARM_RESET 0\r
-#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
-#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
-#define EXCEPT_ARM_PREFETCH_ABORT 3\r
-#define EXCEPT_ARM_DATA_ABORT 4\r
-#define EXCEPT_ARM_RESERVED 5\r
-#define EXCEPT_ARM_IRQ 6\r
-#define EXCEPT_ARM_FIQ 7\r
+#define EXCEPT_ARM_RESET 0\r
+#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r
+#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r
+#define EXCEPT_ARM_PREFETCH_ABORT 3\r
+#define EXCEPT_ARM_DATA_ABORT 4\r
+#define EXCEPT_ARM_RESERVED 5\r
+#define EXCEPT_ARM_IRQ 6\r
+#define EXCEPT_ARM_FIQ 7\r
\r
///\r
/// For coding convenience, define the maximum valid ARM exception.\r
///\r
-#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
+#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r
\r
///\r
/// ARM processor context definition.\r
///\r
typedef struct {\r
- UINT32 R0;\r
- UINT32 R1;\r
- UINT32 R2;\r
- UINT32 R3;\r
- UINT32 R4;\r
- UINT32 R5;\r
- UINT32 R6;\r
- UINT32 R7;\r
- UINT32 R8;\r
- UINT32 R9;\r
- UINT32 R10;\r
- UINT32 R11;\r
- UINT32 R12;\r
- UINT32 SP;\r
- UINT32 LR;\r
- UINT32 PC;\r
- UINT32 CPSR;\r
- UINT32 DFSR;\r
- UINT32 DFAR;\r
- UINT32 IFSR;\r
- UINT32 IFAR;\r
+ UINT32 R0;\r
+ UINT32 R1;\r
+ UINT32 R2;\r
+ UINT32 R3;\r
+ UINT32 R4;\r
+ UINT32 R5;\r
+ UINT32 R6;\r
+ UINT32 R7;\r
+ UINT32 R8;\r
+ UINT32 R9;\r
+ UINT32 R10;\r
+ UINT32 R11;\r
+ UINT32 R12;\r
+ UINT32 SP;\r
+ UINT32 LR;\r
+ UINT32 PC;\r
+ UINT32 CPSR;\r
+ UINT32 DFSR;\r
+ UINT32 DFAR;\r
+ UINT32 IFSR;\r
+ UINT32 IFAR;\r
} EFI_SYSTEM_CONTEXT_ARM;\r
\r
-\r
///\r
/// AARCH64 processor exception types.\r
///\r
-#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
-#define EXCEPT_AARCH64_IRQ 1\r
-#define EXCEPT_AARCH64_FIQ 2\r
-#define EXCEPT_AARCH64_SERROR 3\r
+#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r
+#define EXCEPT_AARCH64_IRQ 1\r
+#define EXCEPT_AARCH64_FIQ 2\r
+#define EXCEPT_AARCH64_SERROR 3\r
\r
///\r
/// For coding convenience, define the maximum valid ARM exception.\r
///\r
-#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
+#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r
\r
typedef struct {\r
// General Purpose Registers\r
- UINT64 X0;\r
- UINT64 X1;\r
- UINT64 X2;\r
- UINT64 X3;\r
- UINT64 X4;\r
- UINT64 X5;\r
- UINT64 X6;\r
- UINT64 X7;\r
- UINT64 X8;\r
- UINT64 X9;\r
- UINT64 X10;\r
- UINT64 X11;\r
- UINT64 X12;\r
- UINT64 X13;\r
- UINT64 X14;\r
- UINT64 X15;\r
- UINT64 X16;\r
- UINT64 X17;\r
- UINT64 X18;\r
- UINT64 X19;\r
- UINT64 X20;\r
- UINT64 X21;\r
- UINT64 X22;\r
- UINT64 X23;\r
- UINT64 X24;\r
- UINT64 X25;\r
- UINT64 X26;\r
- UINT64 X27;\r
- UINT64 X28;\r
- UINT64 FP; // x29 - Frame pointer\r
- UINT64 LR; // x30 - Link Register\r
- UINT64 SP; // x31 - Stack pointer\r
+ UINT64 X0;\r
+ UINT64 X1;\r
+ UINT64 X2;\r
+ UINT64 X3;\r
+ UINT64 X4;\r
+ UINT64 X5;\r
+ UINT64 X6;\r
+ UINT64 X7;\r
+ UINT64 X8;\r
+ UINT64 X9;\r
+ UINT64 X10;\r
+ UINT64 X11;\r
+ UINT64 X12;\r
+ UINT64 X13;\r
+ UINT64 X14;\r
+ UINT64 X15;\r
+ UINT64 X16;\r
+ UINT64 X17;\r
+ UINT64 X18;\r
+ UINT64 X19;\r
+ UINT64 X20;\r
+ UINT64 X21;\r
+ UINT64 X22;\r
+ UINT64 X23;\r
+ UINT64 X24;\r
+ UINT64 X25;\r
+ UINT64 X26;\r
+ UINT64 X27;\r
+ UINT64 X28;\r
+ UINT64 FP; // x29 - Frame pointer\r
+ UINT64 LR; // x30 - Link Register\r
+ UINT64 SP; // x31 - Stack pointer\r
\r
// FP/SIMD Registers\r
- UINT64 V0[2];\r
- UINT64 V1[2];\r
- UINT64 V2[2];\r
- UINT64 V3[2];\r
- UINT64 V4[2];\r
- UINT64 V5[2];\r
- UINT64 V6[2];\r
- UINT64 V7[2];\r
- UINT64 V8[2];\r
- UINT64 V9[2];\r
- UINT64 V10[2];\r
- UINT64 V11[2];\r
- UINT64 V12[2];\r
- UINT64 V13[2];\r
- UINT64 V14[2];\r
- UINT64 V15[2];\r
- UINT64 V16[2];\r
- UINT64 V17[2];\r
- UINT64 V18[2];\r
- UINT64 V19[2];\r
- UINT64 V20[2];\r
- UINT64 V21[2];\r
- UINT64 V22[2];\r
- UINT64 V23[2];\r
- UINT64 V24[2];\r
- UINT64 V25[2];\r
- UINT64 V26[2];\r
- UINT64 V27[2];\r
- UINT64 V28[2];\r
- UINT64 V29[2];\r
- UINT64 V30[2];\r
- UINT64 V31[2];\r
-\r
- UINT64 ELR; // Exception Link Register\r
- UINT64 SPSR; // Saved Processor Status Register\r
- UINT64 FPSR; // Floating Point Status Register\r
- UINT64 ESR; // Exception syndrome register\r
- UINT64 FAR; // Fault Address Register\r
+ UINT64 V0[2];\r
+ UINT64 V1[2];\r
+ UINT64 V2[2];\r
+ UINT64 V3[2];\r
+ UINT64 V4[2];\r
+ UINT64 V5[2];\r
+ UINT64 V6[2];\r
+ UINT64 V7[2];\r
+ UINT64 V8[2];\r
+ UINT64 V9[2];\r
+ UINT64 V10[2];\r
+ UINT64 V11[2];\r
+ UINT64 V12[2];\r
+ UINT64 V13[2];\r
+ UINT64 V14[2];\r
+ UINT64 V15[2];\r
+ UINT64 V16[2];\r
+ UINT64 V17[2];\r
+ UINT64 V18[2];\r
+ UINT64 V19[2];\r
+ UINT64 V20[2];\r
+ UINT64 V21[2];\r
+ UINT64 V22[2];\r
+ UINT64 V23[2];\r
+ UINT64 V24[2];\r
+ UINT64 V25[2];\r
+ UINT64 V26[2];\r
+ UINT64 V27[2];\r
+ UINT64 V28[2];\r
+ UINT64 V29[2];\r
+ UINT64 V30[2];\r
+ UINT64 V31[2];\r
+\r
+ UINT64 ELR; // Exception Link Register\r
+ UINT64 SPSR; // Saved Processor Status Register\r
+ UINT64 FPSR; // Floating Point Status Register\r
+ UINT64 ESR; // Exception syndrome register\r
+ UINT64 FAR; // Fault Address Register\r
} EFI_SYSTEM_CONTEXT_AARCH64;\r
\r
///\r
/// RISC-V processor exception types.\r
///\r
-#define EXCEPT_RISCV_INST_MISALIGNED 0\r
-#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
-#define EXCEPT_RISCV_ILLEGAL_INST 2\r
-#define EXCEPT_RISCV_BREAKPOINT 3\r
-#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
-#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
-#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
-#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
-#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
-\r
-#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
-#define EXCEPT_RISCV_TIMER_INT 0x1\r
+#define EXCEPT_RISCV_INST_MISALIGNED 0\r
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1\r
+#define EXCEPT_RISCV_ILLEGAL_INST 2\r
+#define EXCEPT_RISCV_BREAKPOINT 3\r
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4\r
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5\r
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6\r
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10\r
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11\r
+\r
+#define EXCEPT_RISCV_SOFTWARE_INT 0x0\r
+#define EXCEPT_RISCV_TIMER_INT 0x1\r
\r
typedef struct {\r
- UINT64 X0;\r
- UINT64 X1;\r
- UINT64 X2;\r
- UINT64 X3;\r
- UINT64 X4;\r
- UINT64 X5;\r
- UINT64 X6;\r
- UINT64 X7;\r
- UINT64 X8;\r
- UINT64 X9;\r
- UINT64 X10;\r
- UINT64 X11;\r
- UINT64 X12;\r
- UINT64 X13;\r
- UINT64 X14;\r
- UINT64 X15;\r
- UINT64 X16;\r
- UINT64 X17;\r
- UINT64 X18;\r
- UINT64 X19;\r
- UINT64 X20;\r
- UINT64 X21;\r
- UINT64 X22;\r
- UINT64 X23;\r
- UINT64 X24;\r
- UINT64 X25;\r
- UINT64 X26;\r
- UINT64 X27;\r
- UINT64 X28;\r
- UINT64 X29;\r
- UINT64 X30;\r
- UINT64 X31;\r
+ UINT64 X0;\r
+ UINT64 X1;\r
+ UINT64 X2;\r
+ UINT64 X3;\r
+ UINT64 X4;\r
+ UINT64 X5;\r
+ UINT64 X6;\r
+ UINT64 X7;\r
+ UINT64 X8;\r
+ UINT64 X9;\r
+ UINT64 X10;\r
+ UINT64 X11;\r
+ UINT64 X12;\r
+ UINT64 X13;\r
+ UINT64 X14;\r
+ UINT64 X15;\r
+ UINT64 X16;\r
+ UINT64 X17;\r
+ UINT64 X18;\r
+ UINT64 X19;\r
+ UINT64 X20;\r
+ UINT64 X21;\r
+ UINT64 X22;\r
+ UINT64 X23;\r
+ UINT64 X24;\r
+ UINT64 X25;\r
+ UINT64 X26;\r
+ UINT64 X27;\r
+ UINT64 X28;\r
+ UINT64 X29;\r
+ UINT64 X30;\r
+ UINT64 X31;\r
} EFI_SYSTEM_CONTEXT_RISCV64;\r
\r
///\r
/// Universal EFI_SYSTEM_CONTEXT definition.\r
///\r
typedef union {\r
- EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
- EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
- EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
- EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
- EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
- EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;\r
} EFI_SYSTEM_CONTEXT;\r
\r
//\r
/// Machine type definition\r
///\r
typedef enum {\r
- IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
- IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
- IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
- IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
- IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
- IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
+ IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r
+ IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r
+ IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r
+ IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r
+ IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r
+ IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r
} EFI_INSTRUCTION_SET_ARCHITECTURE;\r
\r
-\r
//\r
// DebugSupport member function definitions\r
//\r
///\r
/// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r
///\r
- EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
- EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
- EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
- EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
- EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
+ EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r
+ EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r
+ EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r
+ EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r
+ EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r
};\r
\r
-extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
+extern EFI_GUID gEfiDebugSupportProtocolGuid;\r
\r
#endif\r
0xd8117cfe, 0x94a6, 0x11d4, {0x9a, 0x3a, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_DECOMPRESS_PROTOCOL EFI_DECOMPRESS_PROTOCOL;\r
+typedef struct _EFI_DECOMPRESS_PROTOCOL EFI_DECOMPRESS_PROTOCOL;\r
\r
/**\r
The GetInfo() function retrieves the size of the uncompressed buffer\r
/// Provides a decompression service.\r
///\r
struct _EFI_DECOMPRESS_PROTOCOL {\r
- EFI_DECOMPRESS_GET_INFO GetInfo;\r
- EFI_DECOMPRESS_DECOMPRESS Decompress;\r
+ EFI_DECOMPRESS_GET_INFO GetInfo;\r
+ EFI_DECOMPRESS_DECOMPRESS Decompress;\r
};\r
\r
-extern EFI_GUID gEfiDecompressProtocolGuid;\r
+extern EFI_GUID gEfiDecompressProtocolGuid;\r
\r
#endif\r
0x15853d7c, 0x3ddf, 0x43e0, { 0xa1, 0xcb, 0xeb, 0xf8, 0x5b, 0x8f, 0x87, 0x2c } \\r
};\r
\r
-typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL EFI_DEFERRED_IMAGE_LOAD_PROTOCOL;\r
+typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL EFI_DEFERRED_IMAGE_LOAD_PROTOCOL;\r
\r
/**\r
Returns information about a deferred image.\r
/// This protocol returns information about a deferred image.\r
///\r
struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL {\r
- EFI_DEFERRED_IMAGE_INFO GetImageInfo;\r
+ EFI_DEFERRED_IMAGE_INFO GetImageInfo;\r
};\r
\r
-extern EFI_GUID gEfiDeferredImageLoadProtocolGuid;\r
+extern EFI_GUID gEfiDeferredImageLoadProtocolGuid;\r
\r
#endif\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_INTERFACE;\r
+typedef EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_INTERFACE;\r
\r
///\r
/// Device IO Access Width\r
);\r
\r
typedef struct {\r
- EFI_DEVICE_IO Read;\r
- EFI_DEVICE_IO Write;\r
+ EFI_DEVICE_IO Read;\r
+ EFI_DEVICE_IO Write;\r
} EFI_IO_ACCESS;\r
\r
/**\r
///\r
/// Allows reads and writes to memory mapped I/O space.\r
///\r
- EFI_IO_ACCESS Mem;\r
+ EFI_IO_ACCESS Mem;\r
///\r
/// Allows reads and writes to I/O space.\r
///\r
- EFI_IO_ACCESS Io;\r
+ EFI_IO_ACCESS Io;\r
///\r
/// Allows reads and writes to PCI configuration space.\r
///\r
- EFI_IO_ACCESS Pci;\r
- EFI_IO_MAP Map;\r
- EFI_PCI_DEVICE_PATH PciDevicePath;\r
- EFI_IO_UNMAP Unmap;\r
- EFI_IO_ALLOCATE_BUFFER AllocateBuffer;\r
- EFI_IO_FLUSH Flush;\r
- EFI_IO_FREE_BUFFER FreeBuffer;\r
+ EFI_IO_ACCESS Pci;\r
+ EFI_IO_MAP Map;\r
+ EFI_PCI_DEVICE_PATH PciDevicePath;\r
+ EFI_IO_UNMAP Unmap;\r
+ EFI_IO_ALLOCATE_BUFFER AllocateBuffer;\r
+ EFI_IO_FLUSH Flush;\r
+ EFI_IO_FREE_BUFFER FreeBuffer;\r
};\r
\r
-extern EFI_GUID gEfiDeviceIoProtocolGuid;\r
+extern EFI_GUID gEfiDeviceIoProtocolGuid;\r
\r
#endif\r
that make up the Device Path.\r
**/\r
typedef struct {\r
- UINT8 Type; ///< 0x01 Hardware Device Path.\r
+ UINT8 Type; ///< 0x01 Hardware Device Path.\r
///< 0x02 ACPI Device Path.\r
///< 0x03 Messaging Device Path.\r
///< 0x04 Media Device Path.\r
///< 0x05 BIOS Boot Specification Device Path.\r
///< 0x7F End of Hardware Device Path.\r
\r
- UINT8 SubType; ///< Varies by Type\r
+ UINT8 SubType; ///< Varies by Type\r
///< 0xFF End Entire Device Path, or\r
///< 0x01 End This Instance of a Device Path and start a new\r
///< Device Path.\r
\r
- UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define\r
- ///< type of data. Size of data is included in Length.\r
-\r
+ UINT8 Length[2]; ///< Specific Device Path data. Type and Sub-Type define\r
+ ///< type of data. Size of data is included in Length.\r
} EFI_DEVICE_PATH_PROTOCOL;\r
\r
///\r
/// Device Path protocol definition for backward-compatible with EFI1.1.\r
///\r
-typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH;\r
+typedef EFI_DEVICE_PATH_PROTOCOL EFI_DEVICE_PATH;\r
\r
///\r
/// Hardware Device Paths.\r
///\r
-#define HARDWARE_DEVICE_PATH 0x01\r
+#define HARDWARE_DEVICE_PATH 0x01\r
\r
///\r
/// PCI Device Path SubType.\r
///\r
-#define HW_PCI_DP 0x01\r
+#define HW_PCI_DP 0x01\r
\r
///\r
/// PCI Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// PCI Function Number.\r
///\r
- UINT8 Function;\r
+ UINT8 Function;\r
///\r
/// PCI Device Number.\r
///\r
- UINT8 Device;\r
+ UINT8 Device;\r
} PCI_DEVICE_PATH;\r
\r
///\r
/// PCCARD Device Path SubType.\r
///\r
-#define HW_PCCARD_DP 0x02\r
+#define HW_PCCARD_DP 0x02\r
\r
///\r
/// PCCARD Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Function Number (0 = First Function).\r
///\r
- UINT8 FunctionNumber;\r
+ UINT8 FunctionNumber;\r
} PCCARD_DEVICE_PATH;\r
\r
///\r
/// Memory Mapped Device Path SubType.\r
///\r
-#define HW_MEMMAP_DP 0x03\r
+#define HW_MEMMAP_DP 0x03\r
\r
///\r
/// Memory Mapped Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// EFI_MEMORY_TYPE\r
///\r
- UINT32 MemoryType;\r
+ UINT32 MemoryType;\r
///\r
/// Starting Memory Address.\r
///\r
- EFI_PHYSICAL_ADDRESS StartingAddress;\r
+ EFI_PHYSICAL_ADDRESS StartingAddress;\r
///\r
/// Ending Memory Address.\r
///\r
- EFI_PHYSICAL_ADDRESS EndingAddress;\r
+ EFI_PHYSICAL_ADDRESS EndingAddress;\r
} MEMMAP_DEVICE_PATH;\r
\r
///\r
/// Hardware Vendor Device Path SubType.\r
///\r
-#define HW_VENDOR_DP 0x04\r
+#define HW_VENDOR_DP 0x04\r
\r
///\r
/// The Vendor Device Path allows the creation of vendor-defined Device Paths. A vendor must\r
/// contents on the n bytes that follow in the Vendor Device Path node.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Vendor-assigned GUID that defines the data that follows.\r
///\r
- EFI_GUID Guid;\r
+ EFI_GUID Guid;\r
///\r
/// Vendor-defined variable size data.\r
///\r
///\r
/// Controller Device Path SubType.\r
///\r
-#define HW_CONTROLLER_DP 0x05\r
+#define HW_CONTROLLER_DP 0x05\r
\r
///\r
/// Controller Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Controller number.\r
///\r
- UINT32 ControllerNumber;\r
+ UINT32 ControllerNumber;\r
} CONTROLLER_DEVICE_PATH;\r
\r
///\r
/// BMC Device Path SubType.\r
///\r
-#define HW_BMC_DP 0x06\r
+#define HW_BMC_DP 0x06\r
\r
///\r
/// BMC Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Interface Type.\r
///\r
- UINT8 InterfaceType;\r
+ UINT8 InterfaceType;\r
///\r
/// Base Address.\r
///\r
- UINT8 BaseAddress[8];\r
+ UINT8 BaseAddress[8];\r
} BMC_DEVICE_PATH;\r
\r
///\r
/// ACPI Device Paths.\r
///\r
-#define ACPI_DEVICE_PATH 0x02\r
+#define ACPI_DEVICE_PATH 0x02\r
\r
///\r
/// ACPI Device Path SubType.\r
///\r
-#define ACPI_DP 0x01\r
+#define ACPI_DP 0x01\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Device's PnP hardware ID stored in a numeric 32-bit\r
/// compressed EISA-type ID. This value must match the\r
/// corresponding _HID in the ACPI name space.\r
///\r
- UINT32 HID;\r
+ UINT32 HID;\r
///\r
/// Unique ID that is required by ACPI if two devices have the\r
/// same _HID. This value must also match the corresponding\r
/// numeric value type of _UID is supported. Thus, strings must\r
/// not be used for the _UID in the ACPI name space.\r
///\r
- UINT32 UID;\r
+ UINT32 UID;\r
} ACPI_HID_DEVICE_PATH;\r
\r
///\r
/// Expanded ACPI Device Path SubType.\r
///\r
-#define ACPI_EXTENDED_DP 0x02\r
+#define ACPI_EXTENDED_DP 0x02\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Device's PnP hardware ID stored in a numeric 32-bit\r
/// compressed EISA-type ID. This value must match the\r
/// corresponding _HID in the ACPI name space.\r
///\r
- UINT32 HID;\r
+ UINT32 HID;\r
///\r
/// Unique ID that is required by ACPI if two devices have the\r
/// same _HID. This value must also match the corresponding\r
/// _UID/_HID pair in the ACPI name space.\r
///\r
- UINT32 UID;\r
+ UINT32 UID;\r
///\r
/// Device's compatible PnP hardware ID stored in a numeric\r
/// 32-bit compressed EISA-type ID. This value must match at\r
/// least one of the compatible device IDs returned by the\r
/// corresponding _CID in the ACPI name space.\r
///\r
- UINT32 CID;\r
+ UINT32 CID;\r
///\r
/// Optional variable length _HIDSTR.\r
/// Optional variable length _UIDSTR.\r
// bits[31:16] - binary number\r
// Compressed ASCII is 5 bits per character 0b00001 = 'A' 0b11010 = 'Z'\r
//\r
-#define PNP_EISA_ID_CONST 0x41d0\r
-#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16))\r
-#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))\r
-#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))\r
+#define PNP_EISA_ID_CONST 0x41d0\r
+#define EISA_ID(_Name, _Num) ((UINT32)((_Name) | (_Num) << 16))\r
+#define EISA_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))\r
+#define EFI_PNP_ID(_PNPId) (EISA_ID(PNP_EISA_ID_CONST, (_PNPId)))\r
\r
-#define PNP_EISA_ID_MASK 0xffff\r
-#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16)\r
+#define PNP_EISA_ID_MASK 0xffff\r
+#define EISA_ID_TO_NUM(_Id) ((_Id) >> 16)\r
\r
///\r
/// ACPI _ADR Device Path SubType.\r
///\r
-#define ACPI_ADR_DP 0x03\r
+#define ACPI_ADR_DP 0x03\r
\r
///\r
/// The _ADR device path is used to contain video output device attributes to support the Graphics\r
/// devices are displaying the same output.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// _ADR value. For video output devices the value of this\r
/// field comes from Table B-2 of the ACPI 3.0 specification. At\r
/// least one _ADR value is required.\r
///\r
- UINT32 ADR;\r
+ UINT32 ADR;\r
//\r
// This device path may optionally contain more than one _ADR entry.\r
//\r
///\r
/// ACPI NVDIMM Device Path SubType.\r
///\r
-#define ACPI_NVDIMM_DP 0x04\r
+#define ACPI_NVDIMM_DP 0x04\r
///\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// NFIT Device Handle, the _ADR of the NVDIMM device.\r
/// The value of this field comes from Section 9.20.3 of the ACPI 6.2A specification.\r
///\r
- UINT32 NFITDeviceHandle;\r
+ UINT32 NFITDeviceHandle;\r
} ACPI_NVDIMM_DEVICE_PATH;\r
\r
#define ACPI_ADR_DISPLAY_TYPE_OTHER 0\r
/// system. This Device Path can describe physical messaging information like SCSI ID, or abstract\r
/// information like networking protocol IP addresses.\r
///\r
-#define MESSAGING_DEVICE_PATH 0x03\r
+#define MESSAGING_DEVICE_PATH 0x03\r
\r
///\r
/// ATAPI Device Path SubType\r
///\r
-#define MSG_ATAPI_DP 0x01\r
+#define MSG_ATAPI_DP 0x01\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Set to zero for primary, or one for secondary.\r
///\r
- UINT8 PrimarySecondary;\r
+ UINT8 PrimarySecondary;\r
///\r
/// Set to zero for master, or one for slave mode.\r
///\r
- UINT8 SlaveMaster;\r
+ UINT8 SlaveMaster;\r
///\r
/// Logical Unit Number.\r
///\r
- UINT16 Lun;\r
+ UINT16 Lun;\r
} ATAPI_DEVICE_PATH;\r
\r
///\r
/// SCSI Device Path SubType.\r
///\r
-#define MSG_SCSI_DP 0x02\r
+#define MSG_SCSI_DP 0x02\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Target ID on the SCSI bus (PUN).\r
///\r
- UINT16 Pun;\r
+ UINT16 Pun;\r
///\r
/// Logical Unit Number (LUN).\r
///\r
- UINT16 Lun;\r
+ UINT16 Lun;\r
} SCSI_DEVICE_PATH;\r
\r
///\r
/// Fibre Channel SubType.\r
///\r
-#define MSG_FIBRECHANNEL_DP 0x03\r
+#define MSG_FIBRECHANNEL_DP 0x03\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Reserved for the future.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
///\r
/// Fibre Channel World Wide Number.\r
///\r
- UINT64 WWN;\r
+ UINT64 WWN;\r
///\r
/// Fibre Channel Logical Unit Number.\r
///\r
- UINT64 Lun;\r
+ UINT64 Lun;\r
} FIBRECHANNEL_DEVICE_PATH;\r
\r
///\r
/// Fibre Channel Ex SubType.\r
///\r
-#define MSG_FIBRECHANNELEX_DP 0x15\r
+#define MSG_FIBRECHANNELEX_DP 0x15\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Reserved for the future.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
///\r
/// 8 byte array containing Fibre Channel End Device Port Name.\r
///\r
- UINT8 WWN[8];\r
+ UINT8 WWN[8];\r
///\r
/// 8 byte array containing Fibre Channel Logical Unit Number.\r
///\r
- UINT8 Lun[8];\r
+ UINT8 Lun[8];\r
} FIBRECHANNELEX_DEVICE_PATH;\r
\r
///\r
/// 1394 Device Path SubType\r
///\r
-#define MSG_1394_DP 0x04\r
+#define MSG_1394_DP 0x04\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Reserved for the future.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
///\r
/// 1394 Global Unique ID (GUID).\r
///\r
- UINT64 Guid;\r
+ UINT64 Guid;\r
} F1394_DEVICE_PATH;\r
\r
///\r
/// USB Device Path SubType.\r
///\r
-#define MSG_USB_DP 0x05\r
+#define MSG_USB_DP 0x05\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// USB Parent Port Number.\r
///\r
- UINT8 ParentPortNumber;\r
+ UINT8 ParentPortNumber;\r
///\r
/// USB Interface Number.\r
///\r
- UINT8 InterfaceNumber;\r
+ UINT8 InterfaceNumber;\r
} USB_DEVICE_PATH;\r
\r
///\r
/// USB Class Device Path SubType.\r
///\r
-#define MSG_USB_CLASS_DP 0x0f\r
+#define MSG_USB_CLASS_DP 0x0f\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Vendor ID assigned by USB-IF. A value of 0xFFFF will\r
/// match any Vendor ID.\r
///\r
- UINT16 VendorId;\r
+ UINT16 VendorId;\r
///\r
/// Product ID assigned by USB-IF. A value of 0xFFFF will\r
/// match any Product ID.\r
///\r
- UINT16 ProductId;\r
+ UINT16 ProductId;\r
///\r
/// The class code assigned by the USB-IF. A value of 0xFF\r
/// will match any class code.\r
///\r
- UINT8 DeviceClass;\r
+ UINT8 DeviceClass;\r
///\r
/// The subclass code assigned by the USB-IF. A value of\r
/// 0xFF will match any subclass code.\r
///\r
- UINT8 DeviceSubClass;\r
+ UINT8 DeviceSubClass;\r
///\r
/// The protocol code assigned by the USB-IF. A value of\r
/// 0xFF will match any protocol code.\r
///\r
- UINT8 DeviceProtocol;\r
+ UINT8 DeviceProtocol;\r
} USB_CLASS_DEVICE_PATH;\r
\r
///\r
/// USB WWID Device Path SubType.\r
///\r
-#define MSG_USB_WWID_DP 0x10\r
+#define MSG_USB_WWID_DP 0x10\r
\r
///\r
/// This device path describes a USB device using its serial number.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// USB interface number.\r
///\r
- UINT16 InterfaceNumber;\r
+ UINT16 InterfaceNumber;\r
///\r
/// USB vendor id of the device.\r
///\r
- UINT16 VendorId;\r
+ UINT16 VendorId;\r
///\r
/// USB product id of the device.\r
///\r
- UINT16 ProductId;\r
+ UINT16 ProductId;\r
///\r
/// Last 64-or-fewer UTF-16 characters of the USB\r
/// serial number. The length of the string is\r
///\r
#define MSG_DEVICE_LOGICAL_UNIT_DP 0x11\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Logical Unit Number for the interface.\r
///\r
- UINT8 Lun;\r
+ UINT8 Lun;\r
} DEVICE_LOGICAL_UNIT_DEVICE_PATH;\r
\r
///\r
/// SATA Device Path SubType.\r
///\r
-#define MSG_SATA_DP 0x12\r
+#define MSG_SATA_DP 0x12\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// The HBA port number that facilitates the connection to the\r
/// device or a port multiplier. The value 0xFFFF is reserved.\r
///\r
- UINT16 HBAPortNumber;\r
+ UINT16 HBAPortNumber;\r
///\r
/// The Port multiplier port number that facilitates the connection\r
/// to the device. Must be set to 0xFFFF if the device is directly\r
/// connected to the HBA.\r
///\r
- UINT16 PortMultiplierPortNumber;\r
+ UINT16 PortMultiplierPortNumber;\r
///\r
/// Logical Unit Number.\r
///\r
- UINT16 Lun;\r
+ UINT16 Lun;\r
} SATA_DEVICE_PATH;\r
\r
///\r
/// Flag for if the device is directly connected to the HBA.\r
///\r
-#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000\r
+#define SATA_HBA_DIRECT_CONNECT_FLAG 0x8000\r
\r
///\r
/// I2O Device Path SubType.\r
///\r
-#define MSG_I2O_DP 0x06\r
+#define MSG_I2O_DP 0x06\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Target ID (TID) for a device.\r
///\r
- UINT32 Tid;\r
+ UINT32 Tid;\r
} I2O_DEVICE_PATH;\r
\r
///\r
/// MAC Address Device Path SubType.\r
///\r
-#define MSG_MAC_ADDR_DP 0x0b\r
+#define MSG_MAC_ADDR_DP 0x0b\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// The MAC address for a network interface padded with 0s.\r
///\r
- EFI_MAC_ADDRESS MacAddress;\r
+ EFI_MAC_ADDRESS MacAddress;\r
///\r
/// Network interface type(i.e. 802.3, FDDI).\r
///\r
- UINT8 IfType;\r
+ UINT8 IfType;\r
} MAC_ADDR_DEVICE_PATH;\r
\r
///\r
/// IPv4 Device Path SubType\r
///\r
-#define MSG_IPv4_DP 0x0c\r
+#define MSG_IPv4_DP 0x0c\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// The local IPv4 address.\r
///\r
- EFI_IPv4_ADDRESS LocalIpAddress;\r
+ EFI_IPv4_ADDRESS LocalIpAddress;\r
///\r
/// The remote IPv4 address.\r
///\r
- EFI_IPv4_ADDRESS RemoteIpAddress;\r
+ EFI_IPv4_ADDRESS RemoteIpAddress;\r
///\r
/// The local port number.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// The remote port number.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
///\r
/// The network protocol(i.e. UDP, TCP).\r
///\r
- UINT16 Protocol;\r
+ UINT16 Protocol;\r
///\r
/// 0x00 - The Source IP Address was assigned though DHCP.\r
/// 0x01 - The Source IP Address is statically bound.\r
///\r
- BOOLEAN StaticIpAddress;\r
+ BOOLEAN StaticIpAddress;\r
///\r
/// The gateway IP address\r
///\r
- EFI_IPv4_ADDRESS GatewayIpAddress;\r
+ EFI_IPv4_ADDRESS GatewayIpAddress;\r
///\r
/// The subnet mask\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
} IPv4_DEVICE_PATH;\r
\r
///\r
/// IPv6 Device Path SubType.\r
///\r
-#define MSG_IPv6_DP 0x0d\r
+#define MSG_IPv6_DP 0x0d\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// The local IPv6 address.\r
///\r
- EFI_IPv6_ADDRESS LocalIpAddress;\r
+ EFI_IPv6_ADDRESS LocalIpAddress;\r
///\r
/// The remote IPv6 address.\r
///\r
- EFI_IPv6_ADDRESS RemoteIpAddress;\r
+ EFI_IPv6_ADDRESS RemoteIpAddress;\r
///\r
/// The local port number.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// The remote port number.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
///\r
/// The network protocol(i.e. UDP, TCP).\r
///\r
- UINT16 Protocol;\r
+ UINT16 Protocol;\r
///\r
/// 0x00 - The Local IP Address was manually configured.\r
/// 0x01 - The Local IP Address is assigned through IPv6\r
/// 0x02 - The Local IP Address is assigned through IPv6\r
/// stateful configuration.\r
///\r
- UINT8 IpAddressOrigin;\r
+ UINT8 IpAddressOrigin;\r
///\r
/// The prefix length\r
///\r
- UINT8 PrefixLength;\r
+ UINT8 PrefixLength;\r
///\r
/// The gateway IP address\r
///\r
- EFI_IPv6_ADDRESS GatewayIpAddress;\r
+ EFI_IPv6_ADDRESS GatewayIpAddress;\r
} IPv6_DEVICE_PATH;\r
\r
///\r
/// InfiniBand Device Path SubType.\r
///\r
-#define MSG_INFINIBAND_DP 0x09\r
+#define MSG_INFINIBAND_DP 0x09\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Flags to help identify/manage InfiniBand device path elements:\r
/// Bit 0 - IOC/Service (0b = IOC, 1b = Service).\r
/// Bit 4 - Network Protocol.\r
/// All other bits are reserved.\r
///\r
- UINT32 ResourceFlags;\r
+ UINT32 ResourceFlags;\r
///\r
/// 128-bit Global Identifier for remote fabric port.\r
///\r
- UINT8 PortGid[16];\r
+ UINT8 PortGid[16];\r
///\r
/// 64-bit unique identifier to remote IOC or server process.\r
/// Interpretation of field specified by Resource Flags (bit 0).\r
///\r
- UINT64 ServiceId;\r
+ UINT64 ServiceId;\r
///\r
/// 64-bit persistent ID of remote IOC port.\r
///\r
- UINT64 TargetPortId;\r
+ UINT64 TargetPortId;\r
///\r
/// 64-bit persistent ID of remote device.\r
///\r
- UINT64 DeviceId;\r
+ UINT64 DeviceId;\r
} INFINIBAND_DEVICE_PATH;\r
\r
#define INFINIBAND_RESOURCE_FLAG_IOC_SERVICE 0x01\r
///\r
/// UART Device Path SubType.\r
///\r
-#define MSG_UART_DP 0x0e\r
+#define MSG_UART_DP 0x0e\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Reserved.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
///\r
/// The baud rate setting for the UART style device. A value of 0\r
/// means that the device's default baud rate will be used.\r
///\r
- UINT64 BaudRate;\r
+ UINT64 BaudRate;\r
///\r
/// The number of data bits for the UART style device. A value\r
/// of 0 means that the device's default number of data bits will be used.\r
///\r
- UINT8 DataBits;\r
+ UINT8 DataBits;\r
///\r
/// The parity setting for the UART style device.\r
/// Parity 0x00 - Default Parity.\r
/// Parity 0x04 - Mark Parity.\r
/// Parity 0x05 - Space Parity.\r
///\r
- UINT8 Parity;\r
+ UINT8 Parity;\r
///\r
/// The number of stop bits for the UART style device.\r
/// Stop Bits 0x00 - Default Stop Bits.\r
/// Stop Bits 0x02 - 1.5 Stop Bits.\r
/// Stop Bits 0x03 - 2 Stop Bits.\r
///\r
- UINT8 StopBits;\r
+ UINT8 StopBits;\r
} UART_DEVICE_PATH;\r
\r
///\r
/// NVDIMM Namespace Device Path SubType.\r
///\r
-#define NVDIMM_NAMESPACE_DP 0x20\r
+#define NVDIMM_NAMESPACE_DP 0x20\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Namespace unique label identifier UUID.\r
///\r
- EFI_GUID Uuid;\r
+ EFI_GUID Uuid;\r
} NVDIMM_NAMESPACE_DEVICE_PATH;\r
\r
//\r
// Use VENDOR_DEVICE_PATH struct\r
//\r
-#define MSG_VENDOR_DP 0x0a\r
-typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH;\r
+#define MSG_VENDOR_DP 0x0a\r
+typedef VENDOR_DEVICE_PATH VENDOR_DEFINED_DEVICE_PATH;\r
\r
-#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID\r
-#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID\r
-#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID\r
-#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID\r
+#define DEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID\r
+#define DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID\r
+#define DEVICE_PATH_MESSAGING_VT_100_PLUS EFI_VT_100_PLUS_GUID\r
+#define DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID\r
\r
///\r
/// A new device path node is defined to declare flow control characteristics.\r
/// UART Flow Control Messaging Device Path\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// DEVICE_PATH_MESSAGING_UART_FLOW_CONTROL GUID.\r
///\r
- EFI_GUID Guid;\r
+ EFI_GUID Guid;\r
///\r
/// Bitmap of supported flow control types.\r
/// Bit 0 set indicates hardware flow control.\r
/// Bit 1 set indicates Xon/Xoff flow control.\r
/// All other bits are reserved and are clear.\r
///\r
- UINT32 FlowControlMap;\r
+ UINT32 FlowControlMap;\r
} UART_FLOW_CONTROL_DEVICE_PATH;\r
\r
-#define UART_FLOW_CONTROL_HARDWARE 0x00000001\r
-#define UART_FLOW_CONTROL_XON_XOFF 0x00000010\r
+#define UART_FLOW_CONTROL_HARDWARE 0x00000001\r
+#define UART_FLOW_CONTROL_XON_XOFF 0x00000010\r
\r
-#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID\r
+#define DEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID\r
///\r
/// Serial Attached SCSI (SAS) Device Path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// DEVICE_PATH_MESSAGING_SAS GUID.\r
///\r
- EFI_GUID Guid;\r
+ EFI_GUID Guid;\r
///\r
/// Reserved for future use.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
///\r
/// SAS Address for Serial Attached SCSI Target.\r
///\r
- UINT64 SasAddress;\r
+ UINT64 SasAddress;\r
///\r
/// SAS Logical Unit Number.\r
///\r
- UINT64 Lun;\r
+ UINT64 Lun;\r
///\r
/// More Information about the device and its interconnect.\r
///\r
- UINT16 DeviceTopology;\r
+ UINT16 DeviceTopology;\r
///\r
/// Relative Target Port (RTP).\r
///\r
- UINT16 RelativeTargetPort;\r
+ UINT16 RelativeTargetPort;\r
} SAS_DEVICE_PATH;\r
\r
///\r
/// Serial Attached SCSI (SAS) Ex Device Path SubType\r
///\r
-#define MSG_SASEX_DP 0x16\r
+#define MSG_SASEX_DP 0x16\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// 8-byte array of the SAS Address for Serial Attached SCSI Target Port.\r
///\r
- UINT8 SasAddress[8];\r
+ UINT8 SasAddress[8];\r
///\r
/// 8-byte array of the SAS Logical Unit Number.\r
///\r
- UINT8 Lun[8];\r
+ UINT8 Lun[8];\r
///\r
/// More Information about the device and its interconnect.\r
///\r
- UINT16 DeviceTopology;\r
+ UINT16 DeviceTopology;\r
///\r
/// Relative Target Port (RTP).\r
///\r
- UINT16 RelativeTargetPort;\r
+ UINT16 RelativeTargetPort;\r
} SASEX_DEVICE_PATH;\r
\r
///\r
/// NvmExpress Namespace Device Path SubType.\r
///\r
-#define MSG_NVME_NAMESPACE_DP 0x17\r
+#define MSG_NVME_NAMESPACE_DP 0x17\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT32 NamespaceId;\r
- UINT64 NamespaceUuid;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT32 NamespaceId;\r
+ UINT64 NamespaceUuid;\r
} NVME_NAMESPACE_DEVICE_PATH;\r
\r
///\r
/// DNS Device Path SubType\r
///\r
-#define MSG_DNS_DP 0x1F\r
+#define MSG_DNS_DP 0x1F\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Indicates the DNS server address is IPv4 or IPv6 address.\r
///\r
- UINT8 IsIPv6;\r
+ UINT8 IsIPv6;\r
///\r
/// Instance of the DNS server address.\r
///\r
- EFI_IP_ADDRESS DnsServerIp[];\r
+ EFI_IP_ADDRESS DnsServerIp[];\r
} DNS_DEVICE_PATH;\r
\r
///\r
/// Uniform Resource Identifiers (URI) Device Path SubType\r
///\r
-#define MSG_URI_DP 0x18\r
+#define MSG_URI_DP 0x18\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Instance of the URI pursuant to RFC 3986.\r
///\r
- CHAR8 Uri[];\r
+ CHAR8 Uri[];\r
} URI_DEVICE_PATH;\r
\r
///\r
/// Universal Flash Storage (UFS) Device Path SubType.\r
///\r
-#define MSG_UFS_DP 0x19\r
+#define MSG_UFS_DP 0x19\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Target ID on the UFS bus (PUN).\r
///\r
- UINT8 Pun;\r
+ UINT8 Pun;\r
///\r
/// Logical Unit Number (LUN).\r
///\r
- UINT8 Lun;\r
+ UINT8 Lun;\r
} UFS_DEVICE_PATH;\r
\r
///\r
/// SD (Secure Digital) Device Path SubType.\r
///\r
-#define MSG_SD_DP 0x1A\r
+#define MSG_SD_DP 0x1A\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT8 SlotNumber;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT8 SlotNumber;\r
} SD_DEVICE_PATH;\r
\r
///\r
/// EMMC (Embedded MMC) Device Path SubType.\r
///\r
-#define MSG_EMMC_DP 0x1D\r
+#define MSG_EMMC_DP 0x1D\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT8 SlotNumber;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT8 SlotNumber;\r
} EMMC_DEVICE_PATH;\r
\r
///\r
/// iSCSI Device Path SubType\r
///\r
-#define MSG_ISCSI_DP 0x13\r
+#define MSG_ISCSI_DP 0x13\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Network Protocol (0 = TCP, 1+ = reserved).\r
///\r
- UINT16 NetworkProtocol;\r
+ UINT16 NetworkProtocol;\r
///\r
/// iSCSI Login Options.\r
///\r
- UINT16 LoginOption;\r
+ UINT16 LoginOption;\r
///\r
/// iSCSI Logical Unit Number.\r
///\r
- UINT64 Lun;\r
+ UINT64 Lun;\r
///\r
/// iSCSI Target Portal group tag the initiator intends\r
/// to establish a session with.\r
///\r
- UINT16 TargetPortalGroupTag;\r
+ UINT16 TargetPortalGroupTag;\r
///\r
/// iSCSI NodeTarget Name. The length of the name\r
/// is determined by subtracting the offset of this field from Length.\r
/// CHAR8 iSCSI Target Name.\r
} ISCSI_DEVICE_PATH;\r
\r
-#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000\r
-#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002\r
-#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000\r
-#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008\r
-#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000\r
-#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000\r
-#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000\r
-#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000\r
+#define ISCSI_LOGIN_OPTION_NO_HEADER_DIGEST 0x0000\r
+#define ISCSI_LOGIN_OPTION_HEADER_DIGEST_USING_CRC32C 0x0002\r
+#define ISCSI_LOGIN_OPTION_NO_DATA_DIGEST 0x0000\r
+#define ISCSI_LOGIN_OPTION_DATA_DIGEST_USING_CRC32C 0x0008\r
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_CHAP 0x0000\r
+#define ISCSI_LOGIN_OPTION_AUTHMETHOD_NON 0x1000\r
+#define ISCSI_LOGIN_OPTION_CHAP_BI 0x0000\r
+#define ISCSI_LOGIN_OPTION_CHAP_UNI 0x2000\r
\r
///\r
/// VLAN Device Path SubType.\r
///\r
-#define MSG_VLAN_DP 0x14\r
+#define MSG_VLAN_DP 0x14\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// VLAN identifier (0-4094).\r
///\r
- UINT16 VlanId;\r
+ UINT16 VlanId;\r
} VLAN_DEVICE_PATH;\r
\r
///\r
/// Bluetooth Device Path SubType.\r
///\r
-#define MSG_BLUETOOTH_DP 0x1b\r
+#define MSG_BLUETOOTH_DP 0x1b\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// 48bit Bluetooth device address.\r
///\r
- BLUETOOTH_ADDRESS BD_ADDR;\r
+ BLUETOOTH_ADDRESS BD_ADDR;\r
} BLUETOOTH_DEVICE_PATH;\r
\r
///\r
/// Wi-Fi Device Path SubType.\r
///\r
-#define MSG_WIFI_DP 0x1C\r
+#define MSG_WIFI_DP 0x1C\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Service set identifier. A 32-byte octets string.\r
///\r
- UINT8 SSId[32];\r
+ UINT8 SSId[32];\r
} WIFI_DEVICE_PATH;\r
\r
///\r
/// Bluetooth LE Device Path SubType.\r
///\r
-#define MSG_BLUETOOTH_LE_DP 0x1E\r
+#define MSG_BLUETOOTH_LE_DP 0x1E\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- BLUETOOTH_LE_ADDRESS Address;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ BLUETOOTH_LE_ADDRESS Address;\r
} BLUETOOTH_LE_DEVICE_PATH;\r
\r
//\r
// Media Device Path\r
//\r
-#define MEDIA_DEVICE_PATH 0x04\r
+#define MEDIA_DEVICE_PATH 0x04\r
\r
///\r
/// Hard Drive Media Device Path SubType.\r
///\r
-#define MEDIA_HARDDRIVE_DP 0x01\r
+#define MEDIA_HARDDRIVE_DP 0x01\r
\r
///\r
/// The Hard Drive Media Device Path is used to represent a partition on a hard drive.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Describes the entry in a partition table, starting with entry 1.\r
/// Partition number zero represents the entire device. Valid\r
/// partition numbers for a MBR partition are [1, 4]. Valid\r
/// partition numbers for a GPT partition are [1, NumberOfPartitionEntries].\r
///\r
- UINT32 PartitionNumber;\r
+ UINT32 PartitionNumber;\r
///\r
/// Starting LBA of the partition on the hard drive.\r
///\r
- UINT64 PartitionStart;\r
+ UINT64 PartitionStart;\r
///\r
/// Size of the partition in units of Logical Blocks.\r
///\r
- UINT64 PartitionSize;\r
+ UINT64 PartitionSize;\r
///\r
/// Signature unique to this partition:\r
/// If SignatureType is 0, this field has to be initialized with 16 zeros.\r
/// The other 12 bytes are initialized with zeros.\r
/// If SignatureType is 2, this field contains a 16 byte signature.\r
///\r
- UINT8 Signature[16];\r
+ UINT8 Signature[16];\r
///\r
/// Partition Format: (Unused values reserved).\r
/// 0x01 - PC-AT compatible legacy MBR.\r
/// 0x02 - GUID Partition Table.\r
///\r
- UINT8 MBRType;\r
+ UINT8 MBRType;\r
///\r
/// Type of Disk Signature: (Unused values reserved).\r
/// 0x00 - No Disk Signature.\r
/// 0x01 - 32-bit signature from address 0x1b8 of the type 0x01 MBR.\r
/// 0x02 - GUID signature.\r
///\r
- UINT8 SignatureType;\r
+ UINT8 SignatureType;\r
} HARDDRIVE_DEVICE_PATH;\r
\r
-#define MBR_TYPE_PCAT 0x01\r
-#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02\r
+#define MBR_TYPE_PCAT 0x01\r
+#define MBR_TYPE_EFI_PARTITION_TABLE_HEADER 0x02\r
\r
-#define NO_DISK_SIGNATURE 0x00\r
-#define SIGNATURE_TYPE_MBR 0x01\r
-#define SIGNATURE_TYPE_GUID 0x02\r
+#define NO_DISK_SIGNATURE 0x00\r
+#define SIGNATURE_TYPE_MBR 0x01\r
+#define SIGNATURE_TYPE_GUID 0x02\r
\r
///\r
/// CD-ROM Media Device Path SubType.\r
///\r
-#define MEDIA_CDROM_DP 0x02\r
+#define MEDIA_CDROM_DP 0x02\r
\r
///\r
/// The CD-ROM Media Device Path is used to define a system partition that exists on a CD-ROM.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Boot Entry number from the Boot Catalog. The Initial/Default entry is defined as zero.\r
///\r
- UINT32 BootEntry;\r
+ UINT32 BootEntry;\r
///\r
/// Starting RBA of the partition on the medium. CD-ROMs use Relative logical Block Addressing.\r
///\r
- UINT64 PartitionStart;\r
+ UINT64 PartitionStart;\r
///\r
/// Size of the partition in units of Blocks, also called Sectors.\r
///\r
- UINT64 PartitionSize;\r
+ UINT64 PartitionSize;\r
} CDROM_DEVICE_PATH;\r
\r
//\r
// Use VENDOR_DEVICE_PATH struct\r
//\r
-#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype.\r
+#define MEDIA_VENDOR_DP 0x03 ///< Media vendor device path subtype.\r
\r
///\r
/// File Path Media Device Path SubType\r
///\r
-#define MEDIA_FILEPATH_DP 0x04\r
+#define MEDIA_FILEPATH_DP 0x04\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// A NULL-terminated Path string including directory and file names.\r
///\r
- CHAR16 PathName[1];\r
+ CHAR16 PathName[1];\r
} FILEPATH_DEVICE_PATH;\r
\r
#define SIZE_OF_FILEPATH_DEVICE_PATH OFFSET_OF(FILEPATH_DEVICE_PATH,PathName)\r
///\r
/// Media Protocol Device Path SubType.\r
///\r
-#define MEDIA_PROTOCOL_DP 0x05\r
+#define MEDIA_PROTOCOL_DP 0x05\r
\r
///\r
/// The Media Protocol Device Path is used to denote the protocol that is being\r
/// Many protocols are inherent to the style of device path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// The ID of the protocol.\r
///\r
- EFI_GUID Protocol;\r
+ EFI_GUID Protocol;\r
} MEDIA_PROTOCOL_DEVICE_PATH;\r
\r
///\r
/// PIWG Firmware File SubType.\r
///\r
-#define MEDIA_PIWG_FW_FILE_DP 0x06\r
+#define MEDIA_PIWG_FW_FILE_DP 0x06\r
\r
///\r
/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware file.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Firmware file name\r
///\r
- EFI_GUID FvFileName;\r
+ EFI_GUID FvFileName;\r
} MEDIA_FW_VOL_FILEPATH_DEVICE_PATH;\r
\r
///\r
/// PIWG Firmware Volume Device Path SubType.\r
///\r
-#define MEDIA_PIWG_FW_VOL_DP 0x07\r
+#define MEDIA_PIWG_FW_VOL_DP 0x07\r
\r
///\r
/// This device path is used by systems implementing the UEFI PI Specification 1.0 to describe a firmware volume.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Firmware volume name.\r
///\r
- EFI_GUID FvName;\r
+ EFI_GUID FvName;\r
} MEDIA_FW_VOL_DEVICE_PATH;\r
\r
///\r
/// Media relative offset range device path.\r
///\r
-#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08\r
+#define MEDIA_RELATIVE_OFFSET_RANGE_DP 0x08\r
\r
///\r
/// Used to describe the offset range of media relative.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT32 Reserved;\r
- UINT64 StartingOffset;\r
- UINT64 EndingOffset;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT32 Reserved;\r
+ UINT64 StartingOffset;\r
+ UINT64 EndingOffset;\r
} MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH;\r
\r
///\r
/// This GUID defines a RAM Disk supporting a raw disk format in volatile memory.\r
///\r
-#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE\r
+#define EFI_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE\r
\r
-extern EFI_GUID gEfiVirtualDiskGuid;\r
+extern EFI_GUID gEfiVirtualDiskGuid;\r
\r
///\r
/// This GUID defines a RAM Disk supporting an ISO image in volatile memory.\r
///\r
-#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE\r
+#define EFI_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE\r
\r
-extern EFI_GUID gEfiVirtualCdGuid;\r
+extern EFI_GUID gEfiVirtualCdGuid;\r
\r
///\r
/// This GUID defines a RAM Disk supporting a raw disk format in persistent memory.\r
///\r
-#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT\r
+#define EFI_PERSISTENT_VIRTUAL_DISK_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT\r
\r
-extern EFI_GUID gEfiPersistentVirtualDiskGuid;\r
+extern EFI_GUID gEfiPersistentVirtualDiskGuid;\r
\r
///\r
/// This GUID defines a RAM Disk supporting an ISO image in persistent memory.\r
///\r
-#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT\r
+#define EFI_PERSISTENT_VIRTUAL_CD_GUID EFI_ACPI_6_0_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT\r
\r
-extern EFI_GUID gEfiPersistentVirtualCdGuid;\r
+extern EFI_GUID gEfiPersistentVirtualCdGuid;\r
\r
///\r
/// Media ram disk device path.\r
///\r
-#define MEDIA_RAM_DISK_DP 0x09\r
+#define MEDIA_RAM_DISK_DP 0x09\r
\r
///\r
/// Used to describe the ram disk device path.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Starting Memory Address.\r
///\r
- UINT32 StartingAddr[2];\r
+ UINT32 StartingAddr[2];\r
///\r
/// Ending Memory Address.\r
///\r
- UINT32 EndingAddr[2];\r
+ UINT32 EndingAddr[2];\r
///\r
/// GUID that defines the type of the RAM Disk.\r
///\r
- EFI_GUID TypeGuid;\r
+ EFI_GUID TypeGuid;\r
///\r
/// RAM Diskinstance number, if supported. The default value is zero.\r
///\r
- UINT16 Instance;\r
+ UINT16 Instance;\r
} MEDIA_RAM_DISK_DEVICE_PATH;\r
\r
///\r
/// BIOS Boot Specification Device Path.\r
///\r
-#define BBS_DEVICE_PATH 0x05\r
+#define BBS_DEVICE_PATH 0x05\r
\r
///\r
/// BIOS Boot Specification Device Path SubType.\r
///\r
-#define BBS_BBS_DP 0x01\r
+#define BBS_BBS_DP 0x01\r
\r
///\r
/// This Device Path is used to describe the booting of non-EFI-aware operating systems.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
///\r
/// Device Type as defined by the BIOS Boot Specification.\r
///\r
- UINT16 DeviceType;\r
+ UINT16 DeviceType;\r
///\r
/// Status Flags as defined by the BIOS Boot Specification.\r
///\r
- UINT16 StatusFlag;\r
+ UINT16 StatusFlag;\r
///\r
/// Null-terminated ASCII string that describes the boot device to a user.\r
///\r
- CHAR8 String[1];\r
+ CHAR8 String[1];\r
} BBS_BBS_DEVICE_PATH;\r
\r
//\r
// DeviceType definitions - from BBS specification\r
//\r
-#define BBS_TYPE_FLOPPY 0x01\r
-#define BBS_TYPE_HARDDRIVE 0x02\r
-#define BBS_TYPE_CDROM 0x03\r
-#define BBS_TYPE_PCMCIA 0x04\r
-#define BBS_TYPE_USB 0x05\r
-#define BBS_TYPE_EMBEDDED_NETWORK 0x06\r
-#define BBS_TYPE_BEV 0x80\r
-#define BBS_TYPE_UNKNOWN 0xFF\r
-\r
+#define BBS_TYPE_FLOPPY 0x01\r
+#define BBS_TYPE_HARDDRIVE 0x02\r
+#define BBS_TYPE_CDROM 0x03\r
+#define BBS_TYPE_PCMCIA 0x04\r
+#define BBS_TYPE_USB 0x05\r
+#define BBS_TYPE_EMBEDDED_NETWORK 0x06\r
+#define BBS_TYPE_BEV 0x80\r
+#define BBS_TYPE_UNKNOWN 0xFF\r
\r
///\r
/// Union of all possible Device Paths and pointers to Device Paths.\r
BBS_BBS_DEVICE_PATH Bbs;\r
} EFI_DEV_PATH;\r
\r
-\r
-\r
typedef union {\r
EFI_DEVICE_PATH_PROTOCOL *DevPath;\r
PCI_DEVICE_PATH *Pci;\r
\r
#pragma pack()\r
\r
-#define END_DEVICE_PATH_TYPE 0x7f\r
-#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF\r
-#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01\r
+#define END_DEVICE_PATH_TYPE 0x7f\r
+#define END_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF\r
+#define END_INSTANCE_DEVICE_PATH_SUBTYPE 0x01\r
\r
-extern EFI_GUID gEfiDevicePathProtocolGuid;\r
+extern EFI_GUID gEfiDevicePathProtocolGuid;\r
\r
#endif\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_NODE)(\r
IN CONST CHAR16 *TextDeviceNode\r
);\r
\r
-\r
/**\r
Convert text to the binary representation of a device node.\r
\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_PATH)(\r
IN CONST CHAR16 *TextDevicePath\r
);\r
/// This protocol converts text to device paths and device nodes.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_FROM_TEXT_NODE ConvertTextToDeviceNode;\r
- EFI_DEVICE_PATH_FROM_TEXT_PATH ConvertTextToDevicePath;\r
+ EFI_DEVICE_PATH_FROM_TEXT_NODE ConvertTextToDeviceNode;\r
+ EFI_DEVICE_PATH_FROM_TEXT_PATH ConvertTextToDevicePath;\r
} EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL;\r
\r
-extern EFI_GUID gEfiDevicePathFromTextProtocolGuid;\r
+extern EFI_GUID gEfiDevicePathFromTextProtocolGuid;\r
\r
#endif\r
\r
**/\r
typedef\r
-CHAR16*\r
+CHAR16 *\r
(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_NODE)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode,\r
IN BOOLEAN DisplayOnly,\r
\r
**/\r
typedef\r
-CHAR16*\r
+CHAR16 *\r
(EFIAPI *EFI_DEVICE_PATH_TO_TEXT_PATH)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
IN BOOLEAN DisplayOnly,\r
/// This protocol converts device paths and device nodes to text.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_TO_TEXT_NODE ConvertDeviceNodeToText;\r
- EFI_DEVICE_PATH_TO_TEXT_PATH ConvertDevicePathToText;\r
+ EFI_DEVICE_PATH_TO_TEXT_NODE ConvertDeviceNodeToText;\r
+ EFI_DEVICE_PATH_TO_TEXT_PATH ConvertDevicePathToText;\r
} EFI_DEVICE_PATH_TO_TEXT_PROTOCOL;\r
\r
-extern EFI_GUID gEfiDevicePathToTextProtocolGuid;\r
+extern EFI_GUID gEfiDevicePathToTextProtocolGuid;\r
\r
#endif\r
-\r
-\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
);\r
\r
-\r
/**\r
Create a duplicate of the specified path.\r
\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
);\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_PATH)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_NODE)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DeviceNode\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE)(\r
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathInstance,\r
OUT UINTN *DevicePathInstanceSize\r
\r
**/\r
typedef\r
-EFI_DEVICE_PATH_PROTOCOL*\r
+EFI_DEVICE_PATH_PROTOCOL *\r
(EFIAPI *EFI_DEVICE_PATH_UTILS_CREATE_NODE)(\r
IN UINT8 NodeType,\r
IN UINT8 NodeSubType,\r
IN UINT16 NodeLength\r
-);\r
+ );\r
\r
/**\r
Returns whether a device path is multi-instance.\r
/// This protocol is used to creates and manipulates device paths and device nodes.\r
///\r
typedef struct {\r
- EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize;\r
- EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH DuplicateDevicePath;\r
- EFI_DEVICE_PATH_UTILS_APPEND_PATH AppendDevicePath;\r
- EFI_DEVICE_PATH_UTILS_APPEND_NODE AppendDeviceNode;\r
- EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE AppendDevicePathInstance;\r
- EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE GetNextDevicePathInstance;\r
- EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE IsDevicePathMultiInstance;\r
- EFI_DEVICE_PATH_UTILS_CREATE_NODE CreateDeviceNode;\r
+ EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize;\r
+ EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH DuplicateDevicePath;\r
+ EFI_DEVICE_PATH_UTILS_APPEND_PATH AppendDevicePath;\r
+ EFI_DEVICE_PATH_UTILS_APPEND_NODE AppendDeviceNode;\r
+ EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE AppendDevicePathInstance;\r
+ EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE GetNextDevicePathInstance;\r
+ EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE IsDevicePathMultiInstance;\r
+ EFI_DEVICE_PATH_UTILS_CREATE_NODE CreateDeviceNode;\r
} EFI_DEVICE_PATH_UTILITIES_PROTOCOL;\r
\r
-extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid;\r
+extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_DHCP4_PROTOCOL EFI_DHCP4_PROTOCOL;\r
\r
-\r
#pragma pack(1)\r
typedef struct {\r
///\r
/// DHCP option code.\r
///\r
- UINT8 OpCode;\r
+ UINT8 OpCode;\r
///\r
/// Length of the DHCP option data. Not present if OpCode is 0 or 255.\r
///\r
- UINT8 Length;\r
+ UINT8 Length;\r
///\r
/// Start of the DHCP option data. Not present if OpCode is 0 or 255 or if Length is zero.\r
///\r
- UINT8 Data[1];\r
+ UINT8 Data[1];\r
} EFI_DHCP4_PACKET_OPTION;\r
#pragma pack()\r
\r
-\r
#pragma pack(1)\r
///\r
/// EFI_DHCP4_PACKET defines the format of DHCPv4 packets. See RFC 2131 for more information.\r
///\r
typedef struct {\r
- UINT8 OpCode;\r
- UINT8 HwType;\r
- UINT8 HwAddrLen;\r
- UINT8 Hops;\r
- UINT32 Xid;\r
- UINT16 Seconds;\r
- UINT16 Reserved;\r
- EFI_IPv4_ADDRESS ClientAddr; ///< Client IP address from client.\r
- EFI_IPv4_ADDRESS YourAddr; ///< Client IP address from server.\r
- EFI_IPv4_ADDRESS ServerAddr; ///< IP address of next server in bootstrap.\r
- EFI_IPv4_ADDRESS GatewayAddr; ///< Relay agent IP address.\r
- UINT8 ClientHwAddr[16]; ///< Client hardware address.\r
- CHAR8 ServerName[64];\r
- CHAR8 BootFileName[128];\r
-}EFI_DHCP4_HEADER;\r
+ UINT8 OpCode;\r
+ UINT8 HwType;\r
+ UINT8 HwAddrLen;\r
+ UINT8 Hops;\r
+ UINT32 Xid;\r
+ UINT16 Seconds;\r
+ UINT16 Reserved;\r
+ EFI_IPv4_ADDRESS ClientAddr; ///< Client IP address from client.\r
+ EFI_IPv4_ADDRESS YourAddr; ///< Client IP address from server.\r
+ EFI_IPv4_ADDRESS ServerAddr; ///< IP address of next server in bootstrap.\r
+ EFI_IPv4_ADDRESS GatewayAddr; ///< Relay agent IP address.\r
+ UINT8 ClientHwAddr[16]; ///< Client hardware address.\r
+ CHAR8 ServerName[64];\r
+ CHAR8 BootFileName[128];\r
+} EFI_DHCP4_HEADER;\r
#pragma pack()\r
\r
-\r
#pragma pack(1)\r
typedef struct {\r
///\r
/// Size of the EFI_DHCP4_PACKET buffer.\r
///\r
- UINT32 Size;\r
+ UINT32 Size;\r
///\r
/// Length of the EFI_DHCP4_PACKET from the first byte of the Header field\r
/// to the last byte of the Option[] field.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
\r
struct {\r
///\r
/// DHCP packet header.\r
///\r
- EFI_DHCP4_HEADER Header;\r
+ EFI_DHCP4_HEADER Header;\r
///\r
/// DHCP magik cookie in network byte order.\r
///\r
- UINT32 Magik;\r
+ UINT32 Magik;\r
///\r
/// Start of the DHCP packed option data.\r
///\r
- UINT8 Option[1];\r
+ UINT8 Option[1];\r
} Dhcp4;\r
} EFI_DHCP4_PACKET;\r
#pragma pack()\r
\r
-\r
typedef enum {\r
///\r
/// The EFI DHCPv4 Protocol driver is stopped.\r
///\r
- Dhcp4Stopped = 0x0,\r
+ Dhcp4Stopped = 0x0,\r
///\r
/// The EFI DHCPv4 Protocol driver is inactive.\r
///\r
- Dhcp4Init = 0x1,\r
+ Dhcp4Init = 0x1,\r
///\r
/// The EFI DHCPv4 Protocol driver is collecting DHCP offer packets from DHCP servers.\r
///\r
- Dhcp4Selecting = 0x2,\r
+ Dhcp4Selecting = 0x2,\r
///\r
/// The EFI DHCPv4 Protocol driver has sent the request to the DHCP server and is waiting for a response.\r
///\r
- Dhcp4Requesting = 0x3,\r
+ Dhcp4Requesting = 0x3,\r
///\r
/// The DHCP configuration has completed.\r
///\r
- Dhcp4Bound = 0x4,\r
+ Dhcp4Bound = 0x4,\r
///\r
/// The DHCP configuration is being renewed and another request has\r
/// been sent out, but it has not received a response from the server yet.\r
///\r
- Dhcp4Renewing = 0x5,\r
+ Dhcp4Renewing = 0x5,\r
///\r
/// The DHCP configuration has timed out and the EFI DHCPv4\r
/// Protocol driver is trying to extend the lease time.\r
///\r
- Dhcp4Rebinding = 0x6,\r
+ Dhcp4Rebinding = 0x6,\r
///\r
/// The EFI DHCPv4 Protocol driver was initialized with a previously\r
/// allocated or known IP address.\r
///\r
- Dhcp4InitReboot = 0x7,\r
+ Dhcp4InitReboot = 0x7,\r
///\r
/// The EFI DHCPv4 Protocol driver is seeking to reuse the previously\r
/// allocated IP address by sending a request to the DHCP server.\r
///\r
- Dhcp4Rebooting = 0x8\r
+ Dhcp4Rebooting = 0x8\r
} EFI_DHCP4_STATE;\r
\r
-\r
-typedef enum{\r
+typedef enum {\r
///\r
/// The packet to start the configuration sequence is about to be sent.\r
///\r
- Dhcp4SendDiscover = 0x01,\r
+ Dhcp4SendDiscover = 0x01,\r
///\r
/// A reply packet was just received.\r
///\r
- Dhcp4RcvdOffer = 0x02,\r
+ Dhcp4RcvdOffer = 0x02,\r
///\r
/// It is time for Dhcp4Callback to select an offer.\r
///\r
- Dhcp4SelectOffer = 0x03,\r
+ Dhcp4SelectOffer = 0x03,\r
///\r
/// A request packet is about to be sent.\r
///\r
- Dhcp4SendRequest = 0x04,\r
+ Dhcp4SendRequest = 0x04,\r
///\r
/// A DHCPACK packet was received and will be passed to Dhcp4Callback.\r
///\r
- Dhcp4RcvdAck = 0x05,\r
+ Dhcp4RcvdAck = 0x05,\r
///\r
/// A DHCPNAK packet was received and will be passed to Dhcp4Callback.\r
///\r
- Dhcp4RcvdNak = 0x06,\r
+ Dhcp4RcvdNak = 0x06,\r
///\r
/// A decline packet is about to be sent.\r
///\r
- Dhcp4SendDecline = 0x07,\r
+ Dhcp4SendDecline = 0x07,\r
///\r
/// The DHCP configuration process has completed. No packet is associated with this event.\r
///\r
/// It is time to enter the Dhcp4Renewing state and to contact the server\r
/// that originally issued the network address. No packet is associated with this event.\r
///\r
- Dhcp4EnterRenewing = 0x09,\r
+ Dhcp4EnterRenewing = 0x09,\r
///\r
/// It is time to enter the Dhcp4Rebinding state and to contact any server.\r
/// No packet is associated with this event.\r
/// the user released the configuration, or a DHCPNAK packet was received in\r
/// the Dhcp4Renewing or Dhcp4Rebinding state. No packet is associated with this event.\r
///\r
- Dhcp4AddressLost = 0x0b,\r
+ Dhcp4AddressLost = 0x0b,\r
///\r
/// The DHCP process failed because a DHCPNAK packet was received or the user\r
/// aborted the DHCP process at a time when the configuration was not available yet.\r
/// No packet is associated with this event.\r
///\r
- Dhcp4Fail = 0x0c\r
+ Dhcp4Fail = 0x0c\r
} EFI_DHCP4_EVENT;\r
\r
/**\r
/// event and waiting for a response during the Dhcp4RcvdOffer event.\r
/// Set to zero to use the default try counts and timeout values.\r
///\r
- UINT32 DiscoverTryCount;\r
+ UINT32 DiscoverTryCount;\r
///\r
/// The maximum amount of time (in seconds) to wait for returned packets in each\r
/// of the retries. Timeout values of zero will default to a timeout value\r
/// of one second. Set to NULL to use default timeout values.\r
///\r
- UINT32 *DiscoverTimeout;\r
+ UINT32 *DiscoverTimeout;\r
///\r
/// The number of times to try sending a packet during the Dhcp4SendRequest event\r
/// and waiting for a response during the Dhcp4RcvdAck event before accepting\r
/// failure. Set to zero to use the default try counts and timeout values.\r
///\r
- UINT32 RequestTryCount;\r
+ UINT32 RequestTryCount;\r
///\r
/// The maximum amount of time (in seconds) to wait for return packets in each of the retries.\r
/// Timeout values of zero will default to a timeout value of one second.\r
/// Set to NULL to use default timeout values.\r
///\r
- UINT32 *RequestTimeout;\r
+ UINT32 *RequestTimeout;\r
///\r
/// For a DHCPDISCOVER, setting this parameter to the previously allocated IP\r
/// address will cause the EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state.\r
/// For a DHCPINFORM this parameter should be set to the client network address\r
/// which was assigned to the client during a DHCPDISCOVER.\r
///\r
- EFI_IPv4_ADDRESS ClientAddress;\r
+ EFI_IPv4_ADDRESS ClientAddress;\r
///\r
/// The callback function to intercept various events that occurred in\r
/// the DHCP configuration process. Set to NULL to ignore all those events.\r
///\r
- EFI_DHCP4_CALLBACK Dhcp4Callback;\r
+ EFI_DHCP4_CALLBACK Dhcp4Callback;\r
///\r
/// The pointer to the context that will be passed to Dhcp4Callback when it is called.\r
///\r
- VOID *CallbackContext;\r
+ VOID *CallbackContext;\r
///\r
/// Number of DHCP options in the OptionList.\r
///\r
- UINT32 OptionCount;\r
+ UINT32 OptionCount;\r
///\r
/// List of DHCP options to be included in every packet that is sent during the\r
/// Dhcp4SendDiscover event. Pad options are appended automatically by DHCP driver\r
/// ignored by the driver. OptionList can be freed after EFI_DHCP4_PROTOCOL.Configure()\r
/// returns. Ignored if OptionCount is zero.\r
///\r
- EFI_DHCP4_PACKET_OPTION **OptionList;\r
+ EFI_DHCP4_PACKET_OPTION **OptionList;\r
} EFI_DHCP4_CONFIG_DATA;\r
\r
-\r
typedef struct {\r
///\r
/// The EFI DHCPv4 Protocol driver operating state.\r
///\r
- EFI_DHCP4_STATE State;\r
+ EFI_DHCP4_STATE State;\r
///\r
/// The configuration data of the current EFI DHCPv4 Protocol driver instance.\r
///\r
- EFI_DHCP4_CONFIG_DATA ConfigData;\r
+ EFI_DHCP4_CONFIG_DATA ConfigData;\r
///\r
/// The client IP address that was acquired from the DHCP server. If it is zero,\r
/// the DHCP acquisition has not completed yet and the following fields in this structure are undefined.\r
///\r
- EFI_IPv4_ADDRESS ClientAddress;\r
+ EFI_IPv4_ADDRESS ClientAddress;\r
///\r
/// The local hardware address.\r
///\r
- EFI_MAC_ADDRESS ClientMacAddress;\r
+ EFI_MAC_ADDRESS ClientMacAddress;\r
///\r
/// The server IP address that is providing the DHCP service to this client.\r
///\r
- EFI_IPv4_ADDRESS ServerAddress;\r
+ EFI_IPv4_ADDRESS ServerAddress;\r
///\r
/// The router IP address that was acquired from the DHCP server.\r
/// May be zero if the server does not offer this address.\r
///\r
- EFI_IPv4_ADDRESS RouterAddress;\r
+ EFI_IPv4_ADDRESS RouterAddress;\r
///\r
/// The subnet mask of the connected network that was acquired from the DHCP server.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// The lease time (in 1-second units) of the configured IP address.\r
/// The value 0xFFFFFFFF means that the lease time is infinite.\r
/// A default lease of 7 days is used if the DHCP server does not provide a value.\r
///\r
- UINT32 LeaseTime;\r
+ UINT32 LeaseTime;\r
///\r
/// The cached latest DHCPACK or DHCPNAK or BOOTP REPLY packet. May be NULL if no packet is cached.\r
///\r
- EFI_DHCP4_PACKET *ReplyPacket;\r
+ EFI_DHCP4_PACKET *ReplyPacket;\r
} EFI_DHCP4_MODE_DATA;\r
\r
-\r
typedef struct {\r
///\r
/// Alternate listening address. It can be a unicast, multicast, or broadcast address.\r
///\r
- EFI_IPv4_ADDRESS ListenAddress;\r
+ EFI_IPv4_ADDRESS ListenAddress;\r
///\r
/// The subnet mask of above listening unicast/broadcast IP address.\r
/// Ignored if ListenAddress is a multicast address.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// Alternate station source (or listening) port number.\r
/// If zero, then the default station port number (68) will be used.\r
///\r
- UINT16 ListenPort;\r
+ UINT16 ListenPort;\r
} EFI_DHCP4_LISTEN_POINT;\r
\r
-\r
typedef struct {\r
///\r
/// The completion status of transmitting and receiving.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// If not NULL, the event that will be signaled when the collection process\r
/// completes. If NULL, this function will busy-wait until the collection process competes.\r
///\r
- EFI_EVENT CompletionEvent;\r
+ EFI_EVENT CompletionEvent;\r
///\r
/// The pointer to the server IP address. This address may be a unicast, multicast, or broadcast address.\r
///\r
- EFI_IPv4_ADDRESS RemoteAddress;\r
+ EFI_IPv4_ADDRESS RemoteAddress;\r
///\r
/// The server listening port number. If zero, the default server listening port number (67) will be used.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
///\r
/// The pointer to the gateway address to override the existing setting.\r
///\r
- EFI_IPv4_ADDRESS GatewayAddress;\r
+ EFI_IPv4_ADDRESS GatewayAddress;\r
///\r
/// The number of entries in ListenPoints. If zero, the default station address and port number 68 are used.\r
///\r
- UINT32 ListenPointCount;\r
+ UINT32 ListenPointCount;\r
///\r
/// An array of station address and port number pairs that are used as receiving filters.\r
/// The first entry is also used as the source address and source port of the outgoing packet.\r
///\r
- EFI_DHCP4_LISTEN_POINT *ListenPoints;\r
+ EFI_DHCP4_LISTEN_POINT *ListenPoints;\r
///\r
/// The number of seconds to collect responses. Zero is invalid.\r
///\r
- UINT32 TimeoutValue;\r
+ UINT32 TimeoutValue;\r
///\r
/// The pointer to the packet to be transmitted.\r
///\r
- EFI_DHCP4_PACKET *Packet;\r
+ EFI_DHCP4_PACKET *Packet;\r
///\r
/// Number of received packets.\r
///\r
- UINT32 ResponseCount;\r
+ UINT32 ResponseCount;\r
///\r
/// The pointer to the allocated list of received packets.\r
///\r
- EFI_DHCP4_PACKET *ResponseList;\r
+ EFI_DHCP4_PACKET *ResponseList;\r
} EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN;\r
\r
-\r
/**\r
Returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol driver.\r
\r
IN EFI_DHCP4_CONFIG_DATA *Dhcp4CfgData OPTIONAL\r
);\r
\r
-\r
/**\r
Starts the DHCP configuration process.\r
\r
OUT EFI_DHCP4_PACKET **NewPacket\r
);\r
\r
-\r
/**\r
Transmits a DHCP formatted packet and optionally waits for responses.\r
\r
IN EFI_DHCP4_TRANSMIT_RECEIVE_TOKEN *Token\r
);\r
\r
-\r
/**\r
Parses the packed DHCP option data.\r
\r
/// and to provide DHCPv4 server and PXE boot server discovery services.\r
///\r
struct _EFI_DHCP4_PROTOCOL {\r
- EFI_DHCP4_GET_MODE_DATA GetModeData;\r
- EFI_DHCP4_CONFIGURE Configure;\r
- EFI_DHCP4_START Start;\r
- EFI_DHCP4_RENEW_REBIND RenewRebind;\r
- EFI_DHCP4_RELEASE Release;\r
- EFI_DHCP4_STOP Stop;\r
- EFI_DHCP4_BUILD Build;\r
- EFI_DHCP4_TRANSMIT_RECEIVE TransmitReceive;\r
- EFI_DHCP4_PARSE Parse;\r
+ EFI_DHCP4_GET_MODE_DATA GetModeData;\r
+ EFI_DHCP4_CONFIGURE Configure;\r
+ EFI_DHCP4_START Start;\r
+ EFI_DHCP4_RENEW_REBIND RenewRebind;\r
+ EFI_DHCP4_RELEASE Release;\r
+ EFI_DHCP4_STOP Stop;\r
+ EFI_DHCP4_BUILD Build;\r
+ EFI_DHCP4_TRANSMIT_RECEIVE TransmitReceive;\r
+ EFI_DHCP4_PARSE Parse;\r
};\r
\r
-extern EFI_GUID gEfiDhcp4ProtocolGuid;\r
-extern EFI_GUID gEfiDhcp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiDhcp4ProtocolGuid;\r
+extern EFI_GUID gEfiDhcp4ServiceBindingProtocolGuid;\r
\r
#endif\r
/// The EFI DHCPv6 Protocol instance is configured, and start() needs\r
/// to be called\r
///\r
- Dhcp6Init = 0x0,\r
+ Dhcp6Init = 0x0,\r
///\r
/// A Solicit packet is sent out to discover DHCPv6 server, and the EFI\r
/// DHCPv6 Protocol instance is collecting Advertise packets.\r
///\r
- Dhcp6Selecting = 0x1,\r
+ Dhcp6Selecting = 0x1,\r
///\r
/// A Request is sent out to the DHCPv6 server, and the EFI DHCPv6\r
/// Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Requesting = 0x2,\r
+ Dhcp6Requesting = 0x2,\r
///\r
/// A Decline packet is sent out to indicate one or more addresses of the\r
/// configured IA are in use by another node, and the EFI DHCPv6.\r
/// Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Declining = 0x3,\r
+ Dhcp6Declining = 0x3,\r
///\r
/// A Confirm packet is sent out to confirm the IPv6 addresses of the\r
/// configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Confirming = 0x4,\r
+ Dhcp6Confirming = 0x4,\r
///\r
/// A Release packet is sent out to release one or more IPv6 addresses of\r
/// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Releasing = 0x5,\r
+ Dhcp6Releasing = 0x5,\r
///\r
/// The DHCPv6 S.A.R.R process is completed for the configured IA.\r
///\r
- Dhcp6Bound = 0x6,\r
+ Dhcp6Bound = 0x6,\r
///\r
/// A Renew packet is sent out to extend lifetime for the IPv6 addresses of\r
/// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Renewing = 0x7,\r
+ Dhcp6Renewing = 0x7,\r
///\r
/// A Rebind packet is sent out to extend lifetime for the IPv6 addresses of\r
/// the configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.\r
///\r
- Dhcp6Rebinding = 0x8\r
+ Dhcp6Rebinding = 0x8\r
} EFI_DHCP6_STATE;\r
\r
typedef enum {\r
/// A Solicit packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6SendSolicit = 0x0,\r
+ Dhcp6SendSolicit = 0x0,\r
///\r
/// An Advertise packet is received and will be passed to Dhcp6Callback.\r
///\r
- Dhcp6RcvdAdvertise = 0x1,\r
+ Dhcp6RcvdAdvertise = 0x1,\r
///\r
/// It is time for Dhcp6Callback to determine whether select the default Advertise\r
/// packet by RFC 3315 policy, or overwrite it by specific user policy.\r
///\r
- Dhcp6SelectAdvertise = 0x2,\r
+ Dhcp6SelectAdvertise = 0x2,\r
///\r
/// A Request packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6SendRequest = 0x3,\r
+ Dhcp6SendRequest = 0x3,\r
///\r
/// A Reply packet is received and will be passed to Dhcp6Callback.\r
///\r
- Dhcp6RcvdReply = 0x4,\r
+ Dhcp6RcvdReply = 0x4,\r
///\r
/// A Reconfigure packet is received and will be passed to Dhcp6Callback.\r
///\r
- Dhcp6RcvdReconfigure = 0x5,\r
+ Dhcp6RcvdReconfigure = 0x5,\r
///\r
/// A Decline packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6SendDecline = 0x6,\r
+ Dhcp6SendDecline = 0x6,\r
///\r
/// A Confirm packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6SendConfirm = 0x7,\r
+ Dhcp6SendConfirm = 0x7,\r
///\r
/// A Release packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6SendRelease = 0x8,\r
+ Dhcp6SendRelease = 0x8,\r
///\r
/// A Renew packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6EnterRenewing = 0x9,\r
+ Dhcp6EnterRenewing = 0x9,\r
///\r
/// A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and\r
/// can be modified or replaced in Dhcp6Callback.\r
///\r
- Dhcp6EnterRebinding = 0xa\r
+ Dhcp6EnterRebinding = 0xa\r
} EFI_DHCP6_EVENT;\r
\r
///\r
/// An IA which carries assigned not temporary address.\r
///\r
-#define EFI_DHCP6_IA_TYPE_NA 3\r
+#define EFI_DHCP6_IA_TYPE_NA 3\r
///\r
/// An IA which carries assigned temporary address.\r
///\r
-#define EFI_DHCP6_IA_TYPE_TA 4\r
+#define EFI_DHCP6_IA_TYPE_TA 4\r
\r
#pragma pack(1)\r
///\r
///\r
/// The DHCPv6 option code, stored in network order.\r
///\r
- UINT16 OpCode;\r
+ UINT16 OpCode;\r
///\r
/// Length of the DHCPv6 option data, stored in network order.\r
/// From the first byte to the last byte of the Data field.\r
///\r
- UINT16 OpLen;\r
+ UINT16 OpLen;\r
///\r
/// The data for the DHCPv6 option, stored in network order.\r
///\r
- UINT8 Data[1];\r
+ UINT8 Data[1];\r
} EFI_DHCP6_PACKET_OPTION;\r
\r
///\r
/// EFI_DHCP6_HEADER\r
/// defines the format of the DHCPv6 header. See RFC 3315 for more information.\r
///\r
-typedef struct{\r
+typedef struct {\r
///\r
/// The DHCPv6 transaction ID.\r
///\r
- UINT32 MessageType:8;\r
+ UINT32 MessageType : 8;\r
///\r
/// The DHCPv6 message type.\r
///\r
- UINT32 TransactionId:24;\r
+ UINT32 TransactionId : 24;\r
} EFI_DHCP6_HEADER;\r
\r
///\r
///\r
/// Size of the EFI_DHCP6_PACKET buffer.\r
///\r
- UINT32 Size;\r
+ UINT32 Size;\r
///\r
/// Length of the EFI_DHCP6_PACKET from the first byte of the Header field to the last\r
/// byte of the Option[] field.\r
///\r
- UINT32 Length;\r
- struct{\r
+ UINT32 Length;\r
+ struct {\r
///\r
/// The DHCPv6 packet header.\r
///\r
- EFI_DHCP6_HEADER Header;\r
+ EFI_DHCP6_HEADER Header;\r
///\r
/// Start of the DHCPv6 packed option data.\r
///\r
- UINT8 Option[1];\r
+ UINT8 Option[1];\r
} Dhcp6;\r
} EFI_DHCP6_PACKET;\r
\r
///\r
/// Length of DUID in octects.\r
///\r
- UINT16 Length;\r
+ UINT16 Length;\r
///\r
/// Array of DUID octects.\r
///\r
- UINT8 Duid[1];\r
+ UINT8 Duid[1];\r
} EFI_DHCP6_DUID;\r
\r
typedef struct {\r
///\r
/// Initial retransmission timeout.\r
///\r
- UINT32 Irt;\r
+ UINT32 Irt;\r
///\r
/// Maximum retransmission count for one packet. If Mrc is zero, there's no upper limit\r
/// for retransmission count.\r
///\r
- UINT32 Mrc;\r
+ UINT32 Mrc;\r
///\r
/// Maximum retransmission timeout for each retry. It's the upper bound of the number of\r
/// retransmission timeout. If Mrt is zero, there is no upper limit for retransmission\r
/// timeout.\r
///\r
- UINT32 Mrt;\r
+ UINT32 Mrt;\r
///\r
/// Maximum retransmission duration for one packet. It's the upper bound of the numbers\r
/// the client may retransmit a message. If Mrd is zero, there's no upper limit for\r
/// retransmission duration.\r
///\r
- UINT32 Mrd;\r
+ UINT32 Mrd;\r
} EFI_DHCP6_RETRANSMISSION;\r
\r
typedef struct {\r
///\r
/// The IPv6 address.\r
///\r
- EFI_IPv6_ADDRESS IpAddress;\r
+ EFI_IPv6_ADDRESS IpAddress;\r
///\r
/// The preferred lifetime in unit of seconds for the IPv6 address.\r
///\r
- UINT32 PreferredLifetime;\r
+ UINT32 PreferredLifetime;\r
///\r
/// The valid lifetime in unit of seconds for the IPv6 address.\r
///\r
- UINT32 ValidLifetime;\r
+ UINT32 ValidLifetime;\r
} EFI_DHCP6_IA_ADDRESS;\r
\r
typedef struct {\r
- UINT16 Type; ///< Type for an IA.\r
- UINT32 IaId; ///< The identifier for an IA.\r
+ UINT16 Type; ///< Type for an IA.\r
+ UINT32 IaId; ///< The identifier for an IA.\r
} EFI_DHCP6_IA_DESCRIPTOR;\r
\r
typedef struct {\r
///\r
/// The descriptor for IA.\r
///\r
- EFI_DHCP6_IA_DESCRIPTOR Descriptor;\r
+ EFI_DHCP6_IA_DESCRIPTOR Descriptor;\r
///\r
/// The state of the configured IA.\r
///\r
- EFI_DHCP6_STATE State;\r
+ EFI_DHCP6_STATE State;\r
///\r
/// Pointer to the cached latest Reply packet. May be NULL if no packet is cached.\r
///\r
- EFI_DHCP6_PACKET *ReplyPacket;\r
+ EFI_DHCP6_PACKET *ReplyPacket;\r
///\r
/// Number of IPv6 addresses of the configured IA.\r
///\r
- UINT32 IaAddressCount;\r
+ UINT32 IaAddressCount;\r
///\r
/// List of the IPv6 addresses of the configured IA. When the state of the configured IA is\r
/// in Dhcp6Bound, Dhcp6Renewing and Dhcp6Rebinding, the IPv6 addresses are usable.\r
///\r
- EFI_DHCP6_IA_ADDRESS IaAddress[1];\r
+ EFI_DHCP6_IA_ADDRESS IaAddress[1];\r
} EFI_DHCP6_IA;\r
\r
typedef struct {\r
///\r
/// Pointer to the DHCPv6 unique identifier. The caller is responsible for freeing this buffer.\r
///\r
- EFI_DHCP6_DUID *ClientId;\r
+ EFI_DHCP6_DUID *ClientId;\r
///\r
/// Pointer to the configured IA of current instance. The caller can free this buffer after\r
/// using it.\r
///\r
- EFI_DHCP6_IA *Ia;\r
+ EFI_DHCP6_IA *Ia;\r
} EFI_DHCP6_MODE_DATA;\r
\r
/**\r
/// The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R\r
/// process. Set to NULL to ignore all those events.\r
///\r
- EFI_DHCP6_CALLBACK Dhcp6Callback;\r
+ EFI_DHCP6_CALLBACK Dhcp6Callback;\r
///\r
/// Pointer to the context that will be passed to Dhcp6Callback.\r
///\r
- VOID *CallbackContext;\r
+ VOID *CallbackContext;\r
///\r
/// Number of the DHCPv6 options in the OptionList.\r
///\r
- UINT32 OptionCount;\r
+ UINT32 OptionCount;\r
///\r
/// List of the DHCPv6 options to be included in Solicit and Request packet. The buffer\r
/// can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. Ignored if\r
/// and any IA option, which will be appended by EFI DHCPv6 Protocol instance\r
/// automatically.\r
///\r
- EFI_DHCP6_PACKET_OPTION **OptionList;\r
+ EFI_DHCP6_PACKET_OPTION **OptionList;\r
///\r
/// The descriptor for the IA of the EFI DHCPv6 Protocol instance.\r
///\r
- EFI_DHCP6_IA_DESCRIPTOR IaDescriptor;\r
+ EFI_DHCP6_IA_DESCRIPTOR IaDescriptor;\r
///\r
/// If not NULL, the event will be signaled when any IPv6 address information of the\r
/// configured IA is updated, including IPv6 address, preferred lifetime and valid\r
/// renewrebind(), decline(), release() and stop() will be blocking\r
/// operations, and they will wait for the exchange process completion or failure.\r
///\r
- EFI_EVENT IaInfoEvent;\r
+ EFI_EVENT IaInfoEvent;\r
///\r
/// If TRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconfigure packet.\r
/// Otherwise, it will ignore it. Reconfigure Accept option can not be specified through\r
/// OptionList parameter.\r
///\r
- BOOLEAN ReconfigureAccept;\r
+ BOOLEAN ReconfigureAccept;\r
///\r
/// If TRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid\r
/// Commit option. Otherwise, Rapid Commit option will not be included in Solicit\r
/// packet. Rapid Commit option can not be specified through OptionList parameter.\r
///\r
- BOOLEAN RapidCommit;\r
+ BOOLEAN RapidCommit;\r
///\r
/// Parameter to control Solicit packet retransmission behavior. The\r
/// buffer can be freed after EFI_DHCP6_PROTOCOL.Configure() returns.\r
///\r
- EFI_DHCP6_RETRANSMISSION *SolicitRetransmission;\r
+ EFI_DHCP6_RETRANSMISSION *SolicitRetransmission;\r
} EFI_DHCP6_CONFIG_DATA;\r
\r
/**\r
IN EFI_DHCP6_PACKET *Packet,\r
IN OUT UINT32 *OptionCount,\r
OUT EFI_DHCP6_PACKET_OPTION *PacketOptionList[] OPTIONAL\r
-);\r
+ );\r
\r
///\r
/// The EFI DHCPv6 Protocol is used to get IPv6 addresses and other configuration parameters\r
/// from DHCPv6 servers.\r
///\r
struct _EFI_DHCP6_PROTOCOL {\r
- EFI_DHCP6_GET_MODE_DATA GetModeData;\r
- EFI_DHCP6_CONFIGURE Configure;\r
- EFI_DHCP6_START Start;\r
- EFI_DHCP6_INFO_REQUEST InfoRequest;\r
- EFI_DHCP6_RENEW_REBIND RenewRebind;\r
- EFI_DHCP6_DECLINE Decline;\r
- EFI_DHCP6_RELEASE Release;\r
- EFI_DHCP6_STOP Stop;\r
- EFI_DHCP6_PARSE Parse;\r
+ EFI_DHCP6_GET_MODE_DATA GetModeData;\r
+ EFI_DHCP6_CONFIGURE Configure;\r
+ EFI_DHCP6_START Start;\r
+ EFI_DHCP6_INFO_REQUEST InfoRequest;\r
+ EFI_DHCP6_RENEW_REBIND RenewRebind;\r
+ EFI_DHCP6_DECLINE Decline;\r
+ EFI_DHCP6_RELEASE Release;\r
+ EFI_DHCP6_STOP Stop;\r
+ EFI_DHCP6_PARSE Parse;\r
};\r
\r
-extern EFI_GUID gEfiDhcp6ProtocolGuid;\r
-extern EFI_GUID gEfiDhcp6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiDhcp6ProtocolGuid;\r
+extern EFI_GUID gEfiDhcp6ServiceBindingProtocolGuid;\r
\r
#endif\r
///\r
/// Forward declaration for EFI_DISK_INFO_PROTOCOL\r
///\r
-typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL;\r
+typedef struct _EFI_DISK_INFO_PROTOCOL EFI_DISK_INFO_PROTOCOL;\r
\r
///\r
/// Global ID for an IDE interface. Used to fill in EFI_DISK_INFO_PROTOCOL.Interface\r
/// A GUID that defines the format of buffers for the other member functions\r
/// of this protocol.\r
///\r
- EFI_GUID Interface;\r
+ EFI_GUID Interface;\r
///\r
/// Return the results of the Inquiry command to a drive in InquiryData. Data\r
/// format of Inquiry data is defined by the Interface GUID.\r
///\r
- EFI_DISK_INFO_INQUIRY Inquiry;\r
+ EFI_DISK_INFO_INQUIRY Inquiry;\r
///\r
/// Return the results of the Identify command to a drive in IdentifyData. Data\r
/// format of Identify data is defined by the Interface GUID.\r
///\r
- EFI_DISK_INFO_IDENTIFY Identify;\r
+ EFI_DISK_INFO_IDENTIFY Identify;\r
///\r
/// Return the results of the Request Sense command to a drive in SenseData. Data\r
/// format of Sense data is defined by the Interface GUID.\r
///\r
- EFI_DISK_INFO_SENSE_DATA SenseData;\r
+ EFI_DISK_INFO_SENSE_DATA SenseData;\r
///\r
/// Specific controller.\r
///\r
- EFI_DISK_INFO_WHICH_IDE WhichIde;\r
+ EFI_DISK_INFO_WHICH_IDE WhichIde;\r
};\r
\r
-extern EFI_GUID gEfiDiskInfoProtocolGuid;\r
+extern EFI_GUID gEfiDiskInfoProtocolGuid;\r
\r
-extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;\r
-extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoIdeInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoScsiInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;\r
+extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;\r
\r
#endif\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_DISK_IO_PROTOCOL EFI_DISK_IO;\r
+typedef EFI_DISK_IO_PROTOCOL EFI_DISK_IO;\r
\r
/**\r
Read BufferSize bytes from Offset into Buffer.\r
IN VOID *Buffer\r
);\r
\r
-#define EFI_DISK_IO_PROTOCOL_REVISION 0x00010000\r
+#define EFI_DISK_IO_PROTOCOL_REVISION 0x00010000\r
\r
///\r
/// Revision defined in EFI1.1\r
/// revisions must be backwards compatible. If a future version is not\r
/// backwards compatible, it is not the same GUID.\r
///\r
- UINT64 Revision;\r
- EFI_DISK_READ ReadDisk;\r
- EFI_DISK_WRITE WriteDisk;\r
+ UINT64 Revision;\r
+ EFI_DISK_READ ReadDisk;\r
+ EFI_DISK_WRITE WriteDisk;\r
};\r
\r
-extern EFI_GUID gEfiDiskIoProtocolGuid;\r
+extern EFI_GUID gEfiDiskIoProtocolGuid;\r
\r
#endif\r
// The caller must be prepared to handle the case where the callback associated with Event occurs\r
// before the original asynchronous I/O request call returns.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
\r
//\r
// Defines whether or not the signaled event encountered an error.\r
//\r
- EFI_STATUS TransactionStatus;\r
+ EFI_STATUS TransactionStatus;\r
} EFI_DISK_IO2_TOKEN;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DISK_CANCEL_EX) (\r
+(EFIAPI *EFI_DISK_CANCEL_EX)(\r
IN EFI_DISK_IO2_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DISK_READ_EX) (\r
+(EFIAPI *EFI_DISK_READ_EX)(\r
IN EFI_DISK_IO2_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN UINT64 Offset,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DISK_WRITE_EX) (\r
+(EFIAPI *EFI_DISK_WRITE_EX)(\r
IN EFI_DISK_IO2_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN UINT64 Offset,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DISK_FLUSH_EX) (\r
+(EFIAPI *EFI_DISK_FLUSH_EX)(\r
IN EFI_DISK_IO2_PROTOCOL *This,\r
IN OUT EFI_DISK_IO2_TOKEN *Token\r
);\r
\r
-#define EFI_DISK_IO2_PROTOCOL_REVISION 0x00020000\r
+#define EFI_DISK_IO2_PROTOCOL_REVISION 0x00020000\r
\r
///\r
/// This protocol is used to abstract Block I/O interfaces.\r
/// revisions must be backwards compatible. If a future version is not\r
/// backwards compatible, it is not the same GUID.\r
///\r
- UINT64 Revision;\r
- EFI_DISK_CANCEL_EX Cancel;\r
- EFI_DISK_READ_EX ReadDiskEx;\r
- EFI_DISK_WRITE_EX WriteDiskEx;\r
- EFI_DISK_FLUSH_EX FlushDiskEx;\r
+ UINT64 Revision;\r
+ EFI_DISK_CANCEL_EX Cancel;\r
+ EFI_DISK_READ_EX ReadDiskEx;\r
+ EFI_DISK_WRITE_EX WriteDiskEx;\r
+ EFI_DISK_FLUSH_EX FlushDiskEx;\r
};\r
\r
-extern EFI_GUID gEfiDiskIo2ProtocolGuid;\r
+extern EFI_GUID gEfiDiskIo2ProtocolGuid;\r
\r
#endif\r
/// DnsServerListCount is zero, the DNS server configuration\r
/// will be retrieved from DHCP server automatically.\r
///\r
- UINTN DnsServerListCount;\r
+ UINTN DnsServerListCount;\r
///\r
/// Pointer to DNS server list containing DnsServerListCount entries or NULL\r
/// if DnsServerListCountis 0. For Configure(), this will be NULL when there are\r
/// freed by the caller. When used with Configure(), the buffer\r
/// containing the list will be allocated and released by the caller.\r
///\r
- EFI_IPv4_ADDRESS *DnsServerList;\r
+ EFI_IPv4_ADDRESS *DnsServerList;\r
///\r
/// Set to TRUE to use the default IP address/subnet mask and default routing table.\r
///\r
- BOOLEAN UseDefaultSetting;\r
+ BOOLEAN UseDefaultSetting;\r
///\r
/// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS\r
/// query will not lookup local DNS cache.\r
///\r
- BOOLEAN EnableDnsCache;\r
+ BOOLEAN EnableDnsCache;\r
///\r
/// Use the protocol number defined in "Links to UEFI-Related\r
/// Documents"(http://uefi.org/uefi) under the heading "IANA\r
/// protocol values are invalid. An implementation can choose to\r
/// support only UDP, or both TCP and UDP.\r
///\r
- UINT8 Protocol;\r
+ UINT8 Protocol;\r
///\r
/// If UseDefaultSetting is FALSE indicates the station address to use.\r
///\r
- EFI_IPv4_ADDRESS StationIp;\r
+ EFI_IPv4_ADDRESS StationIp;\r
///\r
/// If UseDefaultSetting is FALSE indicates the subnet mask to use.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// Local port number. Set to zero to use the automatically assigned port number.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// Retry number if no response received after RetryInterval.\r
///\r
- UINT32 RetryCount;\r
+ UINT32 RetryCount;\r
///\r
/// Minimum interval of retry is 2 second. If the retry interval is less than 2\r
/// seconds, then use the 2 seconds.\r
///\r
- UINT32 RetryInterval;\r
+ UINT32 RetryInterval;\r
} EFI_DNS4_CONFIG_DATA;\r
\r
-\r
///\r
/// EFI_DNS4_CACHE_ENTRY\r
///\r
///\r
/// Host name.\r
///\r
- CHAR16 *HostName;\r
+ CHAR16 *HostName;\r
///\r
/// IP address of this host.\r
///\r
- EFI_IPv4_ADDRESS *IpAddress;\r
+ EFI_IPv4_ADDRESS *IpAddress;\r
///\r
/// Time in second unit that this entry will remain in DNS cache. A value of zero\r
/// means that this entry is permanent. A nonzero value will override the existing\r
/// default timeout value for the dynamically created DNS cache entry after one DNS\r
/// resolve succeeds.\r
///\r
- UINT32 Timeout;\r
+ UINT32 Timeout;\r
} EFI_DNS4_CACHE_ENTRY;\r
\r
///\r
///\r
/// The configuration data of this instance.\r
///\r
- EFI_DNS4_CONFIG_DATA DnsConfigData;\r
+ EFI_DNS4_CONFIG_DATA DnsConfigData;\r
///\r
/// Number of configured DNS server. Each DNS instance has its own DNS server\r
/// configuration.\r
///\r
- UINT32 DnsServerCount;\r
+ UINT32 DnsServerCount;\r
///\r
/// Pointer to common list of addresses of all configured DNS server\r
/// used by EFI_DNS4_PROTOCOL instances. List will include\r
/// The storage for this list is allocated by the driver publishing this\r
/// protocol, and must be freed by the caller.\r
///\r
- EFI_IPv4_ADDRESS *DnsServerList;\r
+ EFI_IPv4_ADDRESS *DnsServerList;\r
///\r
/// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.\r
///\r
- UINT32 DnsCacheCount;\r
+ UINT32 DnsCacheCount;\r
///\r
/// Pointer to a buffer containing DnsCacheCount DNS Cache\r
/// entry structures. The storage for this list is allocated by the driver\r
/// publishing this protocol and must be freed by caller.\r
///\r
- EFI_DNS4_CACHE_ENTRY *DnsCacheList;\r
+ EFI_DNS4_CACHE_ENTRY *DnsCacheList;\r
} EFI_DNS4_MODE_DATA;\r
\r
///\r
///\r
/// Number of the returned IP addresses.\r
///\r
- UINT32 IpCount;\r
+ UINT32 IpCount;\r
///\r
/// Pointer to the all the returned IP addresses.\r
///\r
- EFI_IPv4_ADDRESS *IpList;\r
+ EFI_IPv4_ADDRESS *IpList;\r
} DNS_HOST_TO_ADDR_DATA;\r
\r
///\r
/// Pointer to the primary name for this host address. It's the caller's\r
/// responsibility to free the response memory.\r
///\r
- CHAR16 *HostName;\r
+ CHAR16 *HostName;\r
} DNS_ADDR_TO_HOST_DATA;\r
\r
///\r
///\r
/// The Owner name.\r
///\r
- CHAR8 *QName;\r
+ CHAR8 *QName;\r
///\r
/// The Type Code of this RR.\r
///\r
- UINT16 QType;\r
+ UINT16 QType;\r
///\r
/// The CLASS code of this RR.\r
///\r
- UINT16 QClass;\r
+ UINT16 QClass;\r
///\r
/// 32 bit integer which specify the time interval that the resource record may be\r
/// cached before the source of the information should again be consulted. Zero means\r
/// this RR can not be cached.\r
///\r
- UINT32 TTL;\r
+ UINT32 TTL;\r
///\r
/// 16 big integer which specify the length of RData.\r
///\r
- UINT16 DataLength;\r
+ UINT16 DataLength;\r
///\r
/// A string of octets that describe the resource, the format of this information\r
/// varies according to QType and QClass difference.\r
///\r
- CHAR8 *RData;\r
+ CHAR8 *RData;\r
} DNS_RESOURCE_RECORD;\r
\r
///\r
///\r
/// Number of returned matching RRs.\r
///\r
- UINTN RRCount;\r
+ UINTN RRCount;\r
///\r
/// Pointer to the all the returned matching RRs. It's caller responsibility to free\r
/// the allocated memory to hold the returned RRs.\r
///\r
- DNS_RESOURCE_RECORD *RRList;\r
+ DNS_RESOURCE_RECORD *RRList;\r
} DNS_GENERAL_LOOKUP_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI DNS\r
/// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: The host name to address translation completed successfully.\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Retry number if no response received after RetryInterval. If zero, use the\r
/// parameter configured through Dns.Configure() interface.\r
///\r
- UINT32 RetryCount;\r
+ UINT32 RetryCount;\r
///\r
/// Minimum interval of retry is 2 second. If the retry interval is less than 2\r
/// seconds, then use the 2 seconds. If zero, use the parameter configured through\r
/// Dns.Configure() interface.\r
- UINT32 RetryInterval;\r
+ UINT32 RetryInterval;\r
///\r
/// DNSv4 completion token data\r
///\r
/// When the Token is used for host name to address translation, H2AData is a pointer\r
/// to the DNS_HOST_TO_ADDR_DATA.\r
///\r
- DNS_HOST_TO_ADDR_DATA *H2AData;\r
+ DNS_HOST_TO_ADDR_DATA *H2AData;\r
///\r
/// When the Token is used for host address to host name translation, A2HData is a\r
/// pointer to the DNS_ADDR_TO_HOST_DATA.\r
///\r
- DNS_ADDR_TO_HOST_DATA *A2HData;\r
+ DNS_ADDR_TO_HOST_DATA *A2HData;\r
///\r
/// When the Token is used for a general lookup function, GLookupDATA is a pointer to\r
/// the DNS_GENERAL_LOOKUP_DATA.\r
///\r
- DNS_GENERAL_LOOKUP_DATA *GLookupData;\r
+ DNS_GENERAL_LOOKUP_DATA *GLookupData;\r
} RspData;\r
} EFI_DNS4_COMPLETION_TOKEN;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_GET_MODE_DATA) (\r
+(EFIAPI *EFI_DNS4_GET_MODE_DATA)(\r
IN EFI_DNS4_PROTOCOL *This,\r
OUT EFI_DNS4_MODE_DATA *DnsModeData\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_CONFIGURE) (\r
+(EFIAPI *EFI_DNS4_CONFIGURE)(\r
IN EFI_DNS4_PROTOCOL *This,\r
IN EFI_DNS4_CONFIG_DATA *DnsConfigData\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_HOST_NAME_TO_IP) (\r
- IN EFI_DNS4_PROTOCOL *This,\r
- IN CHAR16 *HostName,\r
- IN EFI_DNS4_COMPLETION_TOKEN *Token\r
+(EFIAPI *EFI_DNS4_HOST_NAME_TO_IP)(\r
+ IN EFI_DNS4_PROTOCOL *This,\r
+ IN CHAR16 *HostName,\r
+ IN EFI_DNS4_COMPLETION_TOKEN *Token\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_IP_TO_HOST_NAME) (\r
- IN EFI_DNS4_PROTOCOL *This,\r
- IN EFI_IPv4_ADDRESS IpAddress,\r
- IN EFI_DNS4_COMPLETION_TOKEN *Token\r
+(EFIAPI *EFI_DNS4_IP_TO_HOST_NAME)(\r
+ IN EFI_DNS4_PROTOCOL *This,\r
+ IN EFI_IPv4_ADDRESS IpAddress,\r
+ IN EFI_DNS4_COMPLETION_TOKEN *Token\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_GENERAL_LOOKUP) (\r
+(EFIAPI *EFI_DNS4_GENERAL_LOOKUP)(\r
IN EFI_DNS4_PROTOCOL *This,\r
IN CHAR8 *QName,\r
IN UINT16 QType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_UPDATE_DNS_CACHE) (\r
+(EFIAPI *EFI_DNS4_UPDATE_DNS_CACHE)(\r
IN EFI_DNS4_PROTOCOL *This,\r
IN BOOLEAN DeleteFlag,\r
IN BOOLEAN Override,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_POLL) (\r
+(EFIAPI *EFI_DNS4_POLL)(\r
IN EFI_DNS4_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS4_CANCEL) (\r
+(EFIAPI *EFI_DNS4_CANCEL)(\r
IN EFI_DNS4_PROTOCOL *This,\r
IN EFI_DNS4_COMPLETION_TOKEN *Token\r
);\r
/// from DNS.\r
///\r
struct _EFI_DNS4_PROTOCOL {\r
- EFI_DNS4_GET_MODE_DATA GetModeData;\r
- EFI_DNS4_CONFIGURE Configure;\r
- EFI_DNS4_HOST_NAME_TO_IP HostNameToIp;\r
- EFI_DNS4_IP_TO_HOST_NAME IpToHostName;\r
- EFI_DNS4_GENERAL_LOOKUP GeneralLookUp;\r
- EFI_DNS4_UPDATE_DNS_CACHE UpdateDnsCache;\r
- EFI_DNS4_POLL Poll;\r
- EFI_DNS4_CANCEL Cancel;\r
+ EFI_DNS4_GET_MODE_DATA GetModeData;\r
+ EFI_DNS4_CONFIGURE Configure;\r
+ EFI_DNS4_HOST_NAME_TO_IP HostNameToIp;\r
+ EFI_DNS4_IP_TO_HOST_NAME IpToHostName;\r
+ EFI_DNS4_GENERAL_LOOKUP GeneralLookUp;\r
+ EFI_DNS4_UPDATE_DNS_CACHE UpdateDnsCache;\r
+ EFI_DNS4_POLL Poll;\r
+ EFI_DNS4_CANCEL Cancel;\r
};\r
\r
-extern EFI_GUID gEfiDns4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiDns4ProtocolGuid;\r
+extern EFI_GUID gEfiDns4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiDns4ProtocolGuid;\r
\r
#endif\r
/// If TRUE, enable DNS cache function for this DNS instance. If FALSE, all DNS query\r
/// will not lookup local DNS cache.\r
///\r
- BOOLEAN EnableDnsCache;\r
+ BOOLEAN EnableDnsCache;\r
///\r
/// Use the protocol number defined in\r
/// http://www.iana.org/assignments/protocol-numbers. Beside TCP/UDP, Other protocol\r
/// is invalid value. An implementation can choose to support UDP, or both TCP and UDP.\r
///\r
- UINT8 Protocol;\r
+ UINT8 Protocol;\r
///\r
/// The local IP address to use. Set to zero to let the underlying IPv6\r
/// driver choose a source address. If not zero it must be one of the\r
/// configured IP addresses in the underlying IPv6 driver.\r
///\r
- EFI_IPv6_ADDRESS StationIp;\r
+ EFI_IPv6_ADDRESS StationIp;\r
///\r
/// Local port number. Set to zero to use the automatically assigned port number.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// Count of the DNS servers. When used with GetModeData(),\r
/// this field is the count of originally configured servers when\r
/// DnsServerListCount is zero, the DNS server configuration\r
/// will be retrieved from DHCP server automatically.\r
///\r
- UINT32 DnsServerCount;\r
+ UINT32 DnsServerCount;\r
///\r
/// Pointer to DNS server list containing DnsServerListCount\r
/// entries or NULL if DnsServerListCount is 0. For Configure(),\r
/// freed by the caller. When used with Configure(), the buffer\r
/// containing the list will be allocated and released by the caller.\r
///\r
- EFI_IPv6_ADDRESS *DnsServerList;\r
+ EFI_IPv6_ADDRESS *DnsServerList;\r
///\r
/// Retry number if no response received after RetryInterval.\r
///\r
- UINT32 RetryCount;\r
+ UINT32 RetryCount;\r
///\r
/// Minimum interval of retry is 2 second. If the retry interval is less than 2\r
/// seconds, then use the 2 seconds.\r
- UINT32 RetryInterval;\r
+ UINT32 RetryInterval;\r
} EFI_DNS6_CONFIG_DATA;\r
\r
///\r
///\r
/// Host name. This should be interpreted as Unicode characters.\r
///\r
- CHAR16 *HostName;\r
+ CHAR16 *HostName;\r
///\r
/// IP address of this host.\r
///\r
- EFI_IPv6_ADDRESS *IpAddress;\r
+ EFI_IPv6_ADDRESS *IpAddress;\r
///\r
/// Time in second unit that this entry will remain in DNS cache. A value of zero means\r
/// that this entry is permanent. A nonzero value will override the existing one if\r
/// this entry to be added is dynamic entry. Implementations may set its default\r
/// timeout value for the dynamically created DNS cache entry after one DNS resolve\r
/// succeeds.\r
- UINT32 Timeout;\r
+ UINT32 Timeout;\r
} EFI_DNS6_CACHE_ENTRY;\r
\r
///\r
///\r
/// The configuration data of this instance.\r
///\r
- EFI_DNS6_CONFIG_DATA DnsConfigData;\r
+ EFI_DNS6_CONFIG_DATA DnsConfigData;\r
///\r
/// Number of configured DNS6 servers.\r
///\r
- UINT32 DnsServerCount;\r
+ UINT32 DnsServerCount;\r
///\r
/// Pointer to common list of addresses of all configured DNS server used by EFI_DNS6_PROTOCOL\r
/// instances. List will include DNS servers configured by this or any other EFI_DNS6_PROTOCOL\r
/// instance. The storage for this list is allocated by the driver publishing this protocol,\r
/// and must be freed by the caller.\r
///\r
- EFI_IPv6_ADDRESS *DnsServerList;\r
+ EFI_IPv6_ADDRESS *DnsServerList;\r
///\r
/// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.\r
///\r
- UINT32 DnsCacheCount;\r
+ UINT32 DnsCacheCount;\r
///\r
/// Pointer to a buffer containing DnsCacheCount DNS Cache\r
/// entry structures. The storage for thislist is allocated by the driver\r
/// publishing this protocol and must be freed by caller.\r
///\r
- EFI_DNS6_CACHE_ENTRY *DnsCacheList;\r
+ EFI_DNS6_CACHE_ENTRY *DnsCacheList;\r
} EFI_DNS6_MODE_DATA;\r
\r
///\r
///\r
/// Number of the returned IP address.\r
///\r
- UINT32 IpCount;\r
+ UINT32 IpCount;\r
///\r
/// Pointer to the all the returned IP address.\r
///\r
- EFI_IPv6_ADDRESS *IpList;\r
+ EFI_IPv6_ADDRESS *IpList;\r
} DNS6_HOST_TO_ADDR_DATA;\r
\r
///\r
/// Pointer to the primary name for this host address. It's the caller's\r
/// responsibility to free the response memory.\r
///\r
- CHAR16 *HostName;\r
+ CHAR16 *HostName;\r
} DNS6_ADDR_TO_HOST_DATA;\r
\r
///\r
///\r
/// The Owner name.\r
///\r
- CHAR8 *QName;\r
+ CHAR8 *QName;\r
///\r
/// The Type Code of this RR.\r
///\r
- UINT16 QType;\r
+ UINT16 QType;\r
///\r
/// The CLASS code of this RR.\r
///\r
- UINT16 QClass;\r
+ UINT16 QClass;\r
///\r
/// 32 bit integer which specify the time interval that the resource record may be\r
/// cached before the source of the information should again be consulted. Zero means\r
/// this RR cannot be cached.\r
///\r
- UINT32 TTL;\r
+ UINT32 TTL;\r
///\r
/// 16 big integer which specify the length of RData.\r
///\r
- UINT16 DataLength;\r
+ UINT16 DataLength;\r
///\r
/// A string of octets that describe the resource, the format of this information\r
/// varies according to QType and QClass difference.\r
///\r
- CHAR8 *RData;\r
+ CHAR8 *RData;\r
} DNS6_RESOURCE_RECORD;\r
\r
///\r
///\r
/// Number of returned matching RRs.\r
///\r
- UINTN RRCount;\r
+ UINTN RRCount;\r
///\r
/// Pointer to the all the returned matching RRs. It's caller responsibility to free\r
/// the allocated memory to hold the returned RRs.\r
///\r
- DNS6_RESOURCE_RECORD *RRList;\r
+ DNS6_RESOURCE_RECORD *RRList;\r
} DNS6_GENERAL_LOOKUP_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI DNSv6\r
/// protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: The host name to address translation completed successfully.\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// The parameter configured through DNSv6.Configure() interface. Retry number if no\r
/// response received after RetryInterval.\r
///\r
- UINT32 RetryCount;\r
+ UINT32 RetryCount;\r
///\r
/// The parameter configured through DNSv6.Configure() interface. Minimum interval of\r
/// retry is 2 seconds. If the retry interval is less than 2 seconds, then use the 2\r
/// seconds.\r
///\r
- UINT32 RetryInterval;\r
+ UINT32 RetryInterval;\r
///\r
/// DNSv6 completion token data\r
///\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_DNS6_GET_MODE_DATA)(\r
+(EFIAPI *EFI_DNS6_GET_MODE_DATA)(\r
IN EFI_DNS6_PROTOCOL *This,\r
OUT EFI_DNS6_MODE_DATA *DnsModeData\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_DNS6_CONFIGURE)(\r
+(EFIAPI *EFI_DNS6_CONFIGURE)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN EFI_DNS6_CONFIG_DATA *DnsConfigData\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_HOST_NAME_TO_IP) (\r
+(EFIAPI *EFI_DNS6_HOST_NAME_TO_IP)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN CHAR16 *HostName,\r
IN EFI_DNS6_COMPLETION_TOKEN *Token\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_IP_TO_HOST_NAME) (\r
+(EFIAPI *EFI_DNS6_IP_TO_HOST_NAME)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN EFI_IPv6_ADDRESS IpAddress,\r
IN EFI_DNS6_COMPLETION_TOKEN *Token\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_GENERAL_LOOKUP) (\r
+(EFIAPI *EFI_DNS6_GENERAL_LOOKUP)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN CHAR8 *QName,\r
IN UINT16 QType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_UPDATE_DNS_CACHE) (\r
+(EFIAPI *EFI_DNS6_UPDATE_DNS_CACHE)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN BOOLEAN DeleteFlag,\r
IN BOOLEAN Override,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_POLL) (\r
+(EFIAPI *EFI_DNS6_POLL)(\r
IN EFI_DNS6_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_DNS6_CANCEL) (\r
+(EFIAPI *EFI_DNS6_CANCEL)(\r
IN EFI_DNS6_PROTOCOL *This,\r
IN EFI_DNS6_COMPLETION_TOKEN *Token\r
);\r
/// DNSv6.\r
///\r
struct _EFI_DNS6_PROTOCOL {\r
- EFI_DNS6_GET_MODE_DATA GetModeData;\r
- EFI_DNS6_CONFIGURE Configure;\r
- EFI_DNS6_HOST_NAME_TO_IP HostNameToIp;\r
- EFI_DNS6_IP_TO_HOST_NAME IpToHostName;\r
- EFI_DNS6_GENERAL_LOOKUP GeneralLookUp;\r
- EFI_DNS6_UPDATE_DNS_CACHE UpdateDnsCache;\r
- EFI_DNS6_POLL Poll;\r
- EFI_DNS6_CANCEL Cancel;\r
+ EFI_DNS6_GET_MODE_DATA GetModeData;\r
+ EFI_DNS6_CONFIGURE Configure;\r
+ EFI_DNS6_HOST_NAME_TO_IP HostNameToIp;\r
+ EFI_DNS6_IP_TO_HOST_NAME IpToHostName;\r
+ EFI_DNS6_GENERAL_LOOKUP GeneralLookUp;\r
+ EFI_DNS6_UPDATE_DNS_CACHE UpdateDnsCache;\r
+ EFI_DNS6_POLL Poll;\r
+ EFI_DNS6_CANCEL Cancel;\r
};\r
\r
-extern EFI_GUID gEfiDns6ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiDns6ProtocolGuid;\r
+extern EFI_GUID gEfiDns6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiDns6ProtocolGuid;\r
\r
#endif\r
0x18a031ab, 0xb443, 0x4d1a, {0xa5, 0xc0, 0xc, 0x9, 0x26, 0x1e, 0x9f, 0x71 } \\r
}\r
\r
-typedef struct _EFI_DRIVER_BINDING_PROTOCOL EFI_DRIVER_BINDING_PROTOCOL;\r
+typedef struct _EFI_DRIVER_BINDING_PROTOCOL EFI_DRIVER_BINDING_PROTOCOL;\r
\r
/**\r
Tests to see if this driver supports a given controller. If a child device is provided,\r
/// If a controller is supported, then it also provides routines to start and stop the controller.\r
///\r
struct _EFI_DRIVER_BINDING_PROTOCOL {\r
- EFI_DRIVER_BINDING_SUPPORTED Supported;\r
- EFI_DRIVER_BINDING_START Start;\r
- EFI_DRIVER_BINDING_STOP Stop;\r
+ EFI_DRIVER_BINDING_SUPPORTED Supported;\r
+ EFI_DRIVER_BINDING_START Start;\r
+ EFI_DRIVER_BINDING_STOP Stop;\r
\r
///\r
/// The version number of the UEFI driver that produced the\r
/// platform/OEM specific drivers. The Version values of 0x10-\r
/// 0xffffffef are reserved for IHV-developed drivers.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
\r
///\r
/// The image handle of the UEFI driver that produced this instance\r
/// of the EFI_DRIVER_BINDING_PROTOCOL.\r
///\r
- EFI_HANDLE ImageHandle;\r
+ EFI_HANDLE ImageHandle;\r
\r
///\r
/// The handle on which this instance of the\r
/// EFI_DRIVER_BINDING_PROTOCOL, this value may not be\r
/// the same as ImageHandle.\r
///\r
- EFI_HANDLE DriverBindingHandle;\r
+ EFI_HANDLE DriverBindingHandle;\r
};\r
\r
-extern EFI_GUID gEfiDriverBindingProtocolGuid;\r
+extern EFI_GUID gEfiDriverBindingProtocolGuid;\r
\r
#endif\r
0x107a772b, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_DRIVER_CONFIGURATION_PROTOCOL EFI_DRIVER_CONFIGURATION_PROTOCOL;\r
+typedef struct _EFI_DRIVER_CONFIGURATION_PROTOCOL EFI_DRIVER_CONFIGURATION_PROTOCOL;\r
\r
/**\r
Allows the user to set controller specific options for a controller that a\r
OUT EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED *ActionRequired\r
);\r
\r
-\r
///\r
/// Used to set configuration options for a controller that an EFI Driver is managing.\r
///\r
struct _EFI_DRIVER_CONFIGURATION_PROTOCOL {\r
- EFI_DRIVER_CONFIGURATION_SET_OPTIONS SetOptions;\r
- EFI_DRIVER_CONFIGURATION_OPTIONS_VALID OptionsValid;\r
- EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS ForceDefaults;\r
+ EFI_DRIVER_CONFIGURATION_SET_OPTIONS SetOptions;\r
+ EFI_DRIVER_CONFIGURATION_OPTIONS_VALID OptionsValid;\r
+ EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS ForceDefaults;\r
///\r
/// A Null-terminated ASCII string that contains one or more\r
/// ISO 639-2 language codes. This is the list of language\r
/// codes that this protocol supports.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-\r
-extern EFI_GUID gEfiDriverConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiDriverConfigurationProtocolGuid;\r
\r
#endif\r
0xbfd7dc1d, 0x24f1, 0x40d9, {0x82, 0xe7, 0x2e, 0x09, 0xbb, 0x6b, 0x4e, 0xbe } \\r
}\r
\r
-typedef struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL EFI_DRIVER_CONFIGURATION2_PROTOCOL;\r
+typedef struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL EFI_DRIVER_CONFIGURATION2_PROTOCOL;\r
\r
typedef enum {\r
///\r
/// The controller is still in a usable state. No actions\r
/// are required before this controller can be used again.\r
///\r
- EfiDriverConfigurationActionNone = 0,\r
+ EfiDriverConfigurationActionNone = 0,\r
///\r
/// The driver has detected that the controller is not in a\r
/// usable state, and it needs to be stopped.\r
///\r
- EfiDriverConfigurationActionStopController = 1,\r
+ EfiDriverConfigurationActionStopController = 1,\r
///\r
/// This controller needs to be stopped and restarted\r
/// before it can be used again.\r
/// A configuration change has been made that requires the platform to be restarted before\r
/// the controller can be used again.\r
///\r
- EfiDriverConfigurationActionRestartPlatform = 3,\r
+ EfiDriverConfigurationActionRestartPlatform = 3,\r
EfiDriverConfigurationActionMaximum\r
} EFI_DRIVER_CONFIGURATION_ACTION_REQUIRED;\r
\r
-#define EFI_DRIVER_CONFIGURATION_SAFE_DEFAULTS 0x00000000\r
-#define EFI_DRIVER_CONFIGURATION_MANUFACTURING_DEFAULTS 0x00000001\r
-#define EFI_DRIVER_CONFIGURATION_CUSTOM_DEFAULTS 0x00000002\r
-#define EFI_DRIVER_CONFIGURATION_PERORMANCE_DEFAULTS 0x00000003\r
+#define EFI_DRIVER_CONFIGURATION_SAFE_DEFAULTS 0x00000000\r
+#define EFI_DRIVER_CONFIGURATION_MANUFACTURING_DEFAULTS 0x00000001\r
+#define EFI_DRIVER_CONFIGURATION_CUSTOM_DEFAULTS 0x00000002\r
+#define EFI_DRIVER_CONFIGURATION_PERORMANCE_DEFAULTS 0x00000003\r
\r
/**\r
Allows the user to set controller specific options for a controller that a\r
/// Used to set configuration options for a controller that an EFI Driver is managing.\r
///\r
struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL {\r
- EFI_DRIVER_CONFIGURATION2_SET_OPTIONS SetOptions;\r
- EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID OptionsValid;\r
- EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS ForceDefaults;\r
+ EFI_DRIVER_CONFIGURATION2_SET_OPTIONS SetOptions;\r
+ EFI_DRIVER_CONFIGURATION2_OPTIONS_VALID OptionsValid;\r
+ EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS ForceDefaults;\r
///\r
/// A Null-terminated ASCII string that contains one or more RFC 4646\r
/// language codes. This is the list of language codes that this protocol supports.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiDriverConfiguration2ProtocolGuid;\r
+extern EFI_GUID gEfiDriverConfiguration2ProtocolGuid;\r
\r
#endif\r
0x0784924f, 0xe296, 0x11d4, {0x9a, 0x49, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL EFI_DRIVER_DIAGNOSTICS_PROTOCOL;\r
+typedef struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL EFI_DRIVER_DIAGNOSTICS_PROTOCOL;\r
\r
typedef enum {\r
///\r
/// Performs standard diagnostics on the controller.\r
///\r
- EfiDriverDiagnosticTypeStandard = 0,\r
+ EfiDriverDiagnosticTypeStandard = 0,\r
///\r
/// This is an optional diagnostic type that performs diagnostics on the controller that may\r
/// take an extended amount of time to execute.\r
///\r
- EfiDriverDiagnosticTypeExtended = 1,\r
+ EfiDriverDiagnosticTypeExtended = 1,\r
///\r
/// This is an optional diagnostic type that performs diagnostics on the controller that are\r
/// suitable for a manufacturing and test environment.\r
///\r
- EfiDriverDiagnosticTypeManufacturing= 2,\r
+ EfiDriverDiagnosticTypeManufacturing = 2,\r
///\r
/// This is an optional diagnostic type that would only be used in the situation where an\r
/// EFI_NOT_READY had been returned by a previous call to RunDiagnostics()\r
/// and there is a desire to cancel the current running diagnostics operation.\r
///\r
- EfiDriverDiagnosticTypeCancel = 3,\r
+ EfiDriverDiagnosticTypeCancel = 3,\r
EfiDriverDiagnosticTypeMaximum\r
} EFI_DRIVER_DIAGNOSTIC_TYPE;\r
\r
/// Used to perform diagnostics on a controller that an EFI Driver is managing.\r
///\r
struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL {\r
- EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS RunDiagnostics;\r
+ EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS RunDiagnostics;\r
///\r
/// A Null-terminated ASCII string that contains one or more ISO 639-2\r
/// language codes. This is the list of language codes that this protocol supports.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiDriverDiagnosticsProtocolGuid;\r
+extern EFI_GUID gEfiDriverDiagnosticsProtocolGuid;\r
\r
#endif\r
0x4d330321, 0x025f, 0x4aac, {0x90, 0xd8, 0x5e, 0xd9, 0x00, 0x17, 0x3b, 0x63 } \\r
}\r
\r
-typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL EFI_DRIVER_DIAGNOSTICS2_PROTOCOL;\r
+typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL EFI_DRIVER_DIAGNOSTICS2_PROTOCOL;\r
\r
/**\r
Runs diagnostics on a controller.\r
/// Used to perform diagnostics on a controller that an EFI Driver is managing.\r
///\r
struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL {\r
- EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics;\r
+ EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics;\r
///\r
/// A Null-terminated ASCII string that contains one or more RFC 4646\r
/// language codes. This is the list of language codes that this protocol supports.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiDriverDiagnostics2ProtocolGuid;\r
+extern EFI_GUID gEfiDriverDiagnostics2ProtocolGuid;\r
\r
#endif\r
0xb1ee129e, 0xda36, 0x4181, { 0x91, 0xf8, 0x4, 0xa4, 0x92, 0x37, 0x66, 0xa7 } \\r
}\r
\r
-typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL;\r
+typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL;\r
\r
//\r
// Prototypes for the Driver Family Override Protocol\r
//\r
//\r
+\r
/**\r
This function returns the version value associated with the driver specified by This.\r
\r
/// Bus Specific Driver Override Protocol.\r
///\r
struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL {\r
- EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion;\r
+ EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion;\r
};\r
\r
-extern EFI_GUID gEfiDriverFamilyOverrideProtocolGuid;\r
+extern EFI_GUID gEfiDriverFamilyOverrideProtocolGuid;\r
\r
#endif\r
0x2a534210, 0x9280, 0x41d8, { 0xae, 0x79, 0xca, 0xda, 0x1, 0xa2, 0xb1, 0x27 } \\r
}\r
\r
-typedef struct _EFI_DRIVER_HEALTH_PROTOCOL EFI_DRIVER_HEALTH_PROTOCOL;\r
+typedef struct _EFI_DRIVER_HEALTH_PROTOCOL EFI_DRIVER_HEALTH_PROTOCOL;\r
\r
///\r
/// EFI_DRIVER_HEALTH_HEALTH_STATUS\r
/// EFI_DRIVER_HEALTH_HII_MESSAGE\r
///\r
typedef struct {\r
- EFI_HII_HANDLE HiiHandle;\r
- EFI_STRING_ID StringId;\r
+ EFI_HII_HANDLE HiiHandle;\r
+ EFI_STRING_ID StringId;\r
\r
///\r
/// 64-bit numeric value of the warning/error specified by this message.\r
/// The values 0x8000000000000000 to 0x8fffffffffffffff is reserved for platform/OEM drivers.\r
/// All other values are reserved and should not be used.\r
///\r
- UINT64 MessageCode;\r
+ UINT64 MessageCode;\r
} EFI_DRIVER_HEALTH_HII_MESSAGE;\r
\r
/**\r
/// hardware configuration changes.\r
///\r
struct _EFI_DRIVER_HEALTH_PROTOCOL {\r
- EFI_DRIVER_HEALTH_GET_HEALTH_STATUS GetHealthStatus;\r
- EFI_DRIVER_HEALTH_REPAIR Repair;\r
+ EFI_DRIVER_HEALTH_GET_HEALTH_STATUS GetHealthStatus;\r
+ EFI_DRIVER_HEALTH_REPAIR Repair;\r
};\r
\r
-extern EFI_GUID gEfiDriverHealthProtocolGuid;\r
+extern EFI_GUID gEfiDriverHealthProtocolGuid;\r
\r
#endif\r
-\r
-\r
-\r
-\r
#define EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL_GUID \\r
{ 0x5c198761, 0x16a8, 0x4e69, { 0x97, 0x2c, 0x89, 0xd6, 0x79, 0x54, 0xf8, 0x1d } }\r
\r
-\r
///\r
/// The EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL provides a\r
/// mechanism for an EFI driver to publish the version of the EFI\r
/// The size, in bytes, of the entire structure. Future versions of this\r
/// specification may grow the size of the structure.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// The latest version of the UEFI specification that this driver conforms to.\r
///\r
- UINT32 FirmwareVersion;\r
+ UINT32 FirmwareVersion;\r
} EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL;\r
\r
-extern EFI_GUID gEfiDriverSupportedEfiVersionProtocolGuid;\r
+extern EFI_GUID gEfiDriverSupportedEfiVersionProtocolGuid;\r
\r
#endif\r
0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e } \\r
}\r
\r
-extern EFI_GUID gEfiDxeMmReadyToLockProtocolGuid;\r
+extern EFI_GUID gEfiDxeMmReadyToLockProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/DxeMmReadyToLock.h>\r
\r
-#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID\r
+#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID\r
\r
-extern EFI_GUID gEfiDxeSmmReadyToLockProtocolGuid;\r
+extern EFI_GUID gEfiDxeSmmReadyToLockProtocolGuid;\r
\r
#endif\r
#ifndef __EFI_EAP_PROTOCOL_H__\r
#define __EFI_EAP_PROTOCOL_H__\r
\r
-\r
#define EFI_EAP_PROTOCOL_GUID \\r
{ \\r
0x5d9f96db, 0xe731, 0x4caa, {0xa0, 0xd, 0x72, 0xe1, 0x87, 0xcd, 0x77, 0x62 } \\r
/// Type for the identification number assigned to the Port by the\r
/// System in which the Port resides.\r
///\r
-typedef VOID * EFI_PORT_HANDLE;\r
+typedef VOID *EFI_PORT_HANDLE;\r
\r
///\r
/// EAP Authentication Method Type (RFC 3748)\r
///@{\r
-#define EFI_EAP_TYPE_TLS 13 ///< REQUIRED - RFC 5216\r
+#define EFI_EAP_TYPE_TLS 13///< REQUIRED - RFC 5216\r
///@}\r
\r
//\r
// EAP_TYPE MD5, OTP and TOEKN_CARD has been removed from UEFI2.3.1B.\r
// Definitions are kept for backward compatibility.\r
//\r
-#define EFI_EAP_TYPE_MD5 4\r
-#define EFI_EAP_TYPE_OTP 5\r
-#define EFI_EAP_TYPE_TOKEN_CARD 6\r
+#define EFI_EAP_TYPE_MD5 4\r
+#define EFI_EAP_TYPE_OTP 5\r
+#define EFI_EAP_TYPE_TOKEN_CARD 6\r
\r
/**\r
One user provided EAP authentication method.\r
/// Port means a NIC. For the details of EAP protocol, please refer to RFC 2284.\r
///\r
struct _EFI_EAP_PROTOCOL {\r
- EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD SetDesiredAuthMethod;\r
- EFI_EAP_REGISTER_AUTHENTICATION_METHOD RegisterAuthMethod;\r
+ EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD SetDesiredAuthMethod;\r
+ EFI_EAP_REGISTER_AUTHENTICATION_METHOD RegisterAuthMethod;\r
};\r
\r
-extern EFI_GUID gEfiEapProtocolGuid;\r
+extern EFI_GUID gEfiEapProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Make sure it not conflict with any real EapTypeXXX\r
///\r
-#define EFI_EAP_TYPE_ATTRIBUTE 0\r
+#define EFI_EAP_TYPE_ATTRIBUTE 0\r
\r
typedef enum {\r
///\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_EAP_CONFIGURATION_SET_DATA) (\r
+(EFIAPI *EFI_EAP_CONFIGURATION_SET_DATA)(\r
IN EFI_EAP_CONFIGURATION_PROTOCOL *This,\r
IN EFI_EAP_TYPE EapType,\r
IN EFI_EAP_CONFIG_DATA_TYPE DataType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_EAP_CONFIGURATION_GET_DATA) (\r
+(EFIAPI *EFI_EAP_CONFIGURATION_GET_DATA)(\r
IN EFI_EAP_CONFIGURATION_PROTOCOL *This,\r
IN EFI_EAP_TYPE EapType,\r
IN EFI_EAP_CONFIG_DATA_TYPE DataType,\r
/// private key file.\r
///\r
struct _EFI_EAP_CONFIGURATION_PROTOCOL {\r
- EFI_EAP_CONFIGURATION_SET_DATA SetData;\r
- EFI_EAP_CONFIGURATION_GET_DATA GetData;\r
+ EFI_EAP_CONFIGURATION_SET_DATA SetData;\r
+ EFI_EAP_CONFIGURATION_GET_DATA GetData;\r
};\r
\r
-extern EFI_GUID gEfiEapConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiEapConfigurationProtocolGuid;\r
\r
#endif\r
/// PAE Capabilities\r
///\r
///@{\r
-#define PAE_SUPPORT_AUTHENTICATOR 0x01\r
-#define PAE_SUPPORT_SUPPLICANT 0x02\r
+#define PAE_SUPPORT_AUTHENTICATOR 0x01\r
+#define PAE_SUPPORT_SUPPLICANT 0x02\r
///@}\r
\r
///\r
/// The identification number assigned to the Port by the System in\r
/// which the Port resides.\r
///\r
- EFI_PORT_HANDLE PortNumber;\r
+ EFI_PORT_HANDLE PortNumber;\r
///\r
/// The protocol version number of the EAPOL implementation\r
/// supported by the Port.\r
///\r
- UINT8 ProtocolVersion;\r
+ UINT8 ProtocolVersion;\r
///\r
/// The capabilities of the PAE associated with the Port. This field\r
/// indicates whether Authenticator functionality, Supplicant\r
/// functionality, both, or neither, is supported by the Port's PAE.\r
///\r
- UINT8 PaeCapabilities;\r
+ UINT8 PaeCapabilities;\r
} EFI_EAPOL_PORT_INFO;\r
\r
///\r
/// Definitions for ValidFieldMask\r
///\r
///@{\r
-#define AUTH_PERIOD_FIELD_VALID 0x01\r
-#define HELD_PERIOD_FIELD_VALID 0x02\r
-#define START_PERIOD_FIELD_VALID 0x04\r
-#define MAX_START_FIELD_VALID 0x08\r
+#define AUTH_PERIOD_FIELD_VALID 0x01\r
+#define HELD_PERIOD_FIELD_VALID 0x02\r
+#define START_PERIOD_FIELD_VALID 0x04\r
+#define MAX_START_FIELD_VALID 0x08\r
///@}\r
\r
///\r
///\r
/// Indicates which of the following fields are valid.\r
///\r
- UINT8 ValidFieldMask;\r
+ UINT8 ValidFieldMask;\r
///\r
/// The initial value for the authWhile timer. Its default value is 30s.\r
///\r
- UINTN AuthPeriod;\r
+ UINTN AuthPeriod;\r
///\r
/// The initial value for the heldWhile timer. Its default value is 60s.\r
///\r
- UINTN HeldPeriod;\r
+ UINTN HeldPeriod;\r
///\r
/// The initial value for the startWhen timer. Its default value is 30s.\r
///\r
- UINTN StartPeriod;\r
+ UINTN StartPeriod;\r
///\r
/// The maximum number of successive EAPOL-Start messages will\r
/// be sent before the Supplicant assumes that there is no\r
/// Authenticator present. Its default value is 3.\r
///\r
- UINTN MaxStart;\r
+ UINTN MaxStart;\r
} EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION;\r
\r
///\r
///\r
/// The number of EAPOL frames of any type that have been received by this Supplican.\r
///\r
- UINTN EapolFramesReceived;\r
+ UINTN EapolFramesReceived;\r
///\r
/// The number of EAPOL frames of any type that have been transmitted by this Supplicant.\r
///\r
- UINTN EapolFramesTransmitted;\r
+ UINTN EapolFramesTransmitted;\r
///\r
/// The number of EAPOL Start frames that have been transmitted by this Supplicant.\r
///\r
- UINTN EapolStartFramesTransmitted;\r
+ UINTN EapolStartFramesTransmitted;\r
///\r
/// The number of EAPOL Logoff frames that have been transmitted by this Supplicant.\r
///\r
- UINTN EapolLogoffFramesTransmitted;\r
+ UINTN EapolLogoffFramesTransmitted;\r
///\r
/// The number of EAP Resp/Id frames that have been transmitted by this Supplicant.\r
///\r
- UINTN EapRespIdFramesTransmitted;\r
+ UINTN EapRespIdFramesTransmitted;\r
///\r
/// The number of valid EAP Response frames (other than Resp/Id frames) that have been\r
/// transmitted by this Supplicant.\r
///\r
- UINTN EapResponseFramesTransmitted;\r
+ UINTN EapResponseFramesTransmitted;\r
///\r
/// The number of EAP Req/Id frames that have been received by this Supplicant.\r
///\r
- UINTN EapReqIdFramesReceived;\r
+ UINTN EapReqIdFramesReceived;\r
///\r
/// The number of EAP Request frames (other than Rq/Id frames) that have been received\r
/// by this Supplicant.\r
///\r
- UINTN EapRequestFramesReceived;\r
+ UINTN EapRequestFramesReceived;\r
///\r
/// The number of EAPOL frames that have been received by this Supplicant in which the\r
/// frame type is not recognized.\r
///\r
- UINTN InvalidEapolFramesReceived;\r
+ UINTN InvalidEapolFramesReceived;\r
///\r
/// The number of EAPOL frames that have been received by this Supplicant in which the\r
/// Packet Body Length field (7.5.5) is invalid.\r
///\r
- UINTN EapLengthErrorFramesReceived;\r
+ UINTN EapLengthErrorFramesReceived;\r
///\r
/// The protocol version number carried in the most recently received EAPOL frame.\r
///\r
- UINTN LastEapolFrameVersion;\r
+ UINTN LastEapolFrameVersion;\r
///\r
/// The source MAC address carried in the most recently received EAPOL frame.\r
///\r
- UINTN LastEapolFrameSource;\r
+ UINTN LastEapolFrameSource;\r
} EFI_EAPOL_SUPPLICANT_PAE_STATISTICS;\r
\r
/**\r
EFI_EAP_GET_SUPPLICANT_STATISTICS GetSupplicantStatistics;\r
};\r
\r
-extern EFI_GUID gEfiEapManagementProtocolGuid;\r
+extern EFI_GUID gEfiEapManagementProtocolGuid;\r
\r
#endif\r
-\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_EAP_GET_KEY) (\r
+(EFIAPI *EFI_EAP_GET_KEY)(\r
IN EFI_EAP_MANAGEMENT2_PROTOCOL *This,\r
IN OUT UINT8 *Msk,\r
IN OUT UINTN *MskSize,\r
EFI_EAP_GET_KEY GetKey;\r
};\r
\r
-extern EFI_GUID gEfiEapManagement2ProtocolGuid;\r
+extern EFI_GUID gEfiEapManagement2ProtocolGuid;\r
\r
#endif\r
//\r
// #define OPCODE_27 0x27\r
//\r
-#define OPCODE_MOVQQ 0x28 // Does this go away?\r
-#define OPCODE_LOADSP 0x29\r
-#define OPCODE_STORESP 0x2A\r
-#define OPCODE_PUSH 0x2B\r
-#define OPCODE_POP 0x2C\r
-#define OPCODE_CMPIEQ 0x2D\r
-#define OPCODE_CMPILTE 0x2E\r
-#define OPCODE_CMPIGTE 0x2F\r
-#define OPCODE_CMPIULTE 0x30\r
-#define OPCODE_CMPIUGTE 0x31\r
-#define OPCODE_MOVNW 0x32\r
-#define OPCODE_MOVND 0x33\r
+#define OPCODE_MOVQQ 0x28 // Does this go away?\r
+#define OPCODE_LOADSP 0x29\r
+#define OPCODE_STORESP 0x2A\r
+#define OPCODE_PUSH 0x2B\r
+#define OPCODE_POP 0x2C\r
+#define OPCODE_CMPIEQ 0x2D\r
+#define OPCODE_CMPILTE 0x2E\r
+#define OPCODE_CMPIGTE 0x2F\r
+#define OPCODE_CMPIULTE 0x30\r
+#define OPCODE_CMPIUGTE 0x31\r
+#define OPCODE_MOVNW 0x32\r
+#define OPCODE_MOVND 0x33\r
//\r
// #define OPCODE_34 0x34\r
//\r
-#define OPCODE_PUSHN 0x35\r
-#define OPCODE_POPN 0x36\r
-#define OPCODE_MOVI 0x37\r
-#define OPCODE_MOVIN 0x38\r
-#define OPCODE_MOVREL 0x39\r
+#define OPCODE_PUSHN 0x35\r
+#define OPCODE_POPN 0x36\r
+#define OPCODE_MOVI 0x37\r
+#define OPCODE_MOVIN 0x38\r
+#define OPCODE_MOVREL 0x39\r
\r
//\r
// Bit masks for opcode encodings\r
//\r
// Bit masks for operand encodings\r
//\r
-#define OPERAND_M_INDIRECT1 0x08\r
-#define OPERAND_M_INDIRECT2 0x80\r
-#define OPERAND_M_OP1 0x07\r
-#define OPERAND_M_OP2 0x70\r
+#define OPERAND_M_INDIRECT1 0x08\r
+#define OPERAND_M_INDIRECT2 0x80\r
+#define OPERAND_M_OP1 0x07\r
+#define OPERAND_M_OP2 0x70\r
\r
//\r
// Masks for data manipulation instructions\r
//\r
-#define DATAMANIP_M_64 0x40 // 64-bit width operation\r
-#define DATAMANIP_M_IMMDATA 0x80\r
+#define DATAMANIP_M_64 0x40 // 64-bit width operation\r
+#define DATAMANIP_M_IMMDATA 0x80\r
\r
//\r
// For MOV instructions, need a mask for the opcode when immediate\r
//\r
// Masks for CALL instruction encodings\r
//\r
-#define OPERAND_M_RELATIVE_ADDR 0x10\r
-#define OPERAND_M_NATIVE_CALL 0x20\r
+#define OPERAND_M_RELATIVE_ADDR 0x10\r
+#define OPERAND_M_NATIVE_CALL 0x20\r
\r
//\r
// Masks for decoding push/pop instructions\r
//\r
-#define PUSHPOP_M_IMMDATA 0x80 // opcode bit indicating immediate data\r
-#define PUSHPOP_M_64 0x40 // opcode bit indicating 64-bit operation\r
+#define PUSHPOP_M_IMMDATA 0x80 // opcode bit indicating immediate data\r
+#define PUSHPOP_M_64 0x40 // opcode bit indicating 64-bit operation\r
//\r
// Mask for operand of JMP instruction\r
//\r
-#define JMP_M_RELATIVE 0x10\r
-#define JMP_M_CONDITIONAL 0x80\r
-#define JMP_M_CS 0x40\r
+#define JMP_M_RELATIVE 0x10\r
+#define JMP_M_CONDITIONAL 0x80\r
+#define JMP_M_CS 0x40\r
\r
//\r
// Macros to determine if a given operand is indirect\r
//\r
-#define OPERAND1_INDIRECT(op) ((op) & OPERAND_M_INDIRECT1)\r
-#define OPERAND2_INDIRECT(op) ((op) & OPERAND_M_INDIRECT2)\r
+#define OPERAND1_INDIRECT(op) ((op) & OPERAND_M_INDIRECT1)\r
+#define OPERAND2_INDIRECT(op) ((op) & OPERAND_M_INDIRECT2)\r
\r
//\r
// Macros to extract the operands from second byte of instructions\r
//\r
-#define OPERAND1_REGNUM(op) ((op) & OPERAND_M_OP1)\r
-#define OPERAND2_REGNUM(op) (((op) & OPERAND_M_OP2) >> 4)\r
+#define OPERAND1_REGNUM(op) ((op) & OPERAND_M_OP1)\r
+#define OPERAND2_REGNUM(op) (((op) & OPERAND_M_OP2) >> 4)\r
\r
-#define OPERAND1_CHAR(op) ('0' + OPERAND1_REGNUM (op))\r
-#define OPERAND2_CHAR(op) ('0' + OPERAND2_REGNUM (op))\r
+#define OPERAND1_CHAR(op) ('0' + OPERAND1_REGNUM (op))\r
+#define OPERAND2_CHAR(op) ('0' + OPERAND2_REGNUM (op))\r
\r
//\r
// Condition masks usually for byte 1 encodings of code\r
//\r
-#define CONDITION_M_CONDITIONAL 0x80\r
-#define CONDITION_M_CS 0x40\r
+#define CONDITION_M_CONDITIONAL 0x80\r
+#define CONDITION_M_CS 0x40\r
\r
///\r
/// Protocol Guid Name defined in spec.\r
///\r
-#define EFI_EBC_PROTOCOL_GUID EFI_EBC_INTERPRETER_PROTOCOL_GUID\r
+#define EFI_EBC_PROTOCOL_GUID EFI_EBC_INTERPRETER_PROTOCOL_GUID\r
\r
///\r
/// Define for forward reference.\r
/// image can then be run using the standard EFI start image services.\r
///\r
struct _EFI_EBC_PROTOCOL {\r
- EFI_EBC_CREATE_THUNK CreateThunk;\r
- EFI_EBC_UNLOAD_IMAGE UnloadImage;\r
- EFI_EBC_REGISTER_ICACHE_FLUSH RegisterICacheFlush;\r
- EFI_EBC_GET_VERSION GetVersion;\r
+ EFI_EBC_CREATE_THUNK CreateThunk;\r
+ EFI_EBC_UNLOAD_IMAGE UnloadImage;\r
+ EFI_EBC_REGISTER_ICACHE_FLUSH RegisterICacheFlush;\r
+ EFI_EBC_GET_VERSION GetVersion;\r
};\r
\r
//\r
// Extern the global EBC protocol GUID\r
//\r
-extern EFI_GUID gEfiEbcProtocolGuid;\r
+extern EFI_GUID gEfiEbcProtocolGuid;\r
\r
#endif\r
/// is available from the video output device. Otherwise, it must be a\r
/// minimum of 128 bytes.\r
///\r
- UINT32 SizeOfEdid;\r
+ UINT32 SizeOfEdid;\r
\r
///\r
/// A pointer to a read-only array of bytes that contains the EDID\r
UINT8 *Edid;\r
} EFI_EDID_ACTIVE_PROTOCOL;\r
\r
-extern EFI_GUID gEfiEdidActiveProtocolGuid;\r
+extern EFI_GUID gEfiEdidActiveProtocolGuid;\r
\r
#endif\r
/// is available from the video output device. Otherwise, it must be a\r
/// minimum of 128 bytes.\r
///\r
- UINT32 SizeOfEdid;\r
+ UINT32 SizeOfEdid;\r
\r
///\r
/// A pointer to a read-only array of bytes that contains the EDID\r
UINT8 *Edid;\r
} EFI_EDID_DISCOVERED_PROTOCOL;\r
\r
-extern EFI_GUID gEfiEdidDiscoveredProtocolGuid;\r
+extern EFI_GUID gEfiEdidDiscoveredProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_EDID_OVERRIDE_PROTOCOL EFI_EDID_OVERRIDE_PROTOCOL;\r
\r
-#define EFI_EDID_OVERRIDE_DONT_OVERRIDE 0x01\r
-#define EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG 0x02\r
+#define EFI_EDID_OVERRIDE_DONT_OVERRIDE 0x01\r
+#define EFI_EDID_OVERRIDE_ENABLE_HOT_PLUG 0x02\r
\r
/**\r
Returns policy information and potentially a replacement EDID for the specified video output device.\r
/// EDID information to the producer of the Graphics Output protocol.\r
///\r
struct _EFI_EDID_OVERRIDE_PROTOCOL {\r
- EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID GetEdid;\r
+ EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID GetEdid;\r
};\r
\r
-extern EFI_GUID gEfiEdidOverrideProtocolGuid;\r
+extern EFI_GUID gEfiEdidOverrideProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_ERASE_BLOCK_PROTOCOL EFI_ERASE_BLOCK_PROTOCOL;\r
\r
-#define EFI_ERASE_BLOCK_PROTOCOL_REVISION ((2<<16) | (60))\r
+#define EFI_ERASE_BLOCK_PROTOCOL_REVISION ((2<<16) | (60))\r
\r
///\r
/// EFI_ERASE_BLOCK_TOKEN\r
// non-blocking I/O is supported, then non-blocking I/O is performed, and\r
// Event will be signaled when the erase request is completed.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
//\r
// Defines whether the signaled event encountered an error.\r
//\r
- EFI_STATUS TransactionStatus;\r
+ EFI_STATUS TransactionStatus;\r
} EFI_ERASE_BLOCK_TOKEN;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_BLOCK_ERASE) (\r
+(EFIAPI *EFI_BLOCK_ERASE)(\r
IN EFI_ERASE_BLOCK_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN EFI_LBA LBA,\r
// revisions must be backwards compatible. If a future version is not\r
// backwards compatible, it is not the same GUID.\r
//\r
- UINT64 Revision;\r
+ UINT64 Revision;\r
//\r
// Returns the erase length granularity as a number of logical blocks. A\r
// value of 1 means the erase granularity is one logical block.\r
//\r
- UINT32 EraseLengthGranularity;\r
- EFI_BLOCK_ERASE EraseBlocks;\r
+ UINT32 EraseLengthGranularity;\r
+ EFI_BLOCK_ERASE EraseBlocks;\r
};\r
\r
-extern EFI_GUID gEfiEraseBlockProtocolGuid;\r
+extern EFI_GUID gEfiEraseBlockProtocolGuid;\r
\r
#endif\r
#ifndef __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__\r
#define __EFI_FIRMWARE_MANAGEMENT_PROTOCOL_H__\r
\r
-\r
#define EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GUID \\r
{ \\r
0x86c77a67, 0xb97, 0x4633, {0xa1, 0x87, 0x49, 0x10, 0x4d, 0x6, 0x85, 0xc7 } \\r
///\r
/// Dependency Expression Opcode\r
///\r
-#define EFI_FMP_DEP_PUSH_GUID 0x00\r
-#define EFI_FMP_DEP_PUSH_VERSION 0x01\r
-#define EFI_FMP_DEP_VERSION_STR 0x02\r
-#define EFI_FMP_DEP_AND 0x03\r
-#define EFI_FMP_DEP_OR 0x04\r
-#define EFI_FMP_DEP_NOT 0x05\r
-#define EFI_FMP_DEP_TRUE 0x06\r
-#define EFI_FMP_DEP_FALSE 0x07\r
-#define EFI_FMP_DEP_EQ 0x08\r
-#define EFI_FMP_DEP_GT 0x09\r
-#define EFI_FMP_DEP_GTE 0x0A\r
-#define EFI_FMP_DEP_LT 0x0B\r
-#define EFI_FMP_DEP_LTE 0x0C\r
-#define EFI_FMP_DEP_END 0x0D\r
+#define EFI_FMP_DEP_PUSH_GUID 0x00\r
+#define EFI_FMP_DEP_PUSH_VERSION 0x01\r
+#define EFI_FMP_DEP_VERSION_STR 0x02\r
+#define EFI_FMP_DEP_AND 0x03\r
+#define EFI_FMP_DEP_OR 0x04\r
+#define EFI_FMP_DEP_NOT 0x05\r
+#define EFI_FMP_DEP_TRUE 0x06\r
+#define EFI_FMP_DEP_FALSE 0x07\r
+#define EFI_FMP_DEP_EQ 0x08\r
+#define EFI_FMP_DEP_GT 0x09\r
+#define EFI_FMP_DEP_GTE 0x0A\r
+#define EFI_FMP_DEP_LT 0x0B\r
+#define EFI_FMP_DEP_LTE 0x0C\r
+#define EFI_FMP_DEP_END 0x0D\r
\r
///\r
/// Image Attribute - Dependency\r
///\r
typedef struct {\r
- UINT8 Dependencies[1];\r
+ UINT8 Dependencies[1];\r
} EFI_FIRMWARE_IMAGE_DEP;\r
\r
///\r
/// A unique number identifying the firmware image within the device. The number is\r
/// between 1 and DescriptorCount.\r
///\r
- UINT8 ImageIndex;\r
+ UINT8 ImageIndex;\r
///\r
/// A unique GUID identifying the firmware image type.\r
///\r
- EFI_GUID ImageTypeId;\r
+ EFI_GUID ImageTypeId;\r
///\r
/// A unique number identifying the firmware image.\r
///\r
- UINT64 ImageId;\r
+ UINT64 ImageId;\r
///\r
/// A pointer to a null-terminated string representing the firmware image name.\r
///\r
- CHAR16 *ImageIdName;\r
+ CHAR16 *ImageIdName;\r
///\r
/// Identifies the version of the device firmware. The format is vendor specific and new\r
/// version must have a greater value than an old version.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// A pointer to a null-terminated string representing the firmware image version name.\r
///\r
- CHAR16 *VersionName;\r
+ CHAR16 *VersionName;\r
///\r
/// Size of the image in bytes. If size=0, then only ImageIndex and ImageTypeId are valid.\r
///\r
- UINTN Size;\r
+ UINTN Size;\r
///\r
/// Image attributes that are supported by this device. See 'Image Attribute Definitions'\r
/// for possible returned values of this parameter. A value of 1 indicates the attribute is\r
/// value of 0 indicates the attribute is not supported and the current setting value in\r
/// AttributesSetting is meaningless.\r
///\r
- UINT64 AttributesSupported;\r
+ UINT64 AttributesSupported;\r
///\r
/// Image attributes. See 'Image Attribute Definitions' for possible returned values of\r
/// this parameter.\r
///\r
- UINT64 AttributesSetting;\r
+ UINT64 AttributesSetting;\r
///\r
/// Image compatibilities. See 'Image Compatibility Definitions' for possible returned\r
/// values of this parameter.\r
///\r
- UINT64 Compatibilities;\r
+ UINT64 Compatibilities;\r
///\r
/// Describes the lowest ImageDescriptor version that the device will accept. Only\r
/// present in version 2 or higher.\r
///\r
- UINT32 LowestSupportedImageVersion;\r
+ UINT32 LowestSupportedImageVersion;\r
///\r
/// Describes the version that was last attempted to update. If no update attempted the\r
/// value will be 0. If the update attempted was improperly formatted and no version\r
/// number was available then the value will be zero. Only present in version 3 or higher.\r
- UINT32 LastAttemptVersion;\r
+ UINT32 LastAttemptVersion;\r
///\r
/// Describes the status that was last attempted to update. If no update has been attempted\r
/// the value will be LAST_ATTEMPT_STATUS_SUCCESS. Only present in version 3 or higher.\r
///\r
- UINT32 LastAttemptStatus;\r
+ UINT32 LastAttemptStatus;\r
///\r
/// An optional number to identify the unique hardware instance within the system for\r
/// devices that may have multiple instances (Example: a plug in pci network card). This\r
/// unique hardware instance number or a hardware instance number is not needed. Only\r
/// present in version 3 or higher.\r
///\r
- UINT64 HardwareInstance;\r
- EFI_FIRMWARE_IMAGE_DEP *Dependencies;\r
+ UINT64 HardwareInstance;\r
+ EFI_FIRMWARE_IMAGE_DEP *Dependencies;\r
} EFI_FIRMWARE_IMAGE_DESCRIPTOR;\r
\r
-\r
//\r
// Image Attribute Definitions\r
//\r
/// The attribute IMAGE_ATTRIBUTE_IMAGE_UPDATABLE indicates this device supports firmware\r
/// image update.\r
///\r
-#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001\r
+#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE 0x0000000000000001\r
///\r
/// The attribute IMAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is required\r
/// for the new firmware image to take effect after a firmware update. The device is the device hosting\r
/// the firmware image.\r
///\r
-#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002\r
+#define IMAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002\r
///\r
/// The attribute IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication is\r
/// required to perform the following image operations: GetImage(), SetImage(), and\r
/// CheckImage(). See 'Image Attribute - Authentication'.\r
///\r
-#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004\r
+#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004\r
///\r
/// The attribute IMAGE_ATTRIBUTE_IN_USE indicates the current state of the firmware image.\r
/// This distinguishes firmware images in a device that supports redundant images.\r
///\r
-#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008\r
+#define IMAGE_ATTRIBUTE_IN_USE 0x0000000000000008\r
///\r
/// The attribute IMAGE_ATTRIBUTE_UEFI_IMAGE indicates that this image is an EFI compatible image.\r
///\r
-#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010\r
+#define IMAGE_ATTRIBUTE_UEFI_IMAGE 0x0000000000000010\r
///\r
/// The attribute IMAGE_ATTRIBUTE_DEPENDENCY indicates that there is an EFI_FIRMWARE_IMAGE_DEP\r
/// section associated with the image.\r
///\r
-#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020\r
-\r
+#define IMAGE_ATTRIBUTE_DEPENDENCY 0x0000000000000020\r
\r
//\r
// Image Compatibility Definitions\r
/// Values from 0x0000000000010000 thru 0xFFFFFFFFFFFFFFFF are used by firmware vendor for\r
/// compatibility check.\r
///\r
-#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001\r
+#define IMAGE_COMPATIBILITY_CHECK_SUPPORTED 0x0000000000000001\r
\r
///\r
/// Descriptor Version exposed by GetImageInfo() function\r
///\r
-#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4\r
-\r
+#define EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION 4\r
\r
///\r
/// Image Attribute - Authentication Required\r
/// It is included in the signature of AuthInfo. It is used to ensure freshness/no replay.\r
/// It is incremented during each firmware image operation.\r
///\r
- UINT64 MonotonicCount;\r
+ UINT64 MonotonicCount;\r
///\r
/// Provides the authorization for the firmware image operations. It is a signature across\r
/// the image data and the Monotonic Count value. Caller uses the private key that is\r
/// Because this is defined as a signature, WIN_CERTIFICATE_UEFI_GUID.CertType must\r
/// be EFI_CERT_TYPE_PKCS7_GUID.\r
///\r
- WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
} EFI_FIRMWARE_IMAGE_AUTHENTICATION;\r
\r
-\r
//\r
// ImageUpdatable Definitions\r
//\r
/// the current image. SetImage VendorCode is optional but can be used for vendor\r
/// specific action.\r
///\r
-#define IMAGE_UPDATABLE_VALID 0x0000000000000001\r
+#define IMAGE_UPDATABLE_VALID 0x0000000000000001\r
///\r
/// IMAGE_UPDATABLE_INVALID indicates SetImage() will reject the new image. No additional\r
/// information is provided for the rejection.\r
///\r
-#define IMAGE_UPDATABLE_INVALID 0x0000000000000002\r
+#define IMAGE_UPDATABLE_INVALID 0x0000000000000002\r
///\r
/// IMAGE_UPDATABLE_INVALID_TYPE indicates SetImage() will reject the new image. The\r
/// rejection is due to the new image is not a firmware image recognized for this device.\r
///\r
-#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004\r
+#define IMAGE_UPDATABLE_INVALID_TYPE 0x0000000000000004\r
///\r
/// IMAGE_UPDATABLE_INVALID_OLD indicates SetImage() will reject the new image. The\r
/// rejection is due to the new image version is older than the current firmware image\r
/// version in the device. The device firmware update policy does not support firmware\r
/// version downgrade.\r
///\r
-#define IMAGE_UPDATABLE_INVALID_OLD 0x0000000000000008\r
+#define IMAGE_UPDATABLE_INVALID_OLD 0x0000000000000008\r
///\r
/// IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE indicates SetImage() will accept and update\r
/// the new image only if a correct VendorCode is provided or else image would be\r
/// rejected and SetImage will return appropriate error.\r
///\r
-#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0000000000000010\r
-\r
+#define IMAGE_UPDATABLE_VALID_WITH_VENDOR_CODE 0x0000000000000010\r
\r
//\r
// Package Attribute Definitions\r
/// The attribute PACKAGE_ATTRIBUTE_VERSION_UPDATABLE indicates this device supports the\r
/// update of the firmware package version.\r
///\r
-#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001\r
+#define PACKAGE_ATTRIBUTE_VERSION_UPDATABLE 0x0000000000000001\r
///\r
/// The attribute PACKAGE_ATTRIBUTE_RESET_REQUIRED indicates a reset of the device is\r
/// required for the new package info to take effect after an update.\r
///\r
-#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002\r
+#define PACKAGE_ATTRIBUTE_RESET_REQUIRED 0x0000000000000002\r
///\r
/// The attribute PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED indicates authentication\r
/// is required to update the package info.\r
///\r
-#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004\r
+#define PACKAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED 0x0000000000000004\r
\r
/**\r
Callback function to report the process of the firmware updating.\r
/// - Label all the firmware images within a device with a single version.\r
///\r
struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL {\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO GetImageInfo;\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE GetImage;\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE SetImage;\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE CheckImage;\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO GetPackageInfo;\r
- EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO SetPackageInfo;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE_INFO GetImageInfo;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE GetImage;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_IMAGE SetImage;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_CHECK_IMAGE CheckImage;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_PACKAGE_INFO GetPackageInfo;\r
+ EFI_FIRMWARE_MANAGEMENT_PROTOCOL_SET_PACKAGE_INFO SetPackageInfo;\r
};\r
\r
-extern EFI_GUID gEfiFirmwareManagementProtocolGuid;\r
+extern EFI_GUID gEfiFirmwareManagementProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_FIRMWARE_VOLUME2_PROTOCOL EFI_FIRMWARE_VOLUME2_PROTOCOL;\r
\r
-\r
///\r
/// EFI_FV_ATTRIBUTES\r
///\r
-typedef UINT64 EFI_FV_ATTRIBUTES;\r
+typedef UINT64 EFI_FV_ATTRIBUTES;\r
\r
//\r
// EFI_FV_ATTRIBUTES bit definitions\r
//\r
// EFI_FV_ATTRIBUTES bit semantics\r
-#define EFI_FV2_READ_DISABLE_CAP 0x0000000000000001ULL\r
-#define EFI_FV2_READ_ENABLE_CAP 0x0000000000000002ULL\r
-#define EFI_FV2_READ_STATUS 0x0000000000000004ULL\r
-#define EFI_FV2_WRITE_DISABLE_CAP 0x0000000000000008ULL\r
-#define EFI_FV2_WRITE_ENABLE_CAP 0x0000000000000010ULL\r
-#define EFI_FV2_WRITE_STATUS 0x0000000000000020ULL\r
-#define EFI_FV2_LOCK_CAP 0x0000000000000040ULL\r
-#define EFI_FV2_LOCK_STATUS 0x0000000000000080ULL\r
-#define EFI_FV2_WRITE_POLICY_RELIABLE 0x0000000000000100ULL\r
-#define EFI_FV2_READ_LOCK_CAP 0x0000000000001000ULL\r
-#define EFI_FV2_READ_LOCK_STATUS 0x0000000000002000ULL\r
-#define EFI_FV2_WRITE_LOCK_CAP 0x0000000000004000ULL\r
-#define EFI_FV2_WRITE_LOCK_STATUS 0x0000000000008000ULL\r
-#define EFI_FV2_ALIGNMENT 0x00000000001F0000ULL\r
-#define EFI_FV2_ALIGNMENT_1 0x0000000000000000ULL\r
-#define EFI_FV2_ALIGNMENT_2 0x0000000000010000ULL\r
-#define EFI_FV2_ALIGNMENT_4 0x0000000000020000ULL\r
-#define EFI_FV2_ALIGNMENT_8 0x0000000000030000ULL\r
-#define EFI_FV2_ALIGNMENT_16 0x0000000000040000ULL\r
-#define EFI_FV2_ALIGNMENT_32 0x0000000000050000ULL\r
-#define EFI_FV2_ALIGNMENT_64 0x0000000000060000ULL\r
-#define EFI_FV2_ALIGNMENT_128 0x0000000000070000ULL\r
-#define EFI_FV2_ALIGNMENT_256 0x0000000000080000ULL\r
-#define EFI_FV2_ALIGNMENT_512 0x0000000000090000ULL\r
-#define EFI_FV2_ALIGNMENT_1K 0x00000000000A0000ULL\r
-#define EFI_FV2_ALIGNMENT_2K 0x00000000000B0000ULL\r
-#define EFI_FV2_ALIGNMENT_4K 0x00000000000C0000ULL\r
-#define EFI_FV2_ALIGNMENT_8K 0x00000000000D0000ULL\r
-#define EFI_FV2_ALIGNMENT_16K 0x00000000000E0000ULL\r
-#define EFI_FV2_ALIGNMENT_32K 0x00000000000F0000ULL\r
-#define EFI_FV2_ALIGNMENT_64K 0x0000000000100000ULL\r
-#define EFI_FV2_ALIGNMENT_128K 0x0000000000110000ULL\r
-#define EFI_FV2_ALIGNMENT_256K 0x0000000000120000ULL\r
-#define EFI_FV2_ALIGNMENT_512K 0x0000000000130000ULL\r
-#define EFI_FV2_ALIGNMENT_1M 0x0000000000140000ULL\r
-#define EFI_FV2_ALIGNMENT_2M 0x0000000000150000ULL\r
-#define EFI_FV2_ALIGNMENT_4M 0x0000000000160000ULL\r
-#define EFI_FV2_ALIGNMENT_8M 0x0000000000170000ULL\r
-#define EFI_FV2_ALIGNMENT_16M 0x0000000000180000ULL\r
-#define EFI_FV2_ALIGNMENT_32M 0x0000000000190000ULL\r
-#define EFI_FV2_ALIGNMENT_64M 0x00000000001A0000ULL\r
-#define EFI_FV2_ALIGNMENT_128M 0x00000000001B0000ULL\r
-#define EFI_FV2_ALIGNMENT_256M 0x00000000001C0000ULL\r
-#define EFI_FV2_ALIGNMENT_512M 0x00000000001D0000ULL\r
-#define EFI_FV2_ALIGNMENT_1G 0x00000000001E0000ULL\r
-#define EFI_FV2_ALIGNMENT_2G 0x00000000001F0000ULL\r
+#define EFI_FV2_READ_DISABLE_CAP 0x0000000000000001ULL\r
+#define EFI_FV2_READ_ENABLE_CAP 0x0000000000000002ULL\r
+#define EFI_FV2_READ_STATUS 0x0000000000000004ULL\r
+#define EFI_FV2_WRITE_DISABLE_CAP 0x0000000000000008ULL\r
+#define EFI_FV2_WRITE_ENABLE_CAP 0x0000000000000010ULL\r
+#define EFI_FV2_WRITE_STATUS 0x0000000000000020ULL\r
+#define EFI_FV2_LOCK_CAP 0x0000000000000040ULL\r
+#define EFI_FV2_LOCK_STATUS 0x0000000000000080ULL\r
+#define EFI_FV2_WRITE_POLICY_RELIABLE 0x0000000000000100ULL\r
+#define EFI_FV2_READ_LOCK_CAP 0x0000000000001000ULL\r
+#define EFI_FV2_READ_LOCK_STATUS 0x0000000000002000ULL\r
+#define EFI_FV2_WRITE_LOCK_CAP 0x0000000000004000ULL\r
+#define EFI_FV2_WRITE_LOCK_STATUS 0x0000000000008000ULL\r
+#define EFI_FV2_ALIGNMENT 0x00000000001F0000ULL\r
+#define EFI_FV2_ALIGNMENT_1 0x0000000000000000ULL\r
+#define EFI_FV2_ALIGNMENT_2 0x0000000000010000ULL\r
+#define EFI_FV2_ALIGNMENT_4 0x0000000000020000ULL\r
+#define EFI_FV2_ALIGNMENT_8 0x0000000000030000ULL\r
+#define EFI_FV2_ALIGNMENT_16 0x0000000000040000ULL\r
+#define EFI_FV2_ALIGNMENT_32 0x0000000000050000ULL\r
+#define EFI_FV2_ALIGNMENT_64 0x0000000000060000ULL\r
+#define EFI_FV2_ALIGNMENT_128 0x0000000000070000ULL\r
+#define EFI_FV2_ALIGNMENT_256 0x0000000000080000ULL\r
+#define EFI_FV2_ALIGNMENT_512 0x0000000000090000ULL\r
+#define EFI_FV2_ALIGNMENT_1K 0x00000000000A0000ULL\r
+#define EFI_FV2_ALIGNMENT_2K 0x00000000000B0000ULL\r
+#define EFI_FV2_ALIGNMENT_4K 0x00000000000C0000ULL\r
+#define EFI_FV2_ALIGNMENT_8K 0x00000000000D0000ULL\r
+#define EFI_FV2_ALIGNMENT_16K 0x00000000000E0000ULL\r
+#define EFI_FV2_ALIGNMENT_32K 0x00000000000F0000ULL\r
+#define EFI_FV2_ALIGNMENT_64K 0x0000000000100000ULL\r
+#define EFI_FV2_ALIGNMENT_128K 0x0000000000110000ULL\r
+#define EFI_FV2_ALIGNMENT_256K 0x0000000000120000ULL\r
+#define EFI_FV2_ALIGNMENT_512K 0x0000000000130000ULL\r
+#define EFI_FV2_ALIGNMENT_1M 0x0000000000140000ULL\r
+#define EFI_FV2_ALIGNMENT_2M 0x0000000000150000ULL\r
+#define EFI_FV2_ALIGNMENT_4M 0x0000000000160000ULL\r
+#define EFI_FV2_ALIGNMENT_8M 0x0000000000170000ULL\r
+#define EFI_FV2_ALIGNMENT_16M 0x0000000000180000ULL\r
+#define EFI_FV2_ALIGNMENT_32M 0x0000000000190000ULL\r
+#define EFI_FV2_ALIGNMENT_64M 0x00000000001A0000ULL\r
+#define EFI_FV2_ALIGNMENT_128M 0x00000000001B0000ULL\r
+#define EFI_FV2_ALIGNMENT_256M 0x00000000001C0000ULL\r
+#define EFI_FV2_ALIGNMENT_512M 0x00000000001D0000ULL\r
+#define EFI_FV2_ALIGNMENT_1G 0x00000000001E0000ULL\r
+#define EFI_FV2_ALIGNMENT_2G 0x00000000001F0000ULL\r
\r
/**\r
Returns the attributes and current settings of the firmware volume.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_GET_ATTRIBUTES)(\r
+(EFIAPI *EFI_FV_GET_ATTRIBUTES)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
OUT EFI_FV_ATTRIBUTES *FvAttributes\r
-);\r
-\r
+ );\r
\r
/**\r
Modifies the current settings of the firmware volume according to the input parameter.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_SET_ATTRIBUTES)(\r
+(EFIAPI *EFI_FV_SET_ATTRIBUTES)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
IN OUT EFI_FV_ATTRIBUTES *FvAttributes\r
-);\r
-\r
+ );\r
\r
/**\r
Retrieves a file and/or file information from the firmware volume.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_READ_FILE)(\r
+(EFIAPI *EFI_FV_READ_FILE)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
IN CONST EFI_GUID *NameGuid,\r
IN OUT VOID **Buffer,\r
OUT EFI_FV_FILETYPE *FoundType,\r
OUT EFI_FV_FILE_ATTRIBUTES *FileAttributes,\r
OUT UINT32 *AuthenticationStatus\r
-);\r
-\r
-\r
+ );\r
\r
/**\r
Locates the requested section within a file and returns it in a buffer.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_READ_SECTION)(\r
+(EFIAPI *EFI_FV_READ_SECTION)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
IN CONST EFI_GUID *NameGuid,\r
IN EFI_SECTION_TYPE SectionType,\r
IN OUT VOID **Buffer,\r
IN OUT UINTN *BufferSize,\r
OUT UINT32 *AuthenticationStatus\r
-);\r
+ );\r
\r
///\r
/// EFI_FV_WRITE_POLICY, two policies (unreliable write and reliable write) are defined.\r
///\r
typedef UINT32 EFI_FV_WRITE_POLICY;\r
-#define EFI_FV_UNRELIABLE_WRITE 0x00000000\r
-#define EFI_FV_RELIABLE_WRITE 0x00000001\r
+#define EFI_FV_UNRELIABLE_WRITE 0x00000000\r
+#define EFI_FV_RELIABLE_WRITE 0x00000001\r
\r
//\r
// EFI_FV_WRITE_FILE_DATA\r
///\r
/// Pointer to a GUID, which is the file name to be written.\r
///\r
- EFI_GUID *NameGuid;\r
+ EFI_GUID *NameGuid;\r
///\r
/// Indicates the type of file to be written.\r
///\r
- EFI_FV_FILETYPE Type;\r
+ EFI_FV_FILETYPE Type;\r
///\r
/// Indicates the attributes for the file to be written.\r
///\r
- EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
+ EFI_FV_FILE_ATTRIBUTES FileAttributes;\r
///\r
/// Pointer to a buffer containing the file to be written.\r
///\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
///\r
/// Indicates the size of the file image contained in Buffer.\r
///\r
- UINT32 BufferSize;\r
+ UINT32 BufferSize;\r
} EFI_FV_WRITE_FILE_DATA;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_WRITE_FILE)(\r
+(EFIAPI *EFI_FV_WRITE_FILE)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
IN UINT32 NumberOfFiles,\r
IN EFI_FV_WRITE_POLICY WritePolicy,\r
IN EFI_FV_WRITE_FILE_DATA *FileData\r
-);\r
-\r
+ );\r
\r
/**\r
Retrieves information about the next file in the firmware volume store\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FV_GET_NEXT_FILE)(\r
+(EFIAPI *EFI_FV_GET_NEXT_FILE)(\r
IN CONST EFI_FIRMWARE_VOLUME2_PROTOCOL *This,\r
IN OUT VOID *Key,\r
IN OUT EFI_FV_FILETYPE *FileType,\r
OUT EFI_GUID *NameGuid,\r
OUT EFI_FV_FILE_ATTRIBUTES *Attributes,\r
OUT UINTN *Size\r
-);\r
+ );\r
\r
/**\r
Return information about a firmware volume.\r
IN CONST EFI_GUID *InformationType,\r
IN OUT UINTN *BufferSize,\r
OUT VOID *Buffer\r
-);\r
-\r
+ );\r
\r
/**\r
Sets information about a firmware volume.\r
IN CONST EFI_GUID *InformationType,\r
IN UINTN BufferSize,\r
IN CONST VOID *Buffer\r
-);\r
-\r
+ );\r
\r
///\r
/// The Firmware Volume Protocol contains the file-level\r
/// Protocol.\r
///\r
struct _EFI_FIRMWARE_VOLUME2_PROTOCOL {\r
- EFI_FV_GET_ATTRIBUTES GetVolumeAttributes;\r
- EFI_FV_SET_ATTRIBUTES SetVolumeAttributes;\r
- EFI_FV_READ_FILE ReadFile;\r
- EFI_FV_READ_SECTION ReadSection;\r
- EFI_FV_WRITE_FILE WriteFile;\r
- EFI_FV_GET_NEXT_FILE GetNextFile;\r
+ EFI_FV_GET_ATTRIBUTES GetVolumeAttributes;\r
+ EFI_FV_SET_ATTRIBUTES SetVolumeAttributes;\r
+ EFI_FV_READ_FILE ReadFile;\r
+ EFI_FV_READ_SECTION ReadSection;\r
+ EFI_FV_WRITE_FILE WriteFile;\r
+ EFI_FV_GET_NEXT_FILE GetNextFile;\r
\r
///\r
/// Data field that indicates the size in bytes\r
/// of the Key input buffer for the\r
/// GetNextFile() API.\r
///\r
- UINT32 KeySize;\r
+ UINT32 KeySize;\r
\r
///\r
/// Handle of the parent firmware volume.\r
///\r
- EFI_HANDLE ParentHandle;\r
- EFI_FV_GET_INFO GetInfo;\r
- EFI_FV_SET_INFO SetInfo;\r
+ EFI_HANDLE ParentHandle;\r
+ EFI_FV_GET_INFO GetInfo;\r
+ EFI_FV_SET_INFO SetInfo;\r
};\r
\r
-\r
-extern EFI_GUID gEfiFirmwareVolume2ProtocolGuid;\r
+extern EFI_GUID gEfiFirmwareVolume2ProtocolGuid;\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_GET_ATTRIBUTES)(\r
+(EFIAPI *EFI_FVB_GET_ATTRIBUTES)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
-);\r
-\r
+ );\r
\r
/**\r
The SetAttributes() function sets configurable firmware volume\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_SET_ATTRIBUTES)(\r
+(EFIAPI *EFI_FVB_SET_ATTRIBUTES)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
-);\r
-\r
+ );\r
\r
/**\r
The GetPhysicalAddress() function retrieves the base address of\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_GET_PHYSICAL_ADDRESS)(\r
+(EFIAPI *EFI_FVB_GET_PHYSICAL_ADDRESS)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
OUT EFI_PHYSICAL_ADDRESS *Address\r
-);\r
+ );\r
\r
/**\r
The GetBlockSize() function retrieves the size of the requested\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_GET_BLOCK_SIZE)(\r
+(EFIAPI *EFI_FVB_GET_BLOCK_SIZE)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
IN EFI_LBA Lba,\r
OUT UINTN *BlockSize,\r
OUT UINTN *NumberOfBlocks\r
-);\r
-\r
+ );\r
\r
/**\r
Reads the specified number of bytes into a buffer from the specified block.\r
IN UINTN Offset,\r
IN OUT UINTN *NumBytes,\r
IN OUT UINT8 *Buffer\r
-);\r
+ );\r
\r
/**\r
Writes the specified number of bytes from the input buffer to the block.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_WRITE)(\r
+(EFIAPI *EFI_FVB_WRITE)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
IN EFI_LBA Lba,\r
IN UINTN Offset,\r
IN OUT UINTN *NumBytes,\r
IN UINT8 *Buffer\r
-);\r
-\r
-\r
-\r
+ );\r
\r
///\r
/// EFI_LBA_LIST_TERMINATOR\r
///\r
-#define EFI_LBA_LIST_TERMINATOR 0xFFFFFFFFFFFFFFFFULL\r
-\r
+#define EFI_LBA_LIST_TERMINATOR 0xFFFFFFFFFFFFFFFFULL\r
\r
/**\r
Erases and initializes a firmware volume block.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_FVB_ERASE_BLOCKS)(\r
+(EFIAPI *EFI_FVB_ERASE_BLOCKS)(\r
IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,\r
...\r
-);\r
+ );\r
\r
///\r
/// The Firmware Volume Block Protocol is the low-level interface\r
/// produces the Firmware Volume Protocol will bind to the\r
/// Firmware Volume Block Protocol.\r
///\r
-struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL{\r
- EFI_FVB_GET_ATTRIBUTES GetAttributes;\r
- EFI_FVB_SET_ATTRIBUTES SetAttributes;\r
- EFI_FVB_GET_PHYSICAL_ADDRESS GetPhysicalAddress;\r
- EFI_FVB_GET_BLOCK_SIZE GetBlockSize;\r
- EFI_FVB_READ Read;\r
- EFI_FVB_WRITE Write;\r
- EFI_FVB_ERASE_BLOCKS EraseBlocks;\r
+struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL {\r
+ EFI_FVB_GET_ATTRIBUTES GetAttributes;\r
+ EFI_FVB_SET_ATTRIBUTES SetAttributes;\r
+ EFI_FVB_GET_PHYSICAL_ADDRESS GetPhysicalAddress;\r
+ EFI_FVB_GET_BLOCK_SIZE GetBlockSize;\r
+ EFI_FVB_READ Read;\r
+ EFI_FVB_WRITE Write;\r
+ EFI_FVB_ERASE_BLOCKS EraseBlocks;\r
///\r
/// The handle of the parent firmware volume.\r
///\r
- EFI_HANDLE ParentHandle;\r
+ EFI_HANDLE ParentHandle;\r
};\r
\r
-\r
-extern EFI_GUID gEfiFirmwareVolumeBlockProtocolGuid;\r
-extern EFI_GUID gEfiFirmwareVolumeBlock2ProtocolGuid;\r
+extern EFI_GUID gEfiFirmwareVolumeBlockProtocolGuid;\r
+extern EFI_GUID gEfiFirmwareVolumeBlock2ProtocolGuid;\r
\r
#endif\r
#define EFI_FORM_BROWSER2_PROTOCOL_GUID \\r
{0xb9d4c360, 0xbcfb, 0x4f9b, {0x92, 0x98, 0x53, 0xc1, 0x36, 0x98, 0x22, 0x58 }}\r
\r
-\r
-typedef struct _EFI_FORM_BROWSER2_PROTOCOL EFI_FORM_BROWSER2_PROTOCOL;\r
-\r
-\r
+typedef struct _EFI_FORM_BROWSER2_PROTOCOL EFI_FORM_BROWSER2_PROTOCOL;\r
\r
/**\r
\r
window will end.\r
**/\r
typedef struct {\r
- UINTN LeftColumn;\r
- UINTN RightColumn;\r
- UINTN TopRow;\r
- UINTN BottomRow;\r
+ UINTN LeftColumn;\r
+ UINTN RightColumn;\r
+ UINTN TopRow;\r
+ UINTN BottomRow;\r
} EFI_SCREEN_DESCRIPTOR;\r
\r
typedef UINTN EFI_BROWSER_ACTION_REQUEST;\r
\r
-#define EFI_BROWSER_ACTION_REQUEST_NONE 0\r
-#define EFI_BROWSER_ACTION_REQUEST_RESET 1\r
-#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2\r
-#define EFI_BROWSER_ACTION_REQUEST_EXIT 3\r
-#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4\r
-#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5\r
-#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6\r
-#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7\r
-#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8\r
-\r
+#define EFI_BROWSER_ACTION_REQUEST_NONE 0\r
+#define EFI_BROWSER_ACTION_REQUEST_RESET 1\r
+#define EFI_BROWSER_ACTION_REQUEST_SUBMIT 2\r
+#define EFI_BROWSER_ACTION_REQUEST_EXIT 3\r
+#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT 4\r
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT 5\r
+#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY 6\r
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD 7\r
+#define EFI_BROWSER_ACTION_REQUEST_RECONNECT 8\r
\r
/**\r
Initialize the browser to display the specified configuration forms.\r
IN EFI_FORM_ID FormId OPTIONAL,\r
IN CONST EFI_SCREEN_DESCRIPTOR *ScreenDimensions OPTIONAL,\r
OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest OPTIONAL\r
-);\r
-\r
+ );\r
\r
/**\r
This function is called by a callback handler to retrieve uncommitted state data from the browser.\r
IN CONST BOOLEAN RetrieveData,\r
IN CONST EFI_GUID *VariableGuid OPTIONAL,\r
IN CONST CHAR16 *VariableName OPTIONAL\r
-);\r
+ );\r
\r
///\r
/// This interface will allow the caller to direct the configuration\r
/// driver to use either the HII database or use the passed-in packet of data.\r
///\r
struct _EFI_FORM_BROWSER2_PROTOCOL {\r
- EFI_SEND_FORM2 SendForm;\r
- EFI_BROWSER_CALLBACK2 BrowserCallback;\r
-} ;\r
+ EFI_SEND_FORM2 SendForm;\r
+ EFI_BROWSER_CALLBACK2 BrowserCallback;\r
+};\r
\r
-extern EFI_GUID gEfiFormBrowser2ProtocolGuid;\r
+extern EFI_GUID gEfiFormBrowser2ProtocolGuid;\r
\r
#endif\r
#ifndef __EFI_FTP4_PROTOCOL_H__\r
#define __EFI_FTP4_PROTOCOL_H__\r
\r
-\r
#define EFI_FTP4_SERVICE_BINDING_PROTOCOL_GUID \\r
{ \\r
0xfaaecb1, 0x226e, 0x4782, {0xaa, 0xce, 0x7d, 0xb9, 0xbc, 0xbf, 0x4d, 0xaf } \\r
/// equal to TPL_CALLBACK. If it is set to NULL, this function will not return until the\r
/// function completes.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// The variable to receive the result of the completed operation.\r
/// EFI_SUCCESS: The FTP connection is established successfully\r
/// error is received.\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
} EFI_FTP4_CONNECTION_TOKEN;\r
\r
///\r
/// Pointer to a ASCII string that contains user name. The caller is\r
/// responsible for freeing Username after GetModeData() is called.\r
///\r
- UINT8 *Username;\r
+ UINT8 *Username;\r
///\r
/// Pointer to a ASCII string that contains password. The caller is\r
/// responsible for freeing Password after GetModeData() is called.\r
///\r
- UINT8 *Password;\r
+ UINT8 *Password;\r
///\r
/// Set it to TRUE to initiate an active data connection. Set it to\r
/// FALSE to initiate a passive data connection.\r
///\r
- BOOLEAN Active;\r
+ BOOLEAN Active;\r
///\r
/// Boolean value indicating if default network settting used.\r
///\r
- BOOLEAN UseDefaultSetting;\r
+ BOOLEAN UseDefaultSetting;\r
///\r
/// IP address of station if UseDefaultSetting is FALSE.\r
///\r
- EFI_IPv4_ADDRESS StationIp;\r
+ EFI_IPv4_ADDRESS StationIp;\r
///\r
/// Subnet mask of station if UseDefaultSetting is FALSE.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// IP address of gateway if UseDefaultSetting is FALSE.\r
///\r
- EFI_IPv4_ADDRESS GatewayIp;\r
+ EFI_IPv4_ADDRESS GatewayIp;\r
///\r
/// IP address of FTPv4 server.\r
///\r
- EFI_IPv4_ADDRESS ServerIp;\r
+ EFI_IPv4_ADDRESS ServerIp;\r
///\r
/// FTPv4 server port number of control connection, and the default\r
/// value is 21 as convention.\r
///\r
- UINT16 ServerPort;\r
+ UINT16 ServerPort;\r
///\r
/// FTPv4 server port number of data connection. If it is zero, use\r
/// (ServerPort - 1) by convention.\r
///\r
- UINT16 AltDataPort;\r
+ UINT16 AltDataPort;\r
///\r
/// A byte indicate the representation type. The right 4 bit is used for\r
/// first parameter, the left 4 bit is use for second parameter\r
/// - If it is a local type, the second parameter is the local byte byte size.\r
/// - If it is a image type, the second parameter is undefined.\r
///\r
- UINT8 RepType;\r
+ UINT8 RepType;\r
///\r
/// Defines the file structure in FTP used. 0x00 = file, 0x01 = record, 0x02 = page.\r
///\r
- UINT8 FileStruct;\r
+ UINT8 FileStruct;\r
///\r
/// Defines the transifer mode used in FTP. 0x00 = stream, 0x01 = Block, 0x02 = Compressed.\r
///\r
- UINT8 TransMode;\r
+ UINT8 TransMode;\r
} EFI_FTP4_CONFIG_DATA;\r
\r
typedef struct _EFI_FTP4_COMMAND_TOKEN EFI_FTP4_COMMAND_TOKEN;\r
/// set to NULL, related function must wait until the function\r
/// completes.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Pointer to a null-terminated ASCII name string.\r
///\r
- UINT8 *Pathname;\r
+ UINT8 *Pathname;\r
///\r
/// The size of data buffer in bytes.\r
///\r
- UINT64 DataBufferSize;\r
+ UINT64 DataBufferSize;\r
///\r
/// Pointer to the data buffer. Data downloaded from FTP server\r
/// through connection is downloaded here.\r
///\r
- VOID *DataBuffer;\r
+ VOID *DataBuffer;\r
///\r
/// Pointer to a callback function. If it is receiving function that leads\r
/// to inbound data, the callback function is called when databuffer is\r
/// DataBufferSize, again. If there is no data remained,\r
/// DataBufferSize should be set to 0.\r
///\r
- EFI_FTP4_DATA_CALLBACK DataCallback;\r
+ EFI_FTP4_DATA_CALLBACK DataCallback;\r
///\r
/// Pointer to the parameter for DataCallback.\r
///\r
- VOID *Context;\r
+ VOID *Context;\r
///\r
/// The variable to receive the result of the completed operation.\r
/// EFI_SUCCESS: The FTP command is completed successfully.\r
/// error is received.\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
};\r
\r
/**\r
IN EFI_FTP4_CONFIG_DATA *FtpConfigData OPTIONAL\r
);\r
\r
-\r
/**\r
Downloads a file from an FTPv4 server.\r
\r
EFI_FTP4_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiFtp4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiFtp4ProtocolGuid;\r
+extern EFI_GUID gEfiFtp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiFtp4ProtocolGuid;\r
\r
#endif\r
-\r
typedef struct _EFI_GRAPHICS_OUTPUT_PROTOCOL EFI_GRAPHICS_OUTPUT_PROTOCOL;\r
\r
typedef struct {\r
- UINT32 RedMask;\r
- UINT32 GreenMask;\r
- UINT32 BlueMask;\r
- UINT32 ReservedMask;\r
+ UINT32 RedMask;\r
+ UINT32 GreenMask;\r
+ UINT32 BlueMask;\r
+ UINT32 ReservedMask;\r
} EFI_PIXEL_BITMASK;\r
\r
typedef enum {\r
/// The version of this data structure. A value of zero represents the\r
/// EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as defined in this specification.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// The size of video screen in pixels in the X dimension.\r
///\r
- UINT32 HorizontalResolution;\r
+ UINT32 HorizontalResolution;\r
///\r
/// The size of video screen in pixels in the Y dimension.\r
///\r
- UINT32 VerticalResolution;\r
+ UINT32 VerticalResolution;\r
///\r
/// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly\r
/// implies that a linear frame buffer is not available for this mode.\r
///\r
- EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;\r
+ EFI_GRAPHICS_PIXEL_FORMAT PixelFormat;\r
///\r
/// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask.\r
/// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reserved.\r
///\r
- EFI_PIXEL_BITMASK PixelInformation;\r
+ EFI_PIXEL_BITMASK PixelInformation;\r
///\r
/// Defines the number of pixel elements per video memory line.\r
///\r
- UINT32 PixelsPerScanLine;\r
+ UINT32 PixelsPerScanLine;\r
} EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;\r
\r
/**\r
);\r
\r
typedef struct {\r
- UINT8 Blue;\r
- UINT8 Green;\r
- UINT8 Red;\r
- UINT8 Reserved;\r
+ UINT8 Blue;\r
+ UINT8 Green;\r
+ UINT8 Red;\r
+ UINT8 Reserved;\r
} EFI_GRAPHICS_OUTPUT_BLT_PIXEL;\r
\r
typedef union {\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel;\r
- UINT32 Raw;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Pixel;\r
+ UINT32 Raw;\r
} EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION;\r
\r
///\r
///\r
/// The number of modes supported by QueryMode() and SetMode().\r
///\r
- UINT32 MaxMode;\r
+ UINT32 MaxMode;\r
///\r
/// Current Mode of the graphics device. Valid mode numbers are 0 to MaxMode -1.\r
///\r
- UINT32 Mode;\r
+ UINT32 Mode;\r
///\r
/// Pointer to read-only EFI_GRAPHICS_OUTPUT_MODE_INFORMATION data.\r
///\r
- EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;\r
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;\r
///\r
/// Size of Info structure in bytes.\r
///\r
- UINTN SizeOfInfo;\r
+ UINTN SizeOfInfo;\r
///\r
/// Base address of graphics linear frame buffer.\r
/// Offset zero in FrameBufferBase represents the upper left pixel of the display.\r
///\r
- EFI_PHYSICAL_ADDRESS FrameBufferBase;\r
+ EFI_PHYSICAL_ADDRESS FrameBufferBase;\r
///\r
/// Amount of frame buffer needed to support the active mode as defined by\r
/// PixelsPerScanLine xVerticalResolution x PixelElementSize.\r
///\r
- UINTN FrameBufferSize;\r
+ UINTN FrameBufferSize;\r
} EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE;\r
\r
///\r
/// frame buffer is also exposed so software can write directly to the video hardware.\r
///\r
struct _EFI_GRAPHICS_OUTPUT_PROTOCOL {\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_QUERY_MODE QueryMode;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_SET_MODE SetMode;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_BLT Blt;\r
///\r
/// Pointer to EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE data.\r
///\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE *Mode;\r
};\r
\r
-extern EFI_GUID gEfiGraphicsOutputProtocolGuid;\r
+extern EFI_GUID gEfiGraphicsOutputProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL;\r
\r
-\r
/**\r
The ExtractSection() function processes the input section and\r
allocates a buffer from the pool in which it returns the section\r
OUT VOID **OutputBuffer,\r
OUT UINTN *OutputSize,\r
OUT UINT32 *AuthenticationStatus\r
-);\r
-\r
+ );\r
\r
///\r
/// Typically, protocol interface structures are identified by associating them with a GUID. Each\r
/// Extraction Protocol is used to correlate it with the GUIDed section type that it is intended to process.\r
///\r
struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL {\r
- EFI_EXTRACT_GUIDED_SECTION ExtractSection;\r
+ EFI_EXTRACT_GUIDED_SECTION ExtractSection;\r
};\r
\r
-\r
#endif\r
\r
typedef struct _EFI_HASH_PROTOCOL EFI_HASH_PROTOCOL;\r
\r
-typedef UINT8 EFI_MD5_HASH[16];\r
-typedef UINT8 EFI_SHA1_HASH[20];\r
-typedef UINT8 EFI_SHA224_HASH[28];\r
-typedef UINT8 EFI_SHA256_HASH[32];\r
-typedef UINT8 EFI_SHA384_HASH[48];\r
-typedef UINT8 EFI_SHA512_HASH[64];\r
+typedef UINT8 EFI_MD5_HASH[16];\r
+typedef UINT8 EFI_SHA1_HASH[20];\r
+typedef UINT8 EFI_SHA224_HASH[28];\r
+typedef UINT8 EFI_SHA256_HASH[32];\r
+typedef UINT8 EFI_SHA384_HASH[48];\r
+typedef UINT8 EFI_SHA512_HASH[64];\r
\r
typedef union {\r
- EFI_MD5_HASH *Md5Hash;\r
- EFI_SHA1_HASH *Sha1Hash;\r
- EFI_SHA224_HASH *Sha224Hash;\r
- EFI_SHA256_HASH *Sha256Hash;\r
- EFI_SHA384_HASH *Sha384Hash;\r
- EFI_SHA512_HASH *Sha512Hash;\r
+ EFI_MD5_HASH *Md5Hash;\r
+ EFI_SHA1_HASH *Sha1Hash;\r
+ EFI_SHA224_HASH *Sha224Hash;\r
+ EFI_SHA256_HASH *Sha256Hash;\r
+ EFI_SHA384_HASH *Sha384Hash;\r
+ EFI_SHA512_HASH *Sha512Hash;\r
} EFI_HASH_OUTPUT;\r
\r
/**\r
/// using one or more hash algorithms.\r
///\r
struct _EFI_HASH_PROTOCOL {\r
- EFI_HASH_GET_HASH_SIZE GetHashSize;\r
- EFI_HASH_HASH Hash;\r
+ EFI_HASH_GET_HASH_SIZE GetHashSize;\r
+ EFI_HASH_HASH Hash;\r
};\r
\r
-extern EFI_GUID gEfiHashServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiHashProtocolGuid;\r
-extern EFI_GUID gEfiHashAlgorithmSha1Guid;\r
-extern EFI_GUID gEfiHashAlgorithmSha224Guid;\r
-extern EFI_GUID gEfiHashAlgorithmSha256Guid;\r
-extern EFI_GUID gEfiHashAlgorithmSha384Guid;\r
-extern EFI_GUID gEfiHashAlgorithmSha512Guid;\r
-extern EFI_GUID gEfiHashAlgorithmMD5Guid;\r
-extern EFI_GUID gEfiHashAlgorithmSha1NoPadGuid;\r
-extern EFI_GUID gEfiHashAlgorithmSha256NoPadGuid;\r
+extern EFI_GUID gEfiHashServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiHashProtocolGuid;\r
+extern EFI_GUID gEfiHashAlgorithmSha1Guid;\r
+extern EFI_GUID gEfiHashAlgorithmSha224Guid;\r
+extern EFI_GUID gEfiHashAlgorithmSha256Guid;\r
+extern EFI_GUID gEfiHashAlgorithmSha384Guid;\r
+extern EFI_GUID gEfiHashAlgorithmSha512Guid;\r
+extern EFI_GUID gEfiHashAlgorithmMD5Guid;\r
+extern EFI_GUID gEfiHashAlgorithmSha1NoPadGuid;\r
+extern EFI_GUID gEfiHashAlgorithmSha256NoPadGuid;\r
\r
#endif\r
\r
typedef struct _EFI_HASH2_PROTOCOL EFI_HASH2_PROTOCOL;\r
\r
-typedef UINT8 EFI_MD5_HASH2[16];\r
-typedef UINT8 EFI_SHA1_HASH2[20];\r
-typedef UINT8 EFI_SHA224_HASH2[28];\r
-typedef UINT8 EFI_SHA256_HASH2[32];\r
-typedef UINT8 EFI_SHA384_HASH2[48];\r
-typedef UINT8 EFI_SHA512_HASH2[64];\r
+typedef UINT8 EFI_MD5_HASH2[16];\r
+typedef UINT8 EFI_SHA1_HASH2[20];\r
+typedef UINT8 EFI_SHA224_HASH2[28];\r
+typedef UINT8 EFI_SHA256_HASH2[32];\r
+typedef UINT8 EFI_SHA384_HASH2[48];\r
+typedef UINT8 EFI_SHA512_HASH2[64];\r
\r
typedef union {\r
- EFI_MD5_HASH2 Md5Hash;\r
- EFI_SHA1_HASH2 Sha1Hash;\r
- EFI_SHA224_HASH2 Sha224Hash;\r
- EFI_SHA256_HASH2 Sha256Hash;\r
- EFI_SHA384_HASH2 Sha384Hash;\r
- EFI_SHA512_HASH2 Sha512Hash;\r
+ EFI_MD5_HASH2 Md5Hash;\r
+ EFI_SHA1_HASH2 Sha1Hash;\r
+ EFI_SHA224_HASH2 Sha224Hash;\r
+ EFI_SHA256_HASH2 Sha256Hash;\r
+ EFI_SHA384_HASH2 Sha384Hash;\r
+ EFI_SHA512_HASH2 Sha512Hash;\r
} EFI_HASH2_OUTPUT;\r
\r
/**\r
/// finalization are performed by the supporting driver.\r
///\r
struct _EFI_HASH2_PROTOCOL {\r
- EFI_HASH2_GET_HASH_SIZE GetHashSize;\r
- EFI_HASH2_HASH Hash;\r
- EFI_HASH2_HASH_INIT HashInit;\r
- EFI_HASH2_HASH_UPDATE HashUpdate;\r
- EFI_HASH2_HASH_FINAL HashFinal;\r
+ EFI_HASH2_GET_HASH_SIZE GetHashSize;\r
+ EFI_HASH2_HASH Hash;\r
+ EFI_HASH2_HASH_INIT HashInit;\r
+ EFI_HASH2_HASH_UPDATE HashUpdate;\r
+ EFI_HASH2_HASH_FINAL HashFinal;\r
};\r
\r
-extern EFI_GUID gEfiHash2ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiHash2ProtocolGuid;\r
+extern EFI_GUID gEfiHash2ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiHash2ProtocolGuid;\r
\r
#endif\r
\r
**/\r
\r
-\r
#ifndef __EFI_HII_CONFIG_ACCESS_H__\r
#define __EFI_HII_CONFIG_ACCESS_H__\r
\r
#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \\r
{ 0x330d4706, 0xf2a0, 0x4e4f, { 0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85 } }\r
\r
-typedef struct _EFI_HII_CONFIG_ACCESS_PROTOCOL EFI_HII_CONFIG_ACCESS_PROTOCOL;\r
+typedef struct _EFI_HII_CONFIG_ACCESS_PROTOCOL EFI_HII_CONFIG_ACCESS_PROTOCOL;\r
\r
typedef UINTN EFI_BROWSER_ACTION;\r
\r
-#define EFI_BROWSER_ACTION_CHANGING 0\r
-#define EFI_BROWSER_ACTION_CHANGED 1\r
-#define EFI_BROWSER_ACTION_RETRIEVE 2\r
-#define EFI_BROWSER_ACTION_FORM_OPEN 3\r
-#define EFI_BROWSER_ACTION_FORM_CLOSE 4\r
-#define EFI_BROWSER_ACTION_SUBMITTED 5\r
-#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000\r
-#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001\r
-#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002\r
-#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000\r
-#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000\r
-#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000\r
+#define EFI_BROWSER_ACTION_CHANGING 0\r
+#define EFI_BROWSER_ACTION_CHANGED 1\r
+#define EFI_BROWSER_ACTION_RETRIEVE 2\r
+#define EFI_BROWSER_ACTION_FORM_OPEN 3\r
+#define EFI_BROWSER_ACTION_FORM_CLOSE 4\r
+#define EFI_BROWSER_ACTION_SUBMITTED 5\r
+#define EFI_BROWSER_ACTION_DEFAULT_STANDARD 0x1000\r
+#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING 0x1001\r
+#define EFI_BROWSER_ACTION_DEFAULT_SAFE 0x1002\r
+#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM 0x2000\r
+#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE 0x3000\r
+#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE 0x4000\r
\r
/**\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_ACCESS_EXTRACT_CONFIG)(\r
+(EFIAPI *EFI_HII_ACCESS_EXTRACT_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,\r
IN CONST EFI_STRING Request,\r
OUT EFI_STRING *Progress,\r
OUT EFI_STRING *Results\r
-);\r
-\r
+ );\r
\r
/**\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_ACCESS_ROUTE_CONFIG)(\r
+(EFIAPI *EFI_HII_ACCESS_ROUTE_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,\r
IN CONST EFI_STRING Configuration,\r
OUT EFI_STRING *Progress\r
-);\r
+ );\r
\r
/**\r
\r
IN OUT EFI_IFR_TYPE_VALUE *Value,\r
OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest\r
)\r
- ;\r
+;\r
\r
///\r
/// This protocol provides a callable interface between the HII and\r
/// to publish this protocol.\r
///\r
struct _EFI_HII_CONFIG_ACCESS_PROTOCOL {\r
- EFI_HII_ACCESS_EXTRACT_CONFIG ExtractConfig;\r
- EFI_HII_ACCESS_ROUTE_CONFIG RouteConfig;\r
- EFI_HII_ACCESS_FORM_CALLBACK Callback;\r
-} ;\r
+ EFI_HII_ACCESS_EXTRACT_CONFIG ExtractConfig;\r
+ EFI_HII_ACCESS_ROUTE_CONFIG RouteConfig;\r
+ EFI_HII_ACCESS_FORM_CALLBACK Callback;\r
+};\r
\r
-extern EFI_GUID gEfiHiiConfigAccessProtocolGuid;\r
+extern EFI_GUID gEfiHiiConfigAccessProtocolGuid;\r
\r
#endif\r
-\r
-\r
0x0a8badd5, 0x03b8, 0x4d19, {0xb1, 0x28, 0x7b, 0x8f, 0x0e, 0xda, 0xa5, 0x96 } \\r
}\r
\r
-//***********************************************************\r
+// ***********************************************************\r
// Progress Errors\r
-//***********************************************************\r
-#define KEYWORD_HANDLER_NO_ERROR 0x00000000\r
-#define KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND 0x00000001\r
-#define KEYWORD_HANDLER_MALFORMED_STRING 0x00000002\r
-#define KEYWORD_HANDLER_KEYWORD_NOT_FOUND 0x00000004\r
-#define KEYWORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED 0x00000008\r
-#define KEYWORD_HANDLER_ACCESS_NOT_PERMITTED 0x00000010\r
-#define KEYWORD_HANDLER_UNDEFINED_PROCESSING_ERROR 0x80000000\r
+// ***********************************************************\r
+#define KEYWORD_HANDLER_NO_ERROR 0x00000000\r
+#define KEYWORD_HANDLER_NAMESPACE_ID_NOT_FOUND 0x00000001\r
+#define KEYWORD_HANDLER_MALFORMED_STRING 0x00000002\r
+#define KEYWORD_HANDLER_KEYWORD_NOT_FOUND 0x00000004\r
+#define KEYWORD_HANDLER_INCOMPATIBLE_VALUE_DETECTED 0x00000008\r
+#define KEYWORD_HANDLER_ACCESS_NOT_PERMITTED 0x00000010\r
+#define KEYWORD_HANDLER_UNDEFINED_PROCESSING_ERROR 0x80000000\r
\r
typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_SET_DATA) (\r
+(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_SET_DATA)(\r
IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This,\r
IN CONST EFI_STRING KeywordString,\r
OUT EFI_STRING *Progress,\r
OUT UINT32 *ProgressErr\r
);\r
\r
-\r
/**\r
\r
This function accepts a <MultiKeywordRequest> formatted string, finds the underlying\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_GET_DATA) (\r
+(EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_GET_DATA)(\r
IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This,\r
IN CONST EFI_STRING NameSpaceId OPTIONAL,\r
IN CONST EFI_STRING KeywordString OPTIONAL,\r
///\r
\r
struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL {\r
- EFI_CONFIG_KEYWORD_HANDLER_SET_DATA SetData;\r
- EFI_CONFIG_KEYWORD_HANDLER_GET_DATA GetData;\r
+ EFI_CONFIG_KEYWORD_HANDLER_SET_DATA SetData;\r
+ EFI_CONFIG_KEYWORD_HANDLER_GET_DATA GetData;\r
};\r
\r
-extern EFI_GUID gEfiConfigKeywordHandlerProtocolGuid;\r
+extern EFI_GUID gEfiConfigKeywordHandlerProtocolGuid;\r
\r
#endif\r
#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \\r
{ 0x587e72d7, 0xcc50, 0x4f79, { 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f } }\r
\r
-\r
typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_EXTRACT_CONFIG)(\r
+(EFIAPI *EFI_HII_EXTRACT_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
IN CONST EFI_STRING Request,\r
OUT EFI_STRING *Progress,\r
OUT EFI_STRING *Results\r
-);\r
+ );\r
\r
/**\r
This function allows the caller to request the current configuration\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_EXPORT_CONFIG)(\r
+(EFIAPI *EFI_HII_EXPORT_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
OUT EFI_STRING *Results\r
-);\r
+ );\r
\r
/**\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_ROUTE_CONFIG)(\r
+(EFIAPI *EFI_HII_ROUTE_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
IN CONST EFI_STRING Configuration,\r
OUT EFI_STRING *Progress\r
-);\r
-\r
+ );\r
\r
/**\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_BLOCK_TO_CONFIG)(\r
+(EFIAPI *EFI_HII_BLOCK_TO_CONFIG)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
IN CONST EFI_STRING ConfigRequest,\r
IN CONST UINT8 *Block,\r
IN CONST UINTN BlockSize,\r
OUT EFI_STRING *Config,\r
OUT EFI_STRING *Progress\r
-);\r
-\r
-\r
+ );\r
\r
/**\r
This function maps a configuration containing a series of\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_CONFIG_TO_BLOCK)(\r
+(EFIAPI *EFI_HII_CONFIG_TO_BLOCK)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
IN CONST EFI_STRING ConfigResp,\r
IN OUT UINT8 *Block,\r
IN OUT UINTN *BlockSize,\r
OUT EFI_STRING *Progress\r
-);\r
+ );\r
\r
/**\r
This helper function is to be called by drivers to extract portions of\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_GET_ALT_CFG)(\r
+(EFIAPI *EFI_HII_GET_ALT_CFG)(\r
IN CONST EFI_HII_CONFIG_ROUTING_PROTOCOL *This,\r
IN CONST EFI_STRING ConfigResp,\r
IN CONST EFI_GUID *Guid,\r
/// instance of this protocol in the system.\r
///\r
struct _EFI_HII_CONFIG_ROUTING_PROTOCOL {\r
- EFI_HII_EXTRACT_CONFIG ExtractConfig;\r
- EFI_HII_EXPORT_CONFIG ExportConfig;\r
- EFI_HII_ROUTE_CONFIG RouteConfig;\r
- EFI_HII_BLOCK_TO_CONFIG BlockToConfig;\r
- EFI_HII_CONFIG_TO_BLOCK ConfigToBlock;\r
- EFI_HII_GET_ALT_CFG GetAltConfig;\r
+ EFI_HII_EXTRACT_CONFIG ExtractConfig;\r
+ EFI_HII_EXPORT_CONFIG ExportConfig;\r
+ EFI_HII_ROUTE_CONFIG RouteConfig;\r
+ EFI_HII_BLOCK_TO_CONFIG BlockToConfig;\r
+ EFI_HII_CONFIG_TO_BLOCK ConfigToBlock;\r
+ EFI_HII_GET_ALT_CFG GetAltConfig;\r
};\r
\r
-extern EFI_GUID gEfiHiiConfigRoutingProtocolGuid;\r
-\r
+extern EFI_GUID gEfiHiiConfigRoutingProtocolGuid;\r
\r
#endif\r
-\r
#define EFI_HII_DATABASE_PROTOCOL_GUID \\r
{ 0xef9fc172, 0xa1b2, 0x4693, { 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42 } }\r
\r
-\r
typedef struct _EFI_HII_DATABASE_PROTOCOL EFI_HII_DATABASE_PROTOCOL;\r
\r
-\r
///\r
/// EFI_HII_DATABASE_NOTIFY_TYPE.\r
///\r
-typedef UINTN EFI_HII_DATABASE_NOTIFY_TYPE;\r
+typedef UINTN EFI_HII_DATABASE_NOTIFY_TYPE;\r
+\r
+#define EFI_HII_DATABASE_NOTIFY_NEW_PACK 0x00000001\r
+#define EFI_HII_DATABASE_NOTIFY_REMOVE_PACK 0x00000002\r
+#define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004\r
+#define EFI_HII_DATABASE_NOTIFY_ADD_PACK 0x00000008\r
\r
-#define EFI_HII_DATABASE_NOTIFY_NEW_PACK 0x00000001\r
-#define EFI_HII_DATABASE_NOTIFY_REMOVE_PACK 0x00000002\r
-#define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004\r
-#define EFI_HII_DATABASE_NOTIFY_ADD_PACK 0x00000008\r
/**\r
\r
Functions which are registered to receive notification of\r
IN CONST EFI_HII_PACKAGE_HEADER *Package,\r
IN EFI_HII_HANDLE Handle,\r
IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType\r
-);\r
+ );\r
\r
/**\r
\r
IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList,\r
IN EFI_HANDLE DriverHandle OPTIONAL,\r
OUT EFI_HII_HANDLE *Handle\r
-);\r
-\r
+ );\r
\r
/**\r
\r
(EFIAPI *EFI_HII_DATABASE_REMOVE_PACK)(\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN EFI_HII_HANDLE Handle\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN EFI_HII_HANDLE Handle,\r
IN CONST EFI_HII_PACKAGE_LIST_HEADER *PackageList\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN CONST EFI_GUID *PackageGuid,\r
IN OUT UINTN *HandleBufferLength,\r
OUT EFI_HII_HANDLE *Handle\r
-);\r
+ );\r
\r
/**\r
\r
IN EFI_HII_HANDLE Handle,\r
IN OUT UINTN *BufferSize,\r
OUT EFI_HII_PACKAGE_LIST_HEADER *Buffer\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN EFI_HII_DATABASE_NOTIFY PackageNotifyFn,\r
IN EFI_HII_DATABASE_NOTIFY_TYPE NotifyType,\r
OUT EFI_HANDLE *NotifyHandle\r
-);\r
-\r
+ );\r
\r
/**\r
\r
(EFIAPI *EFI_HII_DATABASE_UNREGISTER_NOTIFY)(\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN EFI_HANDLE NotificationHandle\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN OUT UINT16 *KeyGuidBufferLength,\r
OUT EFI_GUID *KeyGuidBuffer\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN CONST EFI_GUID *KeyGuid,\r
IN OUT UINT16 *KeyboardLayoutLength,\r
OUT EFI_HII_KEYBOARD_LAYOUT *KeyboardLayout\r
-);\r
+ );\r
\r
/**\r
\r
(EFIAPI *EFI_HII_SET_KEYBOARD_LAYOUT)(\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN CONST EFI_GUID *KeyGuid\r
-);\r
+ );\r
\r
/**\r
\r
IN CONST EFI_HII_DATABASE_PROTOCOL *This,\r
IN EFI_HII_HANDLE PackageListHandle,\r
OUT EFI_HANDLE *DriverHandle\r
-);\r
+ );\r
\r
///\r
/// Database manager for HII-related data structures.\r
///\r
struct _EFI_HII_DATABASE_PROTOCOL {\r
- EFI_HII_DATABASE_NEW_PACK NewPackageList;\r
- EFI_HII_DATABASE_REMOVE_PACK RemovePackageList;\r
- EFI_HII_DATABASE_UPDATE_PACK UpdatePackageList;\r
- EFI_HII_DATABASE_LIST_PACKS ListPackageLists;\r
- EFI_HII_DATABASE_EXPORT_PACKS ExportPackageLists;\r
- EFI_HII_DATABASE_REGISTER_NOTIFY RegisterPackageNotify;\r
- EFI_HII_DATABASE_UNREGISTER_NOTIFY UnregisterPackageNotify;\r
- EFI_HII_FIND_KEYBOARD_LAYOUTS FindKeyboardLayouts;\r
- EFI_HII_GET_KEYBOARD_LAYOUT GetKeyboardLayout;\r
- EFI_HII_SET_KEYBOARD_LAYOUT SetKeyboardLayout;\r
- EFI_HII_DATABASE_GET_PACK_HANDLE GetPackageListHandle;\r
+ EFI_HII_DATABASE_NEW_PACK NewPackageList;\r
+ EFI_HII_DATABASE_REMOVE_PACK RemovePackageList;\r
+ EFI_HII_DATABASE_UPDATE_PACK UpdatePackageList;\r
+ EFI_HII_DATABASE_LIST_PACKS ListPackageLists;\r
+ EFI_HII_DATABASE_EXPORT_PACKS ExportPackageLists;\r
+ EFI_HII_DATABASE_REGISTER_NOTIFY RegisterPackageNotify;\r
+ EFI_HII_DATABASE_UNREGISTER_NOTIFY UnregisterPackageNotify;\r
+ EFI_HII_FIND_KEYBOARD_LAYOUTS FindKeyboardLayouts;\r
+ EFI_HII_GET_KEYBOARD_LAYOUT GetKeyboardLayout;\r
+ EFI_HII_SET_KEYBOARD_LAYOUT SetKeyboardLayout;\r
+ EFI_HII_DATABASE_GET_PACK_HANDLE GetPackageListHandle;\r
};\r
\r
-extern EFI_GUID gEfiHiiDatabaseProtocolGuid;\r
+extern EFI_GUID gEfiHiiDatabaseProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_HII_FONT_PROTOCOL EFI_HII_FONT_PROTOCOL;\r
\r
-typedef VOID *EFI_FONT_HANDLE;\r
+typedef VOID *EFI_FONT_HANDLE;\r
\r
///\r
/// EFI_HII_OUT_FLAGS.\r
///\r
-typedef UINT32 EFI_HII_OUT_FLAGS;\r
+typedef UINT32 EFI_HII_OUT_FLAGS;\r
\r
-#define EFI_HII_OUT_FLAG_CLIP 0x00000001\r
-#define EFI_HII_OUT_FLAG_WRAP 0x00000002\r
-#define EFI_HII_OUT_FLAG_CLIP_CLEAN_Y 0x00000004\r
-#define EFI_HII_OUT_FLAG_CLIP_CLEAN_X 0x00000008\r
-#define EFI_HII_OUT_FLAG_TRANSPARENT 0x00000010\r
-#define EFI_HII_IGNORE_IF_NO_GLYPH 0x00000020\r
-#define EFI_HII_IGNORE_LINE_BREAK 0x00000040\r
-#define EFI_HII_DIRECT_TO_SCREEN 0x00000080\r
+#define EFI_HII_OUT_FLAG_CLIP 0x00000001\r
+#define EFI_HII_OUT_FLAG_WRAP 0x00000002\r
+#define EFI_HII_OUT_FLAG_CLIP_CLEAN_Y 0x00000004\r
+#define EFI_HII_OUT_FLAG_CLIP_CLEAN_X 0x00000008\r
+#define EFI_HII_OUT_FLAG_TRANSPARENT 0x00000010\r
+#define EFI_HII_IGNORE_IF_NO_GLYPH 0x00000020\r
+#define EFI_HII_IGNORE_LINE_BREAK 0x00000040\r
+#define EFI_HII_DIRECT_TO_SCREEN 0x00000080\r
\r
/**\r
Definition of EFI_HII_ROW_INFO.\r
///\r
/// The index of the first character in the string which is displayed on the line.\r
///\r
- UINTN StartIndex;\r
+ UINTN StartIndex;\r
///\r
/// The index of the last character in the string which is displayed on the line.\r
/// If this is the same as StartIndex, then no characters are displayed.\r
///\r
- UINTN EndIndex;\r
- UINTN LineHeight; ///< The height of the line, in pixels.\r
- UINTN LineWidth; ///< The width of the text on the line, in pixels.\r
+ UINTN EndIndex;\r
+ UINTN LineHeight; ///< The height of the line, in pixels.\r
+ UINTN LineWidth; ///< The width of the text on the line, in pixels.\r
\r
///\r
/// The font baseline offset in pixels from the bottom of the row, or 0 if none.\r
///\r
- UINTN BaselineOffset;\r
+ UINTN BaselineOffset;\r
} EFI_HII_ROW_INFO;\r
\r
///\r
/// Font info flag. All flags (FONT, SIZE, STYLE, and COLOR) are defined.\r
/// They are defined as EFI_FONT_INFO_***\r
///\r
-typedef UINT32 EFI_FONT_INFO_MASK;\r
+typedef UINT32 EFI_FONT_INFO_MASK;\r
\r
#define EFI_FONT_INFO_SYS_FONT 0x00000001\r
#define EFI_FONT_INFO_SYS_SIZE 0x00000002\r
// EFI_FONT_INFO\r
//\r
typedef struct {\r
- EFI_HII_FONT_STYLE FontStyle;\r
- UINT16 FontSize; ///< character cell height in pixels\r
- CHAR16 FontName[1];\r
+ EFI_HII_FONT_STYLE FontStyle;\r
+ UINT16 FontSize; ///< character cell height in pixels\r
+ CHAR16 FontName[1];\r
} EFI_FONT_INFO;\r
\r
/**\r
font requested and the font available.\r
**/\r
typedef struct _EFI_FONT_DISPLAY_INFO {\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor;\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor;\r
- EFI_FONT_INFO_MASK FontInfoMask;\r
- EFI_FONT_INFO FontInfo;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor;\r
+ EFI_FONT_INFO_MASK FontInfoMask;\r
+ EFI_FONT_INFO FontInfo;\r
} EFI_FONT_DISPLAY_INFO;\r
\r
/**\r
OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL,\r
OUT UINTN *RowInfoArraySize OPTIONAL,\r
OUT UINTN *ColumnInfoArray OPTIONAL\r
-);\r
-\r
-\r
+ );\r
\r
/**\r
\r
OUT EFI_HII_ROW_INFO **RowInfoArray OPTIONAL,\r
OUT UINTN *RowInfoArraySize OPTIONAL,\r
OUT UINTN *ColumnInfoArray OPTIONAL\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN CONST EFI_FONT_DISPLAY_INFO *StringInfo,\r
OUT EFI_IMAGE_OUTPUT **Blt,\r
OUT UINTN *Baseline OPTIONAL\r
-);\r
+ );\r
\r
/**\r
\r
IN CONST EFI_FONT_DISPLAY_INFO *StringInfoIn OPTIONAL,\r
OUT EFI_FONT_DISPLAY_INFO **StringInfoOut,\r
IN CONST EFI_STRING String OPTIONAL\r
-);\r
+ );\r
\r
///\r
/// The protocol provides the service to retrieve the font informations.\r
///\r
struct _EFI_HII_FONT_PROTOCOL {\r
- EFI_HII_STRING_TO_IMAGE StringToImage;\r
- EFI_HII_STRING_ID_TO_IMAGE StringIdToImage;\r
- EFI_HII_GET_GLYPH GetGlyph;\r
- EFI_HII_GET_FONT_INFO GetFontInfo;\r
+ EFI_HII_STRING_TO_IMAGE StringToImage;\r
+ EFI_HII_STRING_ID_TO_IMAGE StringIdToImage;\r
+ EFI_HII_GET_GLYPH GetGlyph;\r
+ EFI_HII_GET_FONT_INFO GetFontInfo;\r
};\r
\r
-extern EFI_GUID gEfiHiiFontProtocolGuid;\r
-\r
+extern EFI_GUID gEfiHiiFontProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_HII_IMAGE_PROTOCOL EFI_HII_IMAGE_PROTOCOL;\r
\r
-\r
///\r
/// Flags in EFI_IMAGE_INPUT\r
///\r
-#define EFI_IMAGE_TRANSPARENT 0x00000001\r
+#define EFI_IMAGE_TRANSPARENT 0x00000001\r
\r
/**\r
\r
\r
**/\r
typedef struct _EFI_IMAGE_INPUT {\r
- UINT32 Flags;\r
- UINT16 Width;\r
- UINT16 Height;\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;\r
+ UINT32 Flags;\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;\r
} EFI_IMAGE_INPUT;\r
\r
-\r
/**\r
\r
This function adds the image Image to the group of images\r
IN EFI_HII_HANDLE PackageList,\r
OUT EFI_IMAGE_ID *ImageId,\r
IN CONST EFI_IMAGE_INPUT *Image\r
-);\r
+ );\r
\r
/**\r
\r
IN EFI_HII_HANDLE PackageList,\r
IN EFI_IMAGE_ID ImageId,\r
OUT EFI_IMAGE_INPUT *Image\r
-);\r
+ );\r
\r
/**\r
\r
IN EFI_HII_HANDLE PackageList,\r
IN EFI_IMAGE_ID ImageId,\r
IN CONST EFI_IMAGE_INPUT *Image\r
-);\r
-\r
+ );\r
\r
///\r
/// EFI_HII_DRAW_FLAGS describes how the image is to be drawn.\r
/// These flags are defined as EFI_HII_DRAW_FLAG_***\r
///\r
-typedef UINT32 EFI_HII_DRAW_FLAGS;\r
+typedef UINT32 EFI_HII_DRAW_FLAGS;\r
\r
#define EFI_HII_DRAW_FLAG_CLIP 0x00000001\r
#define EFI_HII_DRAW_FLAG_TRANSPARENT 0x00000030\r
\r
**/\r
typedef struct _EFI_IMAGE_OUTPUT {\r
- UINT16 Width;\r
- UINT16 Height;\r
+ UINT16 Width;\r
+ UINT16 Height;\r
union {\r
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL *Screen;\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Bitmap;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *Screen;\r
} Image;\r
} EFI_IMAGE_OUTPUT;\r
\r
-\r
/**\r
\r
This function renders an image to a bitmap or the screen using\r
IN OUT EFI_IMAGE_OUTPUT **Blt,\r
IN UINTN BltX,\r
IN UINTN BltY\r
-);\r
+ );\r
\r
/**\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_HII_DRAW_IMAGE_ID)(\r
-IN CONST EFI_HII_IMAGE_PROTOCOL *This,\r
-IN EFI_HII_DRAW_FLAGS Flags,\r
-IN EFI_HII_HANDLE PackageList,\r
-IN EFI_IMAGE_ID ImageId,\r
-IN OUT EFI_IMAGE_OUTPUT **Blt,\r
-IN UINTN BltX,\r
-IN UINTN BltY\r
-);\r
-\r
+ IN CONST EFI_HII_IMAGE_PROTOCOL *This,\r
+ IN EFI_HII_DRAW_FLAGS Flags,\r
+ IN EFI_HII_HANDLE PackageList,\r
+ IN EFI_IMAGE_ID ImageId,\r
+ IN OUT EFI_IMAGE_OUTPUT **Blt,\r
+ IN UINTN BltX,\r
+ IN UINTN BltY\r
+ );\r
\r
///\r
/// Services to access to images in the images database.\r
///\r
struct _EFI_HII_IMAGE_PROTOCOL {\r
- EFI_HII_NEW_IMAGE NewImage;\r
- EFI_HII_GET_IMAGE GetImage;\r
- EFI_HII_SET_IMAGE SetImage;\r
- EFI_HII_DRAW_IMAGE DrawImage;\r
- EFI_HII_DRAW_IMAGE_ID DrawImageId;\r
+ EFI_HII_NEW_IMAGE NewImage;\r
+ EFI_HII_GET_IMAGE GetImage;\r
+ EFI_HII_SET_IMAGE SetImage;\r
+ EFI_HII_DRAW_IMAGE DrawImage;\r
+ EFI_HII_DRAW_IMAGE_ID DrawImageId;\r
};\r
\r
-extern EFI_GUID gEfiHiiImageProtocolGuid;\r
+extern EFI_GUID gEfiHiiImageProtocolGuid;\r
\r
#endif\r
-\r
-\r
This Protocol was introduced in UEFI Specification 2.6.\r
\r
**/\r
+\r
#ifndef __HII_IMAGE_DECODER_H__\r
#define __HII_IMAGE_DECODER_H__\r
\r
#define EFI_HII_IMAGE_DECODER_PROTOCOL_GUID \\r
{0x9e66f251, 0x727c, 0x418c, { 0xbf, 0xd6, 0xc2, 0xb4, 0x25, 0x28, 0x18, 0xea }}\r
\r
-\r
#define EFI_HII_IMAGE_DECODER_NAME_JPEG_GUID \\r
{0xefefd093, 0xd9b, 0x46eb, { 0xa8, 0x56, 0x48, 0x35, 0x7, 0x0, 0xc9, 0x8 }}\r
\r
UINT8 ColorDepthInBits;\r
} EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER;\r
\r
-#define EFI_IMAGE_JPEG_SCANTYPE_PROGREESSIVE 0x01\r
-#define EFI_IMAGE_JPEG_SCANTYPE_INTERLACED 0x02\r
+#define EFI_IMAGE_JPEG_SCANTYPE_PROGREESSIVE 0x01\r
+#define EFI_IMAGE_JPEG_SCANTYPE_INTERLACED 0x02\r
\r
//\r
// EFI_HII_IMAGE_DECODER_JPEG_INFO\r
// Reserved Reserved\r
//\r
typedef struct _EFI_HII_IMAGE_DECODER_JPEG_INFO {\r
- EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
- UINT16 ScanType;\r
- UINT64 Reserved;\r
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
+ UINT16 ScanType;\r
+ UINT64 Reserved;\r
} EFI_HII_IMAGE_DECODER_JPEG_INFO;\r
\r
//\r
// Reserved Reserved\r
//\r
typedef struct _EFI_HII_IMAGE_DECODER_PNG_INFO {\r
- EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
- UINT16 Channels;\r
- UINT64 Reserved;\r
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
+ UINT16 Channels;\r
+ UINT64 Reserved;\r
} EFI_HII_IMAGE_DECODER_PNG_INFO;\r
\r
//\r
// EFI_HII_IMAGE_DECODER_OTHER_INFO\r
//\r
typedef struct _EFI_HII_IMAGE_DECODER_OTHER_INFO {\r
- EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
- CHAR16 ImageExtenion[1];\r
+ EFI_HII_IMAGE_DECODER_IMAGE_INFO_HEADER Header;\r
+ CHAR16 ImageExtenion[1];\r
//\r
// Variable length of image file extension name.\r
//\r
EFI_HII_IMAGE_DECODER_DECODE DecodeImage;\r
};\r
\r
-extern EFI_GUID gEfiHiiImageDecoderProtocolGuid;\r
-extern EFI_GUID gEfiHiiImageDecoderNameJpegGuid;\r
-extern EFI_GUID gEfiHiiImageDecoderNamePngGuid;\r
+extern EFI_GUID gEfiHiiImageDecoderProtocolGuid;\r
+extern EFI_GUID gEfiHiiImageDecoderNameJpegGuid;\r
+extern EFI_GUID gEfiHiiImageDecoderNamePngGuid;\r
\r
#endif\r
/// Protocol which allows access to the images in the images database.\r
///\r
struct _EFI_HII_IMAGE_EX_PROTOCOL {\r
- EFI_HII_NEW_IMAGE_EX NewImageEx;\r
- EFI_HII_GET_IMAGE_EX GetImageEx;\r
- EFI_HII_SET_IMAGE_EX SetImageEx;\r
- EFI_HII_DRAW_IMAGE_EX DrawImageEx;\r
- EFI_HII_DRAW_IMAGE_ID_EX DrawImageIdEx;\r
- EFI_HII_GET_IMAGE_INFO GetImageInfo;\r
+ EFI_HII_NEW_IMAGE_EX NewImageEx;\r
+ EFI_HII_GET_IMAGE_EX GetImageEx;\r
+ EFI_HII_SET_IMAGE_EX SetImageEx;\r
+ EFI_HII_DRAW_IMAGE_EX DrawImageEx;\r
+ EFI_HII_DRAW_IMAGE_ID_EX DrawImageIdEx;\r
+ EFI_HII_GET_IMAGE_INFO GetImageInfo;\r
};\r
\r
-extern EFI_GUID gEfiHiiImageExProtocolGuid;\r
+extern EFI_GUID gEfiHiiImageExProtocolGuid;\r
\r
#endif\r
#define EFI_HII_PACKAGE_LIST_PROTOCOL_GUID \\r
{ 0x6a1ee763, 0xd47a, 0x43b4, {0xaa, 0xbe, 0xef, 0x1d, 0xe2, 0xab, 0x56, 0xfc}}\r
\r
-typedef EFI_HII_PACKAGE_LIST_HEADER * EFI_HII_PACKAGE_LIST_PROTOCOL;\r
-\r
-extern EFI_GUID gEfiHiiPackageListProtocolGuid;\r
-\r
+typedef EFI_HII_PACKAGE_LIST_HEADER *EFI_HII_PACKAGE_LIST_PROTOCOL;\r
\r
+extern EFI_GUID gEfiHiiPackageListProtocolGuid;\r
\r
#endif\r
-\r
-\r
#define EFI_HII_POPUP_PROTOCOL_GUID \\r
{0x4311edc0, 0x6054, 0x46d4, {0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc}}\r
\r
-#define EFI_HII_POPUP_PROTOCOL_REVISION 1\r
+#define EFI_HII_POPUP_PROTOCOL_REVISION 1\r
\r
typedef struct _EFI_HII_POPUP_PROTOCOL EFI_HII_POPUP_PROTOCOL;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HII_CREATE_POPUP) (\r
+(EFIAPI *EFI_HII_CREATE_POPUP)(\r
IN EFI_HII_POPUP_PROTOCOL *This,\r
IN EFI_HII_POPUP_STYLE PopupStyle,\r
IN EFI_HII_POPUP_TYPE PopupType,\r
IN EFI_HII_HANDLE HiiHandle,\r
IN EFI_STRING_ID Message,\r
OUT EFI_HII_POPUP_SELECTION *UserSelection OPTIONAL\r
-);\r
+ );\r
\r
struct _EFI_HII_POPUP_PROTOCOL {\r
- UINT64 Revision;\r
- EFI_HII_CREATE_POPUP CreatePopup;\r
+ UINT64 Revision;\r
+ EFI_HII_CREATE_POPUP CreatePopup;\r
};\r
\r
-extern EFI_GUID gEfiHiiPopupProtocolGuid;\r
+extern EFI_GUID gEfiHiiPopupProtocolGuid;\r
\r
#endif\r
-\r
IN CONST CHAR16 *LanguageName OPTIONAL,\r
IN CONST EFI_STRING String,\r
IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL\r
-);\r
-\r
+ );\r
\r
/**\r
This function retrieves the string specified by StringId which is associated\r
OUT EFI_STRING String,\r
IN OUT UINTN *StringSize,\r
OUT EFI_FONT_INFO **StringFontInfo OPTIONAL\r
-);\r
+ );\r
\r
/**\r
This function updates the string specified by StringId in the specified PackageList to the text\r
IN CONST CHAR8 *Language,\r
IN EFI_STRING String,\r
IN CONST EFI_FONT_INFO *StringFontInfo OPTIONAL\r
-);\r
-\r
+ );\r
\r
/**\r
This function returns the list of supported languages.\r
IN EFI_HII_HANDLE PackageList,\r
IN OUT CHAR8 *Languages,\r
IN OUT UINTN *LanguagesSize\r
-);\r
-\r
+ );\r
\r
/**\r
Each string package has associated with it a single primary language and zero\r
IN CONST CHAR8 *PrimaryLanguage,\r
IN OUT CHAR8 *SecondaryLanguages,\r
IN OUT UINTN *SecondaryLanguagesSize\r
-);\r
-\r
+ );\r
\r
///\r
/// Services to manipulate the string.\r
///\r
struct _EFI_HII_STRING_PROTOCOL {\r
- EFI_HII_NEW_STRING NewString;\r
- EFI_HII_GET_STRING GetString;\r
- EFI_HII_SET_STRING SetString;\r
- EFI_HII_GET_LANGUAGES GetLanguages;\r
- EFI_HII_GET_2ND_LANGUAGES GetSecondaryLanguages;\r
+ EFI_HII_NEW_STRING NewString;\r
+ EFI_HII_GET_STRING GetString;\r
+ EFI_HII_SET_STRING SetString;\r
+ EFI_HII_GET_LANGUAGES GetLanguages;\r
+ EFI_HII_GET_2ND_LANGUAGES GetSecondaryLanguages;\r
};\r
\r
-\r
-extern EFI_GUID gEfiHiiStringProtocolGuid;\r
+extern EFI_GUID gEfiHiiStringProtocolGuid;\r
\r
#endif\r
/// information in every TCP connection made by this instance. In addition, when set\r
/// to TRUE, LocalAddress and LocalSubnet are ignored.\r
///\r
- BOOLEAN UseDefaultAddress;\r
+ BOOLEAN UseDefaultAddress;\r
///\r
/// If UseDefaultAddress is set to FALSE, this defines the local IP address to be\r
/// used in every TCP connection opened by this instance.\r
///\r
- EFI_IPv4_ADDRESS LocalAddress;\r
+ EFI_IPv4_ADDRESS LocalAddress;\r
///\r
/// If UseDefaultAddress is set to FALSE, this defines the local subnet to be used\r
/// in every TCP connection opened by this instance.\r
///\r
- EFI_IPv4_ADDRESS LocalSubnet;\r
+ EFI_IPv4_ADDRESS LocalSubnet;\r
///\r
/// This defines the local port to be used in\r
/// every TCP connection opened by this instance.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
} EFI_HTTPv4_ACCESS_POINT;\r
\r
///\r
///\r
/// Local IP address to be used in every TCP connection opened by this instance.\r
///\r
- EFI_IPv6_ADDRESS LocalAddress;\r
+ EFI_IPv6_ADDRESS LocalAddress;\r
///\r
/// Local port to be used in every TCP connection opened by this instance.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
} EFI_HTTPv6_ACCESS_POINT;\r
\r
///\r
/// EFI_HTTP_CONFIG_DATA_ACCESS_POINT\r
///\r
\r
-\r
typedef struct {\r
///\r
/// HTTP version that this instance will support.\r
///\r
- EFI_HTTP_VERSION HttpVersion;\r
+ EFI_HTTP_VERSION HttpVersion;\r
///\r
/// Time out (in milliseconds) when blocking for requests.\r
///\r
- UINT32 TimeOutMillisec;\r
+ UINT32 TimeOutMillisec;\r
///\r
/// Defines behavior of EFI DNS and TCP protocols consumed by this instance. If\r
/// FALSE, this instance will use EFI_DNS4_PROTOCOL and EFI_TCP4_PROTOCOL. If TRUE,\r
/// this instance will use EFI_DNS6_PROTOCOL and EFI_TCP6_PROTOCOL.\r
///\r
- BOOLEAN LocalAddressIsIPv6;\r
+ BOOLEAN LocalAddressIsIPv6;\r
\r
union {\r
///\r
/// When LocalAddressIsIPv6 is FALSE, this points to the local address, subnet, and\r
/// port used by the underlying TCP protocol.\r
///\r
- EFI_HTTPv4_ACCESS_POINT *IPv4Node;\r
+ EFI_HTTPv4_ACCESS_POINT *IPv4Node;\r
///\r
/// When LocalAddressIsIPv6 is TRUE, this points to the local IPv6 address and port\r
/// used by the underlying TCP protocol.\r
///\r
- EFI_HTTPv6_ACCESS_POINT *IPv6Node;\r
+ EFI_HTTPv6_ACCESS_POINT *IPv6Node;\r
} AccessPoint;\r
} EFI_HTTP_CONFIG_DATA;\r
\r
///\r
/// The HTTP method (e.g. GET, POST) for this HTTP Request.\r
///\r
- EFI_HTTP_METHOD Method;\r
+ EFI_HTTP_METHOD Method;\r
///\r
/// The URI of a remote host. From the information in this field, the HTTP instance\r
/// will be able to determine whether to use HTTP or HTTPS and will also be able to\r
/// determine the port number to use. If no port number is specified, port 80 (HTTP)\r
/// is assumed. See RFC 3986 for more details on URI syntax.\r
///\r
- CHAR16 *Url;\r
+ CHAR16 *Url;\r
} EFI_HTTP_REQUEST_DATA;\r
\r
///\r
///\r
/// Response status code returned by the remote host.\r
///\r
- EFI_HTTP_STATUS_CODE StatusCode;\r
+ EFI_HTTP_STATUS_CODE StatusCode;\r
} EFI_HTTP_RESPONSE_DATA;\r
\r
///\r
/// Null terminated string which describes a field name. See RFC 2616 Section 14 for\r
/// detailed information about field names.\r
///\r
- CHAR8 *FieldName;\r
+ CHAR8 *FieldName;\r
///\r
/// Null terminated string which describes the corresponding field value. See RFC 2616\r
/// Section 14 for detailed information about field values.\r
///\r
- CHAR8 *FieldValue;\r
+ CHAR8 *FieldValue;\r
} EFI_HTTP_HEADER;\r
\r
///\r
/// When the token is used to send a HTTP request, Request is a pointer to storage that\r
/// contains such data as URL and HTTP method.\r
///\r
- EFI_HTTP_REQUEST_DATA *Request;\r
+ EFI_HTTP_REQUEST_DATA *Request;\r
///\r
/// When used to await a response, Response points to storage containing HTTP response\r
/// status code.\r
///\r
- EFI_HTTP_RESPONSE_DATA *Response;\r
+ EFI_HTTP_RESPONSE_DATA *Response;\r
} Data;\r
///\r
/// Number of HTTP header structures in Headers list. On request, this count is\r
/// provided by the caller. On response, this count is provided by the HTTP driver.\r
///\r
- UINTN HeaderCount;\r
+ UINTN HeaderCount;\r
///\r
/// Array containing list of HTTP headers. On request, this array is populated by the\r
/// caller. On response, this array is allocated and populated by the HTTP driver. It\r
/// is the responsibility of the caller to free this memory on both request and\r
/// response.\r
///\r
- EFI_HTTP_HEADER *Headers;\r
+ EFI_HTTP_HEADER *Headers;\r
///\r
/// Length in bytes of the HTTP body. This can be zero depending on the HttpMethod type.\r
///\r
- UINTN BodyLength;\r
+ UINTN BodyLength;\r
///\r
/// Body associated with the HTTP request or response. This can be NULL depending on\r
/// the HttpMethod type.\r
///\r
- VOID *Body;\r
+ VOID *Body;\r
} EFI_HTTP_MESSAGE;\r
\r
-\r
///\r
/// EFI_HTTP_TOKEN\r
///\r
/// Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL. The Task Priority\r
/// Level (TPL) of Event must be lower than or equal to TPL_CALLBACK.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Status will be set to one of the following value if the HTTP request is\r
/// successfully sent or if an unexpected error occurs:\r
/// EFI_TIMEOUT: The HTTP request timed out before reaching the remote host.\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Pointer to storage containing HTTP message data.\r
///\r
- EFI_HTTP_MESSAGE *Message;\r
+ EFI_HTTP_MESSAGE *Message;\r
} EFI_HTTP_TOKEN;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_HTTP_REQUEST) (\r
+(EFIAPI *EFI_HTTP_REQUEST)(\r
IN EFI_HTTP_PROTOCOL *This,\r
IN EFI_HTTP_TOKEN *Token\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_HTTP_RESPONSE) (\r
+(EFIAPI *EFI_HTTP_RESPONSE)(\r
IN EFI_HTTP_PROTOCOL *This,\r
IN EFI_HTTP_TOKEN *Token\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_HTTP_POLL) (\r
+(EFIAPI *EFI_HTTP_POLL)(\r
IN EFI_HTTP_PROTOCOL *This\r
);\r
\r
/// TCP protocol.\r
///\r
struct _EFI_HTTP_PROTOCOL {\r
- EFI_HTTP_GET_MODE_DATA GetModeData;\r
- EFI_HTTP_CONFIGURE Configure;\r
- EFI_HTTP_REQUEST Request;\r
- EFI_HTTP_CANCEL Cancel;\r
- EFI_HTTP_RESPONSE Response;\r
- EFI_HTTP_POLL Poll;\r
+ EFI_HTTP_GET_MODE_DATA GetModeData;\r
+ EFI_HTTP_CONFIGURE Configure;\r
+ EFI_HTTP_REQUEST Request;\r
+ EFI_HTTP_CANCEL Cancel;\r
+ EFI_HTTP_RESPONSE Response;\r
+ EFI_HTTP_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiHttpServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiHttpProtocolGuid;\r
+extern EFI_GUID gEfiHttpServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiHttpProtocolGuid;\r
\r
#endif\r
0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58, 0x20, 0xb1, 0xd6, 0x52, 0x99} \\r
}\r
\r
-typedef struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL EFI_HTTP_BOOT_CALLBACK_PROTOCOL;\r
+typedef struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL EFI_HTTP_BOOT_CALLBACK_PROTOCOL;\r
\r
///\r
/// EFI_HTTP_BOOT_CALLBACK_DATA_TYPE\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_HTTP_BOOT_CALLBACK) (\r
+(EFIAPI *EFI_HTTP_BOOT_CALLBACK)(\r
IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL *This,\r
IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPE DataType,\r
IN BOOLEAN Received,\r
IN UINT32 DataLength,\r
IN VOID *Data OPTIONAL\r
- );\r
+ );\r
\r
///\r
/// EFI HTTP Boot Callback Protocol is invoked when the HTTP Boot driver is about to transmit or\r
/// as the Load File Protocol for the HTTP Boot.\r
///\r
struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL {\r
- EFI_HTTP_BOOT_CALLBACK Callback;\r
+ EFI_HTTP_BOOT_CALLBACK Callback;\r
};\r
\r
-extern EFI_GUID gEfiHttpBootCallbackProtocolGuid;\r
+extern EFI_GUID gEfiHttpBootCallbackProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_HTTP_UTILITIES_PROTOCOL EFI_HTTP_UTILITIES_PROTOCOL;\r
\r
-\r
/**\r
Create HTTP header based on a combination of seed header, fields\r
to delete, and fields to append.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_HTTP_UTILS_BUILD) (\r
+(EFIAPI *EFI_HTTP_UTILS_BUILD)(\r
IN EFI_HTTP_UTILITIES_PROTOCOL *This,\r
IN UINTN SeedMessageSize,\r
IN VOID *SeedMessage OPTIONAL,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_HTTP_UTILS_PARSE) (\r
+(EFIAPI *EFI_HTTP_UTILS_PARSE)(\r
IN EFI_HTTP_UTILITIES_PROTOCOL *This,\r
IN CHAR8 *HttpMessage,\r
IN UINTN HttpMessageSize,\r
OUT UINTN *FieldCount\r
);\r
\r
-\r
///\r
/// EFI_HTTP_UTILITIES_PROTOCOL\r
/// designed to be used by EFI drivers and applications to parse HTTP\r
/// infrastructure.\r
///\r
struct _EFI_HTTP_UTILITIES_PROTOCOL {\r
- EFI_HTTP_UTILS_BUILD Build;\r
- EFI_HTTP_UTILS_PARSE Parse;\r
+ EFI_HTTP_UTILS_BUILD Build;\r
+ EFI_HTTP_UTILS_PARSE Parse;\r
};\r
\r
-extern EFI_GUID gEfiHttpUtilitiesProtocolGuid;\r
+extern EFI_GUID gEfiHttpUtilitiesProtocolGuid;\r
\r
#endif\r
///\r
typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL;\r
\r
-\r
/**\r
Enable access to an I2C bus configuration.\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION) (\r
+(EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION)(\r
IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,\r
IN UINTN I2cBusConfiguration,\r
IN EFI_EVENT Event OPTIONAL,\r
///\r
/// Enable an I2C bus configuration for use.\r
///\r
- EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration;\r
+ EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration;\r
};\r
\r
///\r
/// Reference to variable defined in the .DEC file\r
///\r
-extern EFI_GUID gEfiI2cBusConfigurationManagementProtocolGuid;\r
+extern EFI_GUID gEfiI2cBusConfigurationManagementProtocolGuid;\r
\r
-#endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__\r
+#endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__\r
\r
#include <Pi/PiI2c.h>\r
\r
-#define EFI_I2C_ENUMERATE_PROTOCOL_GUID { 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, 0xe7, 0x01, 0x89, 0x4c }}\r
+#define EFI_I2C_ENUMERATE_PROTOCOL_GUID { 0xda8cd7c4, 0x1c00, 0x49e2, { 0x80, 0x3e, 0x52, 0x14, 0xe7, 0x01, 0x89, 0x4c }}\r
\r
-typedef struct _EFI_I2C_ENUMERATE_PROTOCOL EFI_I2C_ENUMERATE_PROTOCOL;\r
+typedef struct _EFI_I2C_ENUMERATE_PROTOCOL EFI_I2C_ENUMERATE_PROTOCOL;\r
\r
/**\r
Enumerate the I2C devices\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE) (\r
+(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE)(\r
IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,\r
IN OUT CONST EFI_I2C_DEVICE **Device\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY) (\r
+(EFIAPI *EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY)(\r
IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This,\r
IN UINTN I2cBusConfiguration,\r
OUT UINTN *BusClockHertz\r
/// Traverse the set of I2C devices on an I2C bus. This routine\r
/// returns the next I2C device on an I2C bus.\r
///\r
- EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate;\r
+ EFI_I2C_ENUMERATE_PROTOCOL_ENUMERATE Enumerate;\r
\r
///\r
/// Get the requested I2C bus frequency for a specified bus\r
/// configuration.\r
///\r
- EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY GetBusFrequency;\r
+ EFI_I2C_ENUMERATE_PROTOCOL_GET_BUS_FREQUENCY GetBusFrequency;\r
};\r
\r
///\r
/// Reference to variable defined in the .DEC file\r
///\r
-extern EFI_GUID gEfiI2cEnumerateProtocolGuid;\r
+extern EFI_GUID gEfiI2cEnumerateProtocolGuid;\r
\r
-#endif // __I2C_ENUMERATE_H__\r
+#endif // __I2C_ENUMERATE_H__\r
///\r
typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;\r
\r
-\r
/**\r
Queue an I2C transaction for execution on the I2C controller.\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST) (\r
+(EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST)(\r
IN CONST EFI_I2C_HOST_PROTOCOL *This,\r
IN UINTN I2cBusConfiguration,\r
IN UINTN SlaveAddress,\r
///\r
/// Queue an I2C transaction for execution on the I2C bus\r
///\r
- EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;\r
+ EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;\r
\r
///\r
/// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure\r
/// containing the capabilities of the I2C host controller.\r
///\r
- CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
};\r
\r
///\r
/// Reference to variable defined in the .DEC file\r
///\r
-extern EFI_GUID gEfiI2cHostProtocolGuid;\r
+extern EFI_GUID gEfiI2cHostProtocolGuid;\r
\r
-#endif // __I2C_HOST_H__\r
+#endif // __I2C_HOST_H__\r
\r
#include <Pi/PiI2c.h>\r
\r
-#define EFI_I2C_IO_PROTOCOL_GUID { 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, 0x06, 0x65, 0xa2, 0x8e }}\r
+#define EFI_I2C_IO_PROTOCOL_GUID { 0xb60a3e6b, 0x18c4, 0x46e5, { 0xa2, 0x9a, 0xc9, 0xa1, 0x06, 0x65, 0xa2, 0x8e }}\r
\r
///\r
/// I2C I/O protocol\r
/// for the I2C device required to implement the EFI_I2C_ENUMERATE_PROTOCOL.\r
/// The order of the list must be preserved.\r
///\r
-typedef struct _EFI_I2C_IO_PROTOCOL EFI_I2C_IO_PROTOCOL;\r
-\r
+typedef struct _EFI_I2C_IO_PROTOCOL EFI_I2C_IO_PROTOCOL;\r
\r
/**\r
Queue an I2C transaction for execution on the I2C device.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST) (\r
+(EFIAPI *EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST)(\r
IN CONST EFI_I2C_IO_PROTOCOL *This,\r
IN UINTN SlaveAddressIndex,\r
IN EFI_EVENT Event OPTIONAL,\r
///\r
/// Queue an I2C transaction for execution on the I2C device.\r
///\r
- EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST QueueRequest;\r
+ EFI_I2C_IO_PROTOCOL_QUEUE_REQUEST QueueRequest;\r
\r
///\r
/// Unique value assigned by the silicon manufacture or the third\r
/// combines both the manufacture name and the I2C part number into\r
/// a single value specified as a GUID.\r
///\r
- CONST EFI_GUID *DeviceGuid;\r
+ CONST EFI_GUID *DeviceGuid;\r
\r
///\r
/// Unique ID of the I2C part within the system\r
///\r
- UINT32 DeviceIndex;\r
+ UINT32 DeviceIndex;\r
\r
///\r
/// Hardware revision - ACPI _HRV value. See the Advanced Configuration\r
/// and Power Interface Specification, Revision 5.0 for the field format\r
/// and the Plug and play support for I2C web-page for restriction on values.\r
///\r
- UINT32 HardwareRevision;\r
+ UINT32 HardwareRevision;\r
\r
///\r
/// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing\r
/// the capabilities of the I2C host controller.\r
///\r
- CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
};\r
\r
///\r
/// Reference to variable defined in the .DEC file\r
///\r
-extern EFI_GUID gEfiI2cIoProtocolGuid;\r
+extern EFI_GUID gEfiI2cIoProtocolGuid;\r
\r
-#endif // __I2C_IO_H__\r
+#endif // __I2C_IO_H__\r
\r
#include <Pi/PiI2c.h>\r
\r
-#define EFI_I2C_MASTER_PROTOCOL_GUID { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }}\r
+#define EFI_I2C_MASTER_PROTOCOL_GUID { 0xcd72881f, 0x45b5, 0x4feb, { 0x98, 0xc8, 0x31, 0x3d, 0xa8, 0x11, 0x74, 0x62 }}\r
\r
typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL;\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY) (\r
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY)(\r
IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r
IN OUT UINTN *BusClockHertz\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET) (\r
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_RESET)(\r
IN CONST EFI_I2C_MASTER_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST) (\r
+(EFIAPI *EFI_I2C_MASTER_PROTOCOL_START_REQUEST)(\r
IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r
IN UINTN SlaveAddress,\r
IN EFI_I2C_REQUEST_PACKET *RequestPacket,\r
///\r
/// Set the clock frequency for the I2C bus.\r
///\r
- EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency;\r
+ EFI_I2C_MASTER_PROTOCOL_SET_BUS_FREQUENCY SetBusFrequency;\r
\r
///\r
/// Reset the I2C host controller.\r
///\r
- EFI_I2C_MASTER_PROTOCOL_RESET Reset;\r
+ EFI_I2C_MASTER_PROTOCOL_RESET Reset;\r
\r
///\r
/// Start an I2C transaction in master mode on the host controller.\r
///\r
- EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest;\r
+ EFI_I2C_MASTER_PROTOCOL_START_REQUEST StartRequest;\r
\r
///\r
/// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing\r
/// the capabilities of the I2C host controller.\r
///\r
- CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
+ CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r
};\r
\r
-extern EFI_GUID gEfiI2cMasterProtocolGuid;\r
+extern EFI_GUID gEfiI2cMasterProtocolGuid;\r
\r
-#endif // __I2C_MASTER_H__\r
+#endif // __I2C_MASTER_H__\r
OUT VOID *Buffer\r
);\r
\r
-\r
-\r
/**\r
Sets the iSCSI Initiator Name.\r
\r
/// iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name.\r
///\r
struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL {\r
- EFI_ISCSI_INITIATOR_NAME_GET Get;\r
- EFI_ISCSI_INITIATOR_NAME_SET Set;\r
+ EFI_ISCSI_INITIATOR_NAME_GET Get;\r
+ EFI_ISCSI_INITIATOR_NAME_SET Set;\r
};\r
\r
-extern EFI_GUID gEfiIScsiInitiatorNameProtocolGuid;\r
+extern EFI_GUID gEfiIScsiInitiatorNameProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Forward declaration for EFI_IDE_CONTROLLER_INIT_PROTOCOL.\r
///\r
-typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL;\r
+typedef struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL EFI_IDE_CONTROLLER_INIT_PROTOCOL;\r
\r
///\r
/// The phase of the IDE Controller enumeration.\r
/// EFI_ATA_MODE structure.\r
///\r
typedef struct {\r
- BOOLEAN Valid; ///< TRUE if Mode is valid.\r
- UINT32 Mode; ///< The actual ATA mode. This field is not a bit map.\r
+ BOOLEAN Valid; ///< TRUE if Mode is valid.\r
+ UINT32 Mode; ///< The actual ATA mode. This field is not a bit map.\r
} EFI_ATA_MODE;\r
\r
///\r
/// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL\r
/// is defined below.\r
///\r
- EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol;\r
+ EFI_ATA_EXT_TRANSFER_PROTOCOL TransferProtocol;\r
///\r
/// The mode for operating the transfer protocol that is identified by TransferProtocol.\r
///\r
- UINT32 Mode;\r
+ UINT32 Mode;\r
} EFI_ATA_EXTENDED_MODE;\r
\r
///\r
/// of PIO mode 1 is governed by the ATA/ATAPI specification. Type EFI_ATA_MODE\r
/// is defined below.\r
///\r
- EFI_ATA_MODE PioMode;\r
+ EFI_ATA_MODE PioMode;\r
///\r
/// This field specifies the single word DMA mode. Single word DMA modes are defined\r
/// in the ATA/ATAPI specification, versions 1 and 2. Single word DMA support was\r
/// mode 1. The actual meaning of single word DMA mode 1 is governed by the ATA/\r
/// ATAPI specification.\r
///\r
- EFI_ATA_MODE SingleWordDmaMode;\r
+ EFI_ATA_MODE SingleWordDmaMode;\r
///\r
/// This field specifies the multiword DMA mode. Various multiword DMA modes are\r
/// defined in the ATA/ATAPI specification. A value of 1 in this field means multiword\r
/// DMA mode 1. The actual meaning of multiword DMA mode 1 is governed by the\r
/// ATA/ATAPI specification.\r
///\r
- EFI_ATA_MODE MultiWordDmaMode;\r
+ EFI_ATA_MODE MultiWordDmaMode;\r
///\r
/// This field specifies the ultra DMA (UDMA) mode. UDMA modes are defined in the\r
/// ATA/ATAPI specification. A value of 1 in this field means UDMA mode 1. The\r
/// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification.\r
///\r
- EFI_ATA_MODE UdmaMode;\r
+ EFI_ATA_MODE UdmaMode;\r
///\r
/// The number of extended-mode bitmap entries. Extended modes describe transfer\r
/// protocols beyond PIO, single word DMA, multiword DMA, and UDMA. This field\r
/// can be zero and provides extensibility.\r
///\r
- UINT32 ExtModeCount;\r
+ UINT32 ExtModeCount;\r
///\r
/// ExtModeCount number of entries. Each entry represents a transfer protocol other\r
/// than the ones defined above (i.e., PIO, single word DMA, multiword DMA, and\r
/// transfer protocol is defined to cover SATA transfers. Type\r
/// EFI_ATA_EXTENDED_MODE is defined below.\r
///\r
- EFI_ATA_EXTENDED_MODE ExtMode[1];\r
+ EFI_ATA_EXTENDED_MODE ExtMode[1];\r
} EFI_ATA_COLLECTIVE_MODE;\r
\r
///\r
/// The data that is returned by an ATA device upon successful completion\r
/// of the ATA IDENTIFY_DEVICE command.\r
///\r
- EFI_ATA_IDENTIFY_DATA AtaData;\r
+ EFI_ATA_IDENTIFY_DATA AtaData;\r
///\r
/// The data that is returned by an ATAPI device upon successful completion\r
/// of the ATA IDENTIFY_PACKET_DEVICE command.\r
///\r
- EFI_ATAPI_IDENTIFY_DATA AtapiData;\r
+ EFI_ATAPI_IDENTIFY_DATA AtapiData;\r
} EFI_IDENTIFY_DATA;\r
\r
/**\r
/// each of which can have up to one device. In the presence of a multiplier,\r
/// each channel can have fifteen devices.\r
///\r
- UINT8 ChannelCount;\r
+ UINT8 ChannelCount;\r
};\r
\r
-extern EFI_GUID gEfiIdeControllerInitProtocolGuid;\r
+extern EFI_GUID gEfiIdeControllerInitProtocolGuid;\r
\r
#endif\r
/// resource configuration requirements if the specified device is a recognized\r
/// incompatible PCI device.\r
///\r
- EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;\r
+ EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_CHECK_DEVICE CheckDevice;\r
};\r
\r
-extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid;\r
+extern EFI_GUID gEfiIncompatiblePciDeviceSupportProtocolGuid;\r
\r
#endif\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE InstanceHandle;\r
- EFI_IPv4_ADDRESS Ip4Address;\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_HANDLE InstanceHandle;\r
+ EFI_IPv4_ADDRESS Ip4Address;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
} EFI_IP4_ADDRESS_PAIR;\r
\r
///\r
/// The default IPv4 protocol packets to send and receive. Ignored\r
/// when AcceptPromiscuous is TRUE.\r
///\r
- UINT8 DefaultProtocol;\r
+ UINT8 DefaultProtocol;\r
///\r
/// Set to TRUE to receive all IPv4 packets that get through the receive filters.\r
/// Set to FALSE to receive only the DefaultProtocol IPv4\r
/// packets that get through the receive filters.\r
///\r
- BOOLEAN AcceptAnyProtocol;\r
+ BOOLEAN AcceptAnyProtocol;\r
///\r
/// Set to TRUE to receive ICMP error report packets. Ignored when\r
/// AcceptPromiscuous or AcceptAnyProtocol is TRUE.\r
///\r
- BOOLEAN AcceptIcmpErrors;\r
+ BOOLEAN AcceptIcmpErrors;\r
///\r
/// Set to TRUE to receive broadcast IPv4 packets. Ignored when\r
/// AcceptPromiscuous is TRUE.\r
/// Set to FALSE to stop receiving broadcast IPv4 packets.\r
///\r
- BOOLEAN AcceptBroadcast;\r
+ BOOLEAN AcceptBroadcast;\r
///\r
/// Set to TRUE to receive all IPv4 packets that are sent to any\r
/// hardware address or any protocol address.\r
/// Set to FALSE to stop receiving all promiscuous IPv4 packets\r
///\r
- BOOLEAN AcceptPromiscuous;\r
+ BOOLEAN AcceptPromiscuous;\r
///\r
/// Set to TRUE to use the default IPv4 address and default routing table.\r
///\r
- BOOLEAN UseDefaultAddress;\r
+ BOOLEAN UseDefaultAddress;\r
///\r
/// The station IPv4 address that will be assigned to this EFI IPv4Protocol instance.\r
///\r
- EFI_IPv4_ADDRESS StationAddress;\r
+ EFI_IPv4_ADDRESS StationAddress;\r
///\r
/// The subnet address mask that is associated with the station address.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// TypeOfService field in transmitted IPv4 packets.\r
///\r
- UINT8 TypeOfService;\r
+ UINT8 TypeOfService;\r
///\r
/// TimeToLive field in transmitted IPv4 packets.\r
///\r
- UINT8 TimeToLive;\r
+ UINT8 TimeToLive;\r
///\r
/// State of the DoNotFragment bit in transmitted IPv4 packets.\r
///\r
- BOOLEAN DoNotFragment;\r
+ BOOLEAN DoNotFragment;\r
///\r
/// Set to TRUE to send and receive unformatted packets. The other\r
/// IPv4 receive filters are still applied. Fragmentation is disabled for RawData mode.\r
///\r
- BOOLEAN RawData;\r
+ BOOLEAN RawData;\r
///\r
/// The timer timeout value (number of microseconds) for the\r
/// receive timeout event to be associated with each assembled\r
/// packet. Zero means do not drop assembled packets.\r
///\r
- UINT32 ReceiveTimeout;\r
+ UINT32 ReceiveTimeout;\r
///\r
/// The timer timeout value (number of microseconds) for the\r
/// transmit timeout event to be associated with each outgoing\r
/// packet. Zero means do not drop outgoing packets.\r
///\r
- UINT32 TransmitTimeout;\r
+ UINT32 TransmitTimeout;\r
} EFI_IP4_CONFIG_DATA;\r
\r
-\r
typedef struct {\r
- EFI_IPv4_ADDRESS SubnetAddress;\r
- EFI_IPv4_ADDRESS SubnetMask;\r
- EFI_IPv4_ADDRESS GatewayAddress;\r
+ EFI_IPv4_ADDRESS SubnetAddress;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS GatewayAddress;\r
} EFI_IP4_ROUTE_TABLE;\r
\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Code;\r
+ UINT8 Type;\r
+ UINT8 Code;\r
} EFI_IP4_ICMP_TYPE;\r
\r
typedef struct {\r
///\r
/// Set to TRUE after this EFI IPv4 Protocol instance has been successfully configured.\r
///\r
- BOOLEAN IsStarted;\r
+ BOOLEAN IsStarted;\r
///\r
/// The maximum packet size, in bytes, of the packet which the upper layer driver could feed.\r
///\r
- UINT32 MaxPacketSize;\r
+ UINT32 MaxPacketSize;\r
///\r
/// Current configuration settings.\r
///\r
- EFI_IP4_CONFIG_DATA ConfigData;\r
+ EFI_IP4_CONFIG_DATA ConfigData;\r
///\r
/// Set to TRUE when the EFI IPv4 Protocol instance has a station address and subnet mask.\r
///\r
- BOOLEAN IsConfigured;\r
+ BOOLEAN IsConfigured;\r
///\r
/// Number of joined multicast groups.\r
///\r
- UINT32 GroupCount;\r
+ UINT32 GroupCount;\r
///\r
/// List of joined multicast group addresses.\r
///\r
- EFI_IPv4_ADDRESS *GroupTable;\r
+ EFI_IPv4_ADDRESS *GroupTable;\r
///\r
/// Number of entries in the routing table.\r
///\r
- UINT32 RouteCount;\r
+ UINT32 RouteCount;\r
///\r
/// Routing table entries.\r
///\r
- EFI_IP4_ROUTE_TABLE *RouteTable;\r
+ EFI_IP4_ROUTE_TABLE *RouteTable;\r
///\r
/// Number of entries in the supported ICMP types list.\r
///\r
- UINT32 IcmpTypeCount;\r
+ UINT32 IcmpTypeCount;\r
///\r
/// Array of ICMP types and codes that are supported by this EFI IPv4 Protocol driver\r
///\r
- EFI_IP4_ICMP_TYPE *IcmpTypeList;\r
+ EFI_IP4_ICMP_TYPE *IcmpTypeList;\r
} EFI_IP4_MODE_DATA;\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT8 HeaderLength:4;\r
- UINT8 Version:4;\r
- UINT8 TypeOfService;\r
- UINT16 TotalLength;\r
- UINT16 Identification;\r
- UINT16 Fragmentation;\r
- UINT8 TimeToLive;\r
- UINT8 Protocol;\r
- UINT16 Checksum;\r
- EFI_IPv4_ADDRESS SourceAddress;\r
- EFI_IPv4_ADDRESS DestinationAddress;\r
+ UINT8 HeaderLength : 4;\r
+ UINT8 Version : 4;\r
+ UINT8 TypeOfService;\r
+ UINT16 TotalLength;\r
+ UINT16 Identification;\r
+ UINT16 Fragmentation;\r
+ UINT8 TimeToLive;\r
+ UINT8 Protocol;\r
+ UINT16 Checksum;\r
+ EFI_IPv4_ADDRESS SourceAddress;\r
+ EFI_IPv4_ADDRESS DestinationAddress;\r
} EFI_IP4_HEADER;\r
#pragma pack()\r
\r
-\r
typedef struct {\r
- UINT32 FragmentLength;\r
- VOID *FragmentBuffer;\r
+ UINT32 FragmentLength;\r
+ VOID *FragmentBuffer;\r
} EFI_IP4_FRAGMENT_DATA;\r
\r
-\r
typedef struct {\r
- EFI_TIME TimeStamp;\r
- EFI_EVENT RecycleSignal;\r
- UINT32 HeaderLength;\r
- EFI_IP4_HEADER *Header;\r
- UINT32 OptionsLength;\r
- VOID *Options;\r
- UINT32 DataLength;\r
- UINT32 FragmentCount;\r
- EFI_IP4_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_TIME TimeStamp;\r
+ EFI_EVENT RecycleSignal;\r
+ UINT32 HeaderLength;\r
+ EFI_IP4_HEADER *Header;\r
+ UINT32 OptionsLength;\r
+ VOID *Options;\r
+ UINT32 DataLength;\r
+ UINT32 FragmentCount;\r
+ EFI_IP4_FRAGMENT_DATA FragmentTable[1];\r
} EFI_IP4_RECEIVE_DATA;\r
\r
-\r
typedef struct {\r
- EFI_IPv4_ADDRESS SourceAddress;\r
- EFI_IPv4_ADDRESS GatewayAddress;\r
- UINT8 Protocol;\r
- UINT8 TypeOfService;\r
- UINT8 TimeToLive;\r
- BOOLEAN DoNotFragment;\r
+ EFI_IPv4_ADDRESS SourceAddress;\r
+ EFI_IPv4_ADDRESS GatewayAddress;\r
+ UINT8 Protocol;\r
+ UINT8 TypeOfService;\r
+ UINT8 TimeToLive;\r
+ BOOLEAN DoNotFragment;\r
} EFI_IP4_OVERRIDE_DATA;\r
\r
typedef struct {\r
- EFI_IPv4_ADDRESS DestinationAddress;\r
- EFI_IP4_OVERRIDE_DATA *OverrideData; //OPTIONAL\r
- UINT32 OptionsLength; //OPTIONAL\r
- VOID *OptionsBuffer; //OPTIONAL\r
- UINT32 TotalDataLength;\r
- UINT32 FragmentCount;\r
- EFI_IP4_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_IPv4_ADDRESS DestinationAddress;\r
+ EFI_IP4_OVERRIDE_DATA *OverrideData; // OPTIONAL\r
+ UINT32 OptionsLength; // OPTIONAL\r
+ VOID *OptionsBuffer; // OPTIONAL\r
+ UINT32 TotalDataLength;\r
+ UINT32 FragmentCount;\r
+ EFI_IP4_FRAGMENT_DATA FragmentTable[1];\r
} EFI_IP4_TRANSMIT_DATA;\r
\r
typedef struct {\r
/// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of\r
/// Event must be lower than or equal to TPL_CALLBACK.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// The status that is returned to the caller at the end of the operation\r
/// to indicate whether this operation completed successfully.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
union {\r
///\r
/// When this token is used for receiving, RxData is a pointer to the EFI_IP4_RECEIVE_DATA.\r
///\r
- EFI_IP4_RECEIVE_DATA *RxData;\r
+ EFI_IP4_RECEIVE_DATA *RxData;\r
///\r
/// When this token is used for transmitting, TxData is a pointer to the EFI_IP4_TRANSMIT_DATA.\r
///\r
- EFI_IP4_TRANSMIT_DATA *TxData;\r
+ EFI_IP4_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_IP4_COMPLETION_TOKEN;\r
\r
/// used by drivers, daemons, and applications to transmit and receive network packets.\r
///\r
struct _EFI_IP4_PROTOCOL {\r
- EFI_IP4_GET_MODE_DATA GetModeData;\r
- EFI_IP4_CONFIGURE Configure;\r
- EFI_IP4_GROUPS Groups;\r
- EFI_IP4_ROUTES Routes;\r
- EFI_IP4_TRANSMIT Transmit;\r
- EFI_IP4_RECEIVE Receive;\r
- EFI_IP4_CANCEL Cancel;\r
- EFI_IP4_POLL Poll;\r
+ EFI_IP4_GET_MODE_DATA GetModeData;\r
+ EFI_IP4_CONFIGURE Configure;\r
+ EFI_IP4_GROUPS Groups;\r
+ EFI_IP4_ROUTES Routes;\r
+ EFI_IP4_TRANSMIT Transmit;\r
+ EFI_IP4_RECEIVE Receive;\r
+ EFI_IP4_CANCEL Cancel;\r
+ EFI_IP4_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiIp4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiIp4ProtocolGuid;\r
+extern EFI_GUID gEfiIp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiIp4ProtocolGuid;\r
\r
#endif\r
This Protocol is introduced in UEFI Specification 2.0.\r
\r
**/\r
+\r
#ifndef __EFI_IP4CONFIG_PROTOCOL_H__\r
#define __EFI_IP4CONFIG_PROTOCOL_H__\r
\r
///\r
/// Default station IP address, stored in network byte order.\r
///\r
- EFI_IPv4_ADDRESS StationAddress;\r
+ EFI_IPv4_ADDRESS StationAddress;\r
///\r
/// Default subnet mask, stored in network byte order.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// Number of entries in the following RouteTable. May be zero.\r
///\r
- UINT32 RouteTableSize;\r
+ UINT32 RouteTableSize;\r
///\r
/// Default routing table data (stored in network byte order).\r
/// Ignored if RouteTableSize is zero.\r
///\r
- EFI_IP4_ROUTE_TABLE *RouteTable;\r
+ EFI_IP4_ROUTE_TABLE *RouteTable;\r
} EFI_IP4_IPCONFIG_DATA;\r
\r
-\r
/**\r
Starts running the configuration policy for the EFI IPv4 Protocol driver.\r
\r
/// configurations for the EFI IPv4 Protocol driver.\r
///\r
struct _EFI_IP4_CONFIG_PROTOCOL {\r
- EFI_IP4_CONFIG_START Start;\r
- EFI_IP4_CONFIG_STOP Stop;\r
- EFI_IP4_CONFIG_GET_DATA GetData;\r
+ EFI_IP4_CONFIG_START Start;\r
+ EFI_IP4_CONFIG_STOP Stop;\r
+ EFI_IP4_CONFIG_GET_DATA GetData;\r
};\r
\r
-extern EFI_GUID gEfiIp4ConfigProtocolGuid;\r
+extern EFI_GUID gEfiIp4ConfigProtocolGuid;\r
\r
#endif\r
This Protocol is introduced in UEFI Specification 2.5\r
\r
**/\r
+\r
#ifndef __EFI_IP4CONFIG2_PROTOCOL_H__\r
#define __EFI_IP4CONFIG2_PROTOCOL_H__\r
\r
\r
typedef struct _EFI_IP4_CONFIG2_PROTOCOL EFI_IP4_CONFIG2_PROTOCOL;\r
\r
-\r
///\r
/// EFI_IP4_CONFIG2_DATA_TYPE\r
///\r
///\r
/// EFI_IP4_CONFIG2_INTERFACE_INFO related definitions\r
///\r
-#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32\r
+#define EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE 32\r
\r
///\r
/// EFI_IP4_CONFIG2_INTERFACE_INFO\r
///\r
/// The name of the interface. It is a NULL-terminated Unicode string.\r
///\r
- CHAR16 Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];\r
+ CHAR16 Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];\r
///\r
/// The interface type of the network interface. See RFC 1700,\r
/// section "Number Hardware Type".\r
///\r
- UINT8 IfType;\r
+ UINT8 IfType;\r
///\r
/// The size, in bytes, of the network interface's hardware address.\r
///\r
- UINT32 HwAddressSize;\r
+ UINT32 HwAddressSize;\r
///\r
/// The hardware address for the network interface.\r
///\r
- EFI_MAC_ADDRESS HwAddress;\r
+ EFI_MAC_ADDRESS HwAddress;\r
///\r
/// The station IPv4 address of this EFI IPv4 network stack.\r
///\r
- EFI_IPv4_ADDRESS StationAddress;\r
+ EFI_IPv4_ADDRESS StationAddress;\r
///\r
/// The subnet address mask that is associated with the station address.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
///\r
/// Size of the following RouteTable, in bytes. May be zero.\r
///\r
- UINT32 RouteTableSize;\r
+ UINT32 RouteTableSize;\r
///\r
/// The route table of the IPv4 network stack runs on this interface.\r
/// Set to NULL if RouteTableSize is zero. Type EFI_IP4_ROUTE_TABLE is defined in\r
///\r
/// The IPv4 unicast address.\r
///\r
- EFI_IPv4_ADDRESS Address;\r
+ EFI_IPv4_ADDRESS Address;\r
///\r
/// The subnet mask.\r
///\r
- EFI_IPv4_ADDRESS SubnetMask;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
} EFI_IP4_CONFIG2_MANUAL_ADDRESS;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IP4_CONFIG2_SET_DATA) (\r
+(EFIAPI *EFI_IP4_CONFIG2_SET_DATA)(\r
IN EFI_IP4_CONFIG2_PROTOCOL *This,\r
IN EFI_IP4_CONFIG2_DATA_TYPE DataType,\r
IN UINTN DataSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IP4_CONFIG2_GET_DATA) (\r
+(EFIAPI *EFI_IP4_CONFIG2_GET_DATA)(\r
IN EFI_IP4_CONFIG2_PROTOCOL *This,\r
IN EFI_IP4_CONFIG2_DATA_TYPE DataType,\r
IN OUT UINTN *DataSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IP4_CONFIG2_REGISTER_NOTIFY) (\r
+(EFIAPI *EFI_IP4_CONFIG2_REGISTER_NOTIFY)(\r
IN EFI_IP4_CONFIG2_PROTOCOL *This,\r
IN EFI_IP4_CONFIG2_DATA_TYPE DataType,\r
IN EFI_EVENT Event\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IP4_CONFIG2_UNREGISTER_NOTIFY) (\r
+(EFIAPI *EFI_IP4_CONFIG2_UNREGISTER_NOTIFY)(\r
IN EFI_IP4_CONFIG2_PROTOCOL *This,\r
IN EFI_IP4_CONFIG2_DATA_TYPE DataType,\r
IN EFI_EVENT Event\r
/// the EFI IPv4 network stack runs on.\r
///\r
struct _EFI_IP4_CONFIG2_PROTOCOL {\r
- EFI_IP4_CONFIG2_SET_DATA SetData;\r
- EFI_IP4_CONFIG2_GET_DATA GetData;\r
- EFI_IP4_CONFIG2_REGISTER_NOTIFY RegisterDataNotify;\r
- EFI_IP4_CONFIG2_UNREGISTER_NOTIFY UnregisterDataNotify;\r
+ EFI_IP4_CONFIG2_SET_DATA SetData;\r
+ EFI_IP4_CONFIG2_GET_DATA GetData;\r
+ EFI_IP4_CONFIG2_REGISTER_NOTIFY RegisterDataNotify;\r
+ EFI_IP4_CONFIG2_UNREGISTER_NOTIFY UnregisterDataNotify;\r
};\r
\r
-extern EFI_GUID gEfiIp4Config2ProtocolGuid;\r
+extern EFI_GUID gEfiIp4Config2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/ManagedNetwork.h>\r
\r
-\r
#define EFI_IP6_SERVICE_BINDING_PROTOCOL_GUID \\r
{ \\r
0xec835dd3, 0xfe0f, 0x617b, {0xa6, 0x21, 0xb3, 0x50, 0xc3, 0xe1, 0x33, 0x88 } \\r
/// EFI_IP6_ADDRESS_PAIR is deprecated in the UEFI 2.4B and should not be used any more.\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
-typedef struct{\r
+typedef struct {\r
///\r
/// The EFI IPv6 Protocol instance handle that is using this address/prefix pair.\r
///\r
/// ICMPv6 type definitions for error messages\r
///\r
///@{\r
-#define ICMP_V6_DEST_UNREACHABLE 0x1\r
-#define ICMP_V6_PACKET_TOO_BIG 0x2\r
-#define ICMP_V6_TIME_EXCEEDED 0x3\r
-#define ICMP_V6_PARAMETER_PROBLEM 0x4\r
+#define ICMP_V6_DEST_UNREACHABLE 0x1\r
+#define ICMP_V6_PACKET_TOO_BIG 0x2\r
+#define ICMP_V6_TIME_EXCEEDED 0x3\r
+#define ICMP_V6_PARAMETER_PROBLEM 0x4\r
///@}\r
\r
///\r
/// ICMPv6 type definition for informational messages\r
///\r
///@{\r
-#define ICMP_V6_ECHO_REQUEST 0x80\r
-#define ICMP_V6_ECHO_REPLY 0x81\r
-#define ICMP_V6_LISTENER_QUERY 0x82\r
-#define ICMP_V6_LISTENER_REPORT 0x83\r
-#define ICMP_V6_LISTENER_DONE 0x84\r
-#define ICMP_V6_ROUTER_SOLICIT 0x85\r
-#define ICMP_V6_ROUTER_ADVERTISE 0x86\r
-#define ICMP_V6_NEIGHBOR_SOLICIT 0x87\r
-#define ICMP_V6_NEIGHBOR_ADVERTISE 0x88\r
-#define ICMP_V6_REDIRECT 0x89\r
-#define ICMP_V6_LISTENER_REPORT_2 0x8F\r
+#define ICMP_V6_ECHO_REQUEST 0x80\r
+#define ICMP_V6_ECHO_REPLY 0x81\r
+#define ICMP_V6_LISTENER_QUERY 0x82\r
+#define ICMP_V6_LISTENER_REPORT 0x83\r
+#define ICMP_V6_LISTENER_DONE 0x84\r
+#define ICMP_V6_ROUTER_SOLICIT 0x85\r
+#define ICMP_V6_ROUTER_ADVERTISE 0x86\r
+#define ICMP_V6_NEIGHBOR_SOLICIT 0x87\r
+#define ICMP_V6_NEIGHBOR_ADVERTISE 0x88\r
+#define ICMP_V6_REDIRECT 0x89\r
+#define ICMP_V6_LISTENER_REPORT_2 0x8F\r
///@}\r
\r
///\r
/// ICMPv6 code definitions for ICMP_V6_DEST_UNREACHABLE\r
///\r
///@{\r
-#define ICMP_V6_NO_ROUTE_TO_DEST 0x0\r
-#define ICMP_V6_COMM_PROHIBITED 0x1\r
-#define ICMP_V6_BEYOND_SCOPE 0x2\r
-#define ICMP_V6_ADDR_UNREACHABLE 0x3\r
-#define ICMP_V6_PORT_UNREACHABLE 0x4\r
-#define ICMP_V6_SOURCE_ADDR_FAILED 0x5\r
-#define ICMP_V6_ROUTE_REJECTED 0x6\r
+#define ICMP_V6_NO_ROUTE_TO_DEST 0x0\r
+#define ICMP_V6_COMM_PROHIBITED 0x1\r
+#define ICMP_V6_BEYOND_SCOPE 0x2\r
+#define ICMP_V6_ADDR_UNREACHABLE 0x3\r
+#define ICMP_V6_PORT_UNREACHABLE 0x4\r
+#define ICMP_V6_SOURCE_ADDR_FAILED 0x5\r
+#define ICMP_V6_ROUTE_REJECTED 0x6\r
///@}\r
\r
///\r
/// ICMPv6 code definitions for ICMP_V6_TIME_EXCEEDED\r
///\r
///@{\r
-#define ICMP_V6_TIMEOUT_HOP_LIMIT 0x0\r
-#define ICMP_V6_TIMEOUT_REASSEMBLE 0x1\r
+#define ICMP_V6_TIMEOUT_HOP_LIMIT 0x0\r
+#define ICMP_V6_TIMEOUT_REASSEMBLE 0x1\r
///@}\r
\r
///\r
/// ICMPv6 code definitions for ICMP_V6_PARAMETER_PROBLEM\r
///\r
///@{\r
-#define ICMP_V6_ERRONEOUS_HEADER 0x0\r
-#define ICMP_V6_UNRECOGNIZE_NEXT_HDR 0x1\r
-#define ICMP_V6_UNRECOGNIZE_OPTION 0x2\r
+#define ICMP_V6_ERRONEOUS_HEADER 0x0\r
+#define ICMP_V6_UNRECOGNIZE_NEXT_HDR 0x1\r
+#define ICMP_V6_UNRECOGNIZE_OPTION 0x2\r
///@}\r
\r
///\r
/// the IPv6 header if there are no extension headers. Ignored when\r
/// AcceptPromiscuous is TRUE.\r
///\r
- UINT8 DefaultProtocol;\r
+ UINT8 DefaultProtocol;\r
///\r
/// Set to TRUE to receive all IPv6 packets that get through the\r
/// receive filters.\r
/// packets that get through the receive filters. Ignored when\r
/// AcceptPromiscuous is TRUE.\r
///\r
- BOOLEAN AcceptAnyProtocol;\r
+ BOOLEAN AcceptAnyProtocol;\r
///\r
/// Set to TRUE to receive ICMP error report packets. Ignored when\r
/// AcceptPromiscuous or AcceptAnyProtocol is TRUE.\r
///\r
- BOOLEAN AcceptIcmpErrors;\r
+ BOOLEAN AcceptIcmpErrors;\r
///\r
/// Set to TRUE to receive all IPv6 packets that are sent to any\r
/// hardware address or any protocol address. Set to FALSE to stop\r
/// receiving all promiscuous IPv6 packets.\r
///\r
- BOOLEAN AcceptPromiscuous;\r
+ BOOLEAN AcceptPromiscuous;\r
///\r
/// The destination address of the packets that will be transmitted.\r
/// Ignored if it is unspecified.\r
///\r
- EFI_IPv6_ADDRESS DestinationAddress;\r
+ EFI_IPv6_ADDRESS DestinationAddress;\r
///\r
/// The station IPv6 address that will be assigned to this EFI IPv6\r
/// Protocol instance. This field can be set and changed only when\r
/// only be successfully bound to this EFI IPv6 protocol instance\r
/// after IP6ModeData.IsConfigured changed to TRUE.\r
///\r
- EFI_IPv6_ADDRESS StationAddress;\r
+ EFI_IPv6_ADDRESS StationAddress;\r
///\r
/// TrafficClass field in transmitted IPv6 packets. Default value\r
/// is zero.\r
///\r
- UINT8 TrafficClass;\r
+ UINT8 TrafficClass;\r
///\r
/// HopLimit field in transmitted IPv6 packets.\r
///\r
- UINT8 HopLimit;\r
+ UINT8 HopLimit;\r
///\r
/// FlowLabel field in transmitted IPv6 packets. Default value is\r
/// zero.\r
///\r
- UINT32 FlowLabel;\r
+ UINT32 FlowLabel;\r
///\r
/// The timer timeout value (number of microseconds) for the\r
/// receive timeout event to be associated with each assembled\r
/// packet. Zero means do not drop assembled packets.\r
///\r
- UINT32 ReceiveTimeout;\r
+ UINT32 ReceiveTimeout;\r
///\r
/// The timer timeout value (number of microseconds) for the\r
/// transmit timeout event to be associated with each outgoing\r
/// packet. Zero means do not drop outgoing packets.\r
///\r
- UINT32 TransmitTimeout;\r
+ UINT32 TransmitTimeout;\r
} EFI_IP6_CONFIG_DATA;\r
\r
///\r
/// EFI_IP6_ADDRESS_INFO\r
///\r
typedef struct {\r
- EFI_IPv6_ADDRESS Address; ///< The IPv6 address.\r
- UINT8 PrefixLength; ///< The length of the prefix associated with the Address.\r
+ EFI_IPv6_ADDRESS Address; ///< The IPv6 address.\r
+ UINT8 PrefixLength; ///< The length of the prefix associated with the Address.\r
} EFI_IP6_ADDRESS_INFO;\r
\r
///\r
/// packets to this prefix. If the IPv6 address is all zeros, then the\r
/// prefix is on-link.\r
///\r
- EFI_IPv6_ADDRESS Gateway;\r
+ EFI_IPv6_ADDRESS Gateway;\r
///\r
/// The destination prefix to be routed.\r
///\r
- EFI_IPv6_ADDRESS Destination;\r
+ EFI_IPv6_ADDRESS Destination;\r
///\r
/// The length of the prefix associated with the Destination.\r
///\r
- UINT8 PrefixLength;\r
+ UINT8 PrefixLength;\r
} EFI_IP6_ROUTE_TABLE;\r
\r
///\r
///\r
EfiNeighborReachable,\r
///\r
- ///Reachable Time has elapsed since the last positive confirmation\r
- ///was received. In this state, the forward path to the neighbor was\r
- ///functioning properly.\r
+ /// Reachable Time has elapsed since the last positive confirmation\r
+ /// was received. In this state, the forward path to the neighbor was\r
+ /// functioning properly.\r
///\r
EfiNeighborStale,\r
///\r
/// of entries about individual neighbors to which traffic has been sent recently.\r
///\r
typedef struct {\r
- EFI_IPv6_ADDRESS Neighbor; ///< The on-link unicast/anycast IP address of the neighbor.\r
- EFI_MAC_ADDRESS LinkAddress; ///< Link-layer address of the neighbor.\r
- EFI_IP6_NEIGHBOR_STATE State; ///< State of this neighbor cache entry.\r
+ EFI_IPv6_ADDRESS Neighbor; ///< The on-link unicast/anycast IP address of the neighbor.\r
+ EFI_MAC_ADDRESS LinkAddress; ///< Link-layer address of the neighbor.\r
+ EFI_IP6_NEIGHBOR_STATE State; ///< State of this neighbor cache entry.\r
} EFI_IP6_NEIGHBOR_CACHE;\r
\r
///\r
/// IPv6 Protocol driver.\r
///\r
typedef struct {\r
- UINT8 Type; ///< The type of ICMP message.\r
- UINT8 Code; ///< The code of the ICMP message.\r
+ UINT8 Type; ///< The type of ICMP message.\r
+ UINT8 Code; ///< The code of the ICMP message.\r
} EFI_IP6_ICMP_TYPE;\r
\r
///\r
/// All other fields in this structure are undefined until this field is TRUE.\r
/// Set to FALSE when the EFI IPv6 Protocol instance is stopped.\r
///\r
- BOOLEAN IsStarted;\r
+ BOOLEAN IsStarted;\r
///\r
/// The maximum packet size, in bytes, of the packet which the upper layer driver could feed.\r
///\r
- UINT32 MaxPacketSize;\r
+ UINT32 MaxPacketSize;\r
///\r
/// Current configuration settings. Undefined until IsStarted is TRUE.\r
///\r
- EFI_IP6_CONFIG_DATA ConfigData;\r
+ EFI_IP6_CONFIG_DATA ConfigData;\r
///\r
/// Set to TRUE when the EFI IPv6 Protocol instance is configured.\r
/// The instance is configured when it has a station address and\r
/// corresponding prefix length.\r
/// Set to FALSE when the EFI IPv6 Protocol instance is not configured.\r
///\r
- BOOLEAN IsConfigured;\r
+ BOOLEAN IsConfigured;\r
///\r
/// Number of configured IPv6 addresses on this interface.\r
///\r
- UINT32 AddressCount;\r
+ UINT32 AddressCount;\r
///\r
/// List of currently configured IPv6 addresses and corresponding\r
/// prefix lengths assigned to this interface. It is caller's\r
/// responsibility to free this buffer.\r
///\r
- EFI_IP6_ADDRESS_INFO *AddressList;\r
+ EFI_IP6_ADDRESS_INFO *AddressList;\r
///\r
/// Number of joined multicast groups. Undefined until\r
/// IsConfigured is TRUE.\r
///\r
- UINT32 GroupCount;\r
+ UINT32 GroupCount;\r
///\r
/// List of joined multicast group addresses. It is caller's\r
/// responsibility to free this buffer. Undefined until\r
/// IsConfigured is TRUE.\r
///\r
- EFI_IPv6_ADDRESS *GroupTable;\r
+ EFI_IPv6_ADDRESS *GroupTable;\r
///\r
/// Number of entries in the routing table. Undefined until\r
/// IsConfigured is TRUE.\r
///\r
- UINT32 RouteCount;\r
+ UINT32 RouteCount;\r
///\r
/// Routing table entries. It is caller's responsibility to free this buffer.\r
///\r
- EFI_IP6_ROUTE_TABLE *RouteTable;\r
+ EFI_IP6_ROUTE_TABLE *RouteTable;\r
///\r
/// Number of entries in the neighbor cache. Undefined until\r
/// IsConfigured is TRUE.\r
///\r
- UINT32 NeighborCount;\r
+ UINT32 NeighborCount;\r
///\r
/// Neighbor cache entries. It is caller's responsibility to free this\r
/// buffer. Undefined until IsConfigured is TRUE.\r
///\r
- EFI_IP6_NEIGHBOR_CACHE *NeighborCache;\r
+ EFI_IP6_NEIGHBOR_CACHE *NeighborCache;\r
///\r
/// Number of entries in the prefix table. Undefined until\r
/// IsConfigured is TRUE.\r
///\r
- UINT32 PrefixCount;\r
+ UINT32 PrefixCount;\r
///\r
/// On-link Prefix table entries. It is caller's responsibility to free this\r
/// buffer. Undefined until IsConfigured is TRUE.\r
///\r
- EFI_IP6_ADDRESS_INFO *PrefixTable;\r
+ EFI_IP6_ADDRESS_INFO *PrefixTable;\r
///\r
/// Number of entries in the supported ICMP types list.\r
///\r
- UINT32 IcmpTypeCount;\r
+ UINT32 IcmpTypeCount;\r
///\r
/// Array of ICMP types and codes that are supported by this EFI\r
/// IPv6 Protocol driver. It is caller's responsibility to free this\r
/// buffer.\r
///\r
- EFI_IP6_ICMP_TYPE *IcmpTypeList;\r
+ EFI_IP6_ICMP_TYPE *IcmpTypeList;\r
} EFI_IP6_MODE_DATA;\r
\r
///\r
///\r
#pragma pack(1)\r
typedef struct _EFI_IP6_HEADER {\r
- UINT8 TrafficClassH:4;\r
- UINT8 Version:4;\r
- UINT8 FlowLabelH:4;\r
- UINT8 TrafficClassL:4;\r
- UINT16 FlowLabelL;\r
- UINT16 PayloadLength;\r
- UINT8 NextHeader;\r
- UINT8 HopLimit;\r
- EFI_IPv6_ADDRESS SourceAddress;\r
- EFI_IPv6_ADDRESS DestinationAddress;\r
+ UINT8 TrafficClassH : 4;\r
+ UINT8 Version : 4;\r
+ UINT8 FlowLabelH : 4;\r
+ UINT8 TrafficClassL : 4;\r
+ UINT16 FlowLabelL;\r
+ UINT16 PayloadLength;\r
+ UINT8 NextHeader;\r
+ UINT8 HopLimit;\r
+ EFI_IPv6_ADDRESS SourceAddress;\r
+ EFI_IPv6_ADDRESS DestinationAddress;\r
} EFI_IP6_HEADER;\r
#pragma pack()\r
\r
/// fragment to transmit or that has been received.\r
///\r
typedef struct _EFI_IP6_FRAGMENT_DATA {\r
- UINT32 FragmentLength; ///< Length of fragment data. This field may not be set to zero.\r
- VOID *FragmentBuffer; ///< Pointer to fragment data. This field may not be set to NULL.\r
+ UINT32 FragmentLength; ///< Length of fragment data. This field may not be set to zero.\r
+ VOID *FragmentBuffer; ///< Pointer to fragment data. This field may not be set to NULL.\r
} EFI_IP6_FRAGMENT_DATA;\r
\r
///\r
/// Time when the EFI IPv6 Protocol driver accepted the packet.\r
/// Ignored if it is zero.\r
///\r
- EFI_TIME TimeStamp;\r
+ EFI_TIME TimeStamp;\r
///\r
/// After this event is signaled, the receive data structure is released\r
/// and must not be referenced.\r
///\r
- EFI_EVENT RecycleSignal;\r
+ EFI_EVENT RecycleSignal;\r
///\r
- ///Length of the IPv6 packet headers, including both the IPv6\r
- ///header and any extension headers.\r
+ /// Length of the IPv6 packet headers, including both the IPv6\r
+ /// header and any extension headers.\r
///\r
- UINT32 HeaderLength;\r
+ UINT32 HeaderLength;\r
///\r
/// Pointer to the IPv6 packet header. If the IPv6 packet was\r
/// fragmented, this argument is a pointer to the header in the first\r
/// fragment.\r
///\r
- EFI_IP6_HEADER *Header;\r
+ EFI_IP6_HEADER *Header;\r
///\r
/// Sum of the lengths of IPv6 packet buffers in FragmentTable. May\r
/// be zero.\r
///\r
- UINT32 DataLength;\r
+ UINT32 DataLength;\r
///\r
/// Number of IPv6 payload fragments. May be zero.\r
///\r
- UINT32 FragmentCount;\r
+ UINT32 FragmentCount;\r
///\r
/// Array of payload fragment lengths and buffer pointers.\r
///\r
- EFI_IP6_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_IP6_FRAGMENT_DATA FragmentTable[1];\r
} EFI_IP6_RECEIVE_DATA;\r
\r
///\r
/// default parameters or settings for one Transmit() function call.\r
///\r
typedef struct _EFI_IP6_OVERRIDE_DATA {\r
- UINT8 Protocol; ///< Protocol type override.\r
- UINT8 HopLimit; ///< Hop-Limit override.\r
- UINT32 FlowLabel; ///< Flow-Label override.\r
+ UINT8 Protocol; ///< Protocol type override.\r
+ UINT8 HopLimit; ///< Hop-Limit override.\r
+ UINT32 FlowLabel; ///< Flow-Label override.\r
} EFI_IP6_OVERRIDE_DATA;\r
\r
///\r
/// The destination IPv6 address. If it is unspecified,\r
/// ConfigData.DestinationAddress will be used instead.\r
///\r
- EFI_IPv6_ADDRESS DestinationAddress;\r
+ EFI_IPv6_ADDRESS DestinationAddress;\r
///\r
/// If not NULL, the IPv6 transmission control override data.\r
///\r
- EFI_IP6_OVERRIDE_DATA *OverrideData;\r
+ EFI_IP6_OVERRIDE_DATA *OverrideData;\r
///\r
/// Total length in byte of the IPv6 extension headers specified in\r
/// ExtHdrs.\r
///\r
- UINT32 ExtHdrsLength;\r
+ UINT32 ExtHdrsLength;\r
///\r
/// Pointer to the IPv6 extension headers. The IP layer will append\r
/// the required extension headers if they are not specified by\r
/// ExtHdrs. Ignored if ExtHdrsLength is zero.\r
///\r
- VOID *ExtHdrs;\r
+ VOID *ExtHdrs;\r
///\r
/// The protocol of first extension header in ExtHdrs. Ignored if\r
/// ExtHdrsLength is zero.\r
///\r
- UINT8 NextHeader;\r
+ UINT8 NextHeader;\r
///\r
/// Total length in bytes of the FragmentTable data to transmit.\r
///\r
- UINT32 DataLength;\r
+ UINT32 DataLength;\r
///\r
/// Number of entries in the fragment data table.\r
///\r
- UINT32 FragmentCount;\r
+ UINT32 FragmentCount;\r
///\r
/// Start of the fragment data table.\r
///\r
- EFI_IP6_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_IP6_FRAGMENT_DATA FragmentTable[1];\r
} EFI_IP6_TRANSMIT_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by\r
/// the EFI IPv6 Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// - EFI_SUCCESS: The receive or transmit completed\r
/// failed because of an IPsec policy check.\r
/// - EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
union {\r
///\r
/// When the Token is used for receiving, RxData is a pointer to the EFI_IP6_RECEIVE_DATA.\r
///\r
- EFI_IP6_RECEIVE_DATA *RxData;\r
+ EFI_IP6_RECEIVE_DATA *RxData;\r
///\r
/// When the Token is used for transmitting, TxData is a pointer to the EFI_IP6_TRANSMIT_DATA.\r
///\r
- EFI_IP6_TRANSMIT_DATA *TxData;\r
+ EFI_IP6_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_IP6_COMPLETION_TOKEN;\r
\r
/// used by drivers, daemons, and applications to transmit and receive network packets.\r
///\r
struct _EFI_IP6_PROTOCOL {\r
- EFI_IP6_GET_MODE_DATA GetModeData;\r
- EFI_IP6_CONFIGURE Configure;\r
- EFI_IP6_GROUPS Groups;\r
- EFI_IP6_ROUTES Routes;\r
- EFI_IP6_NEIGHBORS Neighbors;\r
- EFI_IP6_TRANSMIT Transmit;\r
- EFI_IP6_RECEIVE Receive;\r
- EFI_IP6_CANCEL Cancel;\r
- EFI_IP6_POLL Poll;\r
+ EFI_IP6_GET_MODE_DATA GetModeData;\r
+ EFI_IP6_CONFIGURE Configure;\r
+ EFI_IP6_GROUPS Groups;\r
+ EFI_IP6_ROUTES Routes;\r
+ EFI_IP6_NEIGHBORS Neighbors;\r
+ EFI_IP6_TRANSMIT Transmit;\r
+ EFI_IP6_RECEIVE Receive;\r
+ EFI_IP6_CANCEL Cancel;\r
+ EFI_IP6_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiIp6ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiIp6ProtocolGuid;\r
+extern EFI_GUID gEfiIp6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiIp6ProtocolGuid;\r
\r
#endif\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
+\r
#ifndef __EFI_IP6CONFIG_PROTOCOL_H__\r
#define __EFI_IP6CONFIG_PROTOCOL_H__\r
\r
///\r
/// The name of the interface. It is a NULL-terminated string.\r
///\r
- CHAR16 Name[32];\r
+ CHAR16 Name[32];\r
///\r
/// The interface type of the network interface.\r
///\r
- UINT8 IfType;\r
+ UINT8 IfType;\r
///\r
/// The size, in bytes, of the network interface's hardware address.\r
///\r
- UINT32 HwAddressSize;\r
+ UINT32 HwAddressSize;\r
///\r
/// The hardware address for the network interface.\r
///\r
- EFI_MAC_ADDRESS HwAddress;\r
+ EFI_MAC_ADDRESS HwAddress;\r
///\r
/// Number of EFI_IP6_ADDRESS_INFO structures pointed to by AddressInfo.\r
///\r
- UINT32 AddressInfoCount;\r
+ UINT32 AddressInfoCount;\r
///\r
/// Pointer to an array of EFI_IP6_ADDRESS_INFO instances\r
/// which contain the local IPv6 addresses and the corresponding\r
/// prefix length information. Set to NULL if AddressInfoCount\r
/// is zero.\r
///\r
- EFI_IP6_ADDRESS_INFO *AddressInfo;\r
+ EFI_IP6_ADDRESS_INFO *AddressInfo;\r
///\r
/// Number of route table entries in the following RouteTable.\r
///\r
- UINT32 RouteCount;\r
+ UINT32 RouteCount;\r
///\r
/// The route table of the IPv6 network stack runs on this interface.\r
/// Set to NULL if RouteCount is zero.\r
///\r
- EFI_IP6_ROUTE_TABLE *RouteTable;\r
+ EFI_IP6_ROUTE_TABLE *RouteTable;\r
} EFI_IP6_CONFIG_INTERFACE_INFO;\r
\r
///\r
/// describes the 64-bit interface ID.\r
///\r
typedef struct {\r
- UINT8 Id[8];\r
+ UINT8 Id[8];\r
} EFI_IP6_CONFIG_INTERFACE_ID;\r
\r
///\r
/// stack manually when the policy is Ip6ConfigPolicyManual.\r
///\r
typedef struct {\r
- EFI_IPv6_ADDRESS Address; ///< The IPv6 unicast address.\r
- BOOLEAN IsAnycast; ///< Set to TRUE if Address is anycast.\r
- UINT8 PrefixLength; ///< The length, in bits, of the prefix associated with this Address.\r
+ EFI_IPv6_ADDRESS Address; ///< The IPv6 unicast address.\r
+ BOOLEAN IsAnycast; ///< Set to TRUE if Address is anycast.\r
+ UINT8 PrefixLength; ///< The length, in bits, of the prefix associated with this Address.\r
} EFI_IP6_CONFIG_MANUAL_ADDRESS;\r
\r
-\r
/**\r
Set the configuration for the EFI IPv6 network stack running on the communication\r
device this EFI IPv6 Configuration Protocol instance manages.\r
/// types of configurations for the EFI IPv6 network stack.\r
///\r
struct _EFI_IP6_CONFIG_PROTOCOL {\r
- EFI_IP6_CONFIG_SET_DATA SetData;\r
- EFI_IP6_CONFIG_GET_DATA GetData;\r
- EFI_IP6_CONFIG_REGISTER_NOTIFY RegisterDataNotify;\r
- EFI_IP6_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;\r
+ EFI_IP6_CONFIG_SET_DATA SetData;\r
+ EFI_IP6_CONFIG_GET_DATA GetData;\r
+ EFI_IP6_CONFIG_REGISTER_NOTIFY RegisterDataNotify;\r
+ EFI_IP6_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;\r
};\r
\r
-extern EFI_GUID gEfiIp6ConfigProtocolGuid;\r
+extern EFI_GUID gEfiIp6ConfigProtocolGuid;\r
\r
#endif\r
-\r
0xa3979e64, 0xace8, 0x4ddc, {0xbc, 0x7, 0x4d, 0x66, 0xb8, 0xfd, 0x9, 0x77 } \\r
}\r
\r
-typedef struct _EFI_IPSEC_PROTOCOL EFI_IPSEC_PROTOCOL;\r
-typedef struct _EFI_IPSEC2_PROTOCOL EFI_IPSEC2_PROTOCOL;\r
+typedef struct _EFI_IPSEC_PROTOCOL EFI_IPSEC_PROTOCOL;\r
+typedef struct _EFI_IPSEC2_PROTOCOL EFI_IPSEC2_PROTOCOL;\r
\r
///\r
/// EFI_IPSEC_FRAGMENT_DATA\r
/// defines the instances of packet fragments.\r
///\r
typedef struct _EFI_IPSEC_FRAGMENT_DATA {\r
- UINT32 FragmentLength;\r
- VOID *FragmentBuffer;\r
+ UINT32 FragmentLength;\r
+ VOID *FragmentBuffer;\r
} EFI_IPSEC_FRAGMENT_DATA;\r
\r
-\r
/**\r
Handles IPsec packet processing for inbound and outbound IP packets.\r
\r
IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,\r
IN UINT32 *FragmentCount,\r
IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection,\r
- OUT EFI_EVENT *RecycleSignal\r
+ OUT EFI_EVENT *RecycleSignal\r
);\r
\r
///\r
// and IPv6 environment.\r
///\r
struct _EFI_IPSEC_PROTOCOL {\r
- EFI_IPSEC_PROCESS Process; ///< Handle the IPsec message.\r
- EFI_EVENT DisabledEvent; ///< Event signaled when the interface is disabled.\r
- BOOLEAN DisabledFlag; ///< State of the interface.\r
+ EFI_IPSEC_PROCESS Process; ///< Handle the IPsec message.\r
+ EFI_EVENT DisabledEvent; ///< Event signaled when the interface is disabled.\r
+ BOOLEAN DisabledFlag; ///< State of the interface.\r
};\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_IPSEC_PROCESSEXT) (\r
+(EFIAPI *EFI_IPSEC_PROCESSEXT)(\r
IN EFI_IPSEC2_PROTOCOL *This,\r
IN EFI_HANDLE NicHandle,\r
IN UINT8 IpVer,\r
IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,\r
IN OUT UINT32 *FragmentCount,\r
IN EFI_IPSEC_TRAFFIC_DIR TrafficDirection,\r
- OUT EFI_EVENT *RecycleSignal\r
+ OUT EFI_EVENT *RecycleSignal\r
);\r
\r
///\r
/// encrypting each IP packet in a data stream.\r
///\r
struct _EFI_IPSEC2_PROTOCOL {\r
-EFI_IPSEC_PROCESSEXT ProcessExt;\r
-EFI_EVENT DisabledEvent;\r
-BOOLEAN DisabledFlag;\r
+ EFI_IPSEC_PROCESSEXT ProcessExt;\r
+ EFI_EVENT DisabledEvent;\r
+ BOOLEAN DisabledFlag;\r
};\r
\r
-extern EFI_GUID gEfiIpSecProtocolGuid;\r
-extern EFI_GUID gEfiIpSec2ProtocolGuid;\r
+extern EFI_GUID gEfiIpSecProtocolGuid;\r
+extern EFI_GUID gEfiIpSec2ProtocolGuid;\r
#endif\r
#ifndef __EFI_IPSE_CCONFIG_PROTOCOL_H__\r
#define __EFI_IPSE_CCONFIG_PROTOCOL_H__\r
\r
-\r
#define EFI_IPSEC_CONFIG_PROTOCOL_GUID \\r
{ \\r
0xce5e5929, 0xc7a3, 0x4602, {0xad, 0x9e, 0xc9, 0xda, 0xf9, 0x4e, 0xbf, 0xcf } \\r
/// EFI_IP_ADDRESS_INFO\r
///\r
typedef struct _EFI_IP_ADDRESS_INFO {\r
- EFI_IP_ADDRESS Address; ///< The IPv4 or IPv6 address\r
- UINT8 PrefixLength; ///< The length of the prefix associated with the Address.\r
+ EFI_IP_ADDRESS Address; ///< The IPv4 or IPv6 address\r
+ UINT8 PrefixLength; ///< The length of the prefix associated with the Address.\r
} EFI_IP_ADDRESS_INFO;\r
\r
-\r
///\r
/// EFI_IPSEC_SPD_SELECTOR\r
///\r
///\r
/// Specifies the actual number of entries in LocalAddress.\r
///\r
- UINT32 LocalAddressCount;\r
+ UINT32 LocalAddressCount;\r
///\r
/// A list of ranges of IPv4 or IPv6 addresses, which refers to the\r
/// addresses being protected by IPsec policy.\r
///\r
- EFI_IP_ADDRESS_INFO *LocalAddress;\r
+ EFI_IP_ADDRESS_INFO *LocalAddress;\r
///\r
/// Specifies the actual number of entries in RemoteAddress.\r
///\r
- UINT32 RemoteAddressCount;\r
+ UINT32 RemoteAddressCount;\r
///\r
/// A list of ranges of IPv4 or IPv6 addresses, which are peer entities\r
/// to LocalAddress.\r
///\r
- EFI_IP_ADDRESS_INFO *RemoteAddress;\r
+ EFI_IP_ADDRESS_INFO *RemoteAddress;\r
///\r
/// Next layer protocol. Obtained from the IPv4 Protocol or the IPv6\r
/// Next Header fields. The next layer protocol is whatever comes\r
/// after any IP extension headers that are present. A zero value is a\r
/// wildcard that matches any value in NextLayerProtocol field.\r
///\r
- UINT16 NextLayerProtocol;\r
+ UINT16 NextLayerProtocol;\r
///\r
/// Local Port if the Next Layer Protocol uses two ports (as do TCP,\r
/// UDP, and others). A zero value is a wildcard that matches any\r
/// value in LocalPort field.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// A designed port range size. The start port is LocalPort, and\r
/// the total number of ports is described by LocalPortRange.\r
/// This field is ignored if NextLayerProtocol does not use\r
/// ports.\r
///\r
- UINT16 LocalPortRange;\r
+ UINT16 LocalPortRange;\r
///\r
/// Remote Port if the Next Layer Protocol uses two ports. A zero\r
/// value is a wildcard that matches any value in RemotePort field.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
///\r
/// A designed port range size. The start port is RemotePort, and\r
/// the total number of ports is described by RemotePortRange.\r
/// This field is ignored if NextLayerProtocol does not use ports.\r
///\r
- UINT16 RemotePortRange;\r
+ UINT16 RemotePortRange;\r
} EFI_IPSEC_SPD_SELECTOR;\r
\r
///\r
/// AH, this is the authentication algorithm. The ByteCount\r
/// includes pad bytes for cryptographic operations.\r
///\r
- UINT64 ByteCount;\r
+ UINT64 ByteCount;\r
///\r
/// A time interval in second that warns the implementation to\r
/// initiate action such as setting up a replacement SA.\r
///\r
- UINT64 SoftLifetime;\r
+ UINT64 SoftLifetime;\r
///\r
/// A time interval in second when the current SA ends and is\r
/// destroyed.\r
///\r
- UINT64 HardLifetime;\r
+ UINT64 HardLifetime;\r
} EFI_IPSEC_SA_LIFETIME;\r
\r
///\r
///\r
/// Local tunnel address when IPsec mode is EfiIPsecTunnel.\r
///\r
- EFI_IP_ADDRESS LocalTunnelAddress;\r
+ EFI_IP_ADDRESS LocalTunnelAddress;\r
///\r
/// Remote tunnel address when IPsec mode is EfiIPsecTunnel.\r
///\r
- EFI_IP_ADDRESS RemoteTunnelAddress;\r
+ EFI_IP_ADDRESS RemoteTunnelAddress;\r
///\r
/// The option of copying the DF bit from an outbound package\r
/// to the tunnel mode header that it emits, when traffic is\r
/// carried via a tunnel mode SA.\r
///\r
- EFI_IPSEC_TUNNEL_DF_OPTION DF;\r
+ EFI_IPSEC_TUNNEL_DF_OPTION DF;\r
} EFI_IPSEC_TUNNEL_OPTION;\r
\r
///\r
/// Extended Sequence Number. Is this SA using extended sequence\r
/// numbers. 64 bit counter is used if TRUE.\r
///\r
- BOOLEAN ExtSeqNum;\r
+ BOOLEAN ExtSeqNum;\r
///\r
/// A flag indicating whether overflow of the sequence number\r
/// counter should generate an auditable event and prevent\r
/// transmission of additional packets on the SA, or whether rollover\r
/// is permitted.\r
///\r
- BOOLEAN SeqOverflow;\r
+ BOOLEAN SeqOverflow;\r
///\r
/// Is this SA using stateful fragment checking. TRUE represents\r
/// stateful fragment checking.\r
///\r
- BOOLEAN FragCheck;\r
+ BOOLEAN FragCheck;\r
///\r
/// A time interval after which a SA must be replaced with a new SA\r
/// (and new SPI) or terminated.\r
///\r
- EFI_IPSEC_SA_LIFETIME SaLifetime;\r
+ EFI_IPSEC_SA_LIFETIME SaLifetime;\r
///\r
/// IPsec mode: tunnel or transport.\r
///\r
- EFI_IPSEC_MODE Mode;\r
+ EFI_IPSEC_MODE Mode;\r
///\r
/// Tunnel Option. TunnelOption is ignored if Mode is EfiIPsecTransport.\r
///\r
- EFI_IPSEC_TUNNEL_OPTION *TunnelOption;\r
+ EFI_IPSEC_TUNNEL_OPTION *TunnelOption;\r
///\r
/// IPsec protocol: AH or ESP\r
///\r
- EFI_IPSEC_PROTOCOL_TYPE Proto;\r
+ EFI_IPSEC_PROTOCOL_TYPE Proto;\r
///\r
/// Cryptographic algorithm type used for authentication.\r
///\r
- UINT8 AuthAlgoId;\r
+ UINT8 AuthAlgoId;\r
///\r
/// Cryptographic algorithm type used for encryption. EncAlgo is\r
/// NULL when IPsec protocol is AH. For ESP protocol, EncAlgo\r
/// can also be used to describe the algorithm if a combined mode\r
/// algorithm is used.\r
///\r
- UINT8 EncAlgoId;\r
+ UINT8 EncAlgoId;\r
} EFI_IPSEC_PROCESS_POLICY;\r
\r
///\r
/// that is used by a receiver to identity the SA to which an incoming\r
/// package should be bound.\r
///\r
- UINT32 Spi;\r
+ UINT32 Spi;\r
///\r
/// IPsec protocol: AH or ESP\r
///\r
- EFI_IPSEC_PROTOCOL_TYPE Proto;\r
+ EFI_IPSEC_PROTOCOL_TYPE Proto;\r
///\r
/// Destination IP address.\r
///\r
- EFI_IP_ADDRESS DestAddress;\r
+ EFI_IP_ADDRESS DestAddress;\r
} EFI_IPSEC_SA_ID;\r
\r
-\r
-#define MAX_PEERID_LEN 128\r
+#define MAX_PEERID_LEN 128\r
\r
///\r
/// EFI_IPSEC_SPD_DATA\r
/// A null-terminated ASCII name string which is used as a symbolic\r
/// identifier for an IPsec Local or Remote address.\r
///\r
- UINT8 Name[MAX_PEERID_LEN];\r
+ UINT8 Name[MAX_PEERID_LEN];\r
///\r
/// Bit-mapped list describing Populate from Packet flags. When\r
/// creating a SA, if PackageFlag bit is set to TRUE, instantiate\r
/// Bit 4: EFI_IPSEC_SPD_SELECTOR.RemotePort\r
/// Others: Reserved.\r
///\r
- UINT32 PackageFlag;\r
+ UINT32 PackageFlag;\r
///\r
/// The traffic direction of data gram.\r
///\r
- EFI_IPSEC_TRAFFIC_DIR TrafficDirection;\r
+ EFI_IPSEC_TRAFFIC_DIR TrafficDirection;\r
///\r
/// Processing choices to indicate which action is required by this\r
/// policy.\r
///\r
- EFI_IPSEC_ACTION Action;\r
+ EFI_IPSEC_ACTION Action;\r
///\r
/// The policy and rule information for a SPD entry.\r
///\r
- EFI_IPSEC_PROCESS_POLICY *ProcessingPolicy;\r
+ EFI_IPSEC_PROCESS_POLICY *ProcessingPolicy;\r
///\r
/// Specifies the actual number of entries in SaId list.\r
///\r
- UINTN SaIdCount;\r
+ UINTN SaIdCount;\r
///\r
/// The SAD entry used for the traffic processing. The\r
/// existed SAD entry links indicate this is the manual key case.\r
///\r
- EFI_IPSEC_SA_ID SaId[1];\r
+ EFI_IPSEC_SA_ID SaId[1];\r
} EFI_IPSEC_SPD_DATA;\r
\r
///\r
/// The required authentication algorithm is specified in RFC 4305.\r
///\r
typedef struct _EFI_IPSEC_AH_ALGO_INFO {\r
- UINT8 AuthAlgoId;\r
- UINTN AuthKeyLength;\r
- VOID *AuthKey;\r
+ UINT8 AuthAlgoId;\r
+ UINTN AuthKeyLength;\r
+ VOID *AuthKey;\r
} EFI_IPSEC_AH_ALGO_INFO;\r
\r
///\r
/// confidentiality and authentication services.\r
///\r
typedef struct _EFI_IPSEC_ESP_ALGO_INFO {\r
- UINT8 EncAlgoId;\r
- UINTN EncKeyLength;\r
- VOID *EncKey;\r
- UINT8 AuthAlgoId;\r
- UINTN AuthKeyLength;\r
- VOID *AuthKey;\r
+ UINT8 EncAlgoId;\r
+ UINTN EncKeyLength;\r
+ VOID *EncKey;\r
+ UINT8 AuthAlgoId;\r
+ UINTN AuthKeyLength;\r
+ VOID *AuthKey;\r
} EFI_IPSEC_ESP_ALGO_INFO;\r
\r
///\r
/// EFI_IPSEC_ALGO_INFO\r
///\r
typedef union {\r
- EFI_IPSEC_AH_ALGO_INFO AhAlgoInfo;\r
- EFI_IPSEC_ESP_ALGO_INFO EspAlgoInfo;\r
+ EFI_IPSEC_AH_ALGO_INFO AhAlgoInfo;\r
+ EFI_IPSEC_ESP_ALGO_INFO EspAlgoInfo;\r
} EFI_IPSEC_ALGO_INFO;\r
\r
///\r
///\r
/// IPsec mode: tunnel or transport.\r
///\r
- EFI_IPSEC_MODE Mode;\r
+ EFI_IPSEC_MODE Mode;\r
///\r
/// Sequence Number Counter. A 64-bit counter used to generate the\r
/// sequence number field in AH or ESP headers.\r
///\r
- UINT64 SNCount;\r
+ UINT64 SNCount;\r
///\r
/// Anti-Replay Window. A 64-bit counter and a bit-map used to\r
/// determine whether an inbound AH or ESP packet is a replay.\r
///\r
- UINT8 AntiReplayWindows;\r
+ UINT8 AntiReplayWindows;\r
///\r
/// AH/ESP cryptographic algorithm, key and parameters.\r
///\r
- EFI_IPSEC_ALGO_INFO AlgoInfo;\r
+ EFI_IPSEC_ALGO_INFO AlgoInfo;\r
///\r
/// Lifetime of this SA.\r
///\r
- EFI_IPSEC_SA_LIFETIME SaLifetime;\r
+ EFI_IPSEC_SA_LIFETIME SaLifetime;\r
///\r
/// Any observed path MTU and aging variables. The Path MTU\r
/// processing is defined in section 8 of RFC 4301.\r
///\r
- UINT32 PathMTU;\r
+ UINT32 PathMTU;\r
///\r
/// Link to one SPD entry.\r
///\r
- EFI_IPSEC_SPD_SELECTOR *SpdSelector;\r
+ EFI_IPSEC_SPD_SELECTOR *SpdSelector;\r
///\r
/// Indication of whether it's manually set or negotiated automatically.\r
/// If ManualSet is FALSE, the corresponding SA entry is inserted through\r
/// IKE protocol negotiation.\r
///\r
- BOOLEAN ManualSet;\r
+ BOOLEAN ManualSet;\r
} EFI_IPSEC_SA_DATA;\r
\r
///\r
///\r
/// IPsec mode: tunnel or transport\r
///\r
- EFI_IPSEC_MODE Mode;\r
+ EFI_IPSEC_MODE Mode;\r
///\r
/// Sequence Number Counter. A 64-bit counter used to generate the sequence\r
/// number field in AH or ESP headers.\r
///\r
- UINT64 SNCount;\r
+ UINT64 SNCount;\r
///\r
/// Anti-Replay Window. A 64-bit counter and a bit-map used to determine\r
/// whether an inbound AH or ESP packet is a replay.\r
///\r
- UINT8 AntiReplayWindows;\r
+ UINT8 AntiReplayWindows;\r
///\r
/// AH/ESP cryptographic algorithm, key and parameters.\r
///\r
- EFI_IPSEC_ALGO_INFO AlgoInfo;\r
+ EFI_IPSEC_ALGO_INFO AlgoInfo;\r
///\r
/// Lifetime of this SA.\r
///\r
- EFI_IPSEC_SA_LIFETIME SaLifetime;\r
+ EFI_IPSEC_SA_LIFETIME SaLifetime;\r
///\r
/// Any observed path MTU and aging variables. The Path MTU processing is\r
/// defined in section 8 of RFC 4301.\r
///\r
- UINT32 PathMTU;\r
+ UINT32 PathMTU;\r
///\r
/// Link to one SPD entry\r
///\r
- EFI_IPSEC_SPD_SELECTOR *SpdSelector;\r
+ EFI_IPSEC_SPD_SELECTOR *SpdSelector;\r
///\r
/// Indication of whether it's manually set or negotiated automatically.\r
/// If ManualSet is FALSE, the corresponding SA entry is inserted through IKE\r
/// protocol negotiation\r
///\r
- BOOLEAN ManualSet;\r
+ BOOLEAN ManualSet;\r
///\r
/// The tunnel header IP source address.\r
///\r
- EFI_IP_ADDRESS TunnelSourceAddress;\r
+ EFI_IP_ADDRESS TunnelSourceAddress;\r
///\r
/// The tunnel header IP destination address.\r
///\r
- EFI_IP_ADDRESS TunnelDestinationAddress;\r
+ EFI_IP_ADDRESS TunnelDestinationAddress;\r
} EFI_IPSEC_SA_DATA2;\r
\r
-\r
///\r
/// EFI_IPSEC_PAD_ID\r
/// specifies the identifier for PAD entry, which is also used for SPD lookup.\r
///\r
/// Flag to identify which type of PAD Id is used.\r
///\r
- BOOLEAN PeerIdValid;\r
+ BOOLEAN PeerIdValid;\r
union {\r
///\r
/// Pointer to the IPv4 or IPv6 address range.\r
///\r
- EFI_IP_ADDRESS_INFO IpAddress;\r
+ EFI_IP_ADDRESS_INFO IpAddress;\r
///\r
/// Pointer to a null terminated ASCII string\r
/// representing the symbolic names. A PeerId can be a DNS\r
/// name, Distinguished Name, RFC 822 email address or Key ID\r
/// (specified in section 4.4.3.1 of RFC 4301)\r
///\r
- UINT8 PeerId[MAX_PEERID_LEN];\r
+ UINT8 PeerId[MAX_PEERID_LEN];\r
} Id;\r
} EFI_IPSEC_PAD_ID;\r
\r
/// of type EFI_IPSEC_CONFIG_DATA_TYPE.\r
///\r
typedef union {\r
- EFI_IPSEC_SPD_SELECTOR SpdSelector;\r
- EFI_IPSEC_SA_ID SaId;\r
- EFI_IPSEC_PAD_ID PadId;\r
+ EFI_IPSEC_SPD_SELECTOR SpdSelector;\r
+ EFI_IPSEC_SA_ID SaId;\r
+ EFI_IPSEC_PAD_ID PadId;\r
} EFI_IPSEC_CONFIG_SELECTOR;\r
\r
///\r
///\r
/// Authentication Protocol for IPsec security association management.\r
///\r
- EFI_IPSEC_AUTH_PROTOCOL_TYPE AuthProtocol;\r
+ EFI_IPSEC_AUTH_PROTOCOL_TYPE AuthProtocol;\r
///\r
/// Authentication method used.\r
///\r
- EFI_IPSEC_AUTH_METHOD AuthMethod;\r
+ EFI_IPSEC_AUTH_METHOD AuthMethod;\r
///\r
/// The IKE ID payload will be used as a symbolic name for SPD\r
/// lookup if IkeIdFlag is TRUE. Otherwise, the remote IP\r
/// address provided in traffic selector playloads will be used.\r
///\r
- BOOLEAN IkeIdFlag;\r
+ BOOLEAN IkeIdFlag;\r
///\r
/// The size of Authentication data buffer, in bytes.\r
///\r
- UINTN AuthDataSize;\r
+ UINTN AuthDataSize;\r
///\r
/// Buffer for Authentication data, (e.g., the pre-shared secret or the\r
/// trust anchor relative to which the peer's certificate will be\r
/// validated).\r
///\r
- VOID *AuthData;\r
+ VOID *AuthData;\r
///\r
/// The size of RevocationData, in bytes\r
///\r
- UINTN RevocationDataSize;\r
+ UINTN RevocationDataSize;\r
///\r
/// Pointer to CRL or OCSP data, if certificates are used for\r
/// authentication method.\r
///\r
- VOID *RevocationData;\r
+ VOID *RevocationData;\r
} EFI_IPSEC_PAD_DATA;\r
\r
-\r
/**\r
Set the security association, security policy and peer authorization configuration\r
information for the EFI IPsec driver.\r
/// protocol for IPsec configuration in both IPv4 and IPv6 environment.\r
///\r
struct _EFI_IPSEC_CONFIG_PROTOCOL {\r
- EFI_IPSEC_CONFIG_SET_DATA SetData;\r
- EFI_IPSEC_CONFIG_GET_DATA GetData;\r
- EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR GetNextSelector;\r
- EFI_IPSEC_CONFIG_REGISTER_NOTIFY RegisterDataNotify;\r
- EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;\r
+ EFI_IPSEC_CONFIG_SET_DATA SetData;\r
+ EFI_IPSEC_CONFIG_GET_DATA GetData;\r
+ EFI_IPSEC_CONFIG_GET_NEXT_SELECTOR GetNextSelector;\r
+ EFI_IPSEC_CONFIG_REGISTER_NOTIFY RegisterDataNotify;\r
+ EFI_IPSEC_CONFIG_UNREGISTER_NOTIFY UnregisterDataNotify;\r
};\r
\r
-extern EFI_GUID gEfiIpSecConfigProtocolGuid;\r
+extern EFI_GUID gEfiIpSecConfigProtocolGuid;\r
\r
#endif\r
0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81} \\r
}\r
\r
-typedef struct _EFI_ISA_HC_PROTOCOL EFI_ISA_HC_PROTOCOL;\r
-typedef struct _EFI_ISA_HC_PROTOCOL *PEFI_ISA_HC_PROTOCOL;\r
+typedef struct _EFI_ISA_HC_PROTOCOL EFI_ISA_HC_PROTOCOL;\r
+typedef struct _EFI_ISA_HC_PROTOCOL *PEFI_ISA_HC_PROTOCOL;\r
\r
/**\r
Open I/O aperture.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_ISA_HC_OPEN_IO) (\r
+(EFIAPI *EFI_ISA_HC_OPEN_IO)(\r
IN CONST EFI_ISA_HC_PROTOCOL *This,\r
IN UINT16 IoAddress,\r
IN UINT16 IoLength,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_ISA_HC_CLOSE_IO) (\r
+(EFIAPI *EFI_ISA_HC_CLOSE_IO)(\r
IN CONST EFI_ISA_HC_PROTOCOL *This,\r
IN UINT64 IoApertureHandle\r
);\r
/// The version of this protocol. Higher version numbers are backward\r
/// compatible with lower version numbers.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// Open an I/O aperture.\r
///\r
- EFI_ISA_HC_OPEN_IO OpenIoAperture;\r
+ EFI_ISA_HC_OPEN_IO OpenIoAperture;\r
///\r
/// Close an I/O aperture.\r
///\r
- EFI_ISA_HC_CLOSE_IO CloseIoAperture;\r
+ EFI_ISA_HC_CLOSE_IO CloseIoAperture;\r
};\r
\r
///\r
/// Reference to variable defined in the .DEC file\r
///\r
-extern EFI_GUID gEfiIsaHcProtocolGuid;\r
-extern EFI_GUID gEfiIsaHcServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiIsaHcProtocolGuid;\r
+extern EFI_GUID gEfiIsaHcServiceBindingProtocolGuid;\r
\r
-#endif // __ISA_HC_H__\r
+#endif // __ISA_HC_H__\r
// Where appropriate, EFI_KMS_DATA_TYPE values may be combined using a bitwise 'OR'\r
// operation to indicate support for multiple data types.\r
//\r
-#define EFI_KMS_DATA_TYPE_NONE 0\r
-#define EFI_KMS_DATA_TYPE_BINARY 1\r
-#define EFI_KMS_DATA_TYPE_ASCII 2\r
-#define EFI_KMS_DATA_TYPE_UNICODE 4\r
-#define EFI_KMS_DATA_TYPE_UTF8 8\r
-\r
+#define EFI_KMS_DATA_TYPE_NONE 0\r
+#define EFI_KMS_DATA_TYPE_BINARY 1\r
+#define EFI_KMS_DATA_TYPE_ASCII 2\r
+#define EFI_KMS_DATA_TYPE_UNICODE 4\r
+#define EFI_KMS_DATA_TYPE_UTF8 8\r
\r
//\r
// The key formats recognized by the KMS protocol are defined by an EFI_GUID which specifies\r
}\r
///@}\r
\r
-#define EFI_KMS_ATTRIBUTE_TYPE_NONE 0x00\r
-#define EFI_KMS_ATTRIBUTE_TYPE_INTEGER 0x01\r
-#define EFI_KMS_ATTRIBUTE_TYPE_LONG_INTEGER 0x02\r
-#define EFI_KMS_ATTRIBUTE_TYPE_BIG_INTEGER 0x03\r
-#define EFI_KMS_ATTRIBUTE_TYPE_ENUMERATION 0x04\r
-#define EFI_KMS_ATTRIBUTE_TYPE_BOOLEAN 0x05\r
-#define EFI_KMS_ATTRIBUTE_TYPE_BYTE_STRING 0x06\r
-#define EFI_KMS_ATTRIBUTE_TYPE_TEXT_STRING 0x07\r
-#define EFI_KMS_ATTRIBUTE_TYPE_DATE_TIME 0x08\r
-#define EFI_KMS_ATTRIBUTE_TYPE_INTERVAL 0x09\r
-#define EFI_KMS_ATTRIBUTE_TYPE_STRUCTURE 0x0A\r
-#define EFI_KMS_ATTRIBUTE_TYPE_DYNAMIC 0x0B\r
+#define EFI_KMS_ATTRIBUTE_TYPE_NONE 0x00\r
+#define EFI_KMS_ATTRIBUTE_TYPE_INTEGER 0x01\r
+#define EFI_KMS_ATTRIBUTE_TYPE_LONG_INTEGER 0x02\r
+#define EFI_KMS_ATTRIBUTE_TYPE_BIG_INTEGER 0x03\r
+#define EFI_KMS_ATTRIBUTE_TYPE_ENUMERATION 0x04\r
+#define EFI_KMS_ATTRIBUTE_TYPE_BOOLEAN 0x05\r
+#define EFI_KMS_ATTRIBUTE_TYPE_BYTE_STRING 0x06\r
+#define EFI_KMS_ATTRIBUTE_TYPE_TEXT_STRING 0x07\r
+#define EFI_KMS_ATTRIBUTE_TYPE_DATE_TIME 0x08\r
+#define EFI_KMS_ATTRIBUTE_TYPE_INTERVAL 0x09\r
+#define EFI_KMS_ATTRIBUTE_TYPE_STRUCTURE 0x0A\r
+#define EFI_KMS_ATTRIBUTE_TYPE_DYNAMIC 0x0B\r
\r
typedef struct {\r
///\r
/// Length in bytes of the KeyData.\r
///\r
- UINT32 KeySize;\r
+ UINT32 KeySize;\r
///\r
/// The data of the key.\r
///\r
- UINT8 KeyData[1];\r
+ UINT8 KeyData[1];\r
} EFI_KMS_FORMAT_GENERIC_DYNAMIC;\r
\r
typedef struct {\r
///\r
/// The size in bytes for the client identifier.\r
///\r
- UINT16 ClientIdSize;\r
+ UINT16 ClientIdSize;\r
///\r
/// Pointer to a valid client identifier.\r
///\r
- VOID *ClientId;\r
+ VOID *ClientId;\r
///\r
/// The client name string type used by this client. The string type set here must be one of\r
/// the string types reported in the ClientNameStringTypes field of the KMS protocol. If the\r
/// KMS does not support client names, this field should be set to EFI_KMS_DATA_TYPE_NONE.\r
///\r
- UINT8 ClientNameType;\r
+ UINT8 ClientNameType;\r
///\r
/// The size in characters for the client name. This field will be ignored if\r
/// ClientNameStringType is set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it must contain\r
/// number of characters contained in the ClientName field.\r
///\r
- UINT8 ClientNameCount;\r
+ UINT8 ClientNameCount;\r
///\r
/// Pointer to a client name. This field will be ignored if ClientNameStringType is set to\r
/// EFI_KMS_DATA_TYPE_NONE. Otherwise, it must point to a valid string of the specified type.\r
///\r
- VOID *ClientName;\r
+ VOID *ClientName;\r
} EFI_KMS_CLIENT_INFO;\r
\r
typedef struct {\r
///\r
/// The size of the KeyIdentifier field in bytes. This field is limited to the range 0 to 255.\r
///\r
- UINT8 KeyIdentifierSize;\r
+ UINT8 KeyIdentifierSize;\r
///\r
/// Pointer to an array of KeyIdentifierType elements.\r
///\r
- VOID *KeyIdentifier;\r
+ VOID *KeyIdentifier;\r
///\r
/// An EFI_GUID which specifies the algorithm and key value size for this key.\r
///\r
- EFI_GUID KeyFormat;\r
+ EFI_GUID KeyFormat;\r
///\r
/// Pointer to a key value for a key specified by the KeyFormat field. A NULL value for this\r
/// field indicates that no key is available.\r
///\r
- VOID *KeyValue;\r
+ VOID *KeyValue;\r
///\r
/// Specifies the results of KMS operations performed with this descriptor. This field is used\r
/// to indicate the status of individual operations when a KMS function is called with multiple\r
/// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The\r
/// definition of the value is outside the scope of this standard and may be defined by the KMS.\r
///\r
- UINT16 Tag;\r
+ UINT16 Tag;\r
///\r
/// Part of a tag-type-length triplet that identifies the KeyAttributeData formatting. The\r
/// definition of the value is outside the scope of this standard and may be defined by the KMS.\r
///\r
- UINT16 Type;\r
+ UINT16 Type;\r
///\r
/// Length in bytes of the KeyAttributeData.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// An array of bytes to hold the attribute data associated with the KeyAttributeIdentifier.\r
///\r
- UINT8 KeyAttributeData[1];\r
+ UINT8 KeyAttributeData[1];\r
} EFI_KMS_DYNAMIC_FIELD;\r
\r
typedef struct {\r
///\r
/// The number of members in the EFI_KMS_DYNAMIC_ATTRIBUTE structure.\r
///\r
- UINT32 FieldCount;\r
+ UINT32 FieldCount;\r
///\r
/// An array of EFI_KMS_DYNAMIC_FIELD structures.\r
///\r
- EFI_KMS_DYNAMIC_FIELD Field[1];\r
+ EFI_KMS_DYNAMIC_FIELD Field[1];\r
} EFI_KMS_DYNAMIC_ATTRIBUTE;\r
\r
typedef struct {\r
/// by the EFI_KMS_DATA_TYPE constants, except that EFI_KMS_DATA_TYPE_BINARY is not\r
/// valid for this field.\r
///\r
- UINT8 KeyAttributeIdentifierType;\r
+ UINT8 KeyAttributeIdentifierType;\r
///\r
/// The length of the KeyAttributeIdentifier field in units defined by KeyAttributeIdentifierType\r
/// field. This field is limited to the range 0 to 255.\r
///\r
- UINT8 KeyAttributeIdentifierCount;\r
+ UINT8 KeyAttributeIdentifierCount;\r
///\r
/// Pointer to an array of KeyAttributeIdentifierType elements. For string types, there must\r
/// not be a null-termination element at the end of the array.\r
///\r
- VOID *KeyAttributeIdentifier;\r
+ VOID *KeyAttributeIdentifier;\r
///\r
/// The instance number of this attribute. If there is only one instance, the value is set to\r
/// one. If this value is set to 0xFFFF (all binary 1's) then this field should be ignored if an\r
/// field in the request. If set to 0xFFFF in the request, it will match any attribute with the\r
/// same KeyAttributeIdentifier.\r
///\r
- UINT16 KeyAttributeInstance;\r
+ UINT16 KeyAttributeInstance;\r
///\r
/// The data type of the KeyAttributeValue (e.g. struct, bool, etc.). See the list of\r
/// KeyAttributeType definitions.\r
///\r
- UINT16 KeyAttributeType;\r
+ UINT16 KeyAttributeType;\r
///\r
/// The size in bytes of the KeyAttribute field. A value of zero for this field indicates that no\r
/// key attribute value is available.\r
///\r
- UINT16 KeyAttributeValueSize;\r
+ UINT16 KeyAttributeValueSize;\r
///\r
/// Pointer to a key attribute value for the attribute specified by the KeyAttributeIdentifier\r
/// field. If the KeyAttributeValueSize field is zero, then this field must be NULL.\r
///\r
- VOID *KeyAttributeValue;\r
+ VOID *KeyAttributeValue;\r
///\r
/// KeyAttributeStatusSpecifies the results of KMS operations performed with this attribute.\r
/// This field is used to indicate the status of individual operations when a KMS function is\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_GET_SERVICE_STATUS) (\r
+(EFIAPI *EFI_KMS_GET_SERVICE_STATUS)(\r
IN EFI_KMS_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_REGISTER_CLIENT) (\r
+(EFIAPI *EFI_KMS_REGISTER_CLIENT)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINTN *ClientDataSize OPTIONAL,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_CREATE_KEY) (\r
+(EFIAPI *EFI_KMS_CREATE_KEY)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINT16 *KeyDescriptorCount,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_GET_KEY) (\r
+(EFIAPI *EFI_KMS_GET_KEY)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINT16 *KeyDescriptorCount,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_ADD_KEY) (\r
+(EFIAPI *EFI_KMS_ADD_KEY)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINT16 *KeyDescriptorCount,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_DELETE_KEY) (\r
+(EFIAPI *EFI_KMS_DELETE_KEY)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINT16 *KeyDescriptorCount,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_GET_KEY_ATTRIBUTES) (\r
+(EFIAPI *EFI_KMS_GET_KEY_ATTRIBUTES)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN UINT8 *KeyIdentifierSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_ADD_KEY_ATTRIBUTES) (\r
+(EFIAPI *EFI_KMS_ADD_KEY_ATTRIBUTES)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN UINT8 *KeyIdentifierSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_DELETE_KEY_ATTRIBUTES) (\r
+(EFIAPI *EFI_KMS_DELETE_KEY_ATTRIBUTES)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN UINT8 *KeyIdentifierSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_KMS_GET_KEY_BY_ATTRIBUTES) (\r
+(EFIAPI *EFI_KMS_GET_KEY_BY_ATTRIBUTES)(\r
IN EFI_KMS_PROTOCOL *This,\r
IN EFI_KMS_CLIENT_INFO *Client,\r
IN OUT UINTN *KeyAttributeCount,\r
/// connected to the KMS, then a call to this function will initiate a connection. This is the\r
/// only function that is valid for use prior to the service being marked available.\r
///\r
- EFI_KMS_GET_SERVICE_STATUS GetServiceStatus;\r
+ EFI_KMS_GET_SERVICE_STATUS GetServiceStatus;\r
///\r
/// Register a specific client with the KMS.\r
///\r
- EFI_KMS_REGISTER_CLIENT RegisterClient;\r
+ EFI_KMS_REGISTER_CLIENT RegisterClient;\r
///\r
/// Request the generation of a new key and retrieve it.\r
///\r
- EFI_KMS_CREATE_KEY CreateKey;\r
+ EFI_KMS_CREATE_KEY CreateKey;\r
///\r
/// Retrieve an existing key.\r
///\r
- EFI_KMS_GET_KEY GetKey;\r
+ EFI_KMS_GET_KEY GetKey;\r
///\r
/// Add a local key to KMS database. If there is an existing key with this key identifier in the\r
/// KMS database, it will be replaced with the new key.\r
///\r
- EFI_KMS_ADD_KEY AddKey;\r
+ EFI_KMS_ADD_KEY AddKey;\r
///\r
/// Delete an existing key from the KMS database.\r
///\r
- EFI_KMS_DELETE_KEY DeleteKey;\r
+ EFI_KMS_DELETE_KEY DeleteKey;\r
///\r
/// Get attributes for an existing key in the KMS database.\r
///\r
- EFI_KMS_GET_KEY_ATTRIBUTES GetKeyAttributes;\r
+ EFI_KMS_GET_KEY_ATTRIBUTES GetKeyAttributes;\r
///\r
/// Add attributes to an existing key in the KMS database.\r
///\r
- EFI_KMS_ADD_KEY_ATTRIBUTES AddKeyAttributes;\r
+ EFI_KMS_ADD_KEY_ATTRIBUTES AddKeyAttributes;\r
///\r
/// Delete attributes for an existing key in the KMS database.\r
///\r
- EFI_KMS_DELETE_KEY_ATTRIBUTES DeleteKeyAttributes;\r
+ EFI_KMS_DELETE_KEY_ATTRIBUTES DeleteKeyAttributes;\r
///\r
/// Get existing key(s) with the specified attributes.\r
///\r
- EFI_KMS_GET_KEY_BY_ATTRIBUTES GetKeyByAttributes;\r
+ EFI_KMS_GET_KEY_BY_ATTRIBUTES GetKeyByAttributes;\r
///\r
/// The version of this EFI_KMS_PROTOCOL structure. This must be set to 0x00020040 for\r
/// the initial version of this protocol.\r
///\r
- UINT32 ProtocolVersion;\r
+ UINT32 ProtocolVersion;\r
///\r
/// Optional GUID used to identify a specific KMS. This GUID may be supplied by the provider,\r
/// by the implementation, or may be null. If is null, then the ServiceName must not be null.\r
///\r
- EFI_GUID ServiceId;\r
+ EFI_GUID ServiceId;\r
///\r
/// Optional pointer to a unicode string which may be used to identify the KMS or provide\r
/// other information about the supplier.\r
///\r
- CHAR16 *ServiceName;\r
+ CHAR16 *ServiceName;\r
///\r
/// Optional 32-bit value which may be used to indicate the version of the KMS provided by\r
/// the supplier.\r
///\r
- UINT32 ServiceVersion;\r
+ UINT32 ServiceVersion;\r
///\r
/// TRUE if and only if the service is active and available for use. To avoid unnecessary\r
/// delays in POST, this protocol may be installed without connecting to the service. In this\r
/// as defined in the reminder of this protocol are not guaranteed to be valid until the service\r
/// has been marked available.\r
///\r
- BOOLEAN ServiceAvailable;\r
+ BOOLEAN ServiceAvailable;\r
///\r
/// TRUE if and only if the service supports client identifiers. Client identifiers may be used\r
/// for auditing, access control or any other purpose specific to the implementation.\r
///\r
- BOOLEAN ClientIdSupported;\r
+ BOOLEAN ClientIdSupported;\r
///\r
/// TRUE if and only if the service requires a client identifier in order to process key requests.\r
/// FALSE otherwise.\r
///\r
- BOOLEAN ClientIdRequired;\r
+ BOOLEAN ClientIdRequired;\r
///\r
/// The maximum size in bytes for the client identifier.\r
///\r
- UINT16 ClientIdMaxSize;\r
+ UINT16 ClientIdMaxSize;\r
///\r
/// The client name string type(s) supported by the KMS service. If client names are not\r
/// supported, this field will be set the EFI_KMS_DATA_TYPE_NONE. Otherwise, it will be set\r
/// to the inclusive 'OR' of all client name formats supported. Client names may be used for\r
/// auditing, access control or any other purpose specific to the implementation.\r
///\r
- UINT8 ClientNameStringTypes;\r
+ UINT8 ClientNameStringTypes;\r
///\r
/// TRUE if only if the KMS requires a client name to be supplied to the service.\r
/// FALSE otherwise.\r
///\r
- BOOLEAN ClientNameRequired;\r
+ BOOLEAN ClientNameRequired;\r
///\r
/// The maximum number of characters allowed for the client name.\r
///\r
- UINT16 ClientNameMaxCount;\r
+ UINT16 ClientNameMaxCount;\r
///\r
/// TRUE if and only if the service supports arbitrary client data requests. The use of client\r
/// data requires the caller to have specific knowledge of the individual KMS service and\r
/// should be used only if absolutely necessary.\r
/// FALSE otherwise.\r
///\r
- BOOLEAN ClientDataSupported;\r
+ BOOLEAN ClientDataSupported;\r
///\r
/// The maximum size in bytes for the client data. If the maximum data size is not specified\r
/// by the KMS or it is not known, then this field must be filled with all ones.\r
///\r
- UINTN ClientDataMaxSize;\r
+ UINTN ClientDataMaxSize;\r
///\r
/// TRUE if variable length key identifiers are supported.\r
/// FALSE if a fixed length key identifier is supported.\r
///\r
- BOOLEAN KeyIdVariableLenSupported;\r
+ BOOLEAN KeyIdVariableLenSupported;\r
///\r
/// If KeyIdVariableLenSupported is TRUE, this is the maximum supported key identifier length\r
/// in bytes. Otherwise this is the fixed length of key identifier supported. Key ids shorter\r
/// than the fixed length will be padded on the right with blanks.\r
///\r
- UINTN KeyIdMaxSize;\r
+ UINTN KeyIdMaxSize;\r
///\r
/// The number of key format/size GUIDs returned in the KeyFormats field.\r
///\r
- UINTN KeyFormatsCount;\r
+ UINTN KeyFormatsCount;\r
///\r
/// A pointer to an array of EFI_GUID values which specify key formats/sizes supported by\r
/// this KMS. Each format/size pair will be specified by a separate EFI_GUID. At least one\r
/// using an arbitrary GUID, but any GUID not recognized by the implementation or not\r
/// supported by the KMS will return an error code of EFI_UNSUPPORTED\r
///\r
- EFI_GUID *KeyFormats;\r
+ EFI_GUID *KeyFormats;\r
///\r
/// TRUE if key attributes are supported.\r
/// FALSE if key attributes are not supported.\r
///\r
- BOOLEAN KeyAttributesSupported;\r
+ BOOLEAN KeyAttributesSupported;\r
///\r
/// The key attribute identifier string type(s) supported by the KMS service. If key attributes\r
/// are not supported, this field will be set to EFI_KMS_DATA_TYPE_NONE. Otherwise, it will\r
/// be set to the inclusive 'OR' of all key attribute identifier string types supported.\r
/// EFI_KMS_DATA_TYPE_BINARY is not valid for this field.\r
///\r
- UINT8 KeyAttributeIdStringTypes;\r
- UINT16 KeyAttributeIdMaxCount;\r
+ UINT8 KeyAttributeIdStringTypes;\r
+ UINT16 KeyAttributeIdMaxCount;\r
///\r
/// The number of predefined KeyAttributes structures returned in the KeyAttributes\r
/// parameter. If the KMS does not support predefined key attributes, or if it does not\r
/// provide a method to obtain predefined key attributes data, then this field must be zero.\r
///\r
- UINTN KeyAttributesCount;\r
+ UINTN KeyAttributesCount;\r
///\r
/// A pointer to an array of KeyAttributes structures which contains the predefined\r
/// attributes supported by this KMS. Each structure must contain a valid key attribute\r
/// does not distinguish between predefined and used defined attributes, and therefore,\r
/// predefined attributes not enumerated will still be processed to the KMS.\r
///\r
- EFI_KMS_KEY_ATTRIBUTE *KeyAttributes;\r
+ EFI_KMS_KEY_ATTRIBUTE *KeyAttributes;\r
};\r
\r
-extern EFI_GUID gEfiKmsFormatGeneric128Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric160Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric256Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric512Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric1024Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric2048Guid;\r
-extern EFI_GUID gEfiKmsFormatGeneric3072Guid;\r
-extern EFI_GUID gEfiKmsFormatMd2128Guid;\r
-extern EFI_GUID gEfiKmsFormatMdc2128Guid;\r
-extern EFI_GUID gEfiKmsFormatMd4128Guid;\r
-extern EFI_GUID gEfiKmsFormatMdc4128Guid;\r
-extern EFI_GUID gEfiKmsFormatMd5128Guid;\r
-extern EFI_GUID gEfiKmsFormatMd5sha128Guid;\r
-extern EFI_GUID gEfiKmsFormatSha1160Guid;\r
-extern EFI_GUID gEfiKmsFormatSha256256Guid;\r
-extern EFI_GUID gEfiKmsFormatSha512512Guid;\r
-extern EFI_GUID gEfiKmsFormatAesxts128Guid;\r
-extern EFI_GUID gEfiKmsFormatAesxts256Guid;\r
-extern EFI_GUID gEfiKmsFormatAescbc128Guid;\r
-extern EFI_GUID gEfiKmsFormatAescbc256Guid;\r
-extern EFI_GUID gEfiKmsFormatRsasha11024Guid;\r
-extern EFI_GUID gEfiKmsFormatRsasha12048Guid;\r
-extern EFI_GUID gEfiKmsFormatRsasha2562048Guid;\r
-extern EFI_GUID gEfiKmsFormatRsasha2563072Guid;\r
-extern EFI_GUID gEfiKmsProtocolGuid;\r
+extern EFI_GUID gEfiKmsFormatGeneric128Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric160Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric256Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric512Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric1024Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric2048Guid;\r
+extern EFI_GUID gEfiKmsFormatGeneric3072Guid;\r
+extern EFI_GUID gEfiKmsFormatMd2128Guid;\r
+extern EFI_GUID gEfiKmsFormatMdc2128Guid;\r
+extern EFI_GUID gEfiKmsFormatMd4128Guid;\r
+extern EFI_GUID gEfiKmsFormatMdc4128Guid;\r
+extern EFI_GUID gEfiKmsFormatMd5128Guid;\r
+extern EFI_GUID gEfiKmsFormatMd5sha128Guid;\r
+extern EFI_GUID gEfiKmsFormatSha1160Guid;\r
+extern EFI_GUID gEfiKmsFormatSha256256Guid;\r
+extern EFI_GUID gEfiKmsFormatSha512512Guid;\r
+extern EFI_GUID gEfiKmsFormatAesxts128Guid;\r
+extern EFI_GUID gEfiKmsFormatAesxts256Guid;\r
+extern EFI_GUID gEfiKmsFormatAescbc128Guid;\r
+extern EFI_GUID gEfiKmsFormatAescbc256Guid;\r
+extern EFI_GUID gEfiKmsFormatRsasha11024Guid;\r
+extern EFI_GUID gEfiKmsFormatRsasha12048Guid;\r
+extern EFI_GUID gEfiKmsFormatRsasha2562048Guid;\r
+extern EFI_GUID gEfiKmsFormatRsasha2563072Guid;\r
+extern EFI_GUID gEfiKmsProtocolGuid;\r
\r
#endif\r
#ifndef __LEGACY_REGION2_H__\r
#define __LEGACY_REGION2_H__\r
\r
-\r
#define EFI_LEGACY_REGION2_PROTOCOL_GUID \\r
{ \\r
0x70101eaf, 0x85, 0x440c, {0xb3, 0x56, 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } \\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_LEGACY_REGION2_DECODE)(\r
- IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- OUT UINT32 *Granularity,\r
- IN BOOLEAN *On\r
- );\r
-\r
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ OUT UINT32 *Granularity,\r
+ IN BOOLEAN *On\r
+ );\r
\r
/**\r
Modify the hardware to disallow memory writes in a region.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_LEGACY_REGION2_LOCK)(\r
- IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- OUT UINT32 *Granularity\r
- );\r
-\r
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ OUT UINT32 *Granularity\r
+ );\r
\r
/**\r
Modify the hardware to disallow memory attribute changes in a region.\r
OUT UINT32 *Granularity OPTIONAL\r
);\r
\r
-\r
/**\r
Modify the hardware to allow memory writes in a region.\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_LEGACY_REGION2_UNLOCK)(\r
- IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
- IN UINT32 Start,\r
- IN UINT32 Length,\r
- OUT UINT32 *Granularity\r
- );\r
-\r
+ IN EFI_LEGACY_REGION2_PROTOCOL *This,\r
+ IN UINT32 Start,\r
+ IN UINT32 Length,\r
+ OUT UINT32 *Granularity\r
+ );\r
\r
typedef enum {\r
LegacyRegionDecoded, ///< This region is currently set to allow reads.\r
LegacyRegionNotLocked ///< This region's attributes are not locked.\r
} EFI_LEGACY_REGION_ATTRIBUTE;\r
\r
-\r
typedef struct {\r
///\r
/// The beginning of the physical address of this\r
/// region.\r
///\r
- UINT32 Start;\r
+ UINT32 Start;\r
///\r
/// The number of bytes in this region.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// Attribute of the Legacy Region Descriptor that\r
/// describes the capabilities for that memory region.\r
///\r
- EFI_LEGACY_REGION_ATTRIBUTE Attribute;\r
+ EFI_LEGACY_REGION_ATTRIBUTE Attribute;\r
///\r
/// Describes the byte length programmability\r
/// associated with the Start address and the specified\r
/// Attribute setting.\r
- UINT32 Granularity;\r
+ UINT32 Granularity;\r
} EFI_LEGACY_REGION_DESCRIPTOR;\r
\r
-\r
/**\r
Get region information for the attributes of the Legacy Region.\r
\r
OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor\r
);\r
\r
-\r
///\r
/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory\r
/// attributes of the Option ROM shadowing region, 0xC0000 to 0xFFFFF.\r
/// boot-lock. These protocols may be set in any combination.\r
///\r
struct _EFI_LEGACY_REGION2_PROTOCOL {\r
- EFI_LEGACY_REGION2_DECODE Decode;\r
- EFI_LEGACY_REGION2_LOCK Lock;\r
- EFI_LEGACY_REGION2_BOOT_LOCK BootLock;\r
- EFI_LEGACY_REGION2_UNLOCK UnLock;\r
- EFI_LEGACY_REGION_GET_INFO GetInfo;\r
+ EFI_LEGACY_REGION2_DECODE Decode;\r
+ EFI_LEGACY_REGION2_LOCK Lock;\r
+ EFI_LEGACY_REGION2_BOOT_LOCK BootLock;\r
+ EFI_LEGACY_REGION2_UNLOCK UnLock;\r
+ EFI_LEGACY_REGION_GET_INFO GetInfo;\r
};\r
\r
-extern EFI_GUID gEfiLegacyRegion2ProtocolGuid;\r
+extern EFI_GUID gEfiLegacyRegion2ProtocolGuid;\r
\r
#endif\r
{ 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}\r
\r
typedef\r
-struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;\r
\r
/**\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
IN UINT8 EraseBlockOpcode\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
IN UINT8 WriteStatusPrefix\r
);\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
IN UINT32 BiosBaseAddress\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
IN UINT32 BiosAddress,\r
IN UINT32 BlocksToProtect\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r
IN UINT32 BiosAddress,\r
IN UINT32 BlocksToProtect\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER) (\r
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER)(\r
IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r
);\r
\r
///\r
/// Maximum offset from the BIOS base address that is able to be protected.\r
///\r
- UINT32 MaximumOffset;\r
+ UINT32 MaximumOffset;\r
\r
///\r
/// Maximum number of bytes that can be protected by one range register.\r
///\r
- UINT32 MaximumRangeBytes;\r
+ UINT32 MaximumRangeBytes;\r
\r
///\r
/// The number of registers available for protecting the BIOS.\r
///\r
- UINT32 RangeRegisterCount;\r
+ UINT32 RangeRegisterCount;\r
\r
///\r
/// Set the erase block opcode.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;\r
\r
///\r
/// Set the write status prefix opcode.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;\r
\r
///\r
/// Set the BIOS base address.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
\r
///\r
/// Clear the SPI protect range registers.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
\r
///\r
/// Determine if the SPI range is protected.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
\r
///\r
/// Set the next protect range register.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
\r
///\r
/// Lock the SPI controller configuration.\r
///\r
- EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;\r
+ EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;\r
};\r
\r
-extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;\r
+extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;\r
\r
#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS) (\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS)(\r
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
IN UINT32 BiosBaseAddress\r
);\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT) (\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT)(\r
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED) (\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED)(\r
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
IN UINT32 BiosAddress,\r
IN UINT32 BlocksToProtect\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE) (\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE)(\r
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This,\r
IN UINT32 BiosAddress,\r
IN UINT32 BlocksToProtect\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER) (\r
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER)(\r
IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL *This\r
);\r
\r
/// This protocol manipulates the SPI NOR flash parts using a common set of\r
/// commands.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL FlashProtocol;\r
\r
//\r
// Legacy flash (SPI host) controller support\r
///\r
/// Set the BIOS base address.\r
///\r
- EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r
\r
///\r
/// Clear the SPI protect range registers.\r
///\r
- EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r
\r
///\r
/// Determine if the SPI range is protected.\r
///\r
- EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r
\r
///\r
/// Set the next protect range register.\r
///\r
- EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r
\r
///\r
/// Lock the SPI controller configuration.\r
///\r
- EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController;\r
+ EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER LockController;\r
};\r
\r
-extern EFI_GUID gEfiLegacySpiFlashProtocolGuid;\r
+extern EFI_GUID gEfiLegacySpiFlashProtocolGuid;\r
\r
#endif // __LEGACY_SPI_FLASH_PROTOCOL_H__\r
{ 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }}\r
\r
typedef\r
-struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
+ struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r
EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL;\r
\r
-extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid;\r
+extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid;\r
\r
#endif // __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__\r
{ 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }}\r
\r
typedef\r
-struct _EFI_LEGACY_SPI_FLASH_PROTOCOL\r
+ struct _EFI_LEGACY_SPI_FLASH_PROTOCOL\r
EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL;\r
\r
-extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid;\r
+extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid;\r
\r
#endif // __SPI_SMM_FLASH_PROTOCOL_H__\r
///\r
/// Protocol Guid defined by EFI1.1.\r
///\r
-#define LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL_GUID\r
+#define LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL_GUID\r
\r
typedef struct _EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL;\r
\r
///\r
/// Backward-compatible with EFI1.1\r
///\r
-typedef EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_INTERFACE;\r
+typedef EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_INTERFACE;\r
\r
/**\r
Causes the driver to load a specified file.\r
/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices.\r
///\r
struct _EFI_LOAD_FILE_PROTOCOL {\r
- EFI_LOAD_FILE LoadFile;\r
+ EFI_LOAD_FILE LoadFile;\r
};\r
\r
-extern EFI_GUID gEfiLoadFileProtocolGuid;\r
+extern EFI_GUID gEfiLoadFileProtocolGuid;\r
\r
#endif\r
///\r
/// Protocol Guid defined by UEFI2.1.\r
///\r
-#define LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL_GUID\r
+#define LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL_GUID\r
\r
typedef struct _EFI_LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL;\r
\r
-\r
/**\r
Causes the driver to load a specified file.\r
\r
/// The EFI_LOAD_FILE_PROTOCOL is a simple protocol used to obtain files from arbitrary devices.\r
///\r
struct _EFI_LOAD_FILE2_PROTOCOL {\r
- EFI_LOAD_FILE2 LoadFile;\r
+ EFI_LOAD_FILE2 LoadFile;\r
};\r
\r
-extern EFI_GUID gEfiLoadFile2ProtocolGuid;\r
+extern EFI_GUID gEfiLoadFile2ProtocolGuid;\r
\r
#endif\r
///\r
/// Protocol GUID defined in EFI1.1.\r
///\r
-#define LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE_PROTOCOL_GUID\r
+#define LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE_PROTOCOL_GUID\r
\r
///\r
/// EFI_SYSTEM_TABLE & EFI_IMAGE_UNLOAD are defined in EfiApi.h\r
///\r
/// Revision defined in EFI1.1.\r
///\r
-#define EFI_LOADED_IMAGE_INFORMATION_REVISION EFI_LOADED_IMAGE_PROTOCOL_REVISION\r
+#define EFI_LOADED_IMAGE_INFORMATION_REVISION EFI_LOADED_IMAGE_PROTOCOL_REVISION\r
\r
///\r
/// Can be used on any image handle to obtain information about the loaded image.\r
///\r
typedef struct {\r
- UINT32 Revision; ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure.\r
- ///< All future revisions will be backward compatible to the current revision.\r
- EFI_HANDLE ParentHandle; ///< Parent image's image handle. NULL if the image is loaded directly from\r
- ///< the firmware's boot manager.\r
- EFI_SYSTEM_TABLE *SystemTable; ///< the image's EFI system table pointer.\r
+ UINT32 Revision; ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure.\r
+ ///< All future revisions will be backward compatible to the current revision.\r
+ EFI_HANDLE ParentHandle; ///< Parent image's image handle. NULL if the image is loaded directly from\r
+ ///< the firmware's boot manager.\r
+ EFI_SYSTEM_TABLE *SystemTable; ///< the image's EFI system table pointer.\r
\r
//\r
// Source location of image\r
//\r
- EFI_HANDLE DeviceHandle; ///< The device handle that the EFI Image was loaded from.\r
- EFI_DEVICE_PATH_PROTOCOL *FilePath; ///< A pointer to the file path portion specific to DeviceHandle\r
- ///< that the EFI Image was loaded from.\r
- VOID *Reserved; ///< Reserved. DO NOT USE.\r
+ EFI_HANDLE DeviceHandle; ///< The device handle that the EFI Image was loaded from.\r
+ EFI_DEVICE_PATH_PROTOCOL *FilePath; ///< A pointer to the file path portion specific to DeviceHandle\r
+ ///< that the EFI Image was loaded from.\r
+ VOID *Reserved; ///< Reserved. DO NOT USE.\r
\r
//\r
// Images load options\r
//\r
- UINT32 LoadOptionsSize;///< The size in bytes of LoadOptions.\r
- VOID *LoadOptions; ///< A pointer to the image's binary load options.\r
+ UINT32 LoadOptionsSize; ///< The size in bytes of LoadOptions.\r
+ VOID *LoadOptions; ///< A pointer to the image's binary load options.\r
\r
//\r
// Location of where image was loaded\r
//\r
- VOID *ImageBase; ///< The base address at which the image was loaded.\r
- UINT64 ImageSize; ///< The size in bytes of the loaded image.\r
- EFI_MEMORY_TYPE ImageCodeType; ///< The memory type that the code sections were loaded as.\r
- EFI_MEMORY_TYPE ImageDataType; ///< The memory type that the data sections were loaded as.\r
- EFI_IMAGE_UNLOAD Unload;\r
+ VOID *ImageBase; ///< The base address at which the image was loaded.\r
+ UINT64 ImageSize; ///< The size in bytes of the loaded image.\r
+ EFI_MEMORY_TYPE ImageCodeType; ///< The memory type that the code sections were loaded as.\r
+ EFI_MEMORY_TYPE ImageDataType; ///< The memory type that the data sections were loaded as.\r
+ EFI_IMAGE_UNLOAD Unload;\r
} EFI_LOADED_IMAGE_PROTOCOL;\r
\r
//\r
//\r
typedef EFI_LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE;\r
\r
-extern EFI_GUID gEfiLoadedImageProtocolGuid;\r
-extern EFI_GUID gEfiLoadedImageDevicePathProtocolGuid;\r
+extern EFI_GUID gEfiLoadedImageProtocolGuid;\r
+extern EFI_GUID gEfiLoadedImageDevicePathProtocolGuid;\r
\r
#endif\r
} EFI_MANAGED_NETWORK_CONFIG_DATA;\r
\r
typedef struct {\r
- EFI_TIME Timestamp;\r
- EFI_EVENT RecycleEvent;\r
- UINT32 PacketLength;\r
- UINT32 HeaderLength;\r
- UINT32 AddressLength;\r
- UINT32 DataLength;\r
- BOOLEAN BroadcastFlag;\r
- BOOLEAN MulticastFlag;\r
- BOOLEAN PromiscuousFlag;\r
- UINT16 ProtocolType;\r
- VOID *DestinationAddress;\r
- VOID *SourceAddress;\r
- VOID *MediaHeader;\r
- VOID *PacketData;\r
+ EFI_TIME Timestamp;\r
+ EFI_EVENT RecycleEvent;\r
+ UINT32 PacketLength;\r
+ UINT32 HeaderLength;\r
+ UINT32 AddressLength;\r
+ UINT32 DataLength;\r
+ BOOLEAN BroadcastFlag;\r
+ BOOLEAN MulticastFlag;\r
+ BOOLEAN PromiscuousFlag;\r
+ UINT16 ProtocolType;\r
+ VOID *DestinationAddress;\r
+ VOID *SourceAddress;\r
+ VOID *MediaHeader;\r
+ VOID *PacketData;\r
} EFI_MANAGED_NETWORK_RECEIVE_DATA;\r
\r
typedef struct {\r
- UINT32 FragmentLength;\r
- VOID *FragmentBuffer;\r
+ UINT32 FragmentLength;\r
+ VOID *FragmentBuffer;\r
} EFI_MANAGED_NETWORK_FRAGMENT_DATA;\r
\r
typedef struct {\r
- EFI_MAC_ADDRESS *DestinationAddress; //OPTIONAL\r
- EFI_MAC_ADDRESS *SourceAddress; //OPTIONAL\r
- UINT16 ProtocolType; //OPTIONAL\r
- UINT32 DataLength;\r
- UINT16 HeaderLength; //OPTIONAL\r
- UINT16 FragmentCount;\r
- EFI_MANAGED_NETWORK_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_MAC_ADDRESS *DestinationAddress; // OPTIONAL\r
+ EFI_MAC_ADDRESS *SourceAddress; // OPTIONAL\r
+ UINT16 ProtocolType; // OPTIONAL\r
+ UINT32 DataLength;\r
+ UINT16 HeaderLength; // OPTIONAL\r
+ UINT16 FragmentCount;\r
+ EFI_MANAGED_NETWORK_FRAGMENT_DATA FragmentTable[1];\r
} EFI_MANAGED_NETWORK_TRANSMIT_DATA;\r
\r
-\r
typedef struct {\r
///\r
/// This Event will be signaled after the Status field is updated\r
/// EFI_NOTIFY_SIGNAL. The Task Priority Level (TPL) of\r
/// Event must be lower than or equal to TPL_CALLBACK.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// The status that is returned to the caller at the end of the operation\r
/// to indicate whether this operation completed successfully.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
union {\r
///\r
/// When this token is used for receiving, RxData is a pointer to the EFI_MANAGED_NETWORK_RECEIVE_DATA.\r
///\r
- EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData;\r
+ EFI_MANAGED_NETWORK_RECEIVE_DATA *RxData;\r
///\r
/// When this token is used for transmitting, TxData is a pointer to the EFI_MANAGED_NETWORK_TRANSMIT_DATA.\r
///\r
- EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData;\r
+ EFI_MANAGED_NETWORK_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_MANAGED_NETWORK_COMPLETION_TOKEN;\r
\r
IN EFI_MANAGED_NETWORK_COMPLETION_TOKEN *Token\r
);\r
\r
-\r
/**\r
Aborts an asynchronous transmit or receive request.\r
\r
/// perform raw (unformatted) asynchronous network packet I/O.\r
///\r
struct _EFI_MANAGED_NETWORK_PROTOCOL {\r
- EFI_MANAGED_NETWORK_GET_MODE_DATA GetModeData;\r
- EFI_MANAGED_NETWORK_CONFIGURE Configure;\r
- EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC McastIpToMac;\r
- EFI_MANAGED_NETWORK_GROUPS Groups;\r
- EFI_MANAGED_NETWORK_TRANSMIT Transmit;\r
- EFI_MANAGED_NETWORK_RECEIVE Receive;\r
- EFI_MANAGED_NETWORK_CANCEL Cancel;\r
- EFI_MANAGED_NETWORK_POLL Poll;\r
+ EFI_MANAGED_NETWORK_GET_MODE_DATA GetModeData;\r
+ EFI_MANAGED_NETWORK_CONFIGURE Configure;\r
+ EFI_MANAGED_NETWORK_MCAST_IP_TO_MAC McastIpToMac;\r
+ EFI_MANAGED_NETWORK_GROUPS Groups;\r
+ EFI_MANAGED_NETWORK_TRANSMIT Transmit;\r
+ EFI_MANAGED_NETWORK_RECEIVE Receive;\r
+ EFI_MANAGED_NETWORK_CANCEL Cancel;\r
+ EFI_MANAGED_NETWORK_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiManagedNetworkServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiManagedNetworkProtocolGuid;\r
+extern EFI_GUID gEfiManagedNetworkServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiManagedNetworkProtocolGuid;\r
\r
#endif\r
///\r
/// Declare forward reference for the Metronome Architectural Protocol\r
///\r
-typedef struct _EFI_METRONOME_ARCH_PROTOCOL EFI_METRONOME_ARCH_PROTOCOL;\r
+typedef struct _EFI_METRONOME_ARCH_PROTOCOL EFI_METRONOME_ARCH_PROTOCOL;\r
\r
/**\r
The WaitForTick() function waits for the number of ticks specified by\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_METRONOME_WAIT_FOR_TICK)(\r
- IN EFI_METRONOME_ARCH_PROTOCOL *This,\r
- IN UINT32 TickNumber\r
+ IN EFI_METRONOME_ARCH_PROTOCOL *This,\r
+ IN UINT32 TickNumber\r
);\r
\r
///\r
/// require calibrated delays.\r
///\r
struct _EFI_METRONOME_ARCH_PROTOCOL {\r
- EFI_METRONOME_WAIT_FOR_TICK WaitForTick;\r
+ EFI_METRONOME_WAIT_FOR_TICK WaitForTick;\r
\r
///\r
/// The period of platform's known time source in 100 nS units.\r
/// not be modified after the Metronome architectural protocol is\r
/// installed. All consumers must treat this as a read-only field.\r
///\r
- UINT32 TickPeriod;\r
+ UINT32 TickPeriod;\r
};\r
\r
-extern EFI_GUID gEfiMetronomeArchProtocolGuid;\r
+extern EFI_GUID gEfiMetronomeArchProtocolGuid;\r
\r
#endif\r
0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac } \\r
}\r
\r
-\r
-typedef struct _EFI_MM_ACCESS_PROTOCOL EFI_MM_ACCESS_PROTOCOL;\r
+typedef struct _EFI_MM_ACCESS_PROTOCOL EFI_MM_ACCESS_PROTOCOL;\r
\r
/**\r
Opens the MMRAM area to be accessible by a boot-service driver.\r
/// controller would publish this protocol.\r
///\r
struct _EFI_MM_ACCESS_PROTOCOL {\r
- EFI_MM_OPEN Open;\r
- EFI_MM_CLOSE Close;\r
- EFI_MM_LOCK Lock;\r
- EFI_MM_CAPABILITIES GetCapabilities;\r
+ EFI_MM_OPEN Open;\r
+ EFI_MM_CLOSE Close;\r
+ EFI_MM_LOCK Lock;\r
+ EFI_MM_CAPABILITIES GetCapabilities;\r
///\r
/// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is locked.\r
///\r
- BOOLEAN LockState;\r
+ BOOLEAN LockState;\r
///\r
/// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is open.\r
///\r
- BOOLEAN OpenState;\r
+ BOOLEAN OpenState;\r
};\r
\r
-extern EFI_GUID gEfiMmAccessProtocolGuid;\r
+extern EFI_GUID gEfiMmAccessProtocolGuid;\r
\r
#endif\r
-\r
0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 } \\r
}\r
\r
-typedef struct _EFI_MM_BASE_PROTOCOL EFI_MM_BASE_PROTOCOL;\r
+typedef struct _EFI_MM_BASE_PROTOCOL EFI_MM_BASE_PROTOCOL;\r
\r
/**\r
Service to indicate whether the driver is currently executing in the MM Initialization phase.\r
/// services and determine whether the driver is being invoked inside MMRAM or outside of MMRAM.\r
///\r
struct _EFI_MM_BASE_PROTOCOL {\r
- EFI_MM_INSIDE_OUT InMm;\r
- EFI_MM_GET_MMST_LOCATION GetMmstLocation;\r
+ EFI_MM_INSIDE_OUT InMm;\r
+ EFI_MM_GET_MMST_LOCATION GetMmstLocation;\r
};\r
\r
-extern EFI_GUID gEfiMmBaseProtocolGuid;\r
+extern EFI_GUID gEfiMmBaseProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Allows for disambiguation of the message format.\r
///\r
- EFI_GUID HeaderGuid;\r
+ EFI_GUID HeaderGuid;\r
///\r
/// Describes the size of Data (in bytes) and does not include the size of the header.\r
///\r
- UINTN MessageLength;\r
+ UINTN MessageLength;\r
///\r
/// Designates an array of bytes that is MessageLength in size.\r
///\r
- UINT8 Data[1];\r
+ UINT8 Data[1];\r
} EFI_MM_COMMUNICATE_HEADER;\r
\r
#pragma pack()\r
0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 } \\r
}\r
\r
-typedef struct _EFI_MM_COMMUNICATION_PROTOCOL EFI_MM_COMMUNICATION_PROTOCOL;\r
+typedef struct _EFI_MM_COMMUNICATION_PROTOCOL EFI_MM_COMMUNICATION_PROTOCOL;\r
\r
/**\r
Communicates with a registered handler.\r
/// between DXE drivers and a registered MMI handler.\r
///\r
struct _EFI_MM_COMMUNICATION_PROTOCOL {\r
- EFI_MM_COMMUNICATE Communicate;\r
+ EFI_MM_COMMUNICATE Communicate;\r
};\r
\r
-extern EFI_GUID gEfiMmCommunicationProtocolGuid;\r
+extern EFI_GUID gEfiMmCommunicationProtocolGuid;\r
\r
#endif\r
-\r
0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 } \\r
}\r
\r
-typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL EFI_MM_COMMUNICATION2_PROTOCOL;\r
+typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL EFI_MM_COMMUNICATION2_PROTOCOL;\r
\r
/**\r
Communicates with a registered handler.\r
/// between DXE drivers and a registered MMI handler.\r
///\r
struct _EFI_MM_COMMUNICATION2_PROTOCOL {\r
- EFI_MM_COMMUNICATE2 Communicate;\r
+ EFI_MM_COMMUNICATE2 Communicate;\r
};\r
\r
-extern EFI_GUID gEfiMmCommunication2ProtocolGuid;\r
+extern EFI_GUID gEfiMmCommunication2ProtocolGuid;\r
\r
#endif\r
-\r
0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 } \\r
}\r
\r
-typedef struct _EFI_MM_CONFIGURATION_PROTOCOL EFI_MM_CONFIGURATION_PROTOCOL;\r
+typedef struct _EFI_MM_CONFIGURATION_PROTOCOL EFI_MM_CONFIGURATION_PROTOCOL;\r
\r
/**\r
Register the MM Foundation entry point.\r
///\r
/// A pointer to an array MMRAM ranges used by the initial MM entry code.\r
///\r
- EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;\r
- EFI_MM_REGISTER_MM_ENTRY RegisterMmEntry;\r
+ EFI_MM_RESERVED_MMRAM_REGION *MmramReservedRegions;\r
+ EFI_MM_REGISTER_MM_ENTRY RegisterMmEntry;\r
};\r
\r
-extern EFI_GUID gEfiMmConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiMmConfigurationProtocolGuid;\r
\r
#endif\r
-\r
}\r
\r
typedef struct _EFI_MM_CONTROL_PROTOCOL EFI_MM_CONTROL_PROTOCOL;\r
-typedef UINTN EFI_MM_PERIOD;\r
+typedef UINTN EFI_MM_PERIOD;\r
\r
/**\r
Invokes MMI activation from either the preboot or runtime environment.\r
/// these signals.\r
///\r
struct _EFI_MM_CONTROL_PROTOCOL {\r
- EFI_MM_ACTIVATE Trigger;\r
- EFI_MM_DEACTIVATE Clear;\r
+ EFI_MM_ACTIVATE Trigger;\r
+ EFI_MM_DEACTIVATE Clear;\r
///\r
/// Minimum interval at which the platform can set the period. A maximum is not\r
/// specified in that the MM infrastructure code can emulate a maximum interval that is\r
/// greater than the hardware capabilities by using software emulation in the MM\r
/// infrastructure code.\r
///\r
- EFI_MM_PERIOD MinimumTriggerPeriod;\r
+ EFI_MM_PERIOD MinimumTriggerPeriod;\r
};\r
\r
-extern EFI_GUID gEfiMmControlProtocolGuid;\r
+extern EFI_GUID gEfiMmControlProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// x86/X64 standard registers\r
///\r
- EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4,\r
- EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5,\r
- EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6,\r
- EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r
- EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r
- EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r
- EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10,\r
- EFI_MM_SAVE_STATE_REGISTER_ES = 20,\r
- EFI_MM_SAVE_STATE_REGISTER_CS = 21,\r
- EFI_MM_SAVE_STATE_REGISTER_SS = 22,\r
- EFI_MM_SAVE_STATE_REGISTER_DS = 23,\r
- EFI_MM_SAVE_STATE_REGISTER_FS = 24,\r
- EFI_MM_SAVE_STATE_REGISTER_GS = 25,\r
- EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r
- EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27,\r
- EFI_MM_SAVE_STATE_REGISTER_DR7 = 28,\r
- EFI_MM_SAVE_STATE_REGISTER_DR6 = 29,\r
- EFI_MM_SAVE_STATE_REGISTER_R8 = 30,\r
- EFI_MM_SAVE_STATE_REGISTER_R9 = 31,\r
- EFI_MM_SAVE_STATE_REGISTER_R10 = 32,\r
- EFI_MM_SAVE_STATE_REGISTER_R11 = 33,\r
- EFI_MM_SAVE_STATE_REGISTER_R12 = 34,\r
- EFI_MM_SAVE_STATE_REGISTER_R13 = 35,\r
- EFI_MM_SAVE_STATE_REGISTER_R14 = 36,\r
- EFI_MM_SAVE_STATE_REGISTER_R15 = 37,\r
- EFI_MM_SAVE_STATE_REGISTER_RAX = 38,\r
- EFI_MM_SAVE_STATE_REGISTER_RBX = 39,\r
- EFI_MM_SAVE_STATE_REGISTER_RCX = 40,\r
- EFI_MM_SAVE_STATE_REGISTER_RDX = 41,\r
- EFI_MM_SAVE_STATE_REGISTER_RSP = 42,\r
- EFI_MM_SAVE_STATE_REGISTER_RBP = 43,\r
- EFI_MM_SAVE_STATE_REGISTER_RSI = 44,\r
- EFI_MM_SAVE_STATE_REGISTER_RDI = 45,\r
- EFI_MM_SAVE_STATE_REGISTER_RIP = 46,\r
- EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51,\r
- EFI_MM_SAVE_STATE_REGISTER_CR0 = 52,\r
- EFI_MM_SAVE_STATE_REGISTER_CR3 = 53,\r
- EFI_MM_SAVE_STATE_REGISTER_CR4 = 54,\r
- EFI_MM_SAVE_STATE_REGISTER_FCW = 256,\r
- EFI_MM_SAVE_STATE_REGISTER_FSW = 257,\r
- EFI_MM_SAVE_STATE_REGISTER_FTW = 258,\r
- EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259,\r
- EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260,\r
- EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261,\r
- EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r
- EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263,\r
- EFI_MM_SAVE_STATE_REGISTER_MM0 = 264,\r
- EFI_MM_SAVE_STATE_REGISTER_MM1 = 265,\r
- EFI_MM_SAVE_STATE_REGISTER_MM2 = 266,\r
- EFI_MM_SAVE_STATE_REGISTER_MM3 = 267,\r
- EFI_MM_SAVE_STATE_REGISTER_MM4 = 268,\r
- EFI_MM_SAVE_STATE_REGISTER_MM5 = 269,\r
- EFI_MM_SAVE_STATE_REGISTER_MM6 = 270,\r
- EFI_MM_SAVE_STATE_REGISTER_MM7 = 271,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286,\r
- EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287,\r
+ EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4,\r
+ EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5,\r
+ EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6,\r
+ EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r
+ EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r
+ EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r
+ EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10,\r
+ EFI_MM_SAVE_STATE_REGISTER_ES = 20,\r
+ EFI_MM_SAVE_STATE_REGISTER_CS = 21,\r
+ EFI_MM_SAVE_STATE_REGISTER_SS = 22,\r
+ EFI_MM_SAVE_STATE_REGISTER_DS = 23,\r
+ EFI_MM_SAVE_STATE_REGISTER_FS = 24,\r
+ EFI_MM_SAVE_STATE_REGISTER_GS = 25,\r
+ EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r
+ EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27,\r
+ EFI_MM_SAVE_STATE_REGISTER_DR7 = 28,\r
+ EFI_MM_SAVE_STATE_REGISTER_DR6 = 29,\r
+ EFI_MM_SAVE_STATE_REGISTER_R8 = 30,\r
+ EFI_MM_SAVE_STATE_REGISTER_R9 = 31,\r
+ EFI_MM_SAVE_STATE_REGISTER_R10 = 32,\r
+ EFI_MM_SAVE_STATE_REGISTER_R11 = 33,\r
+ EFI_MM_SAVE_STATE_REGISTER_R12 = 34,\r
+ EFI_MM_SAVE_STATE_REGISTER_R13 = 35,\r
+ EFI_MM_SAVE_STATE_REGISTER_R14 = 36,\r
+ EFI_MM_SAVE_STATE_REGISTER_R15 = 37,\r
+ EFI_MM_SAVE_STATE_REGISTER_RAX = 38,\r
+ EFI_MM_SAVE_STATE_REGISTER_RBX = 39,\r
+ EFI_MM_SAVE_STATE_REGISTER_RCX = 40,\r
+ EFI_MM_SAVE_STATE_REGISTER_RDX = 41,\r
+ EFI_MM_SAVE_STATE_REGISTER_RSP = 42,\r
+ EFI_MM_SAVE_STATE_REGISTER_RBP = 43,\r
+ EFI_MM_SAVE_STATE_REGISTER_RSI = 44,\r
+ EFI_MM_SAVE_STATE_REGISTER_RDI = 45,\r
+ EFI_MM_SAVE_STATE_REGISTER_RIP = 46,\r
+ EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51,\r
+ EFI_MM_SAVE_STATE_REGISTER_CR0 = 52,\r
+ EFI_MM_SAVE_STATE_REGISTER_CR3 = 53,\r
+ EFI_MM_SAVE_STATE_REGISTER_CR4 = 54,\r
+ EFI_MM_SAVE_STATE_REGISTER_FCW = 256,\r
+ EFI_MM_SAVE_STATE_REGISTER_FSW = 257,\r
+ EFI_MM_SAVE_STATE_REGISTER_FTW = 258,\r
+ EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259,\r
+ EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260,\r
+ EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261,\r
+ EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r
+ EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM0 = 264,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM1 = 265,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM2 = 266,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM3 = 267,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM4 = 268,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM5 = 269,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM6 = 270,\r
+ EFI_MM_SAVE_STATE_REGISTER_MM7 = 271,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286,\r
+ EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287,\r
///\r
/// Pseudo-Registers\r
///\r
- EFI_MM_SAVE_STATE_REGISTER_IO = 512,\r
- EFI_MM_SAVE_STATE_REGISTER_LMA = 513,\r
- EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514\r
+ EFI_MM_SAVE_STATE_REGISTER_IO = 512,\r
+ EFI_MM_SAVE_STATE_REGISTER_LMA = 513,\r
+ EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514\r
} EFI_MM_SAVE_STATE_REGISTER;\r
\r
///\r
/// Size width of I/O instruction\r
///\r
typedef enum {\r
- EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r
- EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r
- EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r
- EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r
+ EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r
+ EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r
+ EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r
+ EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r
} EFI_MM_SAVE_STATE_IO_WIDTH;\r
\r
///\r
/// Types of I/O instruction\r
///\r
typedef enum {\r
- EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1,\r
- EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r
- EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4,\r
- EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r
+ EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1,\r
+ EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r
+ EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4,\r
+ EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r
} EFI_MM_SAVE_STATE_IO_TYPE;\r
\r
///\r
EFI_MM_SAVE_STATE_IO_TYPE IoType;\r
} EFI_MM_SAVE_STATE_IO_INFO;\r
\r
-typedef struct _EFI_MM_CPU_PROTOCOL EFI_MM_CPU_PROTOCOL;\r
+typedef struct _EFI_MM_CPU_PROTOCOL EFI_MM_CPU_PROTOCOL;\r
\r
/**\r
Read data from the CPU save state.\r
OUT VOID *Buffer\r
);\r
\r
-\r
/**\r
Write data to the CPU save state.\r
\r
/// format.\r
///\r
struct _EFI_MM_CPU_PROTOCOL {\r
- EFI_MM_READ_SAVE_STATE ReadSaveState;\r
- EFI_MM_WRITE_SAVE_STATE WriteSaveState;\r
+ EFI_MM_READ_SAVE_STATE ReadSaveState;\r
+ EFI_MM_WRITE_SAVE_STATE WriteSaveState;\r
};\r
\r
-extern EFI_GUID gEfiMmCpuProtocolGuid;\r
+extern EFI_GUID gEfiMmCpuProtocolGuid;\r
\r
#endif\r
-\r
0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \\r
}\r
\r
-typedef struct _EFI_MM_CPU_IO_PROTOCOL EFI_MM_CPU_IO_PROTOCOL;\r
+typedef struct _EFI_MM_CPU_IO_PROTOCOL EFI_MM_CPU_IO_PROTOCOL;\r
\r
///\r
/// Width of the MM CPU I/O operations\r
///\r
/// This service provides the various modalities of memory and I/O read.\r
///\r
- EFI_MM_CPU_IO Read;\r
+ EFI_MM_CPU_IO Read;\r
///\r
/// This service provides the various modalities of memory and I/O write.\r
///\r
- EFI_MM_CPU_IO Write;\r
+ EFI_MM_CPU_IO Write;\r
} EFI_MM_IO_ACCESS;\r
\r
///\r
///\r
/// Allows reads and writes to memory-mapped I/O space.\r
///\r
- EFI_MM_IO_ACCESS Mem;\r
+ EFI_MM_IO_ACCESS Mem;\r
///\r
/// Allows reads and writes to I/O space.\r
///\r
- EFI_MM_IO_ACCESS Io;\r
+ EFI_MM_IO_ACCESS Io;\r
};\r
\r
-extern EFI_GUID gEfiMmCpuIoProtocolGuid;\r
+extern EFI_GUID gEfiMmCpuIoProtocolGuid;\r
\r
#endif\r
0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d } \\r
}\r
\r
-extern EFI_GUID gEfiMmEndOfDxeProtocolGuid;\r
+extern EFI_GUID gEfiMmEndOfDxeProtocolGuid;\r
\r
#endif\r
/// 0 corresponds to logical GPI[0]; 1 corresponds to logical GPI[1]; and\r
/// GpiNum of N corresponds to GPI[N], where N can span from 0 to 2^64-1.\r
///\r
- UINT64 GpiNum;\r
+ UINT64 GpiNum;\r
} EFI_MM_GPI_REGISTER_CONTEXT;\r
\r
typedef struct _EFI_MM_GPI_DISPATCH_PROTOCOL EFI_MM_GPI_DISPATCH_PROTOCOL;\r
/// for the General Purpose Input (GPI) MMI source generator.\r
///\r
struct _EFI_MM_GPI_DISPATCH_PROTOCOL {\r
- EFI_MM_GPI_REGISTER Register;\r
- EFI_MM_GPI_UNREGISTER UnRegister;\r
+ EFI_MM_GPI_REGISTER Register;\r
+ EFI_MM_GPI_UNREGISTER UnRegister;\r
///\r
/// Denotes the maximum value of inputs that can have handlers attached.\r
///\r
- UINTN NumSupportedGpis;\r
+ UINTN NumSupportedGpis;\r
};\r
\r
-extern EFI_GUID gEfiMmGpiDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmGpiDispatchProtocolGuid;\r
\r
#endif\r
-\r
/// IO trap event that should invoke the handler\r
///\r
typedef struct {\r
- UINT16 Address;\r
- UINT16 Length;\r
- EFI_MM_IO_TRAP_DISPATCH_TYPE Type;\r
+ UINT16 Address;\r
+ UINT16 Length;\r
+ EFI_MM_IO_TRAP_DISPATCH_TYPE Type;\r
} EFI_MM_IO_TRAP_REGISTER_CONTEXT;\r
\r
///\r
/// IO Trap context structure containing information about the IO trap that occurred\r
///\r
typedef struct {\r
- UINT32 WriteData;\r
+ UINT32 WriteData;\r
} EFI_MM_IO_TRAP_CONTEXT;\r
\r
typedef struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_MM_IO_TRAP_DISPATCH_PROTOCOL;\r
IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL *This,\r
IN EFI_MM_HANDLER_ENTRY_POINT DispatchFunction,\r
IN OUT EFI_MM_IO_TRAP_REGISTER_CONTEXT *RegisterContext,\r
- OUT EFI_HANDLE *DispatchHandle\r
+ OUT EFI_HANDLE *DispatchHandle\r
);\r
\r
/**\r
/// This protocol provides a parent dispatch service for IO trap MMI sources.\r
///\r
struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL {\r
- EFI_MM_IO_TRAP_DISPATCH_REGISTER Register;\r
- EFI_MM_IO_TRAP_DISPATCH_UNREGISTER UnRegister;\r
+ EFI_MM_IO_TRAP_DISPATCH_REGISTER Register;\r
+ EFI_MM_IO_TRAP_DISPATCH_UNREGISTER UnRegister;\r
};\r
\r
-extern EFI_GUID gEfiMmIoTrapDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmIoTrapDispatchProtocolGuid;\r
\r
#endif\r
-\r
//\r
// Revision definition.\r
//\r
-#define EFI_MM_MP_PROTOCOL_REVISION 0x00\r
+#define EFI_MM_MP_PROTOCOL_REVISION 0x00\r
\r
//\r
// Attribute flags\r
//\r
-#define EFI_MM_MP_TIMEOUT_SUPPORTED 0x01\r
+#define EFI_MM_MP_TIMEOUT_SUPPORTED 0x01\r
\r
//\r
// Completion token\r
//\r
-typedef VOID* MM_COMPLETION;\r
+typedef VOID *MM_COMPLETION;\r
\r
typedef struct {\r
- MM_COMPLETION Completion;\r
- EFI_STATUS Status;\r
+ MM_COMPLETION Completion;\r
+ EFI_STATUS Status;\r
} MM_DISPATCH_COMPLETION_TOKEN;\r
\r
-typedef struct _EFI_MM_MP_PROTOCOL EFI_MM_MP_PROTOCOL;\r
+typedef struct _EFI_MM_MP_PROTOCOL EFI_MM_MP_PROTOCOL;\r
\r
/**\r
Service to retrieves the number of logical processor in the platform.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_MM_GET_NUMBER_OF_PROCESSORS) (\r
+(EFIAPI *EFI_MM_GET_NUMBER_OF_PROCESSORS)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
OUT UINTN *NumberOfProcessors\r
-);\r
-\r
+ );\r
\r
/**\r
This service allows the caller to invoke a procedure one of the application processors (AP). This\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_MM_DISPATCH_PROCEDURE) (\r
+(EFIAPI *EFI_MM_DISPATCH_PROCEDURE)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
IN EFI_AP_PROCEDURE2 Procedure,\r
IN UINTN CpuNumber,\r
IN OUT VOID *ProcedureArguments OPTIONAL,\r
IN OUT MM_COMPLETION *Token,\r
IN OUT EFI_STATUS *CPUStatus\r
-);\r
+ );\r
\r
/**\r
This service allows the caller to invoke a procedure on all running application processors (AP)\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_MM_BROADCAST_PROCEDURE) (\r
+(EFIAPI *EFI_MM_BROADCAST_PROCEDURE)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
IN EFI_AP_PROCEDURE2 Procedure,\r
IN UINTN TimeoutInMicroseconds,\r
IN OUT VOID *ProcedureArguments OPTIONAL,\r
IN OUT MM_COMPLETION *Token,\r
IN OUT EFI_STATUS *CPUStatus\r
-);\r
-\r
+ );\r
\r
/**\r
This service allows the caller to set a startup procedure that will be executed when an AP powers\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_MM_SET_STARTUP_PROCEDURE) (\r
+(EFIAPI *EFI_MM_SET_STARTUP_PROCEDURE)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
IN EFI_AP_PROCEDURE Procedure,\r
IN OUT VOID *ProcedureArguments OPTIONAL\r
-);\r
+ );\r
\r
/**\r
When non-blocking execution of a procedure on an AP is invoked with DispatchProcedure,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_CHECK_FOR_PROCEDURE) (\r
+(EFIAPI *EFI_CHECK_FOR_PROCEDURE)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
IN MM_COMPLETION Token\r
-);\r
+ );\r
\r
/**\r
When a non-blocking execution of a procedure on an AP is invoked via DispatchProcedure,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_WAIT_FOR_PROCEDURE) (\r
+(EFIAPI *EFI_WAIT_FOR_PROCEDURE)(\r
IN CONST EFI_MM_MP_PROTOCOL *This,\r
IN MM_COMPLETION Token\r
-);\r
-\r
-\r
+ );\r
\r
///\r
/// The MM MP protocol provides a set of functions to allow execution of procedures on processors that\r
/// have entered MM.\r
///\r
struct _EFI_MM_MP_PROTOCOL {\r
- UINT32 Revision;\r
- UINT32 Attributes;\r
- EFI_MM_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
- EFI_MM_DISPATCH_PROCEDURE DispatchProcedure;\r
- EFI_MM_BROADCAST_PROCEDURE BroadcastProcedure;\r
- EFI_MM_SET_STARTUP_PROCEDURE SetStartupProcedure;\r
- EFI_CHECK_FOR_PROCEDURE CheckForProcedure;\r
- EFI_WAIT_FOR_PROCEDURE WaitForProcedure;\r
+ UINT32 Revision;\r
+ UINT32 Attributes;\r
+ EFI_MM_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
+ EFI_MM_DISPATCH_PROCEDURE DispatchProcedure;\r
+ EFI_MM_BROADCAST_PROCEDURE BroadcastProcedure;\r
+ EFI_MM_SET_STARTUP_PROCEDURE SetStartupProcedure;\r
+ EFI_CHECK_FOR_PROCEDURE CheckForProcedure;\r
+ EFI_WAIT_FOR_PROCEDURE WaitForProcedure;\r
};\r
\r
-extern EFI_GUID gEfiMmMpProtocolGuid;\r
+extern EFI_GUID gEfiMmMpProtocolGuid;\r
\r
#endif\r
/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return\r
/// EFI_UNSUPPORTED.\r
///\r
-typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
+typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
-extern EFI_GUID gEfiMmPciRootBridgeIoProtocolGuid;\r
+extern EFI_GUID gEfiMmPciRootBridgeIoProtocolGuid;\r
\r
#endif\r
-\r
/// The minimum period of time in 100 nanosecond units that the child gets called. The\r
/// child will be called back after a time greater than the time Period.\r
///\r
- UINT64 Period;\r
+ UINT64 Period;\r
///\r
/// The period of time interval between MMIs. Children of this interface should use this\r
/// field when registering for periodic timer intervals when a finer granularity periodic\r
/// MMI is desired.\r
///\r
- UINT64 MmiTickInterval;\r
+ UINT64 MmiTickInterval;\r
} EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT;\r
\r
///\r
/// ElapsedTime is the actual time in 100 nanosecond units elapsed since last called, a\r
/// value of 0 indicates an unknown amount of time.\r
///\r
- UINT64 ElapsedTime;\r
+ UINT64 ElapsedTime;\r
} EFI_MM_PERIODIC_TIMER_CONTEXT;\r
\r
-typedef struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL;\r
+typedef struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL;\r
\r
/**\r
Register a child MMI source dispatch function for MM periodic timer.\r
/// This protocol provides the parent dispatch service for the periodical timer MMI source generator.\r
///\r
struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL {\r
- EFI_MM_PERIODIC_TIMER_REGISTER Register;\r
- EFI_MM_PERIODIC_TIMER_UNREGISTER UnRegister;\r
- EFI_MM_PERIODIC_TIMER_INTERVAL GetNextShorterInterval;\r
+ EFI_MM_PERIODIC_TIMER_REGISTER Register;\r
+ EFI_MM_PERIODIC_TIMER_UNREGISTER UnRegister;\r
+ EFI_MM_PERIODIC_TIMER_INTERVAL GetNextShorterInterval;\r
};\r
\r
-extern EFI_GUID gEfiMmPeriodicTimerDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmPeriodicTimerDispatchProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Designates whether this handler should be invoked upon entry or exit.\r
///\r
- EFI_POWER_BUTTON_PHASE Phase;\r
+ EFI_POWER_BUTTON_PHASE Phase;\r
} EFI_MM_POWER_BUTTON_REGISTER_CONTEXT;\r
\r
typedef struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL;\r
/// This protocol provides the parent dispatch service for the power button MMI source generator.\r
///\r
struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL {\r
- EFI_MM_POWER_BUTTON_REGISTER Register;\r
- EFI_MM_POWER_BUTTON_UNREGISTER UnRegister;\r
+ EFI_MM_POWER_BUTTON_REGISTER Register;\r
+ EFI_MM_POWER_BUTTON_UNREGISTER UnRegister;\r
};\r
\r
-extern EFI_GUID gEfiMmPowerButtonDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmPowerButtonDispatchProtocolGuid;\r
\r
#endif\r
-\r
0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 } \\r
}\r
\r
-extern EFI_GUID gEfiMmReadyToLockProtocolGuid;\r
+extern EFI_GUID gEfiMmReadyToLockProtocolGuid;\r
\r
#endif\r
IN UINT32 Instance,\r
IN EFI_GUID *CallerId,\r
IN EFI_STATUS_CODE_DATA *Data\r
-);\r
+ );\r
\r
/**\r
Register the callback function for ReportStatusCode() notification.\r
EFI_STATUS\r
(EFIAPI *EFI_MM_RSC_HANDLER_REGISTER)(\r
IN EFI_MM_RSC_HANDLER_CALLBACK Callback\r
-);\r
+ );\r
\r
/**\r
Remove a previously registered callback function from the notification list.\r
EFI_STATUS\r
(EFIAPI *EFI_MM_RSC_HANDLER_UNREGISTER)(\r
IN EFI_MM_RSC_HANDLER_CALLBACK Callback\r
-);\r
+ );\r
\r
typedef struct _EFI_MM_RSC_HANDLER_PROTOCOL {\r
EFI_MM_RSC_HANDLER_REGISTER Register;\r
EFI_MM_RSC_HANDLER_UNREGISTER Unregister;\r
} EFI_MM_RSC_HANDLER_PROTOCOL;\r
\r
-extern EFI_GUID gEfiMmRscHandlerProtocolGuid;\r
+extern EFI_GUID gEfiMmRscHandlerProtocolGuid;\r
\r
#endif\r
/// Describes whether the child handler should be invoked upon the entry to the button\r
/// activation or upon exit.\r
///\r
- EFI_STANDBY_BUTTON_PHASE Phase;\r
+ EFI_STANDBY_BUTTON_PHASE Phase;\r
} EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT;\r
\r
typedef struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL;\r
/// button MMI source generator.\r
///\r
struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL {\r
- EFI_MM_STANDBY_BUTTON_REGISTER Register;\r
- EFI_MM_STANDBY_BUTTON_UNREGISTER UnRegister;\r
+ EFI_MM_STANDBY_BUTTON_REGISTER Register;\r
+ EFI_MM_STANDBY_BUTTON_UNREGISTER UnRegister;\r
};\r
\r
-extern EFI_GUID gEfiMmStandbyButtonDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmStandbyButtonDispatchProtocolGuid;\r
\r
#endif\r
-\r
#ifndef _MM_STATUS_CODE_H__\r
#define _MM_STATUS_CODE_H__\r
\r
-\r
#define EFI_MM_STATUS_CODE_PROTOCOL_GUID \\r
{ \\r
0x6afd2b77, 0x98c1, 0x4acd, {0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1} \\r
}\r
\r
-typedef struct _EFI_MM_STATUS_CODE_PROTOCOL EFI_MM_STATUS_CODE_PROTOCOL;\r
+typedef struct _EFI_MM_STATUS_CODE_PROTOCOL EFI_MM_STATUS_CODE_PROTOCOL;\r
\r
/**\r
Service to emit the status code in MM.\r
);\r
\r
struct _EFI_MM_STATUS_CODE_PROTOCOL {\r
- EFI_MM_REPORT_STATUS_CODE ReportStatusCode;\r
+ EFI_MM_REPORT_STATUS_CODE ReportStatusCode;\r
};\r
\r
-extern EFI_GUID gEfiMmStatusCodeProtocolGuid;\r
+extern EFI_GUID gEfiMmStatusCodeProtocolGuid;\r
\r
#endif\r
-\r
/// child registration for each SwMmiInputValue.\r
///\r
typedef struct {\r
- UINTN SwMmiInputValue;\r
+ UINTN SwMmiInputValue;\r
} EFI_MM_SW_REGISTER_CONTEXT;\r
\r
///\r
///\r
/// The 0-based index of the CPU which generated the software MMI.\r
///\r
- UINTN SwMmiCpuIndex;\r
+ UINTN SwMmiCpuIndex;\r
///\r
/// This value corresponds directly to the CommandPort parameter used in the call to Trigger().\r
///\r
- UINT8 CommandPort;\r
+ UINT8 CommandPort;\r
///\r
/// This value corresponds directly to the DataPort parameter used in the call to Trigger().\r
///\r
- UINT8 DataPort;\r
+ UINT8 DataPort;\r
} EFI_MM_SW_CONTEXT;\r
\r
-typedef struct _EFI_MM_SW_DISPATCH_PROTOCOL EFI_MM_SW_DISPATCH_PROTOCOL;\r
+typedef struct _EFI_MM_SW_DISPATCH_PROTOCOL EFI_MM_SW_DISPATCH_PROTOCOL;\r
\r
/**\r
Register a child MMI source dispatch function for the specified software MMI.\r
(EFIAPI *EFI_MM_SW_UNREGISTER)(\r
IN CONST EFI_MM_SW_DISPATCH_PROTOCOL *This,\r
IN EFI_HANDLE DispatchHandle\r
-);\r
+ );\r
\r
///\r
/// Interface structure for the MM Software MMI Dispatch Protocol.\r
/// interrupt in the EFI_MM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue.\r
///\r
struct _EFI_MM_SW_DISPATCH_PROTOCOL {\r
- EFI_MM_SW_REGISTER Register;\r
- EFI_MM_SW_UNREGISTER UnRegister;\r
+ EFI_MM_SW_REGISTER Register;\r
+ EFI_MM_SW_UNREGISTER UnRegister;\r
///\r
/// A read-only field that describes the maximum value that can be used in the\r
/// EFI_MM_SW_DISPATCH_PROTOCOL.Register() service.\r
///\r
- UINTN MaximumSwiValue;\r
+ UINTN MaximumSwiValue;\r
};\r
\r
-extern EFI_GUID gEfiMmSwDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmSwDispatchProtocolGuid;\r
\r
#endif\r
/// The dispatch function's context\r
///\r
typedef struct {\r
- EFI_SLEEP_TYPE Type;\r
- EFI_SLEEP_PHASE Phase;\r
+ EFI_SLEEP_TYPE Type;\r
+ EFI_SLEEP_PHASE Phase;\r
} EFI_MM_SX_REGISTER_CONTEXT;\r
\r
-typedef struct _EFI_MM_SX_DISPATCH_PROTOCOL EFI_MM_SX_DISPATCH_PROTOCOL;\r
+typedef struct _EFI_MM_SX_DISPATCH_PROTOCOL EFI_MM_SX_DISPATCH_PROTOCOL;\r
\r
/**\r
Provides the parent dispatch service for a given Sx source generator.\r
/// respond to sleep state related events.\r
///\r
struct _EFI_MM_SX_DISPATCH_PROTOCOL {\r
- EFI_MM_SX_REGISTER Register;\r
- EFI_MM_SX_UNREGISTER UnRegister;\r
+ EFI_MM_SX_REGISTER Register;\r
+ EFI_MM_SX_UNREGISTER UnRegister;\r
};\r
\r
-extern EFI_GUID gEfiMmSxDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmSxDispatchProtocolGuid;\r
\r
#endif\r
/// emulation event, such as port-trap on the PS/2* keyboard control registers, or to a\r
/// USB wake event, such as resumption from a sleep state.\r
///\r
- EFI_USB_MMI_TYPE Type;\r
+ EFI_USB_MMI_TYPE Type;\r
///\r
/// The device path is part of the context structure and describes the location of the\r
/// particular USB host controller in the system for which this register event will occur.\r
/// This location is important because of the possible integration of several USB host\r
/// controllers in a system.\r
///\r
- EFI_DEVICE_PATH_PROTOCOL *Device;\r
+ EFI_DEVICE_PATH_PROTOCOL *Device;\r
} EFI_MM_USB_REGISTER_CONTEXT;\r
\r
typedef struct _EFI_MM_USB_DISPATCH_PROTOCOL EFI_MM_USB_DISPATCH_PROTOCOL;\r
/// This protocol provides the parent dispatch service for the USB MMI source generator.\r
///\r
struct _EFI_MM_USB_DISPATCH_PROTOCOL {\r
- EFI_MM_USB_REGISTER Register;\r
- EFI_MM_USB_UNREGISTER UnRegister;\r
+ EFI_MM_USB_REGISTER Register;\r
+ EFI_MM_USB_UNREGISTER UnRegister;\r
};\r
\r
-extern EFI_GUID gEfiMmUsbDispatchProtocolGuid;\r
+extern EFI_GUID gEfiMmUsbDispatchProtocolGuid;\r
\r
#endif\r
-\r
#define EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID \\r
{0x1da97072, 0xbddc, 0x4b30, {0x99, 0xf1, 0x72, 0xa0, 0xb5, 0x6f, 0xff, 0x2a} }\r
\r
-extern EFI_GUID gEfiMonotonicCounterArchProtocolGuid;\r
+extern EFI_GUID gEfiMonotonicCounterArchProtocolGuid;\r
\r
#endif\r
///\r
/// Value used in the NumberProcessors parameter of the GetProcessorInfo function\r
///\r
-#define CPU_V2_EXTENDED_TOPOLOGY BIT24\r
+#define CPU_V2_EXTENDED_TOPOLOGY BIT24\r
\r
///\r
/// Forward declaration for the EFI_MP_SERVICES_PROTOCOL.\r
///\r
/// Terminator for a list of failed CPUs returned by StartAllAPs().\r
///\r
-#define END_OF_CPU_LIST 0xffffffff\r
+#define END_OF_CPU_LIST 0xffffffff\r
\r
///\r
/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and\r
/// indicates whether the processor is playing the role of BSP. If the bit is 1,\r
/// then the processor is BSP. Otherwise, it is AP.\r
///\r
-#define PROCESSOR_AS_BSP_BIT 0x00000001\r
+#define PROCESSOR_AS_BSP_BIT 0x00000001\r
\r
///\r
/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and\r
/// indicates whether the processor is enabled. If the bit is 1, then the\r
/// processor is enabled. Otherwise, it is disabled.\r
///\r
-#define PROCESSOR_ENABLED_BIT 0x00000002\r
+#define PROCESSOR_ENABLED_BIT 0x00000002\r
\r
///\r
/// This bit is used in the StatusFlag field of EFI_PROCESSOR_INFORMATION and\r
///\r
/// Zero-based physical package number that identifies the cartridge of the processor.\r
///\r
- UINT32 Package;\r
+ UINT32 Package;\r
///\r
/// Zero-based physical core number within package of the processor.\r
///\r
- UINT32 Core;\r
+ UINT32 Core;\r
///\r
/// Zero-based logical thread number within core of the processor.\r
///\r
- UINT32 Thread;\r
+ UINT32 Thread;\r
} EFI_CPU_PHYSICAL_LOCATION;\r
\r
///\r
/// Structure that defines the 6-level physical location of the processor\r
///\r
typedef struct {\r
-///\r
-/// Package Zero-based physical package number that identifies the cartridge of the processor.\r
-///\r
-UINT32 Package;\r
-///\r
-/// Module Zero-based physical module number within package of the processor.\r
-///\r
-UINT32 Module;\r
-///\r
-/// Tile Zero-based physical tile number within module of the processor.\r
-///\r
-UINT32 Tile;\r
-///\r
-/// Die Zero-based physical die number within tile of the processor.\r
-///\r
-UINT32 Die;\r
-///\r
-/// Core Zero-based physical core number within die of the processor.\r
-///\r
-UINT32 Core;\r
-///\r
-/// Thread Zero-based logical thread number within core of the processor.\r
-///\r
-UINT32 Thread;\r
+ ///\r
+ /// Package Zero-based physical package number that identifies the cartridge of the processor.\r
+ ///\r
+ UINT32 Package;\r
+ ///\r
+ /// Module Zero-based physical module number within package of the processor.\r
+ ///\r
+ UINT32 Module;\r
+ ///\r
+ /// Tile Zero-based physical tile number within module of the processor.\r
+ ///\r
+ UINT32 Tile;\r
+ ///\r
+ /// Die Zero-based physical die number within tile of the processor.\r
+ ///\r
+ UINT32 Die;\r
+ ///\r
+ /// Core Zero-based physical core number within die of the processor.\r
+ ///\r
+ UINT32 Core;\r
+ ///\r
+ /// Thread Zero-based logical thread number within core of the processor.\r
+ ///\r
+ UINT32 Thread;\r
} EFI_CPU_PHYSICAL_LOCATION2;\r
\r
-\r
typedef union {\r
/// The 6-level physical location of the processor, including the\r
/// physical package number that identifies the cartridge, the physical\r
/// module number within package, the physical tile number within the module,\r
/// the physical die number within the tile, the physical core number within\r
/// package, and logical thread number within core.\r
- EFI_CPU_PHYSICAL_LOCATION2 Location2;\r
+ EFI_CPU_PHYSICAL_LOCATION2 Location2;\r
} EXTENDED_PROCESSOR_INFORMATION;\r
\r
-\r
///\r
/// Structure that describes information about a logical CPU.\r
///\r
/// are used, and higher bits are reserved. For IPF, the lower 16 bits contains\r
/// id/eid, and higher bits are reserved.\r
///\r
- UINT64 ProcessorId;\r
+ UINT64 ProcessorId;\r
///\r
/// Flags indicating if the processor is BSP or AP, if the processor is enabled\r
/// or disabled, and if the processor is healthy. Bits 3..31 are reserved and\r
/// 1 1 1 Healthy Enabled BSP.\r
/// </pre>\r
///\r
- UINT32 StatusFlag;\r
+ UINT32 StatusFlag;\r
///\r
/// The physical location of the processor, including the physical package number\r
/// that identifies the cartridge, the physical core number within package, and\r
/// logical thread number within core.\r
///\r
- EFI_CPU_PHYSICAL_LOCATION Location;\r
+ EFI_CPU_PHYSICAL_LOCATION Location;\r
///\r
/// The extended information of the processor. This field is filled only when\r
/// CPU_V2_EXTENDED_TOPOLOGY is set in parameter ProcessorNumber.\r
- EXTENDED_PROCESSOR_INFORMATION ExtendedInformation;\r
+ EXTENDED_PROCESSOR_INFORMATION ExtendedInformation;\r
} EFI_PROCESSOR_INFORMATION;\r
\r
/**\r
/// UEFI images must be aware that the functionality of this protocol may be reduced.\r
///\r
struct _EFI_MP_SERVICES_PROTOCOL {\r
- EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
- EFI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;\r
- EFI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;\r
- EFI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;\r
- EFI_MP_SERVICES_SWITCH_BSP SwitchBSP;\r
- EFI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;\r
- EFI_MP_SERVICES_WHOAMI WhoAmI;\r
+ EFI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;\r
+ EFI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;\r
+ EFI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;\r
+ EFI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;\r
+ EFI_MP_SERVICES_SWITCH_BSP SwitchBSP;\r
+ EFI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;\r
+ EFI_MP_SERVICES_WHOAMI WhoAmI;\r
};\r
\r
-extern EFI_GUID gEfiMpServiceProtocolGuid;\r
+extern EFI_GUID gEfiMpServiceProtocolGuid;\r
\r
#endif\r
0x78247c57, 0x63db, 0x4708, {0x99, 0xc2, 0xa8, 0xb4, 0xa9, 0xa6, 0x1f, 0x6b } \\r
}\r
\r
-typedef struct _EFI_MTFTP4_PROTOCOL EFI_MTFTP4_PROTOCOL;\r
-typedef struct _EFI_MTFTP4_TOKEN EFI_MTFTP4_TOKEN;\r
+typedef struct _EFI_MTFTP4_PROTOCOL EFI_MTFTP4_PROTOCOL;\r
+typedef struct _EFI_MTFTP4_TOKEN EFI_MTFTP4_TOKEN;\r
\r
//\r
-//MTFTP4 packet opcode definition\r
+// MTFTP4 packet opcode definition\r
//\r
-#define EFI_MTFTP4_OPCODE_RRQ 1\r
-#define EFI_MTFTP4_OPCODE_WRQ 2\r
-#define EFI_MTFTP4_OPCODE_DATA 3\r
-#define EFI_MTFTP4_OPCODE_ACK 4\r
-#define EFI_MTFTP4_OPCODE_ERROR 5\r
-#define EFI_MTFTP4_OPCODE_OACK 6\r
-#define EFI_MTFTP4_OPCODE_DIR 7\r
-#define EFI_MTFTP4_OPCODE_DATA8 8\r
-#define EFI_MTFTP4_OPCODE_ACK8 9\r
+#define EFI_MTFTP4_OPCODE_RRQ 1\r
+#define EFI_MTFTP4_OPCODE_WRQ 2\r
+#define EFI_MTFTP4_OPCODE_DATA 3\r
+#define EFI_MTFTP4_OPCODE_ACK 4\r
+#define EFI_MTFTP4_OPCODE_ERROR 5\r
+#define EFI_MTFTP4_OPCODE_OACK 6\r
+#define EFI_MTFTP4_OPCODE_DIR 7\r
+#define EFI_MTFTP4_OPCODE_DATA8 8\r
+#define EFI_MTFTP4_OPCODE_ACK8 9\r
\r
//\r
// MTFTP4 error code definition\r
#pragma pack(1)\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT8 Filename[1];\r
+ UINT16 OpCode;\r
+ UINT8 Filename[1];\r
} EFI_MTFTP4_REQ_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT8 Data[1];\r
+ UINT16 OpCode;\r
+ UINT8 Data[1];\r
} EFI_MTFTP4_OACK_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT16 Block;\r
- UINT8 Data[1];\r
+ UINT16 OpCode;\r
+ UINT16 Block;\r
+ UINT8 Data[1];\r
} EFI_MTFTP4_DATA_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT16 Block[1];\r
+ UINT16 OpCode;\r
+ UINT16 Block[1];\r
} EFI_MTFTP4_ACK_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT64 Block;\r
- UINT8 Data[1];\r
+ UINT16 OpCode;\r
+ UINT64 Block;\r
+ UINT8 Data[1];\r
} EFI_MTFTP4_DATA8_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT64 Block[1];\r
+ UINT16 OpCode;\r
+ UINT64 Block[1];\r
} EFI_MTFTP4_ACK8_HEADER;\r
\r
typedef struct {\r
- UINT16 OpCode;\r
- UINT16 ErrorCode;\r
- UINT8 ErrorMessage[1];\r
+ UINT16 OpCode;\r
+ UINT16 ErrorCode;\r
+ UINT8 ErrorMessage[1];\r
} EFI_MTFTP4_ERROR_HEADER;\r
\r
typedef union {\r
///\r
/// Type of packets as defined by the MTFTPv4 packet opcodes.\r
///\r
- UINT16 OpCode;\r
+ UINT16 OpCode;\r
///\r
/// Read request packet header.\r
///\r
- EFI_MTFTP4_REQ_HEADER Rrq;\r
+ EFI_MTFTP4_REQ_HEADER Rrq;\r
///\r
/// Write request packet header.\r
///\r
- EFI_MTFTP4_REQ_HEADER Wrq;\r
+ EFI_MTFTP4_REQ_HEADER Wrq;\r
///\r
/// Option acknowledge packet header.\r
///\r
- EFI_MTFTP4_OACK_HEADER Oack;\r
+ EFI_MTFTP4_OACK_HEADER Oack;\r
///\r
/// Data packet header.\r
///\r
- EFI_MTFTP4_DATA_HEADER Data;\r
+ EFI_MTFTP4_DATA_HEADER Data;\r
///\r
/// Acknowledgement packet header.\r
///\r
- EFI_MTFTP4_ACK_HEADER Ack;\r
+ EFI_MTFTP4_ACK_HEADER Ack;\r
///\r
/// Data packet header with big block number.\r
///\r
- EFI_MTFTP4_DATA8_HEADER Data8;\r
+ EFI_MTFTP4_DATA8_HEADER Data8;\r
///\r
/// Acknowledgement header with big block num.\r
///\r
- EFI_MTFTP4_ACK8_HEADER Ack8;\r
+ EFI_MTFTP4_ACK8_HEADER Ack8;\r
///\r
/// Error packet header.\r
///\r
- EFI_MTFTP4_ERROR_HEADER Error;\r
+ EFI_MTFTP4_ERROR_HEADER Error;\r
} EFI_MTFTP4_PACKET;\r
\r
#pragma pack()\r
/// MTFTP4 option definition.\r
///\r
typedef struct {\r
- UINT8 *OptionStr;\r
- UINT8 *ValueStr;\r
+ UINT8 *OptionStr;\r
+ UINT8 *ValueStr;\r
} EFI_MTFTP4_OPTION;\r
\r
-\r
typedef struct {\r
- BOOLEAN UseDefaultSetting;\r
- EFI_IPv4_ADDRESS StationIp;\r
- EFI_IPv4_ADDRESS SubnetMask;\r
- UINT16 LocalPort;\r
- EFI_IPv4_ADDRESS GatewayIp;\r
- EFI_IPv4_ADDRESS ServerIp;\r
- UINT16 InitialServerPort;\r
- UINT16 TryCount;\r
- UINT16 TimeoutValue;\r
+ BOOLEAN UseDefaultSetting;\r
+ EFI_IPv4_ADDRESS StationIp;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
+ UINT16 LocalPort;\r
+ EFI_IPv4_ADDRESS GatewayIp;\r
+ EFI_IPv4_ADDRESS ServerIp;\r
+ UINT16 InitialServerPort;\r
+ UINT16 TryCount;\r
+ UINT16 TimeoutValue;\r
} EFI_MTFTP4_CONFIG_DATA;\r
\r
-\r
typedef struct {\r
- EFI_MTFTP4_CONFIG_DATA ConfigData;\r
- UINT8 SupportedOptionCount;\r
- UINT8 **SupportedOptoins;\r
- UINT8 UnsupportedOptionCount;\r
- UINT8 **UnsupportedOptoins;\r
+ EFI_MTFTP4_CONFIG_DATA ConfigData;\r
+ UINT8 SupportedOptionCount;\r
+ UINT8 **SupportedOptoins;\r
+ UINT8 UnsupportedOptionCount;\r
+ UINT8 **UnsupportedOptoins;\r
} EFI_MTFTP4_MODE_DATA;\r
\r
-\r
typedef struct {\r
- EFI_IPv4_ADDRESS GatewayIp;\r
- EFI_IPv4_ADDRESS ServerIp;\r
- UINT16 ServerPort;\r
- UINT16 TryCount;\r
- UINT16 TimeoutValue;\r
+ EFI_IPv4_ADDRESS GatewayIp;\r
+ EFI_IPv4_ADDRESS ServerIp;\r
+ UINT16 ServerPort;\r
+ UINT16 TryCount;\r
+ UINT16 TimeoutValue;\r
} EFI_MTFTP4_OVERRIDE_DATA;\r
\r
//\r
OUT VOID **Buffer\r
);\r
\r
-\r
/**\r
Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device.\r
\r
OUT EFI_MTFTP4_MODE_DATA *ModeData\r
);\r
\r
-\r
/**\r
Initializes, changes, or resets the default operational setting for this\r
EFI MTFTPv4 Protocol driver instance.\r
IN EFI_MTFTP4_CONFIG_DATA *MtftpConfigData OPTIONAL\r
);\r
\r
-\r
/**\r
Gets information about a file from an MTFTPv4 server.\r
\r
OUT EFI_MTFTP4_OPTION **OptionList OPTIONAL\r
);\r
\r
-\r
/**\r
Downloads a file from an MTFTPv4 server.\r
\r
IN EFI_MTFTP4_TOKEN *Token\r
);\r
\r
-\r
-\r
/**\r
Sends a file to an MTFTPv4 server.\r
\r
IN EFI_MTFTP4_TOKEN *Token\r
);\r
\r
-\r
/**\r
Downloads a data file "directory" from an MTFTPv4 server. May be unsupported in some EFI\r
implementations.\r
/// The status that is returned to the caller at the end of the operation\r
/// to indicate whether this operation completed successfully.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// The event that will be signaled when the operation completes. If\r
/// set to NULL, the corresponding function will wait until the read or\r
/// EVT_NOTIFY_SIGNAL. The Task Priority Level (TPL) of\r
/// Event must be lower than or equal to TPL_CALLBACK.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// If not NULL, the data that will be used to override the existing configure data.\r
///\r
- EFI_MTFTP4_OVERRIDE_DATA *OverrideData;\r
+ EFI_MTFTP4_OVERRIDE_DATA *OverrideData;\r
///\r
/// The pointer to the null-terminated ASCII file name string.\r
///\r
- UINT8 *Filename;\r
+ UINT8 *Filename;\r
///\r
/// The pointer to the null-terminated ASCII mode string. If NULL, "octet" is used.\r
///\r
- UINT8 *ModeStr;\r
+ UINT8 *ModeStr;\r
///\r
/// Number of option/value string pairs.\r
///\r
- UINT32 OptionCount;\r
+ UINT32 OptionCount;\r
///\r
/// The pointer to an array of option/value string pairs. Ignored if OptionCount is zero.\r
///\r
- EFI_MTFTP4_OPTION *OptionList;\r
+ EFI_MTFTP4_OPTION *OptionList;\r
///\r
/// The size of the data buffer.\r
///\r
- UINT64 BufferSize;\r
+ UINT64 BufferSize;\r
///\r
/// The pointer to the data buffer. Data that is downloaded from the\r
/// MTFTPv4 server is stored here. Data that is uploaded to the\r
/// MTFTPv4 server is read from here. Ignored if BufferSize is zero.\r
///\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
///\r
/// The pointer to the context that will be used by CheckPacket,\r
/// TimeoutCallback and PacketNeeded.\r
///\r
- VOID *Context;\r
+ VOID *Context;\r
///\r
/// The pointer to the callback function to check the contents of the received packet.\r
///\r
- EFI_MTFTP4_CHECK_PACKET CheckPacket;\r
+ EFI_MTFTP4_CHECK_PACKET CheckPacket;\r
///\r
/// The pointer to the function to be called when a timeout occurs.\r
///\r
- EFI_MTFTP4_TIMEOUT_CALLBACK TimeoutCallback;\r
+ EFI_MTFTP4_TIMEOUT_CALLBACK TimeoutCallback;\r
///\r
/// The pointer to the function to provide the needed packet contents.\r
///\r
- EFI_MTFTP4_PACKET_NEEDED PacketNeeded;\r
+ EFI_MTFTP4_PACKET_NEEDED PacketNeeded;\r
};\r
\r
-extern EFI_GUID gEfiMtftp4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiMtftp4ProtocolGuid;\r
+extern EFI_GUID gEfiMtftp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiMtftp4ProtocolGuid;\r
\r
#endif\r
-\r
#ifndef __EFI_MTFTP6_PROTOCOL_H__\r
#define __EFI_MTFTP6_PROTOCOL_H__\r
\r
-\r
#define EFI_MTFTP6_SERVICE_BINDING_PROTOCOL_GUID \\r
{ \\r
0xd9760ff3, 0x3cca, 0x4267, {0x80, 0xf9, 0x75, 0x27, 0xfa, 0xfa, 0x42, 0x23 } \\r
0xbf0a78ba, 0xec29, 0x49cf, {0xa1, 0xc9, 0x7a, 0xe5, 0x4e, 0xab, 0x6a, 0x51 } \\r
}\r
\r
-typedef struct _EFI_MTFTP6_PROTOCOL EFI_MTFTP6_PROTOCOL;\r
-typedef struct _EFI_MTFTP6_TOKEN EFI_MTFTP6_TOKEN;\r
+typedef struct _EFI_MTFTP6_PROTOCOL EFI_MTFTP6_PROTOCOL;\r
+typedef struct _EFI_MTFTP6_TOKEN EFI_MTFTP6_TOKEN;\r
\r
///\r
/// MTFTP Packet OpCodes\r
///@{\r
-#define EFI_MTFTP6_OPCODE_RRQ 1 ///< The MTFTPv6 packet is a read request.\r
-#define EFI_MTFTP6_OPCODE_WRQ 2 ///< The MTFTPv6 packet is a write request.\r
-#define EFI_MTFTP6_OPCODE_DATA 3 ///< The MTFTPv6 packet is a data packet.\r
-#define EFI_MTFTP6_OPCODE_ACK 4 ///< The MTFTPv6 packet is an acknowledgement packet.\r
-#define EFI_MTFTP6_OPCODE_ERROR 5 ///< The MTFTPv6 packet is an error packet.\r
-#define EFI_MTFTP6_OPCODE_OACK 6 ///< The MTFTPv6 packet is an option acknowledgement packet.\r
-#define EFI_MTFTP6_OPCODE_DIR 7 ///< The MTFTPv6 packet is a directory query packet.\r
-#define EFI_MTFTP6_OPCODE_DATA8 8 ///< The MTFTPv6 packet is a data packet with a big block number.\r
-#define EFI_MTFTP6_OPCODE_ACK8 9 ///< The MTFTPv6 packet is an acknowledgement packet with a big block number.\r
+#define EFI_MTFTP6_OPCODE_RRQ 1 ///< The MTFTPv6 packet is a read request.\r
+#define EFI_MTFTP6_OPCODE_WRQ 2 ///< The MTFTPv6 packet is a write request.\r
+#define EFI_MTFTP6_OPCODE_DATA 3 ///< The MTFTPv6 packet is a data packet.\r
+#define EFI_MTFTP6_OPCODE_ACK 4 ///< The MTFTPv6 packet is an acknowledgement packet.\r
+#define EFI_MTFTP6_OPCODE_ERROR 5 ///< The MTFTPv6 packet is an error packet.\r
+#define EFI_MTFTP6_OPCODE_OACK 6 ///< The MTFTPv6 packet is an option acknowledgement packet.\r
+#define EFI_MTFTP6_OPCODE_DIR 7 ///< The MTFTPv6 packet is a directory query packet.\r
+#define EFI_MTFTP6_OPCODE_DATA8 8 ///< The MTFTPv6 packet is a data packet with a big block number.\r
+#define EFI_MTFTP6_OPCODE_ACK8 9 ///< The MTFTPv6 packet is an acknowledgement packet with a big block number.\r
///@}\r
\r
///\r
///\r
/// The error code is not defined. See the error message in the packet (if any) for details.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_NOT_DEFINED 0\r
+#define EFI_MTFTP6_ERRORCODE_NOT_DEFINED 0\r
///\r
/// The file was not found.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_FILE_NOT_FOUND 1\r
+#define EFI_MTFTP6_ERRORCODE_FILE_NOT_FOUND 1\r
///\r
/// There was an access violation.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_ACCESS_VIOLATION 2\r
+#define EFI_MTFTP6_ERRORCODE_ACCESS_VIOLATION 2\r
///\r
/// The disk was full or its allocation was exceeded.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_DISK_FULL 3\r
+#define EFI_MTFTP6_ERRORCODE_DISK_FULL 3\r
///\r
/// The MTFTPv6 operation was illegal.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION 4\r
+#define EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION 4\r
///\r
/// The transfer ID is unknown.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_UNKNOWN_TRANSFER_ID 5\r
+#define EFI_MTFTP6_ERRORCODE_UNKNOWN_TRANSFER_ID 5\r
///\r
/// The file already exists.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_FILE_ALREADY_EXISTS 6\r
+#define EFI_MTFTP6_ERRORCODE_FILE_ALREADY_EXISTS 6\r
///\r
/// There is no such user.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_NO_SUCH_USER 7\r
+#define EFI_MTFTP6_ERRORCODE_NO_SUCH_USER 7\r
///\r
/// The request has been denied due to option negotiation.\r
///\r
-#define EFI_MTFTP6_ERRORCODE_REQUEST_DENIED 8\r
+#define EFI_MTFTP6_ERRORCODE_REQUEST_DENIED 8\r
///@}\r
\r
#pragma pack(1)\r
/// EFI_MTFTP6_PACKET\r
///\r
typedef union {\r
- UINT16 OpCode; ///< Type of packets as defined by the MTFTPv6 packet opcodes.\r
- EFI_MTFTP6_REQ_HEADER Rrq; ///< Read request packet header.\r
- EFI_MTFTP6_REQ_HEADER Wrq; ///< write request packet header.\r
- EFI_MTFTP6_OACK_HEADER Oack; ///< Option acknowledge packet header.\r
- EFI_MTFTP6_DATA_HEADER Data; ///< Data packet header.\r
- EFI_MTFTP6_ACK_HEADER Ack; ///< Acknowledgement packet header.\r
- EFI_MTFTP6_DATA8_HEADER Data8; ///< Data packet header with big block number.\r
- EFI_MTFTP6_ACK8_HEADER Ack8; ///< Acknowledgement header with big block number.\r
- EFI_MTFTP6_ERROR_HEADER Error; ///< Error packet header.\r
+ UINT16 OpCode; ///< Type of packets as defined by the MTFTPv6 packet opcodes.\r
+ EFI_MTFTP6_REQ_HEADER Rrq; ///< Read request packet header.\r
+ EFI_MTFTP6_REQ_HEADER Wrq; ///< write request packet header.\r
+ EFI_MTFTP6_OACK_HEADER Oack; ///< Option acknowledge packet header.\r
+ EFI_MTFTP6_DATA_HEADER Data; ///< Data packet header.\r
+ EFI_MTFTP6_ACK_HEADER Ack; ///< Acknowledgement packet header.\r
+ EFI_MTFTP6_DATA8_HEADER Data8; ///< Data packet header with big block number.\r
+ EFI_MTFTP6_ACK8_HEADER Ack8; ///< Acknowledgement header with big block number.\r
+ EFI_MTFTP6_ERROR_HEADER Error; ///< Error packet header.\r
} EFI_MTFTP6_PACKET;\r
\r
#pragma pack()\r
/// driver choose a source address. If not zero it must be one of the\r
/// configured IP addresses in the underlying IPv6 driver.\r
///\r
- EFI_IPv6_ADDRESS StationIp;\r
+ EFI_IPv6_ADDRESS StationIp;\r
///\r
/// Local port number. Set to zero to use the automatically assigned port number.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// The IP address of the MTFTPv6 server.\r
///\r
- EFI_IPv6_ADDRESS ServerIp;\r
+ EFI_IPv6_ADDRESS ServerIp;\r
///\r
/// The initial MTFTPv6 server port number. Request packets are\r
/// sent to this port. This number is almost always 69 and using zero\r
/// defaults to 69.\r
- UINT16 InitialServerPort;\r
+ UINT16 InitialServerPort;\r
///\r
/// The number of times to transmit MTFTPv6 request packets and wait for a response.\r
///\r
- UINT16 TryCount;\r
+ UINT16 TryCount;\r
///\r
/// The number of seconds to wait for a response after sending the MTFTPv6 request packet.\r
///\r
- UINT16 TimeoutValue;\r
+ UINT16 TimeoutValue;\r
} EFI_MTFTP6_CONFIG_DATA;\r
\r
///\r
///\r
/// The configuration data of this instance.\r
///\r
- EFI_MTFTP6_CONFIG_DATA ConfigData;\r
+ EFI_MTFTP6_CONFIG_DATA ConfigData;\r
///\r
/// The number of option strings in the following SupportedOptions array.\r
///\r
- UINT8 SupportedOptionCount;\r
+ UINT8 SupportedOptionCount;\r
///\r
/// An array of null-terminated ASCII option strings that are recognized and supported by\r
/// this EFI MTFTPv6 Protocol driver implementation. The buffer is\r
/// read only to the caller and the caller should NOT free the buffer.\r
///\r
- UINT8 **SupportedOptions;\r
+ UINT8 **SupportedOptions;\r
} EFI_MTFTP6_MODE_DATA;\r
\r
///\r
/// IP address of the MTFTPv6 server. If set to all zero, the value that\r
/// was set by the EFI_MTFTP6_PROTOCOL.Configure() function will be used.\r
///\r
- EFI_IPv6_ADDRESS ServerIp;\r
+ EFI_IPv6_ADDRESS ServerIp;\r
///\r
/// MTFTPv6 server port number. If set to zero, it will use the value\r
/// that was set by the EFI_MTFTP6_PROTOCOL.Configure() function.\r
///\r
- UINT16 ServerPort;\r
+ UINT16 ServerPort;\r
///\r
/// Number of times to transmit MTFTPv6 request packets and wait\r
/// for a response. If set to zero, the value that was set by\r
/// theEFI_MTFTP6_PROTOCOL.Configure() function will be used.\r
///\r
- UINT16 TryCount;\r
+ UINT16 TryCount;\r
///\r
/// Number of seconds to wait for a response after sending the\r
/// MTFTPv6 request packet. If set to zero, the value that was set by\r
/// the EFI_MTFTP6_PROTOCOL.Configure() function will be used.\r
///\r
- UINT16 TimeoutValue;\r
+ UINT16 TimeoutValue;\r
} EFI_MTFTP6_OVERRIDE_DATA;\r
\r
///\r
/// EFI_MTFTP6_OPTION\r
///\r
typedef struct {\r
- UINT8 *OptionStr; ///< Pointer to the null-terminated ASCII MTFTPv6 option string.\r
- UINT8 *ValueStr; ///< Pointer to the null-terminated ASCII MTFTPv6 value string.\r
+ UINT8 *OptionStr; ///< Pointer to the null-terminated ASCII MTFTPv6 option string.\r
+ UINT8 *ValueStr; ///< Pointer to the null-terminated ASCII MTFTPv6 value string.\r
} EFI_MTFTP6_OPTION;\r
\r
/**\r
/// to indicate whether this operation completed successfully.\r
/// Defined Status values are listed below.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// The event that will be signaled when the operation completes. If\r
/// set to NULL, the corresponding function will wait until the read or\r
/// write operation finishes. The type of Event must be EVT_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// If not NULL, the data that will be used to override the existing\r
/// configure data.\r
///\r
- EFI_MTFTP6_OVERRIDE_DATA *OverrideData;\r
+ EFI_MTFTP6_OVERRIDE_DATA *OverrideData;\r
///\r
/// Pointer to the null-terminated ASCII file name string.\r
///\r
- UINT8 *Filename;\r
+ UINT8 *Filename;\r
///\r
/// Pointer to the null-terminated ASCII mode string. If NULL, octet is used.\r
///\r
- UINT8 *ModeStr;\r
+ UINT8 *ModeStr;\r
///\r
/// Number of option/value string pairs.\r
///\r
- UINT32 OptionCount;\r
+ UINT32 OptionCount;\r
///\r
/// Pointer to an array of option/value string pairs. Ignored if\r
/// OptionCount is zero. Both a remote server and this driver\r
/// options are unrecognized by this implementation, it is sent to the\r
/// remote server without being changed.\r
///\r
- EFI_MTFTP6_OPTION *OptionList;\r
+ EFI_MTFTP6_OPTION *OptionList;\r
///\r
/// On input, the size, in bytes, of Buffer. On output, the number\r
/// of bytes transferred.\r
///\r
- UINT64 BufferSize;\r
+ UINT64 BufferSize;\r
///\r
/// Pointer to the data buffer. Data that is downloaded from the\r
/// MTFTPv6 server is stored here. Data that is uploaded to the\r
/// MTFTPv6 server is read from here. Ignored if BufferSize is zero.\r
///\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
///\r
/// Pointer to the context that will be used by CheckPacket,\r
/// TimeoutCallback and PacketNeeded.\r
///\r
- VOID *Context;\r
+ VOID *Context;\r
///\r
/// Pointer to the callback function to check the contents of the\r
/// received packet.\r
///\r
- EFI_MTFTP6_CHECK_PACKET CheckPacket;\r
+ EFI_MTFTP6_CHECK_PACKET CheckPacket;\r
///\r
/// Pointer to the function to be called when a timeout occurs.\r
///\r
- EFI_MTFTP6_TIMEOUT_CALLBACK TimeoutCallback;\r
+ EFI_MTFTP6_TIMEOUT_CALLBACK TimeoutCallback;\r
///\r
/// Pointer to the function to provide the needed packet contents.\r
/// Only used in WriteFile() operation.\r
///\r
- EFI_MTFTP6_PACKET_NEEDED PacketNeeded;\r
+ EFI_MTFTP6_PACKET_NEEDED PacketNeeded;\r
};\r
\r
/**\r
(EFIAPI *EFI_MTFTP6_CONFIGURE)(\r
IN EFI_MTFTP6_PROTOCOL *This,\r
IN EFI_MTFTP6_CONFIG_DATA *MtftpConfigData OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Get information about a file from an MTFTPv6 server.\r
IN EFI_MTFTP6_OPTION *OptionList OPTIONAL,\r
OUT UINT32 *PacketLength,\r
OUT EFI_MTFTP6_PACKET **Packet OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Parse the options in an MTFTPv6 OACK packet.\r
(EFIAPI *EFI_MTFTP6_READ_DIRECTORY)(\r
IN EFI_MTFTP6_PROTOCOL *This,\r
IN EFI_MTFTP6_TOKEN *Token\r
-);\r
+ );\r
\r
/**\r
Polls for incoming data packets and processes outgoing data packets.\r
/// driver and EFI IPv6 Protocol driver.\r
///\r
struct _EFI_MTFTP6_PROTOCOL {\r
- EFI_MTFTP6_GET_MODE_DATA GetModeData;\r
- EFI_MTFTP6_CONFIGURE Configure;\r
- EFI_MTFTP6_GET_INFO GetInfo;\r
- EFI_MTFTP6_PARSE_OPTIONS ParseOptions;\r
- EFI_MTFTP6_READ_FILE ReadFile;\r
- EFI_MTFTP6_WRITE_FILE WriteFile;\r
- EFI_MTFTP6_READ_DIRECTORY ReadDirectory;\r
- EFI_MTFTP6_POLL Poll;\r
+ EFI_MTFTP6_GET_MODE_DATA GetModeData;\r
+ EFI_MTFTP6_CONFIGURE Configure;\r
+ EFI_MTFTP6_GET_INFO GetInfo;\r
+ EFI_MTFTP6_PARSE_OPTIONS ParseOptions;\r
+ EFI_MTFTP6_READ_FILE ReadFile;\r
+ EFI_MTFTP6_WRITE_FILE WriteFile;\r
+ EFI_MTFTP6_READ_DIRECTORY ReadDirectory;\r
+ EFI_MTFTP6_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiMtftp6ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiMtftp6ProtocolGuid;\r
+extern EFI_GUID gEfiMtftp6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiMtftp6ProtocolGuid;\r
\r
#endif\r
-\r
//\r
// Revision defined in UEFI Specification 2.4\r
//\r
-#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION 0x00020000\r
-\r
+#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION 0x00020000\r
\r
///\r
/// Revision defined in EFI1.1.\r
///\r
-#define EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE_REVISION EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION\r
+#define EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE_REVISION EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION\r
\r
///\r
/// Forward reference for pure ANSI compatability.\r
///\r
-typedef struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL;\r
+typedef struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL;\r
\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE;\r
+typedef EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL EFI_NETWORK_INTERFACE_IDENTIFIER_INTERFACE;\r
\r
///\r
/// An optional protocol that is used to describe details about the software\r
/// layer that is used to produce the Simple Network Protocol.\r
///\r
struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL {\r
- UINT64 Revision; ///< The revision of the EFI_NETWORK_INTERFACE_IDENTIFIER protocol.\r
- UINT64 Id; ///< The address of the first byte of the identifying structure for this network\r
- ///< interface. This is only valid when the network interface is started\r
- ///< (see Start()). When the network interface is not started, this field is set to zero.\r
- UINT64 ImageAddr; ///< The address of the first byte of the identifying structure for this\r
- ///< network interface. This is set to zero if there is no structure.\r
- UINT32 ImageSize; ///< The size of unrelocated network interface image.\r
- CHAR8 StringId[4];///< A four-character ASCII string that is sent in the class identifier field of\r
- ///< option 60 in DHCP. For a Type of EfiNetworkInterfaceUndi, this field is UNDI.\r
- UINT8 Type; ///< Network interface type. This will be set to one of the values\r
- ///< in EFI_NETWORK_INTERFACE_TYPE.\r
- UINT8 MajorVer; ///< Major version number.\r
- UINT8 MinorVer; ///< Minor version number.\r
- BOOLEAN Ipv6Supported; ///< TRUE if the network interface supports IPv6; otherwise FALSE.\r
- UINT16 IfNum; ///< The network interface number that is being identified by this Network\r
- ///< Interface Identifier Protocol. This field must be less than or\r
- ///< equal to the (IFcnt | IFcntExt <<8 ) fields in the !PXE structure.\r
-\r
+ UINT64 Revision; ///< The revision of the EFI_NETWORK_INTERFACE_IDENTIFIER protocol.\r
+ UINT64 Id; ///< The address of the first byte of the identifying structure for this network\r
+ ///< interface. This is only valid when the network interface is started\r
+ ///< (see Start()). When the network interface is not started, this field is set to zero.\r
+ UINT64 ImageAddr; ///< The address of the first byte of the identifying structure for this\r
+ ///< network interface. This is set to zero if there is no structure.\r
+ UINT32 ImageSize; ///< The size of unrelocated network interface image.\r
+ CHAR8 StringId[4]; ///< A four-character ASCII string that is sent in the class identifier field of\r
+ ///< option 60 in DHCP. For a Type of EfiNetworkInterfaceUndi, this field is UNDI.\r
+ UINT8 Type; ///< Network interface type. This will be set to one of the values\r
+ ///< in EFI_NETWORK_INTERFACE_TYPE.\r
+ UINT8 MajorVer; ///< Major version number.\r
+ UINT8 MinorVer; ///< Minor version number.\r
+ BOOLEAN Ipv6Supported; ///< TRUE if the network interface supports IPv6; otherwise FALSE.\r
+ UINT16 IfNum; ///< The network interface number that is being identified by this Network\r
+ ///< Interface Identifier Protocol. This field must be less than or\r
+ ///< equal to the (IFcnt | IFcntExt <<8 ) fields in the !PXE structure.\r
};\r
\r
///\r
-///*******************************************************\r
+/// *******************************************************\r
/// EFI_NETWORK_INTERFACE_TYPE\r
-///*******************************************************\r
+/// *******************************************************\r
///\r
typedef enum {\r
EfiNetworkInterfaceUndi = 1\r
///\r
/// Forward reference for pure ANSI compatability.\r
///\r
-typedef struct undiconfig_table UNDI_CONFIG_TABLE;\r
+typedef struct undiconfig_table UNDI_CONFIG_TABLE;\r
\r
///\r
/// The format of the configuration table for UNDI\r
///\r
struct undiconfig_table {\r
- UINT32 NumberOfInterfaces; ///< The number of NIC devices\r
+ UINT32 NumberOfInterfaces; ///< The number of NIC devices\r
///< that this UNDI controls.\r
- UINT32 reserved;\r
- UNDI_CONFIG_TABLE *nextlink; ///< A pointer to the next UNDI\r
+ UINT32 reserved;\r
+ UNDI_CONFIG_TABLE *nextlink; ///< A pointer to the next UNDI\r
///< configuration table.\r
///\r
/// The length of this array is given in the NumberOfInterfaces field.\r
///\r
struct {\r
- VOID *NII_InterfacePointer; ///< Pointer to the NII interface structure.\r
- VOID *DevicePathPointer; ///< Pointer to the device path for this NIC.\r
+ VOID *NII_InterfacePointer; ///< Pointer to the NII interface structure.\r
+ VOID *DevicePathPointer; ///< Pointer to the device path for this NIC.\r
} NII_entry[1];\r
};\r
\r
-extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid;\r
-extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid_31;\r
+extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid;\r
+extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid_31;\r
\r
#endif\r
\r
typedef struct _EFI_NVDIMM_LABEL_PROTOCOL EFI_NVDIMM_LABEL_PROTOCOL;\r
\r
-#define EFI_NVDIMM_LABEL_INDEX_SIG_LEN 16\r
-#define EFI_NVDIMM_LABEL_INDEX_ALIGN 256\r
+#define EFI_NVDIMM_LABEL_INDEX_SIG_LEN 16\r
+#define EFI_NVDIMM_LABEL_INDEX_ALIGN 256\r
typedef struct {\r
///\r
/// Signature of the Index Block data structure. Must be "NAMESPACE_INDEX\0".\r
///\r
- CHAR8 Sig[EFI_NVDIMM_LABEL_INDEX_SIG_LEN];\r
+ CHAR8 Sig[EFI_NVDIMM_LABEL_INDEX_SIG_LEN];\r
\r
///\r
/// Attributes of this Label Storage Area.\r
///\r
- UINT8 Flags[3];\r
+ UINT8 Flags[3];\r
\r
///\r
/// Size of each label in bytes, 128 bytes << LabelSize.\r
/// 1 means 256 bytes, 2 means 512 bytes, etc. Shall be 1 or greater.\r
///\r
- UINT8 LabelSize;\r
+ UINT8 LabelSize;\r
\r
///\r
/// Sequence number used to identify which of the two Index Blocks is current.\r
///\r
- UINT32 Seq;\r
+ UINT32 Seq;\r
\r
///\r
/// The offset of this Index Block in the Label Storage Area.\r
///\r
- UINT64 MyOff;\r
+ UINT64 MyOff;\r
\r
///\r
/// The size of this Index Block in bytes.\r
/// This field must be a multiple of the EFI_NVDIMM_LABEL_INDEX_ALIGN.\r
///\r
- UINT64 MySize;\r
+ UINT64 MySize;\r
\r
///\r
/// The offset of the other Index Block paired with this one.\r
///\r
- UINT64 OtherOff;\r
+ UINT64 OtherOff;\r
\r
///\r
/// The offset of the first slot where labels are stored in this Label Storage Area.\r
///\r
- UINT64 LabelOff;\r
+ UINT64 LabelOff;\r
\r
///\r
/// The total number of slots for storing labels in this Label Storage Area.\r
///\r
- UINT32 NSlot;\r
+ UINT32 NSlot;\r
\r
///\r
/// Major version number. Value shall be 1.\r
///\r
- UINT16 Major;\r
+ UINT16 Major;\r
\r
///\r
/// Minor version number. Value shall be 2.\r
///\r
- UINT16 Minor;\r
+ UINT16 Minor;\r
\r
///\r
/// 64-bit Fletcher64 checksum of all fields in this Index Block.\r
///\r
- UINT64 Checksum;\r
+ UINT64 Checksum;\r
\r
///\r
/// Array of unsigned bytes implementing a bitmask that tracks which label slots are free.\r
/// padded with additional zero bytes to make the Index Block size a multiple of EFI_NVDIMM_LABEL_INDEX_ALIGN.\r
/// Any bits allocated beyond NSlot bits must be zero.\r
///\r
- UINT8 Free[];\r
+ UINT8 Free[];\r
} EFI_NVDIMM_LABEL_INDEX_BLOCK;\r
\r
-#define EFI_NVDIMM_LABEL_NAME_LEN 64\r
+#define EFI_NVDIMM_LABEL_NAME_LEN 64\r
\r
///\r
/// The label is read-only.\r
///\r
-#define EFI_NVDIMM_LABEL_FLAGS_ROLABEL 0x00000001\r
+#define EFI_NVDIMM_LABEL_FLAGS_ROLABEL 0x00000001\r
\r
///\r
/// When set, the complete label set is local to a single NVDIMM Label Storage Area.\r
/// When clear, the complete label set is contained on multiple NVDIMM Label Storage Areas.\r
///\r
-#define EFI_NVDIMM_LABEL_FLAGS_LOCAL 0x00000002\r
+#define EFI_NVDIMM_LABEL_FLAGS_LOCAL 0x00000002\r
\r
///\r
/// This reserved flag is utilized on older implementations and has been deprecated.\r
/// Do not use.\r
//\r
-#define EFI_NVDIMM_LABEL_FLAGS_RESERVED 0x00000004\r
+#define EFI_NVDIMM_LABEL_FLAGS_RESERVED 0x00000004\r
\r
///\r
/// When set, the label set is being updated.\r
///\r
-#define EFI_NVDIMM_LABEL_FLAGS_UPDATING 0x00000008\r
+#define EFI_NVDIMM_LABEL_FLAGS_UPDATING 0x00000008\r
\r
typedef struct {\r
///\r
/// Unique Label Identifier UUID per RFC 4122.\r
///\r
- EFI_GUID Uuid;\r
+ EFI_GUID Uuid;\r
\r
///\r
/// NULL-terminated string using UTF-8 character formatting.\r
///\r
- CHAR8 Name[EFI_NVDIMM_LABEL_NAME_LEN];\r
+ CHAR8 Name[EFI_NVDIMM_LABEL_NAME_LEN];\r
\r
///\r
/// Attributes of this namespace.\r
///\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
\r
///\r
/// Total number of labels describing this namespace.\r
///\r
- UINT16 NLabel;\r
+ UINT16 NLabel;\r
\r
///\r
/// Position of this label in list of labels for this namespace.\r
///\r
- UINT16 Position;\r
+ UINT16 Position;\r
\r
///\r
/// The SetCookie is utilized by SW to perform consistency checks on the Interleave Set to verify the current\r
/// physical device configuration matches the original physical configuration when the labels were created\r
/// for the set.The label is considered invalid if the actual label set cookie doesn't match the cookie stored here.\r
///\r
- UINT64 SetCookie;\r
+ UINT64 SetCookie;\r
\r
///\r
/// This is the default logical block size in bytes and may be superseded by a block size that is specified\r
/// in the AbstractionGuid.\r
///\r
- UINT64 LbaSize;\r
+ UINT64 LbaSize;\r
\r
///\r
/// The DPA is the DIMM Physical address where the NVM contributing to this namespace begins on this NVDIMM.\r
///\r
- UINT64 Dpa;\r
+ UINT64 Dpa;\r
\r
///\r
/// The extent of the DPA contributed by this label.\r
///\r
- UINT64 RawSize;\r
+ UINT64 RawSize;\r
\r
///\r
/// Current slot in the Label Storage Area where this label is stored.\r
///\r
- UINT32 Slot;\r
+ UINT32 Slot;\r
\r
///\r
/// Alignment hint used to advertise the preferred alignment of the data from within the namespace defined by this label.\r
///\r
- UINT8 Alignment;\r
+ UINT8 Alignment;\r
\r
///\r
/// Shall be 0.\r
///\r
- UINT8 Reserved[3];\r
+ UINT8 Reserved[3];\r
\r
///\r
/// Range Type GUID that describes the access mechanism for the specified DPA range.\r
///\r
- EFI_GUID TypeGuid;\r
+ EFI_GUID TypeGuid;\r
\r
///\r
/// Identifies the address abstraction mechanism for this namespace. A value of 0 indicates no mechanism used.\r
///\r
- EFI_GUID AddressAbstractionGuid;\r
+ EFI_GUID AddressAbstractionGuid;\r
\r
///\r
/// Shall be 0.\r
///\r
- UINT8 Reserved1[88];\r
+ UINT8 Reserved1[88];\r
\r
///\r
/// 64-bit Fletcher64 checksum of all fields in this Label.\r
/// This field is considered zero when the checksum is computed.\r
///\r
- UINT64 Checksum;\r
+ UINT64 Checksum;\r
} EFI_NVDIMM_LABEL;\r
\r
typedef struct {\r
///\r
/// The Region Offset field from the ACPI NFIT NVDIMM Region Mapping Structure for a given entry.\r
///\r
- UINT64 RegionOffset;\r
+ UINT64 RegionOffset;\r
\r
///\r
/// The serial number of the NVDIMM, assigned by the module vendor.\r
///\r
- UINT32 SerialNumber;\r
+ UINT32 SerialNumber;\r
\r
///\r
/// The identifier indicating the vendor of the NVDIMM.\r
///\r
- UINT16 VendorId;\r
+ UINT16 VendorId;\r
\r
///\r
/// The manufacturing date of the NVDIMM, assigned by the module vendor.\r
///\r
- UINT16 ManufacturingDate;\r
+ UINT16 ManufacturingDate;\r
\r
///\r
/// The manufacturing location from for the NVDIMM, assigned by the module vendor.\r
///\r
- UINT8 ManufacturingLocation;\r
+ UINT8 ManufacturingLocation;\r
\r
///\r
/// Shall be 0.\r
///\r
- UINT8 Reserved[31];\r
+ UINT8 Reserved[31];\r
} EFI_NVDIMM_LABEL_SET_COOKIE_MAP;\r
\r
typedef struct {\r
///\r
/// Array size is 1 if EFI_NVDIMM_LABEL_FLAGS_LOCAL is set indicating a Local Namespaces.\r
///\r
- EFI_NVDIMM_LABEL_SET_COOKIE_MAP Mapping[0];\r
+ EFI_NVDIMM_LABEL_SET_COOKIE_MAP Mapping[0];\r
} EFI_NVDIMM_LABEL_SET_COOKIE_INFO;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_INFORMATION) (\r
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_INFORMATION)(\r
IN EFI_NVDIMM_LABEL_PROTOCOL *This,\r
OUT UINT32 *SizeOfLabelStorageArea,\r
OUT UINT32 *MaxTransferLength\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_READ) (\r
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_READ)(\r
IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This,\r
IN UINT32 Offset,\r
IN UINT32 TransferLength,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_WRITE) (\r
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_WRITE)(\r
IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This,\r
IN UINT32 Offset,\r
IN UINT32 TransferLength,\r
/// Provides services that allow management of labels contained in a Label Storage Area.\r
///\r
struct _EFI_NVDIMM_LABEL_PROTOCOL {\r
- EFI_NVDIMM_LABEL_STORAGE_INFORMATION LabelStorageInformation;\r
- EFI_NVDIMM_LABEL_STORAGE_READ LabelStorageRead;\r
- EFI_NVDIMM_LABEL_STORAGE_WRITE LabelStorageWrite;\r
+ EFI_NVDIMM_LABEL_STORAGE_INFORMATION LabelStorageInformation;\r
+ EFI_NVDIMM_LABEL_STORAGE_READ LabelStorageRead;\r
+ EFI_NVDIMM_LABEL_STORAGE_WRITE LabelStorageWrite;\r
};\r
\r
-extern EFI_GUID gEfiNvdimmLabelProtocolGuid;\r
+extern EFI_GUID gEfiNvdimmLabelProtocolGuid;\r
\r
#endif\r
typedef struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL;\r
\r
typedef struct {\r
- UINT32 Attributes;\r
- UINT32 IoAlign;\r
- UINT32 NvmeVersion;\r
+ UINT32 Attributes;\r
+ UINT32 IoAlign;\r
+ UINT32 NvmeVersion;\r
} EFI_NVM_EXPRESS_PASS_THRU_MODE;\r
\r
//\r
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is\r
// for directly addressable namespaces.\r
//\r
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
//\r
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface is\r
// for a single volume logical namespace comprised of multiple namespaces.\r
//\r
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
//\r
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface\r
// supports non-blocking I/O.\r
//\r
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
//\r
// If this bit is set, then the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface\r
// supports NVM command set.\r
//\r
-#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008\r
+#define EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_CMD_SET_NVM 0x0008\r
\r
//\r
// FusedOperation\r
//\r
-#define NORMAL_CMD 0x00\r
-#define FUSED_FIRST_CMD 0x01\r
-#define FUSED_SECOND_CMD 0x02\r
+#define NORMAL_CMD 0x00\r
+#define FUSED_FIRST_CMD 0x01\r
+#define FUSED_SECOND_CMD 0x02\r
\r
typedef struct {\r
- UINT32 Opcode:8;\r
- UINT32 FusedOperation:2;\r
- UINT32 Reserved:22;\r
+ UINT32 Opcode : 8;\r
+ UINT32 FusedOperation : 2;\r
+ UINT32 Reserved : 22;\r
} NVME_CDW0;\r
\r
//\r
// Flags\r
//\r
-#define CDW2_VALID 0x01\r
-#define CDW3_VALID 0x02\r
-#define CDW10_VALID 0x04\r
-#define CDW11_VALID 0x08\r
-#define CDW12_VALID 0x10\r
-#define CDW13_VALID 0x20\r
-#define CDW14_VALID 0x40\r
-#define CDW15_VALID 0x80\r
+#define CDW2_VALID 0x01\r
+#define CDW3_VALID 0x02\r
+#define CDW10_VALID 0x04\r
+#define CDW11_VALID 0x08\r
+#define CDW12_VALID 0x10\r
+#define CDW13_VALID 0x20\r
+#define CDW14_VALID 0x40\r
+#define CDW15_VALID 0x80\r
\r
//\r
// Queue Type\r
//\r
-#define NVME_ADMIN_QUEUE 0x00\r
-#define NVME_IO_QUEUE 0x01\r
+#define NVME_ADMIN_QUEUE 0x00\r
+#define NVME_IO_QUEUE 0x01\r
\r
typedef struct {\r
- NVME_CDW0 Cdw0;\r
- UINT8 Flags;\r
- UINT32 Nsid;\r
- UINT32 Cdw2;\r
- UINT32 Cdw3;\r
- UINT32 Cdw10;\r
- UINT32 Cdw11;\r
- UINT32 Cdw12;\r
- UINT32 Cdw13;\r
- UINT32 Cdw14;\r
- UINT32 Cdw15;\r
+ NVME_CDW0 Cdw0;\r
+ UINT8 Flags;\r
+ UINT32 Nsid;\r
+ UINT32 Cdw2;\r
+ UINT32 Cdw3;\r
+ UINT32 Cdw10;\r
+ UINT32 Cdw11;\r
+ UINT32 Cdw12;\r
+ UINT32 Cdw13;\r
+ UINT32 Cdw14;\r
+ UINT32 Cdw15;\r
} EFI_NVM_EXPRESS_COMMAND;\r
\r
typedef struct {\r
- UINT32 DW0;\r
- UINT32 DW1;\r
- UINT32 DW2;\r
- UINT32 DW3;\r
+ UINT32 DW0;\r
+ UINT32 DW1;\r
+ UINT32 DW2;\r
+ UINT32 DW3;\r
} EFI_NVM_EXPRESS_COMPLETION;\r
\r
typedef struct {\r
- UINT64 CommandTimeout;\r
- VOID *TransferBuffer;\r
- UINT32 TransferLength;\r
- VOID *MetadataBuffer;\r
- UINT32 MetadataLength;\r
- UINT8 QueueType;\r
- EFI_NVM_EXPRESS_COMMAND *NvmeCmd;\r
- EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion;\r
+ UINT64 CommandTimeout;\r
+ VOID *TransferBuffer;\r
+ UINT32 TransferLength;\r
+ VOID *MetadataBuffer;\r
+ UINT32 MetadataLength;\r
+ UINT8 QueueType;\r
+ EFI_NVM_EXPRESS_COMMAND *NvmeCmd;\r
+ EFI_NVM_EXPRESS_COMPLETION *NvmeCompletion;\r
} EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;\r
\r
//\r
// Protocol function prototypes\r
//\r
+\r
/**\r
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r
both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r
(EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE)(\r
IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- OUT UINT32 *NamespaceId\r
+ OUT UINT32 *NamespaceId\r
);\r
\r
//\r
// Protocol Interface Structure\r
//\r
struct _EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL {\r
- EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode;\r
- EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru;\r
- EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace;\r
- EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
- EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace;\r
+ EFI_NVM_EXPRESS_PASS_THRU_MODE *Mode;\r
+ EFI_NVM_EXPRESS_PASS_THRU_PASSTHRU PassThru;\r
+ EFI_NVM_EXPRESS_PASS_THRU_GET_NEXT_NAMESPACE GetNextNamespace;\r
+ EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
+ EFI_NVM_EXPRESS_PASS_THRU_GET_NAMESPACE GetNamespace;\r
};\r
\r
-extern EFI_GUID gEfiNvmExpressPassThruProtocolGuid;\r
+extern EFI_GUID gEfiNvmExpressPassThruProtocolGuid;\r
\r
#endif\r
-\r
#define EFI_PARTITION_INFO_PROTOCOL_GUID \\r
{ 0x8cf2f62c, 0xbc9b, 0x4821, { 0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0 }};\r
\r
-\r
-#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000\r
-#define PARTITION_TYPE_OTHER 0x00\r
-#define PARTITION_TYPE_MBR 0x01\r
-#define PARTITION_TYPE_GPT 0x02\r
+#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000\r
+#define PARTITION_TYPE_OTHER 0x00\r
+#define PARTITION_TYPE_MBR 0x01\r
+#define PARTITION_TYPE_GPT 0x02\r
\r
#pragma pack(1)\r
\r
//\r
// Set to EFI_PARTITION_INFO_PROTOCOL_REVISION.\r
//\r
- UINT32 Revision;\r
+ UINT32 Revision;\r
//\r
// Partition info type (PARTITION_TYPE_MBR, PARTITION_TYPE_GPT, or PARTITION_TYPE_OTHER).\r
//\r
- UINT32 Type;\r
+ UINT32 Type;\r
//\r
// If 1, partition describes an EFI System Partition.\r
//\r
- UINT8 System;\r
- UINT8 Reserved[7];\r
+ UINT8 System;\r
+ UINT8 Reserved[7];\r
union {\r
///\r
/// MBR data\r
///\r
- MBR_PARTITION_RECORD Mbr;\r
+ MBR_PARTITION_RECORD Mbr;\r
///\r
/// GPT data\r
///\r
- EFI_PARTITION_ENTRY Gpt;\r
+ EFI_PARTITION_ENTRY Gpt;\r
} Info;\r
} EFI_PARTITION_INFO_PROTOCOL;\r
\r
///\r
/// Partition Information Protocol GUID variable.\r
///\r
-extern EFI_GUID gEfiPartitionInfoProtocolGuid;\r
+extern EFI_GUID gEfiPartitionInfoProtocolGuid;\r
\r
#endif\r
#ifndef __PCD_H__\r
#define __PCD_H__\r
\r
-extern EFI_GUID gPcdProtocolGuid;\r
+extern EFI_GUID gPcdProtocolGuid;\r
\r
#define PCD_PROTOCOL_GUID \\r
{ 0x11b34006, 0xd85b, 0x4d0a, { 0xa2, 0x90, 0xd5, 0xa5, 0x71, 0x31, 0xe, 0xf7 } }\r
\r
-#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
-\r
+#define PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
\r
/**\r
Sets the SKU value for subsequent calls to set or get PCD token values.\r
IN UINTN SkuId\r
);\r
\r
-\r
-\r
/**\r
Retrieves an 8-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 16-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 32-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 64-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a pointer to a value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a Boolean value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the size of the value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves an 8-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 16-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a 32-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves an 64-bit value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a pointer to a value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves a Boolean value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the size of the value for a given PCD token.\r
\r
IN UINTN TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Sets an 8-bit value for a given PCD token.\r
\r
IN UINT8 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 16-bit value for a given PCD token.\r
\r
IN UINT16 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 32-bit value for a given PCD token.\r
\r
IN UINT32 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 64-bit value for a given PCD token.\r
\r
IN UINT64 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a value of a specified size for a given PCD token.\r
\r
IN VOID *Buffer\r
);\r
\r
-\r
-\r
/**\r
Sets a Boolean value for a given PCD token.\r
\r
IN BOOLEAN Value\r
);\r
\r
-\r
-\r
/**\r
Sets an 8-bit value for a given PCD token.\r
\r
IN UINT8 Value\r
);\r
\r
-\r
-\r
/**\r
Sets an 16-bit value for a given PCD token.\r
\r
IN UINT16 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 32-bit value for a given PCD token.\r
\r
IN UINT32 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a 64-bit value for a given PCD token.\r
\r
IN UINT64 Value\r
);\r
\r
-\r
-\r
/**\r
Sets a value of a specified size for a given PCD token.\r
\r
IN VOID *Buffer\r
);\r
\r
-\r
-\r
/**\r
Sets a Boolean value for a given PCD token.\r
\r
IN BOOLEAN Value\r
);\r
\r
-\r
-\r
/**\r
Callback on SET function prototype definition.\r
\r
IN UINTN TokenDataSize\r
);\r
\r
-\r
-\r
/**\r
Specifies a function to be called anytime the value of a designated token is changed.\r
\r
IN PCD_PROTOCOL_CALLBACK CallBackFunction\r
);\r
\r
-\r
-\r
/**\r
Cancels a previously set callback function for a particular PCD token number.\r
\r
IN PCD_PROTOCOL_CALLBACK CallBackFunction\r
);\r
\r
-\r
-\r
/**\r
Retrieves the next valid token number in a given namespace.\r
\r
IN OUT UINTN *TokenNumber\r
);\r
\r
-\r
-\r
/**\r
Retrieves the next valid PCD token namespace for a given namespace.\r
\r
/// This service abstracts the ability to set/get Platform Configuration Database (PCD).\r
///\r
typedef struct {\r
- PCD_PROTOCOL_SET_SKU SetSku;\r
-\r
- PCD_PROTOCOL_GET8 Get8;\r
- PCD_PROTOCOL_GET16 Get16;\r
- PCD_PROTOCOL_GET32 Get32;\r
- PCD_PROTOCOL_GET64 Get64;\r
- PCD_PROTOCOL_GET_POINTER GetPtr;\r
- PCD_PROTOCOL_GET_BOOLEAN GetBool;\r
- PCD_PROTOCOL_GET_SIZE GetSize;\r
-\r
- PCD_PROTOCOL_GET_EX_8 Get8Ex;\r
- PCD_PROTOCOL_GET_EX_16 Get16Ex;\r
- PCD_PROTOCOL_GET_EX_32 Get32Ex;\r
- PCD_PROTOCOL_GET_EX_64 Get64Ex;\r
- PCD_PROTOCOL_GET_EX_POINTER GetPtrEx;\r
- PCD_PROTOCOL_GET_EX_BOOLEAN GetBoolEx;\r
- PCD_PROTOCOL_GET_EX_SIZE GetSizeEx;\r
-\r
- PCD_PROTOCOL_SET8 Set8;\r
- PCD_PROTOCOL_SET16 Set16;\r
- PCD_PROTOCOL_SET32 Set32;\r
- PCD_PROTOCOL_SET64 Set64;\r
- PCD_PROTOCOL_SET_POINTER SetPtr;\r
- PCD_PROTOCOL_SET_BOOLEAN SetBool;\r
-\r
- PCD_PROTOCOL_SET_EX_8 Set8Ex;\r
- PCD_PROTOCOL_SET_EX_16 Set16Ex;\r
- PCD_PROTOCOL_SET_EX_32 Set32Ex;\r
- PCD_PROTOCOL_SET_EX_64 Set64Ex;\r
- PCD_PROTOCOL_SET_EX_POINTER SetPtrEx;\r
- PCD_PROTOCOL_SET_EX_BOOLEAN SetBoolEx;\r
-\r
- PCD_PROTOCOL_CALLBACK_ONSET CallbackOnSet;\r
- PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback;\r
- PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken;\r
- PCD_PROTOCOL_GET_NEXT_TOKENSPACE GetNextTokenSpace;\r
+ PCD_PROTOCOL_SET_SKU SetSku;\r
+\r
+ PCD_PROTOCOL_GET8 Get8;\r
+ PCD_PROTOCOL_GET16 Get16;\r
+ PCD_PROTOCOL_GET32 Get32;\r
+ PCD_PROTOCOL_GET64 Get64;\r
+ PCD_PROTOCOL_GET_POINTER GetPtr;\r
+ PCD_PROTOCOL_GET_BOOLEAN GetBool;\r
+ PCD_PROTOCOL_GET_SIZE GetSize;\r
+\r
+ PCD_PROTOCOL_GET_EX_8 Get8Ex;\r
+ PCD_PROTOCOL_GET_EX_16 Get16Ex;\r
+ PCD_PROTOCOL_GET_EX_32 Get32Ex;\r
+ PCD_PROTOCOL_GET_EX_64 Get64Ex;\r
+ PCD_PROTOCOL_GET_EX_POINTER GetPtrEx;\r
+ PCD_PROTOCOL_GET_EX_BOOLEAN GetBoolEx;\r
+ PCD_PROTOCOL_GET_EX_SIZE GetSizeEx;\r
+\r
+ PCD_PROTOCOL_SET8 Set8;\r
+ PCD_PROTOCOL_SET16 Set16;\r
+ PCD_PROTOCOL_SET32 Set32;\r
+ PCD_PROTOCOL_SET64 Set64;\r
+ PCD_PROTOCOL_SET_POINTER SetPtr;\r
+ PCD_PROTOCOL_SET_BOOLEAN SetBool;\r
+\r
+ PCD_PROTOCOL_SET_EX_8 Set8Ex;\r
+ PCD_PROTOCOL_SET_EX_16 Set16Ex;\r
+ PCD_PROTOCOL_SET_EX_32 Set32Ex;\r
+ PCD_PROTOCOL_SET_EX_64 Set64Ex;\r
+ PCD_PROTOCOL_SET_EX_POINTER SetPtrEx;\r
+ PCD_PROTOCOL_SET_EX_BOOLEAN SetBoolEx;\r
+\r
+ PCD_PROTOCOL_CALLBACK_ONSET CallbackOnSet;\r
+ PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback;\r
+ PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken;\r
+ PCD_PROTOCOL_GET_NEXT_TOKENSPACE GetNextTokenSpace;\r
} PCD_PROTOCOL;\r
\r
#endif\r
#ifndef __PCD_INFO_H__\r
#define __PCD_INFO_H__\r
\r
-extern EFI_GUID gGetPcdInfoProtocolGuid;\r
+extern EFI_GUID gGetPcdInfoProtocolGuid;\r
\r
#define GET_PCD_INFO_PROTOCOL_GUID \\r
{ 0x5be40f57, 0xfa68, 0x4610, { 0xbb, 0xbf, 0xe9, 0xc5, 0xfc, 0xda, 0xd3, 0x65 } }\r
///\r
/// The forward declaration for GET_PCD_INFO_PROTOCOL.\r
///\r
-typedef struct _GET_PCD_INFO_PROTOCOL GET_PCD_INFO_PROTOCOL;\r
+typedef struct _GET_PCD_INFO_PROTOCOL GET_PCD_INFO_PROTOCOL;\r
\r
/**\r
Retrieve additional information associated with a PCD token.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO) (\r
+(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO)(\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve additional information associated with a PCD token.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO_EX) (\r
+(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_INFO_EX)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve the currently set SKU Id.\r
**/\r
typedef\r
UINTN\r
-(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_SKU) (\r
+(EFIAPI *GET_PCD_INFO_PROTOCOL_GET_SKU)(\r
VOID\r
-);\r
+ );\r
\r
///\r
/// This is the PCD service to use when querying for some additional data that can be contained in the\r
///\r
/// Retrieve additional information associated with a PCD.\r
///\r
- GET_PCD_INFO_PROTOCOL_GET_INFO GetInfo;\r
- GET_PCD_INFO_PROTOCOL_GET_INFO_EX GetInfoEx;\r
+ GET_PCD_INFO_PROTOCOL_GET_INFO GetInfo;\r
+ GET_PCD_INFO_PROTOCOL_GET_INFO_EX GetInfoEx;\r
///\r
/// Retrieve the currently set SKU Id.\r
///\r
- GET_PCD_INFO_PROTOCOL_GET_SKU GetSku;\r
+ GET_PCD_INFO_PROTOCOL_GET_SKU GetSku;\r
};\r
\r
#endif\r
-\r
0x30cfe3e7, 0x3de1, 0x4586, { 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93 } \\r
}\r
\r
-extern EFI_GUID gEfiPciEnumerationCompleteProtocolGuid;\r
+extern EFI_GUID gEfiPciEnumerationCompleteProtocolGuid;\r
\r
#endif\r
/// the PCI bus driver needs to include requests for 64 bit\r
/// memory address in the corresponding 32 bit memory pool.\r
///\r
-#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
+#define EFI_PCI_HOST_BRIDGE_MEM64_DECODE 2\r
\r
///\r
/// A UINT64 value that contains the status of a PCI resource requested\r
/// Configuration parameter returned by GetProposedResources() to identify\r
/// a PCI resources request that can be satisfied.\r
///\r
-#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL\r
\r
///\r
/// The request of this resource type could not be fulfilled for its\r
/// The notification from the PCI bus enumerator that it is about to enter\r
/// a certain phase during the enumeration process.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE NotifyPhase;\r
\r
///\r
/// Retrieves the device handle for the next PCI root bridge that is produced by the\r
/// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE GetNextRootBridge;\r
\r
///\r
/// Retrieves the allocation-related attributes of a PCI root bridge.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES GetAllocAttributes;\r
\r
///\r
/// Sets up a PCI root bridge for bus enumeration.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION StartBusEnumeration;\r
\r
///\r
/// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS SetBusNumbers;\r
\r
///\r
/// Submits the resource requirements for the specified PCI root bridge.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES SubmitResources;\r
\r
///\r
/// Returns the proposed resource assignment for the specified PCI root bridges.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;\r
\r
///\r
/// Provides hooks from the PCI bus driver to every PCI controller\r
/// allow the host bridge driver to preinitialize individual PCI controllers\r
/// before enumeration.\r
///\r
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER PreprocessController;\r
};\r
\r
-extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
+extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid;\r
\r
#endif\r
/// disabled in hardware, or it may be disabled due to user preferences,\r
/// hardware failure, or other reasons. No resource padding is required.\r
///\r
-#define EFI_HPC_STATE_INITIALIZED 0x01\r
+#define EFI_HPC_STATE_INITIALIZED 0x01\r
\r
///\r
/// The HPC initialization function was called, the HPC completed\r
/// initialization, and it was enabled. Resource padding is required.\r
///\r
-#define EFI_HPC_STATE_ENABLED 0x02\r
+#define EFI_HPC_STATE_ENABLED 0x02\r
\r
///\r
/// Location definition for PCI Hot Plug Controller\r
///\r
-typedef struct{\r
+typedef struct {\r
///\r
///\r
/// The device path to the root HPC. An HPC cannot control its parent buses.\r
/// correct HpcPciAddress to the InitializeRootHpc() and GetResourcePadding()\r
/// functions.\r
///\r
- EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath;\r
///\r
/// The device path to the Hot Plug Bus (HPB) that is controlled by the root\r
/// HPC. The PCI bus driver uses this information to check if a particular PCI\r
/// device path of its parent. For Standard(PCI) Hot Plug Controllers (SHPCs)\r
/// and PCI Express*, HpbDevicePath is the same as HpcDevicePath.\r
///\r
- EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *HpbDevicePath;\r
} EFI_HPC_LOCATION;\r
\r
///\r
///\r
/// Returns a list of root HPCs and the buses that they control.\r
///\r
- EFI_GET_ROOT_HPC_LIST GetRootHpcList;\r
+ EFI_GET_ROOT_HPC_LIST GetRootHpcList;\r
\r
///\r
/// Initializes the specified root HPC.\r
///\r
- EFI_INITIALIZE_ROOT_HPC InitializeRootHpc;\r
+ EFI_INITIALIZE_ROOT_HPC InitializeRootHpc;\r
\r
///\r
/// Returns the resource padding that is required by the HPC.\r
///\r
- EFI_GET_HOT_PLUG_PADDING GetResourcePadding;\r
+ EFI_GET_HOT_PLUG_PADDING GetResourcePadding;\r
};\r
\r
-extern EFI_GUID gEfiPciHotPlugInitProtocolGuid;\r
+extern EFI_GUID gEfiPciHotPlugInitProtocolGuid;\r
\r
#endif\r
///\r
/// Forward declaration for EFI_PCI_HOTPLUG_REQUEST_PROTOCOL\r
///\r
-typedef struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL EFI_PCI_HOTPLUG_REQUEST_PROTOCOL;\r
+typedef struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL EFI_PCI_HOTPLUG_REQUEST_PROTOCOL;\r
\r
///\r
/// Enumeration of PCI hot plug operations\r
/// to create or destroy handles for the PCI-like devices. See Section 0 for\r
/// a detailed description.\r
///\r
- EFI_PCI_HOTPLUG_REQUEST_NOTIFY Notify;\r
+ EFI_PCI_HOTPLUG_REQUEST_NOTIFY Notify;\r
};\r
\r
-extern EFI_GUID gEfiPciHotPlugRequestProtocolGuid;\r
+extern EFI_GUID gEfiPciHotPlugRequestProtocolGuid;\r
\r
#endif\r
0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
}\r
\r
-typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
+typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// *******************************************************\r
///\r
typedef enum {\r
- EfiPciIoWidthUint8 = 0,\r
+ EfiPciIoWidthUint8 = 0,\r
EfiPciIoWidthUint16,\r
EfiPciIoWidthUint32,\r
EfiPciIoWidthUint64,\r
//\r
// Complete PCI address generater\r
//\r
-#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
-#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
-#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
-#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
-#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
-#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
-#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
-#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
-\r
-#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
-#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
+#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
+#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined\r
+#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
+#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
+#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
+#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
+#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
+#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
+\r
+#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
+#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
///\r
/// *******************************************************\r
///\r
/// Read PCI controller registers in the PCI memory or I/O space.\r
///\r
- EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
+ EFI_PCI_IO_PROTOCOL_IO_MEM Read;\r
///\r
/// Write PCI controller registers in the PCI memory or I/O space.\r
///\r
- EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
+ EFI_PCI_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
/**\r
///\r
/// Read PCI controller registers in PCI configuration space.\r
///\r
- EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG Read;\r
///\r
/// Write PCI controller registers in PCI configuration space.\r
///\r
- EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
/**\r
/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.\r
///\r
struct _EFI_PCI_IO_PROTOCOL {\r
- EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
- EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
- EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
- EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
- EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
- EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
- EFI_PCI_IO_PROTOCOL_MAP Map;\r
- EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
- EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
- EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
- EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
- EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
- EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
- EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
- EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
+ EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
+ EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
+ EFI_PCI_IO_PROTOCOL_ACCESS Mem;\r
+ EFI_PCI_IO_PROTOCOL_ACCESS Io;\r
+ EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci;\r
+ EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem;\r
+ EFI_PCI_IO_PROTOCOL_MAP Map;\r
+ EFI_PCI_IO_PROTOCOL_UNMAP Unmap;\r
+ EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
+ EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
+ EFI_PCI_IO_PROTOCOL_FLUSH Flush;\r
+ EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation;\r
+ EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes;\r
+ EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes;\r
+ EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes;\r
\r
///\r
/// The size, in bytes, of the ROM image.\r
///\r
- UINT64 RomSize;\r
+ UINT64 RomSize;\r
\r
///\r
/// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible\r
/// The Attributes() function can be used to determine from which of these two sources\r
/// the RomImage buffer was initialized.\r
///\r
- VOID *RomImage;\r
+ VOID *RomImage;\r
};\r
\r
-extern EFI_GUID gEfiPciIoProtocolGuid;\r
+extern EFI_GUID gEfiPciIoProtocolGuid;\r
\r
#endif\r
///\r
typedef EFI_PCI_PLATFORM_PROTOCOL EFI_PCI_OVERRIDE_PROTOCOL;\r
\r
-\r
-extern EFI_GUID gEfiPciOverrideProtocolGuid;\r
+extern EFI_GUID gEfiPciOverrideProtocolGuid;\r
\r
#endif\r
/// be treated like EFI_RESERVE_ISA_IO_NO_ALIAS |\r
/// EFI_RESERVE_VGA_IO_ALIAS.\r
///\r
-typedef UINT32 EFI_PCI_PLATFORM_POLICY;\r
+typedef UINT32 EFI_PCI_PLATFORM_POLICY;\r
\r
///\r
/// Does not set aside either ISA or VGA I/O resources during PCI\r
/// enumeration.\r
///\r
-#define EFI_RESERVE_NONE_IO_ALIAS 0x0000\r
+#define EFI_RESERVE_NONE_IO_ALIAS 0x0000\r
\r
///\r
/// Sets aside ISA I/O range and all aliases:\r
/// - n900..nBFF\r
/// - nD00..nFFF.\r
///\r
-#define EFI_RESERVE_ISA_IO_ALIAS 0x0001\r
+#define EFI_RESERVE_ISA_IO_ALIAS 0x0001\r
\r
///\r
/// Sets aside ISA I/O range 0x100-0x3FF.\r
///\r
-#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002\r
+#define EFI_RESERVE_ISA_IO_NO_ALIAS 0x0002\r
\r
///\r
/// Sets aside VGA I/O ranges and all aliases.\r
///\r
-#define EFI_RESERVE_VGA_IO_ALIAS 0x0004\r
+#define EFI_RESERVE_VGA_IO_ALIAS 0x0004\r
\r
///\r
/// Sets aside VGA I/O ranges\r
///\r
-#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008\r
+#define EFI_RESERVE_VGA_IO_NO_ALIAS 0x0008\r
\r
///\r
/// EFI_PCI_EXECUTION_PHASE is used to call a platform protocol and execute\r
/// The notification from the PCI bus enumerator to the platform that it is about to\r
/// enter a certain phase during the enumeration process.\r
///\r
- EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;\r
+ EFI_PCI_PLATFORM_PHASE_NOTIFY PlatformNotify;\r
///\r
/// The notification from the PCI bus enumerator to the platform for each PCI\r
/// controller at several predefined points during PCI controller initialization.\r
///\r
- EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r
+ EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;\r
///\r
/// Retrieves the platform policy regarding enumeration.\r
///\r
- EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;\r
+ EFI_PCI_PLATFORM_GET_PLATFORM_POLICY GetPlatformPolicy;\r
///\r
/// Gets the PCI device's option ROM from a platform-specific location.\r
///\r
- EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;\r
+ EFI_PCI_PLATFORM_GET_PCI_ROM GetPciRom;\r
};\r
\r
-extern EFI_GUID gEfiPciPlatformProtocolGuid;\r
+extern EFI_GUID gEfiPciPlatformProtocolGuid;\r
\r
#endif\r
0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
+typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
EfiPciOperationMaximum\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;\r
\r
-#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001\r
-#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002\r
-#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004\r
-#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008\r
-#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010\r
-#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020\r
-#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040\r
-#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080\r
-#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800\r
-#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000\r
-#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000\r
-#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000\r
-#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000\r
-#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000\r
-\r
-#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
-\r
-#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
+#define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001\r
+#define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002\r
+#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004\r
+#define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008\r
+#define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010\r
+#define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020\r
+#define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040\r
+#define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080\r
+#define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800\r
+#define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000\r
+#define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000\r
+#define EFI_PCI_ATTRIBUTE_ISA_IO_16 0x10000\r
+#define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000\r
+#define EFI_PCI_ATTRIBUTE_VGA_IO_16 0x40000\r
+\r
+#define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)\r
+\r
+#define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)\r
\r
#define EFI_PCI_ADDRESS(bus, dev, func, reg) \\r
(UINT64) ( \\r
(((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))\r
\r
typedef struct {\r
- UINT8 Register;\r
- UINT8 Function;\r
- UINT8 Device;\r
- UINT8 Bus;\r
- UINT32 ExtendedRegister;\r
+ UINT8 Register;\r
+ UINT8 Function;\r
+ UINT8 Device;\r
+ UINT8 Bus;\r
+ UINT32 ExtendedRegister;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;\r
\r
/**\r
///\r
/// Read PCI controller registers in the PCI root bridge memory space.\r
///\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;\r
///\r
/// Write PCI controller registers in the PCI root bridge memory space.\r
///\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;\r
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;\r
\r
/**\r
///\r
/// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.\r
///\r
- EFI_HANDLE ParentHandle;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
+ EFI_HANDLE ParentHandle;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;\r
\r
///\r
/// The segment number that this PCI root bridge resides.\r
///\r
- UINT32 SegmentNumber;\r
+ UINT32 SegmentNumber;\r
};\r
\r
-extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
+extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;\r
\r
#endif\r
#ifndef __PI_PCD_H__\r
#define __PI_PCD_H__\r
\r
-extern EFI_GUID gEfiPcdProtocolGuid;\r
+extern EFI_GUID gEfiPcdProtocolGuid;\r
\r
#define EFI_PCD_PROTOCOL_GUID \\r
{ 0x13a3f0f6, 0x264a, 0x3ef0, { 0xf2, 0xe0, 0xde, 0xc5, 0x12, 0x34, 0x2f, 0x34 } }\r
\r
-#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
+#define EFI_PCD_INVALID_TOKEN_NUMBER ((UINTN) 0)\r
\r
/**\r
SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. SetSku() is\r
VOID\r
(EFIAPI *EFI_PCD_PROTOCOL_SET_SKU)(\r
IN UINTN SkuId\r
-);\r
+ );\r
\r
/**\r
Retrieves an 8-bit value for a given PCD token.\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_8)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current word-sized value for a PCD token number.\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_16)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current 32-bit sized value for a PCD token number.\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_32)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the 64-bit sized value for a PCD token number.\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_64)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current pointer to the value for a PCD token number. Do not make any assumptions\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_POINTER)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current BOOLEAN-sized value for a PCD token number. If the TokenNumber is\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_BOOLEAN)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Retrieves the current size of a particular PCD token. If the TokenNumber is invalid, the results are\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_SIZE)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber\r
-);\r
+ );\r
\r
/**\r
Sets an 8-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT8 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 16-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT16 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 32-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT32 Value\r
-);\r
+ );\r
\r
/**\r
Sets an 64-bit value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN UINT64 Value\r
-);\r
+ );\r
\r
/**\r
Sets a value of a specified size for a given PCD token.\r
IN UINTN TokenNumber,\r
IN OUT UINTN *SizeOfValue,\r
IN VOID *Buffer\r
-);\r
+ );\r
\r
/**\r
Sets a Boolean value for a given PCD token.\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
IN BOOLEAN Value\r
-);\r
+ );\r
\r
typedef\r
VOID\r
IN UINTN CallBackToken,\r
IN OUT VOID *TokenData,\r
IN UINTN TokenDataSize\r
-);\r
+ );\r
\r
/**\r
Specifies a function to be called anytime the value of a designated token is changed.\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN CallBackToken,\r
IN EFI_PCD_PROTOCOL_CALLBACK CallBackFunction\r
-);\r
+ );\r
\r
/**\r
Cancels a callback function that was set through a previous call to the CallBackOnSet function.\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN CallBackToken,\r
IN EFI_PCD_PROTOCOL_CALLBACK CallBackFunction\r
-);\r
+ );\r
\r
/**\r
Gets the next valid token number in a given namespace. This is useful since the PCD infrastructure\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN)(\r
IN CONST EFI_GUID *Guid OPTIONAL,\r
IN UINTN *TokenNumber\r
-);\r
+ );\r
\r
/**\r
Gets the next valid token namespace for a given namespace. This is useful to traverse the valid\r
EFI_STATUS\r
(EFIAPI *EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE)(\r
IN OUT CONST EFI_GUID **Guid\r
-);\r
+ );\r
\r
typedef struct _EFI_PCD_PROTOCOL {\r
- EFI_PCD_PROTOCOL_SET_SKU SetSku;\r
- EFI_PCD_PROTOCOL_GET_8 Get8;\r
- EFI_PCD_PROTOCOL_GET_16 Get16;\r
- EFI_PCD_PROTOCOL_GET_32 Get32;\r
- EFI_PCD_PROTOCOL_GET_64 Get64;\r
- EFI_PCD_PROTOCOL_GET_POINTER GetPtr;\r
- EFI_PCD_PROTOCOL_GET_BOOLEAN GetBool;\r
- EFI_PCD_PROTOCOL_GET_SIZE GetSize;\r
- EFI_PCD_PROTOCOL_SET_8 Set8;\r
- EFI_PCD_PROTOCOL_SET_16 Set16;\r
- EFI_PCD_PROTOCOL_SET_32 Set32;\r
- EFI_PCD_PROTOCOL_SET_64 Set64;\r
- EFI_PCD_PROTOCOL_SET_POINTER SetPtr;\r
- EFI_PCD_PROTOCOL_SET_BOOLEAN SetBool;\r
- EFI_PCD_PROTOCOL_CALLBACK_ON_SET CallbackOnSet;\r
- EFI_PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback;\r
- EFI_PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken;\r
- EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;\r
+ EFI_PCD_PROTOCOL_SET_SKU SetSku;\r
+ EFI_PCD_PROTOCOL_GET_8 Get8;\r
+ EFI_PCD_PROTOCOL_GET_16 Get16;\r
+ EFI_PCD_PROTOCOL_GET_32 Get32;\r
+ EFI_PCD_PROTOCOL_GET_64 Get64;\r
+ EFI_PCD_PROTOCOL_GET_POINTER GetPtr;\r
+ EFI_PCD_PROTOCOL_GET_BOOLEAN GetBool;\r
+ EFI_PCD_PROTOCOL_GET_SIZE GetSize;\r
+ EFI_PCD_PROTOCOL_SET_8 Set8;\r
+ EFI_PCD_PROTOCOL_SET_16 Set16;\r
+ EFI_PCD_PROTOCOL_SET_32 Set32;\r
+ EFI_PCD_PROTOCOL_SET_64 Set64;\r
+ EFI_PCD_PROTOCOL_SET_POINTER SetPtr;\r
+ EFI_PCD_PROTOCOL_SET_BOOLEAN SetBool;\r
+ EFI_PCD_PROTOCOL_CALLBACK_ON_SET CallbackOnSet;\r
+ EFI_PCD_PROTOCOL_CANCEL_CALLBACK CancelCallback;\r
+ EFI_PCD_PROTOCOL_GET_NEXT_TOKEN GetNextToken;\r
+ EFI_PCD_PROTOCOL_GET_NEXT_TOKEN_SPACE GetNextTokenSpace;\r
} EFI_PCD_PROTOCOL;\r
\r
#endif\r
#ifndef __PI_PCD_INFO_H__\r
#define __PI_PCD_INFO_H__\r
\r
-extern EFI_GUID gEfiGetPcdInfoProtocolGuid;\r
+extern EFI_GUID gEfiGetPcdInfoProtocolGuid;\r
\r
#define EFI_GET_PCD_INFO_PROTOCOL_GUID \\r
{ 0xfd0f4478, 0xefd, 0x461d, { 0xba, 0x2d, 0xe5, 0x8c, 0x45, 0xfd, 0x5f, 0x5e } }\r
///\r
/// The forward declaration for EFI_GET_PCD_INFO_PROTOCOL.\r
///\r
-typedef struct _EFI_GET_PCD_INFO_PROTOCOL EFI_GET_PCD_INFO_PROTOCOL;\r
+typedef struct _EFI_GET_PCD_INFO_PROTOCOL EFI_GET_PCD_INFO_PROTOCOL;\r
\r
/**\r
Retrieve additional information associated with a PCD token.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_INFO) (\r
+(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_INFO)(\r
IN CONST EFI_GUID *Guid,\r
IN UINTN TokenNumber,\r
OUT EFI_PCD_INFO *PcdInfo\r
-);\r
+ );\r
\r
/**\r
Retrieve the currently set SKU Id.\r
**/\r
typedef\r
UINTN\r
-(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_SKU) (\r
+(EFIAPI *EFI_GET_PCD_INFO_PROTOCOL_GET_SKU)(\r
VOID\r
-);\r
+ );\r
\r
///\r
/// Callers to this protocol must be at a TPL_APPLICATION task priority level.\r
};\r
\r
#endif\r
-\r
\r
typedef struct _EFI_PKCS7_VERIFY_PROTOCOL EFI_PKCS7_VERIFY_PROTOCOL;\r
\r
-\r
/**\r
Processes a buffer containing binary DER-encoded PKCS7 signature.\r
The signed data content may be embedded within the buffer or separated. Funtion\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PKCS7_VERIFY_BUFFER) (\r
+(EFIAPI *EFI_PKCS7_VERIFY_BUFFER)(\r
IN EFI_PKCS7_VERIFY_PROTOCOL *This,\r
IN VOID *SignedData,\r
IN UINTN SignedDataSize,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_PKCS7_VERIFY_SIGNATURE) (\r
+(EFIAPI *EFI_PKCS7_VERIFY_SIGNATURE)(\r
IN EFI_PKCS7_VERIFY_PROTOCOL *This,\r
IN VOID *Signature,\r
IN UINTN SignatureSize,\r
/// Support of other hash algorithms is optional.\r
///\r
struct _EFI_PKCS7_VERIFY_PROTOCOL {\r
- EFI_PKCS7_VERIFY_BUFFER VerifyBuffer;\r
- EFI_PKCS7_VERIFY_SIGNATURE VerifySignature;\r
+ EFI_PKCS7_VERIFY_BUFFER VerifyBuffer;\r
+ EFI_PKCS7_VERIFY_SIGNATURE VerifySignature;\r
};\r
\r
-extern EFI_GUID gEfiPkcs7VerifyProtocolGuid;\r
+extern EFI_GUID gEfiPkcs7VerifyProtocolGuid;\r
\r
#endif\r
0x6b30c738, 0xa391, 0x11d4, {0x9a, 0x3b, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL;\r
+typedef struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL;\r
\r
//\r
// Prototypes for the Platform Driver Override Protocol\r
/// order from highest precedence to lowest precedence.\r
///\r
struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL {\r
- EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER GetDriver;\r
- EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH GetDriverPath;\r
- EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED DriverLoaded;\r
+ EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER GetDriver;\r
+ EFI_PLATFORM_DRIVER_OVERRIDE_GET_DRIVER_PATH GetDriverPath;\r
+ EFI_PLATFORM_DRIVER_OVERRIDE_DRIVER_LOADED DriverLoaded;\r
};\r
\r
-extern EFI_GUID gEfiPlatformDriverOverrideProtocolGuid;\r
+extern EFI_GUID gEfiPlatformDriverOverrideProtocolGuid;\r
\r
#endif\r
#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL_GUID \\r
{ 0x642cd590, 0x8059, 0x4c0a, { 0xa9, 0x58, 0xc5, 0xec, 0x7, 0xd2, 0x3c, 0x4b } }\r
\r
-\r
typedef struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL;\r
\r
-\r
/**\r
The UEFI driver must call Query early in the Start() function\r
before any time consuming operations are performed. If\r
OUT EFI_GUID **ParameterTypeGuid,\r
OUT VOID **ParameterBlock,\r
OUT UINTN *ParameterBlockSize\r
-);\r
+ );\r
\r
typedef enum {\r
///\r
/// this controller can be used again with the updated\r
/// configuration settings.\r
///\r
- EfiPlatformConfigurationActionNone = 0,\r
+ EfiPlatformConfigurationActionNone = 0,\r
\r
///\r
/// The driver has detected that the controller specified\r
/// DisconnectControservice to perform this operation, and\r
/// it should be performed as soon as possible.\r
///\r
- EfiPlatformConfigurationActionStopController = 1,\r
+ EfiPlatformConfigurationActionStopController = 1,\r
\r
///\r
/// This controller specified by ControllerHandle needs to\r
/// delayed until all of the configuration options have\r
/// been set.\r
///\r
- EfiPlatformConfigurationActionRestartPlatform = 3,\r
+ EfiPlatformConfigurationActionRestartPlatform = 3,\r
\r
///\r
/// The controller specified by ControllerHandle is still\r
/// configuration settings are not guaranteed to persist\r
/// after ControllerHandle is stopped.\r
///\r
- EfiPlatformConfigurationActionNvramFailed = 4,\r
+ EfiPlatformConfigurationActionNvramFailed = 4,\r
\r
///\r
/// The controller specified by ControllerHandle is still\r
/// ParameterTypeGuid is supported by the platform, Query\r
/// should return EFI_NOT_FOUND.\r
///\r
- EfiPlatformConfigurationActionUnsupportedGuid = 5,\r
+ EfiPlatformConfigurationActionUnsupportedGuid = 5,\r
EfiPlatformConfigurationActionMaximum\r
} EFI_PLATFORM_CONFIGURATION_ACTION;\r
\r
-\r
/**\r
The UEFI driver repeatedly calls Query, processes the\r
information returned by the platform, and calls Response passing\r
IN CONST UINTN *Instance,\r
IN CONST EFI_GUID *ParameterTypeGuid,\r
IN CONST VOID *ParameterBlock,\r
- IN CONST UINTN ParameterBlockSize ,\r
+ IN CONST UINTN ParameterBlockSize,\r
IN CONST EFI_PLATFORM_CONFIGURATION_ACTION ConfigurationAction\r
-);\r
-\r
+ );\r
\r
///\r
/// The EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL is used by the\r
/// taken.\r
///\r
struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL {\r
- EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY Query;\r
- EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE Response;\r
+ EFI_PLATFORM_TO_DRIVER_CONFIGURATION_QUERY Query;\r
+ EFI_PLATFORM_TO_DRIVER_CONFIGURATION_RESPONSE Response;\r
};\r
\r
-\r
-\r
#define EFI_PLATFORM_TO_DRIVER_CONFIGURATION_CLP_GUID \\r
{0x345ecc0e, 0xcb6, 0x4b75, { 0xbb, 0x57, 0x1b, 0x12, 0x9c, 0x47, 0x33,0x3e } }\r
\r
used.\r
**/\r
typedef struct {\r
- CHAR8 *CLPCommand; ///< A pointer to the null-terminated UTF-8 string that specifies the DMTF SM CLP command\r
- ///< line that the driver is required to parse and process when this function is called.\r
- ///< See the DMTF SM CLP Specification 1.0 Final Standard for details on the\r
- ///< format and syntax of the CLP command line string. CLPCommand buffer\r
- ///< is allocated by the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOOL.\r
- UINT32 CLPCommandLength; ///< The length of the CLP Command in bytes.\r
- CHAR8 *CLPReturnString; ///< A pointer to the null-terminated UTF-8 string that indicates the CLP return status\r
- ///< that the driver is required to provide to the calling agent.\r
- ///< The calling agent may parse and/ or pass\r
- ///< this for processing and user feedback. The SM CLP Command Response string\r
- ///< buffer is filled in by the UEFI driver in the "keyword=value" format\r
- ///< described in the SM CLP Specification, unless otherwise requested via the SM\r
- ///< CLP Coutput option in the Command Line string buffer. UEFI driver's support\r
- ///< for this default "keyword=value" output format is required if the UEFI\r
- ///< driver supports this protocol, while support for other SM CLP output\r
- ///< formats is optional (the UEFI Driver should return an EFI_UNSUPPORTED if\r
- ///< the SM CLP Coutput option requested by the caller is not supported by the\r
- ///< UEFI Driver). CLPReturnString buffer is allocated by the consumer of the\r
- ///< EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to\r
- ///< Response().\r
- UINT32 CLPReturnStringLength; ///< The length of the CLP return status string in bytes.\r
- UINT8 CLPCmdStatus; ///< SM CLP Command Status (see DMTF SM CLP Specification 1.0 Final Standard -\r
- ///< Table 4) CLPErrorValue SM CLP Processing Error Value (see DMTF SM\r
- ///< CLP Specification 1.0 Final Standard - Table 6). This field is filled in by\r
- ///< the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC\r
- ///< OL and undefined prior to the call to Response().\r
- UINT8 CLPErrorValue; ///< SM CLP Processing Error Value (see DMTF SM CLP Specification 1.0 Final Standard - Table 6).\r
- ///< This field is filled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL and undefined prior to the call to Response().\r
- UINT16 CLPMsgCode; ///< Bit 15: OEM Message Code Flag 0 = Message Code is an SM CLP Probable\r
- ///< Cause Value. (see SM CLP Specification Table 11) 1 = Message Code is OEM\r
- ///< Specific Bits 14-0: Message Code This field is filled in by the consumer of\r
- ///< the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to\r
- ///< Response().\r
-\r
+ CHAR8 *CLPCommand; ///< A pointer to the null-terminated UTF-8 string that specifies the DMTF SM CLP command\r
+ ///< line that the driver is required to parse and process when this function is called.\r
+ ///< See the DMTF SM CLP Specification 1.0 Final Standard for details on the\r
+ ///< format and syntax of the CLP command line string. CLPCommand buffer\r
+ ///< is allocated by the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOOL.\r
+ UINT32 CLPCommandLength; ///< The length of the CLP Command in bytes.\r
+ CHAR8 *CLPReturnString; ///< A pointer to the null-terminated UTF-8 string that indicates the CLP return status\r
+ ///< that the driver is required to provide to the calling agent.\r
+ ///< The calling agent may parse and/ or pass\r
+ ///< this for processing and user feedback. The SM CLP Command Response string\r
+ ///< buffer is filled in by the UEFI driver in the "keyword=value" format\r
+ ///< described in the SM CLP Specification, unless otherwise requested via the SM\r
+ ///< CLP Coutput option in the Command Line string buffer. UEFI driver's support\r
+ ///< for this default "keyword=value" output format is required if the UEFI\r
+ ///< driver supports this protocol, while support for other SM CLP output\r
+ ///< formats is optional (the UEFI Driver should return an EFI_UNSUPPORTED if\r
+ ///< the SM CLP Coutput option requested by the caller is not supported by the\r
+ ///< UEFI Driver). CLPReturnString buffer is allocated by the consumer of the\r
+ ///< EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to\r
+ ///< Response().\r
+ UINT32 CLPReturnStringLength; ///< The length of the CLP return status string in bytes.\r
+ UINT8 CLPCmdStatus; ///< SM CLP Command Status (see DMTF SM CLP Specification 1.0 Final Standard -\r
+ ///< Table 4) CLPErrorValue SM CLP Processing Error Value (see DMTF SM\r
+ ///< CLP Specification 1.0 Final Standard - Table 6). This field is filled in by\r
+ ///< the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC\r
+ ///< OL and undefined prior to the call to Response().\r
+ UINT8 CLPErrorValue; ///< SM CLP Processing Error Value (see DMTF SM CLP Specification 1.0 Final Standard - Table 6).\r
+ ///< This field is filled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL and undefined prior to the call to Response().\r
+ UINT16 CLPMsgCode; ///< Bit 15: OEM Message Code Flag 0 = Message Code is an SM CLP Probable\r
+ ///< Cause Value. (see SM CLP Specification Table 11) 1 = Message Code is OEM\r
+ ///< Specific Bits 14-0: Message Code This field is filled in by the consumer of\r
+ ///< the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to\r
+ ///< Response().\r
} EFI_CONFIGURE_CLP_PARAMETER_BLK;\r
\r
+extern EFI_GUID gEfiPlatformToDriverConfigurationClpGuid;\r
\r
-\r
-extern EFI_GUID gEfiPlatformToDriverConfigurationClpGuid;\r
-\r
-extern EFI_GUID gEfiPlatformToDriverConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiPlatformToDriverConfigurationProtocolGuid;\r
\r
#endif\r
This Protocol is introduced in EFI Specification 1.10.\r
\r
**/\r
+\r
#ifndef __PXE_BASE_CODE_PROTOCOL_H__\r
#define __PXE_BASE_CODE_PROTOCOL_H__\r
\r
0x03c4e603, 0xac28, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE_PROTOCOL;\r
+typedef struct _EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE_PROTOCOL;\r
\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE;\r
+typedef EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE;\r
\r
///\r
/// Default IP TTL and ToS.\r
///\r
-#define DEFAULT_TTL 16\r
-#define DEFAULT_ToS 0\r
+#define DEFAULT_TTL 16\r
+#define DEFAULT_ToS 0\r
\r
///\r
/// ICMP error format.\r
///\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 Code;\r
- UINT16 Checksum;\r
+ UINT8 Type;\r
+ UINT8 Code;\r
+ UINT16 Checksum;\r
union {\r
- UINT32 reserved;\r
- UINT32 Mtu;\r
- UINT32 Pointer;\r
+ UINT32 reserved;\r
+ UINT32 Mtu;\r
+ UINT32 Pointer;\r
struct {\r
- UINT16 Identifier;\r
- UINT16 Sequence;\r
+ UINT16 Identifier;\r
+ UINT16 Sequence;\r
} Echo;\r
} u;\r
- UINT8 Data[494];\r
+ UINT8 Data[494];\r
} EFI_PXE_BASE_CODE_ICMP_ERROR;\r
\r
///\r
/// TFTP error format.\r
///\r
typedef struct {\r
- UINT8 ErrorCode;\r
- CHAR8 ErrorString[127];\r
+ UINT8 ErrorCode;\r
+ CHAR8 ErrorString[127];\r
} EFI_PXE_BASE_CODE_TFTP_ERROR;\r
\r
///\r
/// IP Receive Filter definitions.\r
///\r
-#define EFI_PXE_BASE_CODE_MAX_IPCNT 8\r
+#define EFI_PXE_BASE_CODE_MAX_IPCNT 8\r
\r
///\r
/// IP Receive Filter structure.\r
///\r
typedef struct {\r
- UINT8 Filters;\r
- UINT8 IpCnt;\r
- UINT16 reserved;\r
- EFI_IP_ADDRESS IpList[EFI_PXE_BASE_CODE_MAX_IPCNT];\r
+ UINT8 Filters;\r
+ UINT8 IpCnt;\r
+ UINT16 reserved;\r
+ EFI_IP_ADDRESS IpList[EFI_PXE_BASE_CODE_MAX_IPCNT];\r
} EFI_PXE_BASE_CODE_IP_FILTER;\r
\r
-#define EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP 0x0001\r
-#define EFI_PXE_BASE_CODE_IP_FILTER_BROADCAST 0x0002\r
-#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS 0x0004\r
-#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS_MULTICAST 0x0008\r
+#define EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP 0x0001\r
+#define EFI_PXE_BASE_CODE_IP_FILTER_BROADCAST 0x0002\r
+#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS 0x0004\r
+#define EFI_PXE_BASE_CODE_IP_FILTER_PROMISCUOUS_MULTICAST 0x0008\r
\r
///\r
/// ARP cache entries.\r
///\r
typedef struct {\r
- EFI_IP_ADDRESS IpAddr;\r
- EFI_MAC_ADDRESS MacAddr;\r
+ EFI_IP_ADDRESS IpAddr;\r
+ EFI_MAC_ADDRESS MacAddr;\r
} EFI_PXE_BASE_CODE_ARP_ENTRY;\r
\r
///\r
/// ARP route table entries.\r
///\r
typedef struct {\r
- EFI_IP_ADDRESS IpAddr;\r
- EFI_IP_ADDRESS SubnetMask;\r
- EFI_IP_ADDRESS GwAddr;\r
+ EFI_IP_ADDRESS IpAddr;\r
+ EFI_IP_ADDRESS SubnetMask;\r
+ EFI_IP_ADDRESS GwAddr;\r
} EFI_PXE_BASE_CODE_ROUTE_ENTRY;\r
\r
//\r
// UDP definitions\r
//\r
-typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;\r
+typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;\r
\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_IP 0x0001\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_PORT 0x0002\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_IP 0x0004\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_PORT 0x0008\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_USE_FILTER 0x0010\r
-#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_MAY_FRAGMENT 0x0020\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_IP 0x0001\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_SRC_PORT 0x0002\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_IP 0x0004\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_ANY_DEST_PORT 0x0008\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_USE_FILTER 0x0010\r
+#define EFI_PXE_BASE_CODE_UDP_OPFLAGS_MAY_FRAGMENT 0x0020\r
\r
//\r
// Discover() definitions\r
// 32768 through 65279 are for vendor use\r
// 65280 through 65534 are reserved\r
//\r
-#define EFI_PXE_BASE_CODE_BOOT_TYPE_PXETEST 65535\r
+#define EFI_PXE_BASE_CODE_BOOT_TYPE_PXETEST 65535\r
\r
#define EFI_PXE_BASE_CODE_BOOT_LAYER_MASK 0x7FFF\r
#define EFI_PXE_BASE_CODE_BOOT_LAYER_INITIAL 0x0000\r
// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml\r
//\r
#if defined (MDE_CPU_IA32)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006\r
#elif defined (MDE_CPU_X64)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007\r
#elif defined (MDE_CPU_ARM)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A\r
#elif defined (MDE_CPU_AARCH64)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B\r
#elif defined (MDE_CPU_RISCV64)\r
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B\r
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B\r
#endif\r
\r
-\r
///\r
/// Discover() server list structure.\r
///\r
typedef struct {\r
- UINT16 Type;\r
- BOOLEAN AcceptAnyResponse;\r
- UINT8 Reserved;\r
- EFI_IP_ADDRESS IpAddr;\r
+ UINT16 Type;\r
+ BOOLEAN AcceptAnyResponse;\r
+ UINT8 Reserved;\r
+ EFI_IP_ADDRESS IpAddr;\r
} EFI_PXE_BASE_CODE_SRVLIST;\r
\r
///\r
/// Discover() information override structure.\r
///\r
typedef struct {\r
- BOOLEAN UseMCast;\r
- BOOLEAN UseBCast;\r
- BOOLEAN UseUCast;\r
- BOOLEAN MustUseList;\r
- EFI_IP_ADDRESS ServerMCastIp;\r
- UINT16 IpCnt;\r
- EFI_PXE_BASE_CODE_SRVLIST SrvList[1];\r
+ BOOLEAN UseMCast;\r
+ BOOLEAN UseBCast;\r
+ BOOLEAN UseUCast;\r
+ BOOLEAN MustUseList;\r
+ EFI_IP_ADDRESS ServerMCastIp;\r
+ UINT16 IpCnt;\r
+ EFI_PXE_BASE_CODE_SRVLIST SrvList[1];\r
} EFI_PXE_BASE_CODE_DISCOVER_INFO;\r
\r
///\r
/// perform the "get file size" and "read directory" operations of MTFTP.\r
///\r
typedef struct {\r
- EFI_IP_ADDRESS MCastIp;\r
- EFI_PXE_BASE_CODE_UDP_PORT CPort;\r
- EFI_PXE_BASE_CODE_UDP_PORT SPort;\r
- UINT16 ListenTimeout;\r
- UINT16 TransmitTimeout;\r
+ EFI_IP_ADDRESS MCastIp;\r
+ EFI_PXE_BASE_CODE_UDP_PORT CPort;\r
+ EFI_PXE_BASE_CODE_UDP_PORT SPort;\r
+ UINT16 ListenTimeout;\r
+ UINT16 TransmitTimeout;\r
} EFI_PXE_BASE_CODE_MTFTP_INFO;\r
\r
///\r
/// DHCPV4 Packet structure.\r
///\r
typedef struct {\r
- UINT8 BootpOpcode;\r
- UINT8 BootpHwType;\r
- UINT8 BootpHwAddrLen;\r
- UINT8 BootpGateHops;\r
- UINT32 BootpIdent;\r
- UINT16 BootpSeconds;\r
- UINT16 BootpFlags;\r
- UINT8 BootpCiAddr[4];\r
- UINT8 BootpYiAddr[4];\r
- UINT8 BootpSiAddr[4];\r
- UINT8 BootpGiAddr[4];\r
- UINT8 BootpHwAddr[16];\r
- UINT8 BootpSrvName[64];\r
- UINT8 BootpBootFile[128];\r
- UINT32 DhcpMagik;\r
- UINT8 DhcpOptions[56];\r
+ UINT8 BootpOpcode;\r
+ UINT8 BootpHwType;\r
+ UINT8 BootpHwAddrLen;\r
+ UINT8 BootpGateHops;\r
+ UINT32 BootpIdent;\r
+ UINT16 BootpSeconds;\r
+ UINT16 BootpFlags;\r
+ UINT8 BootpCiAddr[4];\r
+ UINT8 BootpYiAddr[4];\r
+ UINT8 BootpSiAddr[4];\r
+ UINT8 BootpGiAddr[4];\r
+ UINT8 BootpHwAddr[16];\r
+ UINT8 BootpSrvName[64];\r
+ UINT8 BootpBootFile[128];\r
+ UINT32 DhcpMagik;\r
+ UINT8 DhcpOptions[56];\r
} EFI_PXE_BASE_CODE_DHCPV4_PACKET;\r
\r
///\r
/// DHCPV6 Packet structure.\r
///\r
typedef struct {\r
- UINT32 MessageType:8;\r
- UINT32 TransactionId:24;\r
- UINT8 DhcpOptions[1024];\r
+ UINT32 MessageType : 8;\r
+ UINT32 TransactionId : 24;\r
+ UINT8 DhcpOptions[1024];\r
} EFI_PXE_BASE_CODE_DHCPV6_PACKET;\r
\r
///\r
/// Packet structure.\r
///\r
typedef union {\r
- UINT8 Raw[1472];\r
- EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4;\r
- EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6;\r
+ UINT8 Raw[1472];\r
+ EFI_PXE_BASE_CODE_DHCPV4_PACKET Dhcpv4;\r
+ EFI_PXE_BASE_CODE_DHCPV6_PACKET Dhcpv6;\r
} EFI_PXE_BASE_CODE_PACKET;\r
\r
//\r
// PXE Base Code Mode structure\r
//\r
-#define EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES 8\r
-#define EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES 8\r
+#define EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES 8\r
+#define EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES 8\r
\r
///\r
/// EFI_PXE_BASE_CODE_MODE.\r
/// EFI_PXE_BASE_CODE_PROTOCOL functions.\r
///\r
typedef struct {\r
- BOOLEAN Started;\r
- BOOLEAN Ipv6Available;\r
- BOOLEAN Ipv6Supported;\r
- BOOLEAN UsingIpv6;\r
- BOOLEAN BisSupported;\r
- BOOLEAN BisDetected;\r
- BOOLEAN AutoArp;\r
- BOOLEAN SendGUID;\r
- BOOLEAN DhcpDiscoverValid;\r
- BOOLEAN DhcpAckReceived;\r
- BOOLEAN ProxyOfferReceived;\r
- BOOLEAN PxeDiscoverValid;\r
- BOOLEAN PxeReplyReceived;\r
- BOOLEAN PxeBisReplyReceived;\r
- BOOLEAN IcmpErrorReceived;\r
- BOOLEAN TftpErrorReceived;\r
- BOOLEAN MakeCallbacks;\r
- UINT8 TTL;\r
- UINT8 ToS;\r
- EFI_IP_ADDRESS StationIp;\r
- EFI_IP_ADDRESS SubnetMask;\r
- EFI_PXE_BASE_CODE_PACKET DhcpDiscover;\r
- EFI_PXE_BASE_CODE_PACKET DhcpAck;\r
- EFI_PXE_BASE_CODE_PACKET ProxyOffer;\r
- EFI_PXE_BASE_CODE_PACKET PxeDiscover;\r
- EFI_PXE_BASE_CODE_PACKET PxeReply;\r
- EFI_PXE_BASE_CODE_PACKET PxeBisReply;\r
- EFI_PXE_BASE_CODE_IP_FILTER IpFilter;\r
- UINT32 ArpCacheEntries;\r
- EFI_PXE_BASE_CODE_ARP_ENTRY ArpCache[EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES];\r
- UINT32 RouteTableEntries;\r
- EFI_PXE_BASE_CODE_ROUTE_ENTRY RouteTable[EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES];\r
- EFI_PXE_BASE_CODE_ICMP_ERROR IcmpError;\r
- EFI_PXE_BASE_CODE_TFTP_ERROR TftpError;\r
+ BOOLEAN Started;\r
+ BOOLEAN Ipv6Available;\r
+ BOOLEAN Ipv6Supported;\r
+ BOOLEAN UsingIpv6;\r
+ BOOLEAN BisSupported;\r
+ BOOLEAN BisDetected;\r
+ BOOLEAN AutoArp;\r
+ BOOLEAN SendGUID;\r
+ BOOLEAN DhcpDiscoverValid;\r
+ BOOLEAN DhcpAckReceived;\r
+ BOOLEAN ProxyOfferReceived;\r
+ BOOLEAN PxeDiscoverValid;\r
+ BOOLEAN PxeReplyReceived;\r
+ BOOLEAN PxeBisReplyReceived;\r
+ BOOLEAN IcmpErrorReceived;\r
+ BOOLEAN TftpErrorReceived;\r
+ BOOLEAN MakeCallbacks;\r
+ UINT8 TTL;\r
+ UINT8 ToS;\r
+ EFI_IP_ADDRESS StationIp;\r
+ EFI_IP_ADDRESS SubnetMask;\r
+ EFI_PXE_BASE_CODE_PACKET DhcpDiscover;\r
+ EFI_PXE_BASE_CODE_PACKET DhcpAck;\r
+ EFI_PXE_BASE_CODE_PACKET ProxyOffer;\r
+ EFI_PXE_BASE_CODE_PACKET PxeDiscover;\r
+ EFI_PXE_BASE_CODE_PACKET PxeReply;\r
+ EFI_PXE_BASE_CODE_PACKET PxeBisReply;\r
+ EFI_PXE_BASE_CODE_IP_FILTER IpFilter;\r
+ UINT32 ArpCacheEntries;\r
+ EFI_PXE_BASE_CODE_ARP_ENTRY ArpCache[EFI_PXE_BASE_CODE_MAX_ARP_ENTRIES];\r
+ UINT32 RouteTableEntries;\r
+ EFI_PXE_BASE_CODE_ROUTE_ENTRY RouteTable[EFI_PXE_BASE_CODE_MAX_ROUTE_ENTRIES];\r
+ EFI_PXE_BASE_CODE_ICMP_ERROR IcmpError;\r
+ EFI_PXE_BASE_CODE_TFTP_ERROR TftpError;\r
} EFI_PXE_BASE_CODE_MODE;\r
\r
//\r
//\r
// PXE Base Code Protocol structure\r
//\r
-#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000\r
+#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000\r
\r
//\r
// Revision defined in EFI1.1\r
/// be backwards compatible. If a future version is not backwards compatible\r
/// it is not the same GUID.\r
///\r
- UINT64 Revision;\r
- EFI_PXE_BASE_CODE_START Start;\r
- EFI_PXE_BASE_CODE_STOP Stop;\r
- EFI_PXE_BASE_CODE_DHCP Dhcp;\r
- EFI_PXE_BASE_CODE_DISCOVER Discover;\r
- EFI_PXE_BASE_CODE_MTFTP Mtftp;\r
- EFI_PXE_BASE_CODE_UDP_WRITE UdpWrite;\r
- EFI_PXE_BASE_CODE_UDP_READ UdpRead;\r
- EFI_PXE_BASE_CODE_SET_IP_FILTER SetIpFilter;\r
- EFI_PXE_BASE_CODE_ARP Arp;\r
- EFI_PXE_BASE_CODE_SET_PARAMETERS SetParameters;\r
- EFI_PXE_BASE_CODE_SET_STATION_IP SetStationIp;\r
- EFI_PXE_BASE_CODE_SET_PACKETS SetPackets;\r
+ UINT64 Revision;\r
+ EFI_PXE_BASE_CODE_START Start;\r
+ EFI_PXE_BASE_CODE_STOP Stop;\r
+ EFI_PXE_BASE_CODE_DHCP Dhcp;\r
+ EFI_PXE_BASE_CODE_DISCOVER Discover;\r
+ EFI_PXE_BASE_CODE_MTFTP Mtftp;\r
+ EFI_PXE_BASE_CODE_UDP_WRITE UdpWrite;\r
+ EFI_PXE_BASE_CODE_UDP_READ UdpRead;\r
+ EFI_PXE_BASE_CODE_SET_IP_FILTER SetIpFilter;\r
+ EFI_PXE_BASE_CODE_ARP Arp;\r
+ EFI_PXE_BASE_CODE_SET_PARAMETERS SetParameters;\r
+ EFI_PXE_BASE_CODE_SET_STATION_IP SetStationIp;\r
+ EFI_PXE_BASE_CODE_SET_PACKETS SetPackets;\r
///\r
/// The pointer to the EFI_PXE_BASE_CODE_MODE data for this device.\r
///\r
- EFI_PXE_BASE_CODE_MODE *Mode;\r
+ EFI_PXE_BASE_CODE_MODE *Mode;\r
};\r
\r
-extern EFI_GUID gEfiPxeBaseCodeProtocolGuid;\r
+extern EFI_GUID gEfiPxeBaseCodeProtocolGuid;\r
\r
#endif\r
///\r
/// UEFI Revision Number Definition.\r
///\r
-#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION 0x00010000\r
+#define EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL_REVISION 0x00010000\r
\r
///\r
/// EFI 1.1 Revision Number defintion.\r
///\r
/// UEFI Protocol name.\r
///\r
-typedef struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL;\r
+typedef struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL;\r
\r
///\r
/// EFI1.1 Protocol name.\r
///\r
-typedef EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK;\r
+typedef EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL EFI_PXE_BASE_CODE_CALLBACK;\r
\r
///\r
/// Event type list for PXE Base Code Protocol function.\r
/// be backwards compatible. If a future version is not backwards compatible\r
/// it is not the same GUID.\r
///\r
- UINT64 Revision;\r
- EFI_PXE_CALLBACK Callback;\r
+ UINT64 Revision;\r
+ EFI_PXE_CALLBACK Callback;\r
};\r
\r
-extern EFI_GUID gEfiPxeBaseCodeCallbackProtocolGuid;\r
+extern EFI_GUID gEfiPxeBaseCodeCallbackProtocolGuid;\r
\r
#endif\r
-\r
//\r
// Forward reference for pure ANSI compatability\r
//\r
-typedef struct _EFI_RAM_DISK_PROTOCOL EFI_RAM_DISK_PROTOCOL;\r
+typedef struct _EFI_RAM_DISK_PROTOCOL EFI_RAM_DISK_PROTOCOL;\r
\r
/**\r
Register a RAM disk with specified address, size and type.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_RAM_DISK_REGISTER_RAMDISK) (\r
+(EFIAPI *EFI_RAM_DISK_REGISTER_RAMDISK)(\r
IN UINT64 RamDiskBase,\r
IN UINT64 RamDiskSize,\r
IN EFI_GUID *RamDiskType,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_RAM_DISK_UNREGISTER_RAMDISK) (\r
+(EFIAPI *EFI_RAM_DISK_UNREGISTER_RAMDISK)(\r
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
);\r
\r
/// RAM Disk Protocol structure.\r
///\r
struct _EFI_RAM_DISK_PROTOCOL {\r
- EFI_RAM_DISK_REGISTER_RAMDISK Register;\r
- EFI_RAM_DISK_UNREGISTER_RAMDISK Unregister;\r
+ EFI_RAM_DISK_REGISTER_RAMDISK Register;\r
+ EFI_RAM_DISK_UNREGISTER_RAMDISK Unregister;\r
};\r
\r
///\r
/// RAM Disk Protocol GUID variable.\r
///\r
-extern EFI_GUID gEfiRamDiskProtocolGuid;\r
+extern EFI_GUID gEfiRamDiskProtocolGuid;\r
\r
#endif\r
#define EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID \\r
{ 0x27CFAC87, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } }\r
\r
-extern EFI_GUID gEfiRealTimeClockArchProtocolGuid;\r
+extern EFI_GUID gEfiRealTimeClockArchProtocolGuid;\r
\r
#endif\r
0x5db12509, 0x4550, 0x4347, { 0x96, 0xb3, 0x73, 0xc0, 0xff, 0x6e, 0x86, 0x9f } \\r
}\r
\r
-#define REDFISH_DISCOVER_TOKEN_SIGNATURE SIGNATURE_32 ('R', 'F', 'T', 'S')\r
+#define REDFISH_DISCOVER_TOKEN_SIGNATURE SIGNATURE_32 ('R', 'F', 'T', 'S')\r
\r
typedef UINT32 EFI_REDFISH_DISCOVER_FLAG;\r
-#define EFI_REDFISH_DISCOVER_HOST_INTERFACE 0x00000001 ///< Discover Redfish server reported in SMBIOS 42h.\r
-#define EFI_REDFISH_DISCOVER_SSDP 0x00000002 ///< Discover Redfish server using UPnP Http search method.\r
-#define EFI_REDFISH_DISCOVER_SSDP_UDP6 0x00000004 ///< Use UDP version 6.\r
-#define EFI_REDFISH_DISCOVER_KEEP_ALIVE 0x00000008 ///< Keep to send UPnP Search in the duration indicated in\r
- ///< EFI_REDFISH_DISCOVER_DURATION_MASK.\r
-#define EFI_REDFISH_DISCOVER_RENEW 0x00000010 ///< Set this bit to indicate this function to notify the caller\r
+#define EFI_REDFISH_DISCOVER_HOST_INTERFACE 0x00000001 ///< Discover Redfish server reported in SMBIOS 42h.\r
+#define EFI_REDFISH_DISCOVER_SSDP 0x00000002 ///< Discover Redfish server using UPnP Http search method.\r
+#define EFI_REDFISH_DISCOVER_SSDP_UDP6 0x00000004 ///< Use UDP version 6.\r
+#define EFI_REDFISH_DISCOVER_KEEP_ALIVE 0x00000008 ///< Keep to send UPnP Search in the duration indicated in\r
+ ///< EFI_REDFISH_DISCOVER_DURATION_MASK.\r
+#define EFI_REDFISH_DISCOVER_RENEW 0x00000010 ///< Set this bit to indicate this function to notify the caller\r
///< a list of all Redfish servers it found. Otherwise, this fucntion\r
///< just notify the caller new found Redfish servers.\r
///<\r
} EFI_REDFISH_DISCOVERED_INFORMATION;\r
\r
typedef struct {\r
- EFI_STATUS Status; ///< Status of Redfish service discovery.\r
- EFI_REDFISH_DISCOVERED_INFORMATION Information; ///< Redfish service discovered.\r
+ EFI_STATUS Status; ///< Status of Redfish service discovery.\r
+ EFI_REDFISH_DISCOVERED_INFORMATION Information; ///< Redfish service discovered.\r
} EFI_REDFISH_DISCOVERED_INSTANCE;\r
\r
typedef struct {\r
- UINTN NumberOfServiceFound; ///< Must be 0 when pass to Acquire ().\r
- EFI_REDFISH_DISCOVERED_INSTANCE *RedfishInstances; ///< Must be NULL when pass to Acquire ().\r
+ UINTN NumberOfServiceFound; ///< Must be 0 when pass to Acquire ().\r
+ EFI_REDFISH_DISCOVERED_INSTANCE *RedfishInstances; ///< Must be NULL when pass to Acquire ().\r
} EFI_REDFISH_DISCOVERED_LIST;\r
\r
typedef struct {\r
- EFI_MAC_ADDRESS MacAddress; ///< MAC address of network interfase to discover Redfish service.\r
- BOOLEAN IsIpv6; ///< Indicates it's IP versino 6.\r
- EFI_IP_ADDRESS SubnetId; ///< Subnet ID.\r
- UINT8 SubnetPrefixLength; ///< Subnet prefix-length for IPv4 and IPv6.\r
- UINT16 VlanId; ///< VLAN ID.\r
+ EFI_MAC_ADDRESS MacAddress; ///< MAC address of network interfase to discover Redfish service.\r
+ BOOLEAN IsIpv6; ///< Indicates it's IP versino 6.\r
+ EFI_IP_ADDRESS SubnetId; ///< Subnet ID.\r
+ UINT8 SubnetPrefixLength; ///< Subnet prefix-length for IPv4 and IPv6.\r
+ UINT16 VlanId; ///< VLAN ID.\r
} EFI_REDFISH_DISCOVER_NETWORK_INTERFACE;\r
\r
typedef struct {\r
- UINT32 Signature; ///< Token signature.\r
- EFI_REDFISH_DISCOVERED_LIST DiscoverList; ///< The memory of EFI_REDFISH_DISCOVERED_LIST is\r
- ///< allocated by Acquire() and freed when caller invoke Release().\r
- EFI_EVENT Event; ///< The TPL_CALLBACK event to be notified when Redfish services\r
- ///< are discovered or any errors occurred during discovery.\r
- UINTN Timeout; ///< The timeout value declared in EFI_REDFISH_DISCOVERED_TOKEN\r
- ///< determines the seconds to drop discover process.\r
- ///< Basically, the nearby Redfish services must response in >=1\r
- ///< and <= 5 seconds. The valid timeout value used to have\r
- ///< asynchronous discovery is >= 1 and <= 5 seconds. Set the\r
- ///< timeout to zero means to discover Redfish service synchronously.\r
- ///< Event in token is created by caller to listen the Reefish services\r
- ///< found by Acquire().\r
+ UINT32 Signature; ///< Token signature.\r
+ EFI_REDFISH_DISCOVERED_LIST DiscoverList; ///< The memory of EFI_REDFISH_DISCOVERED_LIST is\r
+ ///< allocated by Acquire() and freed when caller invoke Release().\r
+ EFI_EVENT Event; ///< The TPL_CALLBACK event to be notified when Redfish services\r
+ ///< are discovered or any errors occurred during discovery.\r
+ UINTN Timeout; ///< The timeout value declared in EFI_REDFISH_DISCOVERED_TOKEN\r
+ ///< determines the seconds to drop discover process.\r
+ ///< Basically, the nearby Redfish services must response in >=1\r
+ ///< and <= 5 seconds. The valid timeout value used to have\r
+ ///< asynchronous discovery is >= 1 and <= 5 seconds. Set the\r
+ ///< timeout to zero means to discover Redfish service synchronously.\r
+ ///< Event in token is created by caller to listen the Reefish services\r
+ ///< found by Acquire().\r
} EFI_REDFISH_DISCOVERED_TOKEN;\r
\r
/**\r
IN EFI_HANDLE ImageHandle,\r
OUT UINTN *NumberOfNetworkInterfaces,\r
OUT EFI_REDFISH_DISCOVER_NETWORK_INTERFACE **NetworkInterfaces\r
-);\r
+ );\r
\r
/**\r
This function acquires Redfish services by discovering static Redfish setting\r
IN EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL,\r
IN EFI_REDFISH_DISCOVER_FLAG Flags,\r
IN EFI_REDFISH_DISCOVERED_TOKEN *Token\r
-);\r
+ );\r
\r
/**\r
This function aborts Redfish service discovery on the given network interface.\r
(EFIAPI *EFI_REDFISH_DISCOVER_ABORT_ACQUIRE)(\r
IN EFI_REDFISH_DISCOVER_PROTOCOL *This,\r
IN EFI_REDFISH_DISCOVER_NETWORK_INTERFACE *TargetNetworkInterface OPTIONAL\r
-);\r
+ );\r
\r
/**\r
This function releases Redfish services found by RedfishServiceAcquire().\r
(EFIAPI *EFI_REDFISH_DISCOVER_RELEASE_SERVICE)(\r
IN EFI_REDFISH_DISCOVER_PROTOCOL *This,\r
IN EFI_REDFISH_DISCOVERED_LIST *List\r
-);\r
+ );\r
\r
struct _EFI_REDFISH_DISCOVER_PROTOCOL {\r
- EFI_REDFISH_DISCOVER_NETWORK_LIST GetNetworkInterfaceList;\r
- EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE AcquireRedfishService;\r
- EFI_REDFISH_DISCOVER_ABORT_ACQUIRE AbortAcquireRedfishService;\r
- EFI_REDFISH_DISCOVER_RELEASE_SERVICE ReleaseRedfishService;\r
+ EFI_REDFISH_DISCOVER_NETWORK_LIST GetNetworkInterfaceList;\r
+ EFI_REDFISH_DISCOVER_ACQUIRE_SERVICE AcquireRedfishService;\r
+ EFI_REDFISH_DISCOVER_ABORT_ACQUIRE AbortAcquireRedfishService;\r
+ EFI_REDFISH_DISCOVER_RELEASE_SERVICE ReleaseRedfishService;\r
};\r
\r
-extern EFI_GUID gEfiRedfishDiscoverProtocolGuid;\r
+extern EFI_GUID gEfiRedfishDiscoverProtocolGuid;\r
#endif\r
0x9A473A4A, 0x4CEB, 0xB95A, {0x41, 0x5E, 0x5B, 0xA0, 0xBC, 0x63, 0x9B, 0x2E } \\r
}\r
\r
-typedef struct _EFI_REGULAR_EXPRESSION_PROTOCOL EFI_REGULAR_EXPRESSION_PROTOCOL;\r
-\r
+typedef struct _EFI_REGULAR_EXPRESSION_PROTOCOL EFI_REGULAR_EXPRESSION_PROTOCOL;\r
\r
typedef struct {\r
- CONST CHAR16 *CapturePtr; // Pointer to the start of the captured sub-expression\r
- // within matched String.\r
+ CONST CHAR16 *CapturePtr; // Pointer to the start of the captured sub-expression\r
+ // within matched String.\r
\r
- UINTN Length; // Length of captured sub-expression.\r
+ UINTN Length; // Length of captured sub-expression.\r
} EFI_REGEX_CAPTURE;\r
\r
typedef EFI_GUID EFI_REGEX_SYNTAX_TYPE;\r
//\r
// Protocol member functions\r
//\r
+\r
/**\r
Returns information about the regular expression syntax types supported\r
by the implementation.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REGULAR_EXPRESSION_GET_INFO) (\r
+(EFIAPI *EFI_REGULAR_EXPRESSION_GET_INFO)(\r
IN EFI_REGULAR_EXPRESSION_PROTOCOL *This,\r
IN OUT UINTN *RegExSyntaxTypeListSize,\r
OUT EFI_REGEX_SYNTAX_TYPE *RegExSyntaxTypeList\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REGULAR_EXPRESSION_MATCH) (\r
+(EFIAPI *EFI_REGULAR_EXPRESSION_MATCH)(\r
IN EFI_REGULAR_EXPRESSION_PROTOCOL *This,\r
IN CHAR16 *String,\r
IN CHAR16 *Pattern,\r
);\r
\r
struct _EFI_REGULAR_EXPRESSION_PROTOCOL {\r
- EFI_REGULAR_EXPRESSION_MATCH MatchString;\r
- EFI_REGULAR_EXPRESSION_GET_INFO GetInfo;\r
-} ;\r
+ EFI_REGULAR_EXPRESSION_MATCH MatchString;\r
+ EFI_REGULAR_EXPRESSION_GET_INFO GetInfo;\r
+};\r
\r
-extern EFI_GUID gEfiRegularExpressionProtocolGuid;\r
+extern EFI_GUID gEfiRegularExpressionProtocolGuid;\r
\r
//\r
// For regular expression rules specified in the POSIX Extended Regular\r
// Expression (ERE) Syntax:\r
//\r
-extern EFI_GUID gEfiRegexSyntaxTypePosixExtendedGuid;\r
+extern EFI_GUID gEfiRegexSyntaxTypePosixExtendedGuid;\r
\r
//\r
// For regular expression rules specifiedin the ECMA 262 Specification\r
//\r
-extern EFI_GUID gEfiRegexSyntaxTypeEcma262Guid;\r
+extern EFI_GUID gEfiRegexSyntaxTypeEcma262Guid;\r
\r
//\r
// For regular expression rules specified in the Perl standard:\r
//\r
-extern EFI_GUID gEfiRegexSyntaxTypePerlGuid;\r
+extern EFI_GUID gEfiRegexSyntaxTypePerlGuid;\r
\r
#endif\r
IN UINT32 Instance,\r
IN EFI_GUID *CallerId,\r
IN EFI_STATUS_CODE_DATA *Data\r
-);\r
+ );\r
\r
/**\r
Register the callback function for ReportStatusCode() notification.\r
(EFIAPI *EFI_RSC_HANDLER_REGISTER)(\r
IN EFI_RSC_HANDLER_CALLBACK Callback,\r
IN EFI_TPL Tpl\r
-);\r
+ );\r
\r
/**\r
Remove a previously registered callback function from the notification list.\r
EFI_STATUS\r
(EFIAPI *EFI_RSC_HANDLER_UNREGISTER)(\r
IN EFI_RSC_HANDLER_CALLBACK Callback\r
-);\r
+ );\r
\r
typedef struct {\r
- EFI_RSC_HANDLER_REGISTER Register;\r
- EFI_RSC_HANDLER_UNREGISTER Unregister;\r
+ EFI_RSC_HANDLER_REGISTER Register;\r
+ EFI_RSC_HANDLER_UNREGISTER Unregister;\r
} EFI_RSC_HANDLER_PROTOCOL;\r
\r
-extern EFI_GUID gEfiRscHandlerProtocolGuid;\r
+extern EFI_GUID gEfiRscHandlerProtocolGuid;\r
\r
#endif // __REPORT_STATUS_CODE_HANDLER_H__\r
#define EFI_RESET_ARCH_PROTOCOL_GUID \\r
{ 0x27CFAC88, 0x46CC, 0x11d4, {0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } }\r
\r
-extern EFI_GUID gEfiResetArchProtocolGuid;\r
+extern EFI_GUID gEfiResetArchProtocolGuid;\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REGISTER_RESET_NOTIFY) (\r
+(EFIAPI *EFI_REGISTER_RESET_NOTIFY)(\r
IN EFI_RESET_NOTIFICATION_PROTOCOL *This,\r
IN EFI_RESET_SYSTEM ResetFunction\r
-);\r
+ );\r
\r
/**\r
Unregister a notification function.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_UNREGISTER_RESET_NOTIFY) (\r
+(EFIAPI *EFI_UNREGISTER_RESET_NOTIFY)(\r
IN EFI_RESET_NOTIFICATION_PROTOCOL *This,\r
IN EFI_RESET_SYSTEM ResetFunction\r
-);\r
+ );\r
\r
struct _EFI_RESET_NOTIFICATION_PROTOCOL {\r
- EFI_REGISTER_RESET_NOTIFY RegisterResetNotify;\r
- EFI_UNREGISTER_RESET_NOTIFY UnregisterResetNotify;\r
+ EFI_REGISTER_RESET_NOTIFY RegisterResetNotify;\r
+ EFI_UNREGISTER_RESET_NOTIFY UnregisterResetNotify;\r
};\r
\r
-\r
-extern EFI_GUID gEfiResetNotificationProtocolGuid;\r
+extern EFI_GUID gEfiResetNotificationProtocolGuid;\r
\r
#endif\r
-\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REST_SEND_RECEIVE) (\r
+(EFIAPI *EFI_REST_SEND_RECEIVE)(\r
IN EFI_REST_PROTOCOL *This,\r
IN EFI_HTTP_MESSAGE *RequestMessage,\r
OUT EFI_HTTP_MESSAGE *ResponseMessage\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_REST_GET_TIME) (\r
+(EFIAPI *EFI_REST_GET_TIME)(\r
IN EFI_REST_PROTOCOL *This,\r
OUT EFI_TIME *Time\r
);\r
/// interfaces that abstract HTTP access to the resources.\r
///\r
struct _EFI_REST_PROTOCOL {\r
- EFI_REST_SEND_RECEIVE SendReceive;\r
- EFI_REST_GET_TIME GetServiceTime;\r
+ EFI_REST_SEND_RECEIVE SendReceive;\r
+ EFI_REST_GET_TIME GetServiceTime;\r
};\r
\r
-extern EFI_GUID gEfiRestProtocolGuid;\r
+extern EFI_GUID gEfiRestProtocolGuid;\r
\r
#endif\r
#include <Protocol/Http.h>\r
\r
//\r
-//GUID definitions\r
+// GUID definitions\r
//\r
#define EFI_REST_EX_SERVICE_BINDING_PROTOCOL_GUID \\r
{ \\r
\r
typedef struct _EFI_REST_EX_PROTOCOL EFI_REST_EX_PROTOCOL;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_SERVICE_INFO_VER\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_SERVICE_INFO_VER\r
+// *******************************************************\r
typedef struct {\r
- UINT8 Major;\r
- UINT8 Minor;\r
+ UINT8 Major;\r
+ UINT8 Minor;\r
} EFI_REST_EX_SERVICE_INFO_VER;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_SERVICE_INFO_HEADER\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_SERVICE_INFO_HEADER\r
+// *******************************************************\r
typedef struct {\r
- UINT32 Length;\r
- EFI_REST_EX_SERVICE_INFO_VER RestServiceInfoVer;\r
+ UINT32 Length;\r
+ EFI_REST_EX_SERVICE_INFO_VER RestServiceInfoVer;\r
} EFI_REST_EX_SERVICE_INFO_HEADER;\r
\r
-//*******************************************************\r
+// *******************************************************\r
// EFI_REST_EX_SERVICE_TYPE\r
-//*******************************************************\r
+// *******************************************************\r
typedef enum {\r
EfiRestExServiceUnspecific = 1,\r
EfiRestExServiceRedfish,\r
EfiRestExServiceTypeMax\r
} EFI_REST_EX_SERVICE_TYPE;\r
\r
-//*******************************************************\r
+// *******************************************************\r
// EFI_REST_EX_SERVICE_ACCESS_MODE\r
-//*******************************************************\r
+// *******************************************************\r
typedef enum {\r
- EfiRestExServiceInBandAccess = 1,\r
+ EfiRestExServiceInBandAccess = 1,\r
EfiRestExServiceOutOfBandAccess = 2,\r
EfiRestExServiceModeMax\r
} EFI_REST_EX_SERVICE_ACCESS_MODE;\r
\r
-//*******************************************************\r
+// *******************************************************\r
// EFI_REST_EX_CONFIG_TYPE\r
-//*******************************************************\r
+// *******************************************************\r
typedef enum {\r
EfiRestExConfigHttp,\r
EfiRestExConfigUnspecific,\r
EfiRestExConfigTypeMax\r
} EFI_REST_EX_CONFIG_TYPE;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_SERVICE_INFO v1.0\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_SERVICE_INFO v1.0\r
+// *******************************************************\r
typedef struct {\r
- EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader;\r
- EFI_REST_EX_SERVICE_TYPE RestServiceType;\r
- EFI_REST_EX_SERVICE_ACCESS_MODE RestServiceAccessMode;\r
- EFI_GUID VendorRestServiceName;\r
- UINT32 VendorSpecificDataLength;\r
- UINT8 *VendorSpecifcData;\r
- EFI_REST_EX_CONFIG_TYPE RestExConfigType;\r
- UINT8 RestExConfigDataLength;\r
+ EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader;\r
+ EFI_REST_EX_SERVICE_TYPE RestServiceType;\r
+ EFI_REST_EX_SERVICE_ACCESS_MODE RestServiceAccessMode;\r
+ EFI_GUID VendorRestServiceName;\r
+ UINT32 VendorSpecificDataLength;\r
+ UINT8 *VendorSpecifcData;\r
+ EFI_REST_EX_CONFIG_TYPE RestExConfigType;\r
+ UINT8 RestExConfigDataLength;\r
} EFI_REST_EX_SERVICE_INFO_V_1_0;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_SERVICE_INFO\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_SERVICE_INFO\r
+// *******************************************************\r
typedef union {\r
- EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader;\r
- EFI_REST_EX_SERVICE_INFO_V_1_0 EfiRestExServiceInfoV10;\r
+ EFI_REST_EX_SERVICE_INFO_HEADER EfiRestExServiceInfoHeader;\r
+ EFI_REST_EX_SERVICE_INFO_V_1_0 EfiRestExServiceInfoV10;\r
} EFI_REST_EX_SERVICE_INFO;\r
\r
-//*******************************************************\r
+// *******************************************************\r
// EFI_REST_EX_HTTP_CONFIG_DATA\r
-//*******************************************************\r
+// *******************************************************\r
typedef struct {\r
EFI_HTTP_CONFIG_DATA HttpConfigData;\r
UINT32 SendReceiveTimeout;\r
} EFI_REST_EX_HTTP_CONFIG_DATA;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_CONFIG_DATA\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_CONFIG_DATA\r
+// *******************************************************\r
typedef UINT8 *EFI_REST_EX_CONFIG_DATA;\r
\r
-//*******************************************************\r
-//EFI_REST_EX_TOKEN\r
-//*******************************************************\r
+// *******************************************************\r
+// EFI_REST_EX_TOKEN\r
+// *******************************************************\r
typedef struct {\r
- EFI_EVENT Event;\r
- EFI_STATUS Status;\r
- EFI_HTTP_MESSAGE *ResponseMessage;\r
+ EFI_EVENT Event;\r
+ EFI_STATUS Status;\r
+ EFI_HTTP_MESSAGE *ResponseMessage;\r
} EFI_REST_EX_TOKEN;\r
\r
/**\r
IN EFI_REST_EX_PROTOCOL *This,\r
IN EFI_HTTP_MESSAGE *RequestMessage OPTIONAL,\r
IN EFI_REST_EX_TOKEN *RestExToken\r
-);\r
+ );\r
\r
///\r
/// EFI REST(EX) protocols are designed to support REST communication between EFI REST client\r
/// interface after the corresponding configuration is initialized.\r
///\r
struct _EFI_REST_EX_PROTOCOL {\r
- EFI_REST_SEND_RECEIVE SendReceive;\r
- EFI_REST_GET_TIME GetServiceTime;\r
- EFI_REST_EX_GET_SERVICE GetService;\r
- EFI_REST_EX_GET_MODE_DATA GetModeData;\r
- EFI_REST_EX_CONFIGURE Configure;\r
- EFI_REST_EX_ASYNC_SEND_RECEIVE AyncSendReceive;\r
- EFI_REST_EX_EVENT_SERVICE EventService;\r
+ EFI_REST_SEND_RECEIVE SendReceive;\r
+ EFI_REST_GET_TIME GetServiceTime;\r
+ EFI_REST_EX_GET_SERVICE GetService;\r
+ EFI_REST_EX_GET_MODE_DATA GetModeData;\r
+ EFI_REST_EX_CONFIGURE Configure;\r
+ EFI_REST_EX_ASYNC_SEND_RECEIVE AyncSendReceive;\r
+ EFI_REST_EX_EVENT_SERVICE EventService;\r
};\r
\r
-extern EFI_GUID gEfiRestExServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiRestExProtocolGuid;\r
+extern EFI_GUID gEfiRestExServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiRestExProtocolGuid;\r
\r
#endif\r
0xa9a048f6, 0x48a0, 0x4714, {0xb7, 0xda, 0xa9, 0xad,0x87, 0xd4, 0xda, 0xc9 } \\r
}\r
\r
-typedef struct _EFI_REST_JSON_STRUCTURE_PROTOCOL EFI_REST_JSON_STRUCTURE_PROTOCOL;\r
-typedef CHAR8 * EFI_REST_JSON_RESOURCE_TYPE_DATATYPE;\r
+typedef struct _EFI_REST_JSON_STRUCTURE_PROTOCOL EFI_REST_JSON_STRUCTURE_PROTOCOL;\r
+typedef CHAR8 *EFI_REST_JSON_RESOURCE_TYPE_DATATYPE;\r
\r
///\r
/// Structure defintions of resource name space.\r
/// REST API.\r
///\r
typedef struct _EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE {\r
- CHAR8 *ResourceTypeName; ///< Resource type name\r
- CHAR8 *MajorVersion; ///< Resource major version\r
- CHAR8 *MinorVersion; ///< Resource minor version\r
- CHAR8 *ErrataVersion; ///< Resource errata version\r
+ CHAR8 *ResourceTypeName; ///< Resource type name\r
+ CHAR8 *MajorVersion; ///< Resource major version\r
+ CHAR8 *MinorVersion; ///< Resource minor version\r
+ CHAR8 *ErrataVersion; ///< Resource errata version\r
} EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE;\r
\r
///\r
/// REST resource type consists of name space and data type.\r
///\r
typedef struct _EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER {\r
- EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE NameSpace; ///< Namespace of this resource type.\r
- EFI_REST_JSON_RESOURCE_TYPE_DATATYPE DataType; ///< Name of data type declared in this\r
- ///< resource type.\r
+ EFI_REST_JSON_RESOURCE_TYPE_NAMESPACE NameSpace; ///< Namespace of this resource type.\r
+ EFI_REST_JSON_RESOURCE_TYPE_DATATYPE DataType; ///< Name of data type declared in this\r
+ ///< resource type.\r
} EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER;\r
\r
///\r
/// List of JSON to C structure conversions which this convertor supports.\r
///\r
typedef struct _EFI_REST_JSON_STRUCTURE_SUPPORTED {\r
- LIST_ENTRY NextSupportedRsrcInterp; ///< Linklist to next supported conversion.\r
- EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER RestResourceInterp; ///< JSON resource type this convertor supports.\r
+ LIST_ENTRY NextSupportedRsrcInterp; ///< Linklist to next supported conversion.\r
+ EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER RestResourceInterp; ///< JSON resource type this convertor supports.\r
} EFI_REST_JSON_STRUCTURE_SUPPORTED;\r
\r
///\r
///< choice the proper interpreter.\r
///< Follow by a pointer points to JSON structure, the content in the\r
///< JSON structure is implementation-specific according to converter producer.\r
- VOID *JsonStructurePointer;\r
+ VOID *JsonStructurePointer;\r
} EFI_REST_JSON_STRUCTURE_HEADER;\r
\r
/**\r
IN EFI_REST_JSON_RESOURCE_TYPE_IDENTIFIER *JsonRsrcIdentifier OPTIONAL,\r
IN CHAR8 *ResourceJsonText,\r
OUT EFI_REST_JSON_STRUCTURE_HEADER **JsonStructure\r
-);\r
+ );\r
\r
/**\r
Convert the given REST JSON structure into JSON text.\r
IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This,\r
IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader,\r
OUT CHAR8 **ResourceJsonText\r
-);\r
+ );\r
\r
/**\r
This function destroys the REST JSON structure.\r
(EFIAPI *EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE)(\r
IN EFI_REST_JSON_STRUCTURE_PROTOCOL *This,\r
IN EFI_REST_JSON_STRUCTURE_HEADER *JsonStructureHeader\r
-);\r
+ );\r
+\r
/**\r
This function provides REST JSON resource to structure converter registration.\r
\r
IN EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure,\r
IN EFI_REST_JSON_STRUCTURE_TO_JSON ToJson,\r
IN EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestroyStructure\r
-);\r
+ );\r
\r
///\r
/// EFI REST JSON to C structure protocol definition.\r
///\r
struct _EFI_REST_JSON_STRUCTURE_PROTOCOL {\r
- EFI_REST_JSON_STRUCTURE_REGISTER Register; ///< Register JSON to C structure convertor\r
- EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure; ///< The function to convert JSON to C structure\r
- EFI_REST_JSON_STRUCTURE_TO_JSON ToJson; ///< The function to convert C structure to JSON\r
- EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestoryStructure; ///< Destory C structure.\r
+ EFI_REST_JSON_STRUCTURE_REGISTER Register; ///< Register JSON to C structure convertor\r
+ EFI_REST_JSON_STRUCTURE_TO_STRUCTURE ToStructure; ///< The function to convert JSON to C structure\r
+ EFI_REST_JSON_STRUCTURE_TO_JSON ToJson; ///< The function to convert C structure to JSON\r
+ EFI_REST_JSON_STRUCTURE_DESTORY_STRUCTURE DestoryStructure; ///< Destory C structure.\r
};\r
\r
#endif\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_RNG_GET_INFO) (\r
+(EFIAPI *EFI_RNG_GET_INFO)(\r
IN EFI_RNG_PROTOCOL *This,\r
IN OUT UINTN *RNGAlgorithmListSize,\r
OUT EFI_RNG_ALGORITHM *RNGAlgorithmList\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_RNG_GET_RNG) (\r
+(EFIAPI *EFI_RNG_GET_RNG)(\r
IN EFI_RNG_PROTOCOL *This,\r
IN EFI_RNG_ALGORITHM *RNGAlgorithm OPTIONAL,\r
IN UINTN RNGValueLength,\r
/// applications, or entropy for seeding other random number generators.\r
///\r
struct _EFI_RNG_PROTOCOL {\r
- EFI_RNG_GET_INFO GetInfo;\r
- EFI_RNG_GET_RNG GetRNG;\r
+ EFI_RNG_GET_INFO GetInfo;\r
+ EFI_RNG_GET_RNG GetRNG;\r
};\r
\r
-extern EFI_GUID gEfiRngProtocolGuid;\r
-extern EFI_GUID gEfiRngAlgorithmSp80090Hash256Guid;\r
-extern EFI_GUID gEfiRngAlgorithmSp80090Hmac256Guid;\r
-extern EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid;\r
-extern EFI_GUID gEfiRngAlgorithmX9313DesGuid;\r
-extern EFI_GUID gEfiRngAlgorithmX931AesGuid;\r
-extern EFI_GUID gEfiRngAlgorithmRaw;\r
+extern EFI_GUID gEfiRngProtocolGuid;\r
+extern EFI_GUID gEfiRngAlgorithmSp80090Hash256Guid;\r
+extern EFI_GUID gEfiRngAlgorithmSp80090Hmac256Guid;\r
+extern EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid;\r
+extern EFI_GUID gEfiRngAlgorithmX9313DesGuid;\r
+extern EFI_GUID gEfiRngAlgorithmX931AesGuid;\r
+extern EFI_GUID gEfiRngAlgorithmRaw;\r
\r
#endif\r
#define EFI_RUNTIME_ARCH_PROTOCOL_GUID \\r
{ 0xb7dfb4e1, 0x52f, 0x449f, {0x87, 0xbe, 0x98, 0x18, 0xfc, 0x91, 0xb7, 0x33 } }\r
\r
-typedef struct _EFI_RUNTIME_ARCH_PROTOCOL EFI_RUNTIME_ARCH_PROTOCOL;\r
+typedef struct _EFI_RUNTIME_ARCH_PROTOCOL EFI_RUNTIME_ARCH_PROTOCOL;\r
\r
///\r
/// LIST_ENTRY from BaseType\r
///\r
typedef LIST_ENTRY EFI_LIST_ENTRY;\r
\r
-typedef struct _EFI_RUNTIME_IMAGE_ENTRY EFI_RUNTIME_IMAGE_ENTRY;\r
+typedef struct _EFI_RUNTIME_IMAGE_ENTRY EFI_RUNTIME_IMAGE_ENTRY;\r
\r
///\r
/// EFI_RUNTIME_IMAGE_ENTRY\r
/// Start of image that has been loaded in memory. It is a pointer\r
/// to either the DOS header or PE header of the image.\r
///\r
- VOID *ImageBase;\r
+ VOID *ImageBase;\r
///\r
/// Size in bytes of the image represented by ImageBase.\r
///\r
- UINT64 ImageSize;\r
+ UINT64 ImageSize;\r
///\r
/// Information about the fix-ups that were performed on ImageBase when it was\r
/// loaded into memory.\r
///\r
- VOID *RelocationData;\r
+ VOID *RelocationData;\r
///\r
/// The ImageHandle passed into ImageBase when it was loaded.\r
///\r
- EFI_HANDLE Handle;\r
+ EFI_HANDLE Handle;\r
///\r
/// Entry for this node in the EFI_RUNTIME_ARCHITECTURE_PROTOCOL.ImageHead list.\r
///\r
- EFI_LIST_ENTRY Link;\r
+ EFI_LIST_ENTRY Link;\r
};\r
\r
-typedef struct _EFI_RUNTIME_EVENT_ENTRY EFI_RUNTIME_EVENT_ENTRY;\r
+typedef struct _EFI_RUNTIME_EVENT_ENTRY EFI_RUNTIME_EVENT_ENTRY;\r
\r
///\r
/// EFI_RUNTIME_EVENT_ENTRY\r
///\r
/// The same as Type passed into CreateEvent().\r
///\r
- UINT32 Type;\r
+ UINT32 Type;\r
///\r
/// The same as NotifyTpl passed into CreateEvent().\r
///\r
- EFI_TPL NotifyTpl;\r
+ EFI_TPL NotifyTpl;\r
///\r
/// The same as NotifyFunction passed into CreateEvent().\r
///\r
- EFI_EVENT_NOTIFY NotifyFunction;\r
+ EFI_EVENT_NOTIFY NotifyFunction;\r
///\r
/// The same as NotifyContext passed into CreateEvent().\r
///\r
- VOID *NotifyContext;\r
+ VOID *NotifyContext;\r
///\r
/// The EFI_EVENT returned by CreateEvent(). Event must be in runtime memory.\r
///\r
- EFI_EVENT *Event;\r
+ EFI_EVENT *Event;\r
///\r
/// Entry for this node in the\r
/// EFI_RUNTIME_ARCHITECTURE_PROTOCOL.EventHead list.\r
///\r
- EFI_LIST_ENTRY Link;\r
+ EFI_LIST_ENTRY Link;\r
};\r
\r
///\r
/// by a runtime DXE driver and may only be consumed by the DXE Foundation.\r
///\r
struct _EFI_RUNTIME_ARCH_PROTOCOL {\r
- EFI_LIST_ENTRY ImageHead; ///< A list of type EFI_RUNTIME_IMAGE_ENTRY.\r
- EFI_LIST_ENTRY EventHead; ///< A list of type EFI_RUNTIME_EVENT_ENTRY.\r
- UINTN MemoryDescriptorSize; ///< Size of a memory descriptor that is returned by GetMemoryMap().\r
- UINT32 MemoryDesciptorVersion; ///< Version of a memory descriptor that is returned by GetMemoryMap().\r
- UINTN MemoryMapSize;///< Size of the memory map in bytes contained in MemoryMapPhysical and MemoryMapVirtual.\r
- EFI_MEMORY_DESCRIPTOR *MemoryMapPhysical; ///< Pointer to a runtime buffer that contains a copy of\r
- ///< the memory map returned via GetMemoryMap().\r
- EFI_MEMORY_DESCRIPTOR *MemoryMapVirtual; ///< Pointer to MemoryMapPhysical that is updated to virtual mode after SetVirtualAddressMap().\r
- BOOLEAN VirtualMode; ///< Boolean that is TRUE if SetVirtualAddressMap() has been called.\r
- BOOLEAN AtRuntime; ///< Boolean that is TRUE if ExitBootServices () has been called.\r
+ EFI_LIST_ENTRY ImageHead; ///< A list of type EFI_RUNTIME_IMAGE_ENTRY.\r
+ EFI_LIST_ENTRY EventHead; ///< A list of type EFI_RUNTIME_EVENT_ENTRY.\r
+ UINTN MemoryDescriptorSize; ///< Size of a memory descriptor that is returned by GetMemoryMap().\r
+ UINT32 MemoryDesciptorVersion; ///< Version of a memory descriptor that is returned by GetMemoryMap().\r
+ UINTN MemoryMapSize; ///< Size of the memory map in bytes contained in MemoryMapPhysical and MemoryMapVirtual.\r
+ EFI_MEMORY_DESCRIPTOR *MemoryMapPhysical; ///< Pointer to a runtime buffer that contains a copy of\r
+ ///< the memory map returned via GetMemoryMap().\r
+ EFI_MEMORY_DESCRIPTOR *MemoryMapVirtual; ///< Pointer to MemoryMapPhysical that is updated to virtual mode after SetVirtualAddressMap().\r
+ BOOLEAN VirtualMode; ///< Boolean that is TRUE if SetVirtualAddressMap() has been called.\r
+ BOOLEAN AtRuntime; ///< Boolean that is TRUE if ExitBootServices () has been called.\r
};\r
\r
-extern EFI_GUID gEfiRuntimeArchProtocolGuid;\r
+extern EFI_GUID gEfiRuntimeArchProtocolGuid;\r
\r
#endif\r
#define EFI_S3_SAVE_STATE_PROTOCOL_GUID \\r
{ 0xe857caf6, 0xc046, 0x45dc, { 0xbe, 0x3f, 0xee, 0x7, 0x65, 0xfb, 0xa8, 0x87 }}\r
\r
-\r
typedef VOID *EFI_S3_BOOT_SCRIPT_POSITION;\r
\r
-typedef struct _EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL;\r
+typedef struct _EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL;\r
\r
/**\r
Record operations that need to be replayed during an S3 resume.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_S3_SAVE_STATE_WRITE)(\r
- IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
- IN UINTN OpCode,\r
- ...\r
-);\r
+ IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
+ IN UINTN OpCode,\r
+ ...\r
+ );\r
\r
/**\r
Record operations that need to be replayed during an S3 resume.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_S3_SAVE_STATE_INSERT)(\r
- IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
- IN BOOLEAN BeforeOrAfter,\r
- IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL,\r
- IN UINTN OpCode,\r
- ...\r
-);\r
+ IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL,\r
+ IN UINTN OpCode,\r
+ ...\r
+ );\r
\r
/**\r
Find a label within the boot script table and, if not present, optionally create it.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_S3_SAVE_STATE_LABEL)(\r
- IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
- IN BOOLEAN BeforeOrAfter,\r
- IN BOOLEAN CreateIfNotFound,\r
- IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL,\r
- IN CONST CHAR8 *Label\r
-);\r
+ IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN BOOLEAN CreateIfNotFound,\r
+ IN OUT EFI_S3_BOOT_SCRIPT_POSITION *Position OPTIONAL,\r
+ IN CONST CHAR8 *Label\r
+ );\r
\r
/**\r
Compare two positions in the boot script table and return their relative position.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_S3_SAVE_STATE_COMPARE)(\r
- IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
- IN EFI_S3_BOOT_SCRIPT_POSITION Position1,\r
- IN EFI_S3_BOOT_SCRIPT_POSITION Position2,\r
- OUT UINTN *RelativePosition\r
-);\r
+ IN CONST EFI_S3_SAVE_STATE_PROTOCOL *This,\r
+ IN EFI_S3_BOOT_SCRIPT_POSITION Position1,\r
+ IN EFI_S3_BOOT_SCRIPT_POSITION Position2,\r
+ OUT UINTN *RelativePosition\r
+ );\r
\r
struct _EFI_S3_SAVE_STATE_PROTOCOL {\r
- EFI_S3_SAVE_STATE_WRITE Write;\r
- EFI_S3_SAVE_STATE_INSERT Insert;\r
- EFI_S3_SAVE_STATE_LABEL Label;\r
- EFI_S3_SAVE_STATE_COMPARE Compare;\r
+ EFI_S3_SAVE_STATE_WRITE Write;\r
+ EFI_S3_SAVE_STATE_INSERT Insert;\r
+ EFI_S3_SAVE_STATE_LABEL Label;\r
+ EFI_S3_SAVE_STATE_COMPARE Compare;\r
};\r
\r
-extern EFI_GUID gEfiS3SaveStateProtocolGuid;\r
+extern EFI_GUID gEfiS3SaveStateProtocolGuid;\r
\r
#endif // __S3_SAVE_STATE_H__\r
#define EFI_S3_SMM_SAVE_STATE_PROTOCOL_GUID \\r
{0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, 0xf4, 0xaf, 0x1, 0x4c }}\r
\r
-\r
typedef EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SMM_SAVE_STATE_PROTOCOL;\r
\r
-extern EFI_GUID gEfiS3SmmSaveStateProtocolGuid;\r
+extern EFI_GUID gEfiS3SmmSaveStateProtocolGuid;\r
\r
#endif // __S3_SMM_SAVE_STATE_H__\r
-\r
//\r
// SCSI Device type information, defined in the SCSI Primary Commands standard (e.g., SPC-4)\r
//\r
-#define EFI_SCSI_IO_TYPE_DISK 0x00 ///< Disk device\r
-#define EFI_SCSI_IO_TYPE_TAPE 0x01 ///< Tape device\r
-#define EFI_SCSI_IO_TYPE_PRINTER 0x02 ///< Printer\r
-#define EFI_SCSI_IO_TYPE_PROCESSOR 0x03 ///< Processor\r
-#define EFI_SCSI_IO_TYPE_WORM 0x04 ///< Write-once read-multiple\r
-#define EFI_SCSI_IO_TYPE_CDROM 0x05 ///< CD or DVD device\r
-#define EFI_SCSI_IO_TYPE_SCANNER 0x06 ///< Scanner device\r
-#define EFI_SCSI_IO_TYPE_OPTICAL 0x07 ///< Optical memory device\r
-#define EFI_SCSI_IO_TYPE_MEDIUMCHANGER 0x08 ///< Medium Changer device\r
-#define EFI_SCSI_IO_TYPE_COMMUNICATION 0x09 ///< Communications device\r
-#define MFI_SCSI_IO_TYPE_A 0x0A ///< Obsolete\r
-#define MFI_SCSI_IO_TYPE_B 0x0B ///< Obsolete\r
-#define MFI_SCSI_IO_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)\r
-#define MFI_SCSI_IO_TYPE_SES 0x0D ///< Enclosure services device\r
-#define MFI_SCSI_IO_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)\r
-#define MFI_SCSI_IO_TYPE_OCRW 0x0F ///< Optical card reader/writer device\r
-#define MFI_SCSI_IO_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands\r
-#define MFI_SCSI_IO_TYPE_OSD 0x11 ///< Object-based Storage Device\r
-#define EFI_SCSI_IO_TYPE_RESERVED_LOW 0x12 ///< Reserved (low)\r
-#define EFI_SCSI_IO_TYPE_RESERVED_HIGH 0x1E ///< Reserved (high)\r
-#define EFI_SCSI_IO_TYPE_UNKNOWN 0x1F ///< Unknown no device type\r
+#define EFI_SCSI_IO_TYPE_DISK 0x00 ///< Disk device\r
+#define EFI_SCSI_IO_TYPE_TAPE 0x01 ///< Tape device\r
+#define EFI_SCSI_IO_TYPE_PRINTER 0x02 ///< Printer\r
+#define EFI_SCSI_IO_TYPE_PROCESSOR 0x03 ///< Processor\r
+#define EFI_SCSI_IO_TYPE_WORM 0x04 ///< Write-once read-multiple\r
+#define EFI_SCSI_IO_TYPE_CDROM 0x05 ///< CD or DVD device\r
+#define EFI_SCSI_IO_TYPE_SCANNER 0x06 ///< Scanner device\r
+#define EFI_SCSI_IO_TYPE_OPTICAL 0x07 ///< Optical memory device\r
+#define EFI_SCSI_IO_TYPE_MEDIUMCHANGER 0x08 ///< Medium Changer device\r
+#define EFI_SCSI_IO_TYPE_COMMUNICATION 0x09 ///< Communications device\r
+#define MFI_SCSI_IO_TYPE_A 0x0A ///< Obsolete\r
+#define MFI_SCSI_IO_TYPE_B 0x0B ///< Obsolete\r
+#define MFI_SCSI_IO_TYPE_RAID 0x0C ///< Storage array controller device (e.g., RAID)\r
+#define MFI_SCSI_IO_TYPE_SES 0x0D ///< Enclosure services device\r
+#define MFI_SCSI_IO_TYPE_RBC 0x0E ///< Simplified direct-access device (e.g., magnetic disk)\r
+#define MFI_SCSI_IO_TYPE_OCRW 0x0F ///< Optical card reader/writer device\r
+#define MFI_SCSI_IO_TYPE_BRIDGE 0x10 ///< Bridge Controller Commands\r
+#define MFI_SCSI_IO_TYPE_OSD 0x11 ///< Object-based Storage Device\r
+#define EFI_SCSI_IO_TYPE_RESERVED_LOW 0x12 ///< Reserved (low)\r
+#define EFI_SCSI_IO_TYPE_RESERVED_HIGH 0x1E ///< Reserved (high)\r
+#define EFI_SCSI_IO_TYPE_UNKNOWN 0x1F ///< Unknown no device type\r
\r
//\r
// SCSI Data Direction definition\r
//\r
-#define EFI_SCSI_IO_DATA_DIRECTION_READ 0\r
-#define EFI_SCSI_IO_DATA_DIRECTION_WRITE 1\r
-#define EFI_SCSI_IO_DATA_DIRECTION_BIDIRECTIONAL 2\r
+#define EFI_SCSI_IO_DATA_DIRECTION_READ 0\r
+#define EFI_SCSI_IO_DATA_DIRECTION_WRITE 1\r
+#define EFI_SCSI_IO_DATA_DIRECTION_BIDIRECTIONAL 2\r
\r
//\r
// SCSI Host Adapter Status definition\r
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14 ///< Target bus phase sequence failure\r
#define EFI_SCSI_IO_STATUS_HOST_ADAPTER_OTHER 0x7f\r
\r
-\r
//\r
// SCSI Target Status definition\r
//\r
-#define EFI_SCSI_IO_STATUS_TARGET_GOOD 0x00\r
-#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02 ///< check condition\r
-#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04 ///< condition met\r
-#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08 ///< busy\r
-#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10 ///< intermediate\r
-#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 ///< intermediate-condition met\r
-#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18 ///< reservation conflict\r
-#define EFI_SCSI_IO_STATUS_TARGET_COMMOND_TERMINATED 0x22 ///< command terminated\r
-#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28 ///< queue full\r
+#define EFI_SCSI_IO_STATUS_TARGET_GOOD 0x00\r
+#define EFI_SCSI_IO_STATUS_TARGET_CHECK_CONDITION 0x02 ///< check condition\r
+#define EFI_SCSI_IO_STATUS_TARGET_CONDITION_MET 0x04 ///< condition met\r
+#define EFI_SCSI_IO_STATUS_TARGET_BUSY 0x08 ///< busy\r
+#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE 0x10 ///< intermediate\r
+#define EFI_SCSI_IO_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 ///< intermediate-condition met\r
+#define EFI_SCSI_IO_STATUS_TARGET_RESERVATION_CONFLICT 0x18 ///< reservation conflict\r
+#define EFI_SCSI_IO_STATUS_TARGET_COMMOND_TERMINATED 0x22 ///< command terminated\r
+#define EFI_SCSI_IO_STATUS_TARGET_QUEUE_FULL 0x28 ///< queue full\r
\r
typedef struct {\r
///\r
/// EFI_TIMEOUT if the time required to execute the SCSI Request\r
/// Packet is greater than Timeout.\r
///\r
- UINT64 Timeout;\r
+ UINT64 Timeout;\r
///\r
/// A pointer to the data buffer to transfer between the SCSI\r
/// controller and the SCSI device for SCSI READ command\r
///\r
- VOID *InDataBuffer;\r
+ VOID *InDataBuffer;\r
///\r
/// A pointer to the data buffer to transfer between the SCSI\r
/// controller and the SCSI device for SCSI WRITE command.\r
///\r
- VOID *OutDataBuffer;\r
+ VOID *OutDataBuffer;\r
///\r
/// A pointer to the sense data that was generated by the execution of\r
/// the SCSI Request Packet.\r
///\r
- VOID *SenseData;\r
+ VOID *SenseData;\r
///\r
/// A pointer to buffer that contains the Command Data Block to\r
/// send to the SCSI device.\r
///\r
- VOID *Cdb;\r
+ VOID *Cdb;\r
///\r
/// On Input, the size, in bytes, of InDataBuffer. On output, the\r
/// number of bytes transferred between the SCSI controller and the SCSI device.\r
///\r
- UINT32 InTransferLength;\r
+ UINT32 InTransferLength;\r
///\r
/// On Input, the size, in bytes of OutDataBuffer. On Output, the\r
/// Number of bytes transferred between SCSI Controller and the SCSI device.\r
///\r
- UINT32 OutTransferLength;\r
+ UINT32 OutTransferLength;\r
///\r
/// The length, in bytes, of the buffer Cdb. The standard values are\r
/// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used.\r
///\r
- UINT8 CdbLength;\r
+ UINT8 CdbLength;\r
///\r
/// The direction of the data transfer. 0 for reads, 1 for writes. A\r
/// value of 2 is Reserved for Bi-Directional SCSI commands.\r
///\r
- UINT8 DataDirection;\r
+ UINT8 DataDirection;\r
///\r
/// The status of the SCSI Host Controller that produces the SCSI\r
/// bus where the SCSI device attached when the SCSI Request\r
/// Packet was executed on the SCSI Controller.\r
///\r
- UINT8 HostAdapterStatus;\r
+ UINT8 HostAdapterStatus;\r
///\r
/// The status returned by the SCSI device when the SCSI Request\r
/// Packet was executed.\r
///\r
- UINT8 TargetStatus;\r
+ UINT8 TargetStatus;\r
///\r
/// On input, the length in bytes of the SenseData buffer. On\r
/// output, the number of bytes written to the SenseData buffer.\r
///\r
- UINT8 SenseDataLength;\r
+ UINT8 SenseDataLength;\r
} EFI_SCSI_IO_SCSI_REQUEST_PACKET;\r
\r
/**\r
IN EFI_SCSI_IO_PROTOCOL *This\r
);\r
\r
-\r
/**\r
Sends a SCSI Request Packet to the SCSI Controller for execution.\r
\r
/// Provides services to manage and communicate with SCSI devices.\r
///\r
struct _EFI_SCSI_IO_PROTOCOL {\r
- EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE GetDeviceType;\r
- EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION GetDeviceLocation;\r
- EFI_SCSI_IO_PROTOCOL_RESET_BUS ResetBus;\r
- EFI_SCSI_IO_PROTOCOL_RESET_DEVICE ResetDevice;\r
- EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND ExecuteScsiCommand;\r
+ EFI_SCSI_IO_PROTOCOL_GET_DEVICE_TYPE GetDeviceType;\r
+ EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION GetDeviceLocation;\r
+ EFI_SCSI_IO_PROTOCOL_RESET_BUS ResetBus;\r
+ EFI_SCSI_IO_PROTOCOL_RESET_DEVICE ResetDevice;\r
+ EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND ExecuteScsiCommand;\r
\r
///\r
/// Supplies the alignment requirement for any buffer used in a data transfer.\r
/// Otherwise, IoAlign must be a power of 2, and the requirement is that the\r
/// start address of a buffer must be evenly divisible by IoAlign with no remainder.\r
///\r
- UINT32 IoAlign;\r
+ UINT32 IoAlign;\r
};\r
\r
-extern EFI_GUID gEfiScsiIoProtocolGuid;\r
+extern EFI_GUID gEfiScsiIoProtocolGuid;\r
\r
#endif\r
///\r
/// Forward reference for pure ANSI compatability\r
///\r
-typedef struct _EFI_SCSI_PASS_THRU_PROTOCOL EFI_SCSI_PASS_THRU_PROTOCOL;\r
+typedef struct _EFI_SCSI_PASS_THRU_PROTOCOL EFI_SCSI_PASS_THRU_PROTOCOL;\r
\r
#define EFI_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
#define EFI_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
//\r
// SCSI Target Status definition\r
//\r
-#define EFI_SCSI_STATUS_TARGET_GOOD 0x00\r
-#define EFI_SCSI_STATUS_TARGET_CHECK_CONDITION 0x02 // check condition\r
-#define EFI_SCSI_STATUS_TARGET_CONDITION_MET 0x04 // condition met\r
-#define EFI_SCSI_STATUS_TARGET_BUSY 0x08 // busy\r
-#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE 0x10 // intermediate\r
-#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 // intermediate-condition met\r
-#define EFI_SCSI_STATUS_TARGET_RESERVATION_CONFLICT 0x18 // reservation conflict\r
-#define EFI_SCSI_STATUS_TARGET_COMMOND_TERMINATED 0x22 // command terminated\r
-#define EFI_SCSI_STATUS_TARGET_QUEUE_FULL 0x28 // queue full\r
+#define EFI_SCSI_STATUS_TARGET_GOOD 0x00\r
+#define EFI_SCSI_STATUS_TARGET_CHECK_CONDITION 0x02 // check condition\r
+#define EFI_SCSI_STATUS_TARGET_CONDITION_MET 0x04 // condition met\r
+#define EFI_SCSI_STATUS_TARGET_BUSY 0x08 // busy\r
+#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE 0x10 // intermediate\r
+#define EFI_SCSI_STATUS_TARGET_INTERMEDIATE_CONDITION_MET 0x14 // intermediate-condition met\r
+#define EFI_SCSI_STATUS_TARGET_RESERVATION_CONFLICT 0x18 // reservation conflict\r
+#define EFI_SCSI_STATUS_TARGET_COMMOND_TERMINATED 0x22 // command terminated\r
+#define EFI_SCSI_STATUS_TARGET_QUEUE_FULL 0x28 // queue full\r
\r
typedef struct {\r
///\r
/// EFI_TIMEOUT if the time required to execute the SCSI Request\r
/// Packet is greater than Timeout.\r
///\r
- UINT64 Timeout;\r
+ UINT64 Timeout;\r
///\r
/// A pointer to the data buffer to transfer between the SCSI\r
/// controller and the SCSI device. Must be aligned to the boundary\r
/// specified in the IoAlign field of the\r
/// EFI_SCSI_PASS_THRU_MODE structure.\r
///\r
- VOID *DataBuffer;\r
+ VOID *DataBuffer;\r
///\r
/// A pointer to the sense data that was generated by the execution of\r
/// the SCSI Request Packet.\r
///\r
- VOID *SenseData;\r
+ VOID *SenseData;\r
///\r
/// A pointer to buffer that contains the Command Data Block to\r
/// send to the SCSI device.\r
///\r
- VOID *Cdb;\r
+ VOID *Cdb;\r
///\r
/// On Input, the size, in bytes, of InDataBuffer. On output, the\r
/// number of bytes transferred between the SCSI controller and the SCSI device.\r
///\r
- UINT32 TransferLength;\r
+ UINT32 TransferLength;\r
///\r
/// The length, in bytes, of the buffer Cdb. The standard values are\r
/// 6, 10, 12, and 16, but other values are possible if a variable length CDB is used.\r
///\r
- UINT8 CdbLength;\r
+ UINT8 CdbLength;\r
///\r
/// The direction of the data transfer. 0 for reads, 1 for writes. A\r
/// value of 2 is Reserved for Bi-Directional SCSI commands.\r
///\r
- UINT8 DataDirection;\r
+ UINT8 DataDirection;\r
///\r
/// The status of the SCSI Host Controller that produces the SCSI\r
/// bus where the SCSI device attached when the SCSI Request\r
/// Packet was executed on the SCSI Controller.\r
///\r
- UINT8 HostAdapterStatus;\r
+ UINT8 HostAdapterStatus;\r
///\r
/// The status returned by the SCSI device when the SCSI Request\r
/// Packet was executed.\r
///\r
- UINT8 TargetStatus;\r
+ UINT8 TargetStatus;\r
///\r
/// On input, the length in bytes of the SenseData buffer. On\r
/// output, the number of bytes written to the SenseData buffer.\r
///\r
- UINT8 SenseDataLength;\r
+ UINT8 SenseDataLength;\r
} EFI_SCSI_PASS_THRU_SCSI_REQUEST_PACKET;\r
\r
typedef struct {\r
///\r
/// A Null-terminated Unicode string that represents the printable name of the SCSI controller.\r
///\r
- CHAR16 *ControllerName;\r
+ CHAR16 *ControllerName;\r
///\r
/// A Null-terminated Unicode string that represents the printable name of the SCSI channel.\r
///\r
- CHAR16 *ChannelName;\r
+ CHAR16 *ChannelName;\r
///\r
/// The Target ID of the host adapter on the SCSI channel.\r
///\r
- UINT32 AdapterId;\r
+ UINT32 AdapterId;\r
///\r
/// Additional information on the attributes of the SCSI channel.\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
///\r
/// Supplies the alignment requirement for any buffer used in a data transfer.\r
///\r
- UINT32 IoAlign;\r
+ UINT32 IoAlign;\r
} EFI_SCSI_PASS_THRU_MODE;\r
\r
/**\r
///\r
/// A pointer to the EFI_SCSI_PASS_THRU_MODE data for this SCSI channel.\r
///\r
- EFI_SCSI_PASS_THRU_MODE *Mode;\r
- EFI_SCSI_PASS_THRU_PASSTHRU PassThru;\r
- EFI_SCSI_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;\r
- EFI_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
- EFI_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun;\r
- EFI_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel;\r
- EFI_SCSI_PASS_THRU_RESET_TARGET ResetTarget;\r
+ EFI_SCSI_PASS_THRU_MODE *Mode;\r
+ EFI_SCSI_PASS_THRU_PASSTHRU PassThru;\r
+ EFI_SCSI_PASS_THRU_GET_NEXT_DEVICE GetNextDevice;\r
+ EFI_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
+ EFI_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun;\r
+ EFI_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel;\r
+ EFI_SCSI_PASS_THRU_RESET_TARGET ResetTarget;\r
};\r
\r
-extern EFI_GUID gEfiScsiPassThruProtocolGuid;\r
+extern EFI_GUID gEfiScsiPassThruProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL EFI_EXT_SCSI_PASS_THRU_PROTOCOL;\r
\r
-#define TARGET_MAX_BYTES 0x10\r
+#define TARGET_MAX_BYTES 0x10\r
\r
-#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
-#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
-#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
+#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_PHYSICAL 0x0001\r
+#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_LOGICAL 0x0002\r
+#define EFI_EXT_SCSI_PASS_THRU_ATTRIBUTES_NONBLOCKIO 0x0004\r
\r
//\r
// DataDirection\r
//\r
-#define EFI_EXT_SCSI_DATA_DIRECTION_READ 0\r
-#define EFI_EXT_SCSI_DATA_DIRECTION_WRITE 1\r
-#define EFI_EXT_SCSI_DATA_DIRECTION_BIDIRECTIONAL 2\r
+#define EFI_EXT_SCSI_DATA_DIRECTION_READ 0\r
+#define EFI_EXT_SCSI_DATA_DIRECTION_WRITE 1\r
+#define EFI_EXT_SCSI_DATA_DIRECTION_BIDIRECTIONAL 2\r
//\r
// HostAdapterStatus\r
//\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OK 0x00\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT 0x0b\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_RESET 0x0e\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_FREE 0x13\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14\r
-#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OTHER 0x7f\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OK 0x00\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT_COMMAND 0x09\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_TIMEOUT 0x0b\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_MESSAGE_REJECT 0x0d\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_RESET 0x0e\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PARITY_ERROR 0x0f\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_REQUEST_SENSE_FAILED 0x10\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_SELECTION_TIMEOUT 0x11\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_DATA_OVERRUN_UNDERRUN 0x12\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_BUS_FREE 0x13\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_PHASE_ERROR 0x14\r
+#define EFI_EXT_SCSI_STATUS_HOST_ADAPTER_OTHER 0x7f\r
//\r
// TargetStatus\r
//\r
///\r
/// The Target ID of the host adapter on the SCSI channel.\r
///\r
- UINT32 AdapterId;\r
+ UINT32 AdapterId;\r
///\r
/// Additional information on the attributes of the SCSI channel.\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
///\r
/// Supplies the alignment requirement for any buffer used in a data transfer.\r
///\r
- UINT32 IoAlign;\r
+ UINT32 IoAlign;\r
} EFI_EXT_SCSI_PASS_THRU_MODE;\r
\r
typedef struct {\r
/// EFI_TIMEOUT if the time required to execute the SCSI\r
/// Request Packet is greater than Timeout.\r
///\r
- UINT64 Timeout;\r
+ UINT64 Timeout;\r
///\r
/// A pointer to the data buffer to transfer between the SCSI\r
/// controller and the SCSI device for read and bidirectional commands.\r
///\r
- VOID *InDataBuffer;\r
+ VOID *InDataBuffer;\r
///\r
/// A pointer to the data buffer to transfer between the SCSI\r
/// controller and the SCSI device for write or bidirectional commands.\r
///\r
- VOID *OutDataBuffer;\r
+ VOID *OutDataBuffer;\r
///\r
/// A pointer to the sense data that was generated by the execution of\r
/// the SCSI Request Packet.\r
///\r
- VOID *SenseData;\r
+ VOID *SenseData;\r
///\r
/// A pointer to buffer that contains the Command Data Block to\r
/// send to the SCSI device specified by Target and Lun.\r
///\r
- VOID *Cdb;\r
+ VOID *Cdb;\r
///\r
/// On Input, the size, in bytes, of InDataBuffer. On output, the\r
/// number of bytes transferred between the SCSI controller and the SCSI device.\r
///\r
- UINT32 InTransferLength;\r
+ UINT32 InTransferLength;\r
///\r
/// On Input, the size, in bytes of OutDataBuffer. On Output, the\r
/// Number of bytes transferred between SCSI Controller and the SCSI device.\r
///\r
- UINT32 OutTransferLength;\r
+ UINT32 OutTransferLength;\r
///\r
/// The length, in bytes, of the buffer Cdb. The standard values are 6,\r
/// 10, 12, and 16, but other values are possible if a variable length CDB is used.\r
///\r
- UINT8 CdbLength;\r
+ UINT8 CdbLength;\r
///\r
/// The direction of the data transfer. 0 for reads, 1 for writes. A\r
/// value of 2 is Reserved for Bi-Directional SCSI commands.\r
///\r
- UINT8 DataDirection;\r
+ UINT8 DataDirection;\r
///\r
/// The status of the host adapter specified by This when the SCSI\r
/// Request Packet was executed on the target device.\r
///\r
- UINT8 HostAdapterStatus;\r
+ UINT8 HostAdapterStatus;\r
///\r
/// The status returned by the device specified by Target and Lun\r
/// when the SCSI Request Packet was executed.\r
///\r
- UINT8 TargetStatus;\r
+ UINT8 TargetStatus;\r
///\r
/// On input, the length in bytes of the SenseData buffer. On\r
/// output, the number of bytes written to the SenseData buffer.\r
///\r
- UINT8 SenseDataLength;\r
+ UINT8 SenseDataLength;\r
} EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET;\r
\r
/**\r
///\r
/// A pointer to the EFI_EXT_SCSI_PASS_THRU_MODE data for this SCSI channel.\r
///\r
- EFI_EXT_SCSI_PASS_THRU_MODE *Mode;\r
- EFI_EXT_SCSI_PASS_THRU_PASSTHRU PassThru;\r
- EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN GetNextTargetLun;\r
- EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
- EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun;\r
- EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel;\r
- EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN ResetTargetLun;\r
- EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET GetNextTarget;\r
+ EFI_EXT_SCSI_PASS_THRU_MODE *Mode;\r
+ EFI_EXT_SCSI_PASS_THRU_PASSTHRU PassThru;\r
+ EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET_LUN GetNextTargetLun;\r
+ EFI_EXT_SCSI_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
+ EFI_EXT_SCSI_PASS_THRU_GET_TARGET_LUN GetTargetLun;\r
+ EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL ResetChannel;\r
+ EFI_EXT_SCSI_PASS_THRU_RESET_TARGET_LUN ResetTargetLun;\r
+ EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET GetNextTarget;\r
};\r
\r
-extern EFI_GUID gEfiExtScsiPassThruProtocolGuid;\r
+extern EFI_GUID gEfiExtScsiPassThruProtocolGuid;\r
\r
#endif\r
} EFI_SD_MMC_RESPONSE_TYPE;\r
\r
typedef struct _EFI_SD_MMC_COMMAND_BLOCK {\r
- UINT16 CommandIndex;\r
- UINT32 CommandArgument;\r
- UINT32 CommandType; // One of the EFI_SD_MMC_COMMAND_TYPE values\r
- UINT32 ResponseType; // One of the EFI_SD_MMC_RESPONSE_TYPE values\r
+ UINT16 CommandIndex;\r
+ UINT32 CommandArgument;\r
+ UINT32 CommandType; // One of the EFI_SD_MMC_COMMAND_TYPE values\r
+ UINT32 ResponseType; // One of the EFI_SD_MMC_RESPONSE_TYPE values\r
} EFI_SD_MMC_COMMAND_BLOCK;\r
\r
typedef struct _EFI_SD_MMC_STATUS_BLOCK {\r
- UINT32 Resp0;\r
- UINT32 Resp1;\r
- UINT32 Resp2;\r
- UINT32 Resp3;\r
+ UINT32 Resp0;\r
+ UINT32 Resp1;\r
+ UINT32 Resp2;\r
+ UINT32 Resp3;\r
} EFI_SD_MMC_STATUS_BLOCK;\r
\r
typedef struct _EFI_SD_MMC_PASS_THRU_COMMAND_PACKET {\r
- UINT64 Timeout;\r
- EFI_SD_MMC_COMMAND_BLOCK *SdMmcCmdBlk;\r
- EFI_SD_MMC_STATUS_BLOCK *SdMmcStatusBlk;\r
- VOID *InDataBuffer;\r
- VOID *OutDataBuffer;\r
- UINT32 InTransferLength;\r
- UINT32 OutTransferLength;\r
- EFI_STATUS TransactionStatus;\r
+ UINT64 Timeout;\r
+ EFI_SD_MMC_COMMAND_BLOCK *SdMmcCmdBlk;\r
+ EFI_SD_MMC_STATUS_BLOCK *SdMmcStatusBlk;\r
+ VOID *InDataBuffer;\r
+ VOID *OutDataBuffer;\r
+ UINT32 InTransferLength;\r
+ UINT32 OutTransferLength;\r
+ EFI_STATUS TransactionStatus;\r
} EFI_SD_MMC_PASS_THRU_COMMAND_PACKET;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SD_MMC_PASS_THRU_PASSTHRU) (\r
+(EFIAPI *EFI_SD_MMC_PASS_THRU_PASSTHRU)(\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,\r
IN UINT8 Slot,\r
IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet,\r
IN EFI_EVENT Event OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Used to retrieve next slot numbers supported by the SD controller. The function\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT) (\r
+(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT)(\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,\r
IN OUT UINT8 *Slot\r
-);\r
+ );\r
\r
/**\r
Used to allocate and build a device path node for an SD card on the SD controller.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH) (\r
+(EFIAPI *EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH)(\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,\r
IN UINT8 Slot,\r
OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
-);\r
+ );\r
\r
/**\r
This function retrieves an SD card slot number based on the input device path.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER) (\r
+(EFIAPI *EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER)(\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,\r
IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
OUT UINT8 *Slot\r
-);\r
+ );\r
\r
/**\r
Resets an SD card that is connected to the SD controller.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SD_MMC_PASS_THRU_RESET_DEVICE) (\r
+(EFIAPI *EFI_SD_MMC_PASS_THRU_RESET_DEVICE)(\r
IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This,\r
IN UINT8 Slot\r
-);\r
+ );\r
\r
struct _EFI_SD_MMC_PASS_THRU_PROTOCOL {\r
- UINT32 IoAlign;\r
- EFI_SD_MMC_PASS_THRU_PASSTHRU PassThru;\r
- EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT GetNextSlot;\r
- EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
- EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER GetSlotNumber;\r
- EFI_SD_MMC_PASS_THRU_RESET_DEVICE ResetDevice;\r
+ UINT32 IoAlign;\r
+ EFI_SD_MMC_PASS_THRU_PASSTHRU PassThru;\r
+ EFI_SD_MMC_PASS_THRU_GET_NEXT_SLOT GetNextSlot;\r
+ EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH BuildDevicePath;\r
+ EFI_SD_MMC_PASS_THRU_GET_SLOT_NUMBER GetSlotNumber;\r
+ EFI_SD_MMC_PASS_THRU_RESET_DEVICE ResetDevice;\r
};\r
\r
-extern EFI_GUID gEfiSdMmcPassThruProtocolGuid;\r
+extern EFI_GUID gEfiSdMmcPassThruProtocolGuid;\r
\r
#endif\r
#define EFI_SECURITY_ARCH_PROTOCOL_GUID \\r
{ 0xA46423E3, 0x4617, 0x49f1, {0xB9, 0xFF, 0xD1, 0xBF, 0xA9, 0x11, 0x58, 0x39 } }\r
\r
-typedef struct _EFI_SECURITY_ARCH_PROTOCOL EFI_SECURITY_ARCH_PROTOCOL;\r
+typedef struct _EFI_SECURITY_ARCH_PROTOCOL EFI_SECURITY_ARCH_PROTOCOL;\r
\r
/**\r
The EFI_SECURITY_ARCH_PROTOCOL (SAP) is used to abstract platform-specific\r
/// attestation logging, and other exception operations.\r
///\r
struct _EFI_SECURITY_ARCH_PROTOCOL {\r
- EFI_SECURITY_FILE_AUTHENTICATION_STATE FileAuthenticationState;\r
+ EFI_SECURITY_FILE_AUTHENTICATION_STATE FileAuthenticationState;\r
};\r
\r
-extern EFI_GUID gEfiSecurityArchProtocolGuid;\r
+extern EFI_GUID gEfiSecurityArchProtocolGuid;\r
\r
#endif\r
#define EFI_SECURITY2_ARCH_PROTOCOL_GUID \\r
{ 0x94ab2f58, 0x1438, 0x4ef1, {0x91, 0x52, 0x18, 0x94, 0x1a, 0x3a, 0x0e, 0x68 } }\r
\r
-typedef struct _EFI_SECURITY2_ARCH_PROTOCOL EFI_SECURITY2_ARCH_PROTOCOL;\r
+typedef struct _EFI_SECURITY2_ARCH_PROTOCOL EFI_SECURITY2_ARCH_PROTOCOL;\r
\r
/**\r
The DXE Foundation uses this service to measure and/or verify a UEFI image.\r
drivers from the device path specified by DevicePath. The\r
image has been added into the list of the deferred images.\r
**/\r
-typedef EFI_STATUS (EFIAPI *EFI_SECURITY2_FILE_AUTHENTICATION) (\r
+typedef EFI_STATUS (EFIAPI *EFI_SECURITY2_FILE_AUTHENTICATION)(\r
IN CONST EFI_SECURITY2_ARCH_PROTOCOL *This,\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *File OPTIONAL,\r
IN VOID *FileBuffer,\r
IN UINTN FileSize,\r
IN BOOLEAN BootPolicy\r
-);\r
+ );\r
\r
///\r
/// The EFI_SECURITY2_ARCH_PROTOCOL is used to abstract platform-specific policy from the\r
/// or registered hashes).\r
///\r
struct _EFI_SECURITY2_ARCH_PROTOCOL {\r
- EFI_SECURITY2_FILE_AUTHENTICATION FileAuthentication;\r
+ EFI_SECURITY2_FILE_AUTHENTICATION FileAuthentication;\r
};\r
\r
-extern EFI_GUID gEfiSecurity2ArchProtocolGuid;\r
+extern EFI_GUID gEfiSecurity2ArchProtocolGuid;\r
\r
#endif\r
#define EFI_SECURITY_POLICY_PROTOCOL_GUID \\r
{0x78E4D245, 0xCD4D, 0x4a05, {0xA2, 0xBA, 0x47, 0x43, 0xE8, 0x6C, 0xFC, 0xAB} }\r
\r
-extern EFI_GUID gEfiSecurityPolicyProtocolGuid;\r
+extern EFI_GUID gEfiSecurityPolicyProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL;\r
\r
-\r
///\r
/// Backward-compatible with EFI1.1.\r
///\r
-typedef EFI_SERIAL_IO_PROTOCOL SERIAL_IO_INTERFACE;\r
+typedef EFI_SERIAL_IO_PROTOCOL SERIAL_IO_INTERFACE;\r
\r
///\r
/// Parity type that is computed or checked as each character is transmitted or received. If the\r
//\r
// Read Write\r
//\r
-#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x00001000\r
-#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x00002000\r
-#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x00004000\r
+#define EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE 0x00001000\r
+#define EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE 0x00002000\r
+#define EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE 0x00004000\r
\r
//\r
// Serial IO Member Functions\r
//\r
+\r
/**\r
Reset the serial device.\r
\r
\r
**/\r
typedef struct {\r
- UINT32 ControlMask;\r
+ UINT32 ControlMask;\r
\r
//\r
// current Attributes\r
//\r
- UINT32 Timeout;\r
- UINT64 BaudRate;\r
- UINT32 ReceiveFifoDepth;\r
- UINT32 DataBits;\r
- UINT32 Parity;\r
- UINT32 StopBits;\r
+ UINT32 Timeout;\r
+ UINT64 BaudRate;\r
+ UINT32 ReceiveFifoDepth;\r
+ UINT32 DataBits;\r
+ UINT32 Parity;\r
+ UINT32 StopBits;\r
} EFI_SERIAL_IO_MODE;\r
\r
-#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000\r
-#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001\r
-#define SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION\r
+#define EFI_SERIAL_IO_PROTOCOL_REVISION 0x00010000\r
+#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001\r
+#define SERIAL_IO_INTERFACE_REVISION EFI_SERIAL_IO_PROTOCOL_REVISION\r
\r
///\r
/// The Serial I/O protocol is used to communicate with UART-style serial devices.\r
/// must be backwards compatible. If a future version is not backwards compatible,\r
/// it is not the same GUID.\r
///\r
- UINT32 Revision;\r
- EFI_SERIAL_RESET Reset;\r
- EFI_SERIAL_SET_ATTRIBUTES SetAttributes;\r
- EFI_SERIAL_SET_CONTROL_BITS SetControl;\r
- EFI_SERIAL_GET_CONTROL_BITS GetControl;\r
- EFI_SERIAL_WRITE Write;\r
- EFI_SERIAL_READ Read;\r
+ UINT32 Revision;\r
+ EFI_SERIAL_RESET Reset;\r
+ EFI_SERIAL_SET_ATTRIBUTES SetAttributes;\r
+ EFI_SERIAL_SET_CONTROL_BITS SetControl;\r
+ EFI_SERIAL_GET_CONTROL_BITS GetControl;\r
+ EFI_SERIAL_WRITE Write;\r
+ EFI_SERIAL_READ Read;\r
///\r
/// Pointer to SERIAL_IO_MODE data.\r
///\r
- EFI_SERIAL_IO_MODE *Mode;\r
+ EFI_SERIAL_IO_MODE *Mode;\r
///\r
/// Pointer to a GUID identifying the device connected to the serial port.\r
/// This field is NULL when the protocol is installed by the serial port\r
/// with a known device attached. The field will remain NULL if there is\r
/// no platform serial device identification information available.\r
///\r
- CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1\r
+ CONST EFI_GUID *DeviceTypeGuid; // Revision 1.1\r
};\r
\r
-extern EFI_GUID gEfiSerialIoProtocolGuid;\r
-extern EFI_GUID gEfiSerialTerminalDeviceTypeGuid;\r
+extern EFI_GUID gEfiSerialIoProtocolGuid;\r
+extern EFI_GUID gEfiSerialTerminalDeviceTypeGuid;\r
\r
#endif\r
/// protocol and calling DestroyChild() when it is finished with that protocol.\r
///\r
struct _EFI_SERVICE_BINDING_PROTOCOL {\r
- EFI_SERVICE_BINDING_CREATE_CHILD CreateChild;\r
- EFI_SERVICE_BINDING_DESTROY_CHILD DestroyChild;\r
+ EFI_SERVICE_BINDING_CREATE_CHILD CreateChild;\r
+ EFI_SERVICE_BINDING_DESTROY_CHILD DestroyChild;\r
};\r
\r
#endif\r
///\r
/// The operation completed successfully.\r
///\r
- SHELL_SUCCESS = 0,\r
+ SHELL_SUCCESS = 0,\r
\r
///\r
/// The image failed to load.\r
///\r
- SHELL_LOAD_ERROR = 1,\r
+ SHELL_LOAD_ERROR = 1,\r
\r
///\r
/// The parameter was incorrect.\r
///\r
- SHELL_INVALID_PARAMETER = 2,\r
+ SHELL_INVALID_PARAMETER = 2,\r
\r
///\r
/// The operation is not supported.\r
///\r
- SHELL_UNSUPPORTED = 3,\r
+ SHELL_UNSUPPORTED = 3,\r
\r
///\r
/// The buffer was not the proper size for the request.\r
///\r
- SHELL_BAD_BUFFER_SIZE = 4,\r
+ SHELL_BAD_BUFFER_SIZE = 4,\r
\r
///\r
/// The buffer was not large enough to hold the requested data.\r
/// The required buffer size is returned in the appropriate\r
/// parameter when this error occurs.\r
///\r
- SHELL_BUFFER_TOO_SMALL = 5,\r
+ SHELL_BUFFER_TOO_SMALL = 5,\r
\r
///\r
/// There is no data pending upon return.\r
///\r
- SHELL_NOT_READY = 6,\r
+ SHELL_NOT_READY = 6,\r
\r
///\r
/// The physical device reported an error while attempting the\r
/// operation.\r
///\r
- SHELL_DEVICE_ERROR = 7,\r
+ SHELL_DEVICE_ERROR = 7,\r
\r
///\r
/// The device cannot be written to.\r
///\r
- SHELL_WRITE_PROTECTED = 8,\r
+ SHELL_WRITE_PROTECTED = 8,\r
\r
///\r
/// The resource has run out.\r
///\r
- SHELL_OUT_OF_RESOURCES = 9,\r
+ SHELL_OUT_OF_RESOURCES = 9,\r
\r
///\r
/// An inconsistency was detected on the file system causing the\r
/// operation to fail.\r
///\r
- SHELL_VOLUME_CORRUPTED = 10,\r
+ SHELL_VOLUME_CORRUPTED = 10,\r
\r
///\r
/// There is no more space on the file system.\r
///\r
- SHELL_VOLUME_FULL = 11,\r
+ SHELL_VOLUME_FULL = 11,\r
\r
///\r
/// The device does not contain any medium to perform the\r
/// operation.\r
///\r
- SHELL_NO_MEDIA = 12,\r
+ SHELL_NO_MEDIA = 12,\r
\r
///\r
/// The medium in the device has changed since the last\r
/// access.\r
///\r
- SHELL_MEDIA_CHANGED = 13,\r
+ SHELL_MEDIA_CHANGED = 13,\r
\r
///\r
/// The item was not found.\r
///\r
- SHELL_NOT_FOUND = 14,\r
+ SHELL_NOT_FOUND = 14,\r
\r
///\r
/// Access was denied.\r
///\r
- SHELL_ACCESS_DENIED = 15,\r
+ SHELL_ACCESS_DENIED = 15,\r
\r
// note the skipping of 16 and 17\r
\r
///\r
/// A timeout time expired.\r
///\r
- SHELL_TIMEOUT = 18,\r
+ SHELL_TIMEOUT = 18,\r
\r
///\r
/// The protocol has not been started.\r
///\r
- SHELL_NOT_STARTED = 19,\r
+ SHELL_NOT_STARTED = 19,\r
\r
///\r
/// The protocol has already been started.\r
///\r
- SHELL_ALREADY_STARTED = 20,\r
+ SHELL_ALREADY_STARTED = 20,\r
\r
///\r
/// The operation was aborted.\r
///\r
- SHELL_ABORTED = 21,\r
+ SHELL_ABORTED = 21,\r
\r
// note the skipping of 22, 23, and 24\r
\r
/// A function encountered an internal version that was\r
/// incompatible with a version requested by the caller.\r
///\r
- SHELL_INCOMPATIBLE_VERSION = 25,\r
+ SHELL_INCOMPATIBLE_VERSION = 25,\r
\r
///\r
/// The function was not performed due to a security violation.\r
///\r
- SHELL_SECURITY_VIOLATION = 26,\r
+ SHELL_SECURITY_VIOLATION = 26,\r
\r
///\r
/// The function was performed and resulted in an unequal\r
/// comparison..\r
///\r
- SHELL_NOT_EQUAL = 27\r
+ SHELL_NOT_EQUAL = 27\r
} SHELL_STATUS;\r
\r
-\r
// replaced EFI_LIST_ENTRY with LIST_ENTRY for simplicity.\r
// they are identical outside of the name.\r
typedef struct {\r
- LIST_ENTRY Link; ///< Linked list members.\r
- EFI_STATUS Status; ///< Status of opening the file. Valid only if Handle != NULL.\r
- CONST CHAR16 *FullName; ///< Fully qualified filename.\r
- CONST CHAR16 *FileName; ///< name of this file.\r
- SHELL_FILE_HANDLE Handle; ///< Handle for interacting with the opened file or NULL if closed.\r
- EFI_FILE_INFO *Info; ///< Pointer to the FileInfo struct for this file or NULL.\r
+ LIST_ENTRY Link; ///< Linked list members.\r
+ EFI_STATUS Status; ///< Status of opening the file. Valid only if Handle != NULL.\r
+ CONST CHAR16 *FullName; ///< Fully qualified filename.\r
+ CONST CHAR16 *FileName; ///< name of this file.\r
+ SHELL_FILE_HANDLE Handle; ///< Handle for interacting with the opened file or NULL if closed.\r
+ EFI_FILE_INFO *Info; ///< Pointer to the FileInfo struct for this file or NULL.\r
} EFI_SHELL_FILE_INFO;\r
\r
/**\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *EFI_SHELL_BATCH_IS_ACTIVE) (\r
+(EFIAPI *EFI_SHELL_BATCH_IS_ACTIVE)(\r
VOID\r
);\r
\r
**/\r
typedef\r
VOID\r
-(EFIAPI *EFI_SHELL_DISABLE_PAGE_BREAK) (\r
+(EFIAPI *EFI_SHELL_DISABLE_PAGE_BREAK)(\r
VOID\r
);\r
\r
**/\r
typedef\r
VOID\r
-(EFIAPI *EFI_SHELL_ENABLE_PAGE_BREAK) (\r
+(EFIAPI *EFI_SHELL_ENABLE_PAGE_BREAK)(\r
VOID\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_EXECUTE) (\r
+(EFIAPI *EFI_SHELL_EXECUTE)(\r
IN EFI_HANDLE *ParentImageHandle,\r
IN CHAR16 *CommandLine OPTIONAL,\r
IN CHAR16 **Environment OPTIONAL,\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SHELL_FIND_FILES_IN_DIR)(\r
-IN SHELL_FILE_HANDLE FileDirHandle,\r
-OUT EFI_SHELL_FILE_INFO **FileList\r
-);\r
+ IN SHELL_FILE_HANDLE FileDirHandle,\r
+ OUT EFI_SHELL_FILE_INFO **FileList\r
+ );\r
\r
/**\r
Flushes data back to a device.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_FREE_FILE_LIST) (\r
+(EFIAPI *EFI_SHELL_FREE_FILE_LIST)(\r
IN EFI_SHELL_FILE_INFO **FileList\r
);\r
\r
**/\r
typedef\r
CONST CHAR16 *\r
-(EFIAPI *EFI_SHELL_GET_CUR_DIR) (\r
+(EFIAPI *EFI_SHELL_GET_CUR_DIR)(\r
IN CONST CHAR16 *FileSystemMapping OPTIONAL\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_GET_DEVICE_NAME) (\r
+(EFIAPI *EFI_SHELL_GET_DEVICE_NAME)(\r
IN EFI_HANDLE DeviceHandle,\r
IN EFI_SHELL_DEVICE_NAME_FLAGS Flags,\r
IN CHAR8 *Language,\r
**/\r
typedef\r
CONST EFI_DEVICE_PATH_PROTOCOL *\r
-(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_MAP) (\r
+(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_MAP)(\r
IN CONST CHAR16 *Mapping\r
);\r
\r
**/\r
typedef\r
EFI_DEVICE_PATH_PROTOCOL *\r
-(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH) (\r
+(EFIAPI *EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH)(\r
IN CONST CHAR16 *Path\r
);\r
\r
**/\r
typedef\r
CONST CHAR16 *\r
-(EFIAPI *EFI_SHELL_GET_ENV) (\r
+(EFIAPI *EFI_SHELL_GET_ENV)(\r
IN CONST CHAR16 *Name OPTIONAL\r
);\r
\r
**/\r
typedef\r
CONST CHAR16 *\r
-(EFIAPI *EFI_SHELL_GET_ENV_EX) (\r
+(EFIAPI *EFI_SHELL_GET_ENV_EX)(\r
IN CONST CHAR16 *Name,\r
OUT UINT32 *Attributes OPTIONAL\r
);\r
**/\r
typedef\r
CHAR16 *\r
-(EFIAPI *EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH) (\r
+(EFIAPI *EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH)(\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *Path\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_GET_HELP_TEXT) (\r
+(EFIAPI *EFI_SHELL_GET_HELP_TEXT)(\r
IN CONST CHAR16 *Command,\r
IN CONST CHAR16 *Sections OPTIONAL,\r
OUT CHAR16 **HelpText\r
**/\r
typedef\r
CONST CHAR16 *\r
-(EFIAPI *EFI_SHELL_GET_MAP_FROM_DEVICE_PATH) (\r
+(EFIAPI *EFI_SHELL_GET_MAP_FROM_DEVICE_PATH)(\r
IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
);\r
\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *EFI_SHELL_GET_PAGE_BREAK) (\r
+(EFIAPI *EFI_SHELL_GET_PAGE_BREAK)(\r
VOID\r
);\r
\r
**/\r
typedef\r
BOOLEAN\r
-(EFIAPI *EFI_SHELL_IS_ROOT_SHELL) (\r
-VOID\r
-);\r
+(EFIAPI *EFI_SHELL_IS_ROOT_SHELL)(\r
+ VOID\r
+ );\r
\r
/**\r
Opens a file or a directory by file name.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_OPEN_FILE_BY_NAME) (\r
+(EFIAPI *EFI_SHELL_OPEN_FILE_BY_NAME)(\r
IN CONST CHAR16 *FileName,\r
OUT SHELL_FILE_HANDLE *FileHandle,\r
IN UINT64 OpenMode\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_OPEN_FILE_LIST) (\r
+(EFIAPI *EFI_SHELL_OPEN_FILE_LIST)(\r
IN CHAR16 *Path,\r
IN UINT64 OpenMode,\r
IN OUT EFI_SHELL_FILE_INFO **FileList\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_READ_FILE) (\r
+(EFIAPI *EFI_SHELL_READ_FILE)(\r
IN SHELL_FILE_HANDLE FileHandle,\r
IN OUT UINTN *ReadSize,\r
IN OUT VOID *Buffer\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_REMOVE_DUP_IN_FILE_LIST) (\r
+(EFIAPI *EFI_SHELL_REMOVE_DUP_IN_FILE_LIST)(\r
IN EFI_SHELL_FILE_INFO **FileList\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_SET_CUR_DIR) (\r
+(EFIAPI *EFI_SHELL_SET_CUR_DIR)(\r
IN CONST CHAR16 *FileSystem OPTIONAL,\r
IN CONST CHAR16 *Dir\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SHELL_SET_ENV) (\r
+(EFIAPI *EFI_SHELL_SET_ENV)(\r
IN CONST CHAR16 *Name,\r
IN CONST CHAR16 *Value,\r
IN BOOLEAN Volatile\r
// }\r
//\r
typedef struct _EFI_SHELL_PROTOCOL {\r
- EFI_SHELL_EXECUTE Execute;\r
- EFI_SHELL_GET_ENV GetEnv;\r
- EFI_SHELL_SET_ENV SetEnv;\r
- EFI_SHELL_GET_ALIAS GetAlias;\r
- EFI_SHELL_SET_ALIAS SetAlias;\r
- EFI_SHELL_GET_HELP_TEXT GetHelpText;\r
- EFI_SHELL_GET_DEVICE_PATH_FROM_MAP GetDevicePathFromMap;\r
- EFI_SHELL_GET_MAP_FROM_DEVICE_PATH GetMapFromDevicePath;\r
- EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH GetDevicePathFromFilePath;\r
- EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH GetFilePathFromDevicePath;\r
- EFI_SHELL_SET_MAP SetMap;\r
- EFI_SHELL_GET_CUR_DIR GetCurDir;\r
- EFI_SHELL_SET_CUR_DIR SetCurDir;\r
- EFI_SHELL_OPEN_FILE_LIST OpenFileList;\r
- EFI_SHELL_FREE_FILE_LIST FreeFileList;\r
- EFI_SHELL_REMOVE_DUP_IN_FILE_LIST RemoveDupInFileList;\r
- EFI_SHELL_BATCH_IS_ACTIVE BatchIsActive;\r
- EFI_SHELL_IS_ROOT_SHELL IsRootShell;\r
- EFI_SHELL_ENABLE_PAGE_BREAK EnablePageBreak;\r
- EFI_SHELL_DISABLE_PAGE_BREAK DisablePageBreak;\r
- EFI_SHELL_GET_PAGE_BREAK GetPageBreak;\r
- EFI_SHELL_GET_DEVICE_NAME GetDeviceName;\r
- EFI_SHELL_GET_FILE_INFO GetFileInfo;\r
- EFI_SHELL_SET_FILE_INFO SetFileInfo;\r
- EFI_SHELL_OPEN_FILE_BY_NAME OpenFileByName;\r
- EFI_SHELL_CLOSE_FILE CloseFile;\r
- EFI_SHELL_CREATE_FILE CreateFile;\r
- EFI_SHELL_READ_FILE ReadFile;\r
- EFI_SHELL_WRITE_FILE WriteFile;\r
- EFI_SHELL_DELETE_FILE DeleteFile;\r
- EFI_SHELL_DELETE_FILE_BY_NAME DeleteFileByName;\r
- EFI_SHELL_GET_FILE_POSITION GetFilePosition;\r
- EFI_SHELL_SET_FILE_POSITION SetFilePosition;\r
- EFI_SHELL_FLUSH_FILE FlushFile;\r
- EFI_SHELL_FIND_FILES FindFiles;\r
- EFI_SHELL_FIND_FILES_IN_DIR FindFilesInDir;\r
- EFI_SHELL_GET_FILE_SIZE GetFileSize;\r
- EFI_SHELL_OPEN_ROOT OpenRoot;\r
- EFI_SHELL_OPEN_ROOT_BY_HANDLE OpenRootByHandle;\r
- EFI_EVENT ExecutionBreak;\r
- UINT32 MajorVersion;\r
- UINT32 MinorVersion;\r
+ EFI_SHELL_EXECUTE Execute;\r
+ EFI_SHELL_GET_ENV GetEnv;\r
+ EFI_SHELL_SET_ENV SetEnv;\r
+ EFI_SHELL_GET_ALIAS GetAlias;\r
+ EFI_SHELL_SET_ALIAS SetAlias;\r
+ EFI_SHELL_GET_HELP_TEXT GetHelpText;\r
+ EFI_SHELL_GET_DEVICE_PATH_FROM_MAP GetDevicePathFromMap;\r
+ EFI_SHELL_GET_MAP_FROM_DEVICE_PATH GetMapFromDevicePath;\r
+ EFI_SHELL_GET_DEVICE_PATH_FROM_FILE_PATH GetDevicePathFromFilePath;\r
+ EFI_SHELL_GET_FILE_PATH_FROM_DEVICE_PATH GetFilePathFromDevicePath;\r
+ EFI_SHELL_SET_MAP SetMap;\r
+ EFI_SHELL_GET_CUR_DIR GetCurDir;\r
+ EFI_SHELL_SET_CUR_DIR SetCurDir;\r
+ EFI_SHELL_OPEN_FILE_LIST OpenFileList;\r
+ EFI_SHELL_FREE_FILE_LIST FreeFileList;\r
+ EFI_SHELL_REMOVE_DUP_IN_FILE_LIST RemoveDupInFileList;\r
+ EFI_SHELL_BATCH_IS_ACTIVE BatchIsActive;\r
+ EFI_SHELL_IS_ROOT_SHELL IsRootShell;\r
+ EFI_SHELL_ENABLE_PAGE_BREAK EnablePageBreak;\r
+ EFI_SHELL_DISABLE_PAGE_BREAK DisablePageBreak;\r
+ EFI_SHELL_GET_PAGE_BREAK GetPageBreak;\r
+ EFI_SHELL_GET_DEVICE_NAME GetDeviceName;\r
+ EFI_SHELL_GET_FILE_INFO GetFileInfo;\r
+ EFI_SHELL_SET_FILE_INFO SetFileInfo;\r
+ EFI_SHELL_OPEN_FILE_BY_NAME OpenFileByName;\r
+ EFI_SHELL_CLOSE_FILE CloseFile;\r
+ EFI_SHELL_CREATE_FILE CreateFile;\r
+ EFI_SHELL_READ_FILE ReadFile;\r
+ EFI_SHELL_WRITE_FILE WriteFile;\r
+ EFI_SHELL_DELETE_FILE DeleteFile;\r
+ EFI_SHELL_DELETE_FILE_BY_NAME DeleteFileByName;\r
+ EFI_SHELL_GET_FILE_POSITION GetFilePosition;\r
+ EFI_SHELL_SET_FILE_POSITION SetFilePosition;\r
+ EFI_SHELL_FLUSH_FILE FlushFile;\r
+ EFI_SHELL_FIND_FILES FindFiles;\r
+ EFI_SHELL_FIND_FILES_IN_DIR FindFilesInDir;\r
+ EFI_SHELL_GET_FILE_SIZE GetFileSize;\r
+ EFI_SHELL_OPEN_ROOT OpenRoot;\r
+ EFI_SHELL_OPEN_ROOT_BY_HANDLE OpenRootByHandle;\r
+ EFI_EVENT ExecutionBreak;\r
+ UINT32 MajorVersion;\r
+ UINT32 MinorVersion;\r
// Added for Shell 2.1\r
- EFI_SHELL_REGISTER_GUID_NAME RegisterGuidName;\r
- EFI_SHELL_GET_GUID_NAME GetGuidName;\r
- EFI_SHELL_GET_GUID_FROM_NAME GetGuidFromName;\r
- EFI_SHELL_GET_ENV_EX GetEnvEx;\r
+ EFI_SHELL_REGISTER_GUID_NAME RegisterGuidName;\r
+ EFI_SHELL_GET_GUID_NAME GetGuidName;\r
+ EFI_SHELL_GET_GUID_FROM_NAME GetGuidFromName;\r
+ EFI_SHELL_GET_ENV_EX GetEnvEx;\r
} EFI_SHELL_PROTOCOL;\r
\r
-extern EFI_GUID gEfiShellProtocolGuid;\r
+extern EFI_GUID gEfiShellProtocolGuid;\r
\r
enum ShellVersion {\r
SHELL_MAJOR_VERSION = 2,\r
0x3c7200e9, 0x005f, 0x4ea4, { 0x87, 0xde, 0xa3, 0xdf, 0xac, 0x8a, 0x27, 0xc3 } \\r
}\r
\r
-\r
//\r
// Define for forward reference.\r
//\r
typedef struct _EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL;\r
\r
-\r
/**\r
This is the shell command handler function pointer callback type. This\r
function handles the command when it is invoked in the shell.\r
**/\r
typedef\r
SHELL_STATUS\r
-(EFIAPI * SHELL_COMMAND_HANDLER)(\r
+(EFIAPI *SHELL_COMMAND_HANDLER)(\r
IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This,\r
IN EFI_SYSTEM_TABLE *SystemTable,\r
IN EFI_SHELL_PARAMETERS_PROTOCOL *ShellParameters,\r
@return string Pool allocated help string, must be freed by caller\r
**/\r
typedef\r
-CHAR16*\r
-(EFIAPI * SHELL_COMMAND_GETHELP)(\r
+CHAR16 *\r
+(EFIAPI *SHELL_COMMAND_GETHELP)(\r
IN EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL *This,\r
IN CONST CHAR8 *Language\r
);\r
\r
/// EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL protocol structure.\r
struct _EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL {\r
-\r
- CONST CHAR16 *CommandName;\r
- SHELL_COMMAND_HANDLER Handler;\r
- SHELL_COMMAND_GETHELP GetHelp;\r
-\r
+ CONST CHAR16 *CommandName;\r
+ SHELL_COMMAND_HANDLER Handler;\r
+ SHELL_COMMAND_GETHELP GetHelp;\r
};\r
\r
-extern EFI_GUID gEfiShellDynamicCommandProtocolGuid;\r
+extern EFI_GUID gEfiShellDynamicCommandProtocolGuid;\r
\r
#endif\r
/// path of the executable. Any quotation marks that were used to preserve\r
/// whitespace have been removed.\r
///\r
- CHAR16 **Argv;\r
+ CHAR16 **Argv;\r
\r
///\r
/// The number of elements in the Argv array.\r
///\r
- UINTN Argc;\r
+ UINTN Argc;\r
\r
///\r
/// The file handle for the standard input for this executable. This may be different\r
/// from the ConInHandle in EFI_SYSTEM_TABLE.\r
///\r
- SHELL_FILE_HANDLE StdIn;\r
+ SHELL_FILE_HANDLE StdIn;\r
\r
///\r
/// The file handle for the standard output for this executable. This may be different\r
/// from the ConOutHandle in EFI_SYSTEM_TABLE.\r
///\r
- SHELL_FILE_HANDLE StdOut;\r
+ SHELL_FILE_HANDLE StdOut;\r
\r
///\r
/// The file handle for the standard error output for this executable. This may be\r
/// different from the StdErrHandle in EFI_SYSTEM_TABLE.\r
///\r
- SHELL_FILE_HANDLE StdErr;\r
+ SHELL_FILE_HANDLE StdErr;\r
} EFI_SHELL_PARAMETERS_PROTOCOL;\r
\r
-extern EFI_GUID gEfiShellParametersProtocolGuid;\r
+extern EFI_GUID gEfiShellParametersProtocolGuid;\r
\r
#endif\r
0x964e5b22, 0x6459, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \\r
}\r
\r
-typedef struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL;\r
+typedef struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL;\r
\r
-typedef struct _EFI_FILE_PROTOCOL EFI_FILE_PROTOCOL;\r
-typedef struct _EFI_FILE_PROTOCOL *EFI_FILE_HANDLE;\r
+typedef struct _EFI_FILE_PROTOCOL EFI_FILE_PROTOCOL;\r
+typedef struct _EFI_FILE_PROTOCOL *EFI_FILE_HANDLE;\r
\r
///\r
/// Protocol GUID name defined in EFI1.1.\r
///\r
-#define SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID\r
+#define SIMPLE_FILE_SYSTEM_PROTOCOL EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID\r
\r
///\r
/// Protocol name defined in EFI1.1.\r
///\r
-typedef EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_FILE_IO_INTERFACE;\r
-typedef EFI_FILE_PROTOCOL EFI_FILE;\r
+typedef EFI_SIMPLE_FILE_SYSTEM_PROTOCOL EFI_FILE_IO_INTERFACE;\r
+typedef EFI_FILE_PROTOCOL EFI_FILE;\r
\r
/**\r
Open the root directory on a volume.\r
/// specified by this specification is 0x00010000. All future revisions\r
/// must be backwards compatible.\r
///\r
- UINT64 Revision;\r
- EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME OpenVolume;\r
+ UINT64 Revision;\r
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_OPEN_VOLUME OpenVolume;\r
};\r
\r
/**\r
//\r
// File attributes\r
//\r
-#define EFI_FILE_READ_ONLY 0x0000000000000001ULL\r
-#define EFI_FILE_HIDDEN 0x0000000000000002ULL\r
-#define EFI_FILE_SYSTEM 0x0000000000000004ULL\r
-#define EFI_FILE_RESERVED 0x0000000000000008ULL\r
-#define EFI_FILE_DIRECTORY 0x0000000000000010ULL\r
-#define EFI_FILE_ARCHIVE 0x0000000000000020ULL\r
-#define EFI_FILE_VALID_ATTR 0x0000000000000037ULL\r
+#define EFI_FILE_READ_ONLY 0x0000000000000001ULL\r
+#define EFI_FILE_HIDDEN 0x0000000000000002ULL\r
+#define EFI_FILE_SYSTEM 0x0000000000000004ULL\r
+#define EFI_FILE_RESERVED 0x0000000000000008ULL\r
+#define EFI_FILE_DIRECTORY 0x0000000000000010ULL\r
+#define EFI_FILE_ARCHIVE 0x0000000000000020ULL\r
+#define EFI_FILE_VALID_ATTR 0x0000000000000037ULL\r
\r
/**\r
Closes a specified file handle.\r
// The caller must be prepared to handle the case where the callback associated with Event\r
// occurs before the original asynchronous I/O request call returns.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
\r
//\r
// Defines whether or not the signaled event encountered an error.\r
//\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
//\r
// For OpenEx(): Not Used, ignored.\r
// In both cases, the size is measured in bytes.\r
// For FlushEx(): Not used, ignored.\r
//\r
- UINTN BufferSize;\r
+ UINTN BufferSize;\r
\r
//\r
// For OpenEx(): Not Used, ignored.\r
// For WriteEx(): The buffer of data to write.\r
// For FlushEx(): Not Used, ignored.\r
//\r
- VOID *Buffer;\r
+ VOID *Buffer;\r
} EFI_FILE_IO_TOKEN;\r
\r
/**\r
IN OUT EFI_FILE_IO_TOKEN *Token\r
);\r
\r
-\r
/**\r
Reads data from a file.\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_FILE_READ_EX) (\r
+(EFIAPI *EFI_FILE_READ_EX)(\r
IN EFI_FILE_PROTOCOL *This,\r
IN OUT EFI_FILE_IO_TOKEN *Token\r
-);\r
-\r
+ );\r
\r
/**\r
Writes data to a file.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_FILE_WRITE_EX) (\r
+(EFIAPI *EFI_FILE_WRITE_EX)(\r
IN EFI_FILE_PROTOCOL *This,\r
IN OUT EFI_FILE_IO_TOKEN *Token\r
-);\r
+ );\r
\r
/**\r
Flushes all modified data associated with a file to a device.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_FILE_FLUSH_EX) (\r
+(EFIAPI *EFI_FILE_FLUSH_EX)(\r
IN EFI_FILE_PROTOCOL *This,\r
IN OUT EFI_FILE_IO_TOKEN *Token\r
);\r
\r
-#define EFI_FILE_PROTOCOL_REVISION 0x00010000\r
-#define EFI_FILE_PROTOCOL_REVISION2 0x00020000\r
-#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2\r
+#define EFI_FILE_PROTOCOL_REVISION 0x00010000\r
+#define EFI_FILE_PROTOCOL_REVISION2 0x00020000\r
+#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2\r
\r
//\r
// Revision defined in EFI1.1.\r
//\r
-#define EFI_FILE_REVISION EFI_FILE_PROTOCOL_REVISION\r
+#define EFI_FILE_REVISION EFI_FILE_PROTOCOL_REVISION\r
\r
///\r
/// The EFI_FILE_PROTOCOL provides file IO access to supported file systems.\r
/// by this specification is EFI_FILE_PROTOCOL_LATEST_REVISION.\r
/// Future versions are required to be backward compatible to version 1.0.\r
///\r
- UINT64 Revision;\r
- EFI_FILE_OPEN Open;\r
- EFI_FILE_CLOSE Close;\r
- EFI_FILE_DELETE Delete;\r
- EFI_FILE_READ Read;\r
- EFI_FILE_WRITE Write;\r
- EFI_FILE_GET_POSITION GetPosition;\r
- EFI_FILE_SET_POSITION SetPosition;\r
- EFI_FILE_GET_INFO GetInfo;\r
- EFI_FILE_SET_INFO SetInfo;\r
- EFI_FILE_FLUSH Flush;\r
- EFI_FILE_OPEN_EX OpenEx;\r
- EFI_FILE_READ_EX ReadEx;\r
- EFI_FILE_WRITE_EX WriteEx;\r
- EFI_FILE_FLUSH_EX FlushEx;\r
+ UINT64 Revision;\r
+ EFI_FILE_OPEN Open;\r
+ EFI_FILE_CLOSE Close;\r
+ EFI_FILE_DELETE Delete;\r
+ EFI_FILE_READ Read;\r
+ EFI_FILE_WRITE Write;\r
+ EFI_FILE_GET_POSITION GetPosition;\r
+ EFI_FILE_SET_POSITION SetPosition;\r
+ EFI_FILE_GET_INFO GetInfo;\r
+ EFI_FILE_SET_INFO SetInfo;\r
+ EFI_FILE_FLUSH Flush;\r
+ EFI_FILE_OPEN_EX OpenEx;\r
+ EFI_FILE_READ_EX ReadEx;\r
+ EFI_FILE_WRITE_EX WriteEx;\r
+ EFI_FILE_FLUSH_EX FlushEx;\r
};\r
\r
-\r
-extern EFI_GUID gEfiSimpleFileSystemProtocolGuid;\r
+extern EFI_GUID gEfiSimpleFileSystemProtocolGuid;\r
\r
#endif\r
0xA19832B9, 0xAC25, 0x11D3, {0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \\r
}\r
\r
-typedef struct _EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK_PROTOCOL;\r
-\r
+typedef struct _EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK_PROTOCOL;\r
\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK;\r
+typedef EFI_SIMPLE_NETWORK_PROTOCOL EFI_SIMPLE_NETWORK;\r
\r
///\r
/// Simple Network Protocol data structures.\r
/// Total number of frames received. Includes frames with errors and\r
/// dropped frames.\r
///\r
- UINT64 RxTotalFrames;\r
+ UINT64 RxTotalFrames;\r
\r
///\r
/// Number of valid frames received and copied into receive buffers.\r
///\r
- UINT64 RxGoodFrames;\r
+ UINT64 RxGoodFrames;\r
\r
///\r
/// Number of frames below the minimum length for the media.\r
/// This would be <64 for ethernet.\r
///\r
- UINT64 RxUndersizeFrames;\r
+ UINT64 RxUndersizeFrames;\r
\r
///\r
/// Number of frames longer than the maxminum length for the\r
/// media. This would be >1500 for ethernet.\r
///\r
- UINT64 RxOversizeFrames;\r
+ UINT64 RxOversizeFrames;\r
\r
///\r
/// Valid frames that were dropped because receive buffers were full.\r
///\r
- UINT64 RxDroppedFrames;\r
+ UINT64 RxDroppedFrames;\r
\r
///\r
/// Number of valid unicast frames received and not dropped.\r
///\r
- UINT64 RxUnicastFrames;\r
+ UINT64 RxUnicastFrames;\r
\r
///\r
/// Number of valid broadcast frames received and not dropped.\r
///\r
- UINT64 RxBroadcastFrames;\r
+ UINT64 RxBroadcastFrames;\r
\r
///\r
/// Number of valid mutlicast frames received and not dropped.\r
///\r
- UINT64 RxMulticastFrames;\r
+ UINT64 RxMulticastFrames;\r
\r
///\r
/// Number of frames w/ CRC or alignment errors.\r
///\r
- UINT64 RxCrcErrorFrames;\r
+ UINT64 RxCrcErrorFrames;\r
\r
///\r
/// Total number of bytes received. Includes frames with errors\r
/// and dropped frames.\r
//\r
- UINT64 RxTotalBytes;\r
+ UINT64 RxTotalBytes;\r
\r
///\r
/// Transmit statistics.\r
///\r
- UINT64 TxTotalFrames;\r
- UINT64 TxGoodFrames;\r
- UINT64 TxUndersizeFrames;\r
- UINT64 TxOversizeFrames;\r
- UINT64 TxDroppedFrames;\r
- UINT64 TxUnicastFrames;\r
- UINT64 TxBroadcastFrames;\r
- UINT64 TxMulticastFrames;\r
- UINT64 TxCrcErrorFrames;\r
- UINT64 TxTotalBytes;\r
+ UINT64 TxTotalFrames;\r
+ UINT64 TxGoodFrames;\r
+ UINT64 TxUndersizeFrames;\r
+ UINT64 TxOversizeFrames;\r
+ UINT64 TxDroppedFrames;\r
+ UINT64 TxUnicastFrames;\r
+ UINT64 TxBroadcastFrames;\r
+ UINT64 TxMulticastFrames;\r
+ UINT64 TxCrcErrorFrames;\r
+ UINT64 TxTotalBytes;\r
\r
///\r
/// Number of collisions detection on this subnet.\r
///\r
- UINT64 Collisions;\r
+ UINT64 Collisions;\r
\r
///\r
/// Number of frames destined for unsupported protocol.\r
///\r
- UINT64 UnsupportedProtocol;\r
+ UINT64 UnsupportedProtocol;\r
\r
///\r
/// Number of valid frames received that were duplicated.\r
///\r
- UINT64 RxDuplicatedFrames;\r
+ UINT64 RxDuplicatedFrames;\r
\r
///\r
/// Number of encrypted frames received that failed to decrypt.\r
///\r
- UINT64 RxDecryptErrorFrames;\r
+ UINT64 RxDecryptErrorFrames;\r
\r
///\r
/// Number of frames that failed to transmit after exceeding the retry limit.\r
///\r
- UINT64 TxErrorFrames;\r
+ UINT64 TxErrorFrames;\r
\r
///\r
/// Number of frames transmitted successfully after more than one attempt.\r
///\r
- UINT64 TxRetryFrames;\r
+ UINT64 TxRetryFrames;\r
} EFI_NETWORK_STATISTICS;\r
\r
///\r
#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS 0x08\r
#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10\r
\r
-#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT 0x01\r
-#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT 0x02\r
-#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT 0x04\r
-#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT 0x08\r
+#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT 0x01\r
+#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT 0x02\r
+#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT 0x04\r
+#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT 0x08\r
\r
-#define MAX_MCAST_FILTER_CNT 16\r
+#define MAX_MCAST_FILTER_CNT 16\r
typedef struct {\r
///\r
/// Reports the current state of the network interface.\r
///\r
- UINT32 State;\r
+ UINT32 State;\r
///\r
/// The size, in bytes, of the network interface's HW address.\r
///\r
- UINT32 HwAddressSize;\r
+ UINT32 HwAddressSize;\r
///\r
/// The size, in bytes, of the network interface's media header.\r
///\r
- UINT32 MediaHeaderSize;\r
+ UINT32 MediaHeaderSize;\r
///\r
/// The maximum size, in bytes, of the packets supported by the network interface.\r
///\r
- UINT32 MaxPacketSize;\r
+ UINT32 MaxPacketSize;\r
///\r
/// The size, in bytes, of the NVRAM device attached to the network interface.\r
///\r
- UINT32 NvRamSize;\r
+ UINT32 NvRamSize;\r
///\r
/// The size that must be used for all NVRAM reads and writes. The\r
/// start address for NVRAM read and write operations and the total\r
/// length of those operations, must be a multiple of this value. The\r
/// legal values for this field are 0, 1, 2, 4, and 8.\r
///\r
- UINT32 NvRamAccessSize;\r
+ UINT32 NvRamAccessSize;\r
///\r
/// The multicast receive filter settings supported by the network interface.\r
///\r
- UINT32 ReceiveFilterMask;\r
+ UINT32 ReceiveFilterMask;\r
///\r
/// The current multicast receive filter settings.\r
///\r
- UINT32 ReceiveFilterSetting;\r
+ UINT32 ReceiveFilterSetting;\r
///\r
/// The maximum number of multicast address receive filters supported by the driver.\r
///\r
- UINT32 MaxMCastFilterCount;\r
+ UINT32 MaxMCastFilterCount;\r
///\r
/// The current number of multicast address receive filters.\r
///\r
- UINT32 MCastFilterCount;\r
+ UINT32 MCastFilterCount;\r
///\r
/// Array containing the addresses of the current multicast address receive filters.\r
///\r
- EFI_MAC_ADDRESS MCastFilter[MAX_MCAST_FILTER_CNT];\r
+ EFI_MAC_ADDRESS MCastFilter[MAX_MCAST_FILTER_CNT];\r
///\r
/// The current HW MAC address for the network interface.\r
///\r
- EFI_MAC_ADDRESS CurrentAddress;\r
+ EFI_MAC_ADDRESS CurrentAddress;\r
///\r
/// The current HW MAC address for broadcast packets.\r
///\r
- EFI_MAC_ADDRESS BroadcastAddress;\r
+ EFI_MAC_ADDRESS BroadcastAddress;\r
///\r
/// The permanent HW MAC address for the network interface.\r
///\r
- EFI_MAC_ADDRESS PermanentAddress;\r
+ EFI_MAC_ADDRESS PermanentAddress;\r
///\r
/// The interface type of the network interface.\r
///\r
- UINT8 IfType;\r
+ UINT8 IfType;\r
///\r
/// TRUE if the HW MAC address can be changed.\r
///\r
- BOOLEAN MacAddressChangeable;\r
+ BOOLEAN MacAddressChangeable;\r
///\r
/// TRUE if the network interface can transmit more than one packet at a time.\r
///\r
- BOOLEAN MultipleTxSupported;\r
+ BOOLEAN MultipleTxSupported;\r
///\r
/// TRUE if the presence of media can be determined; otherwise FALSE.\r
///\r
- BOOLEAN MediaPresentSupported;\r
+ BOOLEAN MediaPresentSupported;\r
///\r
/// TRUE if media are connected to the network interface; otherwise FALSE.\r
///\r
- BOOLEAN MediaPresent;\r
+ BOOLEAN MediaPresent;\r
} EFI_SIMPLE_NETWORK_MODE;\r
\r
//\r
// Protocol Member Functions\r
//\r
+\r
/**\r
Changes the state of a network interface from "stopped" to "started".\r
\r
//\r
// Revision defined in EFI1.1\r
//\r
-#define EFI_SIMPLE_NETWORK_INTERFACE_REVISION EFI_SIMPLE_NETWORK_PROTOCOL_REVISION\r
+#define EFI_SIMPLE_NETWORK_INTERFACE_REVISION EFI_SIMPLE_NETWORK_PROTOCOL_REVISION\r
\r
///\r
/// The EFI_SIMPLE_NETWORK_PROTOCOL protocol is used to initialize access\r
/// be backwards compatible. If a future version is not backwards compatible\r
/// it is not the same GUID.\r
///\r
- UINT64 Revision;\r
- EFI_SIMPLE_NETWORK_START Start;\r
- EFI_SIMPLE_NETWORK_STOP Stop;\r
- EFI_SIMPLE_NETWORK_INITIALIZE Initialize;\r
- EFI_SIMPLE_NETWORK_RESET Reset;\r
- EFI_SIMPLE_NETWORK_SHUTDOWN Shutdown;\r
- EFI_SIMPLE_NETWORK_RECEIVE_FILTERS ReceiveFilters;\r
- EFI_SIMPLE_NETWORK_STATION_ADDRESS StationAddress;\r
- EFI_SIMPLE_NETWORK_STATISTICS Statistics;\r
- EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC MCastIpToMac;\r
- EFI_SIMPLE_NETWORK_NVDATA NvData;\r
- EFI_SIMPLE_NETWORK_GET_STATUS GetStatus;\r
- EFI_SIMPLE_NETWORK_TRANSMIT Transmit;\r
- EFI_SIMPLE_NETWORK_RECEIVE Receive;\r
+ UINT64 Revision;\r
+ EFI_SIMPLE_NETWORK_START Start;\r
+ EFI_SIMPLE_NETWORK_STOP Stop;\r
+ EFI_SIMPLE_NETWORK_INITIALIZE Initialize;\r
+ EFI_SIMPLE_NETWORK_RESET Reset;\r
+ EFI_SIMPLE_NETWORK_SHUTDOWN Shutdown;\r
+ EFI_SIMPLE_NETWORK_RECEIVE_FILTERS ReceiveFilters;\r
+ EFI_SIMPLE_NETWORK_STATION_ADDRESS StationAddress;\r
+ EFI_SIMPLE_NETWORK_STATISTICS Statistics;\r
+ EFI_SIMPLE_NETWORK_MCAST_IP_TO_MAC MCastIpToMac;\r
+ EFI_SIMPLE_NETWORK_NVDATA NvData;\r
+ EFI_SIMPLE_NETWORK_GET_STATUS GetStatus;\r
+ EFI_SIMPLE_NETWORK_TRANSMIT Transmit;\r
+ EFI_SIMPLE_NETWORK_RECEIVE Receive;\r
///\r
/// Event used with WaitForEvent() to wait for a packet to be received.\r
///\r
- EFI_EVENT WaitForPacket;\r
+ EFI_EVENT WaitForPacket;\r
///\r
/// Pointer to the EFI_SIMPLE_NETWORK_MODE data for the device.\r
///\r
- EFI_SIMPLE_NETWORK_MODE *Mode;\r
+ EFI_SIMPLE_NETWORK_MODE *Mode;\r
};\r
\r
-extern EFI_GUID gEfiSimpleNetworkProtocolGuid;\r
+extern EFI_GUID gEfiSimpleNetworkProtocolGuid;\r
\r
#endif\r
0x31878c87, 0xb75, 0x11d5, {0x9a, 0x4f, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \\r
}\r
\r
-typedef struct _EFI_SIMPLE_POINTER_PROTOCOL EFI_SIMPLE_POINTER_PROTOCOL;\r
+typedef struct _EFI_SIMPLE_POINTER_PROTOCOL EFI_SIMPLE_POINTER_PROTOCOL;\r
\r
//\r
// Data structures\r
///\r
/// The signed distance in counts that the pointer device has been moved along the x-axis.\r
///\r
- INT32 RelativeMovementX;\r
+ INT32 RelativeMovementX;\r
///\r
/// The signed distance in counts that the pointer device has been moved along the y-axis.\r
///\r
- INT32 RelativeMovementY;\r
+ INT32 RelativeMovementY;\r
///\r
/// The signed distance in counts that the pointer device has been moved along the z-axis.\r
///\r
- INT32 RelativeMovementZ;\r
+ INT32 RelativeMovementZ;\r
///\r
/// If TRUE, then the left button of the pointer device is being\r
/// pressed. If FALSE, then the left button of the pointer device is not being pressed.\r
///\r
- BOOLEAN LeftButton;\r
+ BOOLEAN LeftButton;\r
///\r
/// If TRUE, then the right button of the pointer device is being\r
/// pressed. If FALSE, then the right button of the pointer device is not being pressed.\r
///\r
- BOOLEAN RightButton;\r
+ BOOLEAN RightButton;\r
} EFI_SIMPLE_POINTER_STATE;\r
\r
typedef struct {\r
/// The resolution of the pointer device on the x-axis in counts/mm.\r
/// If 0, then the pointer device does not support an x-axis.\r
///\r
- UINT64 ResolutionX;\r
+ UINT64 ResolutionX;\r
///\r
/// The resolution of the pointer device on the y-axis in counts/mm.\r
/// If 0, then the pointer device does not support an x-axis.\r
///\r
- UINT64 ResolutionY;\r
+ UINT64 ResolutionY;\r
///\r
/// The resolution of the pointer device on the z-axis in counts/mm.\r
/// If 0, then the pointer device does not support an x-axis.\r
///\r
- UINT64 ResolutionZ;\r
+ UINT64 ResolutionZ;\r
///\r
/// TRUE if a left button is present on the pointer device. Otherwise FALSE.\r
///\r
- BOOLEAN LeftButton;\r
+ BOOLEAN LeftButton;\r
///\r
/// TRUE if a right button is present on the pointer device. Otherwise FALSE.\r
///\r
- BOOLEAN RightButton;\r
+ BOOLEAN RightButton;\r
} EFI_SIMPLE_POINTER_MODE;\r
\r
/**\r
/// retrieve the capabilities of the pointer device.\r
///\r
struct _EFI_SIMPLE_POINTER_PROTOCOL {\r
- EFI_SIMPLE_POINTER_RESET Reset;\r
- EFI_SIMPLE_POINTER_GET_STATE GetState;\r
+ EFI_SIMPLE_POINTER_RESET Reset;\r
+ EFI_SIMPLE_POINTER_GET_STATE GetState;\r
///\r
/// Event to use with WaitForEvent() to wait for input from the pointer device.\r
///\r
- EFI_EVENT WaitForInput;\r
+ EFI_EVENT WaitForInput;\r
///\r
/// Pointer to EFI_SIMPLE_POINTER_MODE data.\r
///\r
- EFI_SIMPLE_POINTER_MODE *Mode;\r
+ EFI_SIMPLE_POINTER_MODE *Mode;\r
};\r
\r
-extern EFI_GUID gEfiSimplePointerProtocolGuid;\r
+extern EFI_GUID gEfiSimplePointerProtocolGuid;\r
\r
#endif\r
0x387477c1, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \\r
}\r
\r
-typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL;\r
+typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL;\r
\r
///\r
/// Protocol GUID name defined in EFI1.1.\r
///\r
-#define SIMPLE_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID\r
+#define SIMPLE_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID\r
\r
///\r
/// Protocol name in EFI1.1 for backward-compatible.\r
///\r
-typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL SIMPLE_INPUT_INTERFACE;\r
+typedef struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL SIMPLE_INPUT_INTERFACE;\r
\r
///\r
/// The keystroke information for the key that was pressed.\r
///\r
typedef struct {\r
- UINT16 ScanCode;\r
- CHAR16 UnicodeChar;\r
+ UINT16 ScanCode;\r
+ CHAR16 UnicodeChar;\r
} EFI_INPUT_KEY;\r
\r
//\r
/// It is the minimum required protocol for ConsoleIn.\r
///\r
struct _EFI_SIMPLE_TEXT_INPUT_PROTOCOL {\r
- EFI_INPUT_RESET Reset;\r
- EFI_INPUT_READ_KEY ReadKeyStroke;\r
+ EFI_INPUT_RESET Reset;\r
+ EFI_INPUT_READ_KEY ReadKeyStroke;\r
///\r
/// Event to use with WaitForEvent() to wait for a key to be available\r
///\r
- EFI_EVENT WaitForKey;\r
+ EFI_EVENT WaitForKey;\r
};\r
\r
-extern EFI_GUID gEfiSimpleTextInProtocolGuid;\r
+extern EFI_GUID gEfiSimpleTextInProtocolGuid;\r
\r
#endif\r
#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \\r
{0xdd9e7534, 0x7762, 0x4698, { 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa } }\r
\r
-\r
typedef struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL;\r
\r
/**\r
(EFIAPI *EFI_INPUT_RESET_EX)(\r
IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
IN BOOLEAN ExtendedVerification\r
-);\r
-\r
+ );\r
\r
///\r
/// EFI_KEY_TOGGLE_STATE. The toggle states are defined.\r
/// returned value is valid only if the high\r
/// order bit has been set.\r
///\r
- UINT32 KeyShiftState;\r
+ UINT32 KeyShiftState;\r
///\r
/// Reflects the current internal state of\r
/// various toggled attributes. The returned\r
/// value is valid only if the high order\r
/// bit has been set.\r
///\r
- EFI_KEY_TOGGLE_STATE KeyToggleState;\r
+ EFI_KEY_TOGGLE_STATE KeyToggleState;\r
} EFI_KEY_STATE;\r
\r
typedef struct {\r
///\r
/// The EFI scan code and Unicode value returned from the input device.\r
///\r
- EFI_INPUT_KEY Key;\r
+ EFI_INPUT_KEY Key;\r
///\r
/// The current state of various toggled attributes as well as input modifier values.\r
///\r
- EFI_KEY_STATE KeyState;\r
+ EFI_KEY_STATE KeyState;\r
} EFI_KEY_DATA;\r
\r
//\r
//\r
// Shift state\r
//\r
-#define EFI_SHIFT_STATE_VALID 0x80000000\r
-#define EFI_RIGHT_SHIFT_PRESSED 0x00000001\r
-#define EFI_LEFT_SHIFT_PRESSED 0x00000002\r
-#define EFI_RIGHT_CONTROL_PRESSED 0x00000004\r
-#define EFI_LEFT_CONTROL_PRESSED 0x00000008\r
-#define EFI_RIGHT_ALT_PRESSED 0x00000010\r
-#define EFI_LEFT_ALT_PRESSED 0x00000020\r
-#define EFI_RIGHT_LOGO_PRESSED 0x00000040\r
-#define EFI_LEFT_LOGO_PRESSED 0x00000080\r
-#define EFI_MENU_KEY_PRESSED 0x00000100\r
-#define EFI_SYS_REQ_PRESSED 0x00000200\r
+#define EFI_SHIFT_STATE_VALID 0x80000000\r
+#define EFI_RIGHT_SHIFT_PRESSED 0x00000001\r
+#define EFI_LEFT_SHIFT_PRESSED 0x00000002\r
+#define EFI_RIGHT_CONTROL_PRESSED 0x00000004\r
+#define EFI_LEFT_CONTROL_PRESSED 0x00000008\r
+#define EFI_RIGHT_ALT_PRESSED 0x00000010\r
+#define EFI_LEFT_ALT_PRESSED 0x00000020\r
+#define EFI_RIGHT_LOGO_PRESSED 0x00000040\r
+#define EFI_LEFT_LOGO_PRESSED 0x00000080\r
+#define EFI_MENU_KEY_PRESSED 0x00000100\r
+#define EFI_SYS_REQ_PRESSED 0x00000200\r
\r
//\r
// Toggle state\r
//\r
-#define EFI_TOGGLE_STATE_VALID 0x80\r
-#define EFI_KEY_STATE_EXPOSED 0x40\r
-#define EFI_SCROLL_LOCK_ACTIVE 0x01\r
-#define EFI_NUM_LOCK_ACTIVE 0x02\r
-#define EFI_CAPS_LOCK_ACTIVE 0x04\r
+#define EFI_TOGGLE_STATE_VALID 0x80\r
+#define EFI_KEY_STATE_EXPOSED 0x40\r
+#define EFI_SCROLL_LOCK_ACTIVE 0x01\r
+#define EFI_NUM_LOCK_ACTIVE 0x02\r
+#define EFI_CAPS_LOCK_ACTIVE 0x04\r
\r
//\r
// EFI Scan codes\r
//\r
-#define SCAN_F11 0x0015\r
-#define SCAN_F12 0x0016\r
-#define SCAN_PAUSE 0x0048\r
-#define SCAN_F13 0x0068\r
-#define SCAN_F14 0x0069\r
-#define SCAN_F15 0x006A\r
-#define SCAN_F16 0x006B\r
-#define SCAN_F17 0x006C\r
-#define SCAN_F18 0x006D\r
-#define SCAN_F19 0x006E\r
-#define SCAN_F20 0x006F\r
-#define SCAN_F21 0x0070\r
-#define SCAN_F22 0x0071\r
-#define SCAN_F23 0x0072\r
-#define SCAN_F24 0x0073\r
-#define SCAN_MUTE 0x007F\r
-#define SCAN_VOLUME_UP 0x0080\r
-#define SCAN_VOLUME_DOWN 0x0081\r
-#define SCAN_BRIGHTNESS_UP 0x0100\r
-#define SCAN_BRIGHTNESS_DOWN 0x0101\r
-#define SCAN_SUSPEND 0x0102\r
-#define SCAN_HIBERNATE 0x0103\r
-#define SCAN_TOGGLE_DISPLAY 0x0104\r
-#define SCAN_RECOVERY 0x0105\r
-#define SCAN_EJECT 0x0106\r
+#define SCAN_F11 0x0015\r
+#define SCAN_F12 0x0016\r
+#define SCAN_PAUSE 0x0048\r
+#define SCAN_F13 0x0068\r
+#define SCAN_F14 0x0069\r
+#define SCAN_F15 0x006A\r
+#define SCAN_F16 0x006B\r
+#define SCAN_F17 0x006C\r
+#define SCAN_F18 0x006D\r
+#define SCAN_F19 0x006E\r
+#define SCAN_F20 0x006F\r
+#define SCAN_F21 0x0070\r
+#define SCAN_F22 0x0071\r
+#define SCAN_F23 0x0072\r
+#define SCAN_F24 0x0073\r
+#define SCAN_MUTE 0x007F\r
+#define SCAN_VOLUME_UP 0x0080\r
+#define SCAN_VOLUME_DOWN 0x0081\r
+#define SCAN_BRIGHTNESS_UP 0x0100\r
+#define SCAN_BRIGHTNESS_DOWN 0x0101\r
+#define SCAN_SUSPEND 0x0102\r
+#define SCAN_HIBERNATE 0x0103\r
+#define SCAN_TOGGLE_DISPLAY 0x0104\r
+#define SCAN_RECOVERY 0x0105\r
+#define SCAN_EJECT 0x0106\r
\r
/**\r
The function reads the next keystroke from the input device. If\r
(EFIAPI *EFI_INPUT_READ_KEY_EX)(\r
IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
OUT EFI_KEY_DATA *KeyData\r
-);\r
+ );\r
\r
/**\r
The SetState() function allows the input device hardware to\r
(EFIAPI *EFI_SET_STATE)(\r
IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
IN EFI_KEY_TOGGLE_STATE *KeyToggleState\r
-);\r
+ );\r
\r
///\r
/// The function will be called when the key sequence is typed specified by KeyData.\r
EFI_STATUS\r
(EFIAPI *EFI_KEY_NOTIFY_FUNCTION)(\r
IN EFI_KEY_DATA *KeyData\r
-);\r
+ );\r
\r
/**\r
The RegisterKeystrokeNotify() function registers a function\r
IN EFI_KEY_DATA *KeyData,\r
IN EFI_KEY_NOTIFY_FUNCTION KeyNotificationFunction,\r
OUT VOID **NotifyHandle\r
-);\r
+ );\r
\r
/**\r
The UnregisterKeystrokeNotify() function removes the\r
(EFIAPI *EFI_UNREGISTER_KEYSTROKE_NOTIFY)(\r
IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
IN VOID *NotificationHandle\r
-);\r
-\r
+ );\r
\r
///\r
/// The EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL is used on the ConsoleIn\r
/// which allows a variety of extended shift state information to be\r
/// returned.\r
///\r
-struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL{\r
- EFI_INPUT_RESET_EX Reset;\r
- EFI_INPUT_READ_KEY_EX ReadKeyStrokeEx;\r
+struct _EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL {\r
+ EFI_INPUT_RESET_EX Reset;\r
+ EFI_INPUT_READ_KEY_EX ReadKeyStrokeEx;\r
///\r
/// Event to use with WaitForEvent() to wait for a key to be available.\r
///\r
- EFI_EVENT WaitForKeyEx;\r
- EFI_SET_STATE SetState;\r
- EFI_REGISTER_KEYSTROKE_NOTIFY RegisterKeyNotify;\r
- EFI_UNREGISTER_KEYSTROKE_NOTIFY UnregisterKeyNotify;\r
+ EFI_EVENT WaitForKeyEx;\r
+ EFI_SET_STATE SetState;\r
+ EFI_REGISTER_KEYSTROKE_NOTIFY RegisterKeyNotify;\r
+ EFI_UNREGISTER_KEYSTROKE_NOTIFY UnregisterKeyNotify;\r
};\r
\r
-\r
-extern EFI_GUID gEfiSimpleTextInputExProtocolGuid;\r
+extern EFI_GUID gEfiSimpleTextInputExProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Protocol GUID defined in EFI1.1.\r
///\r
-#define SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID\r
+#define SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID\r
\r
typedef struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL;\r
\r
///\r
/// Backward-compatible with EFI1.1.\r
///\r
-typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL SIMPLE_TEXT_OUTPUT_INTERFACE;\r
+typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL SIMPLE_TEXT_OUTPUT_INTERFACE;\r
\r
//\r
// Defines for required EFI Unicode Box Draw characters\r
//\r
// EFI Required Geometric Shapes Code Chart\r
//\r
-#define GEOMETRICSHAPE_UP_TRIANGLE 0x25b2\r
-#define GEOMETRICSHAPE_RIGHT_TRIANGLE 0x25ba\r
-#define GEOMETRICSHAPE_DOWN_TRIANGLE 0x25bc\r
-#define GEOMETRICSHAPE_LEFT_TRIANGLE 0x25c4\r
+#define GEOMETRICSHAPE_UP_TRIANGLE 0x25b2\r
+#define GEOMETRICSHAPE_RIGHT_TRIANGLE 0x25ba\r
+#define GEOMETRICSHAPE_DOWN_TRIANGLE 0x25bc\r
+#define GEOMETRICSHAPE_LEFT_TRIANGLE 0x25c4\r
\r
//\r
// EFI Required Arrow shapes\r
//\r
-#define ARROW_LEFT 0x2190\r
-#define ARROW_UP 0x2191\r
-#define ARROW_RIGHT 0x2192\r
-#define ARROW_DOWN 0x2193\r
+#define ARROW_LEFT 0x2190\r
+#define ARROW_UP 0x2191\r
+#define ARROW_RIGHT 0x2192\r
+#define ARROW_DOWN 0x2193\r
\r
//\r
// EFI Console Colours\r
//\r
-#define EFI_BLACK 0x00\r
-#define EFI_BLUE 0x01\r
-#define EFI_GREEN 0x02\r
-#define EFI_CYAN (EFI_BLUE | EFI_GREEN)\r
-#define EFI_RED 0x04\r
-#define EFI_MAGENTA (EFI_BLUE | EFI_RED)\r
-#define EFI_BROWN (EFI_GREEN | EFI_RED)\r
-#define EFI_LIGHTGRAY (EFI_BLUE | EFI_GREEN | EFI_RED)\r
-#define EFI_BRIGHT 0x08\r
-#define EFI_DARKGRAY (EFI_BLACK | EFI_BRIGHT)\r
-#define EFI_LIGHTBLUE (EFI_BLUE | EFI_BRIGHT)\r
-#define EFI_LIGHTGREEN (EFI_GREEN | EFI_BRIGHT)\r
-#define EFI_LIGHTCYAN (EFI_CYAN | EFI_BRIGHT)\r
-#define EFI_LIGHTRED (EFI_RED | EFI_BRIGHT)\r
-#define EFI_LIGHTMAGENTA (EFI_MAGENTA | EFI_BRIGHT)\r
-#define EFI_YELLOW (EFI_BROWN | EFI_BRIGHT)\r
-#define EFI_WHITE (EFI_BLUE | EFI_GREEN | EFI_RED | EFI_BRIGHT)\r
+#define EFI_BLACK 0x00\r
+#define EFI_BLUE 0x01\r
+#define EFI_GREEN 0x02\r
+#define EFI_CYAN (EFI_BLUE | EFI_GREEN)\r
+#define EFI_RED 0x04\r
+#define EFI_MAGENTA (EFI_BLUE | EFI_RED)\r
+#define EFI_BROWN (EFI_GREEN | EFI_RED)\r
+#define EFI_LIGHTGRAY (EFI_BLUE | EFI_GREEN | EFI_RED)\r
+#define EFI_BRIGHT 0x08\r
+#define EFI_DARKGRAY (EFI_BLACK | EFI_BRIGHT)\r
+#define EFI_LIGHTBLUE (EFI_BLUE | EFI_BRIGHT)\r
+#define EFI_LIGHTGREEN (EFI_GREEN | EFI_BRIGHT)\r
+#define EFI_LIGHTCYAN (EFI_CYAN | EFI_BRIGHT)\r
+#define EFI_LIGHTRED (EFI_RED | EFI_BRIGHT)\r
+#define EFI_LIGHTMAGENTA (EFI_MAGENTA | EFI_BRIGHT)\r
+#define EFI_YELLOW (EFI_BROWN | EFI_BRIGHT)\r
+#define EFI_WHITE (EFI_BLUE | EFI_GREEN | EFI_RED | EFI_BRIGHT)\r
\r
//\r
// Macro to accept color values in their raw form to create\r
//\r
// Do not use EFI_BACKGROUND_xxx values with this macro.\r
//\r
-#define EFI_TEXT_ATTR(Foreground,Background) ((Foreground) | ((Background) << 4))\r
+#define EFI_TEXT_ATTR(Foreground, Background) ((Foreground) | ((Background) << 4))\r
\r
#define EFI_BACKGROUND_BLACK 0x00\r
#define EFI_BACKGROUND_BLUE 0x10\r
///\r
/// The number of modes supported by QueryMode () and SetMode ().\r
///\r
- INT32 MaxMode;\r
+ INT32 MaxMode;\r
\r
//\r
// current settings\r
///\r
/// The text mode of the output device(s).\r
///\r
- INT32 Mode;\r
+ INT32 Mode;\r
///\r
/// The current character output attribute.\r
///\r
- INT32 Attribute;\r
+ INT32 Attribute;\r
///\r
/// The cursor's column.\r
///\r
- INT32 CursorColumn;\r
+ INT32 CursorColumn;\r
///\r
/// The cursor's row.\r
///\r
- INT32 CursorRow;\r
+ INT32 CursorRow;\r
///\r
/// The cursor is currently visible or not.\r
///\r
- BOOLEAN CursorVisible;\r
+ BOOLEAN CursorVisible;\r
} EFI_SIMPLE_TEXT_OUTPUT_MODE;\r
\r
///\r
/// devices is at least 80 x 25 characters.\r
///\r
struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL {\r
- EFI_TEXT_RESET Reset;\r
+ EFI_TEXT_RESET Reset;\r
\r
- EFI_TEXT_STRING OutputString;\r
- EFI_TEXT_TEST_STRING TestString;\r
+ EFI_TEXT_STRING OutputString;\r
+ EFI_TEXT_TEST_STRING TestString;\r
\r
- EFI_TEXT_QUERY_MODE QueryMode;\r
- EFI_TEXT_SET_MODE SetMode;\r
- EFI_TEXT_SET_ATTRIBUTE SetAttribute;\r
+ EFI_TEXT_QUERY_MODE QueryMode;\r
+ EFI_TEXT_SET_MODE SetMode;\r
+ EFI_TEXT_SET_ATTRIBUTE SetAttribute;\r
\r
- EFI_TEXT_CLEAR_SCREEN ClearScreen;\r
- EFI_TEXT_SET_CURSOR_POSITION SetCursorPosition;\r
- EFI_TEXT_ENABLE_CURSOR EnableCursor;\r
+ EFI_TEXT_CLEAR_SCREEN ClearScreen;\r
+ EFI_TEXT_SET_CURSOR_POSITION SetCursorPosition;\r
+ EFI_TEXT_ENABLE_CURSOR EnableCursor;\r
\r
///\r
/// Pointer to SIMPLE_TEXT_OUTPUT_MODE data.\r
///\r
- EFI_SIMPLE_TEXT_OUTPUT_MODE *Mode;\r
+ EFI_SIMPLE_TEXT_OUTPUT_MODE *Mode;\r
};\r
\r
-extern EFI_GUID gEfiSimpleTextOutProtocolGuid;\r
+extern EFI_GUID gEfiSimpleTextOutProtocolGuid;\r
\r
#endif\r
0xd317f29b, 0xa325, 0x4712, {0x9b, 0xf1, 0xc6, 0x19, 0x54, 0xdc, 0x19, 0x8c} \\r
}\r
\r
-typedef struct _EFI_SMART_CARD_EDGE_PROTOCOL EFI_SMART_CARD_EDGE_PROTOCOL;\r
+typedef struct _EFI_SMART_CARD_EDGE_PROTOCOL EFI_SMART_CARD_EDGE_PROTOCOL;\r
\r
//\r
// Maximum size for a Smart Card AID (Application IDentifier)\r
//\r
-#define SCARD_AID_MAXSIZE 0x0010\r
+#define SCARD_AID_MAXSIZE 0x0010\r
//\r
// Size of CSN (Card Serial Number)\r
//\r
-#define SCARD_CSN_SIZE 0x0010\r
+#define SCARD_CSN_SIZE 0x0010\r
//\r
// Current specification version 1.00\r
//\r
-#define SMART_CARD_EDGE_PROTOCOL_VERSION_1 0x00000100\r
+#define SMART_CARD_EDGE_PROTOCOL_VERSION_1 0x00000100\r
//\r
// Parameters type definition\r
//\r
//\r
// value of tag field for header, the number of containers\r
//\r
-#define SC_EDGE_TAG_HEADER 0x0000\r
+#define SC_EDGE_TAG_HEADER 0x0000\r
//\r
// value of tag field for certificate\r
//\r
-#define SC_EDGE_TAG_CERT 0x0001\r
+#define SC_EDGE_TAG_CERT 0x0001\r
//\r
// value of tag field for key index associated with certificate\r
//\r
-#define SC_EDGE_TAG_KEY_ID 0x0002\r
+#define SC_EDGE_TAG_KEY_ID 0x0002\r
//\r
// value of tag field for key type\r
//\r
-#define SC_EDGE_TAG_KEY_TYPE 0x0003\r
+#define SC_EDGE_TAG_KEY_TYPE 0x0003\r
//\r
// value of tag field for key size\r
//\r
-#define SC_EDGE_TAG_KEY_SIZE 0x0004\r
+#define SC_EDGE_TAG_KEY_SIZE 0x0004\r
\r
//\r
// Length of L fields of TLV items\r
//\r
// size of L field for header\r
//\r
-#define SC_EDGE_L_SIZE_HEADER 1\r
+#define SC_EDGE_L_SIZE_HEADER 1\r
//\r
// size of L field for certificate (big endian)\r
//\r
-#define SC_EDGE_L_SIZE_CERT 2\r
+#define SC_EDGE_L_SIZE_CERT 2\r
//\r
// size of L field for key index\r
//\r
-#define SC_EDGE_L_SIZE_KEY_ID 1\r
+#define SC_EDGE_L_SIZE_KEY_ID 1\r
//\r
// size of L field for key type\r
//\r
-#define SC_EDGE_L_SIZE_KEY_TYPE 1\r
+#define SC_EDGE_L_SIZE_KEY_TYPE 1\r
//\r
// size of L field for key size (big endian)\r
//\r
-#define SC_EDGE_L_SIZE_KEY_SIZE 2\r
+#define SC_EDGE_L_SIZE_KEY_SIZE 2\r
\r
//\r
// Some TLV items have a fixed value for L field\r
//\r
// value of L field for header\r
//\r
-#define SC_EDGE_L_VALUE_HEADER 1\r
+#define SC_EDGE_L_VALUE_HEADER 1\r
//\r
// value of L field for key index\r
//\r
-#define SC_EDGE_L_VALUE_KEY_ID 1\r
+#define SC_EDGE_L_VALUE_KEY_ID 1\r
//\r
// value of L field for key type\r
//\r
-#define SC_EDGE_L_VALUE_KEY_TYPE 1\r
+#define SC_EDGE_L_VALUE_KEY_TYPE 1\r
//\r
// value of L field for key size\r
//\r
-#define SC_EDGE_L_VALUE_KEY_SIZE 2\r
+#define SC_EDGE_L_VALUE_KEY_SIZE 2\r
\r
//\r
// Possible values for key type\r
//\r
// RSA decryption\r
//\r
-#define SC_EDGE_RSA_EXCHANGE 0x01\r
+#define SC_EDGE_RSA_EXCHANGE 0x01\r
//\r
// RSA signature\r
//\r
-#define SC_EDGE_RSA_SIGNATURE 0x02\r
+#define SC_EDGE_RSA_SIGNATURE 0x02\r
//\r
// ECDSA signature\r
//\r
-#define SC_EDGE_ECDSA_256 0x03\r
+#define SC_EDGE_ECDSA_256 0x03\r
//\r
// ECDSA signature\r
//\r
-#define SC_EDGE_ECDSA_384 0x04\r
+#define SC_EDGE_ECDSA_384 0x04\r
//\r
// ECDSA signature\r
//\r
-#define SC_EDGE_ECDSA_521 0x05\r
+#define SC_EDGE_ECDSA_521 0x05\r
//\r
// ECDH agreement\r
//\r
-#define SC_EDGE_ECDH_256 0x06\r
+#define SC_EDGE_ECDH_256 0x06\r
//\r
// ECDH agreement\r
//\r
-#define SC_EDGE_ECDH_384 0x07\r
+#define SC_EDGE_ECDH_384 0x07\r
//\r
// ECDH agreement\r
//\r
-#define SC_EDGE_ECDH_521 0x08\r
+#define SC_EDGE_ECDH_521 0x08\r
\r
//\r
// Padding methods GUIDs for signature\r
0x9317ec24, 0x7cb0, 0x4d0e, {0x8b, 0x32, 0x2e, 0xd9, 0x20, 0x9c, 0xd8, 0xaf} \\r
}\r
\r
-extern EFI_GUID gEfiPaddingRsassaPkcs1V1P5Guid;\r
+extern EFI_GUID gEfiPaddingRsassaPkcs1V1P5Guid;\r
\r
//\r
// RSASSA-PSS padding method, for signature\r
0x7b2349e0, 0x522d, 0x4f8e, {0xb9, 0x27, 0x69, 0xd9, 0x7c, 0x9e, 0x79, 0x5f} \\r
}\r
\r
-extern EFI_GUID gEfiPaddingRsassaPssGuid;\r
+extern EFI_GUID gEfiPaddingRsassaPssGuid;\r
\r
//\r
// Padding methods GUIDs for decryption\r
0x3629ddb1, 0x228c, 0x452e, {0xb6, 0x16, 0x09, 0xed, 0x31, 0x6a, 0x97, 0x00} \\r
}\r
\r
-extern EFI_GUID gEfiPaddingNoneGuid;\r
+extern EFI_GUID gEfiPaddingNoneGuid;\r
\r
//\r
// RSAES-PKCS#1-V1.5 padding, for decryption\r
0xe1c1d0a9, 0x40b1, 0x4632, {0xbd, 0xcc, 0xd9, 0xd6, 0xe5, 0x29, 0x56, 0x31} \\r
}\r
\r
-extern EFI_GUID gEfiPaddingRsaesPkcs1V1P5Guid;\r
+extern EFI_GUID gEfiPaddingRsaesPkcs1V1P5Guid;\r
\r
//\r
// RSAES-OAEP padding, for decryption\r
0xc1e63ac4, 0xd0cf, 0x4ce6, {0x83, 0x5b, 0xee, 0xd0, 0xe6, 0xa8, 0xa4, 0x5b} \\r
}\r
\r
-extern EFI_GUID gEfiPaddingRsaesOaepGuid;\r
+extern EFI_GUID gEfiPaddingRsaesOaepGuid;\r
\r
/**\r
This function retrieves the context driver.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_CONTEXT) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_CONTEXT)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
- OUT UINTN *NumberAidSupported,\r
+ OUT UINTN *NumberAidSupported,\r
IN OUT UINTN *AidTableSize OPTIONAL,\r
- OUT SMART_CARD_AID *AidTable OPTIONAL,\r
- OUT UINTN *NumberSCPresent,\r
+ OUT SMART_CARD_AID *AidTable OPTIONAL,\r
+ OUT UINTN *NumberSCPresent,\r
IN OUT UINTN *CsnTableSize OPTIONAL,\r
- OUT SMART_CARD_CSN *CsnTable OPTIONAL,\r
- OUT UINT32 *VersionScEdgeProtocol OPTIONAL\r
+ OUT SMART_CARD_CSN *CsnTable OPTIONAL,\r
+ OUT UINT32 *VersionScEdgeProtocol OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_CONNECT) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_CONNECT)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
- OUT EFI_HANDLE *SCardHandle,\r
+ OUT EFI_HANDLE *SCardHandle,\r
IN UINT8 *ScardCsn OPTIONAL,\r
- OUT UINT8 *ScardAid OPTIONAL\r
+ OUT UINT8 *ScardAid OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_DISCONNECT) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_DISCONNECT)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_CSN) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_CSN)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
- OUT UINT8 Csn[SCARD_CSN_SIZE]\r
+ OUT UINT8 Csn[SCARD_CSN_SIZE]\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_READER_NAME) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_READER_NAME)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN OUT UINTN *ReaderNameLength,\r
- OUT CHAR16 *ReaderName OPTIONAL\r
+ OUT CHAR16 *ReaderName OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_VERIFY_PIN) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_VERIFY_PIN)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN INT32 PinSize,\r
IN UINT8 *PinCode,\r
- OUT BOOLEAN *PinResult,\r
- OUT UINT32 *RemainingAttempts OPTIONAL\r
+ OUT BOOLEAN *PinResult,\r
+ OUT UINT32 *RemainingAttempts OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_PIN_REMAINING) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_PIN_REMAINING)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
- OUT UINT32 *RemainingAttempts\r
+ OUT UINT32 *RemainingAttempts\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_DATA) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_DATA)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN EFI_GUID *DataId,\r
IN OUT UINTN *DataSize,\r
- OUT VOID *Data OPTIONAL\r
+ OUT VOID *Data OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_GET_CREDENTIAL) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_GET_CREDENTIAL)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN OUT UINTN *CredentialSize,\r
- OUT UINT8 *CredentialList OPTIONAL\r
+ OUT UINT8 *CredentialList OPTIONAL\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_SIGN_DATA) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_SIGN_DATA)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN UINTN KeyId,\r
IN EFI_GUID *HashAlgorithm,\r
IN EFI_GUID *PaddingMethod,\r
IN UINT8 *HashedData,\r
- OUT UINT8 *SignatureData\r
+ OUT UINT8 *SignatureData\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_DECRYPT_DATA) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_DECRYPT_DATA)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN UINTN KeyId,\r
IN UINTN EncryptedSize,\r
IN UINT8 *EncryptedData,\r
IN OUT UINTN *PlaintextSize,\r
- OUT UINT8 *PlaintextData\r
+ OUT UINT8 *PlaintextData\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT) (\r
+(EFIAPI *EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT)(\r
IN EFI_SMART_CARD_EDGE_PROTOCOL *This,\r
IN EFI_HANDLE SCardHandle,\r
IN UINTN KeyId,\r
IN UINT8 *dataQx,\r
IN UINT8 *dataQy,\r
- OUT UINT8 *DHAgreement\r
+ OUT UINT8 *DHAgreement\r
);\r
\r
///\r
/// smart card in the reader or to the reader itself.\r
///\r
struct _EFI_SMART_CARD_EDGE_PROTOCOL {\r
- EFI_SMART_CARD_EDGE_GET_CONTEXT GetContext;\r
- EFI_SMART_CARD_EDGE_CONNECT Connect;\r
- EFI_SMART_CARD_EDGE_DISCONNECT Disconnect;\r
- EFI_SMART_CARD_EDGE_GET_CSN GetCsn;\r
- EFI_SMART_CARD_EDGE_GET_READER_NAME GetReaderName;\r
- EFI_SMART_CARD_EDGE_VERIFY_PIN VerifyPin;\r
- EFI_SMART_CARD_EDGE_GET_PIN_REMAINING GetPinRemaining;\r
- EFI_SMART_CARD_EDGE_GET_DATA GetData;\r
- EFI_SMART_CARD_EDGE_GET_CREDENTIAL GetCredential;\r
- EFI_SMART_CARD_EDGE_SIGN_DATA SignData;\r
- EFI_SMART_CARD_EDGE_DECRYPT_DATA DecryptData;\r
- EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT BuildDHAgreement;\r
+ EFI_SMART_CARD_EDGE_GET_CONTEXT GetContext;\r
+ EFI_SMART_CARD_EDGE_CONNECT Connect;\r
+ EFI_SMART_CARD_EDGE_DISCONNECT Disconnect;\r
+ EFI_SMART_CARD_EDGE_GET_CSN GetCsn;\r
+ EFI_SMART_CARD_EDGE_GET_READER_NAME GetReaderName;\r
+ EFI_SMART_CARD_EDGE_VERIFY_PIN VerifyPin;\r
+ EFI_SMART_CARD_EDGE_GET_PIN_REMAINING GetPinRemaining;\r
+ EFI_SMART_CARD_EDGE_GET_DATA GetData;\r
+ EFI_SMART_CARD_EDGE_GET_CREDENTIAL GetCredential;\r
+ EFI_SMART_CARD_EDGE_SIGN_DATA SignData;\r
+ EFI_SMART_CARD_EDGE_DECRYPT_DATA DecryptData;\r
+ EFI_SMART_CARD_EDGE_BUILD_DH_AGREEMENT BuildDHAgreement;\r
};\r
\r
-extern EFI_GUID gEfiSmartCardEdgeProtocolGuid;\r
+extern EFI_GUID gEfiSmartCardEdgeProtocolGuid;\r
\r
#endif\r
-\r
0x2a4d1adf, 0x21dc, 0x4b81, {0xa4, 0x2f, 0x8b, 0x8e, 0xe2, 0x38, 0x00, 0x60} \\r
}\r
\r
-typedef struct _EFI_SMART_CARD_READER_PROTOCOL EFI_SMART_CARD_READER_PROTOCOL;\r
+typedef struct _EFI_SMART_CARD_READER_PROTOCOL EFI_SMART_CARD_READER_PROTOCOL;\r
\r
//\r
// Codes for access mode\r
//\r
-#define SCARD_AM_READER 0x0001 // Exclusive access to reader\r
-#define SCARD_AM_CARD 0x0002 // Exclusive access to card\r
+#define SCARD_AM_READER 0x0001 // Exclusive access to reader\r
+#define SCARD_AM_CARD 0x0002 // Exclusive access to card\r
//\r
// Codes for card action\r
//\r
-#define SCARD_CA_NORESET 0x0000 // Don't reset card\r
-#define SCARD_CA_COLDRESET 0x0001 // Perform a cold reset\r
-#define SCARD_CA_WARMRESET 0x0002 // Perform a warm reset\r
-#define SCARD_CA_UNPOWER 0x0003 // Power off the card\r
-#define SCARD_CA_EJECT 0x0004 // Eject the card\r
+#define SCARD_CA_NORESET 0x0000 // Don't reset card\r
+#define SCARD_CA_COLDRESET 0x0001 // Perform a cold reset\r
+#define SCARD_CA_WARMRESET 0x0002 // Perform a warm reset\r
+#define SCARD_CA_UNPOWER 0x0003 // Power off the card\r
+#define SCARD_CA_EJECT 0x0004 // Eject the card\r
//\r
// Protocol types\r
//\r
-#define SCARD_PROTOCOL_UNDEFINED 0x0000\r
-#define SCARD_PROTOCOL_T0 0x0001\r
-#define SCARD_PROTOCOL_T1 0x0002\r
-#define SCARD_PROTOCOL_RAW 0x0004\r
+#define SCARD_PROTOCOL_UNDEFINED 0x0000\r
+#define SCARD_PROTOCOL_T0 0x0001\r
+#define SCARD_PROTOCOL_T1 0x0002\r
+#define SCARD_PROTOCOL_RAW 0x0004\r
//\r
// Codes for state type\r
//\r
-#define SCARD_UNKNOWN 0x0000 /* state is unknown */\r
-#define SCARD_ABSENT 0x0001 /* Card is absent */\r
-#define SCARD_INACTIVE 0x0002 /* Card is present and not powered*/\r
-#define SCARD_ACTIVE 0x0003 /* Card is present and powered */\r
+#define SCARD_UNKNOWN 0x0000 /* state is unknown */\r
+#define SCARD_ABSENT 0x0001 /* Card is absent */\r
+#define SCARD_INACTIVE 0x0002 /* Card is present and not powered*/\r
+#define SCARD_ACTIVE 0x0003 /* Card is present and powered */\r
//\r
// Macro to generate a ControlCode & PC/SC part 10 control code\r
//\r
-#define SCARD_CTL_CODE(code) (0x42000000 + (code))\r
-#define CM_IOCTL_GET_FEATURE_REQUEST SCARD_CTL_CODE(3400)\r
+#define SCARD_CTL_CODE(code) (0x42000000 + (code))\r
+#define CM_IOCTL_GET_FEATURE_REQUEST SCARD_CTL_CODE(3400)\r
\r
/**\r
This function requests connection to the smart card or the reader, using the\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_CONNECT) (\r
+(EFIAPI *EFI_SMART_CARD_READER_CONNECT)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
IN UINT32 AccessMode,\r
IN UINT32 CardAction,\r
IN UINT32 PreferredProtocols,\r
- OUT UINT32 *ActiveProtocol\r
+ OUT UINT32 *ActiveProtocol\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_DISCONNECT) (\r
+(EFIAPI *EFI_SMART_CARD_READER_DISCONNECT)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
IN UINT32 CardAction\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_STATUS) (\r
+(EFIAPI *EFI_SMART_CARD_READER_STATUS)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
- OUT CHAR16 *ReaderName OPTIONAL,\r
+ OUT CHAR16 *ReaderName OPTIONAL,\r
IN OUT UINTN *ReaderNameLength OPTIONAL,\r
- OUT UINT32 *State OPTIONAL,\r
- OUT UINT32 *CardProtocol OPTIONAL,\r
- OUT UINT8 *Atr OPTIONAL,\r
+ OUT UINT32 *State OPTIONAL,\r
+ OUT UINT32 *CardProtocol OPTIONAL,\r
+ OUT UINT8 *Atr OPTIONAL,\r
IN OUT UINTN *AtrLength OPTIONAL\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_TRANSMIT) (\r
+(EFIAPI *EFI_SMART_CARD_READER_TRANSMIT)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
IN UINT8 *CAPDU,\r
IN UINTN CAPDULength,\r
- OUT UINT8 *RAPDU,\r
+ OUT UINT8 *RAPDU,\r
IN OUT UINTN *RAPDULength\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_CONTROL) (\r
+(EFIAPI *EFI_SMART_CARD_READER_CONTROL)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
IN UINT32 ControlCode,\r
IN UINT8 *InBuffer OPTIONAL,\r
IN UINTN InBufferLength OPTIONAL,\r
- OUT UINT8 *OutBuffer OPTIONAL,\r
+ OUT UINT8 *OutBuffer OPTIONAL,\r
IN OUT UINTN *OutBufferLength OPTIONAL\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SMART_CARD_READER_GET_ATTRIB) (\r
+(EFIAPI *EFI_SMART_CARD_READER_GET_ATTRIB)(\r
IN EFI_SMART_CARD_READER_PROTOCOL *This,\r
IN UINT32 Attrib,\r
- OUT UINT8 *OutBuffer,\r
+ OUT UINT8 *OutBuffer,\r
IN OUT UINTN *OutBufferLength\r
);\r
\r
/// smart card in the reader or to the reader itself.\r
///\r
struct _EFI_SMART_CARD_READER_PROTOCOL {\r
- EFI_SMART_CARD_READER_CONNECT SCardConnect;\r
- EFI_SMART_CARD_READER_DISCONNECT SCardDisconnect;\r
- EFI_SMART_CARD_READER_STATUS SCardStatus;\r
- EFI_SMART_CARD_READER_TRANSMIT SCardTransmit;\r
- EFI_SMART_CARD_READER_CONTROL SCardControl;\r
- EFI_SMART_CARD_READER_GET_ATTRIB SCardGetAttrib;\r
+ EFI_SMART_CARD_READER_CONNECT SCardConnect;\r
+ EFI_SMART_CARD_READER_DISCONNECT SCardDisconnect;\r
+ EFI_SMART_CARD_READER_STATUS SCardStatus;\r
+ EFI_SMART_CARD_READER_TRANSMIT SCardTransmit;\r
+ EFI_SMART_CARD_READER_CONTROL SCardControl;\r
+ EFI_SMART_CARD_READER_GET_ATTRIB SCardGetAttrib;\r
};\r
\r
-extern EFI_GUID gEfiSmartCardReaderProtocolGuid;\r
+extern EFI_GUID gEfiSmartCardReaderProtocolGuid;\r
\r
#endif\r
-\r
#define EFI_SMBIOS_PROTOCOL_GUID \\r
{ 0x3583ff6, 0xcb36, 0x4940, { 0x94, 0x7e, 0xb9, 0xb3, 0x9f, 0x4a, 0xfa, 0xf7 }}\r
\r
-#define EFI_SMBIOS_TYPE_BIOS_INFORMATION SMBIOS_TYPE_BIOS_INFORMATION\r
-#define EFI_SMBIOS_TYPE_SYSTEM_INFORMATION SMBIOS_TYPE_SYSTEM_INFORMATION\r
-#define EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION SMBIOS_TYPE_BASEBOARD_INFORMATION\r
-#define EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE SMBIOS_TYPE_SYSTEM_ENCLOSURE\r
-#define EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION SMBIOS_TYPE_PROCESSOR_INFORMATION\r
-#define EFI_SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION\r
-#define EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON SMBIOS_TYPE_MEMORY_MODULE_INFORMATON\r
-#define EFI_SMBIOS_TYPE_CACHE_INFORMATION SMBIOS_TYPE_CACHE_INFORMATION\r
-#define EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION\r
-#define EFI_SMBIOS_TYPE_SYSTEM_SLOTS SMBIOS_TYPE_SYSTEM_SLOTS\r
-#define EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION\r
-#define EFI_SMBIOS_TYPE_OEM_STRINGS SMBIOS_TYPE_OEM_STRINGS\r
-#define EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS\r
-#define EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION\r
-#define EFI_SMBIOS_TYPE_GROUP_ASSOCIATIONS SMBIOS_TYPE_GROUP_ASSOCIATIONS\r
-#define EFI_SMBIOS_TYPE_SYSTEM_EVENT_LOG SMBIOS_TYPE_SYSTEM_EVENT_LOG\r
-#define EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY\r
-#define EFI_SMBIOS_TYPE_MEMORY_DEVICE SMBIOS_TYPE_MEMORY_DEVICE\r
-#define EFI_SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION\r
-#define EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS\r
-#define EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS\r
-#define EFI_SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE\r
-#define EFI_SMBIOS_TYPE_PORTABLE_BATTERY SMBIOS_TYPE_PORTABLE_BATTERY\r
-#define EFI_SMBIOS_TYPE_SYSTEM_RESET SMBIOS_TYPE_SYSTEM_RESET\r
-#define EFI_SMBIOS_TYPE_HARDWARE_SECURITY SMBIOS_TYPE_HARDWARE_SECURITY\r
-#define EFI_SMBIOS_TYPE_SYSTEM_POWER_CONTROLS SMBIOS_TYPE_SYSTEM_POWER_CONTROLS\r
-#define EFI_SMBIOS_TYPE_VOLTAGE_PROBE SMBIOS_TYPE_VOLTAGE_PROBE\r
-#define EFI_SMBIOS_TYPE_COOLING_DEVICE SMBIOS_TYPE_COOLING_DEVICE\r
-#define EFI_SMBIOS_TYPE_TEMPERATURE_PROBE SMBIOS_TYPE_TEMPERATURE_PROBE\r
-#define EFI_SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE\r
-#define EFI_SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS\r
-#define EFI_SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE\r
-#define EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION\r
-#define EFI_SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION\r
-#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE SMBIOS_TYPE_MANAGEMENT_DEVICE\r
-#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT\r
-#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA\r
-#define EFI_SMBIOS_TYPE_MEMORY_CHANNEL SMBIOS_TYPE_MEMORY_CHANNEL\r
-#define EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION SMBIOS_TYPE_IPMI_DEVICE_INFORMATION\r
-#define EFI_SMBIOS_TYPE_SYSTEM_POWER_SUPPLY SMBIOS_TYPE_SYSTEM_POWER_SUPPLY\r
-#define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION SMBIOS_TYPE_ADDITIONAL_INFORMATION\r
-#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION\r
-#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE\r
-#define EFI_SMBIOS_TYPE_INACTIVE SMBIOS_TYPE_INACTIVE\r
-#define EFI_SMBIOS_TYPE_END_OF_TABLE SMBIOS_TYPE_END_OF_TABLE\r
-#define EFI_SMBIOS_OEM_BEGIN SMBIOS_OEM_BEGIN\r
-#define EFI_SMBIOS_OEM_END SMBIOS_OEM_END\r
-\r
-typedef SMBIOS_TABLE_STRING EFI_SMBIOS_STRING;\r
-typedef SMBIOS_TYPE EFI_SMBIOS_TYPE;\r
-typedef SMBIOS_HANDLE EFI_SMBIOS_HANDLE;\r
-typedef SMBIOS_STRUCTURE EFI_SMBIOS_TABLE_HEADER;\r
+#define EFI_SMBIOS_TYPE_BIOS_INFORMATION SMBIOS_TYPE_BIOS_INFORMATION\r
+#define EFI_SMBIOS_TYPE_SYSTEM_INFORMATION SMBIOS_TYPE_SYSTEM_INFORMATION\r
+#define EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION SMBIOS_TYPE_BASEBOARD_INFORMATION\r
+#define EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE SMBIOS_TYPE_SYSTEM_ENCLOSURE\r
+#define EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION SMBIOS_TYPE_PROCESSOR_INFORMATION\r
+#define EFI_SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION SMBIOS_TYPE_MEMORY_CONTROLLER_INFORMATION\r
+#define EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON SMBIOS_TYPE_MEMORY_MODULE_INFORMATON\r
+#define EFI_SMBIOS_TYPE_CACHE_INFORMATION SMBIOS_TYPE_CACHE_INFORMATION\r
+#define EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION\r
+#define EFI_SMBIOS_TYPE_SYSTEM_SLOTS SMBIOS_TYPE_SYSTEM_SLOTS\r
+#define EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION\r
+#define EFI_SMBIOS_TYPE_OEM_STRINGS SMBIOS_TYPE_OEM_STRINGS\r
+#define EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS\r
+#define EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION\r
+#define EFI_SMBIOS_TYPE_GROUP_ASSOCIATIONS SMBIOS_TYPE_GROUP_ASSOCIATIONS\r
+#define EFI_SMBIOS_TYPE_SYSTEM_EVENT_LOG SMBIOS_TYPE_SYSTEM_EVENT_LOG\r
+#define EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY\r
+#define EFI_SMBIOS_TYPE_MEMORY_DEVICE SMBIOS_TYPE_MEMORY_DEVICE\r
+#define EFI_SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_32BIT_MEMORY_ERROR_INFORMATION\r
+#define EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS\r
+#define EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS\r
+#define EFI_SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE SMBIOS_TYPE_BUILT_IN_POINTING_DEVICE\r
+#define EFI_SMBIOS_TYPE_PORTABLE_BATTERY SMBIOS_TYPE_PORTABLE_BATTERY\r
+#define EFI_SMBIOS_TYPE_SYSTEM_RESET SMBIOS_TYPE_SYSTEM_RESET\r
+#define EFI_SMBIOS_TYPE_HARDWARE_SECURITY SMBIOS_TYPE_HARDWARE_SECURITY\r
+#define EFI_SMBIOS_TYPE_SYSTEM_POWER_CONTROLS SMBIOS_TYPE_SYSTEM_POWER_CONTROLS\r
+#define EFI_SMBIOS_TYPE_VOLTAGE_PROBE SMBIOS_TYPE_VOLTAGE_PROBE\r
+#define EFI_SMBIOS_TYPE_COOLING_DEVICE SMBIOS_TYPE_COOLING_DEVICE\r
+#define EFI_SMBIOS_TYPE_TEMPERATURE_PROBE SMBIOS_TYPE_TEMPERATURE_PROBE\r
+#define EFI_SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE SMBIOS_TYPE_ELECTRICAL_CURRENT_PROBE\r
+#define EFI_SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS SMBIOS_TYPE_OUT_OF_BAND_REMOTE_ACCESS\r
+#define EFI_SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE SMBIOS_TYPE_BOOT_INTEGRITY_SERVICE\r
+#define EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION\r
+#define EFI_SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION SMBIOS_TYPE_64BIT_MEMORY_ERROR_INFORMATION\r
+#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE SMBIOS_TYPE_MANAGEMENT_DEVICE\r
+#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT SMBIOS_TYPE_MANAGEMENT_DEVICE_COMPONENT\r
+#define EFI_SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA SMBIOS_TYPE_MANAGEMENT_DEVICE_THRESHOLD_DATA\r
+#define EFI_SMBIOS_TYPE_MEMORY_CHANNEL SMBIOS_TYPE_MEMORY_CHANNEL\r
+#define EFI_SMBIOS_TYPE_IPMI_DEVICE_INFORMATION SMBIOS_TYPE_IPMI_DEVICE_INFORMATION\r
+#define EFI_SMBIOS_TYPE_SYSTEM_POWER_SUPPLY SMBIOS_TYPE_SYSTEM_POWER_SUPPLY\r
+#define EFI_SMBIOS_TYPE_ADDITIONAL_INFORMATION SMBIOS_TYPE_ADDITIONAL_INFORMATION\r
+#define EFI_SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION\r
+#define EFI_SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE\r
+#define EFI_SMBIOS_TYPE_INACTIVE SMBIOS_TYPE_INACTIVE\r
+#define EFI_SMBIOS_TYPE_END_OF_TABLE SMBIOS_TYPE_END_OF_TABLE\r
+#define EFI_SMBIOS_OEM_BEGIN SMBIOS_OEM_BEGIN\r
+#define EFI_SMBIOS_OEM_END SMBIOS_OEM_END\r
+\r
+typedef SMBIOS_TABLE_STRING EFI_SMBIOS_STRING;\r
+typedef SMBIOS_TYPE EFI_SMBIOS_TYPE;\r
+typedef SMBIOS_HANDLE EFI_SMBIOS_HANDLE;\r
+typedef SMBIOS_STRUCTURE EFI_SMBIOS_TABLE_HEADER;\r
\r
typedef struct _EFI_SMBIOS_PROTOCOL EFI_SMBIOS_PROTOCOL;\r
\r
IN EFI_HANDLE ProducerHandle OPTIONAL,\r
IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle,\r
IN EFI_SMBIOS_TABLE_HEADER *Record\r
-);\r
+ );\r
\r
/**\r
Update the string associated with an existing SMBIOS record.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SMBIOS_UPDATE_STRING)(\r
- IN CONST EFI_SMBIOS_PROTOCOL *This,\r
- IN EFI_SMBIOS_HANDLE *SmbiosHandle,\r
- IN UINTN *StringNumber,\r
- IN CHAR8 *String\r
-);\r
+ IN CONST EFI_SMBIOS_PROTOCOL *This,\r
+ IN EFI_SMBIOS_HANDLE *SmbiosHandle,\r
+ IN UINTN *StringNumber,\r
+ IN CHAR8 *String\r
+ );\r
\r
/**\r
Remove an SMBIOS record.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SMBIOS_REMOVE)(\r
- IN CONST EFI_SMBIOS_PROTOCOL *This,\r
- IN EFI_SMBIOS_HANDLE SmbiosHandle\r
-);\r
+ IN CONST EFI_SMBIOS_PROTOCOL *This,\r
+ IN EFI_SMBIOS_HANDLE SmbiosHandle\r
+ );\r
\r
/**\r
Allow the caller to discover all or some of the SMBIOS records.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_SMBIOS_GET_NEXT)(\r
- IN CONST EFI_SMBIOS_PROTOCOL *This,\r
- IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle,\r
- IN EFI_SMBIOS_TYPE *Type OPTIONAL,\r
- OUT EFI_SMBIOS_TABLE_HEADER **Record,\r
- OUT EFI_HANDLE *ProducerHandle OPTIONAL\r
-);\r
+ IN CONST EFI_SMBIOS_PROTOCOL *This,\r
+ IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle,\r
+ IN EFI_SMBIOS_TYPE *Type OPTIONAL,\r
+ OUT EFI_SMBIOS_TABLE_HEADER **Record,\r
+ OUT EFI_HANDLE *ProducerHandle OPTIONAL\r
+ );\r
\r
struct _EFI_SMBIOS_PROTOCOL {\r
- EFI_SMBIOS_ADD Add;\r
- EFI_SMBIOS_UPDATE_STRING UpdateString;\r
- EFI_SMBIOS_REMOVE Remove;\r
- EFI_SMBIOS_GET_NEXT GetNext;\r
- UINT8 MajorVersion; ///< The major revision of the SMBIOS specification supported.\r
- UINT8 MinorVersion; ///< The minor revision of the SMBIOS specification supported.\r
+ EFI_SMBIOS_ADD Add;\r
+ EFI_SMBIOS_UPDATE_STRING UpdateString;\r
+ EFI_SMBIOS_REMOVE Remove;\r
+ EFI_SMBIOS_GET_NEXT GetNext;\r
+ UINT8 MajorVersion; ///< The major revision of the SMBIOS specification supported.\r
+ UINT8 MinorVersion; ///< The minor revision of the SMBIOS specification supported.\r
};\r
\r
-extern EFI_GUID gEfiSmbiosProtocolGuid;\r
+extern EFI_GUID gEfiSmbiosProtocolGuid;\r
\r
#endif // __SMBIOS_PROTOCOL_H__\r
IN BOOLEAN PecCheck,\r
IN OUT UINTN *Length,\r
IN OUT VOID *Buffer\r
-);\r
-\r
-\r
+ );\r
\r
/**\r
\r
IN BOOLEAN ArpAll,\r
IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL,\r
IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL\r
-);\r
-\r
+ );\r
\r
/**\r
The GetArpMap() function returns the mapping of all the SMBus devices\r
IN CONST EFI_SMBUS_HC_PROTOCOL *This,\r
IN OUT UINTN *Length,\r
IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap\r
-);\r
+ );\r
\r
/**\r
The notify function does some actions.\r
(EFIAPI *EFI_SMBUS_NOTIFY_FUNCTION)(\r
IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,\r
IN UINTN Data\r
-);\r
-\r
+ );\r
\r
/**\r
\r
IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,\r
IN UINTN Data,\r
IN EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction\r
-);\r
-\r
+ );\r
\r
///\r
/// The EFI_SMBUS_HC_PROTOCOL provides SMBus host controller management and basic data\r
/// host controller.\r
///\r
struct _EFI_SMBUS_HC_PROTOCOL {\r
- EFI_SMBUS_HC_EXECUTE_OPERATION Execute;\r
- EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE ArpDevice;\r
- EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP GetArpMap;\r
- EFI_SMBUS_HC_PROTOCOL_NOTIFY Notify;\r
+ EFI_SMBUS_HC_EXECUTE_OPERATION Execute;\r
+ EFI_SMBUS_HC_PROTOCOL_ARP_DEVICE ArpDevice;\r
+ EFI_SMBUS_HC_PROTOCOL_GET_ARP_MAP GetArpMap;\r
+ EFI_SMBUS_HC_PROTOCOL_NOTIFY Notify;\r
};\r
\r
-\r
-extern EFI_GUID gEfiSmbusHcProtocolGuid;\r
+extern EFI_GUID gEfiSmbusHcProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/MmAccess.h>\r
\r
-#define EFI_SMM_ACCESS2_PROTOCOL_GUID EFI_MM_ACCESS_PROTOCOL_GUID\r
+#define EFI_SMM_ACCESS2_PROTOCOL_GUID EFI_MM_ACCESS_PROTOCOL_GUID\r
\r
-typedef EFI_MM_ACCESS_PROTOCOL EFI_SMM_ACCESS2_PROTOCOL;\r
+typedef EFI_MM_ACCESS_PROTOCOL EFI_SMM_ACCESS2_PROTOCOL;\r
\r
typedef EFI_MM_OPEN EFI_SMM_OPEN2;\r
\r
typedef EFI_MM_LOCK EFI_SMM_LOCK2;\r
\r
typedef EFI_MM_CAPABILITIES EFI_SMM_CAPABILITIES2;\r
-extern EFI_GUID gEfiSmmAccess2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmAccess2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#define EFI_SMM_BASE2_PROTOCOL_GUID EFI_MM_BASE_PROTOCOL_GUID\r
\r
-typedef struct _EFI_SMM_BASE2_PROTOCOL EFI_SMM_BASE2_PROTOCOL;\r
+typedef struct _EFI_SMM_BASE2_PROTOCOL EFI_SMM_BASE2_PROTOCOL;\r
\r
/**\r
Service to indicate whether the driver is currently executing in the SMM Initialization phase.\r
/// services and determine whether the driver is being invoked inside SMRAM or outside of SMRAM.\r
///\r
struct _EFI_SMM_BASE2_PROTOCOL {\r
- EFI_SMM_INSIDE_OUT2 InSmm;\r
- EFI_SMM_GET_SMST_LOCATION2 GetSmstLocation;\r
+ EFI_SMM_INSIDE_OUT2 InSmm;\r
+ EFI_SMM_GET_SMST_LOCATION2 GetSmstLocation;\r
};\r
\r
-extern EFI_GUID gEfiSmmBase2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmBase2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmCommunication.h>\r
\r
-\r
typedef EFI_MM_COMMUNICATE_HEADER EFI_SMM_COMMUNICATE_HEADER;\r
\r
-#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID EFI_MM_COMMUNICATION_PROTOCOL_GUID\r
+#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID EFI_MM_COMMUNICATION_PROTOCOL_GUID\r
\r
typedef EFI_MM_COMMUNICATION_PROTOCOL EFI_SMM_COMMUNICATION_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSmmCommunicationProtocolGuid;\r
+extern EFI_GUID gEfiSmmCommunicationProtocolGuid;\r
\r
#endif\r
-\r
#include <Protocol/MmConfiguration.h>\r
#include <Pi/PiSmmCis.h>\r
\r
-#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID EFI_MM_CONFIGURATION_PROTOCOL_GUID\r
+#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID EFI_MM_CONFIGURATION_PROTOCOL_GUID\r
\r
///\r
/// Structure describing a SMRAM region which cannot be used for the SMRAM heap.\r
UINT64 SmramReservedSize;\r
} EFI_SMM_RESERVED_SMRAM_REGION;\r
\r
-typedef struct _EFI_SMM_CONFIGURATION_PROTOCOL EFI_SMM_CONFIGURATION_PROTOCOL;\r
+typedef struct _EFI_SMM_CONFIGURATION_PROTOCOL EFI_SMM_CONFIGURATION_PROTOCOL;\r
\r
/**\r
Register the SMM Foundation entry point.\r
///\r
/// A pointer to an array SMRAM ranges used by the initial SMM entry code.\r
///\r
- EFI_SMM_RESERVED_SMRAM_REGION *SmramReservedRegions;\r
- EFI_SMM_REGISTER_SMM_ENTRY RegisterSmmEntry;\r
+ EFI_SMM_RESERVED_SMRAM_REGION *SmramReservedRegions;\r
+ EFI_SMM_REGISTER_SMM_ENTRY RegisterSmmEntry;\r
};\r
\r
-extern EFI_GUID gEfiSmmConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiSmmConfigurationProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmControl.h>\r
\r
-#define EFI_SMM_CONTROL2_PROTOCOL_GUID EFI_MM_CONTROL_PROTOCOL_GUID\r
+#define EFI_SMM_CONTROL2_PROTOCOL_GUID EFI_MM_CONTROL_PROTOCOL_GUID\r
\r
typedef EFI_MM_CONTROL_PROTOCOL EFI_SMM_CONTROL2_PROTOCOL;\r
-typedef EFI_MM_PERIOD EFI_SMM_PERIOD;\r
+typedef EFI_MM_PERIOD EFI_SMM_PERIOD;\r
\r
typedef EFI_MM_ACTIVATE EFI_SMM_ACTIVATE2;\r
\r
typedef EFI_MM_DEACTIVATE EFI_SMM_DEACTIVATE2;\r
-extern EFI_GUID gEfiSmmControl2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmControl2ProtocolGuid;\r
\r
#endif\r
-\r
#define EFI_SMM_SAVE_STATE_REGISTER_LMA EFI_MM_SAVE_STATE_REGISTER_LMA\r
#define EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID\r
\r
-typedef EFI_MM_SAVE_STATE_REGISTER EFI_SMM_SAVE_STATE_REGISTER;\r
-\r
-\r
-#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT\r
-#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT\r
+typedef EFI_MM_SAVE_STATE_REGISTER EFI_SMM_SAVE_STATE_REGISTER;\r
\r
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT\r
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT\r
\r
///\r
/// Size width of I/O instruction\r
///\r
-#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 EFI_MM_SAVE_STATE_IO_WIDTH_UINT8\r
-#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 EFI_MM_SAVE_STATE_IO_WIDTH_UINT16\r
-#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 EFI_MM_SAVE_STATE_IO_WIDTH_UINT32\r
-#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 EFI_MM_SAVE_STATE_IO_WIDTH_UINT64\r
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 EFI_MM_SAVE_STATE_IO_WIDTH_UINT8\r
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 EFI_MM_SAVE_STATE_IO_WIDTH_UINT16\r
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 EFI_MM_SAVE_STATE_IO_WIDTH_UINT32\r
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 EFI_MM_SAVE_STATE_IO_WIDTH_UINT64\r
typedef EFI_MM_SAVE_STATE_IO_WIDTH EFI_SMM_SAVE_STATE_IO_WIDTH;\r
\r
///\r
/// Types of I/O instruction\r
///\r
-#define EFI_SMM_SAVE_STATE_IO_TYPE_INPUT EFI_MM_SAVE_STATE_IO_TYPE_INPUT\r
-#define EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT\r
-#define EFI_SMM_SAVE_STATE_IO_TYPE_STRING EFI_MM_SAVE_STATE_IO_TYPE_STRING\r
-#define EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX\r
+#define EFI_SMM_SAVE_STATE_IO_TYPE_INPUT EFI_MM_SAVE_STATE_IO_TYPE_INPUT\r
+#define EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT\r
+#define EFI_SMM_SAVE_STATE_IO_TYPE_STRING EFI_MM_SAVE_STATE_IO_TYPE_STRING\r
+#define EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX\r
typedef EFI_MM_SAVE_STATE_IO_TYPE EFI_SMM_SAVE_STATE_IO_TYPE;\r
\r
typedef EFI_MM_SAVE_STATE_IO_INFO EFI_SMM_SAVE_STATE_IO_INFO;\r
typedef EFI_MM_READ_SAVE_STATE EFI_SMM_READ_SAVE_STATE;\r
\r
typedef EFI_MM_WRITE_SAVE_STATE EFI_SMM_WRITE_SAVE_STATE;\r
-extern EFI_GUID gEfiSmmCpuProtocolGuid;\r
+extern EFI_GUID gEfiSmmCpuProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmCpuIo.h>\r
\r
-#define EFI_SMM_CPU_IO2_PROTOCOL_GUID EFI_MM_CPU_IO_PROTOCOL_GUID\r
+#define EFI_SMM_CPU_IO2_PROTOCOL_GUID EFI_MM_CPU_IO_PROTOCOL_GUID\r
\r
-typedef EFI_MM_CPU_IO_PROTOCOL EFI_SMM_CPU_IO2_PROTOCOL;\r
+typedef EFI_MM_CPU_IO_PROTOCOL EFI_SMM_CPU_IO2_PROTOCOL;\r
\r
///\r
/// Width of the SMM CPU I/O operations\r
///\r
-#define SMM_IO_UINT8 MM_IO_UINT8\r
-#define SMM_IO_UINT16 MM_IO_UINT16\r
-#define SMM_IO_UINT32 MM_IO_UINT32\r
-#define SMM_IO_UINT64 MM_IO_UINT64\r
+#define SMM_IO_UINT8 MM_IO_UINT8\r
+#define SMM_IO_UINT16 MM_IO_UINT16\r
+#define SMM_IO_UINT32 MM_IO_UINT32\r
+#define SMM_IO_UINT64 MM_IO_UINT64\r
\r
typedef EFI_MM_IO_WIDTH EFI_SMM_IO_WIDTH;\r
-typedef EFI_MM_CPU_IO EFI_SMM_CPU_IO2;\r
+typedef EFI_MM_CPU_IO EFI_SMM_CPU_IO2;\r
\r
typedef EFI_MM_IO_ACCESS EFI_SMM_IO_ACCESS2;\r
\r
-extern EFI_GUID gEfiSmmCpuIo2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmCpuIo2ProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/MmEndOfDxe.h>\r
\r
-#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID EFI_MM_END_OF_DXE_PROTOCOL_GUID\r
+#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID EFI_MM_END_OF_DXE_PROTOCOL_GUID\r
\r
-extern EFI_GUID gEfiSmmEndOfDxeProtocolGuid;\r
+extern EFI_GUID gEfiSmmEndOfDxeProtocolGuid;\r
\r
#endif\r
#include <Protocol/MmGpiDispatch.h>\r
#include <Pi/PiSmmCis.h>\r
\r
-#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID EFI_MM_GPI_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID EFI_MM_GPI_DISPATCH_PROTOCOL_GUID\r
///\r
/// The dispatch function's context.\r
///\r
-typedef EFI_MM_GPI_REGISTER_CONTEXT EFI_SMM_GPI_REGISTER_CONTEXT;\r
+typedef EFI_MM_GPI_REGISTER_CONTEXT EFI_SMM_GPI_REGISTER_CONTEXT;\r
\r
typedef EFI_MM_GPI_REGISTER EFI_SMM_GPI_REGISTER2;\r
\r
\r
typedef EFI_MM_GPI_DISPATCH_PROTOCOL EFI_SMM_GPI_DISPATCH2_PROTOCOL;\r
\r
-\r
-\r
-extern EFI_GUID gEfiSmmGpiDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmGpiDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
\r
typedef EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL;\r
\r
-typedef EFI_MM_IO_TRAP_DISPATCH_REGISTER EFI_SMM_IO_TRAP_DISPATCH2_REGISTER;\r
+typedef EFI_MM_IO_TRAP_DISPATCH_REGISTER EFI_SMM_IO_TRAP_DISPATCH2_REGISTER;\r
\r
typedef EFI_MM_IO_TRAP_DISPATCH_UNREGISTER EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER;\r
\r
-extern EFI_GUID gEfiSmmIoTrapDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmIoTrapDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmPciRootBridgeIo.h>\r
\r
-#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID\r
+#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID\r
\r
///\r
/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the\r
/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return\r
/// EFI_UNSUPPORTED.\r
///\r
-typedef EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
+typedef EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSmmPciRootBridgeIoProtocolGuid;\r
+extern EFI_GUID gEfiSmmPciRootBridgeIoProtocolGuid;\r
\r
#endif\r
-\r
#include <Pi/PiSmmCis.h>\r
#include <Protocol/MmPeriodicTimerDispatch.h>\r
\r
-#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// Example: A chipset supports periodic SMIs on every 64ms or 2 seconds.\r
/// The minimum period of time in 100 nanosecond units that the child gets called. The\r
/// child will be called back after a time greater than the time Period.\r
///\r
- UINT64 Period;\r
+ UINT64 Period;\r
///\r
/// The period of time interval between SMIs. Children of this interface should use this\r
/// field when registering for periodic timer intervals when a finer granularity periodic\r
/// SMI is desired.\r
///\r
- UINT64 SmiTickInterval;\r
+ UINT64 SmiTickInterval;\r
} EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT;\r
\r
///\r
///\r
typedef EFI_MM_PERIODIC_TIMER_CONTEXT EFI_SMM_PERIODIC_TIMER_CONTEXT;\r
\r
-typedef struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL;\r
+typedef struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL;\r
\r
/**\r
Register a child SMI source dispatch function for SMM periodic timer.\r
/// This protocol provides the parent dispatch service for the periodical timer SMI source generator.\r
///\r
struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL {\r
- EFI_SMM_PERIODIC_TIMER_REGISTER2 Register;\r
- EFI_SMM_PERIODIC_TIMER_UNREGISTER2 UnRegister;\r
- EFI_SMM_PERIODIC_TIMER_INTERVAL2 GetNextShorterInterval;\r
+ EFI_SMM_PERIODIC_TIMER_REGISTER2 Register;\r
+ EFI_SMM_PERIODIC_TIMER_UNREGISTER2 UnRegister;\r
+ EFI_SMM_PERIODIC_TIMER_INTERVAL2 GetNextShorterInterval;\r
};\r
\r
-extern EFI_GUID gEfiSmmPeriodicTimerDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmPeriodicTimerDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmPowerButtonDispatch.h>\r
\r
-#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// The dispatch function's context.\r
\r
typedef EFI_MM_POWER_BUTTON_UNREGISTER EFI_SMM_POWER_BUTTON_UNREGISTER2;\r
\r
-extern EFI_GUID gEfiSmmPowerButtonDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmPowerButtonDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmReadyToLock.h>\r
\r
-#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_MM_READY_TO_LOCK_PROTOCOL_GUID\r
+#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_MM_READY_TO_LOCK_PROTOCOL_GUID\r
\r
-extern EFI_GUID gEfiSmmReadyToLockProtocolGuid;\r
+extern EFI_GUID gEfiSmmReadyToLockProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/MmReportStatusCodeHandler.h>\r
\r
-#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID EFI_MM_RSC_HANDLER_PROTOCOL_GUID\r
+#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID EFI_MM_RSC_HANDLER_PROTOCOL_GUID\r
\r
typedef EFI_MM_RSC_HANDLER_CALLBACK EFI_SMM_RSC_HANDLER_CALLBACK;\r
\r
\r
typedef EFI_MM_RSC_HANDLER_PROTOCOL EFI_SMM_RSC_HANDLER_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSmmRscHandlerProtocolGuid;\r
+extern EFI_GUID gEfiSmmRscHandlerProtocolGuid;\r
\r
#endif // __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__\r
\r
#include <Protocol/MmStandbyButtonDispatch.h>\r
\r
-#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// The dispatch function's context.\r
\r
typedef EFI_MM_STANDBY_BUTTON_UNREGISTER EFI_SMM_STANDBY_BUTTON_UNREGISTER2;\r
\r
-extern EFI_GUID gEfiSmmStandbyButtonDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmStandbyButtonDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
\r
#include <Protocol/MmStatusCode.h>\r
\r
-#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID EFI_MM_STATUS_CODE_PROTOCOL_GUID\r
+#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID EFI_MM_STATUS_CODE_PROTOCOL_GUID\r
\r
-typedef EFI_MM_STATUS_CODE_PROTOCOL EFI_SMM_STATUS_CODE_PROTOCOL;\r
+typedef EFI_MM_STATUS_CODE_PROTOCOL EFI_SMM_STATUS_CODE_PROTOCOL;\r
\r
typedef EFI_MM_REPORT_STATUS_CODE EFI_SMM_REPORT_STATUS_CODE;\r
\r
-extern EFI_GUID gEfiSmmStatusCodeProtocolGuid;\r
+extern EFI_GUID gEfiSmmStatusCodeProtocolGuid;\r
\r
#endif\r
-\r
#include <Protocol/MmSwDispatch.h>\r
#include <Pi/PiSmmCis.h>\r
\r
-#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID EFI_MM_SW_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID EFI_MM_SW_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// A particular chipset may not support all possible software SMI input values.\r
/// child registration for each SwSmiInputValue.\r
///\r
typedef struct {\r
- UINTN SwSmiInputValue;\r
+ UINTN SwSmiInputValue;\r
} EFI_SMM_SW_REGISTER_CONTEXT;\r
\r
///\r
///\r
/// The 0-based index of the CPU which generated the software SMI.\r
///\r
- UINTN SwSmiCpuIndex;\r
+ UINTN SwSmiCpuIndex;\r
///\r
/// This value corresponds directly to the CommandPort parameter used in the call to Trigger().\r
///\r
- UINT8 CommandPort;\r
+ UINT8 CommandPort;\r
///\r
/// This value corresponds directly to the DataPort parameter used in the call to Trigger().\r
///\r
- UINT8 DataPort;\r
+ UINT8 DataPort;\r
} EFI_SMM_SW_CONTEXT;\r
\r
-typedef struct _EFI_SMM_SW_DISPATCH2_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL;\r
+typedef struct _EFI_SMM_SW_DISPATCH2_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL;\r
\r
/**\r
Register a child SMI source dispatch function for the specified software SMI.\r
(EFIAPI *EFI_SMM_SW_UNREGISTER2)(\r
IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This,\r
IN EFI_HANDLE DispatchHandle\r
-);\r
+ );\r
\r
///\r
/// Interface structure for the SMM Software SMI Dispatch Protocol.\r
/// interrupt in the EFI_SMM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue.\r
///\r
struct _EFI_SMM_SW_DISPATCH2_PROTOCOL {\r
- EFI_SMM_SW_REGISTER2 Register;\r
- EFI_SMM_SW_UNREGISTER2 UnRegister;\r
+ EFI_SMM_SW_REGISTER2 Register;\r
+ EFI_SMM_SW_UNREGISTER2 UnRegister;\r
///\r
/// A read-only field that describes the maximum value that can be used in the\r
/// EFI_SMM_SW_DISPATCH2_PROTOCOL.Register() service.\r
///\r
- UINTN MaximumSwiValue;\r
+ UINTN MaximumSwiValue;\r
};\r
\r
-extern EFI_GUID gEfiSmmSwDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmSwDispatch2ProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/MmSxDispatch.h>\r
\r
-#define EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID EFI_MM_SX_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID EFI_MM_SX_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// The dispatch function's context\r
///\r
typedef EFI_MM_SX_REGISTER_CONTEXT EFI_SMM_SX_REGISTER_CONTEXT;\r
\r
-typedef EFI_MM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL;\r
+typedef EFI_MM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL;\r
\r
typedef EFI_MM_SX_REGISTER EFI_SMM_SX_REGISTER2;\r
\r
typedef EFI_MM_SX_UNREGISTER EFI_SMM_SX_UNREGISTER2;\r
\r
-extern EFI_GUID gEfiSmmSxDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmSxDispatch2ProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/MmUsbDispatch.h>\r
\r
-#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID EFI_MM_USB_DISPATCH_PROTOCOL_GUID\r
+#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID EFI_MM_USB_DISPATCH_PROTOCOL_GUID\r
\r
///\r
/// USB SMI event types\r
\r
typedef EFI_MM_USB_UNREGISTER EFI_SMM_USB_UNREGISTER2;\r
\r
-extern EFI_GUID gEfiSmmUsbDispatch2ProtocolGuid;\r
+extern EFI_GUID gEfiSmmUsbDispatch2ProtocolGuid;\r
\r
#endif\r
-\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_CHIP_SELECT) (\r
+(EFIAPI *EFI_SPI_CHIP_SELECT)(\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN BOOLEAN PinValue\r
);\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_CLOCK) (\r
+(EFIAPI *EFI_SPI_CLOCK)(\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN UINT32 *ClockHz\r
);\r
///\r
/// A Unicode string specifying the SPI chip vendor.\r
///\r
- CONST CHAR16 *Vendor;\r
+ CONST CHAR16 *Vendor;\r
\r
///\r
/// A Unicode string specifying the SPI chip part number.\r
///\r
- CONST CHAR16 *PartNumber;\r
+ CONST CHAR16 *PartNumber;\r
\r
///\r
/// The minimum SPI bus clock frequency used to access this chip. This value\r
/// may be specified in the chip's datasheet. If not, use the value of zero.\r
///\r
- UINT32 MinClockHz;\r
+ UINT32 MinClockHz;\r
\r
///\r
/// The maximum SPI bus clock frequency used to access this chip. This value\r
/// is found in the chip's datasheet.\r
///\r
- UINT32 MaxClockHz;\r
+ UINT32 MaxClockHz;\r
\r
///\r
/// Specify the polarity of the chip select pin. This value can be found in\r
/// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select\r
- ///and FALSE when a zero asserts the chip select.\r
+ /// and FALSE when a zero asserts the chip select.\r
///\r
- BOOLEAN ChipSelectPolarity;\r
+ BOOLEAN ChipSelectPolarity;\r
} EFI_SPI_PART;\r
\r
///\r
///\r
/// A Unicode string describing the SPI bus\r
///\r
- CONST CHAR16 *FriendlyName;\r
+ CONST CHAR16 *FriendlyName;\r
\r
///\r
/// Address of the first EFI_SPI_PERIPHERAL data structure connected to this\r
/// bus. Specify NULL if there are no SPI peripherals connected to this bus.\r
///\r
- CONST EFI_SPI_PERIPHERAL *Peripherallist;\r
+ CONST EFI_SPI_PERIPHERAL *Peripherallist;\r
\r
///\r
/// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely\r
/// describes the SPI controller.\r
///\r
- CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;\r
+ CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;\r
\r
///\r
/// Address of the routine which controls the clock used by the SPI bus for\r
/// this SPI peripheral. The SPI host co ntroller's clock routine is called\r
/// when this value is set to NULL.\r
///\r
- EFI_SPI_CLOCK Clock;\r
+ EFI_SPI_CLOCK Clock;\r
\r
///\r
/// Address of a data structure containing the additional values which\r
/// host's SPI controller driver. When Clock is not NULL, the declaration for\r
/// this data structure is provided by the board layer.\r
///\r
- VOID *ClockParameter;\r
+ VOID *ClockParameter;\r
} EFI_SPI_BUS;\r
\r
///\r
/// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if\r
/// the current data structure is the last one on the SPI bus.\r
///\r
- CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;\r
\r
///\r
/// A unicode string describing the function of the SPI part.\r
///\r
- CONST CHAR16 *FriendlyName;\r
+ CONST CHAR16 *FriendlyName;\r
\r
///\r
/// Address of a GUID provided by the vendor of the SPI peripheral driver.\r
/// This reduces the comparison logic in the SPI peripheral driver's\r
/// Supported routine.\r
///\r
- CONST GUID *SpiPeripheralDriverGuid;\r
+ CONST GUID *SpiPeripheralDriverGuid;\r
\r
///\r
/// The address of an EFI_SPI_PART data structure which describes this chip.\r
///\r
- CONST EFI_SPI_PART *SpiPart;\r
+ CONST EFI_SPI_PART *SpiPart;\r
\r
///\r
/// The maximum clock frequency is specified in the EFI_SPI_P ART. When this\r
/// this value is non-zero and less than the value in the EFI_SPI_PART then\r
/// this value is used for the maximum clock frequency for the SPI part.\r
///\r
- UINT32 MaxClockHz;\r
+ UINT32 MaxClockHz;\r
\r
///\r
/// Specify the idle value of the clock as found in the datasheet.\r
/// Use zero (0) if the clock'S idle value is low or one (1) if the the\r
/// clock's idle value is high.\r
///\r
- BOOLEAN ClockPolarity;\r
+ BOOLEAN ClockPolarity;\r
\r
///\r
/// Specify the clock delay after chip select. Specify zero (0) to delay an\r
/// entire clock cycle or one (1) to delay only half a clock cycle.\r
///\r
- BOOLEAN ClockPhase;\r
+ BOOLEAN ClockPhase;\r
\r
///\r
/// SPI peripheral attributes, select zero or more of:\r
/// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to\r
/// support a 4-bit data bus\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Address of a vendor specific data structure containing additional board\r
/// configuration details related to the SPI chip. The SPI peripheral layer\r
/// uses this data structure when configuring the chip.\r
///\r
- CONST VOID *ConfigurationData;\r
+ CONST VOID *ConfigurationData;\r
\r
///\r
/// The address of an EFI_SPI_BUS data structure which describes the SPI bus\r
/// to which this chip is connected.\r
///\r
- CONST EFI_SPI_BUS *SpiBus;\r
+ CONST EFI_SPI_BUS *SpiBus;\r
\r
///\r
/// Address of the routine which controls the chip select pin for this SPI\r
/// peripheral. Call the SPI host controller's chip select routine when this\r
/// value is set to NULL.\r
///\r
- EFI_SPI_CHIP_SELECT ChipSelect;\r
+ EFI_SPI_CHIP_SELECT ChipSelect;\r
\r
///\r
/// Address of a data structure containing the additional values which\r
/// control. When Chipselect is not NULL, the declaration for this data\r
/// structure is provided by the board layer.\r
///\r
- VOID *ChipSelectParameter;\r
+ VOID *ChipSelectParameter;\r
};\r
\r
///\r
///\r
/// The number of SPI busses on the board.\r
///\r
- UINT32 BusCount;\r
+ UINT32 BusCount;\r
\r
///\r
/// The address of an array of EFI_SPI_BUS data structure addresses.\r
///\r
- CONST EFI_SPI_BUS *CONST *CONST Buslist;\r
+ CONST EFI_SPI_BUS *CONST *CONST Buslist;\r
} EFI_SPI_CONFIGURATION_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSpiConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiSpiConfigurationProtocolGuid;\r
\r
#endif // __SPI_CONFIGURATION_PROTOCOL_H__\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN BOOLEAN PinValue\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral,\r
IN UINT32 *ClockHz\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (\r
+(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION)(\r
IN CONST EFI_SPI_HC_PROTOCOL *This,\r
IN EFI_SPI_BUS_TRANSACTION *BusTransaction\r
);\r
/// sending) operation.The SPI host controller must support a 1 - bit bus\r
/// width.\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Mask of frame sizes which the SPI host controller supports. Frame size of\r
/// N-bits is supported when bit N-1 is set. The host controller must support\r
/// a frame size of 8-bits.\r
///\r
- UINT32 FrameSizeSupportMask;\r
+ UINT32 FrameSizeSupportMask;\r
\r
///\r
/// Maximum transfer size in bytes: 1 - Oxffffffff\r
///\r
- UINT32 MaximumTransferBytes;\r
+ UINT32 MaximumTransferBytes;\r
\r
///\r
/// Assert or deassert the SPI chip select.\r
///\r
- EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
+ EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;\r
\r
///\r
/// Set up the clock generator to produce the correct clock frequency, phase\r
/// and polarity for a SPI chip.\r
///\r
- EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
+ EFI_SPI_HC_PROTOCOL_CLOCK Clock;\r
\r
///\r
/// Perform the SPI transaction on the SPI peripheral using the SPI host\r
/// controller.\r
///\r
- EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
+ EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;\r
};\r
\r
-extern EFI_GUID gEfiSpiHcProtocolGuid;\r
+extern EFI_GUID gEfiSpiHcProtocolGuid;\r
\r
#endif // __SPI_HC_PROTOCOL_H__\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) (\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION)(\r
IN CONST EFI_SPI_IO_PROTOCOL *This,\r
IN EFI_SPI_TRANSACTION_TYPE TransactionType,\r
IN BOOLEAN DebugTransaction,\r
\r
**/\r
typedef EFI_STATUS\r
-(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) (\r
+(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL)(\r
IN CONST EFI_SPI_IO_PROTOCOL *This,\r
IN CONST EFI_SPI_PERIPHERAL *SpiPeripheral\r
);\r
///\r
/// Pointer to the SPI peripheral being manipulated.\r
///\r
- CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
\r
///\r
/// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE\r
/// values.\r
///\r
- EFI_SPI_TRANSACTION_TYPE TransactionType;\r
+ EFI_SPI_TRANSACTION_TYPE TransactionType;\r
\r
///\r
/// TRUE if the transaction is being debugged. Debugging may be turned on for\r
/// messages. All other transactions with this value set to FALSE will not\r
/// display any debugging messages.\r
///\r
- BOOLEAN DebugTransaction;\r
+ BOOLEAN DebugTransaction;\r
\r
///\r
/// SPI bus width in bits: 1, 2, 4\r
///\r
- UINT32 BusWidth;\r
+ UINT32 BusWidth;\r
\r
///\r
/// Frame size in bits, range: 1 - 32\r
///\r
- UINT32 FrameSize;\r
+ UINT32 FrameSize;\r
\r
///\r
/// Length of the write buffer in bytes\r
///\r
- UINT32 WriteBytes;\r
+ UINT32 WriteBytes;\r
\r
///\r
/// Buffer containing data to send to the SPI peripheral\r
/// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame\r
/// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
///\r
- UINT8 *WriteBuffer;\r
+ UINT8 *WriteBuffer;\r
\r
///\r
/// Length of the read buffer in bytes\r
///\r
- UINT32 ReadBytes;\r
+ UINT32 ReadBytes;\r
\r
///\r
/// Buffer to receive the data from the SPI peripheral\r
/// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame\r
/// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame\r
///\r
- UINT8 *ReadBuffer;\r
+ UINT8 *ReadBuffer;\r
} EFI_SPI_BUS_TRANSACTION;\r
\r
///\r
/// Address of an EFI_SPI_PERIPHERAL data structure associated with this\r
/// protocol instance.\r
///\r
- CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
\r
///\r
/// Address of the original EFI_SPI_PERIPHERAL data structure associated with\r
/// this protocol instance.\r
///\r
- CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *OriginalSpiPeripheral;\r
\r
///\r
/// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits\r
/// 8-bit frame sizes by the SPI bus layer if the frame size is not supported\r
/// by the SPI host controller.\r
///\r
- UINT32 FrameSizeSupportMask;\r
+ UINT32 FrameSizeSupportMask;\r
\r
///\r
/// Maximum transfer size in bytes: 1 - Oxffffffff\r
///\r
- UINT32 MaximumTransferBytes;\r
+ UINT32 MaximumTransferBytes;\r
\r
///\r
/// Transaction attributes: One or more from:\r
/// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS\r
/// - Transfer size includes the 3 address bytes\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
\r
///\r
/// Pointer to legacy SPI controller protocol\r
///\r
- CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;\r
+ CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *LegacySpiProtocol;\r
\r
///\r
/// Initiate a SPI transaction between the host and a SPI peripheral.\r
///\r
- EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;\r
+ EFI_SPI_IO_PROTOCOL_TRANSACTION Transaction;\r
\r
///\r
/// Update the SPI peripheral associated with this SPI 10 instance.\r
///\r
- EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;\r
+ EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;\r
};\r
\r
#endif // __SPI_IO_PROTOCOL_H__\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
OUT UINT8 *Buffer\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
IN UINT32 FlashAddress,\r
IN UINT32 LengthInBytes,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
IN UINT32 LengthInBytes,\r
OUT UINT8 *FlashStatus\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
IN UINT32 LengthInBytes,\r
IN UINT8 *FlashStatus\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
IN UINT32 FlashAddress,\r
IN UINT32 LengthInBytes,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE) (\r
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE)(\r
IN CONST EFI_SPI_NOR_FLASH_PROTOCOL *This,\r
IN UINT32 FlashAddress,\r
IN UINT32 BlockCount\r
///\r
/// Pointer to an EFI_SPI_PERIPHERAL data structure\r
///\r
- CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
+ CONST EFI_SPI_PERIPHERAL *SpiPeripheral;\r
\r
///\r
/// Flash size in bytes\r
///\r
- UINT32 FlashSize;\r
+ UINT32 FlashSize;\r
\r
///\r
/// Manufacture and Device ID\r
///\r
- UINT8 Deviceid[3];\r
+ UINT8 Deviceid[3];\r
\r
///\r
/// Erase block size in bytes\r
///\r
- UINT32 EraseBlockBytes;\r
+ UINT32 EraseBlockBytes;\r
\r
///\r
/// Read the 3 byte manufacture and device ID from the SPI flash.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashid;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashid;\r
\r
///\r
/// Read data from the SPI flash.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA ReadData;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA ReadData;\r
\r
///\r
/// Low frequency read data from the SPI flash.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA LfReadData;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA LfReadData;\r
\r
///\r
/// Read the flash status register.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS ReadStatus;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS ReadStatus;\r
\r
///\r
/// Write the flash status register.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus;\r
\r
///\r
/// Write data to the SPI flash.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA WriteData;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA WriteData;\r
\r
///\r
/// Efficiently erases one or more 4KiB regions in the SPI flash.\r
///\r
- EFI_SPI_NOR_FLASH_PROTOCOL_ERASE Erase;\r
+ EFI_SPI_NOR_FLASH_PROTOCOL_ERASE Erase;\r
};\r
\r
-extern EFI_GUID gEfiSpiNorFlashProtocolGuid;\r
+extern EFI_GUID gEfiSpiNorFlashProtocolGuid;\r
\r
#endif // __SPI_NOR_FLASH_PROTOCOL_H__\r
{ 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }}\r
\r
typedef\r
-struct _EFI_SPI_CONFIGURATION_PROTOCOL\r
+ struct _EFI_SPI_CONFIGURATION_PROTOCOL\r
EFI_SPI_SMM_CONFIGURATION_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSpiSmmConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiSpiSmmConfigurationProtocolGuid;\r
\r
#endif // __SPI_SMM_CONFIGURATION_H__\r
{ 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }}\r
\r
typedef\r
-struct _EFI_SPI_HC_PROTOCOL\r
+ struct _EFI_SPI_HC_PROTOCOL\r
EFI_SPI_SMM_HC_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSpiSmmHcProtocolGuid;\r
+extern EFI_GUID gEfiSpiSmmHcProtocolGuid;\r
\r
#endif // __SPI_SMM_HC_H__\r
{ 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a } }\r
\r
typedef\r
-struct _EFI_SPI_NOR_FLASH_PROTOCOL\r
+ struct _EFI_SPI_NOR_FLASH_PROTOCOL\r
EFI_SPI_SMM_NOR_FLASH_PROTOCOL;\r
\r
-extern EFI_GUID gEfiSpiSmmNorFlashProtocolGuid;\r
+extern EFI_GUID gEfiSpiSmmNorFlashProtocolGuid;\r
\r
#endif // __SPI_SMM_NOR_FLASH_PROTOCOL_H__\r
/// This protocol must be produced by a runtime DXE driver.\r
///\r
typedef struct _EFI_STATUS_CODE_PROTOCOL {\r
- EFI_REPORT_STATUS_CODE ReportStatusCode;\r
+ EFI_REPORT_STATUS_CODE ReportStatusCode;\r
} EFI_STATUS_CODE_PROTOCOL;\r
\r
-extern EFI_GUID gEfiStatusCodeRuntimeProtocolGuid;\r
+extern EFI_GUID gEfiStatusCodeRuntimeProtocolGuid;\r
\r
#endif\r
0xC88B0B6D, 0x0DFC, 0x49A7, {0x9C, 0xB4, 0x49, 0x07, 0x4B, 0x4C, 0x3A, 0x78 } \\r
}\r
\r
-typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL EFI_STORAGE_SECURITY_COMMAND_PROTOCOL;\r
+typedef struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL EFI_STORAGE_SECURITY_COMMAND_PROTOCOL;\r
\r
/**\r
Send a security protocol command to a device that receives data and/or the result\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA) (\r
+(EFIAPI *EFI_STORAGE_SECURITY_SEND_DATA)(\r
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,\r
IN UINT32 MediaId,\r
IN UINT64 Timeout,\r
IN UINT16 SecurityProtocolSpecificData,\r
IN UINTN PayloadBufferSize,\r
IN VOID *PayloadBuffer\r
-);\r
+ );\r
\r
///\r
/// The EFI_STORAGE_SECURITY_COMMAND_PROTOCOL is used to send security protocol\r
/// or their successors.\r
///\r
struct _EFI_STORAGE_SECURITY_COMMAND_PROTOCOL {\r
- EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData;\r
- EFI_STORAGE_SECURITY_SEND_DATA SendData;\r
+ EFI_STORAGE_SECURITY_RECEIVE_DATA ReceiveData;\r
+ EFI_STORAGE_SECURITY_SEND_DATA SendData;\r
};\r
\r
-extern EFI_GUID gEfiStorageSecurityCommandProtocolGuid;\r
+extern EFI_GUID gEfiStorageSecurityCommandProtocolGuid;\r
\r
#endif\r
{ 0x215fdd18, 0xbd50, 0x4feb, { 0x89, 0xb, 0x58, 0xca, 0xb, 0x47, 0x39, 0xe9 } }\r
\r
typedef union {\r
- ACPI_SMALL_RESOURCE_HEADER *SmallHeader;\r
- ACPI_LARGE_RESOURCE_HEADER *LargeHeader;\r
+ ACPI_SMALL_RESOURCE_HEADER *SmallHeader;\r
+ ACPI_LARGE_RESOURCE_HEADER *LargeHeader;\r
} ACPI_RESOURCE_HEADER_PTR;\r
\r
typedef struct {\r
- UINT8 Register; ///< Register number.\r
- UINT8 AndMask; ///< Bitwise AND mask.\r
- UINT8 OrMask; ///< Bitwise OR mask.\r
+ UINT8 Register; ///< Register number.\r
+ UINT8 AndMask; ///< Bitwise AND mask.\r
+ UINT8 OrMask; ///< Bitwise OR mask.\r
} EFI_SIO_REGISTER_MODIFY;\r
\r
-typedef struct _EFI_SIO_PROTOCOL EFI_SIO_PROTOCOL;\r
+typedef struct _EFI_SIO_PROTOCOL EFI_SIO_PROTOCOL;\r
\r
/**\r
Provides a low level access to the registers for the Super I/O.\r
IN BOOLEAN ExitCfgMode,\r
IN UINT8 Register,\r
IN OUT UINT8 *Value\r
-);\r
+ );\r
\r
/**\r
Provides an interface to get a list of the current resources consumed by the device in the ACPI\r
(EFIAPI *EFI_SIO_GET_RESOURCES)(\r
IN CONST EFI_SIO_PROTOCOL *This,\r
OUT ACPI_RESOURCE_HEADER_PTR *ResourceList\r
-);\r
+ );\r
\r
/**\r
Sets the resources for the device.\r
(EFIAPI *EFI_SIO_SET_RESOURCES)(\r
IN CONST EFI_SIO_PROTOCOL *This,\r
IN ACPI_RESOURCE_HEADER_PTR ResourceList\r
-);\r
+ );\r
\r
/**\r
Provides a collection of resource descriptor lists. Each resource descriptor list in the collection\r
(EFIAPI *EFI_SIO_POSSIBLE_RESOURCES)(\r
IN CONST EFI_SIO_PROTOCOL *This,\r
OUT ACPI_RESOURCE_HEADER_PTR *ResourceCollection\r
-);\r
+ );\r
\r
/**\r
Provides an interface for a table based programming of the Super I/O registers.\r
IN CONST EFI_SIO_PROTOCOL *This,\r
IN CONST EFI_SIO_REGISTER_MODIFY *Command,\r
IN UINTN NumberOfCommands\r
-);\r
+ );\r
\r
struct _EFI_SIO_PROTOCOL {\r
EFI_SIO_REGISTER_ACCESS RegisterAccess;\r
EFI_SIO_GET_RESOURCES GetResources;\r
EFI_SIO_SET_RESOURCES SetResources;\r
EFI_SIO_POSSIBLE_RESOURCES PossibleResources;\r
- EFI_SIO_MODIFY Modify;\r
+ EFI_SIO_MODIFY Modify;\r
};\r
\r
-extern EFI_GUID gEfiSioProtocolGuid;\r
+extern EFI_GUID gEfiSioProtocolGuid;\r
\r
#endif // __EFI_SUPER_IO_PROTOCOL_H__\r
0xb91978df, 0x9fc1, 0x427d, { 0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27 } \\r
}\r
\r
-typedef struct _EFI_SIO_CONTROL_PROTOCOL EFI_SIO_CONTROL_PROTOCOL;\r
-typedef struct _EFI_SIO_CONTROL_PROTOCOL *PEFI_SIO_CONTROL_PROTOCOL;\r
+typedef struct _EFI_SIO_CONTROL_PROTOCOL EFI_SIO_CONTROL_PROTOCOL;\r
+typedef struct _EFI_SIO_CONTROL_PROTOCOL *PEFI_SIO_CONTROL_PROTOCOL;\r
\r
/**\r
Enable an ISA-style device.\r
///\r
/// The version of this protocol.\r
///\r
- UINT32 Version;\r
+ UINT32 Version;\r
///\r
/// Enable a device.\r
///\r
- EFI_SIO_CONTROL_ENABLE EnableDevice;\r
+ EFI_SIO_CONTROL_ENABLE EnableDevice;\r
///\r
/// Disable a device.\r
///\r
- EFI_SIO_CONTROL_DISABLE DisableDevice;\r
+ EFI_SIO_CONTROL_DISABLE DisableDevice;\r
};\r
\r
-extern EFI_GUID gEfiSioControlProtocolGuid;\r
+extern EFI_GUID gEfiSioControlProtocolGuid;\r
\r
#endif // __EFI_SUPER_IO_CONTROL_PROTOCOL_H__\r
// If TRUE, indicates GTK is just refreshed after a successful call to\r
// EFI_SUPPLICANT_PROTOCOL.BuildResponsePacket().\r
//\r
- BOOLEAN GTKRefresh;\r
+ BOOLEAN GTKRefresh;\r
} EFI_SUPPLICANT_KEY_REFRESH;\r
\r
-#define EFI_MAX_KEY_LEN 64\r
+#define EFI_MAX_KEY_LEN 64\r
\r
///\r
/// EFI_SUPPLICANT_KEY\r
//\r
// The key value.\r
//\r
- UINT8 Key[EFI_MAX_KEY_LEN];\r
+ UINT8 Key[EFI_MAX_KEY_LEN];\r
//\r
// Length in bytes of the Key. Should be up to EFI_MAX_KEY_LEN.\r
//\r
- UINT8 KeyLen;\r
+ UINT8 KeyLen;\r
//\r
// The key identifier.\r
//\r
- UINT8 KeyId;\r
+ UINT8 KeyId;\r
//\r
// Defines whether this key is a group key, pairwise key, PeerKey, or\r
// Integrity Group.\r
//\r
- EFI_SUPPLICANT_KEY_TYPE KeyType;\r
+ EFI_SUPPLICANT_KEY_TYPE KeyType;\r
//\r
// The value is set according to the KeyType.\r
//\r
- EFI_80211_MAC_ADDRESS Addr;\r
+ EFI_80211_MAC_ADDRESS Addr;\r
//\r
// The Receive Sequence Count value.\r
//\r
- UINT8 Rsc[8];\r
+ UINT8 Rsc[8];\r
//\r
// Length in bytes of the Rsc. Should be up to 8.\r
//\r
- UINT8 RscLen;\r
+ UINT8 RscLen;\r
//\r
// Indicates whether the key is configured by the Authenticator or\r
// Supplicant. The value true indicates Authenticator.\r
//\r
- BOOLEAN IsAuthenticator;\r
+ BOOLEAN IsAuthenticator;\r
//\r
// The cipher suite required for this association.\r
//\r
- EFI_80211_SUITE_SELECTOR CipherSuite;\r
+ EFI_80211_SUITE_SELECTOR CipherSuite;\r
//\r
// Indicates the direction for which the keys are to be installed.\r
//\r
- EFI_SUPPLICANT_KEY_DIRECTION Direction;\r
+ EFI_SUPPLICANT_KEY_DIRECTION Direction;\r
} EFI_SUPPLICANT_KEY;\r
\r
///\r
//\r
// Indicates the number of GTKs that are contained in GTKList.\r
//\r
- UINT8 GTKCount;\r
+ UINT8 GTKCount;\r
//\r
// A variable-length array of GTKs of type EFI_SUPPLICANT_KEY. The number of\r
// entries is specified by GTKCount.\r
//\r
- EFI_SUPPLICANT_KEY GTKList[1];\r
+ EFI_SUPPLICANT_KEY GTKList[1];\r
} EFI_SUPPLICANT_GTK_LIST;\r
\r
///\r
//\r
// Length of data buffer in the fragment.\r
//\r
- UINT32 FragmentLength;\r
+ UINT32 FragmentLength;\r
//\r
// Pointer to the data buffer in the fragment.\r
//\r
- VOID *FragmentBuffer;\r
+ VOID *FragmentBuffer;\r
} EFI_SUPPLICANT_FRAGMENT_DATA;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SUPPLICANT_BUILD_RESPONSE_PACKET) (\r
+(EFIAPI *EFI_SUPPLICANT_BUILD_RESPONSE_PACKET)(\r
IN EFI_SUPPLICANT_PROTOCOL *This,\r
IN UINT8 *RequestBuffer OPTIONAL,\r
IN UINTN RequestBufferSize OPTIONAL,\r
- OUT UINT8 *Buffer,\r
+ OUT UINT8 *Buffer,\r
IN OUT UINTN *BufferSize\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SUPPLICANT_PROCESS_PACKET) (\r
+(EFIAPI *EFI_SUPPLICANT_PROCESS_PACKET)(\r
IN EFI_SUPPLICANT_PROTOCOL *This,\r
IN OUT EFI_SUPPLICANT_FRAGMENT_DATA **FragmentTable,\r
IN UINT32 *FragmentCount,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SUPPLICANT_SET_DATA) (\r
+(EFIAPI *EFI_SUPPLICANT_SET_DATA)(\r
IN EFI_SUPPLICANT_PROTOCOL *This,\r
IN EFI_SUPPLICANT_DATA_TYPE DataType,\r
IN VOID *Data,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_SUPPLICANT_GET_DATA) (\r
+(EFIAPI *EFI_SUPPLICANT_GET_DATA)(\r
IN EFI_SUPPLICANT_PROTOCOL *This,\r
IN EFI_SUPPLICANT_DATA_TYPE DataType,\r
- OUT UINT8 *Data OPTIONAL,\r
+ OUT UINT8 *Data OPTIONAL,\r
IN OUT UINTN *DataSize\r
);\r
\r
EFI_SUPPLICANT_GET_DATA GetData;\r
};\r
\r
-extern EFI_GUID gEfiSupplicantServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiSupplicantProtocolGuid;\r
+extern EFI_GUID gEfiSupplicantServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiSupplicantProtocolGuid;\r
\r
#endif\r
typedef struct _EFI_TAPE_IO_PROTOCOL EFI_TAPE_IO_PROTOCOL;\r
\r
typedef struct _EFI_TAPE_HEADER {\r
- UINT64 Signature;\r
- UINT32 Revision;\r
- UINT32 BootDescSize;\r
- UINT32 BootDescCRC;\r
- EFI_GUID TapeGUID;\r
- EFI_GUID TapeType;\r
- EFI_GUID TapeUnique;\r
- UINT32 BLLocation;\r
- UINT32 BLBlocksize;\r
- UINT32 BLFilesize;\r
- CHAR8 OSVersion[40];\r
- CHAR8 AppVersion[40];\r
- CHAR8 CreationDate[10];\r
- CHAR8 CreationTime[10];\r
- CHAR8 SystemName[256]; // UTF-8\r
- CHAR8 TapeTitle[120]; // UTF-8\r
- CHAR8 pad[468]; // pad to 1024\r
+ UINT64 Signature;\r
+ UINT32 Revision;\r
+ UINT32 BootDescSize;\r
+ UINT32 BootDescCRC;\r
+ EFI_GUID TapeGUID;\r
+ EFI_GUID TapeType;\r
+ EFI_GUID TapeUnique;\r
+ UINT32 BLLocation;\r
+ UINT32 BLBlocksize;\r
+ UINT32 BLFilesize;\r
+ CHAR8 OSVersion[40];\r
+ CHAR8 AppVersion[40];\r
+ CHAR8 CreationDate[10];\r
+ CHAR8 CreationTime[10];\r
+ CHAR8 SystemName[256]; // UTF-8\r
+ CHAR8 TapeTitle[120]; // UTF-8\r
+ CHAR8 pad[468]; // pad to 1024\r
} EFI_TAPE_HEADER;\r
\r
/**\r
IN VOID *Buffer\r
);\r
\r
-\r
/**\r
Rewinds the tape.\r
\r
IN EFI_TAPE_IO_PROTOCOL *This\r
);\r
\r
-\r
/**\r
Positions the tape.\r
\r
IN UINTN Type\r
);\r
\r
-\r
/**\r
Writes filemarks to the media.\r
\r
IN UINTN Count\r
);\r
\r
-\r
/**\r
Resets the tape device.\r
\r
/// to load the bootloader image from tape.\r
///\r
struct _EFI_TAPE_IO_PROTOCOL {\r
- EFI_TAPE_READ TapeRead;\r
- EFI_TAPE_WRITE TapeWrite;\r
- EFI_TAPE_REWIND TapeRewind;\r
- EFI_TAPE_SPACE TapeSpace;\r
- EFI_TAPE_WRITEFM TapeWriteFM;\r
- EFI_TAPE_RESET TapeReset;\r
+ EFI_TAPE_READ TapeRead;\r
+ EFI_TAPE_WRITE TapeWrite;\r
+ EFI_TAPE_REWIND TapeRewind;\r
+ EFI_TAPE_SPACE TapeSpace;\r
+ EFI_TAPE_WRITEFM TapeWriteFM;\r
+ EFI_TAPE_RESET TapeReset;\r
};\r
\r
-extern EFI_GUID gEfiTapeIoProtocolGuid;\r
+extern EFI_GUID gEfiTapeIoProtocolGuid;\r
\r
#endif\r
typedef struct tdEFI_TCG2_PROTOCOL EFI_TCG2_PROTOCOL;\r
\r
typedef struct tdEFI_TCG2_VERSION {\r
- UINT8 Major;\r
- UINT8 Minor;\r
+ UINT8 Major;\r
+ UINT8 Minor;\r
} EFI_TCG2_VERSION;\r
\r
typedef UINT32 EFI_TCG2_EVENT_LOG_BITMAP;\r
typedef UINT32 EFI_TCG2_EVENT_LOG_FORMAT;\r
typedef UINT32 EFI_TCG2_EVENT_ALGORITHM_BITMAP;\r
\r
-#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 0x00000001\r
-#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002\r
+#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 0x00000001\r
+#define EFI_TCG2_EVENT_LOG_FORMAT_TCG_2 0x00000002\r
\r
typedef struct tdEFI_TCG2_BOOT_SERVICE_CAPABILITY {\r
//\r
// Allocated size of the structure\r
//\r
- UINT8 Size;\r
+ UINT8 Size;\r
//\r
// Version of the EFI_TCG2_BOOT_SERVICE_CAPABILITY structure itself.\r
// For this version of the protocol, the Major version shall be set to 1\r
// and the Minor version shall be set to 1.\r
//\r
- EFI_TCG2_VERSION StructureVersion;\r
+ EFI_TCG2_VERSION StructureVersion;\r
//\r
// Version of the EFI TCG2 protocol.\r
// For this version of the protocol, the Major version shall be set to 1\r
// and the Minor version shall be set to 1.\r
//\r
- EFI_TCG2_VERSION ProtocolVersion;\r
+ EFI_TCG2_VERSION ProtocolVersion;\r
//\r
// Supported hash algorithms (this bitmap is determined by the supported PCR\r
// banks in the TPM and the hashing algorithms supported by the firmware)\r
//\r
- EFI_TCG2_EVENT_ALGORITHM_BITMAP HashAlgorithmBitmap;\r
+ EFI_TCG2_EVENT_ALGORITHM_BITMAP HashAlgorithmBitmap;\r
//\r
// Bitmap of supported event log formats\r
//\r
- EFI_TCG2_EVENT_LOG_BITMAP SupportedEventLogs;\r
+ EFI_TCG2_EVENT_LOG_BITMAP SupportedEventLogs;\r
//\r
// False = TPM not present\r
//\r
- BOOLEAN TPMPresentFlag;\r
+ BOOLEAN TPMPresentFlag;\r
//\r
// Max size (in bytes) of a command that can be sent to the TPM\r
//\r
- UINT16 MaxCommandSize;\r
+ UINT16 MaxCommandSize;\r
//\r
// Max size (in bytes) of a response that can be provided by the TPM\r
//\r
- UINT16 MaxResponseSize;\r
+ UINT16 MaxResponseSize;\r
//\r
// 4-byte Vendor ID\r
// (see TCG Vendor ID registry, Section "TPM Capabilities Vendor ID")\r
//\r
- UINT32 ManufacturerID;\r
+ UINT32 ManufacturerID;\r
//\r
// Maximum number of PCR banks (hashing algorithms) supported.\r
// No granularity is provided to support a specific set of algorithms.\r
// Minimum value is 1.\r
//\r
- UINT32 NumberOfPCRBanks;\r
+ UINT32 NumberOfPCRBanks;\r
//\r
// A bitmap of currently active PCR banks (hashing algorithms).\r
// This is a subset of the supported hashing algorithms reported in HashAlgorithmBitMap.\r
// NumberOfPcrBanks defines the number of bits that are set.\r
//\r
- EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrBanks;\r
+ EFI_TCG2_EVENT_ALGORITHM_BITMAP ActivePcrBanks;\r
} EFI_TCG2_BOOT_SERVICE_CAPABILITY;\r
\r
-#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001\r
-#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002\r
-#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004\r
-#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008\r
-#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010\r
+#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001\r
+#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002\r
+#define EFI_TCG2_BOOT_HASH_ALG_SHA384 0x00000004\r
+#define EFI_TCG2_BOOT_HASH_ALG_SHA512 0x00000008\r
+#define EFI_TCG2_BOOT_HASH_ALG_SM3_256 0x00000010\r
\r
//\r
// This bit is shall be set when an event shall be extended but not logged.\r
//\r
// This bit shall be set when the intent is to measure a PE/COFF image.\r
//\r
-#define PE_COFF_IMAGE 0x0000000000000010\r
+#define PE_COFF_IMAGE 0x0000000000000010\r
\r
#define MAX_PCR_INDEX 23\r
\r
//\r
// Size of the event header itself (sizeof(EFI_TCG2_EVENT_HEADER)).\r
//\r
- UINT32 HeaderSize;\r
+ UINT32 HeaderSize;\r
//\r
// Header version. For this version of this specification, the value shall be 1.\r
//\r
- UINT16 HeaderVersion;\r
+ UINT16 HeaderVersion;\r
//\r
// Index of the PCR that shall be extended (0 - 23).\r
//\r
- TCG_PCRINDEX PCRIndex;\r
+ TCG_PCRINDEX PCRIndex;\r
//\r
// Type of the event that shall be extended (and optionally logged).\r
//\r
- TCG_EVENTTYPE EventType;\r
+ TCG_EVENTTYPE EventType;\r
} EFI_TCG2_EVENT_HEADER;\r
\r
typedef struct tdEFI_TCG2_EVENT {\r
//\r
// Total size of the event including the Size component, the header and the Event data.\r
//\r
- UINT32 Size;\r
- EFI_TCG2_EVENT_HEADER Header;\r
- UINT8 Event[1];\r
+ UINT32 Size;\r
+ EFI_TCG2_EVENT_HEADER Header;\r
+ UINT8 Event[1];\r
} EFI_TCG2_EVENT;\r
\r
#pragma pack()\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_GET_CAPABILITY) (\r
+(EFIAPI *EFI_TCG2_GET_CAPABILITY)(\r
IN EFI_TCG2_PROTOCOL *This,\r
IN OUT EFI_TCG2_BOOT_SERVICE_CAPABILITY *ProtocolCapability\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_GET_EVENT_LOG) (\r
+(EFIAPI *EFI_TCG2_GET_EVENT_LOG)(\r
IN EFI_TCG2_PROTOCOL *This,\r
IN EFI_TCG2_EVENT_LOG_FORMAT EventLogFormat,\r
OUT EFI_PHYSICAL_ADDRESS *EventLogLocation,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_TCG2_HASH_LOG_EXTEND_EVENT) (\r
+(EFIAPI *EFI_TCG2_HASH_LOG_EXTEND_EVENT)(\r
IN EFI_TCG2_PROTOCOL *This,\r
IN UINT64 Flags,\r
IN EFI_PHYSICAL_ADDRESS DataToHash,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_SUBMIT_COMMAND) (\r
+(EFIAPI *EFI_TCG2_SUBMIT_COMMAND)(\r
IN EFI_TCG2_PROTOCOL *This,\r
IN UINT32 InputParameterBlockSize,\r
IN UINT8 *InputParameterBlock,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_GET_ACTIVE_PCR_BANKS) (\r
+(EFIAPI *EFI_TCG2_GET_ACTIVE_PCR_BANKS)(\r
IN EFI_TCG2_PROTOCOL *This,\r
OUT UINT32 *ActivePcrBanks\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_SET_ACTIVE_PCR_BANKS) (\r
+(EFIAPI *EFI_TCG2_SET_ACTIVE_PCR_BANKS)(\r
IN EFI_TCG2_PROTOCOL *This,\r
IN UINT32 ActivePcrBanks\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS) (\r
+(EFIAPI *EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS)(\r
IN EFI_TCG2_PROTOCOL *This,\r
OUT UINT32 *OperationPresent,\r
OUT UINT32 *Response\r
);\r
\r
struct tdEFI_TCG2_PROTOCOL {\r
- EFI_TCG2_GET_CAPABILITY GetCapability;\r
- EFI_TCG2_GET_EVENT_LOG GetEventLog;\r
- EFI_TCG2_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
- EFI_TCG2_SUBMIT_COMMAND SubmitCommand;\r
- EFI_TCG2_GET_ACTIVE_PCR_BANKS GetActivePcrBanks;\r
- EFI_TCG2_SET_ACTIVE_PCR_BANKS SetActivePcrBanks;\r
- EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS GetResultOfSetActivePcrBanks;\r
+ EFI_TCG2_GET_CAPABILITY GetCapability;\r
+ EFI_TCG2_GET_EVENT_LOG GetEventLog;\r
+ EFI_TCG2_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
+ EFI_TCG2_SUBMIT_COMMAND SubmitCommand;\r
+ EFI_TCG2_GET_ACTIVE_PCR_BANKS GetActivePcrBanks;\r
+ EFI_TCG2_SET_ACTIVE_PCR_BANKS SetActivePcrBanks;\r
+ EFI_TCG2_GET_RESULT_OF_SET_ACTIVE_PCR_BANKS GetResultOfSetActivePcrBanks;\r
};\r
\r
-extern EFI_GUID gEfiTcg2ProtocolGuid;\r
+extern EFI_GUID gEfiTcg2ProtocolGuid;\r
\r
//\r
// Log entries after Get Event Log service\r
#define EFI_TCG2_FINAL_EVENTS_TABLE_GUID \\r
{0x1e2ed096, 0x30e2, 0x4254, { 0xbd, 0x89, 0x86, 0x3b, 0xbe, 0xf8, 0x23, 0x25 }}\r
\r
-extern EFI_GUID gEfiTcg2FinalEventsTableGuid;\r
+extern EFI_GUID gEfiTcg2FinalEventsTableGuid;\r
\r
typedef struct tdEFI_TCG2_FINAL_EVENTS_TABLE {\r
//\r
// The version of this structure.\r
//\r
- UINT64 Version;\r
+ UINT64 Version;\r
//\r
// Number of events recorded after invocation of GetEventLog API\r
//\r
- UINT64 NumberOfEvents;\r
+ UINT64 NumberOfEvents;\r
//\r
// List of events of type TCG_PCR_EVENT2.\r
//\r
-//TCG_PCR_EVENT2 Event[1];\r
+ // TCG_PCR_EVENT2 Event[1];\r
} EFI_TCG2_FINAL_EVENTS_TABLE;\r
\r
-#define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1\r
+#define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1\r
\r
#endif\r
typedef struct _EFI_TCG_PROTOCOL EFI_TCG_PROTOCOL;\r
\r
typedef struct {\r
- UINT8 Major;\r
- UINT8 Minor;\r
- UINT8 RevMajor;\r
- UINT8 RevMinor;\r
+ UINT8 Major;\r
+ UINT8 Minor;\r
+ UINT8 RevMajor;\r
+ UINT8 RevMinor;\r
} TCG_VERSION;\r
\r
typedef struct _TCG_EFI_BOOT_SERVICE_CAPABILITY {\r
BOOLEAN TPMDeactivatedFlag; /// 01h = TPM currently deactivated.\r
} TCG_EFI_BOOT_SERVICE_CAPABILITY;\r
\r
-typedef UINT32 TCG_ALGORITHM_ID;\r
+typedef UINT32 TCG_ALGORITHM_ID;\r
\r
/**\r
This service provides EFI protocol capability information, state information\r
(EFIAPI *EFI_TCG_STATUS_CHECK)(\r
IN EFI_TCG_PROTOCOL *This,\r
OUT TCG_EFI_BOOT_SERVICE_CAPABILITY\r
- *ProtocolCapability,\r
+ *ProtocolCapability,\r
OUT UINT32 *TCGFeatureFlags,\r
OUT EFI_PHYSICAL_ADDRESS *EventLogLocation,\r
OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry\r
IN TCG_ALGORITHM_ID AlgorithmId,\r
IN OUT TCG_PCR_EVENT *TCGLogData,\r
IN OUT UINT32 *EventNumber,\r
- OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry\r
+ OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry\r
);\r
\r
///\r
/// The EFI_TCG Protocol abstracts TCG activity.\r
///\r
struct _EFI_TCG_PROTOCOL {\r
- EFI_TCG_STATUS_CHECK StatusCheck;\r
- EFI_TCG_HASH_ALL HashAll;\r
- EFI_TCG_LOG_EVENT LogEvent;\r
- EFI_TCG_PASS_THROUGH_TO_TPM PassThroughToTpm;\r
- EFI_TCG_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
+ EFI_TCG_STATUS_CHECK StatusCheck;\r
+ EFI_TCG_HASH_ALL HashAll;\r
+ EFI_TCG_LOG_EVENT LogEvent;\r
+ EFI_TCG_PASS_THROUGH_TO_TPM PassThroughToTpm;\r
+ EFI_TCG_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
};\r
\r
-extern EFI_GUID gEfiTcgProtocolGuid;\r
+extern EFI_GUID gEfiTcgProtocolGuid;\r
\r
#endif\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE InstanceHandle;\r
- EFI_IPv4_ADDRESS LocalAddress;\r
- UINT16 LocalPort;\r
- EFI_IPv4_ADDRESS RemoteAddress;\r
- UINT16 RemotePort;\r
+ EFI_HANDLE InstanceHandle;\r
+ EFI_IPv4_ADDRESS LocalAddress;\r
+ UINT16 LocalPort;\r
+ EFI_IPv4_ADDRESS RemoteAddress;\r
+ UINT16 RemotePort;\r
} EFI_TCP4_SERVICE_POINT;\r
\r
///\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE DriverHandle;\r
- UINT32 ServiceCount;\r
- EFI_TCP4_SERVICE_POINT Services[1];\r
+ EFI_HANDLE DriverHandle;\r
+ UINT32 ServiceCount;\r
+ EFI_TCP4_SERVICE_POINT Services[1];\r
} EFI_TCP4_VARIABLE_DATA;\r
\r
typedef struct {\r
- BOOLEAN UseDefaultAddress;\r
- EFI_IPv4_ADDRESS StationAddress;\r
- EFI_IPv4_ADDRESS SubnetMask;\r
- UINT16 StationPort;\r
- EFI_IPv4_ADDRESS RemoteAddress;\r
- UINT16 RemotePort;\r
- BOOLEAN ActiveFlag;\r
+ BOOLEAN UseDefaultAddress;\r
+ EFI_IPv4_ADDRESS StationAddress;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
+ UINT16 StationPort;\r
+ EFI_IPv4_ADDRESS RemoteAddress;\r
+ UINT16 RemotePort;\r
+ BOOLEAN ActiveFlag;\r
} EFI_TCP4_ACCESS_POINT;\r
\r
typedef struct {\r
- UINT32 ReceiveBufferSize;\r
- UINT32 SendBufferSize;\r
- UINT32 MaxSynBackLog;\r
- UINT32 ConnectionTimeout;\r
- UINT32 DataRetries;\r
- UINT32 FinTimeout;\r
- UINT32 TimeWaitTimeout;\r
- UINT32 KeepAliveProbes;\r
- UINT32 KeepAliveTime;\r
- UINT32 KeepAliveInterval;\r
- BOOLEAN EnableNagle;\r
- BOOLEAN EnableTimeStamp;\r
- BOOLEAN EnableWindowScaling;\r
- BOOLEAN EnableSelectiveAck;\r
- BOOLEAN EnablePathMtuDiscovery;\r
+ UINT32 ReceiveBufferSize;\r
+ UINT32 SendBufferSize;\r
+ UINT32 MaxSynBackLog;\r
+ UINT32 ConnectionTimeout;\r
+ UINT32 DataRetries;\r
+ UINT32 FinTimeout;\r
+ UINT32 TimeWaitTimeout;\r
+ UINT32 KeepAliveProbes;\r
+ UINT32 KeepAliveTime;\r
+ UINT32 KeepAliveInterval;\r
+ BOOLEAN EnableNagle;\r
+ BOOLEAN EnableTimeStamp;\r
+ BOOLEAN EnableWindowScaling;\r
+ BOOLEAN EnableSelectiveAck;\r
+ BOOLEAN EnablePathMtuDiscovery;\r
} EFI_TCP4_OPTION;\r
\r
typedef struct {\r
//\r
// I/O parameters\r
//\r
- UINT8 TypeOfService;\r
- UINT8 TimeToLive;\r
+ UINT8 TypeOfService;\r
+ UINT8 TimeToLive;\r
\r
//\r
// Access Point\r
//\r
- EFI_TCP4_ACCESS_POINT AccessPoint;\r
+ EFI_TCP4_ACCESS_POINT AccessPoint;\r
\r
//\r
// TCP Control Options\r
//\r
- EFI_TCP4_OPTION *ControlOption;\r
+ EFI_TCP4_OPTION *ControlOption;\r
} EFI_TCP4_CONFIG_DATA;\r
\r
///\r
/// TCP4 connnection state\r
///\r
typedef enum {\r
- Tcp4StateClosed = 0,\r
- Tcp4StateListen = 1,\r
- Tcp4StateSynSent = 2,\r
- Tcp4StateSynReceived = 3,\r
- Tcp4StateEstablished = 4,\r
- Tcp4StateFinWait1 = 5,\r
- Tcp4StateFinWait2 = 6,\r
- Tcp4StateClosing = 7,\r
- Tcp4StateTimeWait = 8,\r
- Tcp4StateCloseWait = 9,\r
- Tcp4StateLastAck = 10\r
+ Tcp4StateClosed = 0,\r
+ Tcp4StateListen = 1,\r
+ Tcp4StateSynSent = 2,\r
+ Tcp4StateSynReceived = 3,\r
+ Tcp4StateEstablished = 4,\r
+ Tcp4StateFinWait1 = 5,\r
+ Tcp4StateFinWait2 = 6,\r
+ Tcp4StateClosing = 7,\r
+ Tcp4StateTimeWait = 8,\r
+ Tcp4StateCloseWait = 9,\r
+ Tcp4StateLastAck = 10\r
} EFI_TCP4_CONNECTION_STATE;\r
\r
typedef struct {\r
- EFI_EVENT Event;\r
- EFI_STATUS Status;\r
+ EFI_EVENT Event;\r
+ EFI_STATUS Status;\r
} EFI_TCP4_COMPLETION_TOKEN;\r
\r
typedef struct {\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurred.\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
+ EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
} EFI_TCP4_CONNECTION_TOKEN;\r
\r
typedef struct {\r
- EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
- EFI_HANDLE NewChildHandle;\r
+ EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
+ EFI_HANDLE NewChildHandle;\r
} EFI_TCP4_LISTEN_TOKEN;\r
\r
typedef struct {\r
- UINT32 FragmentLength;\r
- VOID *FragmentBuffer;\r
+ UINT32 FragmentLength;\r
+ VOID *FragmentBuffer;\r
} EFI_TCP4_FRAGMENT_DATA;\r
\r
typedef struct {\r
/// EFI_DEVICE_ERROR: An unexpected system or network error occurs.\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
+ EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
union {\r
///\r
/// When this token is used for receiving, RxData is a pointer to EFI_TCP4_RECEIVE_DATA.\r
///\r
- EFI_TCP4_RECEIVE_DATA *RxData;\r
+ EFI_TCP4_RECEIVE_DATA *RxData;\r
///\r
/// When this token is used for transmitting, TxData is a pointer to EFI_TCP4_TRANSMIT_DATA.\r
///\r
- EFI_TCP4_TRANSMIT_DATA *TxData;\r
+ EFI_TCP4_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_TCP4_IO_TOKEN;\r
\r
typedef struct {\r
- EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
- BOOLEAN AbortOnClose;\r
+ EFI_TCP4_COMPLETION_TOKEN CompletionToken;\r
+ BOOLEAN AbortOnClose;\r
} EFI_TCP4_CLOSE_TOKEN;\r
\r
//\r
IN EFI_TCP4_CONFIG_DATA *TcpConfigData OPTIONAL\r
);\r
\r
-\r
/**\r
Add or delete a route entry to the route table\r
\r
IN EFI_TCP4_CONNECTION_TOKEN *ConnectionToken\r
);\r
\r
-\r
/**\r
Listen on the passive instance to accept an incoming connection request. This is a nonblocking operation.\r
\r
IN EFI_TCP4_IO_TOKEN *Token\r
);\r
\r
-\r
/**\r
Places an asynchronous receive request into the receiving queue.\r
\r
IN EFI_TCP4_COMPLETION_TOKEN *Token OPTIONAL\r
);\r
\r
-\r
/**\r
Poll to receive incoming data and transmit outgoing segments.\r
\r
/// such as the routing table.\r
///\r
struct _EFI_TCP4_PROTOCOL {\r
- EFI_TCP4_GET_MODE_DATA GetModeData;\r
- EFI_TCP4_CONFIGURE Configure;\r
- EFI_TCP4_ROUTES Routes;\r
- EFI_TCP4_CONNECT Connect;\r
- EFI_TCP4_ACCEPT Accept;\r
- EFI_TCP4_TRANSMIT Transmit;\r
- EFI_TCP4_RECEIVE Receive;\r
- EFI_TCP4_CLOSE Close;\r
- EFI_TCP4_CANCEL Cancel;\r
- EFI_TCP4_POLL Poll;\r
+ EFI_TCP4_GET_MODE_DATA GetModeData;\r
+ EFI_TCP4_CONFIGURE Configure;\r
+ EFI_TCP4_ROUTES Routes;\r
+ EFI_TCP4_CONNECT Connect;\r
+ EFI_TCP4_ACCEPT Accept;\r
+ EFI_TCP4_TRANSMIT Transmit;\r
+ EFI_TCP4_RECEIVE Receive;\r
+ EFI_TCP4_CLOSE Close;\r
+ EFI_TCP4_CANCEL Cancel;\r
+ EFI_TCP4_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiTcp4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiTcp4ProtocolGuid;\r
+extern EFI_GUID gEfiTcp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiTcp4ProtocolGuid;\r
\r
#endif\r
0x46e44855, 0xbd60, 0x4ab7, {0xab, 0x0d, 0xa6, 0x79, 0xb9, 0x44, 0x7d, 0x77 } \\r
}\r
\r
-\r
typedef struct _EFI_TCP6_PROTOCOL EFI_TCP6_PROTOCOL;\r
\r
///\r
/// The EFI TCPv6 Protocol instance handle that is using this\r
/// address/port pair.\r
///\r
- EFI_HANDLE InstanceHandle;\r
+ EFI_HANDLE InstanceHandle;\r
///\r
/// The local IPv6 address to which this TCP instance is bound. Set\r
/// to 0::/128, if this TCP instance is configured to listen on all\r
/// available source addresses.\r
///\r
- EFI_IPv6_ADDRESS LocalAddress;\r
+ EFI_IPv6_ADDRESS LocalAddress;\r
///\r
/// The local port number in host byte order.\r
///\r
- UINT16 LocalPort;\r
+ UINT16 LocalPort;\r
///\r
/// The remote IPv6 address. It may be 0::/128 if this TCP instance is\r
/// not connected to any remote host.\r
///\r
- EFI_IPv6_ADDRESS RemoteAddress;\r
+ EFI_IPv6_ADDRESS RemoteAddress;\r
///\r
/// The remote port number in host byte order. It may be zero if this\r
/// TCP instance is not connected to any remote host.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
} EFI_TCP6_SERVICE_POINT;\r
\r
///\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE DriverHandle; ///< The handle of the driver that creates this entry.\r
- UINT32 ServiceCount; ///< The number of address/port pairs following this data structure.\r
- EFI_TCP6_SERVICE_POINT Services[1]; ///< List of address/port pairs that are currently in use.\r
+ EFI_HANDLE DriverHandle; ///< The handle of the driver that creates this entry.\r
+ UINT32 ServiceCount; ///< The number of address/port pairs following this data structure.\r
+ EFI_TCP6_SERVICE_POINT Services[1]; ///< List of address/port pairs that are currently in use.\r
} EFI_TCP6_VARIABLE_DATA;\r
\r
///\r
/// it must be one of the configured IP addresses in the underlying\r
/// IPv6 driver.\r
///\r
- EFI_IPv6_ADDRESS StationAddress;\r
+ EFI_IPv6_ADDRESS StationAddress;\r
///\r
/// The local port number to which this EFI TCPv6 Protocol instance\r
/// is bound. If the instance doesn't care the local port number, set\r
/// StationPort to zero to use an ephemeral port.\r
///\r
- UINT16 StationPort;\r
+ UINT16 StationPort;\r
///\r
/// The remote IP address to which this EFI TCPv6 Protocol instance\r
/// is connected. If ActiveFlag is FALSE (i.e. a passive TCPv6\r
/// can be set to zero and means that incoming connection requests\r
/// from any address will be accepted.\r
///\r
- EFI_IPv6_ADDRESS RemoteAddress;\r
+ EFI_IPv6_ADDRESS RemoteAddress;\r
///\r
/// The remote port to which this EFI TCPv6 Protocol instance\r
/// connects or from which connection request will be accepted by\r
/// any port will be accepted. Its value can not be zero when\r
/// ActiveFlag is TRUE.\r
///\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
///\r
/// Set it to TRUE to initiate an active open. Set it to FALSE to\r
/// initiate a passive open to act as a server.\r
///\r
- BOOLEAN ActiveFlag;\r
+ BOOLEAN ActiveFlag;\r
} EFI_TCP6_ACCESS_POINT;\r
\r
///\r
///\r
/// The size of the TCP receive buffer.\r
///\r
- UINT32 ReceiveBufferSize;\r
+ UINT32 ReceiveBufferSize;\r
///\r
/// The size of the TCP send buffer.\r
///\r
- UINT32 SendBufferSize;\r
+ UINT32 SendBufferSize;\r
///\r
/// The length of incoming connect request queue for a passive\r
/// instance. When set to zero, the value is implementation specific.\r
///\r
- UINT32 MaxSynBackLog;\r
+ UINT32 MaxSynBackLog;\r
///\r
/// The maximum seconds a TCP instance will wait for before a TCP\r
/// connection established. When set to zero, the value is\r
/// implementation specific.\r
///\r
- UINT32 ConnectionTimeout;\r
+ UINT32 ConnectionTimeout;\r
///\r
- ///The number of times TCP will attempt to retransmit a packet on\r
- ///an established connection. When set to zero, the value is\r
- ///implementation specific.\r
+ /// The number of times TCP will attempt to retransmit a packet on\r
+ /// an established connection. When set to zero, the value is\r
+ /// implementation specific.\r
///\r
- UINT32 DataRetries;\r
+ UINT32 DataRetries;\r
///\r
/// How many seconds to wait in the FIN_WAIT_2 states for a final\r
/// FIN flag before the TCP instance is closed. This timeout is in\r
/// it should be disabled because the FIN_WAIT_2 timer itself is\r
/// against the standard. The default value is 60.\r
///\r
- UINT32 FinTimeout;\r
+ UINT32 FinTimeout;\r
///\r
/// How many seconds to wait in TIME_WAIT state before the TCP\r
/// instance is closed. The timer is disabled completely to provide a\r
/// method to close the TCP connection quickly if it is set to zero. It\r
/// is against the related RFC documents.\r
///\r
- UINT32 TimeWaitTimeout;\r
+ UINT32 TimeWaitTimeout;\r
///\r
/// The maximum number of TCP keep-alive probes to send before\r
/// giving up and resetting the connection if no response from the\r
/// other end. Set to zero to disable keep-alive probe.\r
///\r
- UINT32 KeepAliveProbes;\r
+ UINT32 KeepAliveProbes;\r
///\r
/// The number of seconds a connection needs to be idle before TCP\r
/// sends out periodical keep-alive probes. When set to zero, the\r
/// value is implementation specific. It should be ignored if keep-\r
/// alive probe is disabled.\r
///\r
- UINT32 KeepAliveTime;\r
+ UINT32 KeepAliveTime;\r
///\r
/// The number of seconds between TCP keep-alive probes after the\r
/// periodical keep-alive probe if no response. When set to zero, the\r
/// value is implementation specific. It should be ignored if keep-\r
/// alive probe is disabled.\r
///\r
- UINT32 KeepAliveInterval;\r
+ UINT32 KeepAliveInterval;\r
///\r
/// Set it to TRUE to enable the Nagle algorithm as defined in\r
/// RFC896. Set it to FALSE to disable it.\r
///\r
- BOOLEAN EnableNagle;\r
+ BOOLEAN EnableNagle;\r
///\r
/// Set it to TRUE to enable TCP timestamps option as defined in\r
/// RFC1323. Set to FALSE to disable it.\r
///\r
- BOOLEAN EnableTimeStamp;\r
+ BOOLEAN EnableTimeStamp;\r
///\r
/// Set it to TRUE to enable TCP window scale option as defined in\r
/// RFC1323. Set it to FALSE to disable it.\r
///\r
- BOOLEAN EnableWindowScaling;\r
+ BOOLEAN EnableWindowScaling;\r
///\r
/// Set it to TRUE to enable selective acknowledge mechanism\r
/// described in RFC 2018. Set it to FALSE to disable it.\r
/// Implementation that supports SACK can optionally support\r
/// DSAK as defined in RFC 2883.\r
///\r
- BOOLEAN EnableSelectiveAck;\r
+ BOOLEAN EnableSelectiveAck;\r
///\r
/// Set it to TRUE to enable path MTU discovery as defined in\r
/// RFC 1191. Set to FALSE to disable it.\r
///\r
- BOOLEAN EnablePathMtuDiscovery;\r
+ BOOLEAN EnablePathMtuDiscovery;\r
} EFI_TCP6_OPTION;\r
\r
///\r
///\r
/// TrafficClass field in transmitted IPv6 packets.\r
///\r
- UINT8 TrafficClass;\r
+ UINT8 TrafficClass;\r
///\r
/// HopLimit field in transmitted IPv6 packets.\r
///\r
- UINT8 HopLimit;\r
+ UINT8 HopLimit;\r
///\r
/// Used to specify TCP communication end settings for a TCP instance.\r
///\r
- EFI_TCP6_ACCESS_POINT AccessPoint;\r
+ EFI_TCP6_ACCESS_POINT AccessPoint;\r
///\r
/// Used to configure the advance TCP option for a connection. If set\r
/// to NULL, implementation specific options for TCP connection will be used.\r
///\r
- EFI_TCP6_OPTION *ControlOption;\r
+ EFI_TCP6_OPTION *ControlOption;\r
} EFI_TCP6_CONFIG_DATA;\r
\r
///\r
/// The Event to signal after request is finished and Status field is\r
/// updated by the EFI TCPv6 Protocol driver.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// The result of the completed operation.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
} EFI_TCP6_COMPLETION_TOKEN;\r
\r
///\r
/// EFI_SECURITY_VIOLATION: The active open was failed because of IPSec policy check.\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
+ EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
} EFI_TCP6_CONNECTION_TOKEN;\r
\r
///\r
/// EFI_ABORTED: The accept request has been aborted.\r
/// EFI_SECURITY_VIOLATION: The accept operation was failed because of IPSec policy check.\r
///\r
- EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
- EFI_HANDLE NewChildHandle;\r
+ EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
+ EFI_HANDLE NewChildHandle;\r
} EFI_TCP6_LISTEN_TOKEN;\r
\r
///\r
/// purpose of this structure is to provide scattered read and write.\r
///\r
typedef struct {\r
- UINT32 FragmentLength; ///< Length of data buffer in the fragment.\r
- VOID *FragmentBuffer; ///< Pointer to the data buffer in the fragment.\r
+ UINT32 FragmentLength; ///< Length of data buffer in the fragment.\r
+ VOID *FragmentBuffer; ///< Pointer to the data buffer in the fragment.\r
} EFI_TCP6_FRAGMENT_DATA;\r
\r
///\r
/// Whether the data is urgent. When this flag is set, the instance is in\r
/// urgent mode.\r
///\r
- BOOLEAN UrgentFlag;\r
+ BOOLEAN UrgentFlag;\r
///\r
/// When calling Receive() function, it is the byte counts of all\r
/// Fragmentbuffer in FragmentTable allocated by user.\r
/// When the token is signaled by TCPv6 driver it is the length of\r
/// received data in the fragments.\r
///\r
- UINT32 DataLength;\r
+ UINT32 DataLength;\r
///\r
/// Number of fragments.\r
///\r
- UINT32 FragmentCount;\r
+ UINT32 FragmentCount;\r
///\r
/// An array of fragment descriptors.\r
///\r
- EFI_TCP6_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_TCP6_FRAGMENT_DATA FragmentTable[1];\r
} EFI_TCP6_RECEIVE_DATA;\r
\r
///\r
/// transmission may be delayed to combine with data from\r
/// subsequent Transmit()s for efficiency.\r
///\r
- BOOLEAN Push;\r
+ BOOLEAN Push;\r
///\r
/// The data in the fragment table are urgent and urgent point is in\r
/// effect if TRUE. Otherwise those data are NOT considered urgent.\r
///\r
- BOOLEAN Urgent;\r
+ BOOLEAN Urgent;\r
///\r
/// Length of the data in the fragments.\r
///\r
- UINT32 DataLength;\r
+ UINT32 DataLength;\r
///\r
/// Number of fragments.\r
///\r
- UINT32 FragmentCount;\r
+ UINT32 FragmentCount;\r
///\r
/// An array of fragment descriptors.\r
///\r
- EFI_TCP6_FRAGMENT_DATA FragmentTable[1];\r
+ EFI_TCP6_FRAGMENT_DATA FragmentTable[1];\r
} EFI_TCP6_TRANSMIT_DATA;\r
\r
///\r
/// operation was failed because of IPSec policy check\r
/// EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
+ EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
union {\r
///\r
/// When this token is used for receiving, RxData is a pointer to\r
/// EFI_TCP6_RECEIVE_DATA.\r
///\r
- EFI_TCP6_RECEIVE_DATA *RxData;\r
+ EFI_TCP6_RECEIVE_DATA *RxData;\r
///\r
/// When this token is used for transmitting, TxData is a pointer to\r
/// EFI_TCP6_TRANSMIT_DATA.\r
///\r
- EFI_TCP6_TRANSMIT_DATA *TxData;\r
+ EFI_TCP6_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_TCP6_IO_TOKEN;\r
\r
/// EFI_ABORTED: User called configure with NULL without close stopping.\r
/// EFI_SECURITY_VIOLATION: The close operation was failed because of IPSec policy check.\r
///\r
- EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
+ EFI_TCP6_COMPLETION_TOKEN CompletionToken;\r
///\r
/// Abort the TCP connection on close instead of the standard TCP\r
/// close process when it is set to TRUE. This option can be used to\r
/// satisfy a fast disconnect.\r
///\r
- BOOLEAN AbortOnClose;\r
+ BOOLEAN AbortOnClose;\r
} EFI_TCP6_CLOSE_TOKEN;\r
\r
/**\r
/// Each instance has its own independent settings.\r
///\r
struct _EFI_TCP6_PROTOCOL {\r
- EFI_TCP6_GET_MODE_DATA GetModeData;\r
- EFI_TCP6_CONFIGURE Configure;\r
- EFI_TCP6_CONNECT Connect;\r
- EFI_TCP6_ACCEPT Accept;\r
- EFI_TCP6_TRANSMIT Transmit;\r
- EFI_TCP6_RECEIVE Receive;\r
- EFI_TCP6_CLOSE Close;\r
- EFI_TCP6_CANCEL Cancel;\r
- EFI_TCP6_POLL Poll;\r
+ EFI_TCP6_GET_MODE_DATA GetModeData;\r
+ EFI_TCP6_CONFIGURE Configure;\r
+ EFI_TCP6_CONNECT Connect;\r
+ EFI_TCP6_ACCEPT Accept;\r
+ EFI_TCP6_TRANSMIT Transmit;\r
+ EFI_TCP6_RECEIVE Receive;\r
+ EFI_TCP6_CLOSE Close;\r
+ EFI_TCP6_CANCEL Cancel;\r
+ EFI_TCP6_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiTcp6ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiTcp6ProtocolGuid;\r
+extern EFI_GUID gEfiTcp6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiTcp6ProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// Declare forward reference for the Timer Architectural Protocol\r
///\r
-typedef struct _EFI_TIMER_ARCH_PROTOCOL EFI_TIMER_ARCH_PROTOCOL;\r
+typedef struct _EFI_TIMER_ARCH_PROTOCOL EFI_TIMER_ARCH_PROTOCOL;\r
\r
/**\r
This function of this type is called when a timer interrupt fires. This\r
(EFIAPI *EFI_TIMER_REGISTER_HANDLER)(\r
IN EFI_TIMER_ARCH_PROTOCOL *This,\r
IN EFI_TIMER_NOTIFY NotifyFunction\r
-);\r
+ );\r
\r
/**\r
This function adjusts the period of timer interrupts to the value specified\r
IN EFI_TIMER_ARCH_PROTOCOL *This\r
);\r
\r
-\r
///\r
/// This protocol provides the services to initialize a periodic timer\r
/// interrupt, and to register a handler that is called each time the timer\r
/// interrupt.\r
///\r
struct _EFI_TIMER_ARCH_PROTOCOL {\r
- EFI_TIMER_REGISTER_HANDLER RegisterHandler;\r
- EFI_TIMER_SET_TIMER_PERIOD SetTimerPeriod;\r
- EFI_TIMER_GET_TIMER_PERIOD GetTimerPeriod;\r
- EFI_TIMER_GENERATE_SOFT_INTERRUPT GenerateSoftInterrupt;\r
+ EFI_TIMER_REGISTER_HANDLER RegisterHandler;\r
+ EFI_TIMER_SET_TIMER_PERIOD SetTimerPeriod;\r
+ EFI_TIMER_GET_TIMER_PERIOD GetTimerPeriod;\r
+ EFI_TIMER_GENERATE_SOFT_INTERRUPT GenerateSoftInterrupt;\r
};\r
\r
-extern EFI_GUID gEfiTimerArchProtocolGuid;\r
+extern EFI_GUID gEfiTimerArchProtocolGuid;\r
\r
#endif\r
#ifndef __EFI_TIME_STAMP_PROTOCOL_H__\r
#define __EFI_TIME_STAMP_PROTOCOL_H__\r
\r
-\r
#define EFI_TIMESTAMP_PROTOCOL_GUID \\r
{ 0xafbfde41, 0x2e6e, 0x4262, {0xba, 0x65, 0x62, 0xb9, 0x23, 0x6e, 0x54, 0x95 } }\r
\r
///\r
/// Declare forward reference for the Time Stamp Protocol\r
///\r
-typedef struct _EFI_TIMESTAMP_PROTOCOL EFI_TIMESTAMP_PROTOCOL;\r
+typedef struct _EFI_TIMESTAMP_PROTOCOL EFI_TIMESTAMP_PROTOCOL;\r
\r
///\r
/// EFI_TIMESTAMP_PROPERTIES\r
///\r
/// The frequency of the timestamp counter in Hz.\r
///\r
- UINT64 Frequency;\r
+ UINT64 Frequency;\r
///\r
/// The value that the timestamp counter ends with immediately before it rolls over.\r
/// For example, a 64-bit free running counter would have an EndValue of 0xFFFFFFFFFFFFFFFF.\r
/// A 24-bit free running counter would have an EndValue of 0xFFFFFF.\r
///\r
- UINT64 EndValue;\r
+ UINT64 EndValue;\r
} EFI_TIMESTAMP_PROPERTIES;\r
\r
/**\r
OUT EFI_TIMESTAMP_PROPERTIES *Properties\r
);\r
\r
-\r
-\r
///\r
/// EFI_TIMESTAMP_PROTOCOL\r
/// The protocol provides a platform independent interface for retrieving a high resolution\r
/// timestamp counter.\r
///\r
struct _EFI_TIMESTAMP_PROTOCOL {\r
- TIMESTAMP_GET GetTimestamp;\r
- TIMESTAMP_GET_PROPERTIES GetProperties;\r
+ TIMESTAMP_GET GetTimestamp;\r
+ TIMESTAMP_GET_PROPERTIES GetProperties;\r
};\r
\r
-extern EFI_GUID gEfiTimestampProtocolGuid;\r
+extern EFI_GUID gEfiTimestampProtocolGuid;\r
\r
#endif\r
-\r
/// SSL2.0 is obsolete and should not be used.\r
///\r
typedef struct {\r
- UINT8 Major;\r
- UINT8 Minor;\r
+ UINT8 Major;\r
+ UINT8 Minor;\r
} EFI_TLS_VERSION;\r
\r
///\r
///\r
#pragma pack (1)\r
typedef struct {\r
- UINT8 Data1;\r
- UINT8 Data2;\r
+ UINT8 Data1;\r
+ UINT8 Data2;\r
} EFI_TLS_CIPHER;\r
#pragma pack ()\r
\r
///\r
#pragma pack (1)\r
typedef struct {\r
- UINT16 ExtensionType;\r
- UINT16 Length;\r
- UINT8 Data[1];\r
+ UINT16 ExtensionType;\r
+ UINT16 Length;\r
+ UINT8 Data[1];\r
} EFI_TLS_EXTENSION;\r
#pragma pack ()\r
\r
/// Use either EFI_TLS_VERIFY_NONE or EFI_TLS_VERIFY_PEER, the last two options\r
/// are 'ORed' with EFI_TLS_VERIFY_PEER if they are desired.\r
///\r
-typedef UINT32 EFI_TLS_VERIFY;\r
+typedef UINT32 EFI_TLS_VERIFY;\r
///\r
/// No certificates will be sent or the TLS/SSL handshake will be continued regardless\r
/// of the certificate verification result.\r
///\r
-#define EFI_TLS_VERIFY_NONE 0x0\r
+#define EFI_TLS_VERIFY_NONE 0x0\r
///\r
/// The TLS/SSL handshake is immediately terminated with an alert message containing\r
/// the reason for the certificate verification failure.\r
///\r
-#define EFI_TLS_VERIFY_PEER 0x1\r
+#define EFI_TLS_VERIFY_PEER 0x1\r
///\r
/// EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT is only meaningful in the server mode.\r
/// TLS session will fail if client certificate is absent.\r
/// TLS session only verify client once, and doesn't request certificate during\r
/// re-negotiation.\r
///\r
-#define EFI_TLS_VERIFY_CLIENT_ONCE 0x4\r
+#define EFI_TLS_VERIFY_CLIENT_ONCE 0x4\r
\r
///\r
/// EFI_TLS_VERIFY_HOST_FLAG\r
/// There is no additional flags set for hostname validation.\r
/// Wildcards are supported and they match only in the left-most label.\r
///\r
-#define EFI_TLS_VERIFY_FLAG_NONE 0x00\r
+#define EFI_TLS_VERIFY_FLAG_NONE 0x00\r
///\r
/// Always check the Subject Distinguished Name (DN) in the peer certificate even if the\r
/// certificate contains Subject Alternative Name (SAN).\r
///\r
-#define EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT 0x01\r
+#define EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT 0x01\r
///\r
/// Disable the match of all wildcards.\r
///\r
-#define EFI_TLS_VERIFY_FLAG_NO_WILDCARDS 0x02\r
+#define EFI_TLS_VERIFY_FLAG_NO_WILDCARDS 0x02\r
///\r
/// Disable the "*" as wildcard in labels that have a prefix or suffix (e.g. "www*" or "*www").\r
///\r
-#define EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS 0x04\r
+#define EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS 0x04\r
///\r
/// Allow the "*" to match more than one labels. Otherwise, only matches a single label.\r
///\r
-#define EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS 0x08\r
+#define EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS 0x08\r
///\r
/// Restrict to only match direct child sub-domains which start with ".".\r
/// For example, a name of ".example.com" would match "www.example.com" with this flag,\r
/// but would not match "www.sub.example.com".\r
///\r
-#define EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS 0x10\r
+#define EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS 0x10\r
///\r
/// Never check the Subject Distinguished Name (DN) even there is no\r
/// Subject Alternative Name (SAN) in the certificate.\r
///\r
-#define EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT 0x20\r
+#define EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT 0x20\r
\r
///\r
/// EFI_TLS_VERIFY_HOST\r
///\r
#pragma pack (1)\r
typedef struct {\r
- EFI_TLS_VERIFY_HOST_FLAG Flags;\r
- CHAR8 *HostName;\r
+ EFI_TLS_VERIFY_HOST_FLAG Flags;\r
+ CHAR8 *HostName;\r
} EFI_TLS_VERIFY_HOST;\r
#pragma pack ()\r
\r
///\r
#pragma pack (1)\r
typedef struct {\r
- UINT32 GmtUnixTime;\r
- UINT8 RandomBytes[28];\r
+ UINT32 GmtUnixTime;\r
+ UINT8 RandomBytes[28];\r
} EFI_TLS_RANDOM;\r
#pragma pack ()\r
\r
///\r
#pragma pack (1)\r
typedef struct {\r
- UINT8 Data[48];\r
+ UINT8 Data[48];\r
} EFI_TLS_MASTER_SECRET;\r
#pragma pack ()\r
\r
#define MAX_TLS_SESSION_ID_LENGTH 32\r
#pragma pack (1)\r
typedef struct {\r
- UINT16 Length;\r
- UINT8 Data[MAX_TLS_SESSION_ID_LENGTH];\r
+ UINT16 Length;\r
+ UINT8 Data[MAX_TLS_SESSION_ID_LENGTH];\r
} EFI_TLS_SESSION_ID;\r
#pragma pack ()\r
\r
EfiTlsSessionError,\r
\r
EfiTlsSessionStateMaximum\r
-\r
} EFI_TLS_SESSION_STATE;\r
\r
///\r
///\r
/// Length of data buffer in the fragment.\r
///\r
- UINT32 FragmentLength;\r
+ UINT32 FragmentLength;\r
///\r
/// Pointer to the data buffer in the fragment.\r
///\r
- VOID *FragmentBuffer;\r
+ VOID *FragmentBuffer;\r
} EFI_TLS_FRAGMENT_DATA;\r
\r
///\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TLS_SET_SESSION_DATA) (\r
+(EFIAPI *EFI_TLS_SET_SESSION_DATA)(\r
IN EFI_TLS_PROTOCOL *This,\r
IN EFI_TLS_SESSION_DATA_TYPE DataType,\r
IN VOID *Data,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TLS_GET_SESSION_DATA) (\r
+(EFIAPI *EFI_TLS_GET_SESSION_DATA)(\r
IN EFI_TLS_PROTOCOL *This,\r
IN EFI_TLS_SESSION_DATA_TYPE DataType,\r
IN OUT VOID *Data OPTIONAL,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TLS_BUILD_RESPONSE_PACKET) (\r
+(EFIAPI *EFI_TLS_BUILD_RESPONSE_PACKET)(\r
IN EFI_TLS_PROTOCOL *This,\r
IN UINT8 *RequestBuffer OPTIONAL,\r
IN UINTN RequestSize OPTIONAL,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TLS_PROCESS_PACKET) (\r
+(EFIAPI *EFI_TLS_PROCESS_PACKET)(\r
IN EFI_TLS_PROTOCOL *This,\r
IN OUT EFI_TLS_FRAGMENT_DATA **FragmentTable,\r
IN UINT32 *FragmentCount,\r
/// For detail of TLS, please refer to TLS related RFC.\r
///\r
struct _EFI_TLS_PROTOCOL {\r
- EFI_TLS_SET_SESSION_DATA SetSessionData;\r
- EFI_TLS_GET_SESSION_DATA GetSessionData;\r
- EFI_TLS_BUILD_RESPONSE_PACKET BuildResponsePacket;\r
- EFI_TLS_PROCESS_PACKET ProcessPacket;\r
+ EFI_TLS_SET_SESSION_DATA SetSessionData;\r
+ EFI_TLS_GET_SESSION_DATA GetSessionData;\r
+ EFI_TLS_BUILD_RESPONSE_PACKET BuildResponsePacket;\r
+ EFI_TLS_PROCESS_PACKET ProcessPacket;\r
};\r
\r
-extern EFI_GUID gEfiTlsServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiTlsProtocolGuid;\r
+extern EFI_GUID gEfiTlsServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiTlsProtocolGuid;\r
\r
-#endif // __EFI_TLS_PROTOCOL_H__\r
+#endif // __EFI_TLS_PROTOCOL_H__\r
This Protocol is introduced in UEFI Specification 2.5\r
\r
**/\r
+\r
#ifndef __EFI_TLS_CONFIGURATION_PROTOCOL_H__\r
#define __EFI_TLS_CONFIGURATION_PROTOCOL_H__\r
\r
EfiTlsConfigDataTypeCertRevocationList,\r
\r
EfiTlsConfigDataTypeMaximum\r
-\r
} EFI_TLS_CONFIG_DATA_TYPE;\r
\r
/**\r
/// TLS configuration, such as Certificate, private key data.\r
///\r
struct _EFI_TLS_CONFIGURATION_PROTOCOL {\r
- EFI_TLS_CONFIGURATION_SET_DATA SetData;\r
- EFI_TLS_CONFIGURATION_GET_DATA GetData;\r
+ EFI_TLS_CONFIGURATION_SET_DATA SetData;\r
+ EFI_TLS_CONFIGURATION_GET_DATA GetData;\r
};\r
\r
-extern EFI_GUID gEfiTlsConfigurationProtocolGuid;\r
+extern EFI_GUID gEfiTlsConfigurationProtocolGuid;\r
\r
-#endif //__EFI_TLS_CONFIGURATION_PROTOCOL_H__\r
+#endif //__EFI_TLS_CONFIGURATION_PROTOCOL_H__\r
typedef struct _EFI_TREE_PROTOCOL EFI_TREE_PROTOCOL;\r
\r
typedef struct _TREE_VERSION {\r
- UINT8 Major;\r
- UINT8 Minor;\r
+ UINT8 Major;\r
+ UINT8 Minor;\r
} TREE_VERSION;\r
\r
typedef UINT32 TREE_EVENT_LOG_BITMAP;\r
typedef UINT32 TREE_EVENT_LOG_FORMAT;\r
\r
-#define TREE_EVENT_LOG_FORMAT_TCG_1_2 0x00000001\r
+#define TREE_EVENT_LOG_FORMAT_TCG_1_2 0x00000001\r
\r
typedef struct _TREE_BOOT_SERVICE_CAPABILITY {\r
//\r
// Allocated size of the structure passed in\r
//\r
- UINT8 Size;\r
+ UINT8 Size;\r
//\r
// Version of the TREE_BOOT_SERVICE_CAPABILITY structure itself.\r
// For this version of the protocol, the Major version shall be set to 1\r
// and the Minor version shall be set to 0.\r
//\r
- TREE_VERSION StructureVersion;\r
+ TREE_VERSION StructureVersion;\r
//\r
// Version of the TrEE protocol.\r
// For this version of the protocol, the Major version shall be set to 1\r
// and the Minor version shall be set to 0.\r
//\r
- TREE_VERSION ProtocolVersion;\r
+ TREE_VERSION ProtocolVersion;\r
//\r
// Supported hash algorithms\r
//\r
- UINT32 HashAlgorithmBitmap;\r
+ UINT32 HashAlgorithmBitmap;\r
//\r
// Bitmap of supported event log formats\r
//\r
- TREE_EVENT_LOG_BITMAP SupportedEventLogs;\r
+ TREE_EVENT_LOG_BITMAP SupportedEventLogs;\r
//\r
// False = TrEE not present\r
//\r
- BOOLEAN TrEEPresentFlag;\r
+ BOOLEAN TrEEPresentFlag;\r
//\r
// Max size (in bytes) of a command that can be sent to the TrEE\r
//\r
- UINT16 MaxCommandSize;\r
+ UINT16 MaxCommandSize;\r
//\r
// Max size (in bytes) of a response that can be provided by the TrEE\r
//\r
- UINT16 MaxResponseSize;\r
+ UINT16 MaxResponseSize;\r
//\r
// 4-byte Vendor ID (see Trusted Computing Group, "TCG Vendor ID Registry,"\r
// Version 1.0, Revision 0.1, August 31, 2007, "TPM Capabilities Vendor ID" section)\r
//\r
- UINT32 ManufacturerID;\r
+ UINT32 ManufacturerID;\r
} TREE_BOOT_SERVICE_CAPABILITY_1_0;\r
\r
typedef TREE_BOOT_SERVICE_CAPABILITY_1_0 TREE_BOOT_SERVICE_CAPABILITY;\r
\r
-#define TREE_BOOT_HASH_ALG_SHA1 0x00000001\r
-#define TREE_BOOT_HASH_ALG_SHA256 0x00000002\r
-#define TREE_BOOT_HASH_ALG_SHA384 0x00000004\r
-#define TREE_BOOT_HASH_ALG_SHA512 0x00000008\r
+#define TREE_BOOT_HASH_ALG_SHA1 0x00000001\r
+#define TREE_BOOT_HASH_ALG_SHA256 0x00000002\r
+#define TREE_BOOT_HASH_ALG_SHA384 0x00000004\r
+#define TREE_BOOT_HASH_ALG_SHA512 0x00000008\r
\r
//\r
// This bit is shall be set when an event shall be extended but not logged.\r
//\r
// This bit shall be set when the intent is to measure a PE/COFF image.\r
//\r
-#define PE_COFF_IMAGE 0x0000000000000010\r
+#define PE_COFF_IMAGE 0x0000000000000010\r
\r
typedef UINT32 TrEE_PCRINDEX;\r
typedef UINT32 TrEE_EVENTTYPE;\r
\r
-#define MAX_PCR_INDEX 23\r
+#define MAX_PCR_INDEX 23\r
#define TREE_EVENT_HEADER_VERSION 1\r
\r
#pragma pack(1)\r
//\r
// Total size of the event including the Size component, the header and the Event data.\r
//\r
- UINT32 Size;\r
- TrEE_EVENT_HEADER Header;\r
- UINT8 Event[1];\r
+ UINT32 Size;\r
+ TrEE_EVENT_HEADER Header;\r
+ UINT8 Event[1];\r
} TrEE_EVENT;\r
\r
#pragma pack()\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TREE_GET_CAPABILITY) (\r
+(EFIAPI *EFI_TREE_GET_CAPABILITY)(\r
IN EFI_TREE_PROTOCOL *This,\r
IN OUT TREE_BOOT_SERVICE_CAPABILITY *ProtocolCapability\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TREE_GET_EVENT_LOG) (\r
+(EFIAPI *EFI_TREE_GET_EVENT_LOG)(\r
IN EFI_TREE_PROTOCOL *This,\r
IN TREE_EVENT_LOG_FORMAT EventLogFormat,\r
OUT EFI_PHYSICAL_ADDRESS *EventLogLocation,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI * EFI_TREE_HASH_LOG_EXTEND_EVENT) (\r
+(EFIAPI *EFI_TREE_HASH_LOG_EXTEND_EVENT)(\r
IN EFI_TREE_PROTOCOL *This,\r
IN UINT64 Flags,\r
IN EFI_PHYSICAL_ADDRESS DataToHash,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_TREE_SUBMIT_COMMAND) (\r
+(EFIAPI *EFI_TREE_SUBMIT_COMMAND)(\r
IN EFI_TREE_PROTOCOL *This,\r
IN UINT32 InputParameterBlockSize,\r
IN UINT8 *InputParameterBlock,\r
);\r
\r
struct _EFI_TREE_PROTOCOL {\r
- EFI_TREE_GET_CAPABILITY GetCapability;\r
- EFI_TREE_GET_EVENT_LOG GetEventLog;\r
- EFI_TREE_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
- EFI_TREE_SUBMIT_COMMAND SubmitCommand;\r
+ EFI_TREE_GET_CAPABILITY GetCapability;\r
+ EFI_TREE_GET_EVENT_LOG GetEventLog;\r
+ EFI_TREE_HASH_LOG_EXTEND_EVENT HashLogExtendEvent;\r
+ EFI_TREE_SUBMIT_COMMAND SubmitCommand;\r
};\r
\r
-extern EFI_GUID gEfiTrEEProtocolGuid;\r
+extern EFI_GUID gEfiTrEEProtocolGuid;\r
\r
#endif\r
\r
#include <Protocol/Ip4.h>\r
//\r
-//GUID definitions\r
+// GUID definitions\r
//\r
#define EFI_UDP4_SERVICE_BINDING_PROTOCOL_GUID \\r
{ \\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE InstanceHandle;\r
- EFI_IPv4_ADDRESS LocalAddress;\r
- UINT16 LocalPort;\r
- EFI_IPv4_ADDRESS RemoteAddress;\r
- UINT16 RemotePort;\r
+ EFI_HANDLE InstanceHandle;\r
+ EFI_IPv4_ADDRESS LocalAddress;\r
+ UINT16 LocalPort;\r
+ EFI_IPv4_ADDRESS RemoteAddress;\r
+ UINT16 RemotePort;\r
} EFI_UDP4_SERVICE_POINT;\r
\r
///\r
/// The definition in here is only present to provide backwards compatability.\r
///\r
typedef struct {\r
- EFI_HANDLE DriverHandle;\r
- UINT32 ServiceCount;\r
- EFI_UDP4_SERVICE_POINT Services[1];\r
+ EFI_HANDLE DriverHandle;\r
+ UINT32 ServiceCount;\r
+ EFI_UDP4_SERVICE_POINT Services[1];\r
} EFI_UDP4_VARIABLE_DATA;\r
\r
typedef struct {\r
- UINT32 FragmentLength;\r
- VOID *FragmentBuffer;\r
+ UINT32 FragmentLength;\r
+ VOID *FragmentBuffer;\r
} EFI_UDP4_FRAGMENT_DATA;\r
\r
typedef struct {\r
- EFI_IPv4_ADDRESS SourceAddress;\r
- UINT16 SourcePort;\r
- EFI_IPv4_ADDRESS DestinationAddress;\r
- UINT16 DestinationPort;\r
+ EFI_IPv4_ADDRESS SourceAddress;\r
+ UINT16 SourcePort;\r
+ EFI_IPv4_ADDRESS DestinationAddress;\r
+ UINT16 DestinationPort;\r
} EFI_UDP4_SESSION_DATA;\r
typedef struct {\r
//\r
// Receiving Filters\r
//\r
- BOOLEAN AcceptBroadcast;\r
- BOOLEAN AcceptPromiscuous;\r
- BOOLEAN AcceptAnyPort;\r
- BOOLEAN AllowDuplicatePort;\r
+ BOOLEAN AcceptBroadcast;\r
+ BOOLEAN AcceptPromiscuous;\r
+ BOOLEAN AcceptAnyPort;\r
+ BOOLEAN AllowDuplicatePort;\r
//\r
// I/O parameters\r
//\r
- UINT8 TypeOfService;\r
- UINT8 TimeToLive;\r
- BOOLEAN DoNotFragment;\r
- UINT32 ReceiveTimeout;\r
- UINT32 TransmitTimeout;\r
+ UINT8 TypeOfService;\r
+ UINT8 TimeToLive;\r
+ BOOLEAN DoNotFragment;\r
+ UINT32 ReceiveTimeout;\r
+ UINT32 TransmitTimeout;\r
//\r
// Access Point\r
//\r
- BOOLEAN UseDefaultAddress;\r
- EFI_IPv4_ADDRESS StationAddress;\r
- EFI_IPv4_ADDRESS SubnetMask;\r
- UINT16 StationPort;\r
- EFI_IPv4_ADDRESS RemoteAddress;\r
- UINT16 RemotePort;\r
+ BOOLEAN UseDefaultAddress;\r
+ EFI_IPv4_ADDRESS StationAddress;\r
+ EFI_IPv4_ADDRESS SubnetMask;\r
+ UINT16 StationPort;\r
+ EFI_IPv4_ADDRESS RemoteAddress;\r
+ UINT16 RemotePort;\r
} EFI_UDP4_CONFIG_DATA;\r
\r
typedef struct {\r
- EFI_UDP4_SESSION_DATA *UdpSessionData; //OPTIONAL\r
- EFI_IPv4_ADDRESS *GatewayAddress; //OPTIONAL\r
+ EFI_UDP4_SESSION_DATA *UdpSessionData; // OPTIONAL\r
+ EFI_IPv4_ADDRESS *GatewayAddress; // OPTIONAL\r
UINT32 DataLength;\r
UINT32 FragmentCount;\r
EFI_UDP4_FRAGMENT_DATA FragmentTable[1];\r
EFI_UDP4_FRAGMENT_DATA FragmentTable[1];\r
} EFI_UDP4_RECEIVE_DATA;\r
\r
-\r
typedef struct {\r
- EFI_EVENT Event;\r
- EFI_STATUS Status;\r
+ EFI_EVENT Event;\r
+ EFI_STATUS Status;\r
union {\r
- EFI_UDP4_RECEIVE_DATA *RxData;\r
- EFI_UDP4_TRANSMIT_DATA *TxData;\r
+ EFI_UDP4_RECEIVE_DATA *RxData;\r
+ EFI_UDP4_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_UDP4_COMPLETION_TOKEN;\r
\r
OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL\r
);\r
\r
-\r
/**\r
Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv4\r
Protocol.\r
/// such as the routing table and group table, which are independent from each other.\r
///\r
struct _EFI_UDP4_PROTOCOL {\r
- EFI_UDP4_GET_MODE_DATA GetModeData;\r
- EFI_UDP4_CONFIGURE Configure;\r
- EFI_UDP4_GROUPS Groups;\r
- EFI_UDP4_ROUTES Routes;\r
- EFI_UDP4_TRANSMIT Transmit;\r
- EFI_UDP4_RECEIVE Receive;\r
- EFI_UDP4_CANCEL Cancel;\r
- EFI_UDP4_POLL Poll;\r
+ EFI_UDP4_GET_MODE_DATA GetModeData;\r
+ EFI_UDP4_CONFIGURE Configure;\r
+ EFI_UDP4_GROUPS Groups;\r
+ EFI_UDP4_ROUTES Routes;\r
+ EFI_UDP4_TRANSMIT Transmit;\r
+ EFI_UDP4_RECEIVE Receive;\r
+ EFI_UDP4_CANCEL Cancel;\r
+ EFI_UDP4_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiUdp4ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiUdp4ProtocolGuid;\r
+extern EFI_GUID gEfiUdp4ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiUdp4ProtocolGuid;\r
\r
#endif\r
///\r
/// The handle of the driver that creates this entry.\r
///\r
- EFI_HANDLE DriverHandle;\r
+ EFI_HANDLE DriverHandle;\r
///\r
/// The number of address/port pairs that follow this data structure.\r
///\r
- UINT32 ServiceCount;\r
+ UINT32 ServiceCount;\r
///\r
/// List of address/port pairs that are currently in use.\r
///\r
- EFI_UDP6_SERVICE_POINT Services[1];\r
+ EFI_UDP6_SERVICE_POINT Services[1];\r
} EFI_UDP6_VARIABLE_DATA;\r
\r
typedef struct _EFI_UDP6_PROTOCOL EFI_UDP6_PROTOCOL;\r
/// The purpose of this structure is to avoid copying the same packet multiple times.\r
///\r
typedef struct {\r
- UINT32 FragmentLength; ///< Length of the fragment data buffer.\r
- VOID *FragmentBuffer; ///< Pointer to the fragment data buffer.\r
+ UINT32 FragmentLength; ///< Length of the fragment data buffer.\r
+ VOID *FragmentBuffer; ///< Pointer to the fragment data buffer.\r
} EFI_UDP6_FRAGMENT_DATA;\r
\r
///\r
/// Address from which this packet is sent. This field should not be used when\r
/// sending packets.\r
///\r
- EFI_IPv6_ADDRESS SourceAddress;\r
+ EFI_IPv6_ADDRESS SourceAddress;\r
///\r
/// Port from which this packet is sent. It is in host byte order. This field should\r
/// not be used when sending packets.\r
///\r
- UINT16 SourcePort;\r
+ UINT16 SourcePort;\r
///\r
/// Address to which this packet is sent. When sending packet, it'll be ignored\r
/// if it is zero.\r
///\r
- EFI_IPv6_ADDRESS DestinationAddress;\r
+ EFI_IPv6_ADDRESS DestinationAddress;\r
///\r
/// Port to which this packet is sent. When sending packet, it'll be\r
/// ignored if it is zero.\r
///\r
- UINT16 DestinationPort;\r
+ UINT16 DestinationPort;\r
} EFI_UDP6_SESSION_DATA;\r
\r
typedef struct {\r
///\r
/// Set to TRUE to accept UDP packets that are sent to any address.\r
///\r
- BOOLEAN AcceptPromiscuous;\r
+ BOOLEAN AcceptPromiscuous;\r
///\r
/// Set to TRUE to accept UDP packets that are sent to any port.\r
///\r
- BOOLEAN AcceptAnyPort;\r
+ BOOLEAN AcceptAnyPort;\r
///\r
/// Set to TRUE to allow this EFI UDPv6 Protocol child instance to open a port number\r
/// that is already being used by another EFI UDPv6 Protocol child instance.\r
///\r
- BOOLEAN AllowDuplicatePort;\r
+ BOOLEAN AllowDuplicatePort;\r
///\r
/// TrafficClass field in transmitted IPv6 packets.\r
///\r
- UINT8 TrafficClass;\r
+ UINT8 TrafficClass;\r
///\r
/// HopLimit field in transmitted IPv6 packets.\r
///\r
- UINT8 HopLimit;\r
+ UINT8 HopLimit;\r
///\r
/// The receive timeout value (number of microseconds) to be associated with each\r
/// incoming packet. Zero means do not drop incoming packets.\r
///\r
- UINT32 ReceiveTimeout;\r
+ UINT32 ReceiveTimeout;\r
///\r
/// The transmit timeout value (number of microseconds) to be associated with each\r
/// outgoing packet. Zero means do not drop outgoing packets.\r
///\r
- UINT32 TransmitTimeout;\r
+ UINT32 TransmitTimeout;\r
///\r
/// The station IP address that will be assigned to this EFI UDPv6 Protocol instance.\r
/// The EFI UDPv6 and EFI IPv6 Protocol drivers will only deliver incoming packets\r
/// transitioning from the stopped to the started states. If no address is available\r
/// for selecting, the EFI IPv6 Protocol driver will use EFI_IP6_CONFIG_PROTOCOL to\r
/// retrieve the IPv6 address.\r
- EFI_IPv6_ADDRESS StationAddress;\r
+ EFI_IPv6_ADDRESS StationAddress;\r
///\r
/// The port number to which this EFI UDPv6 Protocol instance is bound. If a client\r
/// of the EFI UDPv6 Protocol does not care about the port number, set StationPort\r
/// to zero. The EFI UDPv6 Protocol driver will assign a random port number to transmitted\r
/// UDP packets. Ignored it if AcceptAnyPort is TRUE.\r
///\r
- UINT16 StationPort;\r
+ UINT16 StationPort;\r
///\r
/// The IP address of remote host to which this EFI UDPv6 Protocol instance is connecting.\r
/// If RemoteAddress is not 0::/128, this EFI UDPv6 Protocol instance will be connected to\r
/// RemoteAddress; i.e., outgoing packets of this EFI UDPv6 Protocol instance will be sent\r
/// to this address by default and only incoming packets from this address will be delivered\r
/// to client. Ignored for incoming filtering if AcceptPromiscuous is TRUE.\r
- EFI_IPv6_ADDRESS RemoteAddress;\r
+ EFI_IPv6_ADDRESS RemoteAddress;\r
///\r
/// The port number of the remote host to which this EFI UDPv6 Protocol instance is connecting.\r
/// If it is not zero, outgoing packets of this EFI UDPv6 Protocol instance will be sent to\r
/// this port number by default and only incoming packets from this port will be delivered\r
/// to client. Ignored if RemoteAddress is 0::/128 and ignored for incoming filtering if\r
/// AcceptPromiscuous is TRUE.\r
- UINT16 RemotePort;\r
+ UINT16 RemotePort;\r
} EFI_UDP6_CONFIG_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI UDPv6 Protocol\r
/// driver. The type of Event must be EVT_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// - EFI_SUCCESS: The receive or transmit operation completed successfully.\r
/// - EFI_SECURITY_VIOLATION: The transmit or receive was failed because of IPsec policy check.\r
/// - EFI_NO_MEDIA: There was a media error.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
union {\r
///\r
/// When this token is used for receiving, RxData is a pointer to EFI_UDP6_RECEIVE_DATA.\r
///\r
- EFI_UDP6_RECEIVE_DATA *RxData;\r
+ EFI_UDP6_RECEIVE_DATA *RxData;\r
///\r
/// When this token is used for transmitting, TxData is a pointer to EFI_UDP6_TRANSMIT_DATA.\r
///\r
- EFI_UDP6_TRANSMIT_DATA *TxData;\r
+ EFI_UDP6_TRANSMIT_DATA *TxData;\r
} Packet;\r
} EFI_UDP6_COMPLETION_TOKEN;\r
\r
OUT EFI_IP6_MODE_DATA *Ip6ModeData OPTIONAL,\r
OUT EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData OPTIONAL,\r
OUT EFI_SIMPLE_NETWORK_MODE *SnpModeData OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv6\r
(EFIAPI *EFI_UDP6_CONFIGURE)(\r
IN EFI_UDP6_PROTOCOL *This,\r
IN EFI_UDP6_CONFIG_DATA *UdpConfigData OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Joins and leaves multicast groups.\r
IN EFI_UDP6_PROTOCOL *This,\r
IN BOOLEAN JoinFlag,\r
IN EFI_IPv6_ADDRESS *MulticastAddress OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Queues outgoing data packets into the transmit queue.\r
(EFIAPI *EFI_UDP6_TRANSMIT)(\r
IN EFI_UDP6_PROTOCOL *This,\r
IN EFI_UDP6_COMPLETION_TOKEN *Token\r
-);\r
+ );\r
\r
/**\r
Places an asynchronous receive request into the receiving queue.\r
(EFIAPI *EFI_UDP6_RECEIVE)(\r
IN EFI_UDP6_PROTOCOL *This,\r
IN EFI_UDP6_COMPLETION_TOKEN *Token\r
-);\r
+ );\r
\r
/**\r
Aborts an asynchronous transmit or receive request.\r
(EFIAPI *EFI_UDP6_CANCEL)(\r
IN EFI_UDP6_PROTOCOL *This,\r
IN EFI_UDP6_COMPLETION_TOKEN *Token OPTIONAL\r
-);\r
+ );\r
\r
/**\r
Polls for incoming data packets and processes outgoing data packets.\r
EFI_STATUS\r
(EFIAPI *EFI_UDP6_POLL)(\r
IN EFI_UDP6_PROTOCOL *This\r
-);\r
+ );\r
\r
///\r
/// The EFI_UDP6_PROTOCOL defines an EFI UDPv6 Protocol session that can be used by any network drivers,\r
/// Each instance has its own settings, such as group table, that are independent from each other.\r
///\r
struct _EFI_UDP6_PROTOCOL {\r
- EFI_UDP6_GET_MODE_DATA GetModeData;\r
- EFI_UDP6_CONFIGURE Configure;\r
- EFI_UDP6_GROUPS Groups;\r
- EFI_UDP6_TRANSMIT Transmit;\r
- EFI_UDP6_RECEIVE Receive;\r
- EFI_UDP6_CANCEL Cancel;\r
- EFI_UDP6_POLL Poll;\r
+ EFI_UDP6_GET_MODE_DATA GetModeData;\r
+ EFI_UDP6_CONFIGURE Configure;\r
+ EFI_UDP6_GROUPS Groups;\r
+ EFI_UDP6_TRANSMIT Transmit;\r
+ EFI_UDP6_RECEIVE Receive;\r
+ EFI_UDP6_CANCEL Cancel;\r
+ EFI_UDP6_POLL Poll;\r
};\r
\r
-extern EFI_GUID gEfiUdp6ServiceBindingProtocolGuid;\r
-extern EFI_GUID gEfiUdp6ProtocolGuid;\r
+extern EFI_GUID gEfiUdp6ServiceBindingProtocolGuid;\r
+extern EFI_GUID gEfiUdp6ProtocolGuid;\r
\r
#endif\r
//\r
// Forward reference for pure ANSI compatability\r
//\r
-typedef struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL EFI_UFS_DEVICE_CONFIG_PROTOCOL;\r
+typedef struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL EFI_UFS_DEVICE_CONFIG_PROTOCOL;\r
\r
/**\r
Read or write specified device descriptor of a UFS device.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR) (\r
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR)(\r
IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This,\r
IN BOOLEAN Read,\r
IN UINT8 DescId,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_FLAG) (\r
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_FLAG)(\r
IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This,\r
IN BOOLEAN Read,\r
IN UINT8 FlagId,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE) (\r
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE)(\r
IN EFI_UFS_DEVICE_CONFIG_PROTOCOL *This,\r
IN BOOLEAN Read,\r
IN UINT8 AttrId,\r
///\r
/// UFS Device Config Protocol GUID variable.\r
///\r
-extern EFI_GUID gEfiUfsDeviceConfigProtocolGuid;\r
+extern EFI_GUID gEfiUfsDeviceConfigProtocolGuid;\r
\r
#endif\r
#ifndef __UGA_DRAW_H__\r
#define __UGA_DRAW_H__\r
\r
-\r
#define EFI_UGA_DRAW_PROTOCOL_GUID \\r
{ \\r
0x982c298b, 0xf4fa, 0x41cb, {0xb8, 0x38, 0x77, 0xaa, 0x68, 0x8f, 0xb8, 0x39 } \\r
);\r
\r
typedef struct {\r
- UINT8 Blue;\r
- UINT8 Green;\r
- UINT8 Red;\r
- UINT8 Reserved;\r
+ UINT8 Blue;\r
+ UINT8 Green;\r
+ UINT8 Red;\r
+ UINT8 Reserved;\r
} EFI_UGA_PIXEL;\r
\r
typedef union {\r
- EFI_UGA_PIXEL Pixel;\r
- UINT32 Raw;\r
+ EFI_UGA_PIXEL Pixel;\r
+ UINT32 Raw;\r
} EFI_UGA_PIXEL_UNION;\r
\r
///\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_UGA_DRAW_PROTOCOL_BLT)(\r
- IN EFI_UGA_DRAW_PROTOCOL * This,\r
- IN EFI_UGA_PIXEL * BltBuffer OPTIONAL,\r
+ IN EFI_UGA_DRAW_PROTOCOL *This,\r
+ IN EFI_UGA_PIXEL *BltBuffer OPTIONAL,\r
IN EFI_UGA_BLT_OPERATION BltOperation,\r
IN UINTN SourceX,\r
IN UINTN SourceY,\r
/// copy pixels to and from the graphics controller's frame buffer.\r
///\r
struct _EFI_UGA_DRAW_PROTOCOL {\r
- EFI_UGA_DRAW_PROTOCOL_GET_MODE GetMode;\r
- EFI_UGA_DRAW_PROTOCOL_SET_MODE SetMode;\r
- EFI_UGA_DRAW_PROTOCOL_BLT Blt;\r
+ EFI_UGA_DRAW_PROTOCOL_GET_MODE GetMode;\r
+ EFI_UGA_DRAW_PROTOCOL_SET_MODE SetMode;\r
+ EFI_UGA_DRAW_PROTOCOL_BLT Blt;\r
};\r
\r
-extern EFI_GUID gEfiUgaDrawProtocolGuid;\r
+extern EFI_GUID gEfiUgaDrawProtocolGuid;\r
\r
#endif\r
\r
typedef struct _EFI_UGA_IO_PROTOCOL EFI_UGA_IO_PROTOCOL;\r
\r
-typedef UINT32 UGA_STATUS;\r
+typedef UINT32 UGA_STATUS;\r
\r
typedef enum {\r
- UgaDtParentBus = 1,\r
+ UgaDtParentBus = 1,\r
UgaDtGraphicsController,\r
UgaDtOutputController,\r
UgaDtOutputPort,\r
typedef UINT32 UGA_DEVICE_ID, *PUGA_DEVICE_ID;\r
\r
typedef struct {\r
- UGA_DEVICE_TYPE deviceType;\r
- UGA_DEVICE_ID deviceId;\r
- UINT32 ui32DeviceContextSize;\r
- UINT32 ui32SharedContextSize;\r
+ UGA_DEVICE_TYPE deviceType;\r
+ UGA_DEVICE_ID deviceId;\r
+ UINT32 ui32DeviceContextSize;\r
+ UINT32 ui32SharedContextSize;\r
} UGA_DEVICE_DATA, *PUGA_DEVICE_DATA;\r
\r
typedef struct _UGA_DEVICE {\r
- VOID *pvDeviceContext;\r
- VOID *pvSharedContext;\r
- VOID *pvRunTimeContext;\r
- struct _UGA_DEVICE *pParentDevice;\r
- VOID *pvBusIoServices;\r
- VOID *pvStdIoServices;\r
- UGA_DEVICE_DATA deviceData;\r
+ VOID *pvDeviceContext;\r
+ VOID *pvSharedContext;\r
+ VOID *pvRunTimeContext;\r
+ struct _UGA_DEVICE *pParentDevice;\r
+ VOID *pvBusIoServices;\r
+ VOID *pvStdIoServices;\r
+ UGA_DEVICE_DATA deviceData;\r
} UGA_DEVICE, *PUGA_DEVICE;\r
\r
typedef enum {\r
- UgaIoGetVersion = 1,\r
+ UgaIoGetVersion = 1,\r
UgaIoGetChildDevice,\r
UgaIoStartDevice,\r
UgaIoStopDevice,\r
} UGA_IO_REQUEST_CODE, *PUGA_IO_REQUEST_CODE;\r
\r
typedef struct {\r
- IN UGA_IO_REQUEST_CODE ioRequestCode;\r
- IN VOID *pvInBuffer;\r
- IN UINT64 ui64InBufferSize;\r
- OUT VOID *pvOutBuffer;\r
- IN UINT64 ui64OutBufferSize;\r
- OUT UINT64 ui64BytesReturned;\r
+ IN UGA_IO_REQUEST_CODE ioRequestCode;\r
+ IN VOID *pvInBuffer;\r
+ IN UINT64 ui64InBufferSize;\r
+ OUT VOID *pvOutBuffer;\r
+ IN UINT64 ui64OutBufferSize;\r
+ OUT UINT64 ui64BytesReturned;\r
} UGA_IO_REQUEST, *PUGA_IO_REQUEST;\r
\r
-\r
/**\r
Dynamically allocate storage for a child UGA_DEVICE.\r
\r
OUT UGA_DEVICE **Device\r
);\r
\r
-\r
/**\r
Delete a dynamically allocated child UGA_DEVICE object that was allocated via CreateDevice().\r
\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_UGA_IO_PROTOCOL_DELETE_DEVICE)(\r
- IN EFI_UGA_IO_PROTOCOL * This,\r
- IN UGA_DEVICE * Device\r
+ IN EFI_UGA_IO_PROTOCOL *This,\r
+ IN UGA_DEVICE *Device\r
);\r
\r
/**\r
/// Provides a basic abstraction to send I/O requests to the graphics device and any of its children.\r
///\r
struct _EFI_UGA_IO_PROTOCOL {\r
- EFI_UGA_IO_PROTOCOL_CREATE_DEVICE CreateDevice;\r
- EFI_UGA_IO_PROTOCOL_DELETE_DEVICE DeleteDevice;\r
- PUGA_FW_SERVICE_DISPATCH DispatchService;\r
+ EFI_UGA_IO_PROTOCOL_CREATE_DEVICE CreateDevice;\r
+ EFI_UGA_IO_PROTOCOL_DELETE_DEVICE DeleteDevice;\r
+ PUGA_FW_SERVICE_DISPATCH DispatchService;\r
};\r
\r
-extern EFI_GUID gEfiUgaIoProtocolGuid;\r
+extern EFI_GUID gEfiUgaIoProtocolGuid;\r
\r
//\r
// Data structure that is stored in the EFI Configuration Table with the\r
// EBC UGA drivers.\r
//\r
typedef struct {\r
- UINT32 Version;\r
- UINT32 HeaderSize;\r
- UINT32 SizeOfEntries;\r
- UINT32 NumberOfEntries;\r
+ UINT32 Version;\r
+ UINT32 HeaderSize;\r
+ UINT32 SizeOfEntries;\r
+ UINT32 NumberOfEntries;\r
} EFI_DRIVER_OS_HANDOFF_HEADER;\r
\r
typedef enum {\r
} EFI_DRIVER_HANOFF_ENUM;\r
\r
typedef struct {\r
- EFI_DRIVER_HANOFF_ENUM Type;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
- VOID *PciRomImage;\r
- UINT64 PciRomSize;\r
+ EFI_DRIVER_HANOFF_ENUM Type;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ VOID *PciRomImage;\r
+ UINT64 PciRomSize;\r
} EFI_DRIVER_OS_HANDOFF;\r
\r
#endif\r
0xa4c751fc, 0x23ae, 0x4c3e, {0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49 } \\r
}\r
\r
-typedef struct _EFI_UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL;\r
-\r
+typedef struct _EFI_UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL;\r
\r
///\r
/// Protocol GUID name defined in EFI1.1.\r
///\r
-#define UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL_GUID\r
+#define UNICODE_COLLATION_PROTOCOL EFI_UNICODE_COLLATION_PROTOCOL_GUID\r
\r
///\r
/// Protocol defined in EFI1.1.\r
///\r
-typedef EFI_UNICODE_COLLATION_PROTOCOL UNICODE_COLLATION_INTERFACE;\r
+typedef EFI_UNICODE_COLLATION_PROTOCOL UNICODE_COLLATION_INTERFACE;\r
\r
///\r
/// Protocol data structures and defines\r
///\r
-#define EFI_UNICODE_BYTE_ORDER_MARK (CHAR16) (0xfeff)\r
+#define EFI_UNICODE_BYTE_ORDER_MARK (CHAR16) (0xfeff)\r
\r
//\r
// Protocol member functions\r
//\r
+\r
/**\r
Performs a case-insensitive comparison of two Null-terminated strings.\r
\r
/// comparisons of strings.\r
///\r
struct _EFI_UNICODE_COLLATION_PROTOCOL {\r
- EFI_UNICODE_COLLATION_STRICOLL StriColl;\r
- EFI_UNICODE_COLLATION_METAIMATCH MetaiMatch;\r
- EFI_UNICODE_COLLATION_STRLWR StrLwr;\r
- EFI_UNICODE_COLLATION_STRUPR StrUpr;\r
+ EFI_UNICODE_COLLATION_STRICOLL StriColl;\r
+ EFI_UNICODE_COLLATION_METAIMATCH MetaiMatch;\r
+ EFI_UNICODE_COLLATION_STRLWR StrLwr;\r
+ EFI_UNICODE_COLLATION_STRUPR StrUpr;\r
\r
//\r
// for supporting fat volumes\r
//\r
- EFI_UNICODE_COLLATION_FATTOSTR FatToStr;\r
- EFI_UNICODE_COLLATION_STRTOFAT StrToFat;\r
+ EFI_UNICODE_COLLATION_FATTOSTR FatToStr;\r
+ EFI_UNICODE_COLLATION_STRTOFAT StrToFat;\r
\r
///\r
/// A Null-terminated ASCII string array that contains one or more language codes.\r
/// When this field is used for UnicodeCollation2, it is specified in RFC 4646 format.\r
/// When it is used for UnicodeCollation, it is specified in ISO 639-2 format.\r
///\r
- CHAR8 *SupportedLanguages;\r
+ CHAR8 *SupportedLanguages;\r
};\r
\r
-extern EFI_GUID gEfiUnicodeCollationProtocolGuid;\r
-extern EFI_GUID gEfiUnicodeCollation2ProtocolGuid;\r
+extern EFI_GUID gEfiUnicodeCollationProtocolGuid;\r
+extern EFI_GUID gEfiUnicodeCollation2ProtocolGuid;\r
\r
#endif\r
///\r
typedef struct _EFI_USB2_HC_PROTOCOL EFI_USB2_HC_PROTOCOL;\r
\r
-\r
typedef struct {\r
- UINT16 PortStatus; ///< Contains current port status bitmap.\r
- UINT16 PortChangeStatus; ///< Contains current port status change bitmap.\r
+ UINT16 PortStatus; ///< Contains current port status bitmap.\r
+ UINT16 PortChangeStatus; ///< Contains current port status change bitmap.\r
} EFI_USB_PORT_STATUS;\r
\r
///\r
/// EFI_USB_PORT_STATUS.PortStatus bit definition\r
///\r
-#define USB_PORT_STAT_CONNECTION 0x0001\r
-#define USB_PORT_STAT_ENABLE 0x0002\r
-#define USB_PORT_STAT_SUSPEND 0x0004\r
-#define USB_PORT_STAT_OVERCURRENT 0x0008\r
-#define USB_PORT_STAT_RESET 0x0010\r
-#define USB_PORT_STAT_POWER 0x0100\r
-#define USB_PORT_STAT_LOW_SPEED 0x0200\r
-#define USB_PORT_STAT_HIGH_SPEED 0x0400\r
-#define USB_PORT_STAT_SUPER_SPEED 0x0800\r
-#define USB_PORT_STAT_OWNER 0x2000\r
+#define USB_PORT_STAT_CONNECTION 0x0001\r
+#define USB_PORT_STAT_ENABLE 0x0002\r
+#define USB_PORT_STAT_SUSPEND 0x0004\r
+#define USB_PORT_STAT_OVERCURRENT 0x0008\r
+#define USB_PORT_STAT_RESET 0x0010\r
+#define USB_PORT_STAT_POWER 0x0100\r
+#define USB_PORT_STAT_LOW_SPEED 0x0200\r
+#define USB_PORT_STAT_HIGH_SPEED 0x0400\r
+#define USB_PORT_STAT_SUPER_SPEED 0x0800\r
+#define USB_PORT_STAT_OWNER 0x2000\r
\r
///\r
/// EFI_USB_PORT_STATUS.PortChangeStatus bit definition\r
///\r
-#define USB_PORT_STAT_C_CONNECTION 0x0001\r
-#define USB_PORT_STAT_C_ENABLE 0x0002\r
-#define USB_PORT_STAT_C_SUSPEND 0x0004\r
-#define USB_PORT_STAT_C_OVERCURRENT 0x0008\r
-#define USB_PORT_STAT_C_RESET 0x0010\r
-\r
+#define USB_PORT_STAT_C_CONNECTION 0x0001\r
+#define USB_PORT_STAT_C_ENABLE 0x0002\r
+#define USB_PORT_STAT_C_SUSPEND 0x0004\r
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008\r
+#define USB_PORT_STAT_C_RESET 0x0010\r
\r
///\r
/// Usb port features value\r
EfiUsbPortResetChange = 20\r
} EFI_USB_PORT_FEATURE;\r
\r
-#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
-#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
-#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
-#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
+#define EFI_USB_SPEED_FULL 0x0000 ///< 12 Mb/s, USB 1.1 OHCI and UHCI HC.\r
+#define EFI_USB_SPEED_LOW 0x0001 ///< 1 Mb/s, USB 1.1 OHCI and UHCI HC.\r
+#define EFI_USB_SPEED_HIGH 0x0002 ///< 480 Mb/s, USB 2.0 EHCI HC.\r
+#define EFI_USB_SPEED_SUPER 0x0003 ///< 4.8 Gb/s, USB 3.0 XHCI HC.\r
\r
typedef struct {\r
- UINT8 TranslatorHubAddress; ///< device address\r
- UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to.\r
+ UINT8 TranslatorHubAddress; ///< device address\r
+ UINT8 TranslatorPortNumber; ///< the port number of the hub that device is connected to.\r
} EFI_USB2_HC_TRANSACTION_TRANSLATOR;\r
\r
//\r
#define EFI_USB_HC_RESET_HOST_CONTROLLER 0x0002\r
#define EFI_USB_HC_RESET_GLOBAL_WITH_DEBUG 0x0004\r
#define EFI_USB_HC_RESET_HOST_WITH_DEBUG 0x0008\r
+\r
/**\r
Provides software reset for the USB host controller.\r
\r
(EFIAPI *EFI_USB2_HC_PROTOCOL_GET_STATE)(\r
IN EFI_USB2_HC_PROTOCOL *This,\r
OUT EFI_USB_HC_STATE *State\r
-);\r
+ );\r
\r
/**\r
Sets the USB host controller to a specific state.\r
OUT UINT32 *TransferResult\r
);\r
\r
-#define EFI_USB_MAX_BULK_BUFFER_NUM 10\r
+#define EFI_USB_MAX_BULK_BUFFER_NUM 10\r
\r
/**\r
Submits bulk transfer to a bulk endpoint of a USB device.\r
OUT UINT32 *TransferResult\r
);\r
\r
-#define EFI_USB_MAX_ISO_BUFFER_NUM 7\r
-#define EFI_USB_MAX_ISO_BUFFER_NUM1 2\r
+#define EFI_USB_MAX_ISO_BUFFER_NUM 7\r
+#define EFI_USB_MAX_ISO_BUFFER_NUM1 2\r
\r
/**\r
Submits isochronous transfer to an isochronous endpoint of a USB device.\r
/// instance, and an EFI_USB2_HC_PROTOCOL instance.\r
///\r
struct _EFI_USB2_HC_PROTOCOL {\r
- EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability;\r
- EFI_USB2_HC_PROTOCOL_RESET Reset;\r
- EFI_USB2_HC_PROTOCOL_GET_STATE GetState;\r
- EFI_USB2_HC_PROTOCOL_SET_STATE SetState;\r
- EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;\r
- EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;\r
- EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;\r
- EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;\r
- EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;\r
- EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;\r
- EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;\r
- EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;\r
- EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;\r
+ EFI_USB2_HC_PROTOCOL_GET_CAPABILITY GetCapability;\r
+ EFI_USB2_HC_PROTOCOL_RESET Reset;\r
+ EFI_USB2_HC_PROTOCOL_GET_STATE GetState;\r
+ EFI_USB2_HC_PROTOCOL_SET_STATE SetState;\r
+ EFI_USB2_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;\r
+ EFI_USB2_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;\r
+ EFI_USB2_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;\r
+ EFI_USB2_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;\r
+ EFI_USB2_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;\r
+ EFI_USB2_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;\r
+ EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;\r
+ EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;\r
+ EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;\r
\r
///\r
/// The major revision number of the USB host controller. The revision information\r
/// indicates the release of the Universal Serial Bus Specification with which the\r
/// host controller is compliant.\r
///\r
- UINT16 MajorRevision;\r
+ UINT16 MajorRevision;\r
\r
///\r
/// The minor revision number of the USB host controller. The revision information\r
/// indicates the release of the Universal Serial Bus Specification with which the\r
/// host controller is compliant.\r
///\r
- UINT16 MinorRevision;\r
+ UINT16 MinorRevision;\r
};\r
\r
-extern EFI_GUID gEfiUsb2HcProtocolGuid;\r
+extern EFI_GUID gEfiUsb2HcProtocolGuid;\r
\r
#endif\r
0x32d2963a, 0xfe5d, 0x4f30, {0xb6, 0x33, 0x6e, 0x5d, 0xc5, 0x58, 0x3, 0xcc} \\r
}\r
\r
-typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL;\r
+typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL;\r
\r
-#define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001\r
+#define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010001\r
\r
typedef enum _EFI_USBFN_PORT_TYPE {\r
EfiUsbUnknownPort = 0,\r
} EFI_USBFN_PORT_TYPE;\r
\r
typedef struct {\r
- EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;\r
- EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;\r
+ EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;\r
+ EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;\r
} EFI_USB_INTERFACE_INFO;\r
\r
typedef struct {\r
- EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;\r
- EFI_USB_INTERFACE_INFO **InterfaceInfoTable;\r
+ EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;\r
+ EFI_USB_INTERFACE_INFO **InterfaceInfoTable;\r
} EFI_USB_CONFIG_INFO;\r
\r
typedef struct {\r
- EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;\r
- EFI_USB_CONFIG_INFO **ConfigInfoTable;\r
+ EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;\r
+ EFI_USB_CONFIG_INFO **ConfigInfoTable;\r
} EFI_USB_DEVICE_INFO;\r
\r
typedef enum _EFI_USB_ENDPOINT_TYPE {\r
UsbEndpointControl = 0x00,\r
- //UsbEndpointIsochronous = 0x01,\r
+ // UsbEndpointIsochronous = 0x01,\r
UsbEndpointBulk = 0x02,\r
- //UsbEndpointInterrupt = 0x03\r
+ // UsbEndpointInterrupt = 0x03\r
} EFI_USB_ENDPOINT_TYPE;\r
\r
typedef enum _EFI_USBFN_DEVICE_INFO_ID {\r
} EFI_USBFN_TRANSFER_STATUS;\r
\r
typedef struct _EFI_USBFN_TRANSFER_RESULT {\r
- UINTN BytesTransferred;\r
- EFI_USBFN_TRANSFER_STATUS TransferStatus;\r
- UINT8 EndpointIndex;\r
- EFI_USBFN_ENDPOINT_DIRECTION Direction;\r
- VOID *Buffer;\r
+ UINTN BytesTransferred;\r
+ EFI_USBFN_TRANSFER_STATUS TransferStatus;\r
+ UINT8 EndpointIndex;\r
+ EFI_USBFN_ENDPOINT_DIRECTION Direction;\r
+ VOID *Buffer;\r
} EFI_USBFN_TRANSFER_RESULT;\r
\r
typedef enum _EFI_USB_BUS_SPEED {\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_DETECT_PORT) (\r
+(EFIAPI *EFI_USBFN_IO_DETECT_PORT)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
- OUT EFI_USBFN_PORT_TYPE *PortType\r
+ OUT EFI_USBFN_PORT_TYPE *PortType\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (\r
+(EFIAPI *EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
- OUT EFI_USB_DEVICE_INFO *DeviceInfo\r
+ OUT EFI_USB_DEVICE_INFO *DeviceInfo\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (\r
+(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN EFI_USB_ENDPOINT_TYPE EndpointType,\r
IN EFI_USB_BUS_SPEED BusSpeed,\r
- OUT UINT16 *MaxPacketSize\r
+ OUT UINT16 *MaxPacketSize\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_DEVICE_INFO) (\r
+(EFIAPI *EFI_USBFN_IO_GET_DEVICE_INFO)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN EFI_USBFN_DEVICE_INFO_ID Id,\r
IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer OPTIONAL\r
-);\r
+ OUT VOID *Buffer OPTIONAL\r
+ );\r
\r
/**\r
Returns the vendor-id and product-id of the device.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (\r
+(EFIAPI *EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
- OUT UINT16 *Vid,\r
- OUT UINT16 *Pid\r
-);\r
+ OUT UINT16 *Vid,\r
+ OUT UINT16 *Pid\r
+ );\r
\r
/**\r
Aborts the transfer on the specified endpoint.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_ABORT_TRANSFER) (\r
+(EFIAPI *EFI_USBFN_IO_ABORT_TRANSFER)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction\r
-);\r
+ );\r
\r
/**\r
Returns the stall state on the specified endpoint.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (\r
+(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,\r
IN OUT BOOLEAN *State\r
-);\r
+ );\r
\r
/**\r
Sets or clears the stall state on the specified endpoint.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (\r
+(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,\r
IN OUT BOOLEAN *State\r
-);\r
+ );\r
\r
/**\r
This function is called repeatedly to get information on USB bus states,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_EVENTHANDLER) (\r
+(EFIAPI *EFI_USBFN_IO_EVENTHANDLER)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
- OUT EFI_USBFN_MESSAGE *Message,\r
+ OUT EFI_USBFN_MESSAGE *Message,\r
IN OUT UINTN *PayloadSize,\r
- OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload\r
-);\r
+ OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload\r
+ );\r
\r
/**\r
This function handles transferring data to or from the host on the specified\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_TRANSFER) (\r
+(EFIAPI *EFI_USBFN_IO_TRANSFER)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,\r
IN OUT UINTN *BufferSize,\r
IN OUT VOID *Buffer\r
-);\r
+ );\r
\r
/**\r
Returns the maximum supported transfer size.\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (\r
+(EFIAPI *EFI_USBFN_IO_GET_MAXTRANSFER_SIZE)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
- OUT UINTN *MaxTransferSize\r
+ OUT UINTN *MaxTransferSize\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (\r
+(EFIAPI *EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINTN Size,\r
- OUT VOID **Buffer\r
+ OUT VOID **Buffer\r
);\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (\r
+(EFIAPI *EFI_USBFN_IO_FREE_TRANSFER_BUFFER)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN VOID *Buffer\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_START_CONTROLLER) (\r
+(EFIAPI *EFI_USBFN_IO_START_CONTROLLER)(\r
IN EFI_USBFN_IO_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_STOP_CONTROLLER) (\r
+(EFIAPI *EFI_USBFN_IO_STOP_CONTROLLER)(\r
IN EFI_USBFN_IO_PROTOCOL *This\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_POLICY) (\r
+(EFIAPI *EFI_USBFN_IO_SET_ENDPOINT_POLICY)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_POLICY) (\r
+(EFIAPI *EFI_USBFN_IO_GET_ENDPOINT_POLICY)(\r
IN EFI_USBFN_IO_PROTOCOL *This,\r
IN UINT8 EndpointIndex,\r
IN EFI_USBFN_ENDPOINT_DIRECTION Direction,\r
/// controller management for a USB Function port.\r
///\r
struct _EFI_USBFN_IO_PROTOCOL {\r
- UINT32 Revision;\r
- EFI_USBFN_IO_DETECT_PORT DetectPort;\r
- EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints;\r
- EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize;\r
- EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;\r
- EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId;\r
- EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;\r
- EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState;\r
- EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState;\r
- EFI_USBFN_IO_EVENTHANDLER EventHandler;\r
- EFI_USBFN_IO_TRANSFER Transfer;\r
- EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize;\r
- EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;\r
- EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;\r
- EFI_USBFN_IO_START_CONTROLLER StartController;\r
- EFI_USBFN_IO_STOP_CONTROLLER StopController;\r
- EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;\r
- EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;\r
+ UINT32 Revision;\r
+ EFI_USBFN_IO_DETECT_PORT DetectPort;\r
+ EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints;\r
+ EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize;\r
+ EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;\r
+ EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId;\r
+ EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;\r
+ EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState;\r
+ EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState;\r
+ EFI_USBFN_IO_EVENTHANDLER EventHandler;\r
+ EFI_USBFN_IO_TRANSFER Transfer;\r
+ EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize;\r
+ EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;\r
+ EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;\r
+ EFI_USBFN_IO_START_CONTROLLER StartController;\r
+ EFI_USBFN_IO_STOP_CONTROLLER StopController;\r
+ EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;\r
+ EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;\r
};\r
\r
-extern EFI_GUID gEfiUsbFunctionIoProtocolGuid;\r
+extern EFI_GUID gEfiUsbFunctionIoProtocolGuid;\r
\r
#endif\r
-\r
IN EFI_USB_PORT_FEATURE PortFeature\r
);\r
\r
-\r
///\r
/// The EFI_USB_HC_PROTOCOL provides USB host controller management, basic data transactions\r
/// over a USB bus, and USB root hub access. A device driver that wishes to manage a USB bus in a\r
/// EFI_DEVICE_PATH_PROTOCOL instance, and an EFI_USB_HC_PROTOCOL instance.\r
///\r
struct _EFI_USB_HC_PROTOCOL {\r
- EFI_USB_HC_PROTOCOL_RESET Reset;\r
- EFI_USB_HC_PROTOCOL_GET_STATE GetState;\r
- EFI_USB_HC_PROTOCOL_SET_STATE SetState;\r
- EFI_USB_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;\r
- EFI_USB_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;\r
- EFI_USB_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;\r
- EFI_USB_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;\r
- EFI_USB_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;\r
- EFI_USB_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;\r
- EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_NUMBER GetRootHubPortNumber;\r
- EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;\r
- EFI_USB_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;\r
- EFI_USB_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;\r
+ EFI_USB_HC_PROTOCOL_RESET Reset;\r
+ EFI_USB_HC_PROTOCOL_GET_STATE GetState;\r
+ EFI_USB_HC_PROTOCOL_SET_STATE SetState;\r
+ EFI_USB_HC_PROTOCOL_CONTROL_TRANSFER ControlTransfer;\r
+ EFI_USB_HC_PROTOCOL_BULK_TRANSFER BulkTransfer;\r
+ EFI_USB_HC_PROTOCOL_ASYNC_INTERRUPT_TRANSFER AsyncInterruptTransfer;\r
+ EFI_USB_HC_PROTOCOL_SYNC_INTERRUPT_TRANSFER SyncInterruptTransfer;\r
+ EFI_USB_HC_PROTOCOL_ISOCHRONOUS_TRANSFER IsochronousTransfer;\r
+ EFI_USB_HC_PROTOCOL_ASYNC_ISOCHRONOUS_TRANSFER AsyncIsochronousTransfer;\r
+ EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_NUMBER GetRootHubPortNumber;\r
+ EFI_USB_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS GetRootHubPortStatus;\r
+ EFI_USB_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE SetRootHubPortFeature;\r
+ EFI_USB_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE ClearRootHubPortFeature;\r
///\r
/// The major revision number of the USB host controller. The revision information\r
/// indicates the release of the Universal Serial Bus Specification with which the\r
/// host controller is compliant.\r
///\r
- UINT16 MajorRevision;\r
+ UINT16 MajorRevision;\r
///\r
/// The minor revision number of the USB host controller. The revision information\r
/// indicates the release of the Universal Serial Bus Specification with which the\r
/// host controller is compliant.\r
///\r
- UINT16 MinorRevision;\r
+ UINT16 MinorRevision;\r
};\r
\r
-extern EFI_GUID gEfiUsbHcProtocolGuid;\r
+extern EFI_GUID gEfiUsbHcProtocolGuid;\r
\r
#endif\r
0x2B2F68D6, 0x0CD2, 0x44cf, {0x8E, 0x8B, 0xBB, 0xA2, 0x0B, 0x1B, 0x5B, 0x75 } \\r
}\r
\r
-typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL;\r
+typedef struct _EFI_USB_IO_PROTOCOL EFI_USB_IO_PROTOCOL;\r
\r
//\r
// Related Definition for EFI USB I/O protocol\r
//\r
// USB standard descriptors and reqeust\r
//\r
-typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;\r
-typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;\r
-typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;\r
-typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;\r
-typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;\r
+typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;\r
+typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;\r
+typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;\r
+typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;\r
+typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;\r
\r
///\r
/// USB data transfer direction\r
//\r
// USB Transfer Results\r
//\r
-#define EFI_USB_NOERROR 0x00\r
-#define EFI_USB_ERR_NOTEXECUTE 0x01\r
-#define EFI_USB_ERR_STALL 0x02\r
-#define EFI_USB_ERR_BUFFER 0x04\r
-#define EFI_USB_ERR_BABBLE 0x08\r
-#define EFI_USB_ERR_NAK 0x10\r
-#define EFI_USB_ERR_CRC 0x20\r
-#define EFI_USB_ERR_TIMEOUT 0x40\r
-#define EFI_USB_ERR_BITSTUFF 0x80\r
-#define EFI_USB_ERR_SYSTEM 0x100\r
+#define EFI_USB_NOERROR 0x00\r
+#define EFI_USB_ERR_NOTEXECUTE 0x01\r
+#define EFI_USB_ERR_STALL 0x02\r
+#define EFI_USB_ERR_BUFFER 0x04\r
+#define EFI_USB_ERR_BABBLE 0x08\r
+#define EFI_USB_ERR_NAK 0x10\r
+#define EFI_USB_ERR_CRC 0x20\r
+#define EFI_USB_ERR_TIMEOUT 0x40\r
+#define EFI_USB_ERR_BITSTUFF 0x80\r
+#define EFI_USB_ERR_SYSTEM 0x100\r
\r
/**\r
Async USB transfer callback routine.\r
// Prototype for EFI USB I/O protocol\r
//\r
\r
-\r
/**\r
This function is used to manage a USB device with a control transfer pipe. A control transfer is\r
typically used to perform device initialization and configuration.\r
//\r
// IO transfer\r
//\r
- EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer;\r
- EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer;\r
- EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer;\r
- EFI_USB_IO_SYNC_INTERRUPT_TRANSFER UsbSyncInterruptTransfer;\r
- EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer;\r
- EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer;\r
+ EFI_USB_IO_CONTROL_TRANSFER UsbControlTransfer;\r
+ EFI_USB_IO_BULK_TRANSFER UsbBulkTransfer;\r
+ EFI_USB_IO_ASYNC_INTERRUPT_TRANSFER UsbAsyncInterruptTransfer;\r
+ EFI_USB_IO_SYNC_INTERRUPT_TRANSFER UsbSyncInterruptTransfer;\r
+ EFI_USB_IO_ISOCHRONOUS_TRANSFER UsbIsochronousTransfer;\r
+ EFI_USB_IO_ASYNC_ISOCHRONOUS_TRANSFER UsbAsyncIsochronousTransfer;\r
\r
//\r
// Common device request\r
//\r
- EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor;\r
- EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor;\r
- EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor;\r
- EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor;\r
- EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor;\r
- EFI_USB_IO_GET_SUPPORTED_LANGUAGE UsbGetSupportedLanguages;\r
+ EFI_USB_IO_GET_DEVICE_DESCRIPTOR UsbGetDeviceDescriptor;\r
+ EFI_USB_IO_GET_CONFIG_DESCRIPTOR UsbGetConfigDescriptor;\r
+ EFI_USB_IO_GET_INTERFACE_DESCRIPTOR UsbGetInterfaceDescriptor;\r
+ EFI_USB_IO_GET_ENDPOINT_DESCRIPTOR UsbGetEndpointDescriptor;\r
+ EFI_USB_IO_GET_STRING_DESCRIPTOR UsbGetStringDescriptor;\r
+ EFI_USB_IO_GET_SUPPORTED_LANGUAGE UsbGetSupportedLanguages;\r
\r
//\r
// Reset controller's parent port\r
//\r
- EFI_USB_IO_PORT_RESET UsbPortReset;\r
+ EFI_USB_IO_PORT_RESET UsbPortReset;\r
};\r
\r
-extern EFI_GUID gEfiUsbIoProtocolGuid;\r
+extern EFI_GUID gEfiUsbIoProtocolGuid;\r
\r
#endif\r
0x71ee5e94, 0x65b9, 0x45d5, { 0x82, 0x1a, 0x3a, 0x4d, 0x86, 0xcf, 0xe6, 0xbe } \\r
}\r
\r
-typedef struct _EFI_USER_CREDENTIAL_PROTOCOL EFI_USER_CREDENTIAL_PROTOCOL;\r
+typedef struct _EFI_USER_CREDENTIAL_PROTOCOL EFI_USER_CREDENTIAL_PROTOCOL;\r
\r
/**\r
Enroll a user on a credential provider.\r
/// This protocol provides support for a single class of credentials\r
///\r
struct _EFI_USER_CREDENTIAL_PROTOCOL {\r
- EFI_GUID Identifier; ///< Uniquely identifies this credential provider.\r
- EFI_GUID Type; ///< Identifies this class of User Credential Provider.\r
- EFI_CREDENTIAL_ENROLL Enroll;\r
- EFI_CREDENTIAL_FORM Form;\r
- EFI_CREDENTIAL_TILE Tile;\r
- EFI_CREDENTIAL_TITLE Title;\r
- EFI_CREDENTIAL_USER User;\r
- EFI_CREDENTIAL_SELECT Select;\r
- EFI_CREDENTIAL_DESELECT Deselect;\r
- EFI_CREDENTIAL_DEFAULT Default;\r
- EFI_CREDENTIAL_GET_INFO GetInfo;\r
- EFI_CREDENTIAL_GET_NEXT_INFO GetNextInfo;\r
- EFI_CREDENTIAL_CAPABILITIES Capabilities;\r
+ EFI_GUID Identifier; ///< Uniquely identifies this credential provider.\r
+ EFI_GUID Type; ///< Identifies this class of User Credential Provider.\r
+ EFI_CREDENTIAL_ENROLL Enroll;\r
+ EFI_CREDENTIAL_FORM Form;\r
+ EFI_CREDENTIAL_TILE Tile;\r
+ EFI_CREDENTIAL_TITLE Title;\r
+ EFI_CREDENTIAL_USER User;\r
+ EFI_CREDENTIAL_SELECT Select;\r
+ EFI_CREDENTIAL_DESELECT Deselect;\r
+ EFI_CREDENTIAL_DEFAULT Default;\r
+ EFI_CREDENTIAL_GET_INFO GetInfo;\r
+ EFI_CREDENTIAL_GET_NEXT_INFO GetNextInfo;\r
+ EFI_CREDENTIAL_CAPABILITIES Capabilities;\r
};\r
\r
-extern EFI_GUID gEfiUserCredentialProtocolGuid;\r
+extern EFI_GUID gEfiUserCredentialProtocolGuid;\r
\r
#endif\r
0xe98adb03, 0xb8b9, 0x4af8, { 0xba, 0x20, 0x26, 0xe9, 0x11, 0x4c, 0xbc, 0xe5 } \\r
}\r
\r
-typedef struct _EFI_USER_CREDENTIAL2_PROTOCOL EFI_USER_CREDENTIAL2_PROTOCOL;\r
+typedef struct _EFI_USER_CREDENTIAL2_PROTOCOL EFI_USER_CREDENTIAL2_PROTOCOL;\r
\r
/**\r
Enroll a user on a credential provider.\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CREDENTIAL2_DELETE)(\r
- IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This,\r
- IN EFI_USER_PROFILE_HANDLE User\r
-);\r
+ IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This,\r
+ IN EFI_USER_PROFILE_HANDLE User\r
+ );\r
\r
///\r
/// This protocol provides support for a single class of credentials\r
///\r
struct _EFI_USER_CREDENTIAL2_PROTOCOL {\r
- EFI_GUID Identifier; ///< Uniquely identifies this credential provider.\r
- EFI_GUID Type; ///< Identifies this class of User Credential Provider.\r
- EFI_CREDENTIAL2_ENROLL Enroll;\r
- EFI_CREDENTIAL2_FORM Form;\r
- EFI_CREDENTIAL2_TILE Tile;\r
- EFI_CREDENTIAL2_TITLE Title;\r
- EFI_CREDENTIAL2_USER User;\r
- EFI_CREDENTIAL2_SELECT Select;\r
- EFI_CREDENTIAL2_DESELECT Deselect;\r
- EFI_CREDENTIAL2_DEFAULT Default;\r
- EFI_CREDENTIAL2_GET_INFO GetInfo;\r
- EFI_CREDENTIAL2_GET_NEXT_INFO GetNextInfo;\r
- EFI_CREDENTIAL_CAPABILITIES Capabilities;\r
- EFI_CREDENTIAL2_DELETE Delete;\r
+ EFI_GUID Identifier; ///< Uniquely identifies this credential provider.\r
+ EFI_GUID Type; ///< Identifies this class of User Credential Provider.\r
+ EFI_CREDENTIAL2_ENROLL Enroll;\r
+ EFI_CREDENTIAL2_FORM Form;\r
+ EFI_CREDENTIAL2_TILE Tile;\r
+ EFI_CREDENTIAL2_TITLE Title;\r
+ EFI_CREDENTIAL2_USER User;\r
+ EFI_CREDENTIAL2_SELECT Select;\r
+ EFI_CREDENTIAL2_DESELECT Deselect;\r
+ EFI_CREDENTIAL2_DEFAULT Default;\r
+ EFI_CREDENTIAL2_GET_INFO GetInfo;\r
+ EFI_CREDENTIAL2_GET_NEXT_INFO GetNextInfo;\r
+ EFI_CREDENTIAL_CAPABILITIES Capabilities;\r
+ EFI_CREDENTIAL2_DELETE Delete;\r
};\r
\r
-extern EFI_GUID gEfiUserCredential2ProtocolGuid;\r
+extern EFI_GUID gEfiUserCredential2ProtocolGuid;\r
\r
#endif\r
0xbaf1e6de, 0x209e, 0x4adb, { 0x8d, 0x96, 0xfd, 0x8b, 0x71, 0xf3, 0xf6, 0x83 } \\r
}\r
\r
-typedef VOID *EFI_USER_PROFILE_HANDLE;\r
-typedef VOID *EFI_USER_INFO_HANDLE;\r
+typedef VOID *EFI_USER_PROFILE_HANDLE;\r
+typedef VOID *EFI_USER_INFO_HANDLE;\r
\r
///\r
/// The attributes of the user profile information.\r
///\r
typedef UINT16 EFI_USER_INFO_ATTRIBS;\r
-#define EFI_USER_INFO_STORAGE 0x000F\r
-#define EFI_USER_INFO_STORAGE_VOLATILE 0x0000\r
-#define EFI_USER_INFO_STORAGE_CREDENTIAL_NV 0x0001\r
-#define EFI_USER_INFO_STORAGE_PLATFORM_NV 0x0002\r
+#define EFI_USER_INFO_STORAGE 0x000F\r
+#define EFI_USER_INFO_STORAGE_VOLATILE 0x0000\r
+#define EFI_USER_INFO_STORAGE_CREDENTIAL_NV 0x0001\r
+#define EFI_USER_INFO_STORAGE_PLATFORM_NV 0x0002\r
\r
-#define EFI_USER_INFO_ACCESS 0x0070\r
-#define EFI_USER_INFO_PUBLIC 0x0010\r
-#define EFI_USER_INFO_PRIVATE 0x0020\r
-#define EFI_USER_INFO_PROTECTED 0x0030\r
-#define EFI_USER_INFO_EXCLUSIVE 0x0080\r
+#define EFI_USER_INFO_ACCESS 0x0070\r
+#define EFI_USER_INFO_PUBLIC 0x0010\r
+#define EFI_USER_INFO_PRIVATE 0x0020\r
+#define EFI_USER_INFO_PROTECTED 0x0030\r
+#define EFI_USER_INFO_EXCLUSIVE 0x0080\r
\r
///\r
/// User information structure\r
/// The user credential identifier associated with this user information or else Nil if the\r
/// information is not associated with any specific credential.\r
///\r
- EFI_GUID Credential;\r
+ EFI_GUID Credential;\r
///\r
/// The type of user information.\r
///\r
- UINT8 InfoType;\r
+ UINT8 InfoType;\r
///\r
/// Must be set to 0.\r
///\r
- UINT8 Reserved1;\r
+ UINT8 Reserved1;\r
///\r
/// The attributes of the user profile information.\r
///\r
- EFI_USER_INFO_ATTRIBS InfoAttribs;\r
+ EFI_USER_INFO_ATTRIBS InfoAttribs;\r
///\r
/// The size of the user information, in bytes, including this header.\r
///\r
- UINT32 InfoSize;\r
+ UINT32 InfoSize;\r
} EFI_USER_INFO;\r
\r
///\r
#define EFI_USER_CREDENTIAL_CLASS_SECURE_CARD \\r
{ 0x8a6b4a83, 0x42fe, 0x45d2, { 0xa2, 0xef, 0x46, 0xf0, 0x6c, 0x7d, 0x98, 0x52 } }\r
\r
-typedef UINT64 EFI_CREDENTIAL_CAPABILITIES;\r
+typedef UINT64 EFI_CREDENTIAL_CAPABILITIES;\r
#define EFI_CREDENTIAL_CAPABILITIES_ENROLL 0x0000000000000001\r
\r
///\r
/// Credential logon flags\r
///\r
typedef UINT32 EFI_CREDENTIAL_LOGON_FLAGS;\r
-#define EFI_CREDENTIAL_LOGON_FLAG_AUTO 0x00000001\r
-#define EFI_CREDENTIAL_LOGON_FLAG_DEFAULT 0x00000002\r
+#define EFI_CREDENTIAL_LOGON_FLAG_AUTO 0x00000001\r
+#define EFI_CREDENTIAL_LOGON_FLAG_DEFAULT 0x00000002\r
\r
///\r
/// User information record types\r
///\r
/// No information.\r
///\r
-#define EFI_USER_INFO_EMPTY_RECORD 0x00\r
+#define EFI_USER_INFO_EMPTY_RECORD 0x00\r
///\r
/// Provide the user's name for the enrolled user.\r
///\r
-#define EFI_USER_INFO_NAME_RECORD 0x01\r
+#define EFI_USER_INFO_NAME_RECORD 0x01\r
typedef CHAR16 *EFI_USER_INFO_NAME;\r
///\r
/// Provides the date and time when the user profile was created.\r
///\r
-#define EFI_USER_INFO_CREATE_DATE_RECORD 0x02\r
+#define EFI_USER_INFO_CREATE_DATE_RECORD 0x02\r
typedef EFI_TIME EFI_USER_INFO_CREATE_DATE;\r
///\r
/// Provides the date and time when the user profile was selected.\r
///\r
-#define EFI_USER_INFO_USAGE_DATE_RECORD 0x03\r
+#define EFI_USER_INFO_USAGE_DATE_RECORD 0x03\r
typedef EFI_TIME EFI_USER_INFO_USAGE_DATE;\r
///\r
/// Provides the number of times that the user profile has been selected.\r
///\r
-#define EFI_USER_INFO_USAGE_COUNT_RECORD 0x04\r
+#define EFI_USER_INFO_USAGE_COUNT_RECORD 0x04\r
typedef UINT64 EFI_USER_INFO_USAGE_COUNT;\r
///\r
/// Provides a unique non-volatile user identifier for each enrolled user.\r
///\r
-#define EFI_USER_INFO_IDENTIFIER_RECORD 0x05\r
+#define EFI_USER_INFO_IDENTIFIER_RECORD 0x05\r
typedef UINT8 EFI_USER_INFO_IDENTIFIER[16];\r
///\r
/// Specifies the type of a particular credential associated with the user profile.\r
///\r
-#define EFI_USER_INFO_CREDENTIAL_TYPE_RECORD 0x06\r
+#define EFI_USER_INFO_CREDENTIAL_TYPE_RECORD 0x06\r
typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_TYPE;\r
///\r
/// Specifies the user-readable name of a particular credential type.\r
///\r
-#define EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD 0x07\r
+#define EFI_USER_INFO_CREDENTIAL_TYPE_NAME_RECORD 0x07\r
typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_TYPE_NAME;\r
///\r
/// Specifies the credential provider.\r
///\r
-#define EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD 0x08\r
+#define EFI_USER_INFO_CREDENTIAL_PROVIDER_RECORD 0x08\r
typedef EFI_GUID EFI_USER_INFO_CREDENTIAL_PROVIDER;\r
///\r
/// Specifies the user-readable name of a particular credential's provider.\r
///\r
-#define EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD 0x09\r
+#define EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME_RECORD 0x09\r
typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME;\r
///\r
/// Provides PKCS#11 credential information from a smart card.\r
///\r
-#define EFI_USER_INFO_PKCS11_RECORD 0x0A\r
+#define EFI_USER_INFO_PKCS11_RECORD 0x0A\r
///\r
/// Provides standard biometric information in the format specified by the ISO 19785 (Common\r
/// Biometric Exchange Formats Framework) specification.\r
///\r
-#define EFI_USER_INFO_CBEFF_RECORD 0x0B\r
+#define EFI_USER_INFO_CBEFF_RECORD 0x0B\r
typedef VOID *EFI_USER_INFO_CBEFF;\r
///\r
/// Indicates how close of a match the fingerprint must be in order to be considered a match.\r
///\r
-#define EFI_USER_INFO_FAR_RECORD 0x0C\r
+#define EFI_USER_INFO_FAR_RECORD 0x0C\r
typedef UINT8 EFI_USER_INFO_FAR;\r
///\r
/// Indicates how many attempts the user has to with a particular credential before the system prevents\r
/// further attempts.\r
///\r
-#define EFI_USER_INFO_RETRY_RECORD 0x0D\r
+#define EFI_USER_INFO_RETRY_RECORD 0x0D\r
typedef UINT8 EFI_USER_INFO_RETRY;\r
///\r
/// Provides the user's pre-OS access rights.\r
///\r
-#define EFI_USER_INFO_ACCESS_POLICY_RECORD 0x0E\r
+#define EFI_USER_INFO_ACCESS_POLICY_RECORD 0x0E\r
\r
typedef struct {\r
- UINT32 Type; ///< Specifies the type of user access control.\r
- UINT32 Size; ///< Specifies the size of the user access control record, in bytes, including this header.\r
+ UINT32 Type; ///< Specifies the type of user access control.\r
+ UINT32 Size; ///< Specifies the size of the user access control record, in bytes, including this header.\r
} EFI_USER_INFO_ACCESS_CONTROL;\r
\r
typedef EFI_USER_INFO_ACCESS_CONTROL EFI_USER_INFO_ACCESS_POLICY;\r
/// Forbids the user from booting or loading executables from the specified device path or any child\r
/// device paths.\r
///\r
-#define EFI_USER_INFO_ACCESS_FORBID_LOAD 0x00000001\r
+#define EFI_USER_INFO_ACCESS_FORBID_LOAD 0x00000001\r
///\r
/// Permits the user from booting or loading executables from the specified device path or any child\r
/// device paths.\r
/// The definition EFI_USER_INFO_ACCESS_PERMIT_BOOT in the specification should be typo and wait for\r
/// spec update.\r
///\r
-#define EFI_USER_INFO_ACCESS_PERMIT_LOAD 0x00000002\r
+#define EFI_USER_INFO_ACCESS_PERMIT_LOAD 0x00000002\r
///\r
/// Presence of this record indicates that a user can update enrollment information.\r
///\r
-#define EFI_USER_INFO_ACCESS_ENROLL_SELF 0x00000003\r
+#define EFI_USER_INFO_ACCESS_ENROLL_SELF 0x00000003\r
///\r
/// Presence of this record indicates that a user can enroll new users.\r
///\r
-#define EFI_USER_INFO_ACCESS_ENROLL_OTHERS 0x00000004\r
+#define EFI_USER_INFO_ACCESS_ENROLL_OTHERS 0x00000004\r
///\r
/// Presence of this record indicates that a user can update the user information of any user.\r
///\r
-#define EFI_USER_INFO_ACCESS_MANAGE 0x00000005\r
+#define EFI_USER_INFO_ACCESS_MANAGE 0x00000005\r
///\r
/// Describes permissions usable when configuring the platform.\r
///\r
-#define EFI_USER_INFO_ACCESS_SETUP 0x00000006\r
+#define EFI_USER_INFO_ACCESS_SETUP 0x00000006\r
///\r
/// Standard GUIDs for access to configure the platform.\r
///\r
///\r
/// Forbids UEFI drivers from being started from the specified device path(s) or any child device paths.\r
///\r
-#define EFI_USER_INFO_ACCESS_FORBID_CONNECT 0x00000007\r
+#define EFI_USER_INFO_ACCESS_FORBID_CONNECT 0x00000007\r
///\r
/// Permits UEFI drivers to be started on the specified device path(s) or any child device paths.\r
///\r
-#define EFI_USER_INFO_ACCESS_PERMIT_CONNECT 0x00000008\r
+#define EFI_USER_INFO_ACCESS_PERMIT_CONNECT 0x00000008\r
///\r
/// Modifies the boot order.\r
///\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER 0x00000009\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER 0x00000009\r
typedef UINT32 EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR;\r
\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER_MASK 0x0000000F\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER_MASK 0x0000000F\r
///\r
/// Insert new boot options at the beginning of the boot order.\r
///\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER_INSERT 0x00000000\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER_INSERT 0x00000000\r
///\r
/// Append new boot options to the end of the boot order.\r
///\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER_APPEND 0x00000001\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER_APPEND 0x00000001\r
///\r
/// Replace the entire boot order.\r
///\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE 0x00000002\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE 0x00000002\r
///\r
/// The Boot Manager will not attempt find a default boot device\r
/// when the default boot order is does not lead to a bootable device.\r
///\r
-#define EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT 0x00000010\r
+#define EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT 0x00000010\r
\r
///\r
/// Provides the expression which determines which credentials are required to assert user identity.\r
///\r
-#define EFI_USER_INFO_IDENTITY_POLICY_RECORD 0x0F\r
+#define EFI_USER_INFO_IDENTITY_POLICY_RECORD 0x0F\r
\r
typedef struct {\r
- UINT32 Type; ///< Specifies either an operator or a data item.\r
- UINT32 Length; ///< The length of this block, in bytes, including this header.\r
+ UINT32 Type; ///< Specifies either an operator or a data item.\r
+ UINT32 Length; ///< The length of this block, in bytes, including this header.\r
} EFI_USER_INFO_IDENTITY_POLICY;\r
\r
///\r
/// User identity policy expression operators.\r
///\r
-#define EFI_USER_INFO_IDENTITY_FALSE 0x00\r
-#define EFI_USER_INFO_IDENTITY_TRUE 0x01\r
-#define EFI_USER_INFO_IDENTITY_CREDENTIAL_TYPE 0x02\r
-#define EFI_USER_INFO_IDENTITY_CREDENTIAL_PROVIDER 0x03\r
-#define EFI_USER_INFO_IDENTITY_NOT 0x10\r
-#define EFI_USER_INFO_IDENTITY_AND 0x11\r
-#define EFI_USER_INFO_IDENTITY_OR 0x12\r
+#define EFI_USER_INFO_IDENTITY_FALSE 0x00\r
+#define EFI_USER_INFO_IDENTITY_TRUE 0x01\r
+#define EFI_USER_INFO_IDENTITY_CREDENTIAL_TYPE 0x02\r
+#define EFI_USER_INFO_IDENTITY_CREDENTIAL_PROVIDER 0x03\r
+#define EFI_USER_INFO_IDENTITY_NOT 0x10\r
+#define EFI_USER_INFO_IDENTITY_AND 0x11\r
+#define EFI_USER_INFO_IDENTITY_OR 0x12\r
\r
///\r
/// Provides placeholder for additional user profile information identified by a GUID.\r
///\r
-#define EFI_USER_INFO_GUID_RECORD 0xFF\r
+#define EFI_USER_INFO_GUID_RECORD 0xFF\r
typedef EFI_GUID EFI_USER_INFO_GUID;\r
\r
///\r
/// A collection of EFI_USER_INFO records, prefixed with this header.\r
///\r
typedef struct {\r
- UINT64 Size; ///< Total size of the user information table, in bytes.\r
+ UINT64 Size; ///< Total size of the user information table, in bytes.\r
} EFI_USER_INFO_TABLE;\r
\r
-typedef struct _EFI_USER_MANAGER_PROTOCOL EFI_USER_MANAGER_PROTOCOL;\r
+typedef struct _EFI_USER_MANAGER_PROTOCOL EFI_USER_MANAGER_PROTOCOL;\r
\r
/**\r
Create a new user profile.\r
/// This protocol provides the services used to manage user profiles.\r
///\r
struct _EFI_USER_MANAGER_PROTOCOL {\r
- EFI_USER_PROFILE_CREATE Create;\r
- EFI_USER_PROFILE_DELETE Delete;\r
- EFI_USER_PROFILE_GET_NEXT GetNext;\r
- EFI_USER_PROFILE_CURRENT Current;\r
- EFI_USER_PROFILE_IDENTIFY Identify;\r
- EFI_USER_PROFILE_FIND Find;\r
- EFI_USER_PROFILE_NOTIFY Notify;\r
- EFI_USER_PROFILE_GET_INFO GetInfo;\r
- EFI_USER_PROFILE_SET_INFO SetInfo;\r
- EFI_USER_PROFILE_DELETE_INFO DeleteInfo;\r
- EFI_USER_PROFILE_GET_NEXT_INFO GetNextInfo;\r
+ EFI_USER_PROFILE_CREATE Create;\r
+ EFI_USER_PROFILE_DELETE Delete;\r
+ EFI_USER_PROFILE_GET_NEXT GetNext;\r
+ EFI_USER_PROFILE_CURRENT Current;\r
+ EFI_USER_PROFILE_IDENTIFY Identify;\r
+ EFI_USER_PROFILE_FIND Find;\r
+ EFI_USER_PROFILE_NOTIFY Notify;\r
+ EFI_USER_PROFILE_GET_INFO GetInfo;\r
+ EFI_USER_PROFILE_SET_INFO SetInfo;\r
+ EFI_USER_PROFILE_DELETE_INFO DeleteInfo;\r
+ EFI_USER_PROFILE_GET_NEXT_INFO GetNextInfo;\r
};\r
\r
-extern EFI_GUID gEfiUserManagerProtocolGuid;\r
-extern EFI_GUID gEfiEventUserProfileChangedGuid;\r
-extern EFI_GUID gEfiUserCredentialClassUnknownGuid;\r
-extern EFI_GUID gEfiUserCredentialClassPasswordGuid;\r
-extern EFI_GUID gEfiUserCredentialClassSmartCardGuid;\r
-extern EFI_GUID gEfiUserCredentialClassFingerprintGuid;\r
-extern EFI_GUID gEfiUserCredentialClassHandprintGuid;\r
-extern EFI_GUID gEfiUserCredentialClassSecureCardGuid;\r
-extern EFI_GUID gEfiUserInfoAccessSetupAdminGuid;\r
-extern EFI_GUID gEfiUserInfoAccessSetupNormalGuid;\r
-extern EFI_GUID gEfiUserInfoAccessSetupRestrictedGuid;\r
+extern EFI_GUID gEfiUserManagerProtocolGuid;\r
+extern EFI_GUID gEfiEventUserProfileChangedGuid;\r
+extern EFI_GUID gEfiUserCredentialClassUnknownGuid;\r
+extern EFI_GUID gEfiUserCredentialClassPasswordGuid;\r
+extern EFI_GUID gEfiUserCredentialClassSmartCardGuid;\r
+extern EFI_GUID gEfiUserCredentialClassFingerprintGuid;\r
+extern EFI_GUID gEfiUserCredentialClassHandprintGuid;\r
+extern EFI_GUID gEfiUserCredentialClassSecureCardGuid;\r
+extern EFI_GUID gEfiUserInfoAccessSetupAdminGuid;\r
+extern EFI_GUID gEfiUserInfoAccessSetupNormalGuid;\r
+extern EFI_GUID gEfiUserInfoAccessSetupRestrictedGuid;\r
\r
#endif\r
#define EFI_VARIABLE_ARCH_PROTOCOL_GUID \\r
{ 0x1e5668e2, 0x8481, 0x11d4, {0xbc, 0xf1, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
\r
-extern EFI_GUID gEfiVariableArchProtocolGuid;\r
+extern EFI_GUID gEfiVariableArchProtocolGuid;\r
\r
#endif\r
#define EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID \\r
{ 0x6441f818, 0x6362, 0x4e44, {0xb5, 0x70, 0x7d, 0xba, 0x31, 0xdd, 0x24, 0x53 } }\r
\r
-extern EFI_GUID gEfiVariableWriteArchProtocolGuid;\r
+extern EFI_GUID gEfiVariableWriteArchProtocolGuid;\r
\r
#endif\r
#ifndef __EFI_VLANCONFIG_PROTOCOL_H__\r
#define __EFI_VLANCONFIG_PROTOCOL_H__\r
\r
-\r
#define EFI_VLAN_CONFIG_PROTOCOL_GUID \\r
{ \\r
0x9e23d768, 0xd2f3, 0x4366, {0x9f, 0xc3, 0x3a, 0x7a, 0xba, 0x86, 0x43, 0x74 } \\r
\r
typedef struct _EFI_VLAN_CONFIG_PROTOCOL EFI_VLAN_CONFIG_PROTOCOL;\r
\r
-\r
///\r
/// EFI_VLAN_FIND_DATA\r
///\r
typedef struct {\r
- UINT16 VlanId; ///< Vlan Identifier.\r
- UINT8 Priority; ///< Priority of this VLAN.\r
+ UINT16 VlanId; ///< Vlan Identifier.\r
+ UINT8 Priority; ///< Priority of this VLAN.\r
} EFI_VLAN_FIND_DATA;\r
\r
-\r
/**\r
Create a VLAN device or modify the configuration parameter of an\r
already-configured VLAN.\r
/// VLAN tagging implementation is IEEE802.1Q.\r
///\r
struct _EFI_VLAN_CONFIG_PROTOCOL {\r
- EFI_VLAN_CONFIG_SET Set;\r
- EFI_VLAN_CONFIG_FIND Find;\r
- EFI_VLAN_CONFIG_REMOVE Remove;\r
+ EFI_VLAN_CONFIG_SET Set;\r
+ EFI_VLAN_CONFIG_FIND Find;\r
+ EFI_VLAN_CONFIG_REMOVE Remove;\r
};\r
\r
-extern EFI_GUID gEfiVlanConfigProtocolGuid;\r
+extern EFI_GUID gEfiVlanConfigProtocolGuid;\r
\r
#endif\r
///\r
/// Declare forward reference for the Timer Architectural Protocol\r
///\r
-typedef struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL EFI_WATCHDOG_TIMER_ARCH_PROTOCOL;\r
+typedef struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL EFI_WATCHDOG_TIMER_ARCH_PROTOCOL;\r
\r
/**\r
A function of this type is called when the watchdog timer fires if a\r
OUT UINT64 *TimerPeriod\r
);\r
\r
-\r
///\r
/// This protocol provides the services required to implement the Boot Service\r
/// SetWatchdogTimer(). It provides a service to set the amount of time to wait\r
/// reset by calling the Runtime Service ResetSystem().\r
///\r
struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL {\r
- EFI_WATCHDOG_TIMER_REGISTER_HANDLER RegisterHandler;\r
- EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD SetTimerPeriod;\r
- EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD GetTimerPeriod;\r
+ EFI_WATCHDOG_TIMER_REGISTER_HANDLER RegisterHandler;\r
+ EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD SetTimerPeriod;\r
+ EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD GetTimerPeriod;\r
};\r
\r
-extern EFI_GUID gEfiWatchdogTimerArchProtocolGuid;\r
+extern EFI_GUID gEfiWatchdogTimerArchProtocolGuid;\r
\r
#endif\r
-\r
///\r
/// A unique element ID defined in IEEE 802.11 specification.\r
///\r
- UINT8 ElementID;\r
+ UINT8 ElementID;\r
///\r
/// Specifies the number of octets in the element body.\r
///\r
- UINT8 Length;\r
+ UINT8 Length;\r
} EFI_80211_ELEMENT_HEADER;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Start of elements that are requested to be included in the Probe Response frame.\r
/// The elements are listed in order of increasing element ID.\r
///\r
- UINT8 RequestIDs[1];\r
+ UINT8 RequestIDs[1];\r
} EFI_80211_ELEMENT_REQ;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Service set identifier. If Hdr.Length is zero, this field is ignored.\r
///\r
- UINT8 SSId[32];\r
+ UINT8 SSId[32];\r
} EFI_80211_ELEMENT_SSID;\r
\r
///\r
/// Determines whether infrastructure BSS, IBSS, MBSS, or all, are included in the\r
/// scan.\r
///\r
- EFI_80211_BSS_TYPE BSSType;\r
+ EFI_80211_BSS_TYPE BSSType;\r
///\r
/// Indicates a specific or wildcard BSSID. Use all binary 1s to represent all SSIDs.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Length in bytes of the SSId. If zero, ignore SSId field.\r
///\r
- UINT8 SSIdLen;\r
+ UINT8 SSIdLen;\r
///\r
/// Specifies the desired SSID or the wildcard SSID. Use NULL to represent all SSIDs.\r
///\r
- UINT8 *SSId;\r
+ UINT8 *SSId;\r
///\r
/// Indicates passive scanning if TRUE.\r
///\r
- BOOLEAN PassiveMode;\r
+ BOOLEAN PassiveMode;\r
///\r
/// The delay in microseconds to be used prior to transmitting a Probe frame during\r
/// active scanning. If zero, the value can be overridden by an\r
/// implementation-dependent default value.\r
///\r
- UINT32 ProbeDelay;\r
+ UINT32 ProbeDelay;\r
///\r
/// Specifies a list of channels that are examined when scanning for a BSS. If set to\r
/// NULL, all valid channels will be scanned.\r
///\r
- UINT32 *ChannelList;\r
+ UINT32 *ChannelList;\r
///\r
/// Indicates the minimum time in TU to spend on each channel when scanning. If zero,\r
/// the value can be overridden by an implementation-dependent default value.\r
///\r
- UINT32 MinChannelTime;\r
+ UINT32 MinChannelTime;\r
///\r
/// Indicates the maximum time in TU to spend on each channel when scanning. If zero,\r
/// the value can be overridden by an implementation-dependent default value.\r
///\r
- UINT32 MaxChannelTime;\r
+ UINT32 MaxChannelTime;\r
///\r
/// Points to an optionally present element. This is an optional parameter and may be\r
/// NULL.\r
///\r
- EFI_80211_ELEMENT_REQ *RequestInformation;\r
+ EFI_80211_ELEMENT_REQ *RequestInformation;\r
///\r
/// Indicates one or more SSID elements that are optionally present. This is an\r
/// optional parameter and may be NULL.\r
///\r
- EFI_80211_ELEMENT_SSID *SSIDList;\r
+ EFI_80211_ELEMENT_SSID *SSIDList;\r
///\r
/// Specifies a desired specific access network type or the wildcard access network\r
/// type. Use 15 as wildcard access network type.\r
///\r
- EFI_80211_ACC_NET_TYPE AccessNetworkType;\r
+ EFI_80211_ACC_NET_TYPE AccessNetworkType;\r
///\r
/// Specifies zero or more elements. This is an optional parameter and may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_SCAN_DATA;\r
\r
///\r
/// Indicates the lowest channel number in the subband. It has a positive integer\r
/// value less than 201.\r
///\r
- UINT8 FirstChannelNum;\r
+ UINT8 FirstChannelNum;\r
///\r
/// Indicates the number of channels in the subband.\r
///\r
- UINT8 NumOfChannels;\r
+ UINT8 NumOfChannels;\r
///\r
/// Indicates the maximum power in dBm allowed to be transmitted.\r
///\r
- UINT8 MaxTxPowerLevel;\r
+ UINT8 MaxTxPowerLevel;\r
} EFI_80211_COUNTRY_TRIPLET_SUBBAND;\r
\r
///\r
/// Indicates the operating extension identifier. It has a positive integer value of\r
/// 201 or greater.\r
///\r
- UINT8 OperatingExtId;\r
+ UINT8 OperatingExtId;\r
///\r
/// Index into a set of values for radio equipment set of rules.\r
///\r
- UINT8 OperatingClass;\r
+ UINT8 OperatingClass;\r
///\r
/// Specifies aAirPropagationTime characteristics used in BSS operation. Refer the\r
/// definition of aAirPropagationTime in IEEE 802.11 specification.\r
///\r
- UINT8 CoverageClass;\r
+ UINT8 CoverageClass;\r
} EFI_80211_COUNTRY_TRIPLET_OPERATE;\r
\r
///\r
///\r
/// The subband triplet.\r
///\r
- EFI_80211_COUNTRY_TRIPLET_SUBBAND Subband;\r
+ EFI_80211_COUNTRY_TRIPLET_SUBBAND Subband;\r
///\r
/// The operating triplet.\r
///\r
- EFI_80211_COUNTRY_TRIPLET_OPERATE Operating;\r
+ EFI_80211_COUNTRY_TRIPLET_OPERATE Operating;\r
} EFI_80211_COUNTRY_TRIPLET;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Specifies country strings in 3 octets.\r
///\r
- UINT8 CountryStr[3];\r
+ UINT8 CountryStr[3];\r
///\r
/// Indicates a triplet that repeated in country element. The number of triplets is\r
/// determined by the Hdr.Length field.\r
///\r
- EFI_80211_COUNTRY_TRIPLET CountryTriplet[1];\r
+ EFI_80211_COUNTRY_TRIPLET CountryTriplet[1];\r
} EFI_80211_ELEMENT_COUNTRY;\r
\r
///\r
/// Indicates the version number of the RSNA protocol. Value 1 is defined in current\r
/// IEEE 802.11 specification.\r
///\r
- UINT16 Version;\r
+ UINT16 Version;\r
///\r
/// Specifies the cipher suite selector used by the BSS to protect group address frames.\r
///\r
- UINT32 GroupDataCipherSuite;\r
+ UINT32 GroupDataCipherSuite;\r
///\r
/// Indicates the number of pairwise cipher suite selectors that are contained in\r
/// PairwiseCipherSuiteList.\r
///\r
-//UINT16 PairwiseCipherSuiteCount;\r
+ // UINT16 PairwiseCipherSuiteCount;\r
///\r
/// Contains a series of cipher suite selectors that indicate the pairwise cipher\r
/// suites contained in this element.\r
///\r
-//UINT32 PairwiseCipherSuiteList[PairwiseCipherSuiteCount];\r
+ // UINT32 PairwiseCipherSuiteList[PairwiseCipherSuiteCount];\r
///\r
/// Indicates the number of AKM suite selectors that are contained in AKMSuiteList.\r
///\r
-//UINT16 AKMSuiteCount;\r
+ // UINT16 AKMSuiteCount;\r
///\r
/// Contains a series of AKM suite selectors that indicate the AKM suites contained in\r
/// this element.\r
///\r
-//UINT32 AKMSuiteList[AKMSuiteCount];\r
+ // UINT32 AKMSuiteList[AKMSuiteCount];\r
///\r
/// Indicates requested or advertised capabilities.\r
///\r
-//UINT16 RSNCapabilities;\r
+ // UINT16 RSNCapabilities;\r
///\r
/// Indicates the number of PKMIDs in the PMKIDList.\r
///\r
-//UINT16 PMKIDCount;\r
+ // UINT16 PMKIDCount;\r
///\r
/// Contains zero or more PKMIDs that the STA believes to be valid for the destination\r
/// AP.\r
-//UINT8 PMKIDList[PMKIDCount][16];\r
+ // UINT8 PMKIDList[PMKIDCount][16];\r
///\r
/// Specifies the cipher suite selector used by the BSS to protect group addressed\r
/// robust management frames.\r
///\r
-//UINT32 GroupManagementCipherSuite;\r
+ // UINT32 GroupManagementCipherSuite;\r
} EFI_80211_ELEMENT_DATA_RSN;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Points to RSN element. The size of a RSN element is limited to 255 octets.\r
///\r
- EFI_80211_ELEMENT_DATA_RSN *Data;\r
+ EFI_80211_ELEMENT_DATA_RSN *Data;\r
} EFI_80211_ELEMENT_RSN;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Indicates the capabilities being advertised by the STA transmitting the element.\r
/// This is a bit field with variable length. Refer to IEEE 802.11 specification for\r
/// bit value.\r
///\r
- UINT8 Capabilities[1];\r
+ UINT8 Capabilities[1];\r
} EFI_80211_ELEMENT_EXT_CAP;\r
\r
///\r
///\r
/// Indicates a specific BSSID of the found BSS.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the SSID of the found BSS. If NULL, ignore SSIdLen field.\r
///\r
- UINT8 *SSId;\r
+ UINT8 *SSId;\r
///\r
/// Specifies the SSID of the found BSS. If NULL, ignore SSIdLen field.\r
///\r
- UINT8 SSIdLen;\r
+ UINT8 SSIdLen;\r
///\r
/// Specifies the type of the found BSS.\r
///\r
- EFI_80211_BSS_TYPE BSSType;\r
+ EFI_80211_BSS_TYPE BSSType;\r
///\r
/// The beacon period in TU of the found BSS.\r
///\r
- UINT16 BeaconPeriod;\r
+ UINT16 BeaconPeriod;\r
///\r
/// The timestamp of the received frame from the found BSS.\r
///\r
- UINT64 Timestamp;\r
+ UINT64 Timestamp;\r
///\r
/// The advertised capabilities of the BSS.\r
///\r
- UINT16 CapabilityInfo;\r
+ UINT16 CapabilityInfo;\r
///\r
/// The set of data rates that shall be supported by all STAs that desire to join this\r
/// BSS.\r
///\r
- UINT8 *BSSBasicRateSet;\r
+ UINT8 *BSSBasicRateSet;\r
///\r
/// The set of data rates that the peer STA desires to use for communication within\r
/// the BSS.\r
///\r
- UINT8 *OperationalRateSet;\r
+ UINT8 *OperationalRateSet;\r
///\r
/// The information required to identify the regulatory domain in which the peer STA\r
/// is located.\r
///\r
- EFI_80211_ELEMENT_COUNTRY *Country;\r
+ EFI_80211_ELEMENT_COUNTRY *Country;\r
///\r
/// The cipher suites and AKM suites supported in the BSS.\r
///\r
- EFI_80211_ELEMENT_RSN RSN;\r
+ EFI_80211_ELEMENT_RSN RSN;\r
///\r
/// Specifies the RSSI of the received frame.\r
///\r
- UINT8 RSSI;\r
+ UINT8 RSSI;\r
///\r
/// Specifies the RCPI of the received frame.\r
///\r
- UINT8 RCPIMeasurement;\r
+ UINT8 RCPIMeasurement;\r
///\r
/// Specifies the RSNI of the received frame.\r
///\r
- UINT8 RSNIMeasurement;\r
+ UINT8 RSNIMeasurement;\r
///\r
/// Specifies the elements requested by the request element of the Probe Request frame.\r
/// This is an optional parameter and may be NULL.\r
///\r
- UINT8 *RequestedElements;\r
+ UINT8 *RequestedElements;\r
///\r
/// Specifies the BSS membership selectors that represent the set of features that\r
/// shall be supported by all STAs to join this BSS.\r
///\r
- UINT8 *BSSMembershipSelectorSet;\r
+ UINT8 *BSSMembershipSelectorSet;\r
///\r
/// Specifies the parameters within the Extended Capabilities element that are\r
/// supported by the MAC entity. This is an optional parameter and may be NULL.\r
///\r
- EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
+ EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
} EFI_80211_BSS_DESCRIPTION;\r
\r
///\r
///\r
/// Indicates the unique identifier within the containing element or sub-element.\r
///\r
- UINT8 SubElementID;\r
+ UINT8 SubElementID;\r
///\r
/// Specifies the number of octets in the Data field.\r
///\r
- UINT8 Length;\r
+ UINT8 Length;\r
///\r
/// A variable length data buffer.\r
///\r
- UINT8 Data[1];\r
+ UINT8 Data[1];\r
} EFI_80211_SUBELEMENT_INFO;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Indicates the maximum number of BSSIDs in the multiple BSSID set. When Indicator\r
/// is set to n, 2n is the maximum number.\r
///\r
- UINT8 Indicator;\r
+ UINT8 Indicator;\r
///\r
/// Contains zero or more sub-elements.\r
///\r
- EFI_80211_SUBELEMENT_INFO SubElement[1];\r
+ EFI_80211_SUBELEMENT_INFO SubElement[1];\r
} EFI_80211_MULTIPLE_BSSID;\r
\r
///\r
///\r
/// Indicates a specific BSSID of the found BSS.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the type of the found BSS.\r
///\r
- EFI_80211_BSS_TYPE BSSType;\r
+ EFI_80211_BSS_TYPE BSSType;\r
///\r
/// One octet field to report condensed capability information.\r
///\r
- UINT8 ConCapInfo;\r
+ UINT8 ConCapInfo;\r
///\r
/// Two octet's field to report condensed country string.\r
///\r
- UINT8 ConCountryStr[2];\r
+ UINT8 ConCountryStr[2];\r
///\r
/// Indicates the operating class value for the operating channel.\r
///\r
- UINT8 OperatingClass;\r
+ UINT8 OperatingClass;\r
///\r
/// Indicates the operating channel.\r
///\r
- UINT8 Channel;\r
+ UINT8 Channel;\r
///\r
/// Indicates the measurement pilot interval in TU.\r
///\r
- UINT8 Interval;\r
+ UINT8 Interval;\r
///\r
/// Indicates that the BSS is within a multiple BSSID set.\r
///\r
- EFI_80211_MULTIPLE_BSSID *MultipleBSSID;\r
+ EFI_80211_MULTIPLE_BSSID *MultipleBSSID;\r
///\r
/// Specifies the RCPI of the received frame.\r
///\r
- UINT8 RCPIMeasurement;\r
+ UINT8 RCPIMeasurement;\r
///\r
/// Specifies the RSNI of the received frame.\r
///\r
- UINT8 RSNIMeasurement;\r
+ UINT8 RSNIMeasurement;\r
} EFI_80211_BSS_DESP_PILOT;\r
\r
///\r
/// The number of EFI_80211_BSS_DESCRIPTION in BSSDespSet. If zero, BSSDespSet should\r
/// be ignored.\r
///\r
- UINTN NumOfBSSDesp;\r
+ UINTN NumOfBSSDesp;\r
///\r
/// Points to zero or more instances of EFI_80211_BSS_DESCRIPTION.\r
///\r
- EFI_80211_BSS_DESCRIPTION **BSSDespSet;\r
+ EFI_80211_BSS_DESCRIPTION **BSSDespSet;\r
///\r
/// The number of EFI_80211_BSS_DESP_PILOT in BSSDespFromPilotSet. If zero,\r
/// BSSDespFromPilotSet should be ignored.\r
///\r
- UINTN NumofBSSDespFromPilot;\r
+ UINTN NumofBSSDespFromPilot;\r
///\r
/// Points to zero or more instances of EFI_80211_BSS_DESP_PILOT.\r
///\r
- EFI_80211_BSS_DESP_PILOT **BSSDespFromPilotSet;\r
+ EFI_80211_BSS_DESP_PILOT **BSSDespFromPilotSet;\r
///\r
/// Specifies zero or more elements. This is an optional parameter and may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_SCAN_RESULT;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI Wireless\r
/// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: Scan operation completed successfully.\r
/// EFI_ACCESS_DENIED: The scan operation is not completed due to some underlying\r
/// hardware or software state.\r
/// EFI_NOT_READY: The scan operation is started but not yet completed.\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Pointer to the scan data.\r
///\r
- EFI_80211_SCAN_DATA *Data;\r
+ EFI_80211_SCAN_DATA *Data;\r
///\r
/// Indicates the scan state.\r
///\r
- EFI_80211_SCAN_RESULT_CODE ResultCode;\r
+ EFI_80211_SCAN_RESULT_CODE ResultCode;\r
///\r
/// Indicates the scan result. It is caller's responsibility to free this buffer.\r
///\r
- EFI_80211_SCAN_RESULT *Result;\r
+ EFI_80211_SCAN_RESULT *Result;\r
} EFI_80211_SCAN_DATA_TOKEN;\r
\r
///\r
///\r
/// The first channel number in a subband of supported channels.\r
///\r
- UINT8 FirstChannelNumber;\r
+ UINT8 FirstChannelNumber;\r
///\r
/// The number of channels in a subband of supported channels.\r
///\r
- UINT8 NumberOfChannels;\r
+ UINT8 NumberOfChannels;\r
} EFI_80211_ELEMENT_SUPP_CHANNEL_TUPLE;\r
\r
///\r
///\r
/// Specifies the address of the peer MAC entity to associate with.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the requested operational capabilities to the AP in 2 octets.\r
///\r
- UINT16 CapabilityInfo;\r
+ UINT16 CapabilityInfo;\r
///\r
/// Specifies a time limit in TU, after which the associate procedure is terminated.\r
///\r
- UINT32 FailureTimeout;\r
+ UINT32 FailureTimeout;\r
///\r
/// Specifies if in power save mode, how often the STA awakes and listens for the next\r
/// beacon frame in TU.\r
///\r
- UINT32 ListenInterval;\r
+ UINT32 ListenInterval;\r
///\r
/// Indicates a list of channels in which the STA is capable of operating.\r
///\r
- EFI_80211_ELEMENT_SUPP_CHANNEL *Channels;\r
+ EFI_80211_ELEMENT_SUPP_CHANNEL *Channels;\r
///\r
/// The cipher suites and AKM suites selected by the STA.\r
///\r
- EFI_80211_ELEMENT_RSN RSN;\r
+ EFI_80211_ELEMENT_RSN RSN;\r
///\r
/// Specifies the parameters within the Extended Capabilities element that are\r
/// supported by the MAC entity. This is an optional parameter and may be NULL.\r
///\r
- EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
+ EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
///\r
/// Specifies zero or more elements. This is an optional parameter and may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_ASSOCIATE_DATA;\r
\r
///\r
///\r
/// Common header of an element.\r
///\r
- EFI_80211_ELEMENT_HEADER Hdr;\r
+ EFI_80211_ELEMENT_HEADER Hdr;\r
///\r
/// Specifies the timeout interval type.\r
///\r
- UINT8 Type;\r
+ UINT8 Type;\r
///\r
/// Specifies the timeout interval value.\r
///\r
- UINT32 Value;\r
+ UINT32 Value;\r
} EFI_80211_ELEMENT_TIMEOUT_VAL;\r
\r
///\r
/// Specifies the address of the peer MAC entity from which the association request\r
/// was received.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the operational capabilities advertised by the AP.\r
///\r
- UINT16 CapabilityInfo;\r
+ UINT16 CapabilityInfo;\r
///\r
/// Specifies the association ID value assigned by the AP.\r
///\r
- UINT16 AssociationID;\r
+ UINT16 AssociationID;\r
///\r
/// Indicates the measured RCPI of the corresponding association request frame. It is\r
/// an optional parameter and is set to zero if unavailable.\r
///\r
- UINT8 RCPIValue;\r
+ UINT8 RCPIValue;\r
///\r
/// Indicates the measured RSNI at the time the corresponding association request\r
/// frame was received. It is an optional parameter and is set to zero if unavailable.\r
///\r
- UINT8 RSNIValue;\r
+ UINT8 RSNIValue;\r
///\r
/// Specifies the parameters within the Extended Capabilities element that are\r
/// supported by the MAC entity. This is an optional parameter and may be NULL.\r
///\r
- EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
+ EFI_80211_ELEMENT_EXT_CAP *ExtCapElement;\r
///\r
/// Specifies the timeout interval when the result code is AssociateRefusedTemporarily.\r
///\r
- EFI_80211_ELEMENT_TIMEOUT_VAL TimeoutInterval;\r
+ EFI_80211_ELEMENT_TIMEOUT_VAL TimeoutInterval;\r
///\r
/// Specifies zero or more elements. This is an optional parameter and may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_ASSOCIATE_RESULT;\r
\r
///\r
/// Specifies the address of the peer MAC entity with which to perform the\r
/// disassociation process.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the reason for initiating the disassociation process.\r
///\r
- EFI_80211_REASON_CODE ReasonCode;\r
+ EFI_80211_REASON_CODE ReasonCode;\r
///\r
/// Zero or more elements, may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_DISASSOCIATE_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI Wireless\r
/// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: Disassociation operation completed successfully.\r
/// underlying hardware or software state.\r
/// EFI_NOT_READY: The disassociation operation is started but not yet completed.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Pointer to the disassociation data.\r
///\r
- EFI_80211_DISASSOCIATE_DATA *Data;\r
+ EFI_80211_DISASSOCIATE_DATA *Data;\r
///\r
/// Indicates the disassociation state.\r
///\r
- EFI_80211_DISASSOCIATE_RESULT_CODE ResultCode;\r
+ EFI_80211_DISASSOCIATE_RESULT_CODE ResultCode;\r
} EFI_80211_DISASSOCIATE_DATA_TOKEN;\r
\r
///\r
/// Specifies the address of the peer MAC entity with which to perform the\r
/// authentication process.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the type of authentication algorithm to use during the authentication\r
/// process.\r
///\r
- EFI_80211_AUTHENTICATION_TYPE AuthType;\r
+ EFI_80211_AUTHENTICATION_TYPE AuthType;\r
///\r
/// Specifies a time limit in TU after which the authentication procedure is\r
/// terminated.\r
///\r
- UINT32 FailureTimeout;\r
+ UINT32 FailureTimeout;\r
///\r
/// Specifies the set of elements to be included in the first message of the FT\r
/// authentication sequence, may be NULL.\r
///\r
- UINT8 *FTContent;\r
+ UINT8 *FTContent;\r
///\r
/// Specifies the set of elements to be included in the SAE Commit Message or SAE\r
/// Confirm Message, may be NULL.\r
///\r
- UINT8 *SAEContent;\r
+ UINT8 *SAEContent;\r
///\r
/// Zero or more elements, may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_AUTHENTICATE_DATA;\r
\r
///\r
/// Specifies the address of the peer MAC entity from which the authentication request\r
/// was received.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the set of elements to be included in the second message of the FT\r
/// authentication sequence, may be NULL.\r
///\r
- UINT8 *FTContent;\r
+ UINT8 *FTContent;\r
///\r
/// Specifies the set of elements to be included in the SAE Commit Message or SAE\r
/// Confirm Message, may be NULL.\r
///\r
- UINT8 *SAEContent;\r
+ UINT8 *SAEContent;\r
///\r
/// Zero or more elements, may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_AUTHENTICATE_RESULT;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI Wireless\r
/// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: Authentication operation completed successfully.\r
/// underlying hardware or software state.\r
/// EFI_NOT_READY: The authentication operation is started but not yet completed.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Pointer to the authentication data.\r
///\r
- EFI_80211_AUTHENTICATE_DATA *Data;\r
+ EFI_80211_AUTHENTICATE_DATA *Data;\r
///\r
/// Indicates the association state.\r
///\r
- EFI_80211_AUTHENTICATE_RESULT_CODE ResultCode;\r
+ EFI_80211_AUTHENTICATE_RESULT_CODE ResultCode;\r
///\r
/// Indicates the association result. It is caller's responsibility to free this\r
/// buffer.\r
///\r
- EFI_80211_AUTHENTICATE_RESULT *Result;\r
+ EFI_80211_AUTHENTICATE_RESULT *Result;\r
} EFI_80211_AUTHENTICATE_DATA_TOKEN;\r
\r
///\r
/// Specifies the address of the peer MAC entity with which to perform the\r
/// deauthentication process.\r
///\r
- EFI_80211_MAC_ADDRESS BSSId;\r
+ EFI_80211_MAC_ADDRESS BSSId;\r
///\r
/// Specifies the reason for initiating the deauthentication process.\r
///\r
- EFI_80211_REASON_CODE ReasonCode;\r
+ EFI_80211_REASON_CODE ReasonCode;\r
///\r
/// Zero or more elements, may be NULL.\r
///\r
- UINT8 *VendorSpecificInfo;\r
+ UINT8 *VendorSpecificInfo;\r
} EFI_80211_DEAUTHENTICATE_DATA;\r
\r
///\r
/// This Event will be signaled after the Status field is updated by the EFI Wireless\r
/// MAC Connection Protocol driver. The type of Event must be EFI_NOTIFY_SIGNAL.\r
///\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
///\r
/// Will be set to one of the following values:\r
/// EFI_SUCCESS: Deauthentication operation completed successfully.\r
/// EFI_NOT_READY: The deauthentication operation is started but not yet\r
/// completed.\r
///\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
///\r
/// Pointer to the deauthentication data.\r
///\r
- EFI_80211_DEAUTHENTICATE_DATA *Data;\r
+ EFI_80211_DEAUTHENTICATE_DATA *Data;\r
} EFI_80211_DEAUTHENTICATE_DATA_TOKEN;\r
\r
/**\r
/// communication device that the EFI wireless network stack runs on.\r
///\r
struct _EFI_WIRELESS_MAC_CONNECTION_PROTOCOL {\r
- EFI_WIRELESS_MAC_CONNECTION_SCAN Scan;\r
- EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE Associate;\r
- EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE Disassociate;\r
- EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE Authenticate;\r
- EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE Deauthenticate;\r
+ EFI_WIRELESS_MAC_CONNECTION_SCAN Scan;\r
+ EFI_WIRELESS_MAC_CONNECTION_ASSOCIATE Associate;\r
+ EFI_WIRELESS_MAC_CONNECTION_DISASSOCIATE Disassociate;\r
+ EFI_WIRELESS_MAC_CONNECTION_AUTHENTICATE Authenticate;\r
+ EFI_WIRELESS_MAC_CONNECTION_DEAUTHENTICATE Deauthenticate;\r
};\r
\r
-extern EFI_GUID gEfiWiFiProtocolGuid;\r
+extern EFI_GUID gEfiWiFiProtocolGuid;\r
\r
#endif\r
/// EFI_80211_MAC_ADDRESS\r
///\r
typedef struct {\r
- UINT8 Addr[6];\r
+ UINT8 Addr[6];\r
} EFI_80211_MAC_ADDRESS;\r
\r
-#define EFI_MAX_SSID_LEN 32\r
+#define EFI_MAX_SSID_LEN 32\r
\r
///\r
/// EFI_80211_SSID\r
//\r
// Length in bytes of the SSId. If zero, ignore SSId field.\r
//\r
- UINT8 SSIdLen;\r
+ UINT8 SSIdLen;\r
//\r
// Specifies the service set identifier.\r
//\r
- UINT8 SSId[EFI_MAX_SSID_LEN];\r
+ UINT8 SSId[EFI_MAX_SSID_LEN];\r
} EFI_80211_SSID;\r
\r
///\r
// The number of EFI_80211_SSID in SSIDList. If zero, SSIDList should be\r
// ignored.\r
//\r
- UINT32 NumOfSSID;\r
+ UINT32 NumOfSSID;\r
//\r
// The SSIDList is a pointer to an array of EFI_80211_SSID instances. The\r
// number of entries is specified by NumOfSSID. The array should only include\r
// 10 elements in the SSIDList. It is the caller's responsibility to free\r
// this buffer.\r
//\r
- EFI_80211_SSID SSIDList[1];\r
+ EFI_80211_SSID SSIDList[1];\r
} EFI_80211_GET_NETWORKS_DATA;\r
\r
///\r
// Organization Unique Identifier, as defined in IEEE 802.11 standard,\r
// usually set to 00-0F-AC.\r
//\r
- UINT8 Oui[3];\r
+ UINT8 Oui[3];\r
//\r
// Suites types, as defined in IEEE 802.11 standard.\r
//\r
- UINT8 SuiteType;\r
+ UINT8 SuiteType;\r
} EFI_80211_SUITE_SELECTOR;\r
\r
///\r
// Indicates the number of AKM suite selectors that are contained in\r
// AKMSuiteList. If zero, the AKMSuiteList is ignored.\r
//\r
- UINT16 AKMSuiteCount;\r
+ UINT16 AKMSuiteCount;\r
//\r
// A variable-length array of AKM suites, as defined in IEEE 802.11 standard,\r
// Table 8-101. The number of entries is specified by AKMSuiteCount.\r
//\r
- EFI_80211_SUITE_SELECTOR AKMSuiteList[1];\r
+ EFI_80211_SUITE_SELECTOR AKMSuiteList[1];\r
} EFI_80211_AKM_SUITE_SELECTOR;\r
\r
///\r
// Indicates the number of cipher suites that are contained in\r
// CipherSuiteList. If zero, the CipherSuiteList is ignored.\r
//\r
- UINT16 CipherSuiteCount;\r
+ UINT16 CipherSuiteCount;\r
//\r
// A variable-length array of cipher suites, as defined in IEEE 802.11\r
// standard, Table 8-99. The number of entries is specified by\r
// CipherSuiteCount.\r
//\r
- EFI_80211_SUITE_SELECTOR CipherSuiteList[1];\r
+ EFI_80211_SUITE_SELECTOR CipherSuiteList[1];\r
} EFI_80211_CIPHER_SUITE_SELECTOR;\r
\r
///\r
//\r
// Specifies the type of the BSS.\r
//\r
- EFI_80211_BSS_TYPE BSSType;\r
+ EFI_80211_BSS_TYPE BSSType;\r
//\r
// Specifies the SSID of the BSS.\r
//\r
- EFI_80211_SSID SSId;\r
+ EFI_80211_SSID SSId;\r
//\r
// Pointer to the AKM suites supported in the wireless network.\r
//\r
- EFI_80211_AKM_SUITE_SELECTOR *AKMSuite;\r
+ EFI_80211_AKM_SUITE_SELECTOR *AKMSuite;\r
//\r
// Pointer to the cipher suites supported in the wireless network.\r
//\r
- EFI_80211_CIPHER_SUITE_SELECTOR *CipherSuite;\r
+ EFI_80211_CIPHER_SUITE_SELECTOR *CipherSuite;\r
} EFI_80211_NETWORK;\r
\r
///\r
//\r
// Specifies the found wireless network.\r
//\r
- EFI_80211_NETWORK Network;\r
+ EFI_80211_NETWORK Network;\r
//\r
// Indicates the network quality as a value between 0 to 100, where 100\r
// indicates the highest network quality.\r
//\r
- UINT8 NetworkQuality;\r
+ UINT8 NetworkQuality;\r
} EFI_80211_NETWORK_DESCRIPTION;\r
\r
///\r
// The number of EFI_80211_NETWORK_DESCRIPTION in NetworkDesc. If zero,\r
// NetworkDesc should be ignored.\r
//\r
- UINT8 NumOfNetworkDesc;\r
+ UINT8 NumOfNetworkDesc;\r
//\r
// The NetworkDesc is a pointer to an array of EFI_80211_NETWORK_DESCRIPTION\r
// instances. It is caller's responsibility to free this buffer.\r
//\r
- EFI_80211_NETWORK_DESCRIPTION NetworkDesc[1];\r
+ EFI_80211_NETWORK_DESCRIPTION NetworkDesc[1];\r
} EFI_80211_GET_NETWORKS_RESULT;\r
\r
///\r
// Wireless MAC Connection Protocol II driver. The type of Event must be\r
// EFI_NOTIFY_SIGNAL.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
//\r
// Will be set to one of the following values:\r
// EFI_SUCCESS: The operation completed successfully.\r
// hardware or software state.\r
// EFI_NOT_READY: The operation is started but not yet completed.\r
//\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
//\r
// Pointer to the input data for getting networks.\r
//\r
- EFI_80211_GET_NETWORKS_DATA *Data;\r
+ EFI_80211_GET_NETWORKS_DATA *Data;\r
//\r
// Indicates the scan result. It is caller's responsibility to free this\r
// buffer.\r
//\r
- EFI_80211_GET_NETWORKS_RESULT *Result;\r
+ EFI_80211_GET_NETWORKS_RESULT *Result;\r
} EFI_80211_GET_NETWORKS_TOKEN;\r
\r
///\r
//\r
// Specifies the wireless network to connect to.\r
//\r
- EFI_80211_NETWORK *Network;\r
+ EFI_80211_NETWORK *Network;\r
//\r
// Specifies a time limit in seconds that is optionally present, after which\r
// the connection establishment procedure is terminated by the UNDI driver.\r
// This is an optional parameter and may be 0. Values of 5 seconds or higher\r
// are recommended.\r
//\r
- UINT32 FailureTimeout;\r
+ UINT32 FailureTimeout;\r
} EFI_80211_CONNECT_NETWORK_DATA;\r
\r
///\r
// Wireless MAC Connection Protocol II driver. The type of Event must be\r
// EFI_NOTIFY_SIGNAL.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
//\r
// Will be set to one of the following values:\r
// EFI_SUCCESS: The operation completed successfully.\r
// hardware or software state.\r
// EFI_NOT_READY: The operation is started but not yet completed.\r
//\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
//\r
// Pointer to the connection data.\r
//\r
- EFI_80211_CONNECT_NETWORK_DATA *Data;\r
+ EFI_80211_CONNECT_NETWORK_DATA *Data;\r
//\r
// Indicates the connection state.\r
//\r
- EFI_80211_CONNECT_NETWORK_RESULT_CODE ResultCode;\r
+ EFI_80211_CONNECT_NETWORK_RESULT_CODE ResultCode;\r
} EFI_80211_CONNECT_NETWORK_TOKEN;\r
\r
///\r
// Wireless MAC Connection Protocol II driver. The type of Event must be\r
// EFI_NOTIFY_SIGNAL.\r
//\r
- EFI_EVENT Event;\r
+ EFI_EVENT Event;\r
//\r
// Will be set to one of the following values:\r
// EFI_SUCCESS: The operation completed successfully\r
// EFI_ACCESS_DENIED: The operation is not completed due to some underlying\r
// hardware or software state.\r
//\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
} EFI_80211_DISCONNECT_NETWORK_TOKEN;\r
\r
/**\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS) (\r
+(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS)(\r
IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This,\r
IN EFI_80211_GET_NETWORKS_TOKEN *Token\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK) (\r
+(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK)(\r
IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This,\r
IN EFI_80211_CONNECT_NETWORK_TOKEN *Token\r
);\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK) (\r
+(EFIAPI *EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK)(\r
IN EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL *This,\r
IN EFI_80211_DISCONNECT_NETWORK_TOKEN *Token\r
);\r
/// network.\r
///\r
struct _EFI_WIRELESS_MAC_CONNECTION_II_PROTOCOL {\r
- EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS GetNetworks;\r
- EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK ConnectNetwork;\r
- EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK DisconnectNetwork;\r
+ EFI_WIRELESS_MAC_CONNECTION_II_GET_NETWORKS GetNetworks;\r
+ EFI_WIRELESS_MAC_CONNECTION_II_CONNECT_NETWORK ConnectNetwork;\r
+ EFI_WIRELESS_MAC_CONNECTION_II_DISCONNECT_NETWORK DisconnectNetwork;\r
};\r
\r
-extern EFI_GUID gEfiWiFi2ProtocolGuid;\r
+extern EFI_GUID gEfiWiFi2ProtocolGuid;\r
\r
#endif\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Extended Processor Signature and Features\r
\r
///\r
/// [Bits 3:0] Stepping.\r
///\r
- UINT32 Stepping:4;\r
+ UINT32 Stepping : 4;\r
///\r
/// [Bits 7:4] Base Model.\r
///\r
- UINT32 BaseModel:4;\r
+ UINT32 BaseModel : 4;\r
///\r
/// [Bits 11:8] Base Family.\r
///\r
- UINT32 BaseFamily:4;\r
+ UINT32 BaseFamily : 4;\r
///\r
/// [Bit 15:12] Reserved.\r
///\r
- UINT32 Reserved1:4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 19:16] Extended Model.\r
///\r
- UINT32 ExtModel:4;\r
+ UINT32 ExtModel : 4;\r
///\r
/// [Bits 27:20] Extended Family.\r
///\r
- UINT32 ExtFamily:8;\r
+ UINT32 ExtFamily : 8;\r
///\r
/// [Bit 31:28] Reserved.\r
///\r
- UINT32 Reserved2:4;\r
+ UINT32 Reserved2 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r
\r
/**\r
///\r
/// [Bits 27:0] Reserved.\r
///\r
- UINT32 Reserved:28;\r
+ UINT32 Reserved : 28;\r
///\r
/// [Bit 31:28] Package Type.\r
///\r
- UINT32 PkgType:4;\r
+ UINT32 PkgType : 4;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r
\r
/**\r
///\r
/// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
///\r
- UINT32 LAHF_SAHF:1;\r
+ UINT32 LAHF_SAHF : 1;\r
///\r
/// [Bit 1] Core multi-processing legacy mode.\r
///\r
- UINT32 CmpLegacy:1;\r
+ UINT32 CmpLegacy : 1;\r
///\r
/// [Bit 2] Secure Virtual Mode feature.\r
///\r
- UINT32 SVM:1;\r
+ UINT32 SVM : 1;\r
///\r
/// [Bit 3] Extended APIC register space.\r
///\r
- UINT32 ExtApicSpace:1;\r
+ UINT32 ExtApicSpace : 1;\r
///\r
/// [Bit 4] LOCK MOV CR0 means MOV CR8.\r
///\r
- UINT32 AltMovCr8:1;\r
+ UINT32 AltMovCr8 : 1;\r
///\r
/// [Bit 5] LZCNT instruction support.\r
///\r
- UINT32 LZCNT:1;\r
+ UINT32 LZCNT : 1;\r
///\r
/// [Bit 6] SSE4A instruction support.\r
///\r
- UINT32 SSE4A:1;\r
+ UINT32 SSE4A : 1;\r
///\r
/// [Bit 7] Misaligned SSE Mode.\r
///\r
- UINT32 MisAlignSse:1;\r
+ UINT32 MisAlignSse : 1;\r
///\r
/// [Bit 8] ThreeDNow Prefetch instructions.\r
///\r
- UINT32 PREFETCHW:1;\r
+ UINT32 PREFETCHW : 1;\r
///\r
/// [Bit 9] OS Visible Work-around support.\r
///\r
- UINT32 OSVW:1;\r
+ UINT32 OSVW : 1;\r
///\r
/// [Bit 10] Instruction Based Sampling.\r
///\r
- UINT32 IBS:1;\r
+ UINT32 IBS : 1;\r
///\r
/// [Bit 11] Extended Operation Support.\r
///\r
- UINT32 XOP:1;\r
+ UINT32 XOP : 1;\r
///\r
/// [Bit 12] SKINIT and STGI support.\r
///\r
- UINT32 SKINIT:1;\r
+ UINT32 SKINIT : 1;\r
///\r
/// [Bit 13] Watchdog Timer support.\r
///\r
- UINT32 WDT:1;\r
+ UINT32 WDT : 1;\r
///\r
/// [Bit 14] Reserved.\r
///\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 15] Lightweight Profiling support.\r
///\r
- UINT32 LWP:1;\r
+ UINT32 LWP : 1;\r
///\r
/// [Bit 16] 4-Operand FMA instruction support.\r
///\r
- UINT32 FMA4:1;\r
+ UINT32 FMA4 : 1;\r
///\r
/// [Bit 17] Translation Cache Extension.\r
///\r
- UINT32 TCE:1;\r
+ UINT32 TCE : 1;\r
///\r
/// [Bit 21:18] Reserved.\r
///\r
- UINT32 Reserved2:4;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 22] Topology Extensions support.\r
///\r
- UINT32 TopologyExtensions:1;\r
+ UINT32 TopologyExtensions : 1;\r
///\r
/// [Bit 23] Core Performance Counter Extensions.\r
///\r
- UINT32 PerfCtrExtCore:1;\r
+ UINT32 PerfCtrExtCore : 1;\r
///\r
/// [Bit 25:24] Reserved.\r
///\r
- UINT32 Reserved3:2;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 26] Data Breakpoint Extension.\r
///\r
- UINT32 DataBreakpointExtension:1;\r
+ UINT32 DataBreakpointExtension : 1;\r
///\r
/// [Bit 27] Performance Time-Stamp Counter.\r
///\r
- UINT32 PerfTsc:1;\r
+ UINT32 PerfTsc : 1;\r
///\r
/// [Bit 28] L3 Performance Counter Extensions.\r
///\r
- UINT32 PerfCtrExtL3:1;\r
+ UINT32 PerfCtrExtL3 : 1;\r
///\r
/// [Bit 29] MWAITX and MONITORX capability.\r
///\r
- UINT32 MwaitExtended:1;\r
+ UINT32 MwaitExtended : 1;\r
///\r
/// [Bit 31:30] Reserved.\r
///\r
- UINT32 Reserved4:2;\r
+ UINT32 Reserved4 : 2;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r
\r
/**\r
///\r
/// [Bit 0] x87 floating point unit on-chip.\r
///\r
- UINT32 FPU:1;\r
+ UINT32 FPU : 1;\r
///\r
/// [Bit 1] Virtual-mode enhancements.\r
///\r
- UINT32 VME:1;\r
+ UINT32 VME : 1;\r
///\r
/// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r
///\r
- UINT32 DE:1;\r
+ UINT32 DE : 1;\r
///\r
/// [Bit 3] Page-size extensions (4 MB pages).\r
///\r
- UINT32 PSE:1;\r
+ UINT32 PSE : 1;\r
///\r
/// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r
///\r
- UINT32 TSC:1;\r
+ UINT32 TSC : 1;\r
///\r
/// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r
///\r
- UINT32 MSR:1;\r
+ UINT32 MSR : 1;\r
///\r
/// [Bit 6] Physical-address extensions (PAE).\r
///\r
- UINT32 PAE:1;\r
+ UINT32 PAE : 1;\r
///\r
/// [Bit 7] Machine check exception, CR4.MCE.\r
///\r
- UINT32 MCE:1;\r
+ UINT32 MCE : 1;\r
///\r
/// [Bit 8] CMPXCHG8B instruction.\r
///\r
- UINT32 CMPXCHG8B:1;\r
+ UINT32 CMPXCHG8B : 1;\r
///\r
/// [Bit 9] APIC exists and is enabled.\r
///\r
- UINT32 APIC:1;\r
+ UINT32 APIC : 1;\r
///\r
/// [Bit 10] Reserved.\r
///\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 11] SYSCALL and SYSRET instructions.\r
///\r
- UINT32 SYSCALL_SYSRET:1;\r
+ UINT32 SYSCALL_SYSRET : 1;\r
///\r
/// [Bit 12] Memory-type range registers.\r
///\r
- UINT32 MTRR:1;\r
+ UINT32 MTRR : 1;\r
///\r
/// [Bit 13] Page global extension, CR4.PGE.\r
///\r
- UINT32 PGE:1;\r
+ UINT32 PGE : 1;\r
///\r
/// [Bit 14] Machine check architecture, MCG_CAP.\r
///\r
- UINT32 MCA:1;\r
+ UINT32 MCA : 1;\r
///\r
/// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r
///\r
- UINT32 CMOV:1;\r
+ UINT32 CMOV : 1;\r
///\r
/// [Bit 16] Page attribute table.\r
///\r
- UINT32 PAT:1;\r
+ UINT32 PAT : 1;\r
///\r
/// [Bit 17] Page-size extensions.\r
///\r
- UINT32 PSE36 : 1;\r
+ UINT32 PSE36 : 1;\r
///\r
/// [Bit 19:18] Reserved.\r
///\r
- UINT32 Reserved2:2;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 20] No-execute page protection.\r
///\r
- UINT32 NX:1;\r
+ UINT32 NX : 1;\r
///\r
/// [Bit 21] Reserved.\r
///\r
- UINT32 Reserved3:1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 22] AMD Extensions to MMX instructions.\r
///\r
- UINT32 MmxExt:1;\r
+ UINT32 MmxExt : 1;\r
///\r
/// [Bit 23] MMX instructions.\r
///\r
- UINT32 MMX:1;\r
+ UINT32 MMX : 1;\r
///\r
/// [Bit 24] FXSAVE and FXRSTOR instructions.\r
///\r
- UINT32 FFSR:1;\r
+ UINT32 FFSR : 1;\r
///\r
/// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r
///\r
- UINT32 FFXSR:1;\r
+ UINT32 FFXSR : 1;\r
///\r
/// [Bit 26] 1-GByte large page support.\r
///\r
- UINT32 Page1GB:1;\r
+ UINT32 Page1GB : 1;\r
///\r
/// [Bit 27] RDTSCP instructions.\r
///\r
- UINT32 RDTSCP:1;\r
+ UINT32 RDTSCP : 1;\r
///\r
/// [Bit 28] Reserved.\r
///\r
- UINT32 Reserved4:1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 29] Long Mode.\r
///\r
- UINT32 LM:1;\r
+ UINT32 LM : 1;\r
///\r
/// [Bit 30] 3DNow! instructions.\r
///\r
- UINT32 ThreeDNow:1;\r
+ UINT32 ThreeDNow : 1;\r
///\r
/// [Bit 31] AMD Extensions to 3DNow! instructions.\r
///\r
- UINT32 ThreeDNowExt:1;\r
+ UINT32 ThreeDNowExt : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r
\r
-\r
/**\r
CPUID Linear Physical Address Size\r
\r
///\r
/// [Bits 7:0] Maximum physical byte address size in bits.\r
///\r
- UINT32 PhysicalAddressBits:8;\r
+ UINT32 PhysicalAddressBits : 8;\r
///\r
/// [Bits 15:8] Maximum linear byte address size in bits.\r
///\r
- UINT32 LinearAddressBits:8;\r
+ UINT32 LinearAddressBits : 8;\r
///\r
/// [Bits 23:16] Maximum guest physical byte address size in bits.\r
///\r
- UINT32 GuestPhysAddrSize:8;\r
+ UINT32 GuestPhysAddrSize : 8;\r
///\r
/// [Bit 31:24] Reserved.\r
///\r
- UINT32 Reserved:8;\r
+ UINT32 Reserved : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r
\r
/**\r
///\r
/// [Bits 0] Clear Zero Instruction.\r
///\r
- UINT32 CLZERO:1;\r
+ UINT32 CLZERO : 1;\r
///\r
/// [Bits 1] Instructions retired count support.\r
///\r
- UINT32 IRPerf:1;\r
+ UINT32 IRPerf : 1;\r
///\r
/// [Bits 2] Restore error pointers for XSave instructions.\r
///\r
- UINT32 XSaveErPtr:1;\r
+ UINT32 XSaveErPtr : 1;\r
///\r
/// [Bit 31:3] Reserved.\r
///\r
- UINT32 Reserved:29;\r
+ UINT32 Reserved : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r
\r
/**\r
///\r
/// [Bits 7:0] Number of threads - 1.\r
///\r
- UINT32 NC:8;\r
+ UINT32 NC : 8;\r
///\r
/// [Bit 11:8] Reserved.\r
///\r
- UINT32 Reserved1:4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 15:12] APIC ID size.\r
///\r
- UINT32 ApicIdCoreIdSize:4;\r
+ UINT32 ApicIdCoreIdSize : 4;\r
///\r
/// [Bits 17:16] Performance time-stamp counter size.\r
///\r
- UINT32 PerfTscSize:2;\r
+ UINT32 PerfTscSize : 2;\r
///\r
/// [Bit 31:18] Reserved.\r
///\r
- UINT32 Reserved2:14;\r
+ UINT32 Reserved2 : 14;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r
\r
-\r
/**\r
CPUID AMD Processor Topology\r
\r
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r
@retval EDX Reserved.\r
**/\r
-#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r
+#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E\r
\r
/**\r
CPUID AMD Processor Topology EAX for CPUID leaf\r
///\r
/// [Bit 31:0] Extended APIC Id.\r
///\r
- UINT32 ExtendedApicId;\r
+ UINT32 ExtendedApicId;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r
\r
/**\r
///\r
/// [Bits 7:0] Core Id.\r
///\r
- UINT32 CoreId:8;\r
+ UINT32 CoreId : 8;\r
///\r
/// [Bits 15:8] Threads per core.\r
///\r
- UINT32 ThreadsPerCore:8;\r
+ UINT32 ThreadsPerCore : 8;\r
///\r
/// [Bit 31:16] Reserved.\r
///\r
- UINT32 Reserved:16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r
\r
/**\r
///\r
/// [Bits 7:0] Node Id.\r
///\r
- UINT32 NodeId:8;\r
+ UINT32 NodeId : 8;\r
///\r
/// [Bits 10:8] Nodes per processor.\r
///\r
- UINT32 NodesPerProcessor:3;\r
+ UINT32 NodesPerProcessor : 3;\r
///\r
/// [Bit 31:11] Reserved.\r
///\r
- UINT32 Reserved:21;\r
+ UINT32 Reserved : 21;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r
\r
-\r
/**\r
CPUID Memory Encryption Information\r
\r
@endcode\r
**/\r
\r
-#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r
+#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F\r
\r
/**\r
CPUID Memory Encryption support information EAX for CPUID leaf\r
///\r
/// [Bit 0] Secure Memory Encryption (Sme) Support\r
///\r
- UINT32 SmeBit:1;\r
+ UINT32 SmeBit : 1;\r
\r
///\r
/// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r
///\r
- UINT32 SevBit:1;\r
+ UINT32 SevBit : 1;\r
\r
///\r
/// [Bit 2] Page flush MSR support\r
///\r
- UINT32 PageFlushMsrBit:1;\r
+ UINT32 PageFlushMsrBit : 1;\r
\r
///\r
/// [Bit 3] Encrypted state support\r
///\r
- UINT32 SevEsBit:1;\r
+ UINT32 SevEsBit : 1;\r
\r
///\r
/// [Bit 31:4] Reserved\r
///\r
- UINT32 ReservedBits:28;\r
+ UINT32 ReservedBits : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r
\r
/**\r
///\r
/// [Bit 5:0] Page table bit number used to enable memory encryption\r
///\r
- UINT32 PtePosBits:6;\r
+ UINT32 PtePosBits : 6;\r
\r
///\r
/// [Bit 11:6] Reduction of system physical address space bits when\r
/// memory encryption is enabled\r
///\r
- UINT32 ReducedPhysBits:5;\r
+ UINT32 ReducedPhysBits : 5;\r
\r
///\r
/// [Bit 31:12] Reserved\r
///\r
- UINT32 ReservedBits:21;\r
+ UINT32 ReservedBits : 21;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r
\r
/**\r
///\r
/// [Bit 31:0] Number of encrypted guest supported simultaneously\r
///\r
- UINT32 NumGuests;\r
+ UINT32 NumGuests;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r
\r
/**\r
///\r
/// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r
///\r
- UINT32 MinAsid;\r
+ UINT32 MinAsid;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r
\r
#endif\r
Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register\r
\r
**/\r
-#define MSR_SEV_ES_GHCB 0xc0010130\r
+#define MSR_SEV_ES_GHCB 0xc0010130\r
\r
/**\r
MSR information returned for #MSR_SEV_ES_GHCB\r
**/\r
typedef union {\r
struct {\r
- UINT32 Function:12;\r
- UINT32 Reserved1:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 Function : 12;\r
+ UINT32 Reserved1 : 20;\r
+ UINT32 Reserved2 : 32;\r
} GhcbInfo;\r
\r
struct {\r
- UINT8 Reserved[3];\r
- UINT8 SevEncryptionBitPos;\r
- UINT16 SevEsProtocolMin;\r
- UINT16 SevEsProtocolMax;\r
+ UINT8 Reserved[3];\r
+ UINT8 SevEncryptionBitPos;\r
+ UINT16 SevEsProtocolMin;\r
+ UINT16 SevEsProtocolMax;\r
} GhcbProtocol;\r
\r
struct {\r
- UINT32 Function:12;\r
- UINT32 ReasonCodeSet:4;\r
- UINT32 ReasonCode:8;\r
- UINT32 Reserved1:8;\r
- UINT32 Reserved2:32;\r
+ UINT32 Function : 12;\r
+ UINT32 ReasonCodeSet : 4;\r
+ UINT32 ReasonCode : 8;\r
+ UINT32 Reserved1 : 8;\r
+ UINT32 Reserved2 : 32;\r
} GhcbTerminate;\r
\r
struct {\r
- UINT64 Function:12;\r
- UINT64 Features:52;\r
+ UINT64 Function : 12;\r
+ UINT64 Features : 52;\r
} GhcbHypervisorFeatures;\r
\r
struct {\r
- UINT64 Function:12;\r
- UINT64 GuestFrameNumber:52;\r
+ UINT64 Function : 12;\r
+ UINT64 GuestFrameNumber : 52;\r
} GhcbGpaRegister;\r
\r
struct {\r
- UINT64 Function:12;\r
- UINT64 GuestFrameNumber:40;\r
- UINT64 Operation:4;\r
- UINT64 Reserved:8;\r
+ UINT64 Function : 12;\r
+ UINT64 GuestFrameNumber : 40;\r
+ UINT64 Operation : 4;\r
+ UINT64 Reserved : 8;\r
} SnpPageStateChangeRequest;\r
\r
struct {\r
- UINT32 Function:12;\r
- UINT32 Reserved:20;\r
- UINT32 ErrorCode;\r
+ UINT32 Function : 12;\r
+ UINT32 Reserved : 20;\r
+ UINT32 ErrorCode;\r
} SnpPageStateChangeResponse;\r
\r
- VOID *Ghcb;\r
+ VOID *Ghcb;\r
\r
- UINT64 GhcbPhysicalAddress;\r
+ UINT64 GhcbPhysicalAddress;\r
} MSR_SEV_ES_GHCB_REGISTER;\r
\r
-#define GHCB_INFO_SEV_INFO 1\r
-#define GHCB_INFO_SEV_INFO_GET 2\r
-#define GHCB_INFO_CPUID_REQUEST 4\r
-#define GHCB_INFO_CPUID_RESPONSE 5\r
-#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18\r
-#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE 19\r
-#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20\r
-#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE 21\r
-#define GHCB_HYPERVISOR_FEATURES_REQUEST 128\r
-#define GHCB_HYPERVISOR_FEATURES_RESPONSE 129\r
-#define GHCB_INFO_TERMINATE_REQUEST 256\r
-\r
-#define GHCB_TERMINATE_GHCB 0\r
-#define GHCB_TERMINATE_GHCB_GENERAL 0\r
-#define GHCB_TERMINATE_GHCB_PROTOCOL 1\r
+#define GHCB_INFO_SEV_INFO 1\r
+#define GHCB_INFO_SEV_INFO_GET 2\r
+#define GHCB_INFO_CPUID_REQUEST 4\r
+#define GHCB_INFO_CPUID_RESPONSE 5\r
+#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST 18\r
+#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE 19\r
+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST 20\r
+#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE 21\r
+#define GHCB_HYPERVISOR_FEATURES_REQUEST 128\r
+#define GHCB_HYPERVISOR_FEATURES_RESPONSE 129\r
+#define GHCB_INFO_TERMINATE_REQUEST 256\r
+\r
+#define GHCB_TERMINATE_GHCB 0\r
+#define GHCB_TERMINATE_GHCB_GENERAL 0\r
+#define GHCB_TERMINATE_GHCB_PROTOCOL 1\r
\r
/**\r
Secure Encrypted Virtualization (SEV) status register\r
\r
**/\r
-#define MSR_SEV_STATUS 0xc0010131\r
+#define MSR_SEV_STATUS 0xc0010131\r
\r
/**\r
MSR information returned for #MSR_SEV_STATUS\r
///\r
/// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r
///\r
- UINT32 SevBit:1;\r
+ UINT32 SevBit : 1;\r
\r
///\r
/// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r
///\r
- UINT32 SevEsBit:1;\r
+ UINT32 SevEsBit : 1;\r
\r
///\r
/// [Bit 2] Secure Nested Paging (SevSnp) is enabled\r
///\r
- UINT32 SevSnpBit:1;\r
+ UINT32 SevSnpBit : 1;\r
\r
- UINT32 Reserved2:29;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SEV_STATUS_REGISTER;\r
\r
#endif\r
#include <Library/DebugLib.h>\r
\r
#define UD_EXCEPTION 6\r
-#define GP_EXCEPTION 13\r
-#define VC_EXCEPTION 29\r
+#define GP_EXCEPTION 13\r
+#define VC_EXCEPTION 29\r
\r
-#define GHCB_VERSION_MIN 1\r
-#define GHCB_VERSION_MAX 1\r
+#define GHCB_VERSION_MIN 1\r
+#define GHCB_VERSION_MAX 1\r
\r
#define GHCB_STANDARD_USAGE 0\r
\r
//\r
// SVM Exit Codes\r
//\r
-#define SVM_EXIT_DR7_READ 0x27ULL\r
-#define SVM_EXIT_DR7_WRITE 0x37ULL\r
-#define SVM_EXIT_RDTSC 0x6EULL\r
-#define SVM_EXIT_RDPMC 0x6FULL\r
-#define SVM_EXIT_CPUID 0x72ULL\r
-#define SVM_EXIT_INVD 0x76ULL\r
-#define SVM_EXIT_IOIO_PROT 0x7BULL\r
-#define SVM_EXIT_MSR 0x7CULL\r
-#define SVM_EXIT_VMMCALL 0x81ULL\r
-#define SVM_EXIT_RDTSCP 0x87ULL\r
-#define SVM_EXIT_WBINVD 0x89ULL\r
-#define SVM_EXIT_MONITOR 0x8AULL\r
-#define SVM_EXIT_MWAIT 0x8BULL\r
-#define SVM_EXIT_NPF 0x400ULL\r
+#define SVM_EXIT_DR7_READ 0x27ULL\r
+#define SVM_EXIT_DR7_WRITE 0x37ULL\r
+#define SVM_EXIT_RDTSC 0x6EULL\r
+#define SVM_EXIT_RDPMC 0x6FULL\r
+#define SVM_EXIT_CPUID 0x72ULL\r
+#define SVM_EXIT_INVD 0x76ULL\r
+#define SVM_EXIT_IOIO_PROT 0x7BULL\r
+#define SVM_EXIT_MSR 0x7CULL\r
+#define SVM_EXIT_VMMCALL 0x81ULL\r
+#define SVM_EXIT_RDTSCP 0x87ULL\r
+#define SVM_EXIT_WBINVD 0x89ULL\r
+#define SVM_EXIT_MONITOR 0x8AULL\r
+#define SVM_EXIT_MWAIT 0x8BULL\r
+#define SVM_EXIT_NPF 0x400ULL\r
\r
//\r
// VMG Special Exit Codes\r
//\r
-#define SVM_EXIT_MMIO_READ 0x80000001ULL\r
-#define SVM_EXIT_MMIO_WRITE 0x80000002ULL\r
-#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL\r
-#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL\r
-#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL\r
-#define SVM_EXIT_SNP_PAGE_STATE_CHANGE 0x80000010ULL\r
-#define SVM_EXIT_SNP_AP_CREATION 0x80000013ULL\r
-#define SVM_EXIT_HYPERVISOR_FEATURES 0x8000FFFDULL\r
-#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL\r
+#define SVM_EXIT_MMIO_READ 0x80000001ULL\r
+#define SVM_EXIT_MMIO_WRITE 0x80000002ULL\r
+#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL\r
+#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL\r
+#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL\r
+#define SVM_EXIT_SNP_PAGE_STATE_CHANGE 0x80000010ULL\r
+#define SVM_EXIT_SNP_AP_CREATION 0x80000013ULL\r
+#define SVM_EXIT_HYPERVISOR_FEATURES 0x8000FFFDULL\r
+#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL\r
\r
//\r
// IOIO Exit Information\r
//\r
-#define IOIO_TYPE_STR BIT2\r
-#define IOIO_TYPE_IN 1\r
-#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR)\r
-#define IOIO_TYPE_OUT 0\r
-#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR)\r
-\r
-#define IOIO_REP BIT3\r
-\r
-#define IOIO_ADDR_64 BIT9\r
-#define IOIO_ADDR_32 BIT8\r
-#define IOIO_ADDR_16 BIT7\r
-\r
-#define IOIO_DATA_32 BIT6\r
-#define IOIO_DATA_16 BIT5\r
-#define IOIO_DATA_8 BIT4\r
-#define IOIO_DATA_MASK (BIT6 | BIT5 | BIT4)\r
-#define IOIO_DATA_OFFSET 4\r
+#define IOIO_TYPE_STR BIT2\r
+#define IOIO_TYPE_IN 1\r
+#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR)\r
+#define IOIO_TYPE_OUT 0\r
+#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR)\r
+\r
+#define IOIO_REP BIT3\r
+\r
+#define IOIO_ADDR_64 BIT9\r
+#define IOIO_ADDR_32 BIT8\r
+#define IOIO_ADDR_16 BIT7\r
+\r
+#define IOIO_DATA_32 BIT6\r
+#define IOIO_DATA_16 BIT5\r
+#define IOIO_DATA_8 BIT4\r
+#define IOIO_DATA_MASK (BIT6 | BIT5 | BIT4)\r
+#define IOIO_DATA_OFFSET 4\r
#define IOIO_DATA_BYTES(x) (((x) & IOIO_DATA_MASK) >> IOIO_DATA_OFFSET)\r
\r
-#define IOIO_SEG_ES 0\r
-#define IOIO_SEG_DS (BIT11 | BIT10)\r
+#define IOIO_SEG_ES 0\r
+#define IOIO_SEG_DS (BIT11 | BIT10)\r
\r
//\r
// AP Creation Information\r
#define SVM_VMGEXIT_SNP_AP_DESTROY 2\r
\r
typedef PACKED struct {\r
- UINT8 Reserved1[203];\r
- UINT8 Cpl;\r
- UINT8 Reserved8[300];\r
- UINT64 Rax;\r
- UINT8 Reserved4[264];\r
- UINT64 Rcx;\r
- UINT64 Rdx;\r
- UINT64 Rbx;\r
- UINT8 Reserved5[112];\r
- UINT64 SwExitCode;\r
- UINT64 SwExitInfo1;\r
- UINT64 SwExitInfo2;\r
- UINT64 SwScratch;\r
- UINT8 Reserved6[56];\r
- UINT64 XCr0;\r
- UINT8 ValidBitmap[16];\r
- UINT64 X87StateGpa;\r
- UINT8 Reserved7[1016];\r
+ UINT8 Reserved1[203];\r
+ UINT8 Cpl;\r
+ UINT8 Reserved8[300];\r
+ UINT64 Rax;\r
+ UINT8 Reserved4[264];\r
+ UINT64 Rcx;\r
+ UINT64 Rdx;\r
+ UINT64 Rbx;\r
+ UINT8 Reserved5[112];\r
+ UINT64 SwExitCode;\r
+ UINT64 SwExitInfo1;\r
+ UINT64 SwExitInfo2;\r
+ UINT64 SwScratch;\r
+ UINT8 Reserved6[56];\r
+ UINT64 XCr0;\r
+ UINT8 ValidBitmap[16];\r
+ UINT64 X87StateGpa;\r
+ UINT8 Reserved7[1016];\r
} GHCB_SAVE_AREA;\r
\r
typedef PACKED struct {\r
- GHCB_SAVE_AREA SaveArea;\r
- UINT8 SharedBuffer[2032];\r
- UINT8 Reserved1[10];\r
- UINT16 ProtocolVersion;\r
- UINT32 GhcbUsage;\r
+ GHCB_SAVE_AREA SaveArea;\r
+ UINT8 SharedBuffer[2032];\r
+ UINT8 Reserved1[10];\r
+ UINT16 ProtocolVersion;\r
+ UINT32 GhcbUsage;\r
} GHCB;\r
\r
#define GHCB_SAVE_AREA_QWORD_OFFSET(RegisterField) \\r
(OFFSET_OF (GHCB, SaveArea.RegisterField) / sizeof (UINT64))\r
\r
typedef enum {\r
- GhcbCpl = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),\r
- GhcbRax = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),\r
- GhcbRbx = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),\r
- GhcbRcx = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),\r
- GhcbRdx = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),\r
- GhcbXCr0 = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),\r
- GhcbSwExitCode = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),\r
- GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),\r
- GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),\r
- GhcbSwScratch = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),\r
+ GhcbCpl = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),\r
+ GhcbRax = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),\r
+ GhcbRbx = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),\r
+ GhcbRcx = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),\r
+ GhcbRdx = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),\r
+ GhcbXCr0 = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),\r
+ GhcbSwExitCode = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),\r
+ GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),\r
+ GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),\r
+ GhcbSwScratch = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),\r
} GHCB_REGISTER;\r
\r
typedef union {\r
struct {\r
- UINT32 Lower32Bits;\r
- UINT32 Upper32Bits;\r
+ UINT32 Lower32Bits;\r
+ UINT32 Upper32Bits;\r
} Elements;\r
\r
UINT64 Uint64;\r
\r
typedef union {\r
struct {\r
- UINT32 Vector:8;\r
- UINT32 Type:3;\r
- UINT32 ErrorCodeValid:1;\r
- UINT32 Rsvd:19;\r
- UINT32 Valid:1;\r
- UINT32 ErrorCode;\r
+ UINT32 Vector : 8;\r
+ UINT32 Type : 3;\r
+ UINT32 ErrorCodeValid : 1;\r
+ UINT32 Rsvd : 19;\r
+ UINT32 Valid : 1;\r
+ UINT32 ErrorCode;\r
} Elements;\r
\r
UINT64 Uint64;\r
//\r
// Hypervisor features\r
//\r
-#define GHCB_HV_FEATURES_SNP BIT0\r
-#define GHCB_HV_FEATURES_SNP_AP_CREATE (GHCB_HV_FEATURES_SNP | BIT1)\r
-#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)\r
-#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)\r
+#define GHCB_HV_FEATURES_SNP BIT0\r
+#define GHCB_HV_FEATURES_SNP_AP_CREATE (GHCB_HV_FEATURES_SNP | BIT1)\r
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION (GHCB_HV_FEATURES_SNP_AP_CREATE | BIT2)\r
+#define GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION_TIMER (GHCB_HV_FEATURES_SNP_RESTRICTED_INJECTION | BIT3)\r
\r
//\r
// SNP Page State Change.\r
//\r
// Note that the PSMASH and UNSMASH operations are not supported when using the MSR protocol.\r
//\r
-#define SNP_PAGE_STATE_PRIVATE 1\r
-#define SNP_PAGE_STATE_SHARED 2\r
-#define SNP_PAGE_STATE_PSMASH 3\r
-#define SNP_PAGE_STATE_UNSMASH 4\r
+#define SNP_PAGE_STATE_PRIVATE 1\r
+#define SNP_PAGE_STATE_SHARED 2\r
+#define SNP_PAGE_STATE_PSMASH 3\r
+#define SNP_PAGE_STATE_UNSMASH 4\r
\r
typedef struct {\r
- UINT64 CurrentPage:12;\r
- UINT64 GuestFrameNumber:40;\r
- UINT64 Operation:4;\r
- UINT64 PageSize:1;\r
- UINT64 Reserved:7;\r
+ UINT64 CurrentPage : 12;\r
+ UINT64 GuestFrameNumber : 40;\r
+ UINT64 Operation : 4;\r
+ UINT64 PageSize : 1;\r
+ UINT64 Reserved : 7;\r
} SNP_PAGE_STATE_ENTRY;\r
\r
typedef struct {\r
- UINT16 CurrentEntry;\r
- UINT16 EndEntry;\r
- UINT32 Reserved;\r
+ UINT16 CurrentEntry;\r
+ UINT16 EndEntry;\r
+ UINT32 Reserved;\r
} SNP_PAGE_STATE_HEADER;\r
\r
-#define SNP_PAGE_STATE_MAX_ENTRY 253\r
+#define SNP_PAGE_STATE_MAX_ENTRY 253\r
\r
typedef struct {\r
- SNP_PAGE_STATE_HEADER Header;\r
- SNP_PAGE_STATE_ENTRY Entry[SNP_PAGE_STATE_MAX_ENTRY];\r
+ SNP_PAGE_STATE_HEADER Header;\r
+ SNP_PAGE_STATE_ENTRY Entry[SNP_PAGE_STATE_MAX_ENTRY];\r
} SNP_PAGE_STATE_CHANGE_INFO;\r
\r
//\r
#define SEV_ES_RESET_CODE_SEGMENT_TYPE 0xA\r
#define SEV_ES_RESET_DATA_SEGMENT_TYPE 0x2\r
\r
-#define SEV_ES_RESET_LDT_TYPE 0x2\r
-#define SEV_ES_RESET_TSS_TYPE 0x3\r
+#define SEV_ES_RESET_LDT_TYPE 0x2\r
+#define SEV_ES_RESET_TSS_TYPE 0x3\r
\r
#pragma pack (1)\r
typedef union {\r
- struct {\r
- UINT16 Type:4;\r
- UINT16 Sbit:1;\r
- UINT16 Dpl:2;\r
- UINT16 Present:1;\r
- UINT16 Avl:1;\r
- UINT16 Reserved1:1;\r
- UINT16 Db:1;\r
- UINT16 Granularity:1;\r
- } Bits;\r
- UINT16 Uint16;\r
+ struct {\r
+ UINT16 Type : 4;\r
+ UINT16 Sbit : 1;\r
+ UINT16 Dpl : 2;\r
+ UINT16 Present : 1;\r
+ UINT16 Avl : 1;\r
+ UINT16 Reserved1 : 1;\r
+ UINT16 Db : 1;\r
+ UINT16 Granularity : 1;\r
+ } Bits;\r
+ UINT16 Uint16;\r
} SEV_ES_SEGMENT_REGISTER_ATTRIBUTES;\r
\r
typedef struct {\r
} SEV_ES_SEGMENT_REGISTER;\r
\r
typedef struct {\r
- SEV_ES_SEGMENT_REGISTER Es;\r
- SEV_ES_SEGMENT_REGISTER Cs;\r
- SEV_ES_SEGMENT_REGISTER Ss;\r
- SEV_ES_SEGMENT_REGISTER Ds;\r
- SEV_ES_SEGMENT_REGISTER Fs;\r
- SEV_ES_SEGMENT_REGISTER Gs;\r
- SEV_ES_SEGMENT_REGISTER Gdtr;\r
- SEV_ES_SEGMENT_REGISTER Ldtr;\r
- SEV_ES_SEGMENT_REGISTER Idtr;\r
- SEV_ES_SEGMENT_REGISTER Tr;\r
- UINT8 Reserved1[42];\r
- UINT8 Vmpl;\r
- UINT8 Reserved2[5];\r
- UINT64 Efer;\r
- UINT8 Reserved3[112];\r
- UINT64 Cr4;\r
- UINT8 Reserved4[8];\r
- UINT64 Cr0;\r
- UINT64 Dr7;\r
- UINT64 Dr6;\r
- UINT64 Rflags;\r
- UINT64 Rip;\r
- UINT8 Reserved5[232];\r
- UINT64 GPat;\r
- UINT8 Reserved6[320];\r
- UINT64 SevFeatures;\r
- UINT8 Reserved7[48];\r
- UINT64 XCr0;\r
- UINT8 Reserved8[24];\r
- UINT32 Mxcsr;\r
- UINT16 X87Ftw;\r
- UINT8 Reserved9[2];\r
- UINT16 X87Fcw;\r
+ SEV_ES_SEGMENT_REGISTER Es;\r
+ SEV_ES_SEGMENT_REGISTER Cs;\r
+ SEV_ES_SEGMENT_REGISTER Ss;\r
+ SEV_ES_SEGMENT_REGISTER Ds;\r
+ SEV_ES_SEGMENT_REGISTER Fs;\r
+ SEV_ES_SEGMENT_REGISTER Gs;\r
+ SEV_ES_SEGMENT_REGISTER Gdtr;\r
+ SEV_ES_SEGMENT_REGISTER Ldtr;\r
+ SEV_ES_SEGMENT_REGISTER Idtr;\r
+ SEV_ES_SEGMENT_REGISTER Tr;\r
+ UINT8 Reserved1[42];\r
+ UINT8 Vmpl;\r
+ UINT8 Reserved2[5];\r
+ UINT64 Efer;\r
+ UINT8 Reserved3[112];\r
+ UINT64 Cr4;\r
+ UINT8 Reserved4[8];\r
+ UINT64 Cr0;\r
+ UINT64 Dr7;\r
+ UINT64 Dr6;\r
+ UINT64 Rflags;\r
+ UINT64 Rip;\r
+ UINT8 Reserved5[232];\r
+ UINT64 GPat;\r
+ UINT8 Reserved6[320];\r
+ UINT64 SevFeatures;\r
+ UINT8 Reserved7[48];\r
+ UINT64 XCr0;\r
+ UINT8 Reserved8[24];\r
+ UINT32 Mxcsr;\r
+ UINT16 X87Ftw;\r
+ UINT8 Reserved9[2];\r
+ UINT16 X87Fcw;\r
} SEV_ES_SAVE_AREA;\r
#pragma pack ()\r
\r
@endcode\r
@note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_IA32_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_IA32_P5_MC_ADDR 0x00000000\r
\r
/**\r
See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.\r
@endcode\r
@note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_IA32_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_IA32_P5_MC_TYPE 0x00000001\r
\r
/**\r
See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced\r
@endcode\r
@note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.\r
**/\r
-#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
-\r
+#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006\r
\r
/**\r
See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /\r
@endcode\r
@note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.\r
**/\r
-#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
-\r
+#define MSR_IA32_TIME_STAMP_COUNTER 0x00000010\r
\r
/**\r
Platform ID (RO) The operating system can use this MSR to determine "slot"\r
@endcode\r
@note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_IA32_PLATFORM_ID 0x00000017\r
+#define MSR_IA32_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 18;\r
///\r
/// [Bits 52:50] Platform Id (RO) Contains information concerning the\r
/// intended platform for the processor.\r
/// 1 1 0 Processor Flag 6\r
/// 1 1 1 Processor Flag 7\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved3:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved3 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
06_01H.\r
\r
@endcode\r
@note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.\r
**/\r
-#define MSR_IA32_APIC_BASE 0x0000001B\r
+#define MSR_IA32_APIC_BASE 0x0000001B\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_APIC_BASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bit 8] BSP flag (R/W).\r
///\r
- UINT32 BSP:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 BSP : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display\r
/// Model 06_1AH.\r
///\r
- UINT32 EXTD:1;\r
+ UINT32 EXTD : 1;\r
///\r
/// [Bit 11] APIC Global Enable (R/W).\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bits 31:12] APIC Base (R/W).\r
///\r
- UINT32 ApicBase:20;\r
+ UINT32 ApicBase : 20;\r
///\r
/// [Bits 63:32] APIC Base (R/W).\r
///\r
- UINT32 ApicBaseHi:32;\r
+ UINT32 ApicBaseHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_APIC_BASE_REGISTER;\r
\r
-\r
/**\r
Control Features in Intel 64 Processor (R/W). If any one enumeration\r
condition for defined bit field holds.\r
@endcode\r
@note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
+#define MSR_IA32_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL\r
/// is not deasserted. If any one enumeration condition for defined bit\r
/// field position greater than bit 0 holds.\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
///\r
/// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a\r
/// system executive to use VMX in conjunction with SMX to support\r
/// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&\r
/// CPUID.01H:ECX[6] = 1.\r
///\r
- UINT32 EnableVmxInsideSmx:1;\r
+ UINT32 EnableVmxInsideSmx : 1;\r
///\r
/// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX\r
/// for system executive that do not require SMX. BIOS must set this bit\r
/// only when the CPUID function 1 returns VMX feature flag set (ECX bit\r
/// 5). If CPUID.01H:ECX[5] = 1.\r
///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 EnableVmxOutsideSmx : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit\r
/// in the field represents an enable control for a corresponding SENTER\r
/// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If\r
/// CPUID.01H:ECX[6] = 1.\r
///\r
- UINT32 SenterLocalFunctionEnables:7;\r
+ UINT32 SenterLocalFunctionEnables : 7;\r
///\r
/// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable\r
/// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit\r
/// 6] is set. If CPUID.01H:ECX[6] = 1.\r
///\r
- UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 SenterGlobalEnable : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to\r
/// enable runtime reconfiguration of SGX Launch Control via\r
/// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.\r
///\r
- UINT32 SgxLaunchControlEnable:1;\r
+ UINT32 SgxLaunchControlEnable : 1;\r
///\r
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX\r
/// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.\r
///\r
- UINT32 SgxEnable:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 SgxEnable : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 20] LMCE On (R/WL): When set, system software can program the\r
/// MSRs associated with LMCE to configure delivery of some machine check\r
/// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.\r
///\r
- UINT32 LmceOn:1;\r
- UINT32 Reserved4:11;\r
- UINT32 Reserved5:32;\r
+ UINT32 LmceOn : 1;\r
+ UINT32 Reserved4 : 11;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,\r
ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for\r
@endcode\r
@note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.\r
**/\r
-#define MSR_IA32_TSC_ADJUST 0x0000003B\r
-\r
+#define MSR_IA32_TSC_ADJUST 0x0000003B\r
\r
/**\r
BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a\r
@endcode\r
@note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.\r
**/\r
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
-\r
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079\r
\r
/**\r
BIOS Update Signature (RO) Returns the microcode update signature following\r
@endcode\r
@note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.\r
**/\r
-#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008B\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:32;\r
+ UINT32 Reserved : 32;\r
///\r
/// [Bits 63:32] Microcode update signature. This field contains the\r
/// signature of the currently loaded microcode update when read following\r
/// is no microcode update loaded. Another nonzero value will be the\r
/// signature.\r
///\r
- UINT32 MicrocodeUpdateSignature:32;\r
+ UINT32 MicrocodeUpdateSignature : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_BIOS_SIGN_ID_REGISTER;\r
\r
-\r
/**\r
IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the\r
SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the\r
MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
-#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
-#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
-#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C\r
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D\r
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E\r
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F\r
/// @}\r
\r
-\r
/**\r
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =\r
1.\r
@endcode\r
@note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.\r
**/\r
-#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
+#define MSR_IA32_SMM_MONITOR_CTL 0x0000009B\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL\r
/// if the bit is 0. This bit is cleared when the logical processor is\r
/// reset.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If\r
/// IA32_VMX_MISC[28].\r
///\r
- UINT32 BlockSmi:1;\r
- UINT32 Reserved2:9;\r
+ UINT32 BlockSmi : 1;\r
+ UINT32 Reserved2 : 9;\r
///\r
/// [Bits 31:12] MSEG Base (R/W).\r
///\r
- UINT32 MsegBase:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 MsegBase : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_SMM_MONITOR_CTL_REGISTER;\r
\r
/**\r
/// discover the MSEG revision identifier that a processor uses by reading\r
/// the VMX capability MSR IA32_VMX_MISC.\r
//\r
- UINT32 MsegHeaderRevision;\r
+ UINT32 MsegHeaderRevision;\r
///\r
/// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field\r
/// is the IA-32e mode SMM feature bit. It indicates whether the logical\r
/// processor will be in IA-32e mode after the STM is activated.\r
///\r
- UINT32 MonitorFeatures;\r
- UINT32 GdtrLimit;\r
- UINT32 GdtrBaseOffset;\r
- UINT32 CsSelector;\r
- UINT32 EipOffset;\r
- UINT32 EspOffset;\r
- UINT32 Cr3Offset;\r
+ UINT32 MonitorFeatures;\r
+ UINT32 GdtrLimit;\r
+ UINT32 GdtrBaseOffset;\r
+ UINT32 CsSelector;\r
+ UINT32 EipOffset;\r
+ UINT32 EspOffset;\r
+ UINT32 Cr3Offset;\r
///\r
/// Pad header so total size is 2KB\r
///\r
- UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
+ UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)];\r
} MSEG_HEADER;\r
\r
///\r
/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER\r
///\r
-#define STM_FEATURES_IA32E 0x1\r
+#define STM_FEATURES_IA32E 0x1\r
///\r
/// @}\r
///\r
@endcode\r
@note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.\r
**/\r
-#define MSR_IA32_SMBASE 0x0000009E\r
-\r
+#define MSR_IA32_SMBASE 0x0000009E\r
\r
/**\r
General Performance Counters (R/W).\r
MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_PMC0 0x000000C1\r
-#define MSR_IA32_PMC1 0x000000C2\r
-#define MSR_IA32_PMC2 0x000000C3\r
-#define MSR_IA32_PMC3 0x000000C4\r
-#define MSR_IA32_PMC4 0x000000C5\r
-#define MSR_IA32_PMC5 0x000000C6\r
-#define MSR_IA32_PMC6 0x000000C7\r
-#define MSR_IA32_PMC7 0x000000C8\r
+#define MSR_IA32_PMC0 0x000000C1\r
+#define MSR_IA32_PMC1 0x000000C2\r
+#define MSR_IA32_PMC2 0x000000C3\r
+#define MSR_IA32_PMC3 0x000000C4\r
+#define MSR_IA32_PMC4 0x000000C5\r
+#define MSR_IA32_PMC5 0x000000C6\r
+#define MSR_IA32_PMC6 0x000000C7\r
+#define MSR_IA32_PMC7 0x000000C8\r
/// @}\r
\r
-\r
/**\r
TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.\r
C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative\r
@endcode\r
@note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.\r
**/\r
-#define MSR_IA32_MPERF 0x000000E7\r
-\r
+#define MSR_IA32_MPERF 0x000000E7\r
\r
/**\r
Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =\r
@endcode\r
@note MSR_IA32_APERF is defined as IA32_APERF in SDM.\r
**/\r
-#define MSR_IA32_APERF 0x000000E8\r
-\r
+#define MSR_IA32_APERF 0x000000E8\r
\r
/**\r
MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".\r
@endcode\r
@note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.\r
**/\r
-#define MSR_IA32_MTRRCAP 0x000000FE\r
+#define MSR_IA32_MTRRCAP 0x000000FE\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MTRRCAP\r
/// [Bits 7:0] VCNT: The number of variable memory type ranges in the\r
/// processor.\r
///\r
- UINT32 VCNT:8;\r
+ UINT32 VCNT : 8;\r
///\r
/// [Bit 8] Fixed range MTRRs are supported when set.\r
///\r
- UINT32 FIX:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 FIX : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 10] WC Supported when set.\r
///\r
- UINT32 WC:1;\r
+ UINT32 WC : 1;\r
///\r
/// [Bit 11] SMRR Supported when set.\r
///\r
- UINT32 SMRR:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMRR : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MTRRCAP_REGISTER;\r
\r
-\r
/**\r
SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
\r
@endcode\r
@note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.\r
**/\r
-#define MSR_IA32_SYSENTER_CS 0x00000174\r
+#define MSR_IA32_SYSENTER_CS 0x00000174\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_SYSENTER_CS\r
///\r
/// [Bits 15:0] CS Selector.\r
///\r
- UINT32 CS:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
+ UINT32 CS : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_SYSENTER_CS_REGISTER;\r
\r
-\r
/**\r
SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
\r
@endcode\r
@note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.\r
**/\r
-#define MSR_IA32_SYSENTER_ESP 0x00000175\r
-\r
+#define MSR_IA32_SYSENTER_ESP 0x00000175\r
\r
/**\r
SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.\r
@endcode\r
@note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.\r
**/\r
-#define MSR_IA32_SYSENTER_EIP 0x00000176\r
-\r
+#define MSR_IA32_SYSENTER_EIP 0x00000176\r
\r
/**\r
Global Machine Check Capability (RO). Introduced at Display Family / Display\r
@endcode\r
@note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
-#define MSR_IA32_MCG_CAP 0x00000179\r
+#define MSR_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count: Number of reporting banks.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P: Extended machine check state registers are present\r
/// if this bit is set.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.\r
/// Introduced at Display Family / Display Model 06_01H.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P: Threshold-based error status register are present\r
/// if this bit is set.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state\r
/// registers present.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P: The processor supports software error recovery if\r
/// this bit is set.\r
///\r
- UINT32 MCG_SER_P:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 MCG_SER_P : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform\r
/// firmware to be invoked when an error is detected so that it may\r
/// check bank registers. Introduced at Display Family / Display Model\r
/// 06_3EH.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
+ UINT32 MCG_ELOG_P : 1;\r
///\r
/// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended\r
/// state in IA32_MCG_STATUS and associated MSR necessary to configure\r
/// Local Machine Check Exception (LMCE). Introduced at Display Family /\r
/// Display Model 06_3EH.\r
///\r
- UINT32 MCG_LMCE_P:1;\r
- UINT32 Reserved3:4;\r
- UINT32 Reserved4:32;\r
+ UINT32 MCG_LMCE_P : 1;\r
+ UINT32 Reserved3 : 4;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
Global Machine Check Status (R/W0). Introduced at Display Family / Display\r
Model 06_01H.\r
@endcode\r
@note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.\r
**/\r
-#define MSR_IA32_MCG_STATUS 0x0000017A\r
+#define MSR_IA32_MCG_STATUS 0x0000017A\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MCG_STATUS\r
/// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display\r
/// Model 06_01H.\r
///\r
- UINT32 RIPV:1;\r
+ UINT32 RIPV : 1;\r
///\r
/// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display\r
/// Model 06_01H.\r
///\r
- UINT32 EIPV:1;\r
+ UINT32 EIPV : 1;\r
///\r
/// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family\r
/// / Display Model 06_01H.\r
///\r
- UINT32 MCIP:1;\r
+ UINT32 MCIP : 1;\r
///\r
/// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.\r
///\r
- UINT32 LMCE_S:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 LMCE_S : 1;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MCG_STATUS_REGISTER;\r
\r
-\r
/**\r
Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.\r
\r
@endcode\r
@note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.\r
**/\r
-#define MSR_IA32_MCG_CTL 0x0000017B\r
-\r
+#define MSR_IA32_MCG_CTL 0x0000017B\r
\r
/**\r
Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.\r
MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_PERFEVTSEL0 0x00000186\r
-#define MSR_IA32_PERFEVTSEL1 0x00000187\r
-#define MSR_IA32_PERFEVTSEL2 0x00000188\r
-#define MSR_IA32_PERFEVTSEL3 0x00000189\r
+#define MSR_IA32_PERFEVTSEL0 0x00000186\r
+#define MSR_IA32_PERFEVTSEL1 0x00000187\r
+#define MSR_IA32_PERFEVTSEL2 0x00000188\r
+#define MSR_IA32_PERFEVTSEL3 0x00000189\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
/// detect on the selected event logic.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS: Counts while in privilege level is ring 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] Edge: Enables edge detection if set.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC: enables pin control.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT: enables interrupt on counter overflow.\r
///\r
- UINT32 INT:1;\r
+ UINT32 INT : 1;\r
///\r
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR.\r
///\r
- UINT32 ANY:1;\r
+ UINT32 ANY : 1;\r
///\r
/// [Bit 22] EN: enables the corresponding performance counter to commence\r
/// counting when this bit is set.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV: invert the CMASK.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
/// performance counter increments each cycle if the event count is\r
/// greater than or equal to the CMASK.\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERFEVTSEL_REGISTER;\r
\r
-\r
/**\r
Current performance state(P-State) operating point (RO). Introduced at\r
Display Family / Display Model 0F_03H.\r
@endcode\r
@note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.\r
**/\r
-#define MSR_IA32_PERF_STATUS 0x00000198\r
+#define MSR_IA32_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_STATUS\r
///\r
/// [Bits 15:0] Current performance State Value.\r
///\r
- UINT32 State:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
+ UINT32 State : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
(R/W). Introduced at Display Family / Display Model 0F_03H.\r
\r
@endcode\r
@note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.\r
**/\r
-#define MSR_IA32_PERF_CTL 0x00000199\r
+#define MSR_IA32_PERF_CTL 0x00000199\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_CTL\r
///\r
/// [Bits 15:0] Target performance State Value.\r
///\r
- UINT32 TargetState:16;\r
- UINT32 Reserved1:16;\r
+ UINT32 TargetState : 16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH\r
/// (Mobile only).\r
///\r
- UINT32 IDA:1;\r
- UINT32 Reserved2:31;\r
+ UINT32 IDA : 1;\r
+ UINT32 Reserved2 : 31;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_CTL_REGISTER;\r
\r
-\r
/**\r
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled\r
Clock Modulation.". If CPUID.01H:EDX[22] = 1.\r
@endcode\r
@note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
**/\r
-#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
+#define MSR_IA32_CLOCK_MODULATION 0x0000019A\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION\r
/// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If\r
/// CPUID.06H:EAX[5] = 1.\r
///\r
- UINT32 ExtendedOnDemandClockModulationDutyCycle:1;\r
+ UINT32 ExtendedOnDemandClockModulationDutyCycle : 1;\r
///\r
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded\r
/// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 OnDemandClockModulationDutyCycle:3;\r
+ UINT32 OnDemandClockModulationDutyCycle : 3;\r
///\r
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.\r
/// If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 OnDemandClockModulationEnable:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2:32;\r
+ UINT32 OnDemandClockModulationEnable : 1;\r
+ UINT32 Reserved1 : 27;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_CLOCK_MODULATION_REGISTER;\r
\r
-\r
/**\r
Thermal Interrupt Control (R/W) Enables and disables the generation of an\r
interrupt on temperature transitions detected with the processor's thermal\r
@endcode\r
@note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.\r
**/\r
-#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
+#define MSR_IA32_THERM_INTERRUPT 0x0000019B\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT\r
///\r
/// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 HighTempEnable:1;\r
+ UINT32 HighTempEnable : 1;\r
///\r
/// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 LowTempEnable:1;\r
+ UINT32 LowTempEnable : 1;\r
///\r
/// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 PROCHOT_Enable:1;\r
+ UINT32 PROCHOT_Enable : 1;\r
///\r
/// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 FORCEPR_Enable:1;\r
+ UINT32 FORCEPR_Enable : 1;\r
///\r
/// [Bit 4] Critical Temperature Interrupt Enable.\r
/// If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 CriticalTempEnable:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 CriticalTempEnable : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 Threshold1:7;\r
+ UINT32 Threshold1 : 7;\r
///\r
/// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 Threshold1Enable:1;\r
+ UINT32 Threshold1Enable : 1;\r
///\r
/// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 Threshold2:7;\r
+ UINT32 Threshold2 : 7;\r
///\r
/// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 Threshold2Enable:1;\r
+ UINT32 Threshold2Enable : 1;\r
///\r
/// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.\r
///\r
- UINT32 PowerLimitNotificationEnable:1;\r
- UINT32 Reserved2:7;\r
- UINT32 Reserved3:32;\r
+ UINT32 PowerLimitNotificationEnable : 1;\r
+ UINT32 Reserved2 : 7;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_THERM_INTERRUPT_REGISTER;\r
\r
-\r
/**\r
Thermal Status Information (RO) Contains status information about the\r
processor's thermal sensor and automatic thermal monitoring facilities. See\r
@endcode\r
@note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.\r
**/\r
-#define MSR_IA32_THERM_STATUS 0x0000019C\r
+#define MSR_IA32_THERM_STATUS 0x0000019C\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_THERM_STATUS\r
///\r
/// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 ThermalStatusLog:1;\r
+ UINT32 ThermalStatusLog : 1;\r
///\r
/// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 PROCHOT_FORCEPR_Event:1;\r
+ UINT32 PROCHOT_FORCEPR_Event : 1;\r
///\r
/// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 PROCHOT_FORCEPR_Log:1;\r
+ UINT32 PROCHOT_FORCEPR_Log : 1;\r
///\r
/// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 CriticalTempStatus:1;\r
+ UINT32 CriticalTempStatus : 1;\r
///\r
/// [Bit 5] Critical Temperature Status log (R/WC0).\r
/// If CPUID.01H:EDX[22] = 1.\r
///\r
- UINT32 CriticalTempStatusLog:1;\r
+ UINT32 CriticalTempStatusLog : 1;\r
///\r
/// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.\r
///\r
- UINT32 ThermalThreshold1Status:1;\r
+ UINT32 ThermalThreshold1Status : 1;\r
///\r
/// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
///\r
- UINT32 ThermalThreshold1Log:1;\r
+ UINT32 ThermalThreshold1Log : 1;\r
///\r
/// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.\r
///\r
- UINT32 ThermalThreshold2Status:1;\r
+ UINT32 ThermalThreshold2Status : 1;\r
///\r
/// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.\r
///\r
- UINT32 ThermalThreshold2Log:1;\r
+ UINT32 ThermalThreshold2Log : 1;\r
///\r
/// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.\r
///\r
- UINT32 PowerLimitStatus:1;\r
+ UINT32 PowerLimitStatus : 1;\r
///\r
/// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.\r
///\r
- UINT32 PowerLimitLog:1;\r
+ UINT32 PowerLimitLog : 1;\r
///\r
/// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
///\r
- UINT32 CurrentLimitStatus:1;\r
+ UINT32 CurrentLimitStatus : 1;\r
///\r
/// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
///\r
- UINT32 CurrentLimitLog:1;\r
+ UINT32 CurrentLimitLog : 1;\r
///\r
/// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.\r
///\r
- UINT32 CrossDomainLimitStatus:1;\r
+ UINT32 CrossDomainLimitStatus : 1;\r
///\r
/// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.\r
///\r
- UINT32 CrossDomainLimitLog:1;\r
+ UINT32 CrossDomainLimitLog : 1;\r
///\r
/// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.\r
///\r
- UINT32 DigitalReadout:7;\r
- UINT32 Reserved1:4;\r
+ UINT32 DigitalReadout : 7;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =\r
/// 1.\r
///\r
- UINT32 ResolutionInDegreesCelsius:4;\r
+ UINT32 ResolutionInDegreesCelsius : 4;\r
///\r
/// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.\r
///\r
- UINT32 ReadingValid:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 ReadingValid : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_THERM_STATUS_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MISC_ENABLE\r
/// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings\r
/// are disabled. Introduced at Display Family / Display Model 0F_0H.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
/// this bit enables the thermal control circuit (TCC) portion of the\r
/// field varies with product. See respective tables where default value is\r
/// listed. Introduced at Display Family / Display Model 0F_0H.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
/// monitoring enabled 0 = Performance monitoring disabled. Introduced at\r
/// Display Family / Display Model 0F_0H.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't\r
/// support branch trace storage (BTS) 0 = BTS is supported. Introduced at\r
/// Display Family / Display Model 0F_0H.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =\r
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display\r
/// Family / Display Model 06_0FH.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced\r
/// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep\r
/// Technology enabled. If CPUID.01H: ECX[7] =1.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the\r
/// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This\r
/// set to 0 may generate a #GP exception. Introduced at Display Family /\r
/// Display Model 0F_03H.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H\r
/// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup\r
/// depends on the availability of CPUID leaves greater than 2. Introduced\r
/// at Display Family / Display Model 0F_03H.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
/// disabled. xTPR messages are optional messages that allow the processor\r
/// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit\r
/// feature (XD Bit) is disabled and the XD Bit extended feature flag will\r
/// this bit to 1 when the XD Bit extended feature flag is set to 0 may\r
/// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.\r
\r
@endcode\r
@note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
-#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
+#define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS\r
/// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest\r
/// performance. 15 indicates preference to maximize energy saving.\r
///\r
- UINT32 PowerPolicyPreference:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 PowerPolicyPreference : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;\r
\r
-\r
/**\r
Package Thermal Status Information (RO) Contains status information about\r
the package's thermal sensor. See Section 14.8, "Package Level Thermal\r
@endcode\r
@note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.\r
**/\r
-#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
+#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS\r
///\r
/// [Bit 0] Pkg Thermal Status (RO):.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 1] Pkg Thermal Status Log (R/W):.\r
///\r
- UINT32 ThermalStatusLog:1;\r
+ UINT32 ThermalStatusLog : 1;\r
///\r
/// [Bit 2] Pkg PROCHOT # event (RO).\r
///\r
- UINT32 PROCHOT_Event:1;\r
+ UINT32 PROCHOT_Event : 1;\r
///\r
/// [Bit 3] Pkg PROCHOT # log (R/WC0).\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 4] Pkg Critical Temperature Status (RO).\r
///\r
- UINT32 CriticalTempStatus:1;\r
+ UINT32 CriticalTempStatus : 1;\r
///\r
/// [Bit 5] Pkg Critical Temperature Status log (R/WC0).\r
///\r
- UINT32 CriticalTempStatusLog:1;\r
+ UINT32 CriticalTempStatusLog : 1;\r
///\r
/// [Bit 6] Pkg Thermal Threshold #1 Status (RO).\r
///\r
- UINT32 ThermalThreshold1Status:1;\r
+ UINT32 ThermalThreshold1Status : 1;\r
///\r
/// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).\r
///\r
- UINT32 ThermalThreshold1Log:1;\r
+ UINT32 ThermalThreshold1Log : 1;\r
///\r
/// [Bit 8] Pkg Thermal Threshold #2 Status (RO).\r
///\r
- UINT32 ThermalThreshold2Status:1;\r
+ UINT32 ThermalThreshold2Status : 1;\r
///\r
/// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).\r
///\r
- UINT32 ThermalThreshold2Log:1;\r
+ UINT32 ThermalThreshold2Log : 1;\r
///\r
/// [Bit 10] Pkg Power Limitation Status (RO).\r
///\r
- UINT32 PowerLimitStatus:1;\r
+ UINT32 PowerLimitStatus : 1;\r
///\r
/// [Bit 11] Pkg Power Limitation log (R/WC0).\r
///\r
- UINT32 PowerLimitLog:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerLimitLog : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 22:16] Pkg Digital Readout (RO).\r
///\r
- UINT32 DigitalReadout:7;\r
- UINT32 Reserved2:9;\r
- UINT32 Reserved3:32;\r
+ UINT32 DigitalReadout : 7;\r
+ UINT32 Reserved2 : 9;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;\r
\r
-\r
/**\r
Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of\r
an interrupt on temperature transitions detected with the package's thermal\r
@endcode\r
@note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.\r
**/\r
-#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT\r
///\r
/// [Bit 0] Pkg High-Temperature Interrupt Enable.\r
///\r
- UINT32 HighTempEnable:1;\r
+ UINT32 HighTempEnable : 1;\r
///\r
/// [Bit 1] Pkg Low-Temperature Interrupt Enable.\r
///\r
- UINT32 LowTempEnable:1;\r
+ UINT32 LowTempEnable : 1;\r
///\r
/// [Bit 2] Pkg PROCHOT# Interrupt Enable.\r
///\r
- UINT32 PROCHOT_Enable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 PROCHOT_Enable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Pkg Overheat Interrupt Enable.\r
///\r
- UINT32 OverheatEnable:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 OverheatEnable : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 14:8] Pkg Threshold #1 Value.\r
///\r
- UINT32 Threshold1:7;\r
+ UINT32 Threshold1 : 7;\r
///\r
/// [Bit 15] Pkg Threshold #1 Interrupt Enable.\r
///\r
- UINT32 Threshold1Enable:1;\r
+ UINT32 Threshold1Enable : 1;\r
///\r
/// [Bits 22:16] Pkg Threshold #2 Value.\r
///\r
- UINT32 Threshold2:7;\r
+ UINT32 Threshold2 : 7;\r
///\r
/// [Bit 23] Pkg Threshold #2 Interrupt Enable.\r
///\r
- UINT32 Threshold2Enable:1;\r
+ UINT32 Threshold2Enable : 1;\r
///\r
/// [Bit 24] Pkg Power Limit Notification Enable.\r
///\r
- UINT32 PowerLimitNotificationEnable:1;\r
- UINT32 Reserved3:7;\r
- UINT32 Reserved4:32;\r
+ UINT32 PowerLimitNotificationEnable : 1;\r
+ UINT32 Reserved3 : 7;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;\r
\r
-\r
/**\r
Trace/Profile Resource Control (R/W). Introduced at Display Family / Display\r
Model 06_0EH.\r
@endcode\r
@note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.\r
**/\r
-#define MSR_IA32_DEBUGCTL 0x000001D9\r
+#define MSR_IA32_DEBUGCTL 0x000001D9\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_DEBUGCTL\r
/// running trace of the most recent branches taken by the processor in\r
/// the LBR stack. Introduced at Display Family / Display Model 06_01H.\r
///\r
- UINT32 LBR:1;\r
+ UINT32 LBR : 1;\r
///\r
/// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat\r
/// EFLAGS.TF as single-step on branches instead of single-step on\r
/// instructions. Introduced at Display Family / Display Model 06_01H.\r
///\r
- UINT32 BTF:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 BTF : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be\r
/// sent. Introduced at Display Family / Display Model 06_0EH.\r
///\r
- UINT32 TR:1;\r
+ UINT32 TR : 1;\r
///\r
/// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to\r
/// be logged in a BTS buffer. Introduced at Display Family / Display\r
/// Model 06_0EH.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular\r
/// fashion. When this bit is set, an interrupt is generated by the BTS\r
/// facility when the BTS buffer is full. Introduced at Display Family /\r
/// Display Model 06_0EH.\r
///\r
- UINT32 BTINT:1;\r
+ UINT32 BTINT : 1;\r
///\r
/// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.\r
/// Introduced at Display Family / Display Model 06_0FH.\r
///\r
- UINT32 BTS_OFF_OS:1;\r
+ UINT32 BTS_OFF_OS : 1;\r
///\r
/// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.\r
/// Introduced at Display Family / Display Model 06_0FH.\r
///\r
- UINT32 BTS_OFF_USR:1;\r
+ UINT32 BTS_OFF_USR : 1;\r
///\r
/// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a\r
/// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
///\r
- UINT32 FREEZE_LBRS_ON_PMI:1;\r
+ UINT32 FREEZE_LBRS_ON_PMI : 1;\r
///\r
/// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the\r
/// global counter control MSR are frozen (address 38FH) on a PMI request.\r
/// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.\r
///\r
- UINT32 FREEZE_PERFMON_ON_PMI:1;\r
+ UINT32 FREEZE_PERFMON_ON_PMI : 1;\r
///\r
/// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to\r
/// receive and generate PMI on behalf of the uncore. Introduced at\r
/// Display Family / Display Model 06_1AH.\r
///\r
- UINT32 ENABLE_UNCORE_PMI:1;\r
+ UINT32 ENABLE_UNCORE_PMI : 1;\r
///\r
/// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace\r
/// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.\r
///\r
- UINT32 FREEZE_WHILE_SMM:1;\r
+ UINT32 FREEZE_WHILE_SMM : 1;\r
///\r
/// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If\r
/// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).\r
///\r
- UINT32 RTM_DEBUG:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 RTM_DEBUG : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_DEBUGCTL_REGISTER;\r
\r
-\r
/**\r
SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.\r
If IA32_MTRRCAP.SMRR[11] = 1.\r
@endcode\r
@note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.\r
**/\r
-#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
+#define MSR_IA32_SMRR_PHYSBASE 0x000001F2\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE\r
///\r
/// [Bits 7:0] Type. Specifies memory type of the range.\r
///\r
- UINT32 Type:8;\r
- UINT32 Reserved1:4;\r
+ UINT32 Type : 8;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
///\r
- UINT32 PhysBase:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysBase : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_SMRR_PHYSBASE_REGISTER;\r
\r
-\r
/**\r
SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If\r
IA32_MTRRCAP[SMRR] = 1.\r
@endcode\r
@note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.\r
**/\r
-#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
+#define MSR_IA32_SMRR_PHYSMASK 0x000001F3\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Valid Enable range mask.\r
///\r
- UINT32 Valid:1;\r
+ UINT32 Valid : 1;\r
///\r
/// [Bits 31:12] PhysMask SMRR address range mask.\r
///\r
- UINT32 PhysMask:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysMask : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_SMRR_PHYSMASK_REGISTER;\r
\r
-\r
/**\r
DCA Capability (R). If CPUID.01H: ECX[18] = 1.\r
\r
@endcode\r
@note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.\r
**/\r
-#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
-\r
+#define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8\r
\r
/**\r
If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.\r
@endcode\r
@note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.\r
**/\r
-#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
-\r
+#define MSR_IA32_CPU_DCA_CAP 0x000001F9\r
\r
/**\r
DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.\r
@endcode\r
@note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.\r
**/\r
-#define MSR_IA32_DCA_0_CAP 0x000001FA\r
+#define MSR_IA32_DCA_0_CAP 0x000001FA\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_DCA_0_CAP\r
/// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no\r
/// defeatures are set.\r
///\r
- UINT32 DCA_ACTIVE:1;\r
+ UINT32 DCA_ACTIVE : 1;\r
///\r
/// [Bits 2:1] TRANSACTION.\r
///\r
- UINT32 TRANSACTION:2;\r
+ UINT32 TRANSACTION : 2;\r
///\r
/// [Bits 6:3] DCA_TYPE.\r
///\r
- UINT32 DCA_TYPE:4;\r
+ UINT32 DCA_TYPE : 4;\r
///\r
/// [Bits 10:7] DCA_QUEUE_SIZE.\r
///\r
- UINT32 DCA_QUEUE_SIZE:4;\r
- UINT32 Reserved1:2;\r
+ UINT32 DCA_QUEUE_SIZE : 4;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW\r
/// side-effect.\r
///\r
- UINT32 DCA_DELAY:4;\r
- UINT32 Reserved2:7;\r
+ UINT32 DCA_DELAY : 4;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.\r
///\r
- UINT32 SW_BLOCK:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 SW_BLOCK : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).\r
///\r
- UINT32 HW_BLOCK:1;\r
- UINT32 Reserved4:5;\r
- UINT32 Reserved5:32;\r
+ UINT32 HW_BLOCK : 1;\r
+ UINT32 Reserved4 : 5;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_DCA_0_CAP_REGISTER;\r
\r
-\r
/**\r
MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".\r
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
-#define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r
-#define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r
-#define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r
-#define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r
-#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r
-#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r
-#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r
-#define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r
-#define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r
+#define MSR_IA32_MTRR_PHYSBASE0 0x00000200\r
+#define MSR_IA32_MTRR_PHYSBASE1 0x00000202\r
+#define MSR_IA32_MTRR_PHYSBASE2 0x00000204\r
+#define MSR_IA32_MTRR_PHYSBASE3 0x00000206\r
+#define MSR_IA32_MTRR_PHYSBASE4 0x00000208\r
+#define MSR_IA32_MTRR_PHYSBASE5 0x0000020A\r
+#define MSR_IA32_MTRR_PHYSBASE6 0x0000020C\r
+#define MSR_IA32_MTRR_PHYSBASE7 0x0000020E\r
+#define MSR_IA32_MTRR_PHYSBASE8 0x00000210\r
+#define MSR_IA32_MTRR_PHYSBASE9 0x00000212\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] Type. Specifies memory type of the range.\r
///\r
- UINT32 Type:8;\r
- UINT32 Reserved1:4;\r
+ UINT32 Type : 8;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 31:12] PhysBase. MTRR physical Base Address.\r
///\r
- UINT32 PhysBase:20;\r
+ UINT32 PhysBase : 20;\r
///\r
/// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.\r
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
/// leaf 80000008H, the processor supports 36-bit physical address size,\r
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
///\r
- UINT32 PhysBaseHi:32;\r
+ UINT32 PhysBaseHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MTRR_PHYSBASE_REGISTER;\r
\r
-\r
/**\r
MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".\r
If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.\r
MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
-#define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r
-#define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r
-#define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r
-#define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r
-#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r
-#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r
-#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r
-#define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r
-#define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r
+#define MSR_IA32_MTRR_PHYSMASK0 0x00000201\r
+#define MSR_IA32_MTRR_PHYSMASK1 0x00000203\r
+#define MSR_IA32_MTRR_PHYSMASK2 0x00000205\r
+#define MSR_IA32_MTRR_PHYSMASK3 0x00000207\r
+#define MSR_IA32_MTRR_PHYSMASK4 0x00000209\r
+#define MSR_IA32_MTRR_PHYSMASK5 0x0000020B\r
+#define MSR_IA32_MTRR_PHYSMASK6 0x0000020D\r
+#define MSR_IA32_MTRR_PHYSMASK7 0x0000020F\r
+#define MSR_IA32_MTRR_PHYSMASK8 0x00000211\r
+#define MSR_IA32_MTRR_PHYSMASK9 0x00000213\r
/// @}\r
\r
/**\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Valid Enable range mask.\r
///\r
- UINT32 V:1;\r
+ UINT32 V : 1;\r
///\r
/// [Bits 31:12] PhysMask. MTRR address range mask.\r
///\r
- UINT32 PhysMask:20;\r
+ UINT32 PhysMask : 20;\r
///\r
/// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.\r
/// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the\r
/// leaf 80000008H, the processor supports 36-bit physical address size,\r
/// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.\r
///\r
- UINT32 PhysMaskHi:32;\r
+ UINT32 PhysMaskHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MTRR_PHYSMASK_REGISTER;\r
\r
-\r
/**\r
MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.\r
\r
@endcode\r
@note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
-\r
+#define MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
\r
/**\r
MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
-\r
+#define MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
\r
/**\r
MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
-\r
+#define MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
\r
/**\r
See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
-\r
+#define MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
\r
/**\r
MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
-\r
+#define MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
\r
/**\r
MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
-\r
+#define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
\r
/**\r
MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
-\r
+#define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
\r
/**\r
MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
-\r
+#define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
\r
/**\r
MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
-\r
+#define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
\r
/**\r
MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
-\r
+#define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
\r
/**\r
MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.\r
@endcode\r
@note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.\r
**/\r
-#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
-\r
+#define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
\r
/**\r
IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.\r
@endcode\r
@note MSR_IA32_PAT is defined as IA32_PAT in SDM.\r
**/\r
-#define MSR_IA32_PAT 0x00000277\r
+#define MSR_IA32_PAT 0x00000277\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PAT\r
///\r
/// [Bits 2:0] PA0.\r
///\r
- UINT32 PA0:3;\r
- UINT32 Reserved1:5;\r
+ UINT32 PA0 : 3;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 10:8] PA1.\r
///\r
- UINT32 PA1:3;\r
- UINT32 Reserved2:5;\r
+ UINT32 PA1 : 3;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bits 18:16] PA2.\r
///\r
- UINT32 PA2:3;\r
- UINT32 Reserved3:5;\r
+ UINT32 PA2 : 3;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bits 26:24] PA3.\r
///\r
- UINT32 PA3:3;\r
- UINT32 Reserved4:5;\r
+ UINT32 PA3 : 3;\r
+ UINT32 Reserved4 : 5;\r
///\r
/// [Bits 34:32] PA4.\r
///\r
- UINT32 PA4:3;\r
- UINT32 Reserved5:5;\r
+ UINT32 PA4 : 3;\r
+ UINT32 Reserved5 : 5;\r
///\r
/// [Bits 42:40] PA5.\r
///\r
- UINT32 PA5:3;\r
- UINT32 Reserved6:5;\r
+ UINT32 PA5 : 3;\r
+ UINT32 Reserved6 : 5;\r
///\r
/// [Bits 50:48] PA6.\r
///\r
- UINT32 PA6:3;\r
- UINT32 Reserved7:5;\r
+ UINT32 PA6 : 3;\r
+ UINT32 Reserved7 : 5;\r
///\r
/// [Bits 58:56] PA7.\r
///\r
- UINT32 PA7:3;\r
- UINT32 Reserved8:5;\r
+ UINT32 PA7 : 3;\r
+ UINT32 Reserved8 : 5;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PAT_REGISTER;\r
\r
-\r
/**\r
Provides the programming interface to use corrected MC error signaling\r
capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.\r
MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MC0_CTL2 0x00000280\r
-#define MSR_IA32_MC1_CTL2 0x00000281\r
-#define MSR_IA32_MC2_CTL2 0x00000282\r
-#define MSR_IA32_MC3_CTL2 0x00000283\r
-#define MSR_IA32_MC4_CTL2 0x00000284\r
-#define MSR_IA32_MC5_CTL2 0x00000285\r
-#define MSR_IA32_MC6_CTL2 0x00000286\r
-#define MSR_IA32_MC7_CTL2 0x00000287\r
-#define MSR_IA32_MC8_CTL2 0x00000288\r
-#define MSR_IA32_MC9_CTL2 0x00000289\r
-#define MSR_IA32_MC10_CTL2 0x0000028A\r
-#define MSR_IA32_MC11_CTL2 0x0000028B\r
-#define MSR_IA32_MC12_CTL2 0x0000028C\r
-#define MSR_IA32_MC13_CTL2 0x0000028D\r
-#define MSR_IA32_MC14_CTL2 0x0000028E\r
-#define MSR_IA32_MC15_CTL2 0x0000028F\r
-#define MSR_IA32_MC16_CTL2 0x00000290\r
-#define MSR_IA32_MC17_CTL2 0x00000291\r
-#define MSR_IA32_MC18_CTL2 0x00000292\r
-#define MSR_IA32_MC19_CTL2 0x00000293\r
-#define MSR_IA32_MC20_CTL2 0x00000294\r
-#define MSR_IA32_MC21_CTL2 0x00000295\r
-#define MSR_IA32_MC22_CTL2 0x00000296\r
-#define MSR_IA32_MC23_CTL2 0x00000297\r
-#define MSR_IA32_MC24_CTL2 0x00000298\r
-#define MSR_IA32_MC25_CTL2 0x00000299\r
-#define MSR_IA32_MC26_CTL2 0x0000029A\r
-#define MSR_IA32_MC27_CTL2 0x0000029B\r
-#define MSR_IA32_MC28_CTL2 0x0000029C\r
-#define MSR_IA32_MC29_CTL2 0x0000029D\r
-#define MSR_IA32_MC30_CTL2 0x0000029E\r
-#define MSR_IA32_MC31_CTL2 0x0000029F\r
+#define MSR_IA32_MC0_CTL2 0x00000280\r
+#define MSR_IA32_MC1_CTL2 0x00000281\r
+#define MSR_IA32_MC2_CTL2 0x00000282\r
+#define MSR_IA32_MC3_CTL2 0x00000283\r
+#define MSR_IA32_MC4_CTL2 0x00000284\r
+#define MSR_IA32_MC5_CTL2 0x00000285\r
+#define MSR_IA32_MC6_CTL2 0x00000286\r
+#define MSR_IA32_MC7_CTL2 0x00000287\r
+#define MSR_IA32_MC8_CTL2 0x00000288\r
+#define MSR_IA32_MC9_CTL2 0x00000289\r
+#define MSR_IA32_MC10_CTL2 0x0000028A\r
+#define MSR_IA32_MC11_CTL2 0x0000028B\r
+#define MSR_IA32_MC12_CTL2 0x0000028C\r
+#define MSR_IA32_MC13_CTL2 0x0000028D\r
+#define MSR_IA32_MC14_CTL2 0x0000028E\r
+#define MSR_IA32_MC15_CTL2 0x0000028F\r
+#define MSR_IA32_MC16_CTL2 0x00000290\r
+#define MSR_IA32_MC17_CTL2 0x00000291\r
+#define MSR_IA32_MC18_CTL2 0x00000292\r
+#define MSR_IA32_MC19_CTL2 0x00000293\r
+#define MSR_IA32_MC20_CTL2 0x00000294\r
+#define MSR_IA32_MC21_CTL2 0x00000295\r
+#define MSR_IA32_MC22_CTL2 0x00000296\r
+#define MSR_IA32_MC23_CTL2 0x00000297\r
+#define MSR_IA32_MC24_CTL2 0x00000298\r
+#define MSR_IA32_MC25_CTL2 0x00000299\r
+#define MSR_IA32_MC26_CTL2 0x0000029A\r
+#define MSR_IA32_MC27_CTL2 0x0000029B\r
+#define MSR_IA32_MC28_CTL2 0x0000029C\r
+#define MSR_IA32_MC29_CTL2 0x0000029D\r
+#define MSR_IA32_MC30_CTL2 0x0000029E\r
+#define MSR_IA32_MC31_CTL2 0x0000029F\r
/// @}\r
\r
/**\r
///\r
/// [Bits 14:0] Corrected error count threshold.\r
///\r
- UINT32 CorrectedErrorCountThreshold:15;\r
- UINT32 Reserved1:15;\r
+ UINT32 CorrectedErrorCountThreshold : 15;\r
+ UINT32 Reserved1 : 15;\r
///\r
/// [Bit 30] CMCI_EN.\r
///\r
- UINT32 CMCI_EN:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 CMCI_EN : 1;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MC_CTL2_REGISTER;\r
\r
-\r
/**\r
MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.\r
\r
@endcode\r
@note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.\r
**/\r
-#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
+#define MSR_IA32_MTRR_DEF_TYPE 0x000002FF\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE\r
///\r
/// [Bits 2:0] Default Memory Type.\r
///\r
- UINT32 Type:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Type : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] Fixed Range MTRR Enable.\r
///\r
- UINT32 FE:1;\r
+ UINT32 FE : 1;\r
///\r
/// [Bit 11] MTRR Enable.\r
///\r
- UINT32 E:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 E : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MTRR_DEF_TYPE_REGISTER;\r
\r
-\r
/**\r
Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If\r
CPUID.0AH: EDX[4:0] > 0.\r
@endcode\r
@note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.\r
**/\r
-#define MSR_IA32_FIXED_CTR0 0x00000309\r
-\r
+#define MSR_IA32_FIXED_CTR0 0x00000309\r
\r
/**\r
Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If\r
@endcode\r
@note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.\r
**/\r
-#define MSR_IA32_FIXED_CTR1 0x0000030A\r
-\r
+#define MSR_IA32_FIXED_CTR1 0x0000030A\r
\r
/**\r
Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If\r
@endcode\r
@note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.\r
**/\r
-#define MSR_IA32_FIXED_CTR2 0x0000030B\r
-\r
+#define MSR_IA32_FIXED_CTR2 0x0000030B\r
\r
/**\r
RO. If CPUID.01H: ECX[15] = 1.\r
@endcode\r
@note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.\r
**/\r
-#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
+#define MSR_IA32_PERF_CAPABILITIES 0x00000345\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES\r
///\r
/// [Bits 5:0] LBR format.\r
///\r
- UINT32 LBR_FMT:6;\r
+ UINT32 LBR_FMT : 6;\r
///\r
/// [Bit 6] PEBS Trap.\r
///\r
- UINT32 PEBS_TRAP:1;\r
+ UINT32 PEBS_TRAP : 1;\r
///\r
/// [Bit 7] PEBSSaveArchRegs.\r
///\r
- UINT32 PEBS_ARCH_REG:1;\r
+ UINT32 PEBS_ARCH_REG : 1;\r
///\r
/// [Bits 11:8] PEBS Record Format.\r
///\r
- UINT32 PEBS_REC_FMT:4;\r
+ UINT32 PEBS_REC_FMT : 4;\r
///\r
/// [Bit 12] 1: Freeze while SMM is supported.\r
///\r
- UINT32 SMM_FREEZE:1;\r
+ UINT32 SMM_FREEZE : 1;\r
///\r
/// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.\r
///\r
- UINT32 FW_WRITE:1;\r
- UINT32 Reserved1:18;\r
- UINT32 Reserved2:32;\r
+ UINT32 FW_WRITE : 1;\r
+ UINT32 Reserved1 : 18;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_CAPABILITIES_REGISTER;\r
\r
-\r
/**\r
Fixed-Function Performance Counter Control (R/W) Counter increments while\r
the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with\r
@endcode\r
@note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.\r
**/\r
-#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
+#define MSR_IA32_FIXED_CTR_CTRL 0x0000038D\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL\r
///\r
/// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.\r
///\r
- UINT32 EN0_OS:1;\r
+ UINT32 EN0_OS : 1;\r
///\r
/// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.\r
///\r
- UINT32 EN0_Usr:1;\r
+ UINT32 EN0_Usr : 1;\r
///\r
/// [Bit 2] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
///\r
- UINT32 AnyThread0:1;\r
+ UINT32 AnyThread0 : 1;\r
///\r
/// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.\r
///\r
- UINT32 EN0_PMI:1;\r
+ UINT32 EN0_PMI : 1;\r
///\r
/// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.\r
///\r
- UINT32 EN1_OS:1;\r
+ UINT32 EN1_OS : 1;\r
///\r
/// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.\r
///\r
- UINT32 EN1_Usr:1;\r
+ UINT32 EN1_Usr : 1;\r
///\r
/// [Bit 6] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
///\r
- UINT32 AnyThread1:1;\r
+ UINT32 AnyThread1 : 1;\r
///\r
/// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.\r
///\r
- UINT32 EN1_PMI:1;\r
+ UINT32 EN1_PMI : 1;\r
///\r
/// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.\r
///\r
- UINT32 EN2_OS:1;\r
+ UINT32 EN2_OS : 1;\r
///\r
/// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.\r
///\r
- UINT32 EN2_Usr:1;\r
+ UINT32 EN2_Usr : 1;\r
///\r
/// [Bit 10] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.\r
///\r
- UINT32 AnyThread2:1;\r
+ UINT32 AnyThread2 : 1;\r
///\r
/// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.\r
///\r
- UINT32 EN2_PMI:1;\r
- UINT32 Reserved1:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN2_PMI : 1;\r
+ UINT32 Reserved1 : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_FIXED_CTR_CTRL_REGISTER;\r
\r
-\r
/**\r
Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.\r
\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS\r
/// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:\r
/// EAX[15:8] > 0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:\r
/// EAX[15:8] > 1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:\r
/// EAX[15:8] > 2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:\r
/// EAX[15:8] > 3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If\r
/// CPUID.0AH: EAX[7:0] > 1.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If\r
/// CPUID.0AH: EAX[7:0] > 1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If\r
/// CPUID.0AH: EAX[7:0] > 1.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory\r
/// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
/// && IA32_RTIT_CTL.ToPA = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] LBR_Frz: LBRs are frozen due to -\r
/// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If\r
/// CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due\r
/// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU\r
/// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] ASCI: Data in the performance counters in the core PMU may\r
/// include contributions from the direct or indirect operation intel SGX\r
/// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:\r
/// EAX[7:0] > 2.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:\r
/// EAX[7:0] > 0.\r
///\r
- UINT32 OvfBuf:1;\r
+ UINT32 OvfBuf : 1;\r
///\r
/// [Bit 63] CondChgd: status bits of this register has changed. If\r
/// CPUID.0AH: EAX[7:0] > 0.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Global Performance Counter Control (R/W) Counter increments while the result\r
of ANDing respective enable bit in this MSR with the corresponding OS or USR\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
+#define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL\r
typedef union {\r
///\r
/// Individual bit fields\r
-///\r
+ ///\r
struct {\r
///\r
/// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.\r
/// Enable bitmask. Only the first n-1 bits are valid.\r
/// Bits n..31 are reserved.\r
///\r
- UINT32 EN_PMCn:32;\r
+ UINT32 EN_PMCn : 32;\r
///\r
/// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.\r
/// Enable bitmask. Only the first n-1 bits are valid.\r
/// Bits 31:n are reserved.\r
///\r
- UINT32 EN_FIXED_CTRn:32;\r
+ UINT32 EN_FIXED_CTRn : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >\r
0 && CPUID.0AH: EAX[7:0] <= 3.\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL\r
/// Clear bitmask. Only the first n-1 bits are valid.\r
/// Bits 31:n are reserved.\r
///\r
- UINT32 Ovf_PMCn:32;\r
+ UINT32 Ovf_PMCn : 32;\r
///\r
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
/// If CPUID.0AH: EDX[4:0] > n.\r
/// Clear bitmask. Only the first n-1 bits are valid.\r
/// Bits 22:n are reserved.\r
///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
+ UINT32 Ovf_FIXED_CTRn : 23;\r
///\r
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:5;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
/// Display Model 06_2EH.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
///\r
- UINT32 OvfBuf:1;\r
+ UINT32 OvfBuf : 1;\r
///\r
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
-\r
/**\r
Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:\r
EAX[7:0] > 3.\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+#define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET\r
/// Clear bitmask. Only the first n-1 bits are valid.\r
/// Bits 31:n are reserved.\r
///\r
- UINT32 Ovf_PMCn:32;\r
+ UINT32 Ovf_PMCn : 32;\r
///\r
/// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.\r
/// If CPUID.0AH: EDX[4:0] > n.\r
/// Clear bitmask. Only the first n-1 bits are valid.\r
/// Bits 22:n are reserved.\r
///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
+ UINT32 Ovf_FIXED_CTRn : 23;\r
///\r
/// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,\r
/// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /\r
/// Display Model 06_2EH.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.\r
///\r
- UINT32 OvfBuf:1;\r
+ UINT32 OvfBuf : 1;\r
///\r
/// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
-\r
/**\r
Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:\r
EAX[7:0] > 3.\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+#define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET\r
/// Set bitmask. Only the first n-1 bits are valid.\r
/// Bits 31:n are reserved.\r
///\r
- UINT32 Ovf_PMCn:32;\r
+ UINT32 Ovf_PMCn : 32;\r
///\r
/// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.\r
/// If CPUID.0AH: EAX[7:0] > n.\r
/// Set bitmask. Only the first n-1 bits are valid.\r
/// Bits 22:n are reserved.\r
///\r
- UINT32 Ovf_FIXED_CTRn:23;\r
+ UINT32 Ovf_FIXED_CTRn : 23;\r
///\r
/// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.\r
///\r
- UINT32 OvfBuf:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 OvfBuf : 1;\r
+ UINT32 Reserved3 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
-\r
/**\r
Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >\r
3.\r
@endcode\r
@note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.\r
**/\r
-#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
+#define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE\r
/// Status bitmask. Only the first n-1 bits are valid.\r
/// Bits 31:n are reserved.\r
///\r
- UINT32 IA32_PERFEVTSELn:32;\r
+ UINT32 IA32_PERFEVTSELn : 32;\r
///\r
/// [Bits 62:32] IA32_FIXED_CTRn in use.\r
/// If CPUID.0AH: EAX[7:0] > n.\r
/// Status bitmask. Only the first n-1 bits are valid.\r
/// Bits 30:n are reserved.\r
///\r
- UINT32 IA32_FIXED_CTRn:31;\r
+ UINT32 IA32_FIXED_CTRn : 31;\r
///\r
/// [Bit 63] PMI in use.\r
///\r
- UINT32 PMI:1;\r
+ UINT32 PMI : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;\r
\r
-\r
/**\r
PEBS Control (R/W).\r
\r
@endcode\r
@note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
+#define MSR_IA32_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE\r
/// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /\r
/// Display Model 06_0FH.\r
///\r
- UINT32 Enable:1;\r
+ UINT32 Enable : 1;\r
///\r
/// [Bits 3:1] Reserved or Model specific.\r
///\r
- UINT32 Reserved1:3;\r
- UINT32 Reserved2:28;\r
+ UINT32 Reserved1 : 3;\r
+ UINT32 Reserved2 : 28;\r
///\r
/// [Bits 35:32] Reserved or Model specific.\r
///\r
- UINT32 Reserved3:4;\r
- UINT32 Reserved4:28;\r
+ UINT32 Reserved3 : 4;\r
+ UINT32 Reserved4 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
MCn_CTL. If IA32_MCG_CAP.CNT > n.\r
\r
MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MC0_CTL 0x00000400\r
-#define MSR_IA32_MC1_CTL 0x00000404\r
-#define MSR_IA32_MC2_CTL 0x00000408\r
-#define MSR_IA32_MC3_CTL 0x0000040C\r
-#define MSR_IA32_MC4_CTL 0x00000410\r
-#define MSR_IA32_MC5_CTL 0x00000414\r
-#define MSR_IA32_MC6_CTL 0x00000418\r
-#define MSR_IA32_MC7_CTL 0x0000041C\r
-#define MSR_IA32_MC8_CTL 0x00000420\r
-#define MSR_IA32_MC9_CTL 0x00000424\r
-#define MSR_IA32_MC10_CTL 0x00000428\r
-#define MSR_IA32_MC11_CTL 0x0000042C\r
-#define MSR_IA32_MC12_CTL 0x00000430\r
-#define MSR_IA32_MC13_CTL 0x00000434\r
-#define MSR_IA32_MC14_CTL 0x00000438\r
-#define MSR_IA32_MC15_CTL 0x0000043C\r
-#define MSR_IA32_MC16_CTL 0x00000440\r
-#define MSR_IA32_MC17_CTL 0x00000444\r
-#define MSR_IA32_MC18_CTL 0x00000448\r
-#define MSR_IA32_MC19_CTL 0x0000044C\r
-#define MSR_IA32_MC20_CTL 0x00000450\r
-#define MSR_IA32_MC21_CTL 0x00000454\r
-#define MSR_IA32_MC22_CTL 0x00000458\r
-#define MSR_IA32_MC23_CTL 0x0000045C\r
-#define MSR_IA32_MC24_CTL 0x00000460\r
-#define MSR_IA32_MC25_CTL 0x00000464\r
-#define MSR_IA32_MC26_CTL 0x00000468\r
-#define MSR_IA32_MC27_CTL 0x0000046C\r
-#define MSR_IA32_MC28_CTL 0x00000470\r
+#define MSR_IA32_MC0_CTL 0x00000400\r
+#define MSR_IA32_MC1_CTL 0x00000404\r
+#define MSR_IA32_MC2_CTL 0x00000408\r
+#define MSR_IA32_MC3_CTL 0x0000040C\r
+#define MSR_IA32_MC4_CTL 0x00000410\r
+#define MSR_IA32_MC5_CTL 0x00000414\r
+#define MSR_IA32_MC6_CTL 0x00000418\r
+#define MSR_IA32_MC7_CTL 0x0000041C\r
+#define MSR_IA32_MC8_CTL 0x00000420\r
+#define MSR_IA32_MC9_CTL 0x00000424\r
+#define MSR_IA32_MC10_CTL 0x00000428\r
+#define MSR_IA32_MC11_CTL 0x0000042C\r
+#define MSR_IA32_MC12_CTL 0x00000430\r
+#define MSR_IA32_MC13_CTL 0x00000434\r
+#define MSR_IA32_MC14_CTL 0x00000438\r
+#define MSR_IA32_MC15_CTL 0x0000043C\r
+#define MSR_IA32_MC16_CTL 0x00000440\r
+#define MSR_IA32_MC17_CTL 0x00000444\r
+#define MSR_IA32_MC18_CTL 0x00000448\r
+#define MSR_IA32_MC19_CTL 0x0000044C\r
+#define MSR_IA32_MC20_CTL 0x00000450\r
+#define MSR_IA32_MC21_CTL 0x00000454\r
+#define MSR_IA32_MC22_CTL 0x00000458\r
+#define MSR_IA32_MC23_CTL 0x0000045C\r
+#define MSR_IA32_MC24_CTL 0x00000460\r
+#define MSR_IA32_MC25_CTL 0x00000464\r
+#define MSR_IA32_MC26_CTL 0x00000468\r
+#define MSR_IA32_MC27_CTL 0x0000046C\r
+#define MSR_IA32_MC28_CTL 0x00000470\r
/// @}\r
\r
-\r
/**\r
MCn_STATUS. If IA32_MCG_CAP.CNT > n.\r
\r
MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MC0_STATUS 0x00000401\r
-#define MSR_IA32_MC1_STATUS 0x00000405\r
-#define MSR_IA32_MC2_STATUS 0x00000409\r
-#define MSR_IA32_MC3_STATUS 0x0000040D\r
-#define MSR_IA32_MC4_STATUS 0x00000411\r
-#define MSR_IA32_MC5_STATUS 0x00000415\r
-#define MSR_IA32_MC6_STATUS 0x00000419\r
-#define MSR_IA32_MC7_STATUS 0x0000041D\r
-#define MSR_IA32_MC8_STATUS 0x00000421\r
-#define MSR_IA32_MC9_STATUS 0x00000425\r
-#define MSR_IA32_MC10_STATUS 0x00000429\r
-#define MSR_IA32_MC11_STATUS 0x0000042D\r
-#define MSR_IA32_MC12_STATUS 0x00000431\r
-#define MSR_IA32_MC13_STATUS 0x00000435\r
-#define MSR_IA32_MC14_STATUS 0x00000439\r
-#define MSR_IA32_MC15_STATUS 0x0000043D\r
-#define MSR_IA32_MC16_STATUS 0x00000441\r
-#define MSR_IA32_MC17_STATUS 0x00000445\r
-#define MSR_IA32_MC18_STATUS 0x00000449\r
-#define MSR_IA32_MC19_STATUS 0x0000044D\r
-#define MSR_IA32_MC20_STATUS 0x00000451\r
-#define MSR_IA32_MC21_STATUS 0x00000455\r
-#define MSR_IA32_MC22_STATUS 0x00000459\r
-#define MSR_IA32_MC23_STATUS 0x0000045D\r
-#define MSR_IA32_MC24_STATUS 0x00000461\r
-#define MSR_IA32_MC25_STATUS 0x00000465\r
-#define MSR_IA32_MC26_STATUS 0x00000469\r
-#define MSR_IA32_MC27_STATUS 0x0000046D\r
-#define MSR_IA32_MC28_STATUS 0x00000471\r
+#define MSR_IA32_MC0_STATUS 0x00000401\r
+#define MSR_IA32_MC1_STATUS 0x00000405\r
+#define MSR_IA32_MC2_STATUS 0x00000409\r
+#define MSR_IA32_MC3_STATUS 0x0000040D\r
+#define MSR_IA32_MC4_STATUS 0x00000411\r
+#define MSR_IA32_MC5_STATUS 0x00000415\r
+#define MSR_IA32_MC6_STATUS 0x00000419\r
+#define MSR_IA32_MC7_STATUS 0x0000041D\r
+#define MSR_IA32_MC8_STATUS 0x00000421\r
+#define MSR_IA32_MC9_STATUS 0x00000425\r
+#define MSR_IA32_MC10_STATUS 0x00000429\r
+#define MSR_IA32_MC11_STATUS 0x0000042D\r
+#define MSR_IA32_MC12_STATUS 0x00000431\r
+#define MSR_IA32_MC13_STATUS 0x00000435\r
+#define MSR_IA32_MC14_STATUS 0x00000439\r
+#define MSR_IA32_MC15_STATUS 0x0000043D\r
+#define MSR_IA32_MC16_STATUS 0x00000441\r
+#define MSR_IA32_MC17_STATUS 0x00000445\r
+#define MSR_IA32_MC18_STATUS 0x00000449\r
+#define MSR_IA32_MC19_STATUS 0x0000044D\r
+#define MSR_IA32_MC20_STATUS 0x00000451\r
+#define MSR_IA32_MC21_STATUS 0x00000455\r
+#define MSR_IA32_MC22_STATUS 0x00000459\r
+#define MSR_IA32_MC23_STATUS 0x0000045D\r
+#define MSR_IA32_MC24_STATUS 0x00000461\r
+#define MSR_IA32_MC25_STATUS 0x00000465\r
+#define MSR_IA32_MC26_STATUS 0x00000469\r
+#define MSR_IA32_MC27_STATUS 0x0000046D\r
+#define MSR_IA32_MC28_STATUS 0x00000471\r
/// @}\r
\r
-\r
/**\r
MCn_ADDR. If IA32_MCG_CAP.CNT > n.\r
\r
MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MC0_ADDR 0x00000402\r
-#define MSR_IA32_MC1_ADDR 0x00000406\r
-#define MSR_IA32_MC2_ADDR 0x0000040A\r
-#define MSR_IA32_MC3_ADDR 0x0000040E\r
-#define MSR_IA32_MC4_ADDR 0x00000412\r
-#define MSR_IA32_MC5_ADDR 0x00000416\r
-#define MSR_IA32_MC6_ADDR 0x0000041A\r
-#define MSR_IA32_MC7_ADDR 0x0000041E\r
-#define MSR_IA32_MC8_ADDR 0x00000422\r
-#define MSR_IA32_MC9_ADDR 0x00000426\r
-#define MSR_IA32_MC10_ADDR 0x0000042A\r
-#define MSR_IA32_MC11_ADDR 0x0000042E\r
-#define MSR_IA32_MC12_ADDR 0x00000432\r
-#define MSR_IA32_MC13_ADDR 0x00000436\r
-#define MSR_IA32_MC14_ADDR 0x0000043A\r
-#define MSR_IA32_MC15_ADDR 0x0000043E\r
-#define MSR_IA32_MC16_ADDR 0x00000442\r
-#define MSR_IA32_MC17_ADDR 0x00000446\r
-#define MSR_IA32_MC18_ADDR 0x0000044A\r
-#define MSR_IA32_MC19_ADDR 0x0000044E\r
-#define MSR_IA32_MC20_ADDR 0x00000452\r
-#define MSR_IA32_MC21_ADDR 0x00000456\r
-#define MSR_IA32_MC22_ADDR 0x0000045A\r
-#define MSR_IA32_MC23_ADDR 0x0000045E\r
-#define MSR_IA32_MC24_ADDR 0x00000462\r
-#define MSR_IA32_MC25_ADDR 0x00000466\r
-#define MSR_IA32_MC26_ADDR 0x0000046A\r
-#define MSR_IA32_MC27_ADDR 0x0000046E\r
-#define MSR_IA32_MC28_ADDR 0x00000472\r
+#define MSR_IA32_MC0_ADDR 0x00000402\r
+#define MSR_IA32_MC1_ADDR 0x00000406\r
+#define MSR_IA32_MC2_ADDR 0x0000040A\r
+#define MSR_IA32_MC3_ADDR 0x0000040E\r
+#define MSR_IA32_MC4_ADDR 0x00000412\r
+#define MSR_IA32_MC5_ADDR 0x00000416\r
+#define MSR_IA32_MC6_ADDR 0x0000041A\r
+#define MSR_IA32_MC7_ADDR 0x0000041E\r
+#define MSR_IA32_MC8_ADDR 0x00000422\r
+#define MSR_IA32_MC9_ADDR 0x00000426\r
+#define MSR_IA32_MC10_ADDR 0x0000042A\r
+#define MSR_IA32_MC11_ADDR 0x0000042E\r
+#define MSR_IA32_MC12_ADDR 0x00000432\r
+#define MSR_IA32_MC13_ADDR 0x00000436\r
+#define MSR_IA32_MC14_ADDR 0x0000043A\r
+#define MSR_IA32_MC15_ADDR 0x0000043E\r
+#define MSR_IA32_MC16_ADDR 0x00000442\r
+#define MSR_IA32_MC17_ADDR 0x00000446\r
+#define MSR_IA32_MC18_ADDR 0x0000044A\r
+#define MSR_IA32_MC19_ADDR 0x0000044E\r
+#define MSR_IA32_MC20_ADDR 0x00000452\r
+#define MSR_IA32_MC21_ADDR 0x00000456\r
+#define MSR_IA32_MC22_ADDR 0x0000045A\r
+#define MSR_IA32_MC23_ADDR 0x0000045E\r
+#define MSR_IA32_MC24_ADDR 0x00000462\r
+#define MSR_IA32_MC25_ADDR 0x00000466\r
+#define MSR_IA32_MC26_ADDR 0x0000046A\r
+#define MSR_IA32_MC27_ADDR 0x0000046E\r
+#define MSR_IA32_MC28_ADDR 0x00000472\r
/// @}\r
\r
-\r
/**\r
MCn_MISC. If IA32_MCG_CAP.CNT > n.\r
\r
MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.\r
@{\r
**/\r
-#define MSR_IA32_MC0_MISC 0x00000403\r
-#define MSR_IA32_MC1_MISC 0x00000407\r
-#define MSR_IA32_MC2_MISC 0x0000040B\r
-#define MSR_IA32_MC3_MISC 0x0000040F\r
-#define MSR_IA32_MC4_MISC 0x00000413\r
-#define MSR_IA32_MC5_MISC 0x00000417\r
-#define MSR_IA32_MC6_MISC 0x0000041B\r
-#define MSR_IA32_MC7_MISC 0x0000041F\r
-#define MSR_IA32_MC8_MISC 0x00000423\r
-#define MSR_IA32_MC9_MISC 0x00000427\r
-#define MSR_IA32_MC10_MISC 0x0000042B\r
-#define MSR_IA32_MC11_MISC 0x0000042F\r
-#define MSR_IA32_MC12_MISC 0x00000433\r
-#define MSR_IA32_MC13_MISC 0x00000437\r
-#define MSR_IA32_MC14_MISC 0x0000043B\r
-#define MSR_IA32_MC15_MISC 0x0000043F\r
-#define MSR_IA32_MC16_MISC 0x00000443\r
-#define MSR_IA32_MC17_MISC 0x00000447\r
-#define MSR_IA32_MC18_MISC 0x0000044B\r
-#define MSR_IA32_MC19_MISC 0x0000044F\r
-#define MSR_IA32_MC20_MISC 0x00000453\r
-#define MSR_IA32_MC21_MISC 0x00000457\r
-#define MSR_IA32_MC22_MISC 0x0000045B\r
-#define MSR_IA32_MC23_MISC 0x0000045F\r
-#define MSR_IA32_MC24_MISC 0x00000463\r
-#define MSR_IA32_MC25_MISC 0x00000467\r
-#define MSR_IA32_MC26_MISC 0x0000046B\r
-#define MSR_IA32_MC27_MISC 0x0000046F\r
-#define MSR_IA32_MC28_MISC 0x00000473\r
+#define MSR_IA32_MC0_MISC 0x00000403\r
+#define MSR_IA32_MC1_MISC 0x00000407\r
+#define MSR_IA32_MC2_MISC 0x0000040B\r
+#define MSR_IA32_MC3_MISC 0x0000040F\r
+#define MSR_IA32_MC4_MISC 0x00000413\r
+#define MSR_IA32_MC5_MISC 0x00000417\r
+#define MSR_IA32_MC6_MISC 0x0000041B\r
+#define MSR_IA32_MC7_MISC 0x0000041F\r
+#define MSR_IA32_MC8_MISC 0x00000423\r
+#define MSR_IA32_MC9_MISC 0x00000427\r
+#define MSR_IA32_MC10_MISC 0x0000042B\r
+#define MSR_IA32_MC11_MISC 0x0000042F\r
+#define MSR_IA32_MC12_MISC 0x00000433\r
+#define MSR_IA32_MC13_MISC 0x00000437\r
+#define MSR_IA32_MC14_MISC 0x0000043B\r
+#define MSR_IA32_MC15_MISC 0x0000043F\r
+#define MSR_IA32_MC16_MISC 0x00000443\r
+#define MSR_IA32_MC17_MISC 0x00000447\r
+#define MSR_IA32_MC18_MISC 0x0000044B\r
+#define MSR_IA32_MC19_MISC 0x0000044F\r
+#define MSR_IA32_MC20_MISC 0x00000453\r
+#define MSR_IA32_MC21_MISC 0x00000457\r
+#define MSR_IA32_MC22_MISC 0x0000045B\r
+#define MSR_IA32_MC23_MISC 0x0000045F\r
+#define MSR_IA32_MC24_MISC 0x00000463\r
+#define MSR_IA32_MC25_MISC 0x00000467\r
+#define MSR_IA32_MC26_MISC 0x0000046B\r
+#define MSR_IA32_MC27_MISC 0x0000046F\r
+#define MSR_IA32_MC28_MISC 0x00000473\r
/// @}\r
\r
-\r
/**\r
Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic\r
VMX Information.". If CPUID.01H:ECX.[5] = 1.\r
@endcode\r
@note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.\r
**/\r
-#define MSR_IA32_VMX_BASIC 0x00000480\r
+#define MSR_IA32_VMX_BASIC 0x00000480\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_VMX_BASIC\r
/// processors produced prior to this change, bit 31 of this MSR was read\r
/// as 0.\r
///\r
- UINT32 VmcsRevisonId:31;\r
- UINT32 MustBeZero:1;\r
+ UINT32 VmcsRevisonId : 31;\r
+ UINT32 MustBeZero : 1;\r
///\r
/// [Bit 44:32] Reports the number of bytes that software should allocate\r
/// for the VMXON region and any VMCS region. It is a value greater than\r
/// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).\r
///\r
- UINT32 VmcsSize:13;\r
- UINT32 Reserved1:3;\r
+ UINT32 VmcsSize : 13;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 48] Indicates the width of the physical addresses that may be used\r
/// for the VMXON region, each VMCS, and data structures referenced by\r
/// @note On processors that support Intel 64 architecture, the pointer\r
/// must not set bits beyond the processor's physical address width.\r
///\r
- UINT32 VmcsAddressWidth:1;\r
+ UINT32 VmcsAddressWidth : 1;\r
///\r
/// [Bit 49] If bit 49 is read as 1, the logical processor supports the\r
/// dual-monitor treatment of system-management interrupts and\r
/// system-management mode. See Section 34.15 for details of this treatment.\r
///\r
- UINT32 DualMonitor:1;\r
+ UINT32 DualMonitor : 1;\r
///\r
/// [Bit 53:50] report the memory type that should be used for the VMCS,\r
/// for data structures referenced by pointers in the VMCS (I/O bitmaps,\r
/// performance of software accesses to those structures to suffer.\r
///\r
///\r
- UINT32 MemoryType:4;\r
+ UINT32 MemoryType : 4;\r
///\r
/// [Bit 54] If bit 54 is read as 1, the processor reports information in\r
/// the VM-exit instruction-information field on VM exitsdue to execution\r
/// of the INS and OUTS instructions (see Section 27.2.4). This reporting\r
/// is done only if this bit is read as 1.\r
///\r
- UINT32 InsOutsReporting:1;\r
+ UINT32 InsOutsReporting : 1;\r
///\r
/// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may\r
/// be cleared to 0. See Appendix A.2 for details. It also reports support\r
/// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,\r
/// Appendix A.4, and Appendix A.5 for details.\r
///\r
- UINT32 VmxControls:1;\r
- UINT32 Reserved2:8;\r
+ UINT32 VmxControls : 1;\r
+ UINT32 Reserved2 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_VMX_BASIC_REGISTER;\r
\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
Capability Reporting Register of Pinbased VM-execution Controls (R/O) See\r
Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.\r
@endcode\r
@note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
-\r
+#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481\r
\r
/**\r
Capability Reporting Register of Primary Processor-based VM-execution\r
@endcode\r
@note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
-\r
+#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482\r
\r
/**\r
Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,\r
@endcode\r
@note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
-\r
+#define MSR_IA32_VMX_EXIT_CTLS 0x00000483\r
\r
/**\r
Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,\r
@endcode\r
@note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
-\r
+#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484\r
\r
/**\r
Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,\r
@endcode\r
@note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.\r
**/\r
-#define MSR_IA32_VMX_MISC 0x00000485\r
+#define MSR_IA32_VMX_MISC 0x00000485\r
\r
/**\r
MSR information returned for MSR index #IA32_VMX_MISC\r
/// Specifically, the VMX-preemption timer (if it is active) counts down by\r
/// 1 every time bit X in the TSC changes due to a TSC increment.\r
///\r
- UINT32 VmxTimerRatio:5;\r
+ UINT32 VmxTimerRatio : 5;\r
///\r
/// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA\r
/// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more\r
/// details. This bit is read as 1 on any logical processor that supports\r
/// the 1-setting of the "unrestricted guest" VM-execution control.\r
///\r
- UINT32 VmExitEferLma:1;\r
+ UINT32 VmExitEferLma : 1;\r
///\r
/// [Bit 6] reports (if set) the support for activity state 1 (HLT).\r
///\r
- UINT32 HltActivityStateSupported:1;\r
+ UINT32 HltActivityStateSupported : 1;\r
///\r
/// [Bit 7] reports (if set) the support for activity state 2 (shutdown).\r
///\r
- UINT32 ShutdownActivityStateSupported:1;\r
+ UINT32 ShutdownActivityStateSupported : 1;\r
///\r
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).\r
///\r
- UINT32 WaitForSipiActivityStateSupported:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 WaitForSipiActivityStateSupported : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used\r
/// in VMX operation. If the processor supports Intel PT but does not allow\r
/// operation) using the WRMSR instruction causes a general-protection\r
/// exception.\r
///\r
- UINT32 ProcessorTraceSupported:1;\r
+ UINT32 ProcessorTraceSupported : 1;\r
///\r
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-\r
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).\r
/// See Section 34.15.6.3.\r
///\r
- UINT32 SmBaseMsrSupported:1;\r
+ UINT32 SmBaseMsrSupported : 1;\r
///\r
/// [Bits 24:16] Indicate the number of CR3-target values supported by the\r
/// processor. This number is a value between 0 and 256, inclusive (bit 24\r
/// is set if and only if bits 23:16 are clear).\r
///\r
- UINT32 NumberOfCr3TargetValues:9;\r
+ UINT32 NumberOfCr3TargetValues : 9;\r
///\r
/// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum\r
/// number of MSRs that should appear in the VM-exit MSR-store list, the\r
/// limit is exceeded, undefined processor behavior may result (including a\r
/// machine check during the VMX transition).\r
///\r
- UINT32 MsrStoreListMaximum:3;\r
+ UINT32 MsrStoreListMaximum : 3;\r
///\r
/// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set\r
/// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1\r
/// (see Section 34.14.4).\r
///\r
- UINT32 BlockSmiSupported:1;\r
+ UINT32 BlockSmiSupported : 1;\r
///\r
/// [Bit 29] read as 1, software can use VMWRITE to write to any supported\r
/// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit\r
/// information fields.\r
///\r
- UINT32 VmWriteSupported:1;\r
+ UINT32 VmWriteSupported : 1;\r
///\r
/// [Bit 30] If read as 1, VM entry allows injection of a software\r
/// interrupt, software exception, or privileged software exception with an\r
/// instruction length of 0.\r
///\r
- UINT32 VmInjectSupported:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VmInjectSupported : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the\r
/// processor.\r
///\r
- UINT32 MsegRevisionIdentifier:32;\r
+ UINT32 MsegRevisionIdentifier : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} IA32_VMX_MISC_REGISTER;\r
\r
-\r
/**\r
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,\r
"VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.\r
@endcode\r
@note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.\r
**/\r
-#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
-\r
+#define MSR_IA32_VMX_CR0_FIXED0 0x00000486\r
\r
/**\r
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,\r
@endcode\r
@note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.\r
**/\r
-#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
-\r
+#define MSR_IA32_VMX_CR0_FIXED1 0x00000487\r
\r
/**\r
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,\r
@endcode\r
@note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.\r
**/\r
-#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
-\r
+#define MSR_IA32_VMX_CR4_FIXED0 0x00000488\r
\r
/**\r
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,\r
@endcode\r
@note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.\r
**/\r
-#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
-\r
+#define MSR_IA32_VMX_CR4_FIXED1 0x00000489\r
\r
/**\r
Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix\r
@endcode\r
@note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.\r
**/\r
-#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
-\r
+#define MSR_IA32_VMX_VMCS_ENUM 0x0000048A\r
\r
/**\r
Capability Reporting Register of Secondary Processor-based VM-execution\r
@endcode\r
@note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.\r
**/\r
-#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
-\r
+#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B\r
\r
/**\r
Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,\r
@endcode\r
@note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.\r
**/\r
-#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
-\r
+#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C\r
\r
/**\r
Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)\r
@endcode\r
@note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
-\r
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D\r
\r
/**\r
Capability Reporting Register of Primary Processor-based VM-execution Flex\r
@endcode\r
@note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
-\r
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E\r
\r
/**\r
Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix\r
@endcode\r
@note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
-\r
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F\r
\r
/**\r
Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix\r
@endcode\r
@note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.\r
**/\r
-#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
-\r
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490\r
\r
/**\r
Capability Reporting Register of VMfunction Controls (R/O). If(\r
@endcode\r
@note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.\r
**/\r
-#define MSR_IA32_VMX_VMFUNC 0x00000491\r
-\r
+#define MSR_IA32_VMX_VMFUNC 0x00000491\r
\r
/**\r
Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&\r
MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_A_PMC0 0x000004C1\r
-#define MSR_IA32_A_PMC1 0x000004C2\r
-#define MSR_IA32_A_PMC2 0x000004C3\r
-#define MSR_IA32_A_PMC3 0x000004C4\r
-#define MSR_IA32_A_PMC4 0x000004C5\r
-#define MSR_IA32_A_PMC5 0x000004C6\r
-#define MSR_IA32_A_PMC6 0x000004C7\r
-#define MSR_IA32_A_PMC7 0x000004C8\r
+#define MSR_IA32_A_PMC0 0x000004C1\r
+#define MSR_IA32_A_PMC1 0x000004C2\r
+#define MSR_IA32_A_PMC2 0x000004C3\r
+#define MSR_IA32_A_PMC3 0x000004C4\r
+#define MSR_IA32_A_PMC4 0x000004C5\r
+#define MSR_IA32_A_PMC5 0x000004C6\r
+#define MSR_IA32_A_PMC6 0x000004C7\r
+#define MSR_IA32_A_PMC7 0x000004C8\r
/// @}\r
\r
-\r
/**\r
(R/W). If IA32_MCG_CAP.LMCE_P =1.\r
\r
@endcode\r
@note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.\r
**/\r
-#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
+#define MSR_IA32_MCG_EXT_CTL 0x000004D0\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL\r
///\r
/// [Bit 0] LMCE_EN.\r
///\r
- UINT32 LMCE_EN:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 LMCE_EN : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_MCG_EXT_CTL_REGISTER;\r
\r
-\r
/**\r
Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,\r
ECX=0H): EBX[2] = 1.\r
@endcode\r
@note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.\r
**/\r
-#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
+#define MSR_IA32_SGX_SVN_STATUS 0x00000500\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS\r
/// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated\r
/// Code Modules (ACMs)".\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:15;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 15;\r
///\r
/// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with\r
/// Authenticated Code Modules (ACMs)".\r
///\r
- UINT32 SGX_SVN_SINIT:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 SGX_SVN_SINIT : 8;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_SGX_SVN_STATUS_REGISTER;\r
\r
-\r
/**\r
Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)\r
&& ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)\r
@endcode\r
@note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.\r
**/\r
-#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:7;\r
+ UINT32 Reserved : 7;\r
///\r
/// [Bits 31:7] Base physical address.\r
///\r
- UINT32 Base:25;\r
+ UINT32 Base : 25;\r
///\r
/// [Bits 63:32] Base physical address.\r
///\r
- UINT32 BaseHi:32;\r
+ UINT32 BaseHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;\r
\r
-\r
/**\r
Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,\r
ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)\r
@endcode\r
@note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.\r
**/\r
-#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
+#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:7;\r
+ UINT32 Reserved : 7;\r
///\r
/// [Bits 31:7] MaskOrTableOffset.\r
///\r
- UINT32 MaskOrTableOffset:25;\r
+ UINT32 MaskOrTableOffset : 25;\r
///\r
/// [Bits 63:32] Output Offset.\r
///\r
- UINT32 OutputOffset:32;\r
+ UINT32 OutputOffset : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;\r
\r
/**\r
///\r
/// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 END:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 END : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 INT:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 INT : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 STOP:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 STOP : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 6:9] Indicates the size of the associated output region. See Section\r
/// 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 Size:4;\r
- UINT32 Reserved4:2;\r
+ UINT32 Size : 4;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 12:31] Output Region Base Physical Address low part.\r
/// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.\r
/// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 Base:20;\r
+ UINT32 Base : 20;\r
///\r
/// [Bit 32:63] Output Region Base Physical Address high part.\r
/// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.\r
/// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.\r
/// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".\r
///\r
- UINT32 BaseHi:32;\r
+ UINT32 BaseHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} RTIT_TOPA_TABLE_ENTRY;\r
\r
///\r
@endcode\r
@note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
**/\r
-#define MSR_IA32_RTIT_CTL 0x00000570\r
+#define MSR_IA32_RTIT_CTL 0x00000570\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
///\r
/// [Bit 0] TraceEn.\r
///\r
- UINT32 TraceEn:1;\r
+ UINT32 TraceEn : 1;\r
///\r
/// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
///\r
- UINT32 CYCEn:1;\r
+ UINT32 CYCEn : 1;\r
///\r
/// [Bit 2] OS.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 3] User.\r
///\r
- UINT32 User:1;\r
+ UINT32 User : 1;\r
///\r
/// [Bit 4] PwrEvtEn.\r
///\r
- UINT32 PwrEvtEn:1;\r
+ UINT32 PwrEvtEn : 1;\r
///\r
/// [Bit 5] FUPonPTW.\r
///\r
- UINT32 FUPonPTW:1;\r
+ UINT32 FUPonPTW : 1;\r
///\r
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
///\r
- UINT32 FabricEn:1;\r
+ UINT32 FabricEn : 1;\r
///\r
/// [Bit 7] CR3 filter.\r
///\r
- UINT32 CR3:1;\r
+ UINT32 CR3 : 1;\r
///\r
/// [Bit 8] ToPA.\r
///\r
- UINT32 ToPA:1;\r
+ UINT32 ToPA : 1;\r
///\r
/// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
///\r
- UINT32 MTCEn:1;\r
+ UINT32 MTCEn : 1;\r
///\r
/// [Bit 10] TSCEn.\r
///\r
- UINT32 TSCEn:1;\r
+ UINT32 TSCEn : 1;\r
///\r
/// [Bit 11] DisRETC.\r
///\r
- UINT32 DisRETC:1;\r
+ UINT32 DisRETC : 1;\r
///\r
/// [Bit 12] PTWEn.\r
///\r
- UINT32 PTWEn:1;\r
+ UINT32 PTWEn : 1;\r
///\r
/// [Bit 13] BranchEn.\r
///\r
- UINT32 BranchEn:1;\r
+ UINT32 BranchEn : 1;\r
///\r
/// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).\r
///\r
- UINT32 MTCFreq:4;\r
- UINT32 Reserved3:1;\r
+ UINT32 MTCFreq : 4;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
///\r
- UINT32 CYCThresh:4;\r
- UINT32 Reserved4:1;\r
+ UINT32 CYCThresh : 4;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).\r
///\r
- UINT32 PSBFreq:4;\r
- UINT32 Reserved5:4;\r
+ UINT32 PSBFreq : 4;\r
+ UINT32 Reserved5 : 4;\r
///\r
/// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).\r
///\r
- UINT32 ADDR0_CFG:4;\r
+ UINT32 ADDR0_CFG : 4;\r
///\r
/// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).\r
///\r
- UINT32 ADDR1_CFG:4;\r
+ UINT32 ADDR1_CFG : 4;\r
///\r
/// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).\r
///\r
- UINT32 ADDR2_CFG:4;\r
+ UINT32 ADDR2_CFG : 4;\r
///\r
/// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).\r
///\r
- UINT32 ADDR3_CFG:4;\r
- UINT32 Reserved6:16;\r
+ UINT32 ADDR3_CFG : 4;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_CTL_REGISTER;\r
\r
-\r
/**\r
Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
\r
@endcode\r
@note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.\r
**/\r
-#define MSR_IA32_RTIT_STATUS 0x00000571\r
+#define MSR_IA32_RTIT_STATUS 0x00000571\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_STATUS\r
/// [Bit 0] FilterEn, (writes ignored).\r
/// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).\r
///\r
- UINT32 FilterEn:1;\r
+ UINT32 FilterEn : 1;\r
///\r
/// [Bit 1] ContexEn, (writes ignored).\r
///\r
- UINT32 ContexEn:1;\r
+ UINT32 ContexEn : 1;\r
///\r
/// [Bit 2] TriggerEn, (writes ignored).\r
///\r
- UINT32 TriggerEn:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 TriggerEn : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Error.\r
///\r
- UINT32 Error:1;\r
+ UINT32 Error : 1;\r
///\r
/// [Bit 5] Stopped.\r
///\r
- UINT32 Stopped:1;\r
- UINT32 Reserved2:26;\r
+ UINT32 Stopped : 1;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).\r
///\r
- UINT32 PacketByteCnt:17;\r
- UINT32 Reserved3:15;\r
+ UINT32 PacketByteCnt : 17;\r
+ UINT32 Reserved3 : 15;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_STATUS_REGISTER;\r
\r
-\r
/**\r
Trace Filter CR3 Match Register (R/W).\r
If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).\r
@endcode\r
@note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.\r
**/\r
-#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:5;\r
+ UINT32 Reserved : 5;\r
///\r
/// [Bits 31:5] CR3[63:5] value to match.\r
///\r
- UINT32 Cr3:27;\r
+ UINT32 Cr3 : 27;\r
///\r
/// [Bits 63:32] CR3[63:5] value to match.\r
///\r
- UINT32 Cr3Hi:32;\r
+ UINT32 Cr3Hi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_CR3_MATCH_REGISTER;\r
\r
-\r
/**\r
Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
\r
MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.\r
@{\r
**/\r
-#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
-#define MSR_IA32_RTIT_ADDR1_A 0x00000582\r
-#define MSR_IA32_RTIT_ADDR2_A 0x00000584\r
-#define MSR_IA32_RTIT_ADDR3_A 0x00000586\r
+#define MSR_IA32_RTIT_ADDR0_A 0x00000580\r
+#define MSR_IA32_RTIT_ADDR1_A 0x00000582\r
+#define MSR_IA32_RTIT_ADDR2_A 0x00000584\r
+#define MSR_IA32_RTIT_ADDR3_A 0x00000586\r
/// @}\r
\r
-\r
/**\r
Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).\r
\r
MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.\r
@{\r
**/\r
-#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
-#define MSR_IA32_RTIT_ADDR1_B 0x00000583\r
-#define MSR_IA32_RTIT_ADDR2_B 0x00000585\r
-#define MSR_IA32_RTIT_ADDR3_B 0x00000587\r
+#define MSR_IA32_RTIT_ADDR0_B 0x00000581\r
+#define MSR_IA32_RTIT_ADDR1_B 0x00000583\r
+#define MSR_IA32_RTIT_ADDR2_B 0x00000585\r
+#define MSR_IA32_RTIT_ADDR3_B 0x00000587\r
/// @}\r
\r
-\r
/**\r
MSR information returned for MSR indexes\r
#MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and\r
///\r
/// [Bits 31:0] Virtual Address.\r
///\r
- UINT32 VirtualAddress:32;\r
+ UINT32 VirtualAddress : 32;\r
///\r
/// [Bits 47:32] Virtual Address.\r
///\r
- UINT32 VirtualAddressHi:16;\r
+ UINT32 VirtualAddressHi : 16;\r
///\r
/// [Bits 63:48] SignExt_VA.\r
///\r
- UINT32 SignExt_VA:16;\r
+ UINT32 SignExt_VA : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_RTIT_ADDR_REGISTER;\r
\r
-\r
/**\r
DS Save Area (R/W) Points to the linear address of the first byte of the DS\r
buffer management area, which is used to manage the BTS and PEBS buffers.\r
@endcode\r
@note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.\r
**/\r
-#define MSR_IA32_DS_AREA 0x00000600\r
-\r
+#define MSR_IA32_DS_AREA 0x00000600\r
\r
/**\r
TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =\r
@endcode\r
@note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.\r
**/\r
-#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
-\r
+#define MSR_IA32_TSC_DEADLINE 0x000006E0\r
\r
/**\r
Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.\r
@endcode\r
@note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.\r
**/\r
-#define MSR_IA32_PM_ENABLE 0x00000770\r
+#define MSR_IA32_PM_ENABLE 0x00000770\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PM_ENABLE\r
/// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If\r
/// CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 HWP_ENABLE:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 HWP_ENABLE : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PM_ENABLE_REGISTER;\r
\r
-\r
/**\r
HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.\r
\r
@endcode\r
@note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.\r
**/\r
-#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
+#define MSR_IA32_HWP_CAPABILITIES 0x00000771\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES\r
/// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance\r
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Highest_Performance:8;\r
+ UINT32 Highest_Performance : 8;\r
///\r
/// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP\r
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Guaranteed_Performance:8;\r
+ UINT32 Guaranteed_Performance : 8;\r
///\r
/// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP\r
/// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Most_Efficient_Performance:8;\r
+ UINT32 Most_Efficient_Performance : 8;\r
///\r
/// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance\r
/// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Lowest_Performance:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Lowest_Performance : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_HWP_CAPABILITIES_REGISTER;\r
\r
-\r
/**\r
Power Management Control Hints for All Logical Processors in a Package\r
(R/W). If CPUID.06H:EAX.[11] = 1.\r
@endcode\r
@note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.\r
**/\r
-#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
+#define MSR_IA32_HWP_REQUEST_PKG 0x00000772\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG\r
/// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[11] = 1.\r
///\r
- UINT32 Minimum_Performance:8;\r
+ UINT32 Minimum_Performance : 8;\r
///\r
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[11] = 1.\r
///\r
- UINT32 Maximum_Performance:8;\r
+ UINT32 Maximum_Performance : 8;\r
///\r
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
/// If CPUID.06H:EAX.[11] = 1.\r
///\r
- UINT32 Desired_Performance:8;\r
+ UINT32 Desired_Performance : 8;\r
///\r
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
/// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.\r
///\r
- UINT32 Energy_Performance_Preference:8;\r
+ UINT32 Energy_Performance_Preference : 8;\r
///\r
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.\r
///\r
- UINT32 Activity_Window:10;\r
- UINT32 Reserved:22;\r
+ UINT32 Activity_Window : 10;\r
+ UINT32 Reserved : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_HWP_REQUEST_PKG_REGISTER;\r
\r
-\r
/**\r
Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.\r
\r
@endcode\r
@note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.\r
**/\r
-#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
+#define MSR_IA32_HWP_INTERRUPT 0x00000773\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT\r
/// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP\r
/// Notifications". If CPUID.06H:EAX.[8] = 1.\r
///\r
- UINT32 EN_Guaranteed_Performance_Change:1;\r
+ UINT32 EN_Guaranteed_Performance_Change : 1;\r
///\r
/// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".\r
/// If CPUID.06H:EAX.[8] = 1.\r
///\r
- UINT32 EN_Excursion_Minimum:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN_Excursion_Minimum : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_HWP_INTERRUPT_REGISTER;\r
\r
-\r
/**\r
Power Management Control Hints to a Logical Processor (R/W). If\r
CPUID.06H:EAX.[7] = 1.\r
@endcode\r
@note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.\r
**/\r
-#define MSR_IA32_HWP_REQUEST 0x00000774\r
+#define MSR_IA32_HWP_REQUEST 0x00000774\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_HWP_REQUEST\r
/// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Minimum_Performance:8;\r
+ UINT32 Minimum_Performance : 8;\r
///\r
/// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Maximum_Performance:8;\r
+ UINT32 Maximum_Performance : 8;\r
///\r
/// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".\r
/// If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Desired_Performance:8;\r
+ UINT32 Desired_Performance : 8;\r
///\r
/// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,\r
/// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.\r
///\r
- UINT32 Energy_Performance_Preference:8;\r
+ UINT32 Energy_Performance_Preference : 8;\r
///\r
/// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.\r
///\r
- UINT32 Activity_Window:10;\r
+ UINT32 Activity_Window : 10;\r
///\r
/// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If\r
/// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.\r
///\r
- UINT32 Package_Control:1;\r
- UINT32 Reserved:21;\r
+ UINT32 Package_Control : 1;\r
+ UINT32 Reserved : 21;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_HWP_REQUEST_REGISTER;\r
\r
-\r
/**\r
Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If\r
CPUID.06H:EAX.[7] = 1.\r
@endcode\r
@note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.\r
**/\r
-#define MSR_IA32_HWP_STATUS 0x00000777\r
+#define MSR_IA32_HWP_STATUS 0x00000777\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_HWP_STATUS\r
/// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,\r
/// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Guaranteed_Performance_Change:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Guaranteed_Performance_Change : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP\r
/// Feedback". If CPUID.06H:EAX.[7] = 1.\r
///\r
- UINT32 Excursion_To_Minimum:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 Excursion_To_Minimum : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_HWP_STATUS_REGISTER;\r
\r
-\r
/**\r
x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1\r
&& IA32_APIC_BASE.[10] = 1.\r
@endcode\r
@note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_APICID 0x00000802\r
-\r
+#define MSR_IA32_X2APIC_APICID 0x00000802\r
\r
/**\r
x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_VERSION 0x00000803\r
-\r
+#define MSR_IA32_X2APIC_VERSION 0x00000803\r
\r
/**\r
x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_TPR 0x00000808\r
-\r
+#define MSR_IA32_X2APIC_TPR 0x00000808\r
\r
/**\r
x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_PPR 0x0000080A\r
-\r
+#define MSR_IA32_X2APIC_PPR 0x0000080A\r
\r
/**\r
x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]\r
@endcode\r
@note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_EOI 0x0000080B\r
-\r
+#define MSR_IA32_X2APIC_EOI 0x0000080B\r
\r
/**\r
x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LDR 0x0000080D\r
-\r
+#define MSR_IA32_X2APIC_LDR 0x0000080D\r
\r
/**\r
x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1\r
@endcode\r
@note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
-\r
+#define MSR_IA32_X2APIC_SIVR 0x0000080F\r
\r
/**\r
x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).\r
MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_X2APIC_ISR0 0x00000810\r
-#define MSR_IA32_X2APIC_ISR1 0x00000811\r
-#define MSR_IA32_X2APIC_ISR2 0x00000812\r
-#define MSR_IA32_X2APIC_ISR3 0x00000813\r
-#define MSR_IA32_X2APIC_ISR4 0x00000814\r
-#define MSR_IA32_X2APIC_ISR5 0x00000815\r
-#define MSR_IA32_X2APIC_ISR6 0x00000816\r
-#define MSR_IA32_X2APIC_ISR7 0x00000817\r
+#define MSR_IA32_X2APIC_ISR0 0x00000810\r
+#define MSR_IA32_X2APIC_ISR1 0x00000811\r
+#define MSR_IA32_X2APIC_ISR2 0x00000812\r
+#define MSR_IA32_X2APIC_ISR3 0x00000813\r
+#define MSR_IA32_X2APIC_ISR4 0x00000814\r
+#define MSR_IA32_X2APIC_ISR5 0x00000815\r
+#define MSR_IA32_X2APIC_ISR6 0x00000816\r
+#define MSR_IA32_X2APIC_ISR7 0x00000817\r
/// @}\r
\r
-\r
/**\r
x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).\r
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_X2APIC_TMR0 0x00000818\r
-#define MSR_IA32_X2APIC_TMR1 0x00000819\r
-#define MSR_IA32_X2APIC_TMR2 0x0000081A\r
-#define MSR_IA32_X2APIC_TMR3 0x0000081B\r
-#define MSR_IA32_X2APIC_TMR4 0x0000081C\r
-#define MSR_IA32_X2APIC_TMR5 0x0000081D\r
-#define MSR_IA32_X2APIC_TMR6 0x0000081E\r
-#define MSR_IA32_X2APIC_TMR7 0x0000081F\r
+#define MSR_IA32_X2APIC_TMR0 0x00000818\r
+#define MSR_IA32_X2APIC_TMR1 0x00000819\r
+#define MSR_IA32_X2APIC_TMR2 0x0000081A\r
+#define MSR_IA32_X2APIC_TMR3 0x0000081B\r
+#define MSR_IA32_X2APIC_TMR4 0x0000081C\r
+#define MSR_IA32_X2APIC_TMR5 0x0000081D\r
+#define MSR_IA32_X2APIC_TMR6 0x0000081E\r
+#define MSR_IA32_X2APIC_TMR7 0x0000081F\r
/// @}\r
\r
-\r
/**\r
x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).\r
If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.\r
MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.\r
@{\r
**/\r
-#define MSR_IA32_X2APIC_IRR0 0x00000820\r
-#define MSR_IA32_X2APIC_IRR1 0x00000821\r
-#define MSR_IA32_X2APIC_IRR2 0x00000822\r
-#define MSR_IA32_X2APIC_IRR3 0x00000823\r
-#define MSR_IA32_X2APIC_IRR4 0x00000824\r
-#define MSR_IA32_X2APIC_IRR5 0x00000825\r
-#define MSR_IA32_X2APIC_IRR6 0x00000826\r
-#define MSR_IA32_X2APIC_IRR7 0x00000827\r
+#define MSR_IA32_X2APIC_IRR0 0x00000820\r
+#define MSR_IA32_X2APIC_IRR1 0x00000821\r
+#define MSR_IA32_X2APIC_IRR2 0x00000822\r
+#define MSR_IA32_X2APIC_IRR3 0x00000823\r
+#define MSR_IA32_X2APIC_IRR4 0x00000824\r
+#define MSR_IA32_X2APIC_IRR5 0x00000825\r
+#define MSR_IA32_X2APIC_IRR6 0x00000826\r
+#define MSR_IA32_X2APIC_IRR7 0x00000827\r
/// @}\r
\r
-\r
/**\r
x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
IA32_APIC_BASE.[10] = 1.\r
@endcode\r
@note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_ESR 0x00000828\r
-\r
+#define MSR_IA32_X2APIC_ESR 0x00000828\r
\r
/**\r
x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
-\r
+#define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F\r
\r
/**\r
x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_ICR 0x00000830\r
-\r
+#define MSR_IA32_X2APIC_ICR 0x00000830\r
\r
/**\r
x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
-\r
+#define MSR_IA32_X2APIC_LVT_TIMER 0x00000832\r
\r
/**\r
x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
-\r
+#define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833\r
\r
/**\r
x2APIC LVT Performance Monitor Interrupt Register (R/W). If\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
-\r
+#define MSR_IA32_X2APIC_LVT_PMI 0x00000834\r
\r
/**\r
x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
-\r
+#define MSR_IA32_X2APIC_LVT_LINT0 0x00000835\r
\r
/**\r
x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
-\r
+#define MSR_IA32_X2APIC_LVT_LINT1 0x00000836\r
\r
/**\r
x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
-\r
+#define MSR_IA32_X2APIC_LVT_ERROR 0x00000837\r
\r
/**\r
x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
-\r
+#define MSR_IA32_X2APIC_INIT_COUNT 0x00000838\r
\r
/**\r
x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
-\r
+#define MSR_IA32_X2APIC_CUR_COUNT 0x00000839\r
\r
/**\r
x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
-\r
+#define MSR_IA32_X2APIC_DIV_CONF 0x0000083E\r
\r
/**\r
x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&\r
@endcode\r
@note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.\r
**/\r
-#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
-\r
+#define MSR_IA32_X2APIC_SELF_IPI 0x0000083F\r
\r
/**\r
Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.\r
@endcode\r
@note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.\r
**/\r
-#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
+#define MSR_IA32_DEBUG_INTERFACE 0x00000C80\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE\r
/// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.\r
/// Default is 0. If CPUID.01H:ECX.[11] = 1.\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:29;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 29;\r
///\r
/// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The\r
/// lock bit is set automatically on the first SMI assertion even if not\r
/// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
///\r
/// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to\r
/// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.\r
///\r
- UINT32 DebugOccurred:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 DebugOccurred : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_DEBUG_INTERFACE_REGISTER;\r
\r
-\r
/**\r
L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).\r
\r
@endcode\r
@note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
**/\r
-#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
+#define MSR_IA32_L3_QOS_CFG 0x00000C81\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG\r
/// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate\r
/// in Code and Data Prioritization (CDP) mode.\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_L3_QOS_CFG_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.\r
**/\r
-#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
+#define MSR_IA32_L2_QOS_CFG 0x00000C82\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG\r
/// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate\r
/// in Code and Data Prioritization (CDP) mode.\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_L2_QOS_CFG_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
-#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_QM_EVTSEL\r
/// [Bits 7:0] Event ID: ID of a supported monitoring event to report via\r
/// IA32_QM_CTR.\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved : 24;\r
///\r
/// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to\r
/// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (\r
/// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
///\r
- UINT32 ResourceMonitoringID:32;\r
+ UINT32 ResourceMonitoringID : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1\r
).\r
@endcode\r
@note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.\r
**/\r
-#define MSR_IA32_QM_CTR 0x00000C8E\r
+#define MSR_IA32_QM_CTR 0x00000C8E\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_QM_CTR\r
///\r
/// [Bits 31:0] Resource Monitored Data.\r
///\r
- UINT32 ResourceMonitoredData:32;\r
+ UINT32 ResourceMonitoredData : 32;\r
///\r
/// [Bits 61:32] Resource Monitored Data.\r
///\r
- UINT32 ResourceMonitoredDataHi:30;\r
+ UINT32 ResourceMonitoredDataHi : 30;\r
///\r
/// [Bit 62] Unavailable: If 1, indicates data for this RMID is not\r
/// available or not monitored for this resource or RMID.\r
///\r
- UINT32 Unavailable:1;\r
+ UINT32 Unavailable : 1;\r
///\r
/// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was\r
/// written to IA32_PQR_QM_EVTSEL.\r
///\r
- UINT32 Error:1;\r
+ UINT32 Error : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_QM_CTR_REGISTER;\r
\r
-\r
/**\r
Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]\r
=1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).\r
@endcode\r
@note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PQR_ASSOC\r
/// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`\r
/// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).\r
///\r
- UINT32 ResourceMonitoringID:32;\r
+ UINT32 ResourceMonitoringID : 32;\r
///\r
/// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on\r
/// writes); returns the current COS when read. If ( CPUID.(EAX=07H,\r
/// ECX=0):EBX.[15] = 1 ).\r
///\r
- UINT32 COS:32;\r
+ UINT32 COS : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,\r
ECX=0H):EBX[14] = 1).\r
@endcode\r
@note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.\r
**/\r
-#define MSR_IA32_BNDCFGS 0x00000D90\r
+#define MSR_IA32_BNDCFGS 0x00000D90\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_BNDCFGS\r
///\r
/// [Bit 0] EN: Enable Intel MPX in supervisor mode.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch\r
/// instructions in the absence of the BND prefix.\r
///\r
- UINT32 BNDPRESERVE:1;\r
- UINT32 Reserved:10;\r
+ UINT32 BNDPRESERVE : 1;\r
+ UINT32 Reserved : 10;\r
///\r
/// [Bits 31:12] Base Address of Bound Directory.\r
///\r
- UINT32 Base:20;\r
+ UINT32 Base : 20;\r
///\r
/// [Bits 63:32] Base Address of Bound Directory.\r
///\r
- UINT32 BaseHi:32;\r
+ UINT32 BaseHi : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_BNDCFGS_REGISTER;\r
\r
-\r
/**\r
Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.\r
\r
@endcode\r
@note MSR_IA32_XSS is defined as IA32_XSS in SDM.\r
**/\r
-#define MSR_IA32_XSS 0x00000DA0\r
+#define MSR_IA32_XSS 0x00000DA0\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_XSS\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bit 8] Trace Packet Configuration State (R/W).\r
///\r
- UINT32 TracePacketConfigurationState:1;\r
- UINT32 Reserved2:23;\r
- UINT32 Reserved3:32;\r
+ UINT32 TracePacketConfigurationState : 1;\r
+ UINT32 Reserved2 : 23;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_XSS_REGISTER;\r
\r
-\r
/**\r
Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.\r
\r
@endcode\r
@note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.\r
**/\r
-#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
+#define MSR_IA32_PKG_HDC_CTL 0x00000DB0\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL\r
/// logical processors in the package. See Section 14.5.2, "Package level\r
/// Enabling HDC". If CPUID.06H:EAX.[13] = 1.\r
///\r
- UINT32 HDC_Pkg_Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 HDC_Pkg_Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PKG_HDC_CTL_REGISTER;\r
\r
-\r
/**\r
Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.\r
\r
@endcode\r
@note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.\r
**/\r
-#define MSR_IA32_PM_CTL1 0x00000DB1\r
+#define MSR_IA32_PM_CTL1 0x00000DB1\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_PM_CTL1\r
/// package level HDC control. See Section 14.5.3.\r
/// If CPUID.06H:EAX.[13] = 1.\r
///\r
- UINT32 HDC_Allow_Block:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 HDC_Allow_Block : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_PM_CTL1_REGISTER;\r
\r
-\r
/**\r
Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.\r
Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical\r
@endcode\r
@note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.\r
**/\r
-#define MSR_IA32_THREAD_STALL 0x00000DB2\r
-\r
+#define MSR_IA32_THREAD_STALL 0x00000DB2\r
\r
/**\r
Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]\r
@endcode\r
@note MSR_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
-#define MSR_IA32_EFER 0xC0000080\r
+#define MSR_IA32_EFER 0xC0000080\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_EFER\r
/// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET\r
/// instructions in 64-bit mode.\r
///\r
- UINT32 SCE:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 SCE : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode\r
/// operation.\r
///\r
- UINT32 LME:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 LME : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode\r
/// is active when set.\r
///\r
- UINT32 LMA:1;\r
+ UINT32 LMA : 1;\r
///\r
/// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).\r
///\r
- UINT32 NXE:1;\r
- UINT32 Reserved3:20;\r
- UINT32 Reserved4:32;\r
+ UINT32 NXE : 1;\r
+ UINT32 Reserved3 : 20;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_EFER_REGISTER;\r
\r
-\r
/**\r
System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
\r
@endcode\r
@note MSR_IA32_STAR is defined as IA32_STAR in SDM.\r
**/\r
-#define MSR_IA32_STAR 0xC0000081\r
-\r
+#define MSR_IA32_STAR 0xC0000081\r
\r
/**\r
IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.\r
@endcode\r
@note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.\r
**/\r
-#define MSR_IA32_LSTAR 0xC0000082\r
+#define MSR_IA32_LSTAR 0xC0000082\r
\r
/**\r
IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL\r
@endcode\r
@note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.\r
**/\r
-#define MSR_IA32_CSTAR 0xC0000083\r
+#define MSR_IA32_CSTAR 0xC0000083\r
\r
/**\r
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.\r
@endcode\r
@note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.\r
**/\r
-#define MSR_IA32_FMASK 0xC0000084\r
-\r
+#define MSR_IA32_FMASK 0xC0000084\r
\r
/**\r
Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
@endcode\r
@note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.\r
**/\r
-#define MSR_IA32_FS_BASE 0xC0000100\r
-\r
+#define MSR_IA32_FS_BASE 0xC0000100\r
\r
/**\r
Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
@endcode\r
@note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.\r
**/\r
-#define MSR_IA32_GS_BASE 0xC0000101\r
-\r
+#define MSR_IA32_GS_BASE 0xC0000101\r
\r
/**\r
Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.\r
@endcode\r
@note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.\r
**/\r
-#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
-\r
+#define MSR_IA32_KERNEL_GS_BASE 0xC0000102\r
\r
/**\r
Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.\r
@endcode\r
@note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.\r
**/\r
-#define MSR_IA32_TSC_AUX 0xC0000103\r
+#define MSR_IA32_TSC_AUX 0xC0000103\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_TSC_AUX\r
///\r
/// [Bits 31:0] AUX: Auxiliary signature of TSC.\r
///\r
- UINT32 AUX:32;\r
- UINT32 Reserved:32;\r
+ UINT32 AUX : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_TSC_AUX_REGISTER;\r
\r
#endif\r
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
@endcode\r
**/\r
-#define CPUID_SIGNATURE 0x00\r
+#define CPUID_SIGNATURE 0x00\r
\r
///\r
/// @{ CPUID signature values returned by Intel processors\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Version Information\r
\r
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_VERSION_INFO 0x01\r
+#define CPUID_VERSION_INFO 0x01\r
\r
/**\r
CPUID Version Information returned in EAX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r
- UINT32 Model:4; ///< [Bits 7:4] Model\r
- UINT32 FamilyId:4; ///< [Bits 11:8] Family\r
- UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r
- UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r
- UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r
- UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r
- UINT32 Reserved2:4; ///< Reserved\r
+ UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID\r
+ UINT32 Model : 4; ///< [Bits 7:4] Model\r
+ UINT32 FamilyId : 4; ///< [Bits 11:8] Family\r
+ UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type\r
+ UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved\r
+ UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID\r
+ UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID\r
+ UINT32 Reserved2 : 4; ///< Reserved\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bits 7:0] Provides an entry into a brand string table that contains\r
/// brand strings for IA-32 processors.\r
///\r
- UINT32 BrandIndex:8;\r
+ UINT32 BrandIndex : 8;\r
///\r
/// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r
/// and CLFLUSHOPT instructions in 8-byte increments. This field was\r
/// introduced in the Pentium 4 processor.\r
///\r
- UINT32 CacheLineSize:8;\r
+ UINT32 CacheLineSize : 8;\r
///\r
/// [Bits 23:16] Maximum number of addressable IDs for logical processors\r
/// in this physical package.\r
/// logical processors in a physical package. This field is only valid if\r
/// CPUID.1.EDX.HTT[bit 28]= 1.\r
///\r
- UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 8;\r
///\r
/// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r
/// processor during power up. This field was introduced in the Pentium 4\r
/// processor.\r
///\r
- UINT32 InitialLocalApicId:8;\r
+ UINT32 InitialLocalApicId : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
/// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r
/// processor supports this technology\r
///\r
- UINT32 SSE3:1;\r
+ UINT32 SSE3 : 1;\r
///\r
/// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r
/// instruction. Carryless Multiplication\r
///\r
- UINT32 PCLMULQDQ:1;\r
+ UINT32 PCLMULQDQ : 1;\r
///\r
/// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r
/// DS area using 64-bit layout.\r
///\r
- UINT32 DTES64:1;\r
+ UINT32 DTES64 : 1;\r
///\r
/// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r
/// this feature.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r
/// supports the extensions to the Debug Store feature to allow for branch\r
/// message storage qualified by CPL\r
///\r
- UINT32 DS_CPL:1;\r
+ UINT32 DS_CPL : 1;\r
///\r
/// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r
/// processor supports this technology.\r
///\r
- UINT32 VMX:1;\r
+ UINT32 VMX : 1;\r
///\r
/// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r
/// supports this technology\r
///\r
- UINT32 SMX:1;\r
+ UINT32 SMX : 1;\r
///\r
/// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r
/// that the processor supports this technology\r
///\r
- UINT32 EIST:1;\r
+ UINT32 EIST : 1;\r
///\r
/// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r
/// supports this technology\r
///\r
- UINT32 TM2:1;\r
+ UINT32 TM2 : 1;\r
///\r
/// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r
/// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r
/// extensions are not present in the processor.\r
///\r
- UINT32 SSSE3:1;\r
+ UINT32 SSSE3 : 1;\r
///\r
/// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r
/// can be set to either adaptive mode or shared mode. A value of 0 indicates\r
/// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r
/// Bit 24 (L1 Data Cache Context Mode) for details\r
///\r
- UINT32 CNXT_ID:1;\r
+ UINT32 CNXT_ID : 1;\r
///\r
/// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r
/// MSR for silicon debug\r
///\r
- UINT32 SDBG:1;\r
+ UINT32 SDBG : 1;\r
///\r
/// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r
/// Add) extensions using YMM state.\r
///\r
- UINT32 FMA:1;\r
+ UINT32 FMA : 1;\r
///\r
/// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r
/// is available.\r
///\r
- UINT32 CMPXCHG16B:1;\r
+ UINT32 CMPXCHG16B : 1;\r
///\r
/// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r
/// supports changing IA32_MISC_ENABLE[Bit 23].\r
///\r
- UINT32 xTPR_Update_Control:1;\r
+ UINT32 xTPR_Update_Control : 1;\r
///\r
/// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r
/// processor supports the performance and debug feature indication MSR\r
/// IA32_PERF_CAPABILITIES.\r
///\r
- UINT32 PDCM:1;\r
- UINT32 Reserved:1;\r
+ UINT32 PDCM : 1;\r
+ UINT32 Reserved : 1;\r
///\r
/// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r
/// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r
///\r
- UINT32 PCID:1;\r
+ UINT32 PCID : 1;\r
///\r
/// [Bit 18] A value of 1 indicates the processor supports the ability to\r
/// prefetch data from a memory mapped device. Direct Cache Access.\r
///\r
- UINT32 DCA:1;\r
+ UINT32 DCA : 1;\r
///\r
/// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r
///\r
- UINT32 SSE4_1:1;\r
+ UINT32 SSE4_1 : 1;\r
///\r
/// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r
///\r
- UINT32 SSE4_2:1;\r
+ UINT32 SSE4_2 : 1;\r
///\r
/// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r
/// feature.\r
///\r
- UINT32 x2APIC:1;\r
+ UINT32 x2APIC : 1;\r
///\r
/// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r
/// instruction.\r
///\r
- UINT32 MOVBE:1;\r
+ UINT32 MOVBE : 1;\r
///\r
/// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r
/// instruction.\r
///\r
- UINT32 POPCNT:1;\r
+ UINT32 POPCNT : 1;\r
///\r
/// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r
/// supports one-shot operation using a TSC deadline value.\r
///\r
- UINT32 TSC_Deadline:1;\r
+ UINT32 TSC_Deadline : 1;\r
///\r
/// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r
/// instruction extensions.\r
///\r
- UINT32 AESNI:1;\r
+ UINT32 AESNI : 1;\r
///\r
/// [Bit 26] A value of 1 indicates that the processor supports the\r
/// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r
/// instructions, and XCR0.\r
///\r
- UINT32 XSAVE:1;\r
+ UINT32 XSAVE : 1;\r
///\r
/// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r
/// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r
/// processor extended state management using XSAVE/XRSTOR.\r
///\r
- UINT32 OSXSAVE:1;\r
+ UINT32 OSXSAVE : 1;\r
///\r
/// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r
/// extensions.\r
///\r
- UINT32 AVX:1;\r
+ UINT32 AVX : 1;\r
///\r
/// [Bit 29] A value of 1 indicates that processor supports 16-bit\r
/// floating-point conversion instructions.\r
///\r
- UINT32 F16C:1;\r
+ UINT32 F16C : 1;\r
///\r
/// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r
///\r
- UINT32 RDRAND:1;\r
+ UINT32 RDRAND : 1;\r
///\r
/// [Bit 31] Always returns 0.\r
///\r
- UINT32 NotUsed:1;\r
+ UINT32 NotUsed : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
/// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r
///\r
- UINT32 FPU:1;\r
+ UINT32 FPU : 1;\r
///\r
/// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r
/// including CR4.VME for controlling the feature, CR4.PVI for protected\r
/// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r
/// EFLAGS.VIP flags.\r
///\r
- UINT32 VME:1;\r
+ UINT32 VME : 1;\r
///\r
/// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r
/// CR4.DE for controlling the feature, and optional trapping of accesses to\r
/// DR4 and DR5.\r
///\r
- UINT32 DE:1;\r
+ UINT32 DE : 1;\r
///\r
/// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r
/// including CR4.PSE for controlling the feature, the defined dirty bit in\r
/// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r
/// PDEs, and PTEs.\r
///\r
- UINT32 PSE:1;\r
+ UINT32 PSE : 1;\r
///\r
/// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r
/// including CR4.TSD for controlling privilege.\r
///\r
- UINT32 TSC:1;\r
+ UINT32 TSC : 1;\r
///\r
/// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r
/// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r
/// implementation dependent.\r
///\r
- UINT32 MSR:1;\r
+ UINT32 MSR : 1;\r
///\r
/// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r
/// bits are supported: extended page table entry formats, an extra level in\r
/// the page translation tables is defined, 2-MByte pages are supported\r
/// instead of 4 Mbyte pages if PAE bit is 1.\r
///\r
- UINT32 PAE:1;\r
+ UINT32 PAE : 1;\r
///\r
/// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r
/// Checks, including CR4.MCE for controlling the feature. This feature does\r
/// processing of the exception, or test for the presence of the Machine\r
/// Check feature.\r
///\r
- UINT32 MCE:1;\r
+ UINT32 MCE : 1;\r
///\r
/// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r
/// instruction is supported (implicitly locked and atomic).\r
///\r
- UINT32 CX8:1;\r
+ UINT32 CX8 : 1;\r
///\r
/// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r
/// Interrupt Controller (APIC), responding to memory mapped commands in the\r
/// physical address range FFFE0000H to FFFE0FFFH (by default - some\r
/// processors permit the APIC to be relocated).\r
///\r
- UINT32 APIC:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 APIC : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r
/// and associated MSRs are supported.\r
///\r
- UINT32 SEP:1;\r
+ UINT32 SEP : 1;\r
///\r
/// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r
/// MSR contains feature bits that describe what memory types are supported,\r
/// how many variable MTRRs are supported, and whether fixed MTRRs are\r
/// supported.\r
///\r
- UINT32 MTRR:1;\r
+ UINT32 MTRR : 1;\r
///\r
/// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r
/// entries that map a page, indicating TLB entries that are common to\r
/// different processes and need not be flushed. The CR4.PGE bit controls\r
/// this feature.\r
///\r
- UINT32 PGE:1;\r
+ UINT32 PGE : 1;\r
///\r
/// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r
/// Check Architecture of reporting machine errors is supported. The MCG_CAP\r
/// MSR contains feature bits describing how many banks of error reporting\r
/// MSRs are supported.\r
///\r
- UINT32 MCA:1;\r
+ UINT32 MCA : 1;\r
///\r
/// [Bit 15] Conditional Move Instructions. The conditional move instruction\r
/// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r
/// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r
///\r
- UINT32 CMOV:1;\r
+ UINT32 CMOV : 1;\r
///\r
/// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r
/// feature augments the Memory Type Range Registers (MTRRs), allowing an\r
/// operating system to specify attributes of memory accessed through a\r
/// linear address on a 4KB granularity.\r
///\r
- UINT32 PAT:1;\r
+ UINT32 PAT : 1;\r
///\r
/// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r
/// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r
/// encoded in bits 20:13 of the page-directory entry. Such physical\r
/// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r
///\r
- UINT32 PSE_36:1;\r
+ UINT32 PSE_36 : 1;\r
///\r
/// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r
/// processor identification number feature and the feature is enabled.\r
///\r
- UINT32 PSN:1;\r
+ UINT32 PSN : 1;\r
///\r
/// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r
///\r
- UINT32 CLFSH:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 CLFSH : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 21] Debug Store. The processor supports the ability to write debug\r
/// information into a memory resident buffer. This feature is used by the\r
/// branch trace store (BTS) and precise event-based sampling (PEBS)\r
/// facilities.\r
///\r
- UINT32 DS:1;\r
+ UINT32 DS : 1;\r
///\r
/// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r
/// processor implements internal MSRs that allow processor temperature to\r
/// be monitored and processor performance to be modulated in predefined\r
/// duty cycles under software control.\r
///\r
- UINT32 ACPI:1;\r
+ UINT32 ACPI : 1;\r
///\r
/// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r
/// technology.\r
///\r
- UINT32 MMX:1;\r
+ UINT32 MMX : 1;\r
///\r
/// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r
/// instructions are supported for fast save and restore of the floating\r
/// available for an operating system to indicate that it supports the\r
/// FXSAVE and FXRSTOR instructions.\r
///\r
- UINT32 FXSR:1;\r
+ UINT32 FXSR : 1;\r
///\r
/// [Bit 25] SSE. The processor supports the SSE extensions.\r
///\r
- UINT32 SSE:1;\r
+ UINT32 SSE : 1;\r
///\r
/// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r
///\r
- UINT32 SSE2:1;\r
+ UINT32 SSE2 : 1;\r
///\r
/// [Bit 27] Self Snoop. The processor supports the management of\r
/// conflicting memory types by performing a snoop of its own cache\r
/// structure for transactions issued to the bus.\r
///\r
- UINT32 SS:1;\r
+ UINT32 SS : 1;\r
///\r
/// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r
/// indicates there is only a single logical processor in the package and\r
/// addressable IDs for logical processors in this package) is valid for the\r
/// package.\r
///\r
- UINT32 HTT:1;\r
+ UINT32 HTT : 1;\r
///\r
/// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r
/// automatic thermal control circuitry (TCC).\r
///\r
- UINT32 TM:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 TM : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 31] Pending Break Enable. The processor supports the use of the\r
/// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r
/// the processor should return to normal operation to handle the interrupt.\r
/// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r
///\r
- UINT32 PBE:1;\r
+ UINT32 PBE : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
UINT32 Uint32;\r
} CPUID_VERSION_INFO_EDX;\r
\r
-\r
/**\r
CPUID Cache and TLB Information\r
\r
use CPUID leaf 4 to query cache parameters</td></tr>\r
</table>\r
**/\r
-#define CPUID_CACHE_INFO 0x02\r
+#define CPUID_CACHE_INFO 0x02\r
\r
/**\r
CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:31;\r
+ UINT32 Reserved : 31;\r
///\r
/// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r
/// if 1, then none of the cache descriptor bytes in the register are valid.\r
///\r
- UINT32 NotValid:1;\r
+ UINT32 NotValid : 1;\r
} Bits;\r
///\r
/// Array of Cache and TLB descriptor bytes\r
///\r
- UINT8 CacheDescriptor[4];\r
+ UINT8 CacheDescriptor[4];\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_INFO_CACHE_TLB;\r
\r
-\r
/**\r
CPUID Processor Serial Number\r
\r
AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
@endcode\r
**/\r
-#define CPUID_SERIAL_NUMBER 0x03\r
-\r
+#define CPUID_SERIAL_NUMBER 0x03\r
\r
/**\r
CPUID Cache Parameters\r
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
@endcode\r
**/\r
-#define CPUID_CACHE_PARAMS 0x04\r
+#define CPUID_CACHE_PARAMS 0x04\r
\r
/**\r
CPUID Cache Parameters Information returned in EAX for CPUID leaf\r
/// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r
/// then there is no information for the requested cache level.\r
///\r
- UINT32 CacheType:5;\r
+ UINT32 CacheType : 5;\r
///\r
/// [Bits 7:5] Cache level (Starts at 1).\r
///\r
- UINT32 CacheLevel:3;\r
+ UINT32 CacheLevel : 3;\r
///\r
/// [Bit 8] Self Initializing cache level (does not need SW initialization).\r
///\r
- UINT32 SelfInitializingCache:1;\r
+ UINT32 SelfInitializingCache : 1;\r
///\r
/// [Bit 9] Fully Associative cache.\r
///\r
- UINT32 FullyAssociativeCache:1;\r
+ UINT32 FullyAssociativeCache : 1;\r
///\r
/// [Bits 13:10] Reserved.\r
///\r
- UINT32 Reserved:4;\r
+ UINT32 Reserved : 4;\r
///\r
/// [Bits 25:14] Maximum number of addressable IDs for logical processors\r
/// sharing this cache.\r
/// is the number of unique initial APIC IDs reserved for addressing\r
/// different logical processors sharing this cache.\r
///\r
- UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors : 12;\r
///\r
/// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r
/// the physical package.\r
/// The returned value is constant for valid initial values in ECX. Valid\r
/// ECX values start from 0.\r
///\r
- UINT32 MaximumAddressableIdsForProcessorCores:6;\r
+ UINT32 MaximumAddressableIdsForProcessorCores : 6;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EAX;\r
\r
///\r
/// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r
/// get the result.\r
///\r
- UINT32 LineSize:12;\r
+ UINT32 LineSize : 12;\r
///\r
/// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r
/// get the result.\r
///\r
- UINT32 LinePartitions:10;\r
+ UINT32 LinePartitions : 10;\r
///\r
/// [Bits 31:22] Ways of associativity. Add one to the return value to get\r
/// the result.\r
///\r
- UINT32 Ways:10;\r
+ UINT32 Ways : 10;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EBX;\r
\r
/**\r
/// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r
/// non-originating threads sharing this cache.\r
///\r
- UINT32 Invalidate:1;\r
+ UINT32 Invalidate : 1;\r
///\r
/// [Bit 1] Cache Inclusiveness.\r
/// 0 = Cache is not inclusive of lower cache levels.\r
/// 1 = Cache is inclusive of lower cache levels.\r
///\r
- UINT32 CacheInclusiveness:1;\r
+ UINT32 CacheInclusiveness : 1;\r
///\r
/// [Bit 2] Complex Cache Indexing.\r
/// 0 = Direct mapped cache.\r
/// 1 = A complex function is used to index the cache, potentially using all\r
/// address bits.\r
///\r
- UINT32 ComplexCacheIndexing:1;\r
- UINT32 Reserved:29;\r
+ UINT32 ComplexCacheIndexing : 1;\r
+ UINT32 Reserved : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_CACHE_PARAMS_EDX;\r
\r
-\r
/**\r
CPUID MONITOR/MWAIT Information\r
\r
AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_MONITOR_MWAIT 0x05\r
+#define CPUID_MONITOR_MWAIT 0x05\r
\r
/**\r
CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r
/// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r
/// monitor granularity).\r
///\r
- UINT32 SmallestMonitorLineSize:16;\r
- UINT32 Reserved:16;\r
+ UINT32 SmallestMonitorLineSize : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EAX;\r
\r
/**\r
/// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r
/// monitor granularity).\r
///\r
- UINT32 LargestMonitorLineSize:16;\r
- UINT32 Reserved:16;\r
+ UINT32 LargestMonitorLineSize : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EBX;\r
\r
/**\r
/// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r
/// and EDX are valid.\r
///\r
- UINT32 ExtensionsSupported:1;\r
+ UINT32 ExtensionsSupported : 1;\r
///\r
/// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r
/// interrupts disabled.\r
///\r
- UINT32 InterruptAsBreak:1;\r
- UINT32 Reserved:30;\r
+ UINT32 InterruptAsBreak : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_ECX;\r
\r
/**\r
///\r
/// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r
///\r
- UINT32 C0States:4;\r
+ UINT32 C0States : 4;\r
///\r
/// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r
///\r
- UINT32 C1States:4;\r
+ UINT32 C1States : 4;\r
///\r
/// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r
///\r
- UINT32 C2States:4;\r
+ UINT32 C2States : 4;\r
///\r
/// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r
///\r
- UINT32 C3States:4;\r
+ UINT32 C3States : 4;\r
///\r
/// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r
///\r
- UINT32 C4States:4;\r
+ UINT32 C4States : 4;\r
///\r
/// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r
///\r
- UINT32 C5States:4;\r
+ UINT32 C5States : 4;\r
///\r
/// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r
///\r
- UINT32 C6States:4;\r
+ UINT32 C6States : 4;\r
///\r
/// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r
///\r
- UINT32 C7States:4;\r
+ UINT32 C7States : 4;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_MONITOR_MWAIT_EDX;\r
\r
-\r
/**\r
CPUID Thermal and Power Management\r
\r
AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
+#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
\r
/**\r
CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r
///\r
/// [Bit 0] Digital temperature sensor is supported if set.\r
///\r
- UINT32 DigitalTemperatureSensor:1;\r
+ UINT32 DigitalTemperatureSensor : 1;\r
///\r
/// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r
///\r
- UINT32 TurboBoostTechnology:1;\r
+ UINT32 TurboBoostTechnology : 1;\r
///\r
/// [Bit 2] APIC-Timer-always-running feature is supported if set.\r
///\r
- UINT32 ARAT:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARAT : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Power limit notification controls are supported if set.\r
///\r
- UINT32 PLN:1;\r
+ UINT32 PLN : 1;\r
///\r
/// [Bit 5] Clock modulation duty cycle extension is supported if set.\r
///\r
- UINT32 ECMD:1;\r
+ UINT32 ECMD : 1;\r
///\r
/// [Bit 6] Package thermal management is supported if set.\r
///\r
- UINT32 PTM:1;\r
+ UINT32 PTM : 1;\r
///\r
/// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r
/// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r
///\r
- UINT32 HWP:1;\r
+ UINT32 HWP : 1;\r
///\r
/// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r
///\r
- UINT32 HWP_Notification:1;\r
+ UINT32 HWP_Notification : 1;\r
///\r
/// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r
///\r
- UINT32 HWP_Activity_Window:1;\r
+ UINT32 HWP_Activity_Window : 1;\r
///\r
/// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r
///\r
- UINT32 HWP_Energy_Performance_Preference:1;\r
+ UINT32 HWP_Energy_Performance_Preference : 1;\r
///\r
/// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r
///\r
- UINT32 HWP_Package_Level_Request:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 HWP_Package_Level_Request : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r
/// IA32_THREAD_STALL MSRs are supported if set.\r
///\r
- UINT32 HDC:1;\r
+ UINT32 HDC : 1;\r
///\r
/// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.\r
///\r
- UINT32 TurboBoostMaxTechnology30:1;\r
+ UINT32 TurboBoostMaxTechnology30 : 1;\r
///\r
/// [Bit 15] HWP Capabilities.\r
/// Highest Performance change is supported if set.\r
///\r
- UINT32 HWPCapabilities:1;\r
+ UINT32 HWPCapabilities : 1;\r
///\r
/// [Bit 16] HWP PECI override is supported if set.\r
///\r
- UINT32 HWPPECIOverride:1;\r
+ UINT32 HWPPECIOverride : 1;\r
///\r
/// [Bit 17] Flexible HWP is supported if set.\r
///\r
- UINT32 FlexibleHWP:1;\r
+ UINT32 FlexibleHWP : 1;\r
///\r
/// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.\r
///\r
- UINT32 FastAccessMode:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 FastAccessMode : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.\r
///\r
- UINT32 IgnoringIdleLogicalProcessorHWPRequest:1;\r
- UINT32 Reserved5:11;\r
+ UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;\r
+ UINT32 Reserved5 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r
\r
/**\r
///\r
/// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r
///\r
- UINT32 InterruptThresholds:4;\r
- UINT32 Reserved:28;\r
+ UINT32 InterruptThresholds : 4;\r
+ UINT32 Reserved : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r
\r
/**\r
/// processor performance (since last reset of the counters), as a percentage\r
/// of the expected processor performance when running at the TSC frequency.\r
///\r
- UINT32 HardwareCoordinationFeedback:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 HardwareCoordinationFeedback : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] If this bit is set, then the processor supports performance-energy\r
/// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r
/// (1B0H).\r
///\r
- UINT32 PerformanceEnergyBias:1;\r
- UINT32 Reserved2:28;\r
+ UINT32 PerformanceEnergyBias : 1;\r
+ UINT32 Reserved2 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r
\r
-\r
/**\r
CPUID Structured Extended Feature Flags Enumeration\r
\r
}\r
@endcode\r
**/\r
-#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
\r
///\r
/// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r
///\r
/// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r
///\r
- UINT32 FSGSBASE:1;\r
+ UINT32 FSGSBASE : 1;\r
///\r
/// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
///\r
- UINT32 IA32_TSC_ADJUST:1;\r
+ UINT32 IA32_TSC_ADJUST : 1;\r
///\r
/// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r
/// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r
///\r
- UINT32 SGX:1;\r
+ UINT32 SGX : 1;\r
///\r
/// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
/// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
///\r
- UINT32 BMI1:1;\r
+ UINT32 BMI1 : 1;\r
///\r
/// [Bit 4] Hardware Lock Elision\r
///\r
- UINT32 HLE:1;\r
+ UINT32 HLE : 1;\r
///\r
/// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r
///\r
- UINT32 AVX2:1;\r
+ UINT32 AVX2 : 1;\r
///\r
/// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r
///\r
- UINT32 FDP_EXCPTN_ONLY:1;\r
+ UINT32 FDP_EXCPTN_ONLY : 1;\r
///\r
/// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r
///\r
- UINT32 SMEP:1;\r
+ UINT32 SMEP : 1;\r
///\r
/// [Bit 8] If 1 indicates the processor supports the second group of\r
/// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r
/// SARX, SHLX, SHRX)\r
///\r
- UINT32 BMI2:1;\r
+ UINT32 BMI2 : 1;\r
///\r
/// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r
///\r
- UINT32 EnhancedRepMovsbStosb:1;\r
+ UINT32 EnhancedRepMovsbStosb : 1;\r
///\r
/// [Bit 10] If 1, supports INVPCID instruction for system software that\r
/// manages process-context identifiers.\r
///\r
- UINT32 INVPCID:1;\r
+ UINT32 INVPCID : 1;\r
///\r
/// [Bit 11] Restricted Transactional Memory\r
///\r
- UINT32 RTM:1;\r
+ UINT32 RTM : 1;\r
///\r
/// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
/// Monitoring capability if 1.\r
///\r
- UINT32 RDT_M:1;\r
+ UINT32 RDT_M : 1;\r
///\r
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
///\r
- UINT32 DeprecateFpuCsDs:1;\r
+ UINT32 DeprecateFpuCsDs : 1;\r
///\r
/// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r
///\r
- UINT32 MPX:1;\r
+ UINT32 MPX : 1;\r
///\r
/// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r
/// Allocation capability if 1.\r
///\r
- UINT32 RDT_A:1;\r
+ UINT32 RDT_A : 1;\r
///\r
/// [Bit 16] AVX512F.\r
///\r
- UINT32 AVX512F:1;\r
+ UINT32 AVX512F : 1;\r
///\r
/// [Bit 17] AVX512DQ.\r
///\r
- UINT32 AVX512DQ:1;\r
+ UINT32 AVX512DQ : 1;\r
///\r
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
///\r
- UINT32 RDSEED:1;\r
+ UINT32 RDSEED : 1;\r
///\r
/// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r
/// instructions.\r
///\r
- UINT32 ADX:1;\r
+ UINT32 ADX : 1;\r
///\r
/// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r
/// instructions) if 1.\r
///\r
- UINT32 SMAP:1;\r
+ UINT32 SMAP : 1;\r
///\r
/// [Bit 21] AVX512_IFMA.\r
///\r
- UINT32 AVX512_IFMA:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 AVX512_IFMA : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
///\r
- UINT32 CLFLUSHOPT:1;\r
+ UINT32 CLFLUSHOPT : 1;\r
///\r
/// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r
///\r
- UINT32 CLWB:1;\r
+ UINT32 CLWB : 1;\r
///\r
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
/// extensions.\r
///\r
- UINT32 IntelProcessorTrace:1;\r
+ UINT32 IntelProcessorTrace : 1;\r
///\r
/// [Bit 26] AVX512PF. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512PF:1;\r
+ UINT32 AVX512PF : 1;\r
///\r
/// [Bit 27] AVX512ER. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512ER:1;\r
+ UINT32 AVX512ER : 1;\r
///\r
/// [Bit 28] AVX512CD.\r
///\r
- UINT32 AVX512CD:1;\r
+ UINT32 AVX512CD : 1;\r
///\r
/// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r
/// SHA Extensions) if 1.\r
///\r
- UINT32 SHA:1;\r
+ UINT32 SHA : 1;\r
///\r
/// [Bit 30] AVX512BW.\r
///\r
- UINT32 AVX512BW:1;\r
+ UINT32 AVX512BW : 1;\r
///\r
/// [Bit 31] AVX512VL.\r
///\r
- UINT32 AVX512VL:1;\r
+ UINT32 AVX512VL : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r
\r
/**\r
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
/// (Intel Xeon Phi only.)\r
///\r
- UINT32 PREFETCHWT1:1;\r
+ UINT32 PREFETCHWT1 : 1;\r
///\r
/// [Bit 1] AVX512_VBMI.\r
///\r
- UINT32 AVX512_VBMI:1;\r
+ UINT32 AVX512_VBMI : 1;\r
///\r
/// [Bit 2] Supports user-mode instruction prevention if 1.\r
///\r
- UINT32 UMIP:1;\r
+ UINT32 UMIP : 1;\r
///\r
/// [Bit 3] Supports protection keys for user-mode pages if 1.\r
///\r
- UINT32 PKU:1;\r
+ UINT32 PKU : 1;\r
///\r
/// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r
/// RDPKRU/WRPKRU instructions).\r
///\r
- UINT32 OSPKE:1;\r
- UINT32 Reserved5:9;\r
+ UINT32 OSPKE : 1;\r
+ UINT32 Reserved5 : 9;\r
///\r
/// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r
///\r
- UINT32 AVX512_VPOPCNTDQ:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 AVX512_VPOPCNTDQ : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bits 16] Supports 5-level paging if 1.\r
///\r
- UINT32 FiveLevelPage:1;\r
+ UINT32 FiveLevelPage : 1;\r
///\r
/// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r
/// in 64-bit mode.\r
///\r
- UINT32 MAWAU:5;\r
+ UINT32 MAWAU : 5;\r
///\r
/// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.\r
///\r
- UINT32 RDPID:1;\r
- UINT32 Reserved3:7;\r
+ UINT32 RDPID : 1;\r
+ UINT32 Reserved3 : 7;\r
///\r
/// [Bit 30] Supports SGX Launch Configuration if 1.\r
///\r
- UINT32 SGX_LC:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 SGX_LC : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
\r
/**\r
///\r
/// [Bit 1:0] Reserved.\r
///\r
- UINT32 Reserved1:2;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)\r
///\r
- UINT32 AVX512_4VNNIW:1;\r
+ UINT32 AVX512_4VNNIW : 1;\r
///\r
/// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)\r
///\r
- UINT32 AVX512_4FMAPS:1;\r
+ UINT32 AVX512_4FMAPS : 1;\r
///\r
/// [Bit 14:4] Reserved.\r
///\r
- UINT32 Reserved4:11;\r
+ UINT32 Reserved4 : 11;\r
///\r
/// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.\r
///\r
- UINT32 Hybrid:1;\r
+ UINT32 Hybrid : 1;\r
///\r
/// [Bit 25:16] Reserved.\r
///\r
- UINT32 Reserved5:10;\r
+ UINT32 Reserved5 : 10;\r
///\r
/// [Bit 26] Enumerates support for indirect branch restricted speculation\r
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors\r
/// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and\r
/// IA32_PRED_CMD[0] (IBPB).\r
///\r
- UINT32 EnumeratesSupportForIBRSAndIBPB:1;\r
+ UINT32 EnumeratesSupportForIBRSAndIBPB : 1;\r
///\r
/// [Bit 27] Enumerates support for single thread indirect branch\r
/// predictors (STIBP). Processors that set this bit support the\r
/// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]\r
/// (STIBP).\r
///\r
- UINT32 EnumeratesSupportForSTIBP:1;\r
+ UINT32 EnumeratesSupportForSTIBP : 1;\r
///\r
/// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit\r
/// support the IA32_FLUSH_CMD MSR. They allow software to set\r
/// IA32_FLUSH_CMD[0] (L1D_FLUSH).\r
///\r
- UINT32 EnumeratesSupportForL1D_FLUSH:1;\r
+ UINT32 EnumeratesSupportForL1D_FLUSH : 1;\r
///\r
/// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.\r
///\r
- UINT32 EnumeratesSupportForCapability:1;\r
+ UINT32 EnumeratesSupportForCapability : 1;\r
///\r
/// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.\r
///\r
- UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;\r
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1;\r
///\r
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).\r
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow\r
/// software to set IA32_SPEC_CTRL[2] (SSBD).\r
///\r
- UINT32 EnumeratesSupportForSSBD:1;\r
+ UINT32 EnumeratesSupportForSSBD : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;\r
\r
/**\r
AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
-\r
+#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
\r
/**\r
CPUID Architectural Performance Monitoring\r
///\r
/// [Bit 7:0] Version ID of architectural performance monitoring.\r
///\r
- UINT32 ArchPerfMonVerID:8;\r
+ UINT32 ArchPerfMonVerID : 8;\r
///\r
/// [Bits 15:8] Number of general-purpose performance monitoring counter\r
/// per logical processor.\r
/// paired with a corresponding performance counter in the 0C1H address\r
/// block.\r
///\r
- UINT32 PerformanceMonitorCounters:8;\r
+ UINT32 PerformanceMonitorCounters : 8;\r
///\r
/// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
///\r
/// may be written with any value, and the high-order bits are sign-extended\r
/// from the value of bit 31.\r
///\r
- UINT32 PerformanceMonitorCounterWidth:8;\r
+ UINT32 PerformanceMonitorCounterWidth : 8;\r
///\r
/// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
/// performance monitoring events.\r
///\r
- UINT32 EbxBitVectorLength:8;\r
+ UINT32 EbxBitVectorLength : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
\r
/**\r
///\r
/// [Bit 0] Core cycle event not available if 1.\r
///\r
- UINT32 UnhaltedCoreCycles:1;\r
+ UINT32 UnhaltedCoreCycles : 1;\r
///\r
/// [Bit 1] Instruction retired event not available if 1.\r
///\r
- UINT32 InstructionsRetired:1;\r
+ UINT32 InstructionsRetired : 1;\r
///\r
/// [Bit 2] Reference cycles event not available if 1.\r
///\r
- UINT32 UnhaltedReferenceCycles:1;\r
+ UINT32 UnhaltedReferenceCycles : 1;\r
///\r
/// [Bit 3] Last-level cache reference event not available if 1.\r
///\r
- UINT32 LastLevelCacheReferences:1;\r
+ UINT32 LastLevelCacheReferences : 1;\r
///\r
/// [Bit 4] Last-level cache misses event not available if 1.\r
///\r
- UINT32 LastLevelCacheMisses:1;\r
+ UINT32 LastLevelCacheMisses : 1;\r
///\r
/// [Bit 5] Branch instruction retired event not available if 1.\r
///\r
- UINT32 BranchInstructionsRetired:1;\r
+ UINT32 BranchInstructionsRetired : 1;\r
///\r
/// [Bit 6] Branch mispredict retired event not available if 1.\r
///\r
- UINT32 AllBranchMispredictRetired:1;\r
- UINT32 Reserved:25;\r
+ UINT32 AllBranchMispredictRetired : 1;\r
+ UINT32 Reserved : 25;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
\r
/**\r
/// [Bits 4:0] Number of fixed-function performance counters\r
/// (if Version ID > 1).\r
///\r
- UINT32 FixedFunctionPerformanceCounters:5;\r
+ UINT32 FixedFunctionPerformanceCounters : 5;\r
///\r
/// [Bits 12:5] Bit width of fixed-function performance counters\r
/// (if Version ID > 1).\r
///\r
- UINT32 FixedFunctionPerformanceCounterWidth:8;\r
- UINT32 Reserved1:2;\r
+ UINT32 FixedFunctionPerformanceCounterWidth : 8;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bits 15] AnyThread deprecation.\r
///\r
- UINT32 AnyThreadDeprecation:1;\r
- UINT32 Reserved2:16;\r
+ UINT32 AnyThreadDeprecation : 1;\r
+ UINT32 Reserved2 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
\r
-\r
/**\r
CPUID Extended Topology Information\r
\r
} while (Eax.Bits.ApicIdShift != 0);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
+#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
\r
/**\r
CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
/// Software should use this field (EAX[4:0]) to enumerate processor\r
/// topology of the system.\r
///\r
- UINT32 ApicIdShift:5;\r
- UINT32 Reserved:27;\r
+ UINT32 ApicIdShift : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_EAX;\r
\r
/**\r
/// available to BIOS/OS/Applications may be different from the value of\r
/// EBX[15:0], depending on software and platform hardware configurations.\r
///\r
- UINT32 LogicalProcessors:16;\r
- UINT32 Reserved:16;\r
+ UINT32 LogicalProcessors : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_EBX;\r
\r
/**\r
///\r
/// [Bits 7:0] Level number. Same value in ECX input.\r
///\r
- UINT32 LevelNumber:8;\r
+ UINT32 LevelNumber : 8;\r
///\r
/// [Bits 15:8] Level type.\r
///\r
/// The value of the "level type" field is not related to level numbers in\r
/// any way, higher "level type" values do not mean higher levels.\r
///\r
- UINT32 LevelType:8;\r
- UINT32 Reserved:16;\r
+ UINT32 LevelType : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TOPOLOGY_ECX;\r
\r
///\r
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
///\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Extended State Information\r
\r
CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
**/\r
-#define CPUID_EXTENDED_STATE 0x0D\r
+#define CPUID_EXTENDED_STATE 0x0D\r
\r
/**\r
CPUID Extended State Information Main Leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
///\r
/// [Bit 0] x87 state.\r
///\r
- UINT32 x87:1;\r
+ UINT32 x87 : 1;\r
///\r
/// [Bit 1] SSE state.\r
///\r
- UINT32 SSE:1;\r
+ UINT32 SSE : 1;\r
///\r
/// [Bit 2] AVX state.\r
///\r
- UINT32 AVX:1;\r
+ UINT32 AVX : 1;\r
///\r
/// [Bits 4:3] MPX state.\r
///\r
- UINT32 MPX:2;\r
+ UINT32 MPX : 2;\r
///\r
/// [Bits 7:5] AVX-512 state.\r
///\r
- UINT32 AVX_512:3;\r
+ UINT32 AVX_512 : 3;\r
///\r
/// [Bit 8] Used for IA32_XSS.\r
///\r
- UINT32 IA32_XSS:1;\r
+ UINT32 IA32_XSS : 1;\r
///\r
/// [Bit 9] PKRU state.\r
///\r
- UINT32 PKRU:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 PKRU : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 13] Used for IA32_XSS, part 2.\r
///\r
- UINT32 IA32_XSS_2:1;\r
- UINT32 Reserved2:18;\r
+ UINT32 IA32_XSS_2 : 1;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
\r
/**\r
CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
///\r
/// [Bit 0] XSAVEOPT is available.\r
///\r
- UINT32 XSAVEOPT:1;\r
+ UINT32 XSAVEOPT : 1;\r
///\r
/// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
///\r
- UINT32 XSAVEC:1;\r
+ UINT32 XSAVEC : 1;\r
///\r
/// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
///\r
- UINT32 XGETBV:1;\r
+ UINT32 XGETBV : 1;\r
///\r
/// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
///\r
- UINT32 XSAVES:1;\r
- UINT32 Reserved:28;\r
+ UINT32 XSAVES : 1;\r
+ UINT32 Reserved : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 7:0] Used for XCR0.\r
///\r
- UINT32 XCR0:1;\r
+ UINT32 XCR0 : 1;\r
///\r
/// [Bit 8] PT STate.\r
///\r
- UINT32 PT:1;\r
+ UINT32 PT : 1;\r
///\r
/// [Bit 9] Used for XCR0.\r
///\r
- UINT32 XCR0_1:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 XCR0_1 : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 13] HWP state.\r
///\r
- UINT32 HWPState:1;\r
- UINT32 Reserved8:18;\r
+ UINT32 HWPState : 1;\r
+ UINT32 Reserved8 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
\r
/**\r
}\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
\r
/**\r
CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
/// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
/// in XCR0.\r
///\r
- UINT32 XSS:1;\r
+ UINT32 XSS : 1;\r
///\r
/// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
/// this extended state component located on the next 64-byte boundary\r
/// following the preceding state component (otherwise, it is located\r
/// immediately following the preceding state component).\r
///\r
- UINT32 Compacted:1;\r
- UINT32 Reserved:30;\r
+ UINT32 Compacted : 1;\r
+ UINT32 Reserved : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
\r
-\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
\r
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING 0x0F\r
+#define CPUID_INTEL_RDT_MONITORING 0x0F\r
\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r
///\r
- UINT32 L3CacheRDT_M:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 L3CacheRDT_M : 1;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r
///\r
/// [Bit 0] Supports L3 occupancy monitoring if 1.\r
///\r
- UINT32 L3CacheOccupancyMonitoring:1;\r
+ UINT32 L3CacheOccupancyMonitoring : 1;\r
///\r
/// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r
///\r
- UINT32 L3CacheTotalBandwidthMonitoring:1;\r
+ UINT32 L3CacheTotalBandwidthMonitoring : 1;\r
///\r
/// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r
///\r
- UINT32 L3CacheLocalBandwidthMonitoring:1;\r
- UINT32 Reserved:29;\r
+ UINT32 L3CacheLocalBandwidthMonitoring : 1;\r
+ UINT32 Reserved : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r
\r
-\r
/**\r
CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r
\r
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
+#define CPUID_INTEL_RDT_ALLOCATION 0x10\r
\r
/**\r
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r
\r
/**\r
CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r
///\r
- UINT32 L3CacheAllocation:1;\r
+ UINT32 L3CacheAllocation : 1;\r
///\r
/// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r
///\r
- UINT32 L2CacheAllocation:1;\r
+ UINT32 L2CacheAllocation : 1;\r
///\r
/// [Bit 3] Supports Memory Bandwidth Allocation if 1.\r
///\r
- UINT32 MemoryBandwidth:1;\r
- UINT32 Reserved3:28;\r
+ UINT32 MemoryBandwidth : 1;\r
+ UINT32 Reserved3 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r
\r
-\r
/**\r
L3 Cache Allocation Technology Enumeration Sub-leaf\r
\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r
\r
/**\r
CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
/// using minus-one notation.\r
///\r
- UINT32 CapacityLength:5;\r
- UINT32 Reserved:27;\r
+ UINT32 CapacityLength : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved3:2;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
///\r
- UINT32 CodeDataPrioritization:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 CodeDataPrioritization : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r
\r
/**\r
CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r
/// using minus-one notation.\r
///\r
- UINT32 CapacityLength:5;\r
- UINT32 Reserved:27;\r
+ UINT32 CapacityLength : 5;\r
+ UINT32 Reserved : 27;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r
\r
/**\r
CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf\r
/// [Bits 11:0] Reports the maximum MBA throttling value supported for\r
/// the corresponding ResID using minus-one notation.\r
///\r
- UINT32 MaximumMBAThrottling:12;\r
- UINT32 Reserved:20;\r
+ UINT32 MaximumMBAThrottling : 12;\r
+ UINT32 Reserved : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 1:0] Reserved.\r
///\r
- UINT32 Reserved1:2;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bits 3] Reports whether the response of the delay values is linear.\r
///\r
- UINT32 Liner:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 Liner : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;\r
\r
/**\r
///\r
/// [Bits 15:0] Highest COS number supported for this ResID.\r
///\r
- UINT32 HighestCosNumber:16;\r
- UINT32 Reserved:16;\r
+ UINT32 HighestCosNumber : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;\r
\r
/**\r
until the sub-leaf type is invalid.\r
\r
**/\r
-#define CPUID_INTEL_SGX 0x12\r
+#define CPUID_INTEL_SGX 0x12\r
\r
/**\r
Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r
\r
/**\r
Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r
///\r
/// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r
///\r
- UINT32 SGX1:1;\r
+ UINT32 SGX1 : 1;\r
///\r
/// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r
///\r
- UINT32 SGX2:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 SGX2 : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves\r
/// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.\r
///\r
- UINT32 ENCLV:1;\r
+ UINT32 ENCLV : 1;\r
///\r
/// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,\r
/// ERDINFO, ELDBC, and ELDUC.\r
///\r
- UINT32 ENCLS:1;\r
- UINT32 Reserved2:25;\r
+ UINT32 ENCLS : 1;\r
+ UINT32 Reserved2 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r
\r
/**\r
/// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r
/// when not in 64-bit mode.\r
///\r
- UINT32 MaxEnclaveSize_Not64:8;\r
+ UINT32 MaxEnclaveSize_Not64 : 8;\r
///\r
/// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r
/// when operating in 64-bit mode.\r
///\r
- UINT32 MaxEnclaveSize_64:8;\r
- UINT32 Reserved:16;\r
+ UINT32 MaxEnclaveSize_64 : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r
\r
-\r
/**\r
Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r
Enumerates Intel SGX capability of processor state configuration and enclave\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
-\r
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r
\r
/**\r
Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r
/// in EBX:EAX and EDX:ECX.\r
/// All other encoding are reserved.\r
///\r
- UINT32 SubLeafType:4;\r
- UINT32 Reserved:8;\r
+ UINT32 SubLeafType : 4;\r
+ UINT32 Reserved : 8;\r
///\r
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r
/// the base of the EPC section.\r
///\r
- UINT32 LowAddressOfEpcSection:20;\r
+ UINT32 LowAddressOfEpcSection : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r
\r
/**\r
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r
/// the base of the EPC section.\r
///\r
- UINT32 HighAddressOfEpcSection:20;\r
- UINT32 Reserved:12;\r
+ UINT32 HighAddressOfEpcSection : 20;\r
+ UINT32 Reserved : 12;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r
\r
/**\r
/// 0001b: The EPC section is confidentiality, integrity and replay protected.\r
/// All other encoding are reserved.\r
///\r
- UINT32 EpcSection:4;\r
- UINT32 Reserved:8;\r
+ UINT32 EpcSection : 4;\r
+ UINT32 Reserved : 8;\r
///\r
/// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r
/// corresponding EPC section within the Processor Reserved Memory.\r
///\r
- UINT32 LowSizeOfEpcSection:20;\r
+ UINT32 LowSizeOfEpcSection : 20;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r
\r
/**\r
/// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r
/// corresponding EPC section within the Processor Reserved Memory.\r
///\r
- UINT32 HighSizeOfEpcSection:20;\r
- UINT32 Reserved:12;\r
+ UINT32 HighSizeOfEpcSection : 20;\r
+ UINT32 Reserved : 12;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r
\r
-\r
/**\r
CPUID Intel Processor Trace Information\r
\r
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
\r
/**\r
CPUID Intel Processor Trace Information Main Leaf\r
);\r
@endcode\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
/// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
///\r
- UINT32 Cr3Filter:1;\r
+ UINT32 Cr3Filter : 1;\r
///\r
/// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r
/// Mode.\r
///\r
- UINT32 ConfigurablePsb:1;\r
+ UINT32 ConfigurablePsb : 1;\r
///\r
/// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r
/// and preservation of Intel PT MSRs across warm reset.\r
///\r
- UINT32 IpTraceStopFiltering:1;\r
+ UINT32 IpTraceStopFiltering : 1;\r
///\r
/// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r
/// COFI-based packets.\r
///\r
- UINT32 Mtc:1;\r
+ UINT32 Mtc : 1;\r
///\r
/// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r
/// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r
/// can generate packets.\r
///\r
- UINT32 PTWrite:1;\r
+ UINT32 PTWrite : 1;\r
///\r
/// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r
/// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r
/// generation.\r
///\r
- UINT32 PowerEventTrace:1;\r
- UINT32 Reserved:26;\r
+ UINT32 PowerEventTrace : 1;\r
+ UINT32 Reserved : 26;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
\r
/**\r
/// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
/// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
///\r
- UINT32 RTIT:1;\r
+ UINT32 RTIT : 1;\r
///\r
/// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
/// the maximum allowed by the MaskOrTableOffset field of\r
/// IA32_RTIT_OUTPUT_MASK_PTRS.\r
///\r
- UINT32 ToPA:1;\r
+ UINT32 ToPA : 1;\r
///\r
/// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r
///\r
- UINT32 SingleRangeOutput:1;\r
+ UINT32 SingleRangeOutput : 1;\r
///\r
/// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r
///\r
- UINT32 TraceTransportSubsystem:1;\r
- UINT32 Reserved:27;\r
+ UINT32 TraceTransportSubsystem : 1;\r
+ UINT32 Reserved : 27;\r
///\r
/// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r
/// values, which include the CS base component.\r
///\r
- UINT32 LIP:1;\r
+ UINT32 LIP : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
\r
-\r
/**\r
CPUID Intel Processor Trace Information Sub-leaf\r
\r
}\r
@endcode\r
**/\r
-#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
\r
/**\r
CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
///\r
/// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
///\r
- UINT32 ConfigurableAddressRanges:3;\r
- UINT32 Reserved:13;\r
+ UINT32 ConfigurableAddressRanges : 3;\r
+ UINT32 Reserved : 13;\r
///\r
/// [Bits 31:16] Bitmap of supported MTC period encodings\r
///\r
- UINT32 MtcPeriodEncodings:16;\r
-\r
+ UINT32 MtcPeriodEncodings : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
///\r
- UINT32 CycleThresholdEncodings:16;\r
+ UINT32 CycleThresholdEncodings : 16;\r
///\r
/// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
///\r
- UINT32 PsbFrequencyEncodings:16;\r
-\r
+ UINT32 PsbFrequencyEncodings : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
\r
-\r
/**\r
CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r
\r
AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r
@endcode\r
**/\r
-#define CPUID_TIME_STAMP_COUNTER 0x15\r
-\r
+#define CPUID_TIME_STAMP_COUNTER 0x15\r
\r
/**\r
CPUID Processor Frequency Information\r
AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_PROCESSOR_FREQUENCY 0x16\r
+#define CPUID_PROCESSOR_FREQUENCY 0x16\r
\r
/**\r
CPUID Processor Frequency Information EAX for CPUID leaf\r
///\r
/// [Bits 15:0] Processor Base Frequency (in MHz).\r
///\r
- UINT32 ProcessorBaseFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 ProcessorBaseFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_EAX;\r
\r
/**\r
///\r
/// [Bits 15:0] Maximum Frequency (in MHz).\r
///\r
- UINT32 MaximumFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 MaximumFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_EBX;\r
\r
/**\r
///\r
/// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
///\r
- UINT32 BusFrequency:16;\r
- UINT32 Reserved:16;\r
+ UINT32 BusFrequency : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_PROCESSOR_FREQUENCY_ECX;\r
\r
-\r
/**\r
CPUID SoC Vendor Information\r
\r
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
\r
**/\r
-#define CPUID_SOC_VENDOR 0x17\r
+#define CPUID_SOC_VENDOR 0x17\r
\r
/**\r
CPUID SoC Vendor Information\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
\r
/**\r
CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
///\r
/// [Bits 15:0] SOC Vendor ID.\r
///\r
- UINT32 SocVendorId:16;\r
+ UINT32 SocVendorId : 16;\r
///\r
/// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
/// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
/// assigned by Intel.\r
///\r
- UINT32 IsVendorScheme:1;\r
- UINT32 Reserved:15;\r
+ UINT32 IsVendorScheme : 1;\r
+ UINT32 Reserved : 15;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
\r
/**\r
CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
///\r
/// 4 UTF-8 characters of Soc Vendor Brand String\r
///\r
- CHAR8 BrandString[4];\r
+ CHAR8 BrandString[4];\r
///\r
/// All fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
\r
/**\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
\r
/**\r
CPUID SoC Vendor Information\r
);\r
@endcode\r
**/\r
-#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
\r
/**\r
CPUID Deterministic Address Translation Parameters\r
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)\r
\r
**/\r
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r
\r
/**\r
CPUID Deterministic Address Translation Parameters\r
);\r
@endcode\r
**/\r
-#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.\r
///\r
/// [Bits 0] 4K page size entries supported by this structure.\r
///\r
- UINT32 Page4K:1;\r
+ UINT32 Page4K : 1;\r
///\r
/// [Bits 1] 2MB page size entries supported by this structure.\r
///\r
- UINT32 Page2M:1;\r
+ UINT32 Page2M : 1;\r
///\r
/// [Bits 2] 4MB page size entries supported by this structure.\r
///\r
- UINT32 Page4M:1;\r
+ UINT32 Page4M : 1;\r
///\r
/// [Bits 3] 1 GB page size entries supported by this structure.\r
///\r
- UINT32 Page1G:1;\r
+ UINT32 Page1G : 1;\r
///\r
/// [Bits 7:4] Reserved.\r
///\r
- UINT32 Reserved1:4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 10:8] Partitioning (0: Soft partitioning between the logical\r
/// processors sharing this structure)\r
///\r
- UINT32 Partitioning:3;\r
+ UINT32 Partitioning : 3;\r
///\r
/// [Bits 15:11] Reserved.\r
///\r
- UINT32 Reserved2:5;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bits 31:16] W = Ways of associativity.\r
///\r
- UINT32 Way:16;\r
+ UINT32 Way : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;\r
\r
/**\r
///\r
/// [Bits 4:0] Translation cache type field.\r
///\r
- UINT32 TranslationCacheType:5;\r
+ UINT32 TranslationCacheType : 5;\r
///\r
/// [Bits 7:5] Translation cache level (starts at 1).\r
///\r
- UINT32 TranslationCacheLevel:3;\r
+ UINT32 TranslationCacheLevel : 3;\r
///\r
/// [Bits 8] Fully associative structure.\r
///\r
- UINT32 FullyAssociative:1;\r
+ UINT32 FullyAssociative : 1;\r
///\r
/// [Bits 13:9] Reserved.\r
///\r
- UINT32 Reserved1:5;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 25:14] Maximum number of addressable IDs for logical\r
/// processors sharing this translation cache.\r
///\r
- UINT32 MaximumNum:12;\r
+ UINT32 MaximumNum : 12;\r
///\r
/// [Bits 31:26] Reserved.\r
///\r
- UINT32 Reserved2:6;\r
+ UINT32 Reserved2 : 6;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;\r
\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID Hybrid Information Enumeration Leaf\r
\r
@endcode\r
\r
**/\r
-#define CPUID_HYBRID_INFORMATION 0x1A\r
+#define CPUID_HYBRID_INFORMATION 0x1A\r
\r
///\r
/// CPUID Hybrid Information Enumeration main leaf\r
///\r
-#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r
+#define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r
\r
/**\r
CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,\r
/// across core types, and not related to the model ID reported in CPUID\r
/// leaf 01H, and does not identify the SOC.\r
///\r
- UINT32 NativeModelId:24;\r
+ UINT32 NativeModelId : 24;\r
///\r
/// [Bit 31:24] Core type\r
///\r
- UINT32 CoreType:8;\r
+ UINT32 CoreType : 8;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;\r
\r
///\r
/// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType\r
///\r
-#define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r
-#define CPUID_CORE_TYPE_INTEL_CORE 0x40\r
+#define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r
+#define CPUID_CORE_TYPE_INTEL_CORE 0x40\r
///\r
/// @}\r
///\r
\r
-\r
/**\r
CPUID V2 Extended Topology Enumeration Leaf\r
\r
@param ECX Level number\r
\r
**/\r
-#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r
+#define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r
\r
///\r
/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
/// The value of the "level type" field is not related to level numbers in\r
/// any way, higher "level type" values do not mean higher levels.\r
///\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r
-#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r
+#define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r
///\r
/// @}\r
///\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_FUNCTION 0x80000000\r
-\r
+#define CPUID_EXTENDED_FUNCTION 0x80000000\r
\r
/**\r
CPUID Extended Processor Signature and Feature Bits\r
AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
+#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
\r
/**\r
CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r
///\r
/// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
///\r
- UINT32 LAHF_SAHF:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 LAHF_SAHF : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 5] LZCNT.\r
///\r
- UINT32 LZCNT:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 LZCNT : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 8] PREFETCHW.\r
///\r
- UINT32 PREFETCHW:1;\r
- UINT32 Reserved3:23;\r
+ UINT32 PREFETCHW : 1;\r
+ UINT32 Reserved3 : 23;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CPU_SIG_ECX;\r
\r
/**\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r
///\r
- UINT32 SYSCALL_SYSRET:1;\r
- UINT32 Reserved2:8;\r
+ UINT32 SYSCALL_SYSRET : 1;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bit 20] Execute Disable Bit available.\r
///\r
- UINT32 NX:1;\r
- UINT32 Reserved3:5;\r
+ UINT32 NX : 1;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bit 26] 1-GByte pages are available if 1.\r
///\r
- UINT32 Page1GB:1;\r
+ UINT32 Page1GB : 1;\r
///\r
/// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r
///\r
- UINT32 RDTSCP:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 RDTSCP : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 29] Intel(R) 64 Architecture available if 1.\r
///\r
- UINT32 LM:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 LM : 1;\r
+ UINT32 Reserved5 : 2;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CPU_SIG_EDX;\r
\r
-\r
/**\r
CPUID Processor Brand String\r
\r
AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING1 0x80000002\r
+#define CPUID_BRAND_STRING1 0x80000002\r
\r
/**\r
CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r
///\r
/// 4 ASCII characters of Processor Brand String\r
///\r
- CHAR8 BrandString[4];\r
+ CHAR8 BrandString[4];\r
///\r
/// All fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_BRAND_STRING_DATA;\r
\r
/**\r
AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING2 0x80000003\r
+#define CPUID_BRAND_STRING2 0x80000003\r
\r
/**\r
CPUID Processor Brand String\r
AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_BRAND_STRING3 0x80000004\r
-\r
+#define CPUID_BRAND_STRING3 0x80000004\r
\r
/**\r
CPUID Extended Cache information\r
AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
+#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
\r
/**\r
CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r
///\r
/// [Bits 7:0] Cache line size in bytes.\r
///\r
- UINT32 CacheLineSize:8;\r
- UINT32 Reserved:4;\r
+ UINT32 CacheLineSize : 8;\r
+ UINT32 Reserved : 4;\r
///\r
/// [Bits 15:12] L2 Associativity field. Supported values are in the range\r
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r
/// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r
///\r
- UINT32 L2Associativity:4;\r
+ UINT32 L2Associativity : 4;\r
///\r
/// [Bits 31:16] Cache size in 1K units.\r
///\r
- UINT32 CacheSize:16;\r
+ UINT32 CacheSize : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_CACHE_INFO_ECX;\r
\r
///\r
AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
@endcode\r
**/\r
-#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
\r
/**\r
CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bit 8] Invariant TSC available if 1.\r
///\r
- UINT32 InvariantTsc:1;\r
- UINT32 Reserved2:23;\r
+ UINT32 InvariantTsc : 1;\r
+ UINT32 Reserved2 : 23;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r
\r
-\r
/**\r
CPUID Linear Physical Address Size\r
\r
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
@endcode\r
**/\r
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
\r
/**\r
CPUID Linear Physical Address Size EAX for CPUID leaf\r
/// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r
/// number supported should come from this field.\r
///\r
- UINT32 PhysicalAddressBits:8;\r
+ UINT32 PhysicalAddressBits : 8;\r
///\r
/// [Bits 15:8] Number of linear address bits.\r
///\r
- UINT32 LinearAddressBits:8;\r
- UINT32 Reserved:16;\r
+ UINT32 LinearAddressBits : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r
\r
#endif\r
//\r
// Definition for Local APIC registers and related values\r
//\r
-#define XAPIC_ID_OFFSET 0x20\r
-#define XAPIC_VERSION_OFFSET 0x30\r
-#define XAPIC_EOI_OFFSET 0x0b0\r
-#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
-#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
-#define XAPIC_ICR_LOW_OFFSET 0x300\r
-#define XAPIC_ICR_HIGH_OFFSET 0x310\r
-#define XAPIC_LVT_TIMER_OFFSET 0x320\r
-#define XAPIC_LVT_LINT0_OFFSET 0x350\r
-#define XAPIC_LVT_LINT1_OFFSET 0x360\r
-#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
-#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
-#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
-\r
-#define X2APIC_MSR_BASE_ADDRESS 0x800\r
-#define X2APIC_MSR_ICR_ADDRESS 0x830\r
-\r
-#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
-#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
-#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
-#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
-#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
-#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
-#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
-\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
-#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
+#define XAPIC_ID_OFFSET 0x20\r
+#define XAPIC_VERSION_OFFSET 0x30\r
+#define XAPIC_EOI_OFFSET 0x0b0\r
+#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
+#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
+#define XAPIC_ICR_LOW_OFFSET 0x300\r
+#define XAPIC_ICR_HIGH_OFFSET 0x310\r
+#define XAPIC_LVT_TIMER_OFFSET 0x320\r
+#define XAPIC_LVT_LINT0_OFFSET 0x350\r
+#define XAPIC_LVT_LINT1_OFFSET 0x360\r
+#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
+\r
+#define X2APIC_MSR_BASE_ADDRESS 0x800\r
+#define X2APIC_MSR_ICR_ADDRESS 0x830\r
+\r
+#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
+#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
+#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
+#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
+#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
+#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
+\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
\r
//\r
// Local APIC Version Register.\r
//\r
typedef union {\r
struct {\r
- UINT32 Version:8; ///< The version numbers of the local APIC.\r
- UINT32 Reserved0:8; ///< Reserved.\r
- UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1.\r
- UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported.\r
- UINT32 Reserved1:7; ///< Reserved.\r
+ UINT32 Version : 8; ///< The version numbers of the local APIC.\r
+ UINT32 Reserved0 : 8; ///< Reserved.\r
+ UINT32 MaxLvtEntry : 8; ///< Number of LVT entries minus 1.\r
+ UINT32 EoiBroadcastSuppression : 1; ///< 1 if EOI-broadcast suppression supported.\r
+ UINT32 Reserved1 : 7; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_VERSION;\r
//\r
typedef union {\r
struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent.\r
- UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode.\r
- UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
- UINT32 Reserved0:1; ///< Reserved.\r
- UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
- UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
- UINT32 Reserved1:2; ///< Reserved.\r
- UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt.\r
- UINT32 Reserved2:12; ///< Reserved.\r
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode : 3; ///< Specifies the type of IPI to be sent.\r
+ UINT32 DestinationMode : 1; ///< 0: physical destination mode, 1: logical destination mode.\r
+ UINT32 DeliveryStatus : 1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
+ UINT32 Reserved0 : 1; ///< Reserved.\r
+ UINT32 Level : 1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
+ UINT32 TriggerMode : 1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
+ UINT32 Reserved1 : 2; ///< Reserved.\r
+ UINT32 DestinationShorthand : 2; ///< A shorthand notation to specify the destination of the interrupt.\r
+ UINT32 Reserved2 : 12; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_ICR_LOW;\r
//\r
typedef union {\r
struct {\r
- UINT32 Reserved0:24; ///< Reserved.\r
- UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode.\r
+ UINT32 Reserved0 : 24; ///< Reserved.\r
+ UINT32 Destination : 8; ///< Specifies the target processor or processors in xAPIC mode.\r
} Bits;\r
UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
} LOCAL_APIC_ICR_HIGH;\r
//\r
typedef union {\r
struct {\r
- UINT32 SpuriousVector:8; ///< Spurious Vector.\r
- UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable.\r
- UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking.\r
- UINT32 Reserved0:2; ///< Reserved.\r
- UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression.\r
- UINT32 Reserved1:19; ///< Reserved.\r
+ UINT32 SpuriousVector : 8; ///< Spurious Vector.\r
+ UINT32 SoftwareEnable : 1; ///< APIC Software Enable/Disable.\r
+ UINT32 FocusProcessorChecking : 1; ///< Focus Processor Checking.\r
+ UINT32 Reserved0 : 2; ///< Reserved.\r
+ UINT32 EoiBroadcastSuppression : 1; ///< EOI-Broadcast Suppression.\r
+ UINT32 Reserved1 : 19; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_SVR;\r
//\r
typedef union {\r
struct {\r
- UINT32 DivideValue1:2; ///< Low 2 bits of the divide value.\r
- UINT32 Reserved0:1; ///< Always 0.\r
- UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value.\r
- UINT32 Reserved1:28; ///< Reserved.\r
+ UINT32 DivideValue1 : 2; ///< Low 2 bits of the divide value.\r
+ UINT32 Reserved0 : 1; ///< Always 0.\r
+ UINT32 DivideValue2 : 1; ///< Highest 1 bit of the divide value.\r
+ UINT32 Reserved1 : 28; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_DCR;\r
//\r
typedef union {\r
struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 Reserved0:4; ///< Reserved.\r
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
- UINT32 Reserved1:3; ///< Reserved.\r
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
- UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic.\r
- UINT32 Reserved2:14; ///< Reserved.\r
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
+ UINT32 Reserved0 : 4; ///< Reserved.\r
+ UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.\r
+ UINT32 Reserved1 : 3; ///< Reserved.\r
+ UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 TimerMode : 1; ///< 0: One-shot, 1: Periodic.\r
+ UINT32 Reserved2 : 14; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_LVT_TIMER;\r
//\r
typedef union {\r
struct {\r
- UINT32 Vector:8; ///< The vector number of the interrupt being sent.\r
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
- UINT32 Reserved0:1; ///< Reserved.\r
- UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending.\r
- UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity.\r
- UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
- UINT32 TriggerMode:1; ///< 0:edge, 1:level.\r
- UINT32 Mask:1; ///< 0: Not masked, 1: Masked.\r
- UINT32 Reserved1:15; ///< Reserved.\r
+ UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
+ UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0 : 1; ///< Reserved.\r
+ UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.\r
+ UINT32 InputPinPolarity : 1; ///< Interrupt Input Pin Polarity.\r
+ UINT32 RemoteIrr : 1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
+ UINT32 TriggerMode : 1; ///< 0:edge, 1:level.\r
+ UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.\r
+ UINT32 Reserved1 : 15; ///< Reserved.\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_LVT_LINT;\r
//\r
typedef union {\r
struct {\r
- UINT32 Reserved0:2; ///< Reserved\r
- UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r
- UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r
- UINT32 Reserved1:8; ///< Reserved.\r
- UINT32 DestinationId:8; ///< Specifies the Destination ID.\r
- UINT32 BaseAddress:12; ///< Must be 0FEEH\r
+ UINT32 Reserved0 : 2; ///< Reserved\r
+ UINT32 DestinationMode : 1; ///< Specifies the Destination Mode.\r
+ UINT32 RedirectionHint : 1; ///< Specifies the Redirection Hint.\r
+ UINT32 Reserved1 : 8; ///< Reserved.\r
+ UINT32 DestinationId : 8; ///< Specifies the Destination ID.\r
+ UINT32 BaseAddress : 12; ///< Must be 0FEEH\r
} Bits;\r
UINT32 Uint32;\r
} LOCAL_APIC_MSI_ADDRESS;\r
//\r
typedef union {\r
struct {\r
- UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r
- UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
- UINT32 Reserved0:3; ///< Reserved.\r
- UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
- UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r
- UINT32 Reserved1:16; ///< Reserved.\r
- UINT32 Reserved2:32; ///< Reserved.\r
+ UINT32 Vector : 8; ///< Interrupt vector in range 010h..0FEH\r
+ UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0 : 3; ///< Reserved.\r
+ UINT32 Level : 1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
+ UINT32 TriggerMode : 1; ///< 0:Edge, 1:Level.\r
+ UINT32 Reserved1 : 16; ///< Reserved.\r
+ UINT32 Reserved2 : 32; ///< Reserved.\r
} Bits;\r
UINT64 Uint64;\r
} LOCAL_APIC_MSI_DATA;\r
\r
#endif\r
-\r
///\r
typedef union {\r
struct {\r
- UINT32 Year:16;\r
- UINT32 Day:8;\r
- UINT32 Month:8;\r
+ UINT32 Year : 16;\r
+ UINT32 Day : 8;\r
+ UINT32 Month : 8;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPU_MICROCODE_DATE;\r
\r
///\r
///\r
typedef union {\r
struct {\r
- UINT32 Stepping:4;\r
- UINT32 Model:4;\r
- UINT32 Family:4;\r
- UINT32 Type:2;\r
- UINT32 Reserved1:2;\r
- UINT32 ExtendedModel:4;\r
- UINT32 ExtendedFamily:8;\r
- UINT32 Reserved2:4;\r
+ UINT32 Stepping : 4;\r
+ UINT32 Model : 4;\r
+ UINT32 Family : 4;\r
+ UINT32 Type : 2;\r
+ UINT32 Reserved1 : 2;\r
+ UINT32 ExtendedModel : 4;\r
+ UINT32 ExtendedFamily : 8;\r
+ UINT32 Reserved2 : 4;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} CPU_MICROCODE_PROCESSOR_SIGNATURE;\r
\r
#pragma pack (1)\r
///\r
/// Version number of the update header\r
///\r
- UINT32 HeaderVersion;\r
+ UINT32 HeaderVersion;\r
///\r
/// Unique version number for the update, the basis for the update\r
/// signature provided by the processor to indicate the current update\r
/// value in this field cannot be used for processor stepping identification\r
/// alone. This is a signed 32-bit number.\r
///\r
- UINT32 UpdateRevision;\r
+ UINT32 UpdateRevision;\r
///\r
/// Date of the update creation in binary format: mmddyyyy (e.g.\r
/// 07/18/98 is 07181998H).\r
///\r
- CPU_MICROCODE_DATE Date;\r
+ CPU_MICROCODE_DATE Date;\r
///\r
/// Extended family, extended model, type, family, model, and stepping\r
/// of processor that requires this particular update revision (e.g.,\r
/// this field exactly corresponds to the bit representations returned by\r
/// the CPUID instruction.\r
///\r
- CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
///\r
/// Checksum of Update Data and Header. Used to verify the integrity of\r
/// the update header and data. Checksum is correct when the\r
/// Signature Table) that comprise the microcode update result in\r
/// 00000000H.\r
///\r
- UINT32 Checksum;\r
+ UINT32 Checksum;\r
///\r
/// Version number of the loader program needed to correctly load this\r
/// update. The initial version is 00000001H\r
///\r
- UINT32 LoaderRevision;\r
+ UINT32 LoaderRevision;\r
///\r
/// Platform type information is encoded in the lower 8 bits of this 4-\r
/// byte field. Each bit represents a particular platform type for a given\r
/// update is appropriate to load on a processor. Multiple bits may be set\r
/// representing support for multiple platform IDs.\r
///\r
- UINT32 ProcessorFlags;\r
+ UINT32 ProcessorFlags;\r
///\r
/// Specifies the size of the encrypted data in bytes, and must be a\r
/// multiple of DWORDs. If this value is 00000000H, then the microcode\r
/// update encrypted data is 2000 bytes (or 500 DWORDs).\r
///\r
- UINT32 DataSize;\r
+ UINT32 DataSize;\r
///\r
/// Specifies the total size of the microcode update in bytes. It is the\r
/// summation of the header size, the encrypted data size and the size of\r
/// the optional extended signature table. This value is always a multiple\r
/// of 1024.\r
///\r
- UINT32 TotalSize;\r
+ UINT32 TotalSize;\r
///\r
/// Reserved fields for future expansion.\r
///\r
- UINT8 Reserved[12];\r
+ UINT8 Reserved[12];\r
} CPU_MICROCODE_HEADER;\r
\r
///\r
/// Signature[n], processor flags[n] and checksum[n]) that exist in this\r
/// microcode update\r
///\r
- UINT32 ExtendedSignatureCount;\r
+ UINT32 ExtendedSignatureCount;\r
///\r
/// Checksum of update extended processor signature table. Used to\r
/// verify the integrity of the extended processor signature table.\r
/// comprise the extended processor signature table results in\r
/// 00000000H.\r
///\r
- UINT32 ExtendedChecksum;\r
+ UINT32 ExtendedChecksum;\r
///\r
/// Reserved fields.\r
///\r
- UINT8 Reserved[12];\r
+ UINT8 Reserved[12];\r
} CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
\r
///\r
/// this field exactly corresponds to the bit representations returned by\r
/// the CPUID instruction.\r
///\r
- CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
+ CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;\r
///\r
/// Platform type information is encoded in the lower 8 bits of this 4-\r
/// byte field. Each bit represents a particular platform type for a given\r
/// update is appropriate to load on a processor. Multiple bits may be set\r
/// representing support for multiple platform IDs.\r
///\r
- UINT32 ProcessorFlag;\r
+ UINT32 ProcessorFlag;\r
///\r
/// Used by utility software to decompose a microcode update into\r
/// multiple microcode updates where each of the new updates is\r
/// summation of all DWORDs that comprise the created Extended\r
/// Processor Patch results in 00000000H.\r
///\r
- UINT32 Checksum;\r
+ UINT32 Checksum;\r
} CPU_MICROCODE_EXTENDED_TABLE;\r
\r
#pragma pack ()\r
@endcode\r
@note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_ATOM_PLATFORM_ID 0x00000017\r
+#define MSR_ATOM_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:32;\r
+ UINT32 MaximumQualifiedRatio : 5;\r
+ UINT32 Reserved2 : 19;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
processor features; (R) indicates current processor configuration.\r
@endcode\r
@note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r
+#define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Always 0.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Always 0.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
///\r
- UINT32 AERR_DriveEnable:1;\r
+ UINT32 AERR_DriveEnable : 1;\r
///\r
/// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r
/// Disabled Always 0.\r
///\r
- UINT32 BERR_Enable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 BERR_Enable : 1;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
/// Always 0.\r
///\r
- UINT32 AERR_ObservationEnabled:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 AERR_ObservationEnabled : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
/// Always 0.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r
///\r
- UINT32 APICClusterID:2;\r
- UINT32 Reserved8:2;\r
+ UINT32 APICClusterID : 2;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved9:5;\r
- UINT32 Reserved10:32;\r
+ UINT32 IntegerBusFrequencyRatio : 5;\r
+ UINT32 Reserved9 : 5;\r
+ UINT32 Reserved10 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r
-#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r
-#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r
-#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r
-#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r
+#define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r
/// @}\r
\r
-\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The To_IP part of the\r
MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r
-#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r
-#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r
-#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r
-#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r
+#define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r
/// @}\r
\r
-\r
/**\r
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Intel Atom microarchitecture:.\r
@endcode\r
@note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_ATOM_FSB_FREQ 0x000000CD\r
+#define MSR_ATOM_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r
/// System Bus Speed when\r
/// encoding is 011B.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_FSB_FREQ_REGISTER;\r
\r
-\r
/**\r
Shared.\r
\r
@endcode\r
@note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r
+#define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved3 : 8;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
Shared.\r
\r
@endcode\r
@note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
-#define MSR_ATOM_PERF_STATUS 0x00000198\r
+#define MSR_ATOM_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r
///\r
/// [Bits 15:0] Current Performance State Value.\r
///\r
- UINT32 CurrentPerformanceStateValue:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:8;\r
+ UINT32 CurrentPerformanceStateValue : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
/// configured for the processor.\r
///\r
- UINT32 MaximumBusRatio:5;\r
- UINT32 Reserved3:19;\r
+ UINT32 MaximumBusRatio : 5;\r
+ UINT32 Reserved3 : 19;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
Shared.\r
\r
@endcode\r
@note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_ATOM_THERM2_CTL 0x0000019D\r
+#define MSR_ATOM_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 0.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
/// the processor to indicate a pending break event within the processor 0\r
/// = Indicates compatible FERR# signaling behavior This bit must be set\r
/// to 1 to support XAPIC interrupt model usage.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
+ UINT32 PEBS : 1;\r
///\r
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
/// thermal sensor indicates that the die temperature is at the\r
/// contents of the TM2 bit location. The processor is operating out of\r
/// specification if both this bit and the TM1 bit are set to 0.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved5 : 2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
/// (R/WO) When set, this bit causes the following bits to become\r
/// be set before an Enhanced Intel SpeedStep Technology transition is\r
/// requested. This bit is cleared on reset.\r
///\r
- UINT32 EISTLock:1;\r
- UINT32 Reserved8:1;\r
+ UINT32 EISTLock : 1;\r
+ UINT32 Reserved8 : 1;\r
///\r
/// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved9:8;\r
- UINT32 Reserved10:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved9 : 8;\r
+ UINT32 Reserved10 : 2;\r
///\r
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved11:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved11 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_ATOM_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_ATOM_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_ATOM_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_ATOM_LER_TO_LIP 0x000001DE\r
\r
/**\r
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
@endcode\r
@note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_ATOM_PEBS_ENABLE 0x000003F1\r
+#define MSR_ATOM_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Package C2 Residency Note: C-state values are processor specific\r
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
@endcode\r
@note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r
-\r
+#define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Package C4 Residency Note: C-state values are processor specific\r
@endcode\r
@note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r
**/\r
-#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r
-\r
+#define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Package C6 Residency Note: C-state values are processor specific\r
@endcode\r
@note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r
+#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r
\r
#endif\r
@endcode\r
@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
/// Addresses (ToPA).".\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:5;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bit 61] Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Ovf_BufDSSAVE.\r
///\r
- UINT32 OvfBuf:1;\r
+ UINT32 OvfBuf : 1;\r
///\r
/// [Bit 63] CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
+ UINT32 Limit : 4;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
+ UINT32 C1Undemotion : 1;\r
///\r
/// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
///\r
- UINT32 CStateAutoDemotion:1;\r
+ UINT32 CStateAutoDemotion : 1;\r
///\r
/// [Bit 30] Enable Package C-State Undemotion (R/W).\r
///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUndemotion : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6core active.\r
///\r
- UINT32 Maximum6C:8;\r
- UINT32 Reserved:16;\r
+ UINT32 Maximum6C : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
fields represent the widest possible range of uncore frequencies. Writing to\r
AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved2:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved3:17;\r
- UINT32 Reserved4:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved3 : 17;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
+#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
\r
#endif\r
@endcode\r
@note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_CORE2_PLATFORM_ID 0x00000017\r
+#define MSR_CORE2_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
+ UINT32 MaximumQualifiedRatio : 5;\r
+ UINT32 Reserved2 : 19;\r
+ UINT32 Reserved3 : 18;\r
///\r
/// [Bits 52:50] See Table 2-2.\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved4 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
processor features; (R) indicates current processor configuration.\r
@endcode\r
@note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
+#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 MCERR_DriveEnable:1;\r
+ UINT32 MCERR_DriveEnable : 1;\r
///\r
/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
/// Not all processor implements R/W.\r
///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 AddressParityEnable : 1;\r
+ UINT32 Reserved2 : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 MCERR_ObservationEnabled:1;\r
+ UINT32 MCERR_ObservationEnabled : 1;\r
///\r
/// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r
///\r
- UINT32 IntelTXTCapableChipset:1;\r
+ UINT32 IntelTXTCapableChipset : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O).\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r
/// Non-integer ratio.\r
///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 NonIntegerBusRatio : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
///\r
- UINT32 IntegerBusFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
+ UINT32 IntegerBusFrequencyRatio : 5;\r
+ UINT32 Reserved7 : 5;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.\r
\r
@endcode\r
@note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
+#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r
/// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r
/// visible and writeable while in SMM.\r
///\r
- UINT32 SMRREnable:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMRREnable : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
/// @}\r
\r
-\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
record registers on the last branch record stack. This To_IP part of the\r
MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
/// @}\r
\r
-\r
/**\r
Unique. System Management Mode Base Address register (WO in SMM)\r
Model-specific implementation of SMRR-like interface, read visible and write\r
@endcode\r
@note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r
**/\r
-#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
+#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:12;\r
+ UINT32 Reserved1 : 12;\r
///\r
/// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
///\r
- UINT32 PhysBase:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysBase : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r
\r
-\r
/**\r
Unique. System Management Mode Physical Address Mask register (WO in SMM)\r
Model-specific implementation of SMRR-like interface, read visible and write\r
@endcode\r
@note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r
**/\r
-#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
+#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Valid. Physical address base and range mask are valid.\r
///\r
- UINT32 Valid:1;\r
+ UINT32 Valid : 1;\r
///\r
/// [Bits 31:12] PhysMask. SMRR physical address range mask.\r
///\r
- UINT32 PhysMask:20;\r
- UINT32 Reserved2:32;\r
+ UINT32 PhysMask : 20;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r
\r
-\r
/**\r
Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Intel Core microarchitecture:.\r
@endcode\r
@note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_CORE2_FSB_FREQ 0x000000CD\r
+#define MSR_CORE2_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r
/// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r
/// performing calculation with System Bus Speed when encoding is 100B.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_FSB_FREQ_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_STATUS 0x00000198\r
+#define MSR_CORE2_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r
///\r
/// [Bits 15:0] Current Performance State Value.\r
///\r
- UINT32 CurrentPerformanceStateValue:16;\r
- UINT32 Reserved1:15;\r
+ UINT32 CurrentPerformanceStateValue : 16;\r
+ UINT32 Reserved1 : 15;\r
///\r
/// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r
/// is cleared.\r
///\r
- UINT32 XEOperation:1;\r
- UINT32 Reserved2:8;\r
+ UINT32 XEOperation : 1;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
/// configured for the processor.\r
///\r
- UINT32 MaximumBusRatio:5;\r
- UINT32 Reserved3:1;\r
+ UINT32 MaximumBusRatio : 5;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r
/// is enabled. Applies processors based on Enhanced Intel Core\r
/// microarchitecture.\r
///\r
- UINT32 NonIntegerBusRatio:1;\r
- UINT32 Reserved4:17;\r
+ UINT32 NonIntegerBusRatio : 1;\r
+ UINT32 Reserved4 : 17;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_CORE2_THERM2_CTL 0x0000019D\r
+#define MSR_CORE2_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r
/// hardware prefetcher operation on streams of data. When clear\r
/// (default), enables the prefetch queue. Disabling of the hardware\r
/// prefetcher may impact processor performance.\r
///\r
- UINT32 HardwarePrefetcherDisable:1;\r
+ UINT32 HardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
/// the processor to indicate a pending break event within the processor 0\r
/// = Indicates compatible FERR# signaling behavior This bit must be set\r
/// to 1 to support XAPIC interrupt model usage.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
+ UINT32 PEBS : 1;\r
///\r
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
/// thermal sensor indicates that the die temperature is at the\r
/// contents of the TM2 bit location. The processor is operating out of\r
/// specification if both this bit and the TM1 bit are set to 0.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r
/// to 1, the processor fetches the cache line that contains data\r
/// validation and testing. BIOS may contain a setup option that controls\r
/// the setting of this bit.\r
///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ UINT32 AdjacentCacheLinePrefetchDisable : 1;\r
///\r
/// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
/// (R/WO) When set, this bit causes the following bits to become\r
/// be set before an Enhanced Intel SpeedStep Technology transition is\r
/// requested. This bit is cleared on reset.\r
///\r
- UINT32 EISTLock:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 EISTLock : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:2;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 2;\r
///\r
/// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r
/// L1 data cache prefetcher is disabled. The default value after reset is\r
/// assumes the next line will be required. The next line is prefetched in\r
/// to the L1 data cache from memory or L2.\r
///\r
- UINT32 DCUPrefetcherDisable:1;\r
+ UINT32 DCUPrefetcherDisable : 1;\r
///\r
/// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r
/// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r
/// power-on default value is 1, IDA is available in the processor. If\r
/// power-on default value is 0, IDA is not available.\r
///\r
- UINT32 IDADisable:1;\r
+ UINT32 IDADisable : 1;\r
///\r
/// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r
/// prefetcher is disabled. The default value after reset is 0. BIOS may\r
/// to determine whether to prefetch the next expected data into the L1\r
/// cache from memory or L2.\r
///\r
- UINT32 IPPrefetcherDisable:1;\r
- UINT32 Reserved10:24;\r
+ UINT32 IPPrefetcherDisable : 1;\r
+ UINT32 Reserved10 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
\r
/**\r
Unique. Fixed-Function Performance Counter Register n (R/W).\r
MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
-#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
-#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
+#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
+#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
+#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
/// @}\r
\r
-\r
/**\r
Unique. RO. This applies to processors that do not support architectural\r
perfmon version 2.\r
@endcode\r
@note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r
**/\r
-#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
+#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r
///\r
/// [Bits 5:0] LBR Format. See Table 2-2.\r
///\r
- UINT32 LBR_FMT:6;\r
+ UINT32 LBR_FMT : 6;\r
///\r
/// [Bit 6] PEBS Record Format.\r
///\r
- UINT32 PEBS_FMT:1;\r
+ UINT32 PEBS_FMT : 1;\r
///\r
/// [Bit 7] PEBSSaveArchRegs. See Table 2-2.\r
///\r
- UINT32 PEBS_ARCH_REG:1;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 PEBS_ARCH_REG : 1;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r
\r
-\r
/**\r
Unique. Fixed-Function-Counter Control Register (R/W).\r
\r
@endcode\r
@note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
-\r
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
\r
/**\r
Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
-\r
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
@endcode\r
@note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
+#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
-#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
-#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
-#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
-#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
-#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
-#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
-#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
+#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
+#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
+#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
+#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
+#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
+#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
+#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
+#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
/// @}\r
\r
-\r
/**\r
Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r
7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
@endcode\r
@note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r
**/\r
-#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
+#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
\r
#endif\r
@endcode\r
@note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_CORE_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_CORE_P5_MC_ADDR 0x00000000\r
\r
/**\r
Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.\r
@endcode\r
@note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_CORE_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_CORE_P5_MC_TYPE 0x00000001\r
\r
/**\r
Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
@endcode\r
@note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
+#define MSR_CORE_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
/// Note: Not all processor implements R/W.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 MCERR_DriveEnable:1;\r
+ UINT32 MCERR_DriveEnable : 1;\r
///\r
/// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
/// Not all processor implements R/W.\r
///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 AddressParityEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
/// all processor implements R/W.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 MCERR_ObservationEnabled : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O).\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.\r
///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 SystemBusFrequency : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Clock Frequency Ratio (R/O).\r
///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
+ UINT32 ClockFrequencyRatio : 5;\r
+ UINT32 Reserved7 : 5;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on\r
the last branch record stack: bits 31-0 hold the 'from' address and bits\r
MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_LASTBRANCH_0 0x00000040\r
-#define MSR_CORE_LASTBRANCH_1 0x00000041\r
-#define MSR_CORE_LASTBRANCH_2 0x00000042\r
-#define MSR_CORE_LASTBRANCH_3 0x00000043\r
-#define MSR_CORE_LASTBRANCH_4 0x00000044\r
-#define MSR_CORE_LASTBRANCH_5 0x00000045\r
-#define MSR_CORE_LASTBRANCH_6 0x00000046\r
-#define MSR_CORE_LASTBRANCH_7 0x00000047\r
+#define MSR_CORE_LASTBRANCH_0 0x00000040\r
+#define MSR_CORE_LASTBRANCH_1 0x00000041\r
+#define MSR_CORE_LASTBRANCH_2 0x00000042\r
+#define MSR_CORE_LASTBRANCH_3 0x00000043\r
+#define MSR_CORE_LASTBRANCH_4 0x00000044\r
+#define MSR_CORE_LASTBRANCH_5 0x00000045\r
+#define MSR_CORE_LASTBRANCH_6 0x00000046\r
+#define MSR_CORE_LASTBRANCH_7 0x00000047\r
/// @}\r
\r
-\r
/**\r
Shared. Scalable Bus Speed (RO) This field indicates the scalable bus\r
clock speed:.\r
@endcode\r
@note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_CORE_FSB_FREQ 0x000000CD\r
+#define MSR_CORE_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_FSB_FREQ\r
/// Speed when encoding is 101B. 166.67 MHz should be utilized if\r
/// performing calculation with System Bus Speed when encoding is 001B.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_FSB_FREQ_REGISTER;\r
\r
-\r
/**\r
Shared.\r
\r
@endcode\r
@note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
+#define MSR_CORE_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved3 : 8;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_CORE_THERM2_CTL 0x0000019D\r
+#define MSR_CORE_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_CORE_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
/// the processor to indicate a pending break event within the processor 0\r
/// = Indicates compatible FERR# signaling behavior This bit must be set\r
/// to 1 to support XAPIC interrupt model usage.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BTS : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
/// thermal sensor indicates that the die temperature is at the\r
/// out of spec if both this bit and the TM1 bit are set to disabled\r
/// states.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved5 : 2;\r
///\r
/// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
/// Enhanced Intel SpeedStep Technology enabled.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved7:1;\r
- UINT32 Reserved8:2;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved7 : 1;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this\r
/// bit may cause behavior in software that depends on the availability of\r
/// CPUID leaves greater than 2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
- UINT32 Reserved9:9;\r
- UINT32 Reserved10:2;\r
+ UINT32 LimitCpuidMaxval : 1;\r
+ UINT32 Reserved9 : 9;\r
+ UINT32 Reserved10 : 2;\r
///\r
/// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved11:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved11 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_CORE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_CORE_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_CORE_LER_TO_LIP 0x000001DE\r
+#define MSR_CORE_LER_TO_LIP 0x000001DE\r
\r
/**\r
Unique.\r
MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
-#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
-#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
-#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
-#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
-#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
-#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
-#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
+#define MSR_CORE_MTRRPHYSBASE0 0x00000200\r
+#define MSR_CORE_MTRRPHYSBASE1 0x00000202\r
+#define MSR_CORE_MTRRPHYSBASE2 0x00000204\r
+#define MSR_CORE_MTRRPHYSBASE3 0x00000206\r
+#define MSR_CORE_MTRRPHYSBASE4 0x00000208\r
+#define MSR_CORE_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_CORE_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_CORE_MTRRPHYSMASK7 0x0000020F\r
/// @}\r
\r
-\r
/**\r
Unique.\r
\r
MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
@{\r
**/\r
-#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
-#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
-#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
-#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
-#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
-#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
-#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
-#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
+#define MSR_CORE_MTRRPHYSMASK0 0x00000201\r
+#define MSR_CORE_MTRRPHYSMASK1 0x00000203\r
+#define MSR_CORE_MTRRPHYSMASK2 0x00000205\r
+#define MSR_CORE_MTRRPHYSMASK3 0x00000207\r
+#define MSR_CORE_MTRRPHYSMASK4 0x00000209\r
+#define MSR_CORE_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_CORE_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_CORE_MTRRPHYSBASE7 0x0000020E\r
/// @}\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
-\r
+#define MSR_CORE_MTRRFIX64K_00000 0x00000250\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
-\r
+#define MSR_CORE_MTRRFIX16K_80000 0x00000258\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
-\r
+#define MSR_CORE_MTRRFIX16K_A0000 0x00000259\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
-\r
+#define MSR_CORE_MTRRFIX4K_C0000 0x00000268\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
-\r
+#define MSR_CORE_MTRRFIX4K_C8000 0x00000269\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
-\r
+#define MSR_CORE_MTRRFIX4K_D0000 0x0000026A\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
-\r
+#define MSR_CORE_MTRRFIX4K_D8000 0x0000026B\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
-\r
+#define MSR_CORE_MTRRFIX4K_E0000 0x0000026C\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
-\r
+#define MSR_CORE_MTRRFIX4K_E8000 0x0000026D\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
-\r
+#define MSR_CORE_MTRRFIX4K_F0000 0x0000026E\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
**/\r
-#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
-\r
+#define MSR_CORE_MTRRFIX4K_F8000 0x0000026F\r
\r
/**\r
Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
**/\r
-#define MSR_CORE_MC4_CTL 0x0000040C\r
-\r
+#define MSR_CORE_MC4_CTL 0x0000040C\r
\r
/**\r
Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
@endcode\r
@note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
**/\r
-#define MSR_CORE_MC4_STATUS 0x0000040D\r
-\r
+#define MSR_CORE_MC4_STATUS 0x0000040D\r
\r
/**\r
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
@endcode\r
@note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC4_ADDR 0x0000040E\r
-\r
+#define MSR_CORE_MC4_ADDR 0x0000040E\r
\r
/**\r
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
@endcode\r
@note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC3_ADDR 0x00000412\r
-\r
+#define MSR_CORE_MC3_ADDR 0x00000412\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
**/\r
-#define MSR_CORE_MC3_MISC 0x00000413\r
-\r
+#define MSR_CORE_MC3_MISC 0x00000413\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
**/\r
-#define MSR_CORE_MC5_CTL 0x00000414\r
-\r
+#define MSR_CORE_MC5_CTL 0x00000414\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
**/\r
-#define MSR_CORE_MC5_STATUS 0x00000415\r
-\r
+#define MSR_CORE_MC5_STATUS 0x00000415\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
**/\r
-#define MSR_CORE_MC5_ADDR 0x00000416\r
-\r
+#define MSR_CORE_MC5_ADDR 0x00000416\r
\r
/**\r
Unique.\r
@endcode\r
@note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
**/\r
-#define MSR_CORE_MC5_MISC 0x00000417\r
-\r
+#define MSR_CORE_MC5_MISC 0x00000417\r
\r
/**\r
Unique. See Table 2-2.\r
@endcode\r
@note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.\r
**/\r
-#define MSR_CORE_IA32_EFER 0xC0000080\r
+#define MSR_CORE_IA32_EFER 0xC0000080\r
\r
/**\r
MSR information returned for MSR index #MSR_CORE_IA32_EFER\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:11;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 11] Execute Disable Bit Enable.\r
///\r
- UINT32 NXE:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 NXE : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_CORE_IA32_EFER_REGISTER;\r
\r
#endif\r
@endcode\r
@note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
+#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r
///\r
/// [Bit 0] Lock bit (R/WL)\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
///\r
/// [Bit 1] Enable VMX inside SMX operation (R/WL)\r
///\r
- UINT32 EnableVmxInsideSmx:1;\r
+ UINT32 EnableVmxInsideSmx : 1;\r
///\r
/// [Bit 2] Enable VMX outside SMX operation (R/WL)\r
///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 EnableVmxOutsideSmx : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bits 14:8] SENTER local function enables (R/WL)\r
///\r
- UINT32 SenterLocalFunctionEnables:7;\r
+ UINT32 SenterLocalFunctionEnables : 7;\r
///\r
/// [Bit 15] SENTER global functions enable (R/WL)\r
///\r
- UINT32 SenterGlobalEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 SenterGlobalEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 18] SGX global functions enable (R/WL)\r
///\r
- UINT32 SgxEnable:1;\r
- UINT32 Reserved3:13;\r
- UINT32 Reserved4:32;\r
+ UINT32 SgxEnable : 1;\r
+ UINT32 Reserved3 : 13;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. See http://biosbits.org.\r
\r
@endcode\r
@note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
+#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
/// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
/// specify an temperature offset.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved3:1;\r
- UINT32 Reserved4:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved3 : 1;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r
/// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r
/// 0111b: C9 1000b: C10.\r
///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
+ UINT32 Limit : 4;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 16;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r
Accessible only while in SMM.\r
@endcode\r
@note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
+#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and the\r
/// MSR_SMM_FEATURE_CONTROL is supported.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
/// supported.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 1.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. See http://biosbits.org.\r
\r
@endcode\r
@note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
-#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
+#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r
/// from processor cores; When 1, disables hardware coordination of\r
/// Enhanced Intel Speedstep Technology requests.\r
///\r
- UINT32 EISTHardwareCoordinationDisable:1;\r
- UINT32 Reserved1:21;\r
+ UINT32 EISTHardwareCoordinationDisable : 1;\r
+ UINT32 Reserved1 : 21;\r
///\r
/// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r
/// thermal interrupt on one core is routed to all cores.\r
///\r
- UINT32 ThermalInterruptCoordinationEnable:1;\r
- UINT32 Reserved2:9;\r
- UINT32 Reserved3:32;\r
+ UINT32 ThermalInterruptCoordinationEnable : 1;\r
+ UINT32 Reserved2 : 9;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r
Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r
@endcode\r
@note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 0 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup0:8;\r
+ UINT32 MaxRatioLimitGroup0 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 1 threshold and greater than Group 0 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup1:8;\r
+ UINT32 MaxRatioLimitGroup1 : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 2 threshold and greater than Group 1 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup2:8;\r
+ UINT32 MaxRatioLimitGroup2 : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 3 threshold and greater than Group 2 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup3:8;\r
+ UINT32 MaxRatioLimitGroup3 : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 4 threshold and greater than Group 3 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup4:8;\r
+ UINT32 MaxRatioLimitGroup4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 5 threshold and greater than Group 4 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup5:8;\r
+ UINT32 MaxRatioLimitGroup5 : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 6 threshold and greater than Group 5 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup6:8;\r
+ UINT32 MaxRatioLimitGroup6 : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r
/// Maximum turbo ratio limit when number of active cores is less or equal\r
/// to Group 7 threshold and greater than Group 6 threshold.\r
///\r
- UINT32 MaxRatioLimitGroup7:8;\r
+ UINT32 MaxRatioLimitGroup7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r
0 threshold is ignored.\r
@endcode\r
@note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r
/// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 0 Max Turbo Ratio limit.\r
///\r
- UINT32 CoreCountThresholdGroup0:8;\r
+ UINT32 CoreCountThresholdGroup0 : 8;\r
///\r
/// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r
/// greater than Group 0 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup1:8;\r
+ UINT32 CoreCountThresholdGroup1 : 8;\r
///\r
/// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r
/// greater than Group 1 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup2:8;\r
+ UINT32 CoreCountThresholdGroup2 : 8;\r
///\r
/// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r
/// greater than Group 2 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup3:8;\r
+ UINT32 CoreCountThresholdGroup3 : 8;\r
///\r
/// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r
/// greater than Group 3 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup4:8;\r
+ UINT32 CoreCountThresholdGroup4 : 8;\r
///\r
/// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r
/// greater than Group 4 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup5:8;\r
+ UINT32 CoreCountThresholdGroup5 : 8;\r
///\r
/// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r
/// greater than Group 5 Core Count.\r
///\r
- UINT32 CoreCountThresholdGroup6:8;\r
+ UINT32 CoreCountThresholdGroup6 : 8;\r
///\r
/// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r
/// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r
/// greater than Group 6 Core Count and not less than the total number of\r
/// processor cores in the package. E.g. specify 255.\r
///\r
- UINT32 CoreCountThresholdGroup7:8;\r
+ UINT32 CoreCountThresholdGroup7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
"Filtering of Last Branch Records.".\r
@endcode\r
@note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
+#define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
+ UINT32 FAR_BRANCH : 1;\r
///\r
/// [Bit 9] EN_CALL_STACK.\r
///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN_CALL_STACK : 1;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r
points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Power Control Register. See http://biosbits.org.\r
@endcode\r
@note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
-#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
+#define MSR_GOLDMONT_POWER_CTL 0x000001FC\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
/// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
/// operating point when all execution cores enter MWAIT (C1).\r
///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 C1EEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_POWER_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
-\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r
\r
//\r
// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
-\r
+#define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r
\r
/**\r
Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r
@endcode\r
@note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r
**/\r
-#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
-\r
+#define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r
\r
//\r
// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
-\r
+#define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r
\r
/**\r
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
@endcode\r
@note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Set 1 to clear LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to clear CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to clear ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r
Monitoring Version 4.".\r
@endcode\r
@note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r
///\r
- UINT32 Ovf_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Ovf_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Set 1 to cause LBR_Frz = 1.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Set 1 to cause CTR_Frz = 1.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Set 1 to cause ASCI = 1.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Set 1 to cause Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
(PEBS).".\r
@endcode\r
@note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
+#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r
/// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC0. (R/W).\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
@endcode\r
@note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
-\r
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r
\r
/**\r
Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
@endcode\r
@note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r
/// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
/// further changes.\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
/// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
/// the package that attempts to execute SMM code not within the ranges\r
/// defined by the SMRR will assert an unrecoverable MCE.\r
///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMM_Code_Chk_En : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
processors in the package. Available only while in SMM and\r
@endcode\r
@note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
-\r
+#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r
\r
/**\r
Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
@endcode\r
@note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
**/\r
-#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
-\r
+#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r
\r
/**\r
Core. Trace Control Register (R/W).\r
@endcode\r
@note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r
**/\r
-#define MSR_IA32_RTIT_CTL 0x00000570\r
+#define MSR_IA32_RTIT_CTL 0x00000570\r
\r
/**\r
MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r
///\r
/// [Bit 0] TraceEn.\r
///\r
- UINT32 TraceEn:1;\r
+ UINT32 TraceEn : 1;\r
///\r
/// [Bit 1] CYCEn.\r
///\r
- UINT32 CYCEn:1;\r
+ UINT32 CYCEn : 1;\r
///\r
/// [Bit 2] OS.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 3] User.\r
///\r
- UINT32 User:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 User : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 7] CR3 filter.\r
///\r
- UINT32 CR3:1;\r
+ UINT32 CR3 : 1;\r
///\r
/// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r
///\r
- UINT32 ToPA:1;\r
+ UINT32 ToPA : 1;\r
///\r
/// [Bit 9] MTCEn.\r
///\r
- UINT32 MTCEn:1;\r
+ UINT32 MTCEn : 1;\r
///\r
/// [Bit 10] TSCEn.\r
///\r
- UINT32 TSCEn:1;\r
+ UINT32 TSCEn : 1;\r
///\r
/// [Bit 11] DisRETC.\r
///\r
- UINT32 DisRETC:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 DisRETC : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 13] BranchEn.\r
///\r
- UINT32 BranchEn:1;\r
+ UINT32 BranchEn : 1;\r
///\r
/// [Bits 17:14] MTCFreq.\r
///\r
- UINT32 MTCFreq:4;\r
- UINT32 Reserved3:1;\r
+ UINT32 MTCFreq : 4;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 22:19] CYCThresh.\r
///\r
- UINT32 CYCThresh:4;\r
- UINT32 Reserved4:1;\r
+ UINT32 CYCThresh : 4;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bits 27:24] PSBFreq.\r
///\r
- UINT32 PSBFreq:4;\r
- UINT32 Reserved5:4;\r
+ UINT32 PSBFreq : 4;\r
+ UINT32 Reserved5 : 4;\r
///\r
/// [Bits 35:32] ADDR0_CFG.\r
///\r
- UINT32 ADDR0_CFG:4;\r
+ UINT32 ADDR0_CFG : 4;\r
///\r
/// [Bits 39:36] ADDR1_CFG.\r
///\r
- UINT32 ADDR1_CFG:4;\r
- UINT32 Reserved6:24;\r
+ UINT32 ADDR1_CFG : 4;\r
+ UINT32 Reserved6 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
"RAPL Interfaces.".\r
@endcode\r
@note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r
/// 3:0. Default value is 1000b, indicating power unit is in 3.9\r
/// milliWatts increment.\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Energy Status Units. Energy related information (in\r
/// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r
/// integer represented by bits 12:8. Default value is 01110b, indicating\r
/// energy unit is in 61 microJoules.\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r
/// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r
/// 19:16. Default value is 1010b, indicating power unit is in 0.977\r
/// millisecond.\r
///\r
- UINT32 TimeUnit:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnit : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
+#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C3 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
+#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7S state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r
\r
-\r
/**\r
Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r
interrupt response time limit used by the processor to manage transition to\r
@endcode\r
@note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
+#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r
/// that should be used to decide if the package should be put into a\r
/// package C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
@endcode\r
@note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. PKG RAPL Parameters (R/W).\r
@endcode\r
@note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
+#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r
/// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain.".\r
///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 ThermalSpecPower : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r
/// Domain.".\r
///\r
- UINT32 MinimumPower:15;\r
- UINT32 Reserved2:1;\r
+ UINT32 MinimumPower : 15;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r
/// Domain.".\r
///\r
- UINT32 MaximumPower:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 MaximumPower : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r
/// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r
/// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r
/// MSR_RAPL_POWER_UNIT.\r
///\r
- UINT32 MaximumTimeWindow:7;\r
- UINT32 Reserved4:9;\r
+ UINT32 MaximumTimeWindow : 7;\r
+ UINT32 Reserved4 : 9;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,.\r
@endcode\r
@note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
**/\r
-#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
-\r
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. ConfigTDP Control (R/W).\r
@endcode\r
@note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
refers to processor core frequency).\r
@endcode\r
@note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOTStatus:1;\r
+ UINT32 PROCHOTStatus : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved1:5;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved1 : 5;\r
///\r
/// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
/// below the operating system request due to domain-level power limiting.\r
///\r
- UINT32 PowerLimitingStatus:1;\r
+ UINT32 PowerLimitingStatus : 1;\r
///\r
/// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
///\r
/// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r
/// is reduced below the maximum efficiency frequency.\r
///\r
- UINT32 MaximumEfficiencyFrequencyStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 MaximumEfficiencyFrequencyStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT:1;\r
+ UINT32 PROCHOT : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
+ UINT32 ThermalLog : 1;\r
///\r
/// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved3:5;\r
+ UINT32 PL2Log : 1;\r
+ UINT32 Reserved3 : 5;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
///\r
/// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r
/// the Maximum Efficiency Frequency Status bit has asserted since the log\r
/// bit was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 MaximumEfficiencyFrequencyLog:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 MaximumEfficiencyFrequencyLog : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
-#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r
/// @}\r
\r
/**\r
///\r
/// [Bit 31:0] From Linear Address (R/W).\r
///\r
- UINT32 FromLinearAddress:32;\r
+ UINT32 FromLinearAddress : 32;\r
///\r
/// [Bit 47:32] From Linear Address (R/W).\r
///\r
- UINT32 FromLinearAddressHi:16;\r
+ UINT32 FromLinearAddressHi : 16;\r
///\r
/// [Bits 62:48] Signed extension of bits 47:0.\r
///\r
- UINT32 SignedExtension:15;\r
+ UINT32 SignedExtension : 15;\r
///\r
/// [Bit 63] Mispred.\r
///\r
- UINT32 Mispred:1;\r
+ UINT32 Mispred : 1;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r
registers on the last branch record stack. The To_IP part of the stack\r
MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
-#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r
/// @}\r
\r
/**\r
///\r
/// [Bit 31:0] Target Linear Address (R/W).\r
///\r
- UINT32 TargetLinearAddress:32;\r
+ UINT32 TargetLinearAddress : 32;\r
///\r
/// [Bit 47:32] Target Linear Address (R/W).\r
///\r
- UINT32 TargetLinearAddressHi:16;\r
+ UINT32 TargetLinearAddressHi : 16;\r
///\r
/// [Bits 63:48] Elapsed cycles from last update to the LBR.\r
///\r
- UINT32 ElapsedCycles:16;\r
+ UINT32 ElapsedCycles : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r
\r
-\r
/**\r
Core. Resource Association Register (R/W).\r
\r
@endcode\r
@note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
+ UINT32 Reserved1 : 32;\r
///\r
/// [Bits 33:32] COS (R/W).\r
///\r
- UINT32 COS:2;\r
- UINT32 Reserved2:30;\r
+ UINT32 COS : 2;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=n.\r
MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r
@{\r
**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
///\r
- UINT32 CBM:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBM : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r
\r
-\r
/**\r
Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=3.\r
@endcode\r
@note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r
**/\r
-#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r
///\r
/// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved1:12;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved1 : 12;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r
\r
-\r
#endif\r
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1\r
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE\r
/// [Bit 0] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC0.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 1] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC1.\r
///\r
- UINT32 Fix_Me_2:1;\r
+ UINT32 Fix_Me_2 : 1;\r
///\r
/// [Bit 2] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC2.\r
///\r
- UINT32 Fix_Me_3:1;\r
+ UINT32 Fix_Me_3 : 1;\r
///\r
/// [Bit 3] Enable PEBS trigger and recording for the programmed event\r
/// (precise or otherwise) on IA32_PMC3.\r
///\r
- UINT32 Fix_Me_4:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 Fix_Me_4 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.\r
///\r
- UINT32 Fix_Me_5:1;\r
+ UINT32 Fix_Me_5 : 1;\r
///\r
/// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.\r
///\r
- UINT32 Fix_Me_6:1;\r
+ UINT32 Fix_Me_6 : 1;\r
///\r
/// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.\r
///\r
- UINT32 Fix_Me_7:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 Fix_Me_7 : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up\r
the first entry of the 32-entry LBR stack. The From_IP part of the stack\r
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);\r
@endcode\r
**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP 0x0000069F\r
\r
/**\r
Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up\r
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);\r
@endcode\r
**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF\r
-\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP 0x000006DF\r
\r
/**\r
Core. Last Branch Record N Additional Information (R/W) One of the three\r
AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);\r
@endcode\r
**/\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE\r
-#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0 0x00000DC0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1 0x00000DC1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2 0x00000DC2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3 0x00000DC3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4 0x00000DC4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5 0x00000DC5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6 0x00000DC6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7 0x00000DC7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8 0x00000DC8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9 0x00000DC9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10 0x00000DCA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11 0x00000DCB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12 0x00000DCC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13 0x00000DCD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14 0x00000DCE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15 0x00000DCF\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16 0x00000DD0\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17 0x00000DD1\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18 0x00000DD2\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19 0x00000DD3\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20 0x00000DD4\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21 0x00000DD5\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22 0x00000DD6\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23 0x00000DD7\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24 0x00000DD8\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25 0x00000DD9\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26 0x00000DDA\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27 0x00000DDB\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28 0x00000DDC\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29 0x00000DDD\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30 0x00000DDE\r
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31 0x00000DDF\r
\r
#endif\r
@endcode\r
@note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.\r
**/\r
-#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT\r
/// currently enabled (by either factory configuration or BIOS\r
/// configuration) in the physical package.\r
///\r
- UINT32 Core_Count:16;\r
+ UINT32 Core_Count : 16;\r
///\r
/// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that\r
/// are currently enabled (by either factory configuration or BIOS\r
/// configuration) in the physical package.\r
///\r
- UINT32 Thread_Count:16;\r
- UINT32 Reserved:32;\r
+ UINT32 Thread_Count : 16;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;\r
\r
-\r
/**\r
Thread. A Hardware Assigned ID for the Logical Processor (RO).\r
\r
@endcode\r
@note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.\r
**/\r
-#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO\r
/// ID is not related to Initial APIC ID or x2APIC ID, it is unique within\r
/// a physical package.\r
///\r
- UINT32 Logical_Processor_ID:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 Logical_Processor_ID : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL\r
/// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
/// supported by the processor are available.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
+ UINT32 C1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotion:1;\r
+ UINT32 CStateDemotion : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUndemotion : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Global Machine Check Capability (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
-#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
+#define MSR_HASWELL_E_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P.\r
///\r
- UINT32 MCG_SER_P:1;\r
+ UINT32 MCG_SER_P : 1;\r
///\r
/// [Bit 25] MCG_EM_P.\r
///\r
- UINT32 MCG_EM_P:1;\r
+ UINT32 MCG_EM_P : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 MCG_ELOG_P : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
@endcode\r
@note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
+#define MSR_HASWELL_E_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package. MC Bank Error Configuration (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
+#define MSR_HASWELL_E_ERROR_CONTROL 0x0000017F\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
/// to log additional info in bits 36:32.\r
///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 MemErrorLogEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
/// limit of 7 core active.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
/// limit of 8 core active.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
/// limit of 9 core active.\r
///\r
- UINT32 Maximum9C:8;\r
+ UINT32 Maximum9C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
/// limit of 10 core active.\r
///\r
- UINT32 Maximum10C:8;\r
+ UINT32 Maximum10C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
/// limit of 11 core active.\r
///\r
- UINT32 Maximum11C:8;\r
+ UINT32 Maximum11C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
/// limit of 12 core active.\r
///\r
- UINT32 Maximum12C:8;\r
+ UINT32 Maximum12C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
/// limit of 13 core active.\r
///\r
- UINT32 Maximum13C:8;\r
+ UINT32 Maximum13C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
/// limit of 14 core active.\r
///\r
- UINT32 Maximum14C:8;\r
+ UINT32 Maximum14C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
/// limit of 15 core active.\r
///\r
- UINT32 Maximum15C:8;\r
+ UINT32 Maximum15C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio\r
/// limit of 16 core active.\r
///\r
- UINT32 Maximum16C:8;\r
+ UINT32 Maximum16C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2 0x000001AF\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio\r
/// limit of 17 core active.\r
///\r
- UINT32 Maximum17C:8;\r
+ UINT32 Maximum17C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio\r
/// limit of 18 core active.\r
///\r
- UINT32 Maximum18C:8;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:31;\r
+ UINT32 Maximum18C : 8;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 31;\r
///\r
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
/// the processor uses override configuration specified in\r
/// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set\r
/// configuration (Default).\r
///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_HASWELL_E_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
@endcode\r
@note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.\r
@endcode\r
@note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS\r
/// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
/// to enable DRAM RAPL mode 0 (Direct VR).\r
///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 Energy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
RAPL Domain.".\r
@endcode\r
@note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_HASWELL_E_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_HASWELL_E_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Configuration of PCIE PLL Relative to BCLK(R/W).\r
@endcode\r
@note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO\r
/// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz\r
/// operation.\r
///\r
- UINT32 PCIERatio:2;\r
+ UINT32 PCIERatio : 2;\r
///\r
/// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of\r
/// PCIE Ratio.\r
///\r
- UINT32 LPLLSelect:1;\r
+ UINT32 LPLLSelect : 1;\r
///\r
/// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out\r
/// before re-locking Gen2/Gen3 PLLs.\r
///\r
- UINT32 LONGRESET:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 LONGRESET : 1;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
fields represent the widest possible range of uncore frequencies. Writing to\r
AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
/// reduced below the operating system request due to PBM limit.\r
///\r
- UINT32 PowerBudgetManagementStatus:1;\r
+ UINT32 PowerBudgetManagementStatus : 1;\r
///\r
/// [Bit 3] Platform Configuration Services Status (R0) When set,\r
/// frequency is reduced below the operating system request due to PCS\r
/// limit.\r
///\r
- UINT32 PlatformConfigurationServicesStatus:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 PlatformConfigurationServicesStatus : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Multi-Core Turbo limits.\r
///\r
- UINT32 MultiCoreTurboStatus:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 MultiCoreTurboStatus : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
/// below max non-turbo P1.\r
///\r
- UINT32 FrequencyP1Status:1;\r
+ UINT32 FrequencyP1Status : 1;\r
///\r
/// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
/// set, frequency is reduced below max n-core turbo frequency.\r
///\r
- UINT32 TurboFrequencyLimitingStatus:1;\r
+ UINT32 TurboFrequencyLimitingStatus : 1;\r
///\r
/// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
/// reduced below the operating system request.\r
///\r
- UINT32 FrequencyLimitingStatus:1;\r
+ UINT32 FrequencyLimitingStatus : 1;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
+ UINT32 ThermalLog : 1;\r
///\r
/// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PowerBudgetManagementLog:1;\r
+ UINT32 PowerBudgetManagementLog : 1;\r
///\r
/// [Bit 19] Platform Configuration Services Log When set, indicates that\r
/// the PCS Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PlatformConfigurationServicesLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 PlatformConfigurationServicesLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the AUBFC Status bit has asserted since the log bit was\r
/// last cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
/// Turbo Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MultiCoreTurboLog:1;\r
- UINT32 Reserved8:2;\r
+ UINT32 MultiCoreTurboLog : 1;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
/// Frequency P1 Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyP1Log:1;\r
+ UINT32 CoreFrequencyP1Log : 1;\r
///\r
/// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
/// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 TurboFrequencyLimitingLog:1;\r
+ UINT32 TurboFrequencyLimitingLog : 1;\r
///\r
/// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
/// Frequency Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyLimitingLog:1;\r
- UINT32 Reserved9:32;\r
+ UINT32 CoreFrequencyLimitingLog : 1;\r
+ UINT32 Reserved9 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,\r
ECX=0):EBX.RDT-M[bit 12] = 1.\r
@endcode\r
@note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
-#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_HASWELL_E_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL\r
/// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3\r
/// occupancy monitoring all other encoding reserved..\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bits 41:32] RMID (RW).\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved2 : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
THREAD. Resource Association Register (R/W)..\r
\r
@endcode\r
@note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_HASWELL_E_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC\r
///\r
/// [Bits 9:0] RMID.\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Package. Uncore perfmon per-socket global control.\r
\r
@endcode\r
@note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL 0x00000700\r
\r
/**\r
Package. Uncore perfmon per-socket global status.\r
@endcode\r
@note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS 0x00000701\r
\r
/**\r
Package. Uncore perfmon per-socket global configuration.\r
@endcode\r
@note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
**/\r
-#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
-\r
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG 0x00000702\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter control.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
-\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL 0x00000703\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
-\r
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR 0x00000704\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 0.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
-\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0 0x00000705\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 1.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
-\r
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1 0x00000706\r
\r
/**\r
Package. Uncore U-box perfmon U-box wide status.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
-\r
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS 0x00000708\r
\r
/**\r
Package. Uncore U-box perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
-\r
+#define MSR_HASWELL_E_U_PMON_CTR0 0x00000709\r
\r
/**\r
Package. Uncore U-box perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
-\r
+#define MSR_HASWELL_E_U_PMON_CTR1 0x0000070A\r
\r
/**\r
Package. Uncore PCU perfmon for PCU-box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL 0x00000710\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 0.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0 0x00000711\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 1.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1 0x00000712\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 2.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2 0x00000713\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 3.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3 0x00000714\r
\r
/**\r
Package. Uncore PCU perfmon box-wide filter.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER 0x00000715\r
\r
/**\r
Package. Uncore PCU perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS 0x00000716\r
\r
/**\r
Package. Uncore PCU perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR0 0x00000717\r
\r
/**\r
Package. Uncore PCU perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR1 0x00000718\r
\r
/**\r
Package. Uncore PCU perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR2 0x00000719\r
\r
/**\r
Package. Uncore PCU perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
-\r
+#define MSR_HASWELL_E_PCU_PMON_CTR3 0x0000071A\r
\r
/**\r
Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
-\r
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL 0x00000720\r
\r
/**\r
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0 0x00000721\r
\r
/**\r
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1 0x00000722\r
\r
/**\r
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2 0x00000723\r
\r
/**\r
Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
-\r
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3 0x00000724\r
\r
/**\r
Package. Uncore SBo 0 perfmon box-wide filter.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
-\r
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER 0x00000725\r
\r
/**\r
Package. Uncore SBo 0 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR0 0x00000726\r
\r
/**\r
Package. Uncore SBo 0 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR1 0x00000727\r
\r
/**\r
Package. Uncore SBo 0 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR2 0x00000728\r
\r
/**\r
Package. Uncore SBo 0 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
-\r
+#define MSR_HASWELL_E_S0_PMON_CTR3 0x00000729\r
\r
/**\r
Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
-\r
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL 0x0000072A\r
\r
/**\r
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0 0x0000072B\r
\r
/**\r
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1 0x0000072C\r
\r
/**\r
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2 0x0000072D\r
\r
/**\r
Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
-\r
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3 0x0000072E\r
\r
/**\r
Package. Uncore SBo 1 perfmon box-wide filter.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
-\r
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER 0x0000072F\r
\r
/**\r
Package. Uncore SBo 1 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR0 0x00000730\r
\r
/**\r
Package. Uncore SBo 1 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR1 0x00000731\r
\r
/**\r
Package. Uncore SBo 1 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR2 0x00000732\r
\r
/**\r
Package. Uncore SBo 1 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
-\r
+#define MSR_HASWELL_E_S1_PMON_CTR3 0x00000733\r
\r
/**\r
Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
-\r
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL 0x00000734\r
\r
/**\r
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0 0x00000735\r
\r
/**\r
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1 0x00000736\r
\r
/**\r
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2 0x00000737\r
\r
/**\r
Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
-\r
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3 0x00000738\r
\r
/**\r
Package. Uncore SBo 2 perfmon box-wide filter.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
-\r
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER 0x00000739\r
\r
/**\r
Package. Uncore SBo 2 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR0 0x0000073A\r
\r
/**\r
Package. Uncore SBo 2 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR1 0x0000073B\r
\r
/**\r
Package. Uncore SBo 2 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR2 0x0000073C\r
\r
/**\r
Package. Uncore SBo 2 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
-\r
+#define MSR_HASWELL_E_S2_PMON_CTR3 0x0000073D\r
\r
/**\r
Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
-\r
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL 0x0000073E\r
\r
/**\r
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0 0x0000073F\r
\r
/**\r
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1 0x00000740\r
\r
/**\r
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2 0x00000741\r
\r
/**\r
Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
-\r
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3 0x00000742\r
\r
/**\r
Package. Uncore SBo 3 perfmon box-wide filter.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
-\r
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER 0x00000743\r
\r
/**\r
Package. Uncore SBo 3 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR0 0x00000744\r
\r
/**\r
Package. Uncore SBo 3 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR1 0x00000745\r
\r
/**\r
Package. Uncore SBo 3 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR2 0x00000746\r
\r
/**\r
Package. Uncore SBo 3 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
-\r
+#define MSR_HASWELL_E_S3_PMON_CTR3 0x00000747\r
\r
/**\r
Package. Uncore C-box 0 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL 0x00000E00\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0 0x00000E01\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1 0x00000E02\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2 0x00000E03\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
-\r
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3 0x00000E04\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0 0x00000E05\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter 1.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1 0x00000E06\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
-\r
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS 0x00000E07\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR0 0x00000E08\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR1 0x00000E09\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR2 0x00000E0A\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
-\r
+#define MSR_HASWELL_E_C0_PMON_CTR3 0x00000E0B\r
\r
/**\r
Package. Uncore C-box 1 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL 0x00000E10\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0 0x00000E11\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1 0x00000E12\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2 0x00000E13\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
-\r
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3 0x00000E14\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0 0x00000E15\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1 0x00000E16\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
-\r
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS 0x00000E17\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR0 0x00000E18\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR1 0x00000E19\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR2 0x00000E1A\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
-\r
+#define MSR_HASWELL_E_C1_PMON_CTR3 0x00000E1B\r
\r
/**\r
Package. Uncore C-box 2 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL 0x00000E20\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0 0x00000E21\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1 0x00000E22\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2 0x00000E23\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
-\r
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3 0x00000E24\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0 0x00000E25\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1 0x00000E26\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
-\r
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS 0x00000E27\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR0 0x00000E28\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR1 0x00000E29\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR2 0x00000E2A\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
-\r
+#define MSR_HASWELL_E_C2_PMON_CTR3 0x00000E2B\r
\r
/**\r
Package. Uncore C-box 3 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL 0x00000E30\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0 0x00000E31\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1 0x00000E32\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2 0x00000E33\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
-\r
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3 0x00000E34\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0 0x00000E35\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1 0x00000E36\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
-\r
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS 0x00000E37\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR0 0x00000E38\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR1 0x00000E39\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR2 0x00000E3A\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
-\r
+#define MSR_HASWELL_E_C3_PMON_CTR3 0x00000E3B\r
\r
/**\r
Package. Uncore C-box 4 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL 0x00000E40\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0 0x00000E41\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1 0x00000E42\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2 0x00000E43\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
-\r
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3 0x00000E44\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0 0x00000E45\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1 0x00000E46\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
-\r
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS 0x00000E47\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR0 0x00000E48\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR1 0x00000E49\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR2 0x00000E4A\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
-\r
+#define MSR_HASWELL_E_C4_PMON_CTR3 0x00000E4B\r
\r
/**\r
Package. Uncore C-box 5 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL 0x00000E50\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0 0x00000E51\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1 0x00000E52\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2 0x00000E53\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
-\r
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3 0x00000E54\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0 0x00000E55\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1 0x00000E56\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
-\r
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS 0x00000E57\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR0 0x00000E58\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR1 0x00000E59\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR2 0x00000E5A\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
-\r
+#define MSR_HASWELL_E_C5_PMON_CTR3 0x00000E5B\r
\r
/**\r
Package. Uncore C-box 6 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL 0x00000E60\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0 0x00000E61\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1 0x00000E62\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2 0x00000E63\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
-\r
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3 0x00000E64\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0 0x00000E65\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1 0x00000E66\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
-\r
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS 0x00000E67\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR0 0x00000E68\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR1 0x00000E69\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR2 0x00000E6A\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
-\r
+#define MSR_HASWELL_E_C6_PMON_CTR3 0x00000E6B\r
\r
/**\r
Package. Uncore C-box 7 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL 0x00000E70\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0 0x00000E71\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1 0x00000E72\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2 0x00000E73\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
-\r
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3 0x00000E74\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0 0x00000E75\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1 0x00000E76\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
-\r
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS 0x00000E77\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR0 0x00000E78\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR1 0x00000E79\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR2 0x00000E7A\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
-\r
+#define MSR_HASWELL_E_C7_PMON_CTR3 0x00000E7B\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL 0x00000E80\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0 0x00000E81\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1 0x00000E82\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2 0x00000E83\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
-\r
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3 0x00000E84\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0 0x00000E85\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1 0x00000E86\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
-\r
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS 0x00000E87\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR0 0x00000E88\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR1 0x00000E89\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR2 0x00000E8A\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
-\r
+#define MSR_HASWELL_E_C8_PMON_CTR3 0x00000E8B\r
\r
/**\r
Package. Uncore C-box 9 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL 0x00000E90\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0 0x00000E91\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1 0x00000E92\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2 0x00000E93\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
-\r
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3 0x00000E94\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0 0x00000E95\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1 0x00000E96\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
-\r
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS 0x00000E97\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR0 0x00000E98\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR1 0x00000E99\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR2 0x00000E9A\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
-\r
+#define MSR_HASWELL_E_C9_PMON_CTR3 0x00000E9B\r
\r
/**\r
Package. Uncore C-box 10 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL 0x00000EA0\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0 0x00000EA1\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1 0x00000EA2\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2 0x00000EA3\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
-\r
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3 0x00000EA4\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0 0x00000EA5\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1 0x00000EA6\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
-\r
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS 0x00000EA7\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR0 0x00000EA8\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR1 0x00000EA9\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR2 0x00000EAA\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
-\r
+#define MSR_HASWELL_E_C10_PMON_CTR3 0x00000EAB\r
\r
/**\r
Package. Uncore C-box 11 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL 0x00000EB0\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0 0x00000EB1\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1 0x00000EB2\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2 0x00000EB3\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
-\r
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3 0x00000EB4\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0 0x00000EB5\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1 0x00000EB6\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
-\r
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS 0x00000EB7\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR0 0x00000EB8\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR1 0x00000EB9\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR2 0x00000EBA\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
-\r
+#define MSR_HASWELL_E_C11_PMON_CTR3 0x00000EBB\r
\r
/**\r
Package. Uncore C-box 12 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL 0x00000EC0\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0 0x00000EC1\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1 0x00000EC2\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2 0x00000EC3\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
-\r
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3 0x00000EC4\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0 0x00000EC5\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1 0x00000EC6\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
-\r
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS 0x00000EC7\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR0 0x00000EC8\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR1 0x00000EC9\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR2 0x00000ECA\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
-\r
+#define MSR_HASWELL_E_C12_PMON_CTR3 0x00000ECB\r
\r
/**\r
Package. Uncore C-box 13 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL 0x00000ED0\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0 0x00000ED1\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1 0x00000ED2\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2 0x00000ED3\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
-\r
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3 0x00000ED4\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0 0x00000ED5\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1 0x00000ED6\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
-\r
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS 0x00000ED7\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR0 0x00000ED8\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR1 0x00000ED9\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR2 0x00000EDA\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
-\r
+#define MSR_HASWELL_E_C13_PMON_CTR3 0x00000EDB\r
\r
/**\r
Package. Uncore C-box 14 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL 0x00000EE0\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0 0x00000EE1\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1 0x00000EE2\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2 0x00000EE3\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
-\r
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3 0x00000EE4\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER 0x00000EE5\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1 0x00000EE6\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
-\r
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS 0x00000EE7\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR0 0x00000EE8\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR1 0x00000EE9\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR2 0x00000EEA\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
-\r
+#define MSR_HASWELL_E_C14_PMON_CTR3 0x00000EEB\r
\r
/**\r
Package. Uncore C-box 15 perfmon local box wide control.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL 0x00000EF0\r
\r
/**\r
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0 0x00000EF1\r
\r
/**\r
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1 0x00000EF2\r
\r
/**\r
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2 0x00000EF3\r
\r
/**\r
Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
-\r
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3 0x00000EF4\r
\r
/**\r
Package. Uncore C-box 15 perfmon box wide filter0.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0 0x00000EF5\r
\r
/**\r
Package. Uncore C-box 15 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1 0x00000EF6\r
\r
/**\r
Package. Uncore C-box 15 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
-\r
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS 0x00000EF7\r
\r
/**\r
Package. Uncore C-box 15 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR0 0x00000EF8\r
\r
/**\r
Package. Uncore C-box 15 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR1 0x00000EF9\r
\r
/**\r
Package. Uncore C-box 15 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR2 0x00000EFA\r
\r
/**\r
Package. Uncore C-box 15 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
-\r
+#define MSR_HASWELL_E_C15_PMON_CTR3 0x00000EFB\r
\r
/**\r
Package. Uncore C-box 16 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL 0x00000F00\r
\r
/**\r
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0 0x00000F01\r
\r
/**\r
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1 0x00000F02\r
\r
/**\r
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2 0x00000F03\r
\r
/**\r
Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
-\r
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3 0x00000F04\r
\r
/**\r
Package. Uncore C-box 16 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0 0x00000F05\r
\r
/**\r
Package. Uncore C-box 16 perfmon box wide filter 1.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1 0x00000F06\r
\r
/**\r
Package. Uncore C-box 16 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
-\r
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS 0x00000F07\r
\r
/**\r
Package. Uncore C-box 16 perfmon counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR0 0x00000F08\r
\r
/**\r
Package. Uncore C-box 16 perfmon counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR1 0x00000F09\r
\r
/**\r
Package. Uncore C-box 16 perfmon counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR2 0x00000F0A\r
\r
/**\r
Package. Uncore C-box 16 perfmon counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
-\r
+#define MSR_HASWELL_E_C16_PMON_CTR3 0x00000E0B\r
\r
/**\r
Package. Uncore C-box 17 perfmon for box-wide control.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL 0x00000F10\r
\r
/**\r
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0 0x00000F11\r
\r
/**\r
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1 0x00000F12\r
\r
/**\r
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2 0x00000F13\r
\r
/**\r
Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
-\r
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3 0x00000F14\r
\r
/**\r
Package. Uncore C-box 17 perfmon box wide filter 0.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0 0x00000F15\r
\r
/**\r
Package. Uncore C-box 17 perfmon box wide filter1.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1 0x00000F16\r
\r
/**\r
Package. Uncore C-box 17 perfmon box wide status.\r
@endcode\r
@note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
-\r
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS 0x00000F17\r
\r
/**\r
Package. Uncore C-box 17 perfmon counter n.\r
MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.\r
@{\r
**/\r
-#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
-#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
-#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
-#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
+#define MSR_HASWELL_E_C17_PMON_CTR0 0x00000F18\r
+#define MSR_HASWELL_E_C17_PMON_CTR1 0x00000F19\r
+#define MSR_HASWELL_E_C17_PMON_CTR2 0x00000F1A\r
+#define MSR_HASWELL_E_C17_PMON_CTR3 0x00000F1B\r
/// @}\r
\r
#endif\r
@endcode\r
@note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
+#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
/// indicates that LPM is supported, and when set to 0, indicates LPM is\r
/// not supported.\r
///\r
- UINT32 LowPowerModeSupport:1;\r
+ UINT32 LowPowerModeSupport : 1;\r
///\r
/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
/// TDP level available. 01: One additional TDP level available. 02: Two\r
/// additional TDP level available. 11: Reserved.\r
///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
+ UINT32 ConfigTDPLevels : 2;\r
+ UINT32 Reserved4 : 5;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
///\r
/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
/// minimum supported operating ratio in units of 100 MHz.\r
///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
+ UINT32 MinimumOperatingRatio : 8;\r
+ UINT32 Reserved5 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Thread. Performance Event Select for Counter n (R/W) Supports all fields\r
described inTable 2-2 and the fields below.\r
MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
-#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
-#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
+#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
+#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
+#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
/// @}\r
\r
/**\r
///\r
/// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
/// detect on the selected event logic.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS: Counts while in privilege level is ring 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] Edge: Enables edge detection if set.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC: enables pin control.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT: enables interrupt on counter overflow.\r
///\r
- UINT32 INT:1;\r
+ UINT32 INT : 1;\r
///\r
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR.\r
///\r
- UINT32 ANY:1;\r
+ UINT32 ANY : 1;\r
///\r
/// [Bit 22] EN: enables the corresponding performance counter to commence\r
/// counting when this bit is set.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV: invert the CMASK.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
/// performance counter increments each cycle if the event count is\r
/// greater than or equal to the CMASK.\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved : 32;\r
///\r
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
/// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
///\r
- UINT32 IN_TX:1;\r
- UINT32 Reserved2:31;\r
+ UINT32 IN_TX : 1;\r
+ UINT32 Reserved2 : 31;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r
\r
-\r
/**\r
Thread. Performance Event Select for Counter 2 (R/W) Supports all fields\r
described inTable 2-2 and the fields below.\r
@endcode\r
@note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
+#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r
///\r
/// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
/// detect on the selected event logic.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS: Counts while in privilege level is ring 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] Edge: Enables edge detection if set.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC: enables pin control.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT: enables interrupt on counter overflow.\r
///\r
- UINT32 INT:1;\r
+ UINT32 INT : 1;\r
///\r
/// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
/// event conditions occurring across all logical processors sharing a\r
/// associated event conditions occurring in the logical processor which\r
/// programmed the MSR.\r
///\r
- UINT32 ANY:1;\r
+ UINT32 ANY : 1;\r
///\r
/// [Bit 22] EN: enables the corresponding performance counter to commence\r
/// counting when this bit is set.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV: invert the CMASK.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
/// performance counter increments each cycle if the event count is\r
/// greater than or equal to the CMASK.\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved : 32;\r
///\r
/// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,\r
/// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
///\r
- UINT32 IN_TX:1;\r
+ UINT32 IN_TX : 1;\r
///\r
/// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and\r
/// in sampling, spurious PMI may occur and transactions may continuously\r
/// IN_TXCP and also always reset the counter even when no overflow\r
/// condition was reported.\r
///\r
- UINT32 IN_TXCP:1;\r
- UINT32 Reserved2:30;\r
+ UINT32 IN_TXCP : 1;\r
+ UINT32 Reserved2 : 30;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
+#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
+ UINT32 FAR_BRANCH : 1;\r
///\r
/// [Bit 9] EN_CALL_STACK.\r
///\r
- UINT32 EN_CALL_STACK:1;\r
- UINT32 Reserved1:22;\r
- UINT32 Reserved2:32;\r
+ UINT32 EN_CALL_STACK : 1;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r
**/\r
-#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
+#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKGC_IRTL1_REGISTER;\r
\r
-\r
/**\r
Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r
the interrupt response time limit used by the processor to manage transition\r
@endcode\r
@note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r
**/\r
-#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
+#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r
/// that should be used to decide if the package should be put into a\r
/// package C6 or C7 state.\r
///\r
- UINT32 InterruptResponseTimeLimit:10;\r
+ UINT32 InterruptResponseTimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r
/// of the interrupt response time limit. See Table 2-19 for supported\r
/// time unit encodings.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKGC_IRTL2_REGISTER;\r
\r
-\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
\r
@endcode\r
@note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. Base TDP Ratio (R/O).\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
+#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r
/// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
/// specific processor (in units of 100 MHz).\r
///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Base : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r
///\r
/// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL1 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL1_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
+ UINT32 PKG_MAX_PWR_LVL1 : 15;\r
///\r
/// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MIN_PWR_LVL1:16;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MIN_PWR_LVL1 : 16;\r
+ UINT32 Reserved3 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
+#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r
///\r
/// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL2 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL2_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
+ UINT32 PKG_MAX_PWR_LVL2 : 15;\r
///\r
/// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MIN_PWR_LVL2:16;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MIN_PWR_LVL2 : 16;\r
+ UINT32 Reserved3 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
+#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r
///\r
/// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
+ UINT32 TDP_LEVEL : 2;\r
+ UINT32 Reserved1 : 29;\r
///\r
/// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
/// this register is locked until a reset.\r
///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r
/// 0100b: C7 0101b: C7s Package C states C7 are not available to\r
/// processor with signature 06_3CH.\r
///\r
- UINT32 Limit:4;\r
- UINT32 Reserved1:6;\r
+ UINT32 Limit : 4;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
@endcode\r
@note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
+#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and the\r
/// MSR_SMM_FEATURE_CONTROL is supported.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
/// supported.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Maximum4C : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU global control.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Core 0 select.\r
///\r
- UINT32 PMI_Sel_Core0:1;\r
+ UINT32 PMI_Sel_Core0 : 1;\r
///\r
/// [Bit 1] Core 1 select.\r
///\r
- UINT32 PMI_Sel_Core1:1;\r
+ UINT32 PMI_Sel_Core1 : 1;\r
///\r
/// [Bit 2] Core 2 select.\r
///\r
- UINT32 PMI_Sel_Core2:1;\r
+ UINT32 PMI_Sel_Core2 : 1;\r
///\r
/// [Bit 3] Core 3 select.\r
///\r
- UINT32 PMI_Sel_Core3:1;\r
- UINT32 Reserved1:15;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Core3 : 1;\r
+ UINT32 Reserved1 : 15;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
+#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 47:32] Current count.\r
///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
+ UINT32 CurrentCountHi : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r
///\r
/// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
@endcode\r
@note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
+#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r
/// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
/// further changes.\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
/// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
/// the package that attempts to execute SMM code not within the ranges\r
/// defined by the SMRR will assert an unrecoverable MCE.\r
///\r
- UINT32 SMM_Code_Chk_En:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 SMM_Code_Chk_En : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
processors in the package. Available only while in SMM and\r
@endcode\r
@note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
-\r
+#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
\r
/**\r
Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
@endcode\r
@note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r
**/\r
-#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
-\r
+#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
@endcode\r
@note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
-\r
+#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
**/\r
-#define MSR_HASWELL_PP1_POLICY 0x00000642\r
-\r
+#define MSR_HASWELL_PP1_POLICY 0x00000642\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Processor Graphics driver\r
/// override.\r
///\r
- UINT32 GraphicsDriverStatus:1;\r
+ UINT32 GraphicsDriverStatus : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
/// below the operating system request due to domain-level power limiting.\r
///\r
- UINT32 PLStatus:1;\r
+ UINT32 PLStatus : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 PLLog:1;\r
+ UINT32 PLLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
(frequency refers to processor graphics frequency).\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Processor Graphics driver\r
/// override.\r
///\r
- UINT32 GraphicsDriverStatus:1;\r
+ UINT32 GraphicsDriverStatus : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
///\r
/// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r
/// reduced below the operating system request due to domain-level power\r
/// limiting.\r
///\r
- UINT32 GraphicsPowerLimitingStatus:1;\r
+ UINT32 GraphicsPowerLimitingStatus : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1STatus:1;\r
+ UINT32 PL1STatus : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
(frequency refers to ring interconnect in the uncore).\r
@endcode\r
@note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
+#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL1.\r
///\r
- UINT32 PL1STatus:1;\r
+ UINT32 PL1STatus : 1;\r
///\r
/// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
/// frequency is reduced below the operating system request due to\r
/// package-level power limiting PL2.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved4:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved4 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved5:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved5 : 2;\r
///\r
/// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
/// Driver Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 GraphicsDriverLog:1;\r
+ UINT32 GraphicsDriverLog : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the Autonomous Utilization-Based Frequency Control\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
///\r
/// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
/// Power Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CorePowerLimitingLog:1;\r
+ UINT32 CorePowerLimitingLog : 1;\r
///\r
/// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
/// that the Package Level PL1 Power Limiting Status bit has asserted\r
/// since the log bit was last cleared. This log bit will remain set until\r
/// cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
/// the Package Level PL2 Power Limiting Status bit has asserted since the\r
/// log bit was last cleared. This log bit will remain set until cleared\r
/// by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved8:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved7 : 2;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box 0, counter 0 event select MSR.\r
\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
\r
/**\r
Package. Uncore C-Box 0, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
\r
/**\r
Package. Uncore C-Box 1, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
\r
/**\r
Package. Uncore C-Box 1, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
\r
/**\r
Package. Uncore C-Box 2, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
\r
/**\r
Package. Uncore C-Box 2, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
\r
/**\r
Package. Uncore C-Box 3, counter 0 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
\r
/**\r
Package. Uncore C-Box 3, counter 1 event select MSR.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 0.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 1.\r
@endcode\r
@note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
-#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
+#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r
/// that this package is in processor-specific C8 states. Count at the\r
/// same frequency as the TSC.\r
///\r
- UINT32 C8ResidencyCounter:32;\r
+ UINT32 C8ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C8 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C8ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C8ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
@endcode\r
@note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
+#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r
/// that this package is in processor-specific C9 states. Count at the\r
/// same frequency as the TSC.\r
///\r
- UINT32 C9ResidencyCounter:32;\r
+ UINT32 C9ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C9 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C9ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C9ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
@endcode\r
@note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r
**/\r
-#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
+#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
\r
/**\r
MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r
/// reset that this package is in processor-specific C10 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C10ResidencyCounter:32;\r
+ UINT32 C10ResidencyCounter : 32;\r
///\r
/// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
/// reset that this package is in processor-specific C10 states. Count at\r
/// the same frequency as the TSC.\r
///\r
- UINT32 C10ResidencyCounterHi:28;\r
- UINT32 Reserved:4;\r
+ UINT32 C10ResidencyCounterHi : 28;\r
+ UINT32 Reserved : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r
\r
#endif\r
@endcode\r
@note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
/// indicates that LPM is supported, and when set to 0, indicates LPM is\r
/// not supported.\r
///\r
- UINT32 LowPowerModeSupport:1;\r
+ UINT32 LowPowerModeSupport : 1;\r
///\r
/// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
/// TDP level available. 01: One additional TDP level available. 02: Two\r
/// additional TDP level available. 11: Reserved.\r
///\r
- UINT32 ConfigTDPLevels:2;\r
- UINT32 Reserved4:5;\r
+ UINT32 ConfigTDPLevels : 2;\r
+ UINT32 Reserved4 : 5;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
///\r
/// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
/// minimum supported operating ratio in units of 100 MHz.\r
///\r
- UINT32 MinimumOperatingRatio:8;\r
- UINT32 Reserved5:8;\r
+ UINT32 MinimumOperatingRatio : 8;\r
+ UINT32 Reserved5 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r
/// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
/// This field cannot be used to limit package C-state to C3.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C6/C7 requests to C3 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
/// demoted C3.\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
/// demoted C1.\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Base TDP Ratio (R/O).\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r
/// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
/// specific processor (in units of 100 MHz).\r
///\r
- UINT32 Config_TDP_Base:8;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Base : 8;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r
///\r
/// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
///\r
- UINT32 PKG_TDP_LVL1:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL1 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL1_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL1_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MAX_PWR_LVL1:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MAX_PWR_LVL1 : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
/// Level 1.\r
///\r
- UINT32 PKG_MIN_PWR_LVL1:15;\r
- UINT32 Reserved4:1;\r
+ UINT32 PKG_MIN_PWR_LVL1 : 15;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r
///\r
/// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
///\r
- UINT32 PKG_TDP_LVL2:15;\r
- UINT32 Reserved1:1;\r
+ UINT32 PKG_TDP_LVL2 : 15;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
/// for this specific processor.\r
///\r
- UINT32 Config_TDP_LVL2_Ratio:8;\r
- UINT32 Reserved2:8;\r
+ UINT32 Config_TDP_LVL2_Ratio : 8;\r
+ UINT32 Reserved2 : 8;\r
///\r
/// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MAX_PWR_LVL2:15;\r
- UINT32 Reserved3:1;\r
+ UINT32 PKG_MAX_PWR_LVL2 : 15;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
/// Level 2.\r
///\r
- UINT32 PKG_MIN_PWR_LVL2:15;\r
- UINT32 Reserved4:1;\r
+ UINT32 PKG_MIN_PWR_LVL2 : 15;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r
///\r
/// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
///\r
- UINT32 TDP_LEVEL:2;\r
- UINT32 Reserved1:29;\r
+ UINT32 TDP_LEVEL : 2;\r
+ UINT32 Reserved1 : 29;\r
///\r
/// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
/// this register is locked until a reset.\r
///\r
- UINT32 Config_TDP_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 Config_TDP_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package. ConfigTDP Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r
/// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
/// field.\r
///\r
- UINT32 MAX_NON_TURBO_RATIO:8;\r
- UINT32 Reserved1:23;\r
+ UINT32 MAX_NON_TURBO_RATIO : 8;\r
+ UINT32 Reserved1 : 23;\r
///\r
/// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
/// content of this register is locked until a reset.\r
///\r
- UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 TURBO_ACTIVATION_RATIO_Lock : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number Enable Control (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
+#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r
/// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
/// prevent unauthorized modification to MSR_PPIN_CTL.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
/// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r
/// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r
/// is 0.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) A unique value within a given CPUID\r
@endcode\r
@note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
-\r
+#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
\r
/**\r
Package. See http://biosbits.org.\r
@endcode\r
@note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r
/// Protected Processor Inventory Number (PPIN) capability can be enabled\r
/// set to 0, PPIN capability is not supported. An attempt to access\r
/// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r
/// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r
/// specify an temperature offset.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r
\r
-\r
/**\r
Package. MC Bank Error Configuration (R/W).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
/// to log additional info in bits 36:32.\r
///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 MemErrorLogEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r
/// PROCHOT# will be asserted. The value is degree C.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r
/// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r
/// will assert at the offset target temperature. Write is permitted only\r
/// MSR_PLATFORM_INFO.[30] is set.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r
/// limit of 9 core active.\r
///\r
- UINT32 Maximum9C:8;\r
+ UINT32 Maximum9C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r
/// limit of 10core active.\r
///\r
- UINT32 Maximum10C:8;\r
+ UINT32 Maximum10C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r
/// limit of 11 core active.\r
///\r
- UINT32 Maximum11C:8;\r
+ UINT32 Maximum11C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r
/// limit of 12 core active.\r
///\r
- UINT32 Maximum12C:8;\r
+ UINT32 Maximum12C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r
/// limit of 13 core active.\r
///\r
- UINT32 Maximum13C:8;\r
+ UINT32 Maximum13C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r
/// limit of 14 core active.\r
///\r
- UINT32 Maximum14C:8;\r
+ UINT32 Maximum14C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r
/// limit of 15 core active.\r
///\r
- UINT32 Maximum15C:8;\r
- UINT32 Reserved:7;\r
+ UINT32 Maximum15C : 8;\r
+ UINT32 Reserved : 7;\r
///\r
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
/// the processor uses override configuration specified in\r
/// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
/// uses factory-set configuration (Default).\r
///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r
\r
-\r
/**\r
Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r
///\r
/// [Bits 5:0] Recoverable Address LSB.\r
///\r
- UINT32 RecoverableAddressLSB:6;\r
+ UINT32 RecoverableAddressLSB : 6;\r
///\r
/// [Bits 8:6] Address Mode.\r
///\r
- UINT32 AddressMode:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 AddressMode : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bits 31:16] PCI Express Requestor ID.\r
///\r
- UINT32 PCIExpressRequestorID:16;\r
+ UINT32 PCIExpressRequestorID : 16;\r
///\r
/// [Bits 39:32] PCI Express Segment Number.\r
///\r
- UINT32 PCIExpressSegmentNumber:8;\r
- UINT32 Reserved2:24;\r
+ UINT32 PCIExpressSegmentNumber : 8;\r
+ UINT32 Reserved2 : 24;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
-#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
-#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
-#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
-#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
-#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
-#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r
/// @}\r
\r
-\r
/**\r
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
15.3.2.4, "IA32_MCi_MISC MSRs.".\r
MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r
@{\r
**/\r
-#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
-#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
-#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r
/// @}\r
\r
-\r
/**\r
Package. Package RAPL Perf Status (R/O).\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
@endcode\r
@note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC0:1;\r
+ UINT32 PEBS_EN_PMC0 : 1;\r
///\r
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC1:1;\r
+ UINT32 PEBS_EN_PMC1 : 1;\r
///\r
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC2:1;\r
+ UINT32 PEBS_EN_PMC2 : 1;\r
///\r
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 PEBS_EN_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
///\r
- UINT32 LL_EN_PMC0:1;\r
+ UINT32 LL_EN_PMC0 : 1;\r
///\r
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
///\r
- UINT32 LL_EN_PMC1:1;\r
+ UINT32 LL_EN_PMC1 : 1;\r
///\r
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
///\r
- UINT32 LL_EN_PMC2:1;\r
+ UINT32 LL_EN_PMC2 : 1;\r
///\r
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:28;\r
+ UINT32 LL_EN_PMC3 : 1;\r
+ UINT32 Reserved2 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Uncore perfmon per-socket global control.\r
\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
\r
/**\r
Package. Uncore perfmon per-socket global status.\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
\r
/**\r
Package. Uncore perfmon per-socket global configuration.\r
@endcode\r
@note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
-\r
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
\r
/**\r
Package. Uncore U-box perfmon U-box wide status.\r
@endcode\r
@note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
-\r
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
\r
/**\r
Package. Uncore PCU perfmon box wide status.\r
@endcode\r
@note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
-\r
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
-\r
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
-\r
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
-\r
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
-\r
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
-\r
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
-\r
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
-\r
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
-\r
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
\r
/**\r
Package. Uncore C-box 8 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
\r
/**\r
Package. Uncore C-box 8 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
-\r
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
\r
/**\r
Package. Uncore C-box 9 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
\r
/**\r
Package. Uncore C-box 9 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
\r
/**\r
Package. Uncore C-box 9 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
-\r
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
\r
/**\r
Package. Uncore C-box 10 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
\r
/**\r
Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
\r
/**\r
Package. Uncore C-box 10 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
\r
/**\r
Package. Uncore C-box 10 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
-\r
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
\r
/**\r
Package. Uncore C-box 11 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
\r
/**\r
Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
\r
/**\r
Package. Uncore C-box 11 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
\r
/**\r
Package. Uncore C-box 11 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
-\r
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
\r
/**\r
Package. Uncore C-box 12 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
\r
/**\r
Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
\r
/**\r
Package. Uncore C-box 12 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
\r
/**\r
Package. Uncore C-box 12 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
-\r
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
\r
/**\r
Package. Uncore C-box 13 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
\r
/**\r
Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
\r
/**\r
Package. Uncore C-box 13 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
\r
/**\r
Package. Uncore C-box 13 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
-\r
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
\r
/**\r
Package. Uncore C-box 14 perfmon local box wide control.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
\r
/**\r
Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 0.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 2.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
\r
/**\r
Package. Uncore C-box 14 perfmon counter 3.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
-\r
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
\r
/**\r
Package. Uncore C-box 14 perfmon box wide filter1.\r
@endcode\r
@note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
**/\r
-#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
\r
#endif\r
@endcode\r
@note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
+#define MSR_NEHALEM_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 18;\r
///\r
/// [Bits 52:50] See Table 2-2.\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved3:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved3 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Thread. SMI Counter (R/O).\r
\r
@endcode\r
@note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
+#define MSR_NEHALEM_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
/// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
/// RESET.\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
\r
-\r
/**\r
Package. see http://biosbits.org.\r
\r
@endcode\r
@note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
+#define MSR_NEHALEM_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. The invariant TSC\r
/// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
/// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
/// programmable, and when set to 0, indicates TDC and TDP Limits for\r
/// Turbo mode are not programmable.\r
///\r
- UINT32 TDC_TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
+ UINT32 TDC_TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 133.33MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
@endcode\r
@note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
/// C-state limit. Note: This field cannot be used to limit package\r
/// C-state to C3.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:8;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 8;\r
///\r
/// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores\r
/// in a deep C-State will wake only when the event message is destined\r
/// for that core. When 0, all processor cores in a deep C-State will wake\r
/// for an event message.\r
///\r
- UINT32 InterruptFiltering:1;\r
+ UINT32 InterruptFiltering : 1;\r
///\r
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C6/C7 requests to C3 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
+ UINT32 C1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotion:1;\r
+ UINT32 CStateDemotion : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUndemotion : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
@endcode\r
@note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
/// address redirection is enabled, this is the IO port address reported\r
/// to the OS/software.\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
/// maximum C-State code name to be included when IO read to MWAIT\r
/// is the max C-State to include 001b - C6 is the max C-State to include\r
/// 010b - C7 is the max C-State to include.\r
///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 3;\r
+ UINT32 Reserved1 : 13;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 1.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Thread.\r
\r
@endcode\r
@note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
/// PROCHOT# will be asserted. The value is degree C.\r
///\r
- UINT32 TemperatureTarget:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 TemperatureTarget : 8;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
/// disables the adjacent cache line prefetcher, which fetches the cache\r
/// line that comprises a cache line pair (128 bytes).\r
///\r
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
+ UINT32 L2AdjacentCacheLinePrefetcherDisable : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
/// data cache IP prefetcher, which uses sequential load history (based on\r
/// instruction Pointer of previous loads) to determine whether to\r
/// prefetch additional lines.\r
///\r
- UINT32 DCUIPPrefetcherDisable:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 DCUIPPrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
See http://biosbits.org.\r
@endcode\r
@note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
-#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
+#define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
/// request from processor cores; When 1, disables hardware coordination\r
/// of Enhanced Intel Speedstep Technology requests.\r
///\r
- UINT32 EISTHardwareCoordinationDisable:1;\r
+ UINT32 EISTHardwareCoordinationDisable : 1;\r
///\r
/// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes\r
/// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
/// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
/// CPUID.(EAX=06h):ECX[3].\r
///\r
- UINT32 EnergyPerformanceBiasEnable:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 EnergyPerformanceBiasEnable : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
\r
-\r
/**\r
See http://biosbits.org.\r
\r
@endcode\r
@note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r
**/\r
-#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
+#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
/// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt\r
/// granularity.\r
///\r
- UINT32 TDPLimit:15;\r
+ UINT32 TDPLimit : 15;\r
///\r
/// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0\r
/// indicates override is not active, and a value = 1 indicates active.\r
///\r
- UINT32 TDPLimitOverrideEnable:1;\r
+ UINT32 TDPLimitOverrideEnable : 1;\r
///\r
/// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp\r
/// granularity.\r
///\r
- UINT32 TDCLimit:15;\r
+ UINT32 TDCLimit : 15;\r
///\r
/// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0\r
/// indicates override is not active, and a value = 1 indicates active.\r
///\r
- UINT32 TDCLimitOverrideEnable:1;\r
- UINT32 Reserved:32;\r
+ UINT32 TDCLimitOverrideEnable : 1;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Maximum4C : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
"Filtering of Last Branch Records.".\r
@endcode\r
@note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
+#define MSR_NEHALEM_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_NEHALEM_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_NEHALEM_LER_TO_LIP 0x000001DE\r
\r
/**\r
Core. Power Control Register. See http://biosbits.org.\r
@endcode\r
@note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
-#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
+#define MSR_NEHALEM_POWER_CTL 0x000001FC\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r
/// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
/// operating point when all execution cores enter MWAIT (C1).\r
///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 C1EEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_POWER_CTL_REGISTER;\r
\r
-\r
/**\r
Thread. (RO).\r
\r
@endcode\r
@note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:29;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 29;\r
///\r
/// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
///\r
- UINT32 Ovf_Uncore:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Ovf_Uncore : 1;\r
+ UINT32 Reserved3 : 2;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Thread. (R/W).\r
\r
@endcode\r
@note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:29;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 29;\r
///\r
/// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
///\r
- UINT32 Ovf_Uncore:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Ovf_Uncore : 1;\r
+ UINT32 Reserved3 : 2;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@endcode\r
@note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
+#define MSR_NEHALEM_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC0:1;\r
+ UINT32 PEBS_EN_PMC0 : 1;\r
///\r
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC1:1;\r
+ UINT32 PEBS_EN_PMC1 : 1;\r
///\r
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC2:1;\r
+ UINT32 PEBS_EN_PMC2 : 1;\r
///\r
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 PEBS_EN_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
///\r
- UINT32 LL_EN_PMC0:1;\r
+ UINT32 LL_EN_PMC0 : 1;\r
///\r
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
///\r
- UINT32 LL_EN_PMC1:1;\r
+ UINT32 LL_EN_PMC1 : 1;\r
///\r
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
///\r
- UINT32 LL_EN_PMC2:1;\r
+ UINT32 LL_EN_PMC2 : 1;\r
///\r
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:28;\r
+ UINT32 LL_EN_PMC3 : 1;\r
+ UINT32 Reserved2 : 28;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
@endcode\r
@note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
**/\r
-#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
+#define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
/// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
/// that will be counted. (R/W).\r
///\r
- UINT32 MinimumThreshold:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
+ UINT32 MinimumThreshold : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
@endcode\r
@note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
-\r
+#define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
-\r
+#define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F\r
/// @}\r
\r
-\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
record registers on the last branch record stack. This part of the stack\r
MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF\r
/// @}\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r
**/\r
-#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
+#define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301\r
\r
/**\r
MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
///\r
/// [Bit 0] From M to S (R/W).\r
///\r
- UINT32 FromMtoS:1;\r
+ UINT32 FromMtoS : 1;\r
///\r
/// [Bit 1] From E to S (R/W).\r
///\r
- UINT32 FromEtoS:1;\r
+ UINT32 FromEtoS : 1;\r
///\r
/// [Bit 2] From S to S (R/W).\r
///\r
- UINT32 FromStoS:1;\r
+ UINT32 FromStoS : 1;\r
///\r
/// [Bit 3] From F to S (R/W).\r
///\r
- UINT32 FromFtoS:1;\r
+ UINT32 FromFtoS : 1;\r
///\r
/// [Bit 4] From M to I (R/W).\r
///\r
- UINT32 FromMtoI:1;\r
+ UINT32 FromMtoI : 1;\r
///\r
/// [Bit 5] From E to I (R/W).\r
///\r
- UINT32 FromEtoI:1;\r
+ UINT32 FromEtoI : 1;\r
///\r
/// [Bit 6] From S to I (R/W).\r
///\r
- UINT32 FromStoI:1;\r
+ UINT32 FromStoI : 1;\r
///\r
/// [Bit 7] From F to I (R/W).\r
///\r
- UINT32 FromFtoI:1;\r
- UINT32 Reserved1:24;\r
- UINT32 Reserved2:32;\r
+ UINT32 FromFtoI : 1;\r
+ UINT32 Reserved1 : 24;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
\r
-\r
/**\r
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
@endcode\r
@note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
-\r
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391\r
\r
/**\r
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
@endcode\r
@note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
-\r
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392\r
\r
/**\r
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
**/\r
#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393\r
\r
-\r
/**\r
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
@endcode\r
@note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
-\r
+#define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394\r
\r
/**\r
Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
@endcode\r
@note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
-\r
+#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395\r
\r
/**\r
Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".\r
@endcode\r
@note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
-\r
+#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396\r
\r
/**\r
Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r
@{\r
**/\r
-#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
-#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
-#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
-#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
-#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
-#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
-#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
-#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
+#define MSR_NEHALEM_UNCORE_PMC0 0x000003B0\r
+#define MSR_NEHALEM_UNCORE_PMC1 0x000003B1\r
+#define MSR_NEHALEM_UNCORE_PMC2 0x000003B2\r
+#define MSR_NEHALEM_UNCORE_PMC3 0x000003B3\r
+#define MSR_NEHALEM_UNCORE_PMC4 0x000003B4\r
+#define MSR_NEHALEM_UNCORE_PMC5 0x000003B5\r
+#define MSR_NEHALEM_UNCORE_PMC6 0x000003B6\r
+#define MSR_NEHALEM_UNCORE_PMC7 0x000003B7\r
/// @}\r
\r
/**\r
MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r
@{\r
**/\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
-#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6\r
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7\r
/// @}\r
\r
-\r
/**\r
Package. Uncore W-box perfmon fixed counter.\r
\r
@endcode\r
@note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
-\r
+#define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394\r
\r
/**\r
Package. Uncore U-box perfmon fixed counter control MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
-\r
+#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395\r
\r
/**\r
Package. Uncore U-box perfmon global control MSR.\r
@endcode\r
@note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
-\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00\r
\r
/**\r
Package. Uncore U-box perfmon global status MSR.\r
@endcode\r
@note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
-\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01\r
\r
/**\r
Package. Uncore U-box perfmon global overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
-\r
+#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02\r
\r
/**\r
Package. Uncore U-box perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r
**/\r
-#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
-\r
+#define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10\r
\r
/**\r
Package. Uncore U-box perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r
**/\r
-#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
-\r
+#define MSR_NEHALEM_U_PMON_CTR 0x00000C11\r
\r
/**\r
Package. Uncore B-box 0 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
-\r
+#define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20\r
\r
/**\r
Package. Uncore B-box 0 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
-\r
+#define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21\r
\r
/**\r
Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
-\r
+#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22\r
\r
/**\r
Package. Uncore B-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
-\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30\r
\r
/**\r
Package. Uncore B-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
-\r
+#define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31\r
\r
/**\r
Package. Uncore B-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
-\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32\r
\r
/**\r
Package. Uncore B-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
-\r
+#define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33\r
\r
/**\r
Package. Uncore B-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
-\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34\r
\r
/**\r
Package. Uncore B-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
-\r
+#define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35\r
\r
/**\r
Package. Uncore B-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
-\r
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36\r
\r
/**\r
Package. Uncore B-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
-\r
+#define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37\r
\r
/**\r
Package. Uncore S-box 0 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
-\r
+#define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40\r
\r
/**\r
Package. Uncore S-box 0 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
-\r
+#define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41\r
\r
/**\r
Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
-\r
+#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42\r
\r
/**\r
Package. Uncore S-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
-\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50\r
\r
/**\r
Package. Uncore S-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
-\r
+#define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51\r
\r
/**\r
Package. Uncore S-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
-\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52\r
\r
/**\r
Package. Uncore S-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
-\r
+#define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53\r
\r
/**\r
Package. Uncore S-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
-\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54\r
\r
/**\r
Package. Uncore S-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
-\r
+#define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55\r
\r
/**\r
Package. Uncore S-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
-\r
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56\r
\r
/**\r
Package. Uncore S-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
-\r
+#define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57\r
\r
/**\r
Package. Uncore B-box 1 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
-\r
+#define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60\r
\r
/**\r
Package. Uncore B-box 1 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
-\r
+#define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61\r
\r
/**\r
Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
-\r
+#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62\r
\r
/**\r
Package. Uncore B-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
-\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70\r
\r
/**\r
Package. Uncore B-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
-\r
+#define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71\r
\r
/**\r
Package. Uncore B-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
-\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72\r
\r
/**\r
Package. Uncore B-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
-\r
+#define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73\r
\r
/**\r
Package. Uncore B-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
-\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74\r
\r
/**\r
Package. Uncore B-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
-\r
+#define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75\r
\r
/**\r
Package. Uncore B-box 1vperfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
-\r
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76\r
\r
/**\r
Package. Uncore B-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
-\r
+#define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77\r
\r
/**\r
Package. Uncore W-box perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
-\r
+#define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80\r
\r
/**\r
Package. Uncore W-box perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
-\r
+#define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81\r
\r
/**\r
Package. Uncore W-box perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
-\r
+#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82\r
\r
/**\r
Package. Uncore W-box perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
-\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90\r
\r
/**\r
Package. Uncore W-box perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
-\r
+#define MSR_NEHALEM_W_PMON_CTR0 0x00000C91\r
\r
/**\r
Package. Uncore W-box perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
-\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92\r
\r
/**\r
Package. Uncore W-box perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
-\r
+#define MSR_NEHALEM_W_PMON_CTR1 0x00000C93\r
\r
/**\r
Package. Uncore W-box perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
-\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94\r
\r
/**\r
Package. Uncore W-box perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
-\r
+#define MSR_NEHALEM_W_PMON_CTR2 0x00000C95\r
\r
/**\r
Package. Uncore W-box perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
-\r
+#define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96\r
\r
/**\r
Package. Uncore W-box perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
-\r
+#define MSR_NEHALEM_W_PMON_CTR3 0x00000C97\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
-\r
+#define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
-\r
+#define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
-\r
+#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2\r
\r
/**\r
Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
-\r
+#define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4\r
\r
/**\r
Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
-\r
+#define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5\r
\r
/**\r
Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
-\r
+#define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6\r
\r
/**\r
Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
-\r
+#define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7\r
\r
/**\r
Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
-\r
+#define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8\r
\r
/**\r
Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
-\r
+#define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9\r
\r
/**\r
Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
-\r
+#define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA\r
\r
/**\r
Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
-\r
+#define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9\r
\r
/**\r
Package. Uncore M-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
-\r
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA\r
\r
/**\r
Package. Uncore M-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
-\r
+#define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB\r
\r
/**\r
Package. Uncore S-box 1 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
-\r
+#define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0\r
\r
/**\r
Package. Uncore S-box 1 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
-\r
+#define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1\r
\r
/**\r
Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
-\r
+#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2\r
\r
/**\r
Package. Uncore S-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
-\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0\r
\r
/**\r
Package. Uncore S-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
-\r
+#define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1\r
\r
/**\r
Package. Uncore S-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
-\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2\r
\r
/**\r
Package. Uncore S-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
-\r
+#define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3\r
\r
/**\r
Package. Uncore S-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
-\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4\r
\r
/**\r
Package. Uncore S-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
-\r
+#define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5\r
\r
/**\r
Package. Uncore S-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
-\r
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6\r
\r
/**\r
Package. Uncore S-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
-\r
+#define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
-\r
+#define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
-\r
+#define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
-\r
+#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2\r
\r
/**\r
Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
-\r
+#define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4\r
\r
/**\r
Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
-\r
+#define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5\r
\r
/**\r
Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
-\r
+#define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6\r
\r
/**\r
Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
-\r
+#define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7\r
\r
/**\r
Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
-\r
+#define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8\r
\r
/**\r
Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
-\r
+#define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9\r
\r
/**\r
Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
-\r
+#define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA\r
\r
/**\r
Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
-\r
+#define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9\r
\r
/**\r
Package. Uncore M-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
-\r
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA\r
\r
/**\r
Package. Uncore M-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
-\r
+#define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB\r
\r
/**\r
Package. Uncore C-box 0 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
-\r
+#define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00\r
\r
/**\r
Package. Uncore C-box 0 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
-\r
+#define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01\r
\r
/**\r
Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
-\r
+#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
-\r
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
-\r
+#define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B\r
\r
/**\r
Package. Uncore C-box 4 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
-\r
+#define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20\r
\r
/**\r
Package. Uncore C-box 4 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
-\r
+#define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21\r
\r
/**\r
Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
-\r
+#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
-\r
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
-\r
+#define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B\r
\r
/**\r
Package. Uncore C-box 2 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
-\r
+#define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40\r
\r
/**\r
Package. Uncore C-box 2 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
-\r
+#define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41\r
\r
/**\r
Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
-\r
+#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
-\r
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
-\r
+#define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B\r
\r
/**\r
Package. Uncore C-box 6 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
-\r
+#define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60\r
\r
/**\r
Package. Uncore C-box 6 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
-\r
+#define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61\r
\r
/**\r
Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
-\r
+#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
-\r
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
-\r
+#define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B\r
\r
/**\r
Package. Uncore C-box 1 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
-\r
+#define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80\r
\r
/**\r
Package. Uncore C-box 1 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
-\r
+#define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81\r
\r
/**\r
Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
-\r
+#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
-\r
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
-\r
+#define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B\r
\r
/**\r
Package. Uncore C-box 5 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
-\r
+#define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0\r
\r
/**\r
Package. Uncore C-box 5 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
-\r
+#define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1\r
\r
/**\r
Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
-\r
+#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
-\r
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
-\r
+#define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB\r
\r
/**\r
Package. Uncore C-box 3 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
-\r
+#define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0\r
\r
/**\r
Package. Uncore C-box 3 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
-\r
+#define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1\r
\r
/**\r
Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
-\r
+#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
-\r
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
-\r
+#define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB\r
\r
/**\r
Package. Uncore C-box 7 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
-\r
+#define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0\r
\r
/**\r
Package. Uncore C-box 7 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
-\r
+#define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1\r
\r
/**\r
Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
-\r
+#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
-\r
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
-\r
+#define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB\r
\r
/**\r
Package. Uncore R-box 0 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
-\r
+#define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00\r
\r
/**\r
Package. Uncore R-box 0 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
-\r
+#define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01\r
\r
/**\r
Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
-\r
+#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A\r
\r
/**\r
Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
-\r
+#define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B\r
\r
/**\r
Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
-\r
+#define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C\r
\r
/**\r
Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
-\r
+#define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D\r
\r
/**\r
Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
-\r
+#define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E\r
\r
/**\r
Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
-\r
+#define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D\r
\r
/**\r
Package. Uncore R-box 0 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
-\r
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E\r
\r
/**\r
Package. Uncore R-box 0 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r
**/\r
-#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
-\r
+#define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F\r
\r
/**\r
Package. Uncore R-box 1 perfmon local box control MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
-\r
+#define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20\r
\r
/**\r
Package. Uncore R-box 1 perfmon local box status MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
-\r
+#define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21\r
\r
/**\r
Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
-\r
+#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A\r
\r
/**\r
Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
-\r
+#define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B\r
\r
/**\r
Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
-\r
+#define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C\r
\r
/**\r
Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
-\r
+#define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D\r
\r
/**\r
Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
-\r
+#define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E\r
\r
/**\r
Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
-\r
+#define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A\r
\r
/**\r
Package. Uncore R-box 1perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D\r
\r
/**\r
Package. Uncore R-box 1 perfmon event select MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
-\r
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E\r
\r
/**\r
Package. Uncore R-box 1 perfmon counter MSR.\r
@endcode\r
@note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r
**/\r
-#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
-\r
+#define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F\r
\r
/**\r
Package. Uncore B-box 0 perfmon local box match MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
-\r
+#define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45\r
\r
/**\r
Package. Uncore B-box 0 perfmon local box mask MSR.\r
@endcode\r
@note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
-\r
+#define MSR_NEHALEM_B0_PMON_MASK 0x00000E46\r
\r
/**\r
Package. Uncore S-box 0 perfmon local box match MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
-\r
+#define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49\r
\r
/**\r
Package. Uncore S-box 0 perfmon local box mask MSR.\r
@endcode\r
@note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
-\r
+#define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A\r
\r
/**\r
Package. Uncore B-box 1 perfmon local box match MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
-\r
+#define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D\r
\r
/**\r
Package. Uncore B-box 1 perfmon local box mask MSR.\r
@endcode\r
@note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
-\r
+#define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
-\r
+#define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box address match MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
-\r
+#define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55\r
\r
/**\r
Package. Uncore M-box 0 perfmon local box address mask MSR.\r
@endcode\r
@note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
-\r
+#define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56\r
\r
/**\r
Package. Uncore S-box 1 perfmon local box match MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
-\r
+#define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59\r
\r
/**\r
Package. Uncore S-box 1 perfmon local box mask MSR.\r
@endcode\r
@note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
-\r
+#define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
-\r
+#define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box address match MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
-\r
+#define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D\r
\r
/**\r
Package. Uncore M-box 1 perfmon local box address mask MSR.\r
@endcode\r
@note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r
**/\r
-#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
+#define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E\r
\r
#endif\r
@endcode\r
@note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_P6_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_P6_P5_MC_ADDR 0x00000000\r
\r
/**\r
See Section 2.22, "MSRs in Pentium Processors.".\r
@endcode\r
@note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_P6_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_P6_P5_MC_TYPE 0x00000001\r
\r
/**\r
See Section 17.17, "Time-Stamp Counter.".\r
@endcode\r
@note MSR_P6_TSC is defined as TSC in SDM.\r
**/\r
-#define MSR_P6_TSC 0x00000010\r
-\r
+#define MSR_P6_TSC 0x00000010\r
\r
/**\r
Platform ID (R) The operating system can use this MSR to determine "slot"\r
@endcode\r
@note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
+#define MSR_P6_IA32_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:18;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 18;\r
///\r
/// [Bits 52:50] Platform Id (R) Contains information concerning the\r
/// intended platform for the processor.\r
/// 1 1 0 Processor Flag 6\r
/// 1 1 1 Processor Flag 7\r
///\r
- UINT32 PlatformId:3;\r
+ UINT32 PlatformId : 3;\r
///\r
/// [Bits 56:53] L2 Cache Latency Read.\r
///\r
- UINT32 L2CacheLatencyRead:4;\r
- UINT32 Reserved3:3;\r
+ UINT32 L2CacheLatencyRead : 4;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 60] Clock Frequency Ratio Read.\r
///\r
- UINT32 ClockFrequencyRatioRead:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 ClockFrequencyRatioRead : 1;\r
+ UINT32 Reserved4 : 3;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_IA32_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Section 10.4.4, "Local APIC Status and Location.".\r
\r
@endcode\r
@note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.\r
**/\r
-#define MSR_P6_APIC_BASE 0x0000001B\r
+#define MSR_P6_APIC_BASE 0x0000001B\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_APIC_BASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.\r
///\r
- UINT32 BSP:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 BSP : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =\r
/// Disabled.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bits 31:12] APIC Base Address.\r
///\r
- UINT32 ApicBase:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 ApicBase : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_APIC_BASE_REGISTER;\r
\r
-\r
/**\r
Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
features; (R) indicates current processor configuration.\r
@endcode\r
@note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
+#define MSR_P6_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)\r
/// 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 AERR_DriveEnable:1;\r
+ UINT32 AERR_DriveEnable : 1;\r
///\r
/// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =\r
/// Disabled.\r
///\r
- UINT32 BERR_Enable:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 BERR_Enable : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =\r
/// Enabled 0 = Disabled.\r
///\r
- UINT32 BERR_DriverEnable:1;\r
+ UINT32 BERR_DriverEnable : 1;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 AERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 AERR_ObservationEnabled : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
///\r
/// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.\r
///\r
- UINT32 InOrderQueueDepth:1;\r
+ UINT32 InOrderQueueDepth : 1;\r
///\r
/// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.\r
///\r
- UINT32 ResetVector:1;\r
+ UINT32 ResetVector : 1;\r
///\r
/// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.\r
///\r
- UINT32 FRCModeEnable:1;\r
+ UINT32 FRCModeEnable : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R).\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =\r
/// 133MHz 11 = Reserved.\r
///\r
- UINT32 SystemBusFrequency:2;\r
+ UINT32 SystemBusFrequency : 2;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R).\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 25:22] Clock Frequency Ratio (R).\r
///\r
- UINT32 ClockFrequencyRatio:4;\r
+ UINT32 ClockFrequencyRatio : 4;\r
///\r
/// [Bit 26] Low Power Mode Enable (R/W).\r
///\r
- UINT32 LowPowerModeEnable:1;\r
+ UINT32 LowPowerModeEnable : 1;\r
///\r
/// [Bit 27] Clock Frequency Ratio.\r
///\r
- UINT32 ClockFrequencyRatio1:1;\r
- UINT32 Reserved4:4;\r
- UINT32 Reserved5:32;\r
+ UINT32 ClockFrequencyRatio1 : 1;\r
+ UINT32 Reserved4 : 4;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Test Control Register.\r
\r
@endcode\r
@note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.\r
**/\r
-#define MSR_P6_TEST_CTL 0x00000033\r
+#define MSR_P6_TEST_CTL 0x00000033\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_TEST_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:30;\r
+ UINT32 Reserved1 : 30;\r
///\r
/// [Bit 30] Streaming Buffer Disable.\r
///\r
- UINT32 StreamingBufferDisable:1;\r
+ UINT32 StreamingBufferDisable : 1;\r
///\r
/// [Bit 31] Disable LOCK# Assertion for split locked access.\r
///\r
- UINT32 Disable_LOCK:1;\r
- UINT32 Reserved2:32;\r
+ UINT32 Disable_LOCK : 1;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_TEST_CTL_REGISTER;\r
\r
-\r
/**\r
BIOS Update Trigger Register.\r
\r
@endcode\r
@note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.\r
**/\r
-#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
-\r
+#define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r
\r
/**\r
Chunk n data register D[63:0]: used to write to and read from the L2.\r
MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.\r
@{\r
**/\r
-#define MSR_P6_BBL_CR_D0 0x00000088\r
-#define MSR_P6_BBL_CR_D1 0x00000089\r
-#define MSR_P6_BBL_CR_D2 0x0000008A\r
+#define MSR_P6_BBL_CR_D0 0x00000088\r
+#define MSR_P6_BBL_CR_D1 0x00000089\r
+#define MSR_P6_BBL_CR_D2 0x0000008A\r
/// @}\r
\r
-\r
/**\r
BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to\r
write to and read from the L2 depending on the usage model.\r
@endcode\r
@note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.\r
**/\r
-#define MSR_P6_BIOS_SIGN 0x0000008B\r
-\r
+#define MSR_P6_BIOS_SIGN 0x0000008B\r
\r
/**\r
\r
MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.\r
@{\r
**/\r
-#define MSR_P6_PERFCTR0 0x000000C1\r
-#define MSR_P6_PERFCTR1 0x000000C2\r
+#define MSR_P6_PERFCTR0 0x000000C1\r
+#define MSR_P6_PERFCTR1 0x000000C2\r
/// @}\r
\r
-\r
/**\r
\r
\r
@endcode\r
@note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.\r
**/\r
-#define MSR_P6_MTRRCAP 0x000000FE\r
-\r
+#define MSR_P6_MTRRCAP 0x000000FE\r
\r
/**\r
Address register: used to send specified address (A31-A3) to L2 during cache\r
@endcode\r
@note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_ADDR 0x00000116\r
+#define MSR_P6_BBL_CR_ADDR 0x00000116\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bits 31:3] Address bits\r
///\r
- UINT32 Address:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 Address : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_BBL_CR_ADDR_REGISTER;\r
\r
-\r
/**\r
Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.\r
\r
@endcode\r
@note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_DECC 0x00000118\r
-\r
+#define MSR_P6_BBL_CR_DECC 0x00000118\r
\r
/**\r
Control register: used to program L2 commands to be issued via cache\r
@endcode\r
@note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_CTL 0x00000119\r
+#define MSR_P6_BBL_CR_CTL 0x00000119\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_BBL_CR_CTL\r
/// Tag Write w/ Data Write (TWW)\r
/// Tag Write (TW).\r
///\r
- UINT32 L2Command:5;\r
+ UINT32 L2Command : 5;\r
///\r
/// [Bits 6:5] State to L2\r
///\r
- UINT32 StateToL2:2;\r
- UINT32 Reserved:1;\r
+ UINT32 StateToL2 : 2;\r
+ UINT32 Reserved : 1;\r
///\r
/// [Bits 9:8] Way to L2.\r
///\r
- UINT32 WayToL2:2;\r
+ UINT32 WayToL2 : 2;\r
///\r
/// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.\r
///\r
- UINT32 Way:2;\r
+ UINT32 Way : 2;\r
///\r
/// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.\r
///\r
- UINT32 MESI:2;\r
+ UINT32 MESI : 2;\r
///\r
/// [Bits 15:14] State from L2.\r
///\r
- UINT32 StateFromL2:2;\r
- UINT32 Reserved2:1;\r
+ UINT32 StateFromL2 : 2;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 17] L2 Hit.\r
///\r
- UINT32 L2Hit:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 L2Hit : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bits 20:19] User supplied ECC.\r
///\r
- UINT32 UserEcc:2;\r
+ UINT32 UserEcc : 2;\r
///\r
/// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.\r
///\r
- UINT32 ProcessorNumber:1;\r
- UINT32 Reserved4:10;\r
- UINT32 Reserved5:32;\r
+ UINT32 ProcessorNumber : 1;\r
+ UINT32 Reserved4 : 10;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_BBL_CR_CTL_REGISTER;\r
\r
-\r
/**\r
Trigger register: used to initiate a cache configuration accesses access,\r
Write only with Data = 0.\r
@endcode\r
@note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
-\r
+#define MSR_P6_BBL_CR_TRIG 0x0000011A\r
\r
/**\r
Busy register: indicates when a cache configuration accesses L2 command is\r
@endcode\r
@note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
-\r
+#define MSR_P6_BBL_CR_BUSY 0x0000011B\r
\r
/**\r
Control register 3: used to configure the L2 Cache.\r
@endcode\r
@note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
+#define MSR_P6_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3\r
///\r
/// [Bit 0] L2 Configured (read/write ).\r
///\r
- UINT32 L2Configured:1;\r
+ UINT32 L2Configured : 1;\r
///\r
/// [Bits 4:1] L2 Cache Latency (read/write).\r
///\r
- UINT32 L2CacheLatency:4;\r
+ UINT32 L2CacheLatency : 4;\r
///\r
/// [Bit 5] ECC Check Enable (read/write).\r
///\r
- UINT32 ECCCheckEnable:1;\r
+ UINT32 ECCCheckEnable : 1;\r
///\r
/// [Bit 6] Address Parity Check Enable (read/write).\r
///\r
- UINT32 AddressParityCheckEnable:1;\r
+ UINT32 AddressParityCheckEnable : 1;\r
///\r
/// [Bit 7] CRTN Parity Check Enable (read/write).\r
///\r
- UINT32 CRTNParityCheckEnable:1;\r
+ UINT32 CRTNParityCheckEnable : 1;\r
///\r
/// [Bit 8] L2 Enabled (read/write).\r
///\r
- UINT32 L2Enabled:1;\r
+ UINT32 L2Enabled : 1;\r
///\r
/// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way\r
/// Reserved.\r
///\r
- UINT32 L2Associativity:2;\r
+ UINT32 L2Associativity : 2;\r
///\r
/// [Bits 12:11] Number of L2 banks (read only).\r
///\r
- UINT32 L2Banks:2;\r
+ UINT32 L2Banks : 2;\r
///\r
/// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes\r
/// 1MByte 2MByte 4MBytes.\r
///\r
- UINT32 CacheSizePerBank:5;\r
+ UINT32 CacheSizePerBank : 5;\r
///\r
/// [Bit 18] Cache State error checking enable (read/write).\r
///\r
- UINT32 CacheStateErrorEnable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 CacheStateErrorEnable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes\r
/// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.\r
///\r
- UINT32 L2AddressRange:3;\r
+ UINT32 L2AddressRange : 3;\r
///\r
/// [Bit 23] L2 Hardware Disable (read only).\r
///\r
- UINT32 L2HardwareDisable:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 L2HardwareDisable : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 25] Cache bus fraction (read only).\r
///\r
- UINT32 CacheBusFraction:1;\r
- UINT32 Reserved3:6;\r
- UINT32 Reserved4:32;\r
+ UINT32 CacheBusFraction : 1;\r
+ UINT32 Reserved3 : 6;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
CS register target for CPL 0 code.\r
\r
@endcode\r
@note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.\r
**/\r
-#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
-\r
+#define MSR_P6_SYSENTER_CS_MSR 0x00000174\r
\r
/**\r
Stack pointer for CPL 0 stack.\r
@endcode\r
@note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.\r
**/\r
-#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
-\r
+#define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r
\r
/**\r
CPL 0 code entry point.\r
@endcode\r
@note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.\r
**/\r
-#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
-\r
+#define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.\r
**/\r
-#define MSR_P6_MCG_CAP 0x00000179\r
-\r
+#define MSR_P6_MCG_CAP 0x00000179\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.\r
**/\r
-#define MSR_P6_MCG_STATUS 0x0000017A\r
-\r
+#define MSR_P6_MCG_STATUS 0x0000017A\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.\r
**/\r
-#define MSR_P6_MCG_CTL 0x0000017B\r
-\r
+#define MSR_P6_MCG_CTL 0x0000017B\r
\r
/**\r
\r
MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.\r
@{\r
**/\r
-#define MSR_P6_PERFEVTSEL0 0x00000186\r
-#define MSR_P6_PERFEVTSEL1 0x00000187\r
+#define MSR_P6_PERFEVTSEL0 0x00000186\r
+#define MSR_P6_PERFEVTSEL1 0x00000187\r
/// @}\r
\r
/**\r
/// [Bits 7:0] Event Select Refer to Performance Counter section for a\r
/// list of event encodings.\r
///\r
- UINT32 EventSelect:8;\r
+ UINT32 EventSelect : 8;\r
///\r
/// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable\r
/// all count options.\r
///\r
- UINT32 UMASK:8;\r
+ UINT32 UMASK : 8;\r
///\r
/// [Bit 16] USER Controls the counting of events at Privilege levels of\r
/// 1, 2, and 3.\r
///\r
- UINT32 USR:1;\r
+ UINT32 USR : 1;\r
///\r
/// [Bit 17] OS Controls the counting of events at Privilege level of 0.\r
///\r
- UINT32 OS:1;\r
+ UINT32 OS : 1;\r
///\r
/// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.\r
///\r
- UINT32 E:1;\r
+ UINT32 E : 1;\r
///\r
/// [Bit 19] PC Enabled the signaling of performance counter overflow via\r
/// BP0 pin.\r
///\r
- UINT32 PC:1;\r
+ UINT32 PC : 1;\r
///\r
/// [Bit 20] INT Enables the signaling of counter overflow via input to\r
/// APIC 1 = Enable 0 = Disable.\r
///\r
- UINT32 INT:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 INT : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 22] ENABLE Enables the counting of performance events in both\r
/// counters 1 = Enable 0 = Disable.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0\r
/// = Non-Inverted.\r
///\r
- UINT32 INV:1;\r
+ UINT32 INV : 1;\r
///\r
/// [Bits 31:24] CMASK (Counter Mask).\r
///\r
- UINT32 CMASK:8;\r
- UINT32 Reserved2:32;\r
+ UINT32 CMASK : 8;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_PERFEVTSEL_REGISTER;\r
\r
-\r
/**\r
\r
\r
@endcode\r
@note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.\r
**/\r
-#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
+#define MSR_P6_DEBUGCTLMSR 0x000001D9\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR\r
///\r
/// [Bit 0] Enable/Disable Last Branch Records.\r
///\r
- UINT32 LBR:1;\r
+ UINT32 LBR : 1;\r
///\r
/// [Bit 1] Branch Trap Flag.\r
///\r
- UINT32 BTF:1;\r
+ UINT32 BTF : 1;\r
///\r
/// [Bit 2] Performance Monitoring/Break Point Pins.\r
///\r
- UINT32 PB0:1;\r
+ UINT32 PB0 : 1;\r
///\r
/// [Bit 3] Performance Monitoring/Break Point Pins.\r
///\r
- UINT32 PB1:1;\r
+ UINT32 PB1 : 1;\r
///\r
/// [Bit 4] Performance Monitoring/Break Point Pins.\r
///\r
- UINT32 PB2:1;\r
+ UINT32 PB2 : 1;\r
///\r
/// [Bit 5] Performance Monitoring/Break Point Pins.\r
///\r
- UINT32 PB3:1;\r
+ UINT32 PB3 : 1;\r
///\r
/// [Bit 6] Enable/Disable Execution Trace Messages.\r
///\r
- UINT32 TR:1;\r
- UINT32 Reserved1:25;\r
- UINT32 Reserved2:32;\r
+ UINT32 TR : 1;\r
+ UINT32 Reserved1 : 25;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_DEBUGCTLMSR_REGISTER;\r
\r
-\r
/**\r
\r
\r
@endcode\r
@note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.\r
**/\r
-#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
-\r
+#define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.\r
**/\r
-#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
-\r
+#define MSR_P6_LASTBRANCHTOIP 0x000001DC\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.\r
**/\r
-#define MSR_P6_LASTINTFROMIP 0x000001DD\r
-\r
+#define MSR_P6_LASTINTFROMIP 0x000001DD\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.\r
**/\r
-#define MSR_P6_LASTINTTOIP 0x000001DE\r
+#define MSR_P6_LASTINTTOIP 0x000001DE\r
\r
/**\r
\r
MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r
@{\r
**/\r
-#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
-#define MSR_P6_MTRRPHYSBASE1 0x00000202\r
-#define MSR_P6_MTRRPHYSBASE2 0x00000204\r
-#define MSR_P6_MTRRPHYSBASE3 0x00000206\r
-#define MSR_P6_MTRRPHYSBASE4 0x00000208\r
-#define MSR_P6_MTRRPHYSBASE5 0x0000020A\r
-#define MSR_P6_MTRRPHYSBASE6 0x0000020C\r
-#define MSR_P6_MTRRPHYSBASE7 0x0000020E\r
+#define MSR_P6_MTRRPHYSBASE0 0x00000200\r
+#define MSR_P6_MTRRPHYSBASE1 0x00000202\r
+#define MSR_P6_MTRRPHYSBASE2 0x00000204\r
+#define MSR_P6_MTRRPHYSBASE3 0x00000206\r
+#define MSR_P6_MTRRPHYSBASE4 0x00000208\r
+#define MSR_P6_MTRRPHYSBASE5 0x0000020A\r
+#define MSR_P6_MTRRPHYSBASE6 0x0000020C\r
+#define MSR_P6_MTRRPHYSBASE7 0x0000020E\r
/// @}\r
\r
-\r
/**\r
\r
\r
MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r
@{\r
**/\r
-#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
-#define MSR_P6_MTRRPHYSMASK1 0x00000203\r
-#define MSR_P6_MTRRPHYSMASK2 0x00000205\r
-#define MSR_P6_MTRRPHYSMASK3 0x00000207\r
-#define MSR_P6_MTRRPHYSMASK4 0x00000209\r
-#define MSR_P6_MTRRPHYSMASK5 0x0000020B\r
-#define MSR_P6_MTRRPHYSMASK6 0x0000020D\r
-#define MSR_P6_MTRRPHYSMASK7 0x0000020F\r
+#define MSR_P6_MTRRPHYSMASK0 0x00000201\r
+#define MSR_P6_MTRRPHYSMASK1 0x00000203\r
+#define MSR_P6_MTRRPHYSMASK2 0x00000205\r
+#define MSR_P6_MTRRPHYSMASK3 0x00000207\r
+#define MSR_P6_MTRRPHYSMASK4 0x00000209\r
+#define MSR_P6_MTRRPHYSMASK5 0x0000020B\r
+#define MSR_P6_MTRRPHYSMASK6 0x0000020D\r
+#define MSR_P6_MTRRPHYSMASK7 0x0000020F\r
/// @}\r
\r
-\r
/**\r
\r
\r
@endcode\r
@note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
-\r
+#define MSR_P6_MTRRFIX64K_00000 0x00000250\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
-\r
+#define MSR_P6_MTRRFIX16K_80000 0x00000258\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
-\r
+#define MSR_P6_MTRRFIX16K_A0000 0x00000259\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
-\r
+#define MSR_P6_MTRRFIX4K_C0000 0x00000268\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
-\r
+#define MSR_P6_MTRRFIX4K_C8000 0x00000269\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
-\r
+#define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
-\r
+#define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
-\r
+#define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
-\r
+#define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
-\r
+#define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r
**/\r
-#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
-\r
+#define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r
\r
/**\r
\r
@endcode\r
@note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.\r
**/\r
-#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
+#define MSR_P6_MTRRDEFTYPE 0x000002FF\r
\r
/**\r
MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE\r
///\r
/// [Bits 2:0] Default memory type.\r
///\r
- UINT32 Type:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Type : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] Fixed MTRR enable.\r
///\r
- UINT32 FE:1;\r
+ UINT32 FE : 1;\r
///\r
/// [Bit 11] MTRR Enable.\r
///\r
- UINT32 E:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 E : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_MTRRDEFTYPE_REGISTER;\r
\r
-\r
/**\r
\r
\r
MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.\r
@{\r
**/\r
-#define MSR_P6_MC0_CTL 0x00000400\r
-#define MSR_P6_MC1_CTL 0x00000404\r
-#define MSR_P6_MC2_CTL 0x00000408\r
-#define MSR_P6_MC3_CTL 0x00000410\r
-#define MSR_P6_MC4_CTL 0x0000040C\r
+#define MSR_P6_MC0_CTL 0x00000400\r
+#define MSR_P6_MC1_CTL 0x00000404\r
+#define MSR_P6_MC2_CTL 0x00000408\r
+#define MSR_P6_MC3_CTL 0x00000410\r
+#define MSR_P6_MC4_CTL 0x0000040C\r
/// @}\r
\r
-\r
/**\r
\r
Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,\r
MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_P6_MC0_STATUS 0x00000401\r
-#define MSR_P6_MC1_STATUS 0x00000405\r
-#define MSR_P6_MC2_STATUS 0x00000409\r
-#define MSR_P6_MC3_STATUS 0x00000411\r
-#define MSR_P6_MC4_STATUS 0x0000040D\r
+#define MSR_P6_MC0_STATUS 0x00000401\r
+#define MSR_P6_MC1_STATUS 0x00000405\r
+#define MSR_P6_MC2_STATUS 0x00000409\r
+#define MSR_P6_MC3_STATUS 0x00000411\r
+#define MSR_P6_MC4_STATUS 0x0000040D\r
/// @}\r
\r
/**\r
///\r
/// [Bits 15:0] MC_STATUS_MCACOD.\r
///\r
- UINT32 MC_STATUS_MCACOD:16;\r
+ UINT32 MC_STATUS_MCACOD : 16;\r
///\r
/// [Bits 31:16] MC_STATUS_MSCOD.\r
///\r
- UINT32 MC_STATUS_MSCOD:16;\r
- UINT32 Reserved:25;\r
+ UINT32 MC_STATUS_MSCOD : 16;\r
+ UINT32 Reserved : 25;\r
///\r
/// [Bit 57] MC_STATUS_DAM.\r
///\r
- UINT32 MC_STATUS_DAM:1;\r
+ UINT32 MC_STATUS_DAM : 1;\r
///\r
/// [Bit 58] MC_STATUS_ADDRV.\r
///\r
- UINT32 MC_STATUS_ADDRV:1;\r
+ UINT32 MC_STATUS_ADDRV : 1;\r
///\r
/// [Bit 59] MC_STATUS_MISCV.\r
///\r
- UINT32 MC_STATUS_MISCV:1;\r
+ UINT32 MC_STATUS_MISCV : 1;\r
///\r
/// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is\r
/// hardcoded to 1.).\r
///\r
- UINT32 MC_STATUS_EN:1;\r
+ UINT32 MC_STATUS_EN : 1;\r
///\r
/// [Bit 61] MC_STATUS_UC.\r
///\r
- UINT32 MC_STATUS_UC:1;\r
+ UINT32 MC_STATUS_UC : 1;\r
///\r
/// [Bit 62] MC_STATUS_O.\r
///\r
- UINT32 MC_STATUS_O:1;\r
+ UINT32 MC_STATUS_O : 1;\r
///\r
/// [Bit 63] MC_STATUS_V.\r
///\r
- UINT32 MC_STATUS_V:1;\r
+ UINT32 MC_STATUS_V : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_P6_MC_STATUS_REGISTER;\r
\r
-\r
/**\r
\r
MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.\r
MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.\r
@{\r
**/\r
-#define MSR_P6_MC0_ADDR 0x00000402\r
-#define MSR_P6_MC1_ADDR 0x00000406\r
-#define MSR_P6_MC2_ADDR 0x0000040A\r
-#define MSR_P6_MC3_ADDR 0x00000412\r
-#define MSR_P6_MC4_ADDR 0x0000040E\r
+#define MSR_P6_MC0_ADDR 0x00000402\r
+#define MSR_P6_MC1_ADDR 0x00000406\r
+#define MSR_P6_MC2_ADDR 0x0000040A\r
+#define MSR_P6_MC3_ADDR 0x00000412\r
+#define MSR_P6_MC4_ADDR 0x0000040E\r
/// @}\r
\r
-\r
/**\r
Defined in MCA architecture but not implemented in the P6 family processors.\r
\r
MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.\r
@{\r
**/\r
-#define MSR_P6_MC0_MISC 0x00000403\r
-#define MSR_P6_MC1_MISC 0x00000407\r
-#define MSR_P6_MC2_MISC 0x0000040B\r
-#define MSR_P6_MC3_MISC 0x00000413\r
-#define MSR_P6_MC4_MISC 0x0000040F\r
+#define MSR_P6_MC0_MISC 0x00000403\r
+#define MSR_P6_MC1_MISC 0x00000407\r
+#define MSR_P6_MC2_MISC 0x0000040B\r
+#define MSR_P6_MC3_MISC 0x00000413\r
+#define MSR_P6_MC4_MISC 0x0000040F\r
/// @}\r
\r
#endif\r
@endcode\r
@note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
-\r
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
@endcode\r
@note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
+#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
/// The value in this bit is written on the deassertion of RESET#; the bit\r
/// is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 OutputTriStateEnabled:1;\r
+ UINT32 OutputTriStateEnabled : 1;\r
///\r
/// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
/// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
/// value in this bit is written on the deassertion of RESET#; the bit is\r
/// set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
/// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
/// strapping of A7#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 InOrderQueueDepth:1;\r
+ UINT32 InOrderQueueDepth : 1;\r
///\r
/// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
/// observation is enabled (0) or disabled (1) as determined by the\r
/// strapping of A9#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 MCERR_ObservationDisabled:1;\r
+ UINT32 MCERR_ObservationDisabled : 1;\r
///\r
/// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
/// observation is enabled (0) or disabled (1) as determined by the\r
/// strapping of A10#. The value in this bit is written on the deassertion\r
/// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
///\r
/// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
/// value as set by the strapping of A12# and A11#. The logical cluster ID\r
/// value is written into the field on the deassertion of RESET#; the\r
/// field is set to 1 when the address bus signal is asserted.\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
/// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
/// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
/// the address bus signal is asserted.\r
///\r
- UINT32 BusParkDisable:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 BusParkDisable : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
/// by the strapping of BR[3:0]. The logical ID value is written into the\r
/// field on the deassertion of RESET#; the field is set to 1 when the\r
/// address bus signal is asserted.\r
///\r
- UINT32 AgentID:2;\r
- UINT32 Reserved2:18;\r
- UINT32 Reserved3:32;\r
+ UINT32 AgentID : 2;\r
+ UINT32 Reserved2 : 18;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
Enables and disables processor features.\r
@endcode\r
@note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
+#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
/// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
/// to disabled (0, default).\r
///\r
- UINT32 RCNT_SCNT:1;\r
+ UINT32 RCNT_SCNT : 1;\r
///\r
/// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
/// bus parity checking; clear to enable parity checking.\r
///\r
- UINT32 DataErrorCheckingDisable:1;\r
+ UINT32 DataErrorCheckingDisable : 1;\r
///\r
/// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
/// (default); clear to enable.\r
///\r
- UINT32 ResponseErrorCheckingDisable:1;\r
+ UINT32 ResponseErrorCheckingDisable : 1;\r
///\r
/// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
/// (default); clear to enable.\r
///\r
- UINT32 AddressRequestErrorCheckingDisable:1;\r
+ UINT32 AddressRequestErrorCheckingDisable : 1;\r
///\r
/// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
/// for initiator bus requests (default); clear to enable.\r
///\r
- UINT32 InitiatorMCERR_Disable:1;\r
+ UINT32 InitiatorMCERR_Disable : 1;\r
///\r
/// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
/// for initiator internal errors (default); clear to enable.\r
///\r
- UINT32 InternalMCERR_Disable:1;\r
+ UINT32 InternalMCERR_Disable : 1;\r
///\r
/// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
/// (default); clear to enable driver.\r
///\r
- UINT32 BINIT_DriverDisable:1;\r
- UINT32 Reserved1:25;\r
- UINT32 Reserved2:32;\r
+ UINT32 BINIT_DriverDisable : 1;\r
+ UINT32 Reserved1 : 25;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
\r
-\r
/**\r
2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
this MSR varies according to the MODEL value in the CPUID version\r
@endcode\r
@note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
/// bus speed: *EncodingScalable Bus Speed*\r
/// Speed when encoding is 100B and model encoding = 6. All other values\r
/// are reserved.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:5;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved2 : 5;\r
///\r
/// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
/// The processor core clock frequency to system bus frequency ratio\r
/// observed at the de-assertion of the reset pin.\r
///\r
- UINT32 ClockRatio:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 ClockRatio : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
\r
-\r
/**\r
0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
this MSR varies according to the MODEL value of the CPUID version\r
@endcode\r
@note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:21;\r
+ UINT32 Reserved1 : 21;\r
///\r
/// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
/// bus speed: *Encoding* *Scalable Bus Speed*\r
///\r
/// 000B 100 MHz All others values reserved.\r
///\r
- UINT32 ScalableBusSpeed:3;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 ScalableBusSpeed : 3;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
-\r
+#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
-\r
+#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
-\r
+#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
-\r
+#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
-\r
+#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
-\r
+#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
-\r
+#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
-\r
+#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
-\r
+#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
@endcode\r
@note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
-\r
+#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
@endcode\r
@note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
+#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
/// code. It is the responsibility of the user (BIOS or operating system)\r
/// to clear this bit for normal operation.\r
///\r
- UINT32 DS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 DS : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
-\r
+#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
-\r
+#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
-\r
+#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
-\r
+#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
-\r
+#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
-\r
+#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
-\r
+#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
@endcode\r
@note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
-\r
+#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
\r
/**\r
Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
@endcode\r
@note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
-\r
+#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable. See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
///\r
- UINT32 FPU:1;\r
+ UINT32 FPU : 1;\r
///\r
/// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
/// Monitor," and see Table 2-2.\r
///\r
- UINT32 TM1:1;\r
+ UINT32 TM1 : 1;\r
///\r
/// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
/// to be issued instead of a split-lock cycle. Operating systems that set\r
/// bus.\r
/// This debug feature is specific to the Pentium 4 processor.\r
///\r
- UINT32 SplitLockDisable:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 SplitLockDisable : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
/// cache is disabled; when clear (default) the third-level cache is\r
/// control register CR0, the page-level cache controls, and/or the MTRRs.\r
/// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
///\r
- UINT32 ThirdLevelCacheDisable:1;\r
+ UINT32 ThirdLevelCacheDisable : 1;\r
///\r
/// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
+ UINT32 PerformanceMonitoring : 1;\r
///\r
/// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
/// suppressed during a Split Lock access. When clear (default), LOCK is\r
/// not suppressed.\r
///\r
- UINT32 SuppressLockEnable:1;\r
+ UINT32 SuppressLockEnable : 1;\r
///\r
/// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
/// When clear (default), enables the prefetch queue.\r
///\r
- UINT32 PrefetchQueueDisable:1;\r
+ UINT32 PrefetchQueueDisable : 1;\r
///\r
/// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
/// reporting through the FERR# pin is enabled; when clear, this interrupt\r
/// the normal operation of the FERR# pin (to indicate an unmasked\r
/// floatingpoint error) when the STPCLK# pin is not asserted.\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
/// Table 2-2. When set, the processor does not support branch trace\r
/// storage (BTS); when clear, BTS is supported.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r
/// (R) See Table 2-2. When set, the processor does not support processor\r
/// event-based sampling (PEBS); when clear, PEBS is supported.\r
///\r
- UINT32 PEBS:1;\r
+ UINT32 PEBS : 1;\r
///\r
/// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
/// sensor indicates that the die temperature is at the predetermined\r
/// this bit location. The processor is operating out of spec if both this\r
/// bit and the TM1 bit are set to disabled states.\r
///\r
- UINT32 TM2:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 TM2 : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
+ UINT32 MONITOR : 1;\r
///\r
/// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
/// the processor fetches the cache line of the 128-byte sector containing\r
/// in validation and testing. BIOS may contain a setup option that\r
/// controls the setting of this bit.\r
///\r
- UINT32 AdjacentCacheLinePrefetchDisable:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 AdjacentCacheLinePrefetchDisable : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r
/// can cause unexpected behavior to software that depends on the\r
/// availability of CPUID leaves greater than 3.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
+ UINT32 xTPR_Message_Disable : 1;\r
///\r
/// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
/// is placed in shared mode; when clear (default), the cache is placed in\r
/// the ability to switch modes is not supported. BIOS must not alter the\r
/// contents of IA32_MISC_ENABLE[24].\r
///\r
- UINT32 L1DataCacheContextMode:1;\r
- UINT32 Reserved5:7;\r
- UINT32 Reserved6:2;\r
+ UINT32 L1DataCacheContextMode : 1;\r
+ UINT32 Reserved5 : 7;\r
+ UINT32 Reserved6 : 2;\r
///\r
/// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved7:29;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved7 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
3, 4, 6. Shared. Platform Feature Requirements (R).\r
\r
@endcode\r
@note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
+#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:18;\r
+ UINT32 Reserved1 : 18;\r
///\r
/// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
/// has specific platform requirements. The details of the platform\r
/// requirements are listed in the respective data sheets of the processor.\r
///\r
- UINT32 PLATFORM:1;\r
- UINT32 Reserved2:13;\r
- UINT32 Reserved3:32;\r
+ UINT32 PLATFORM : 1;\r
+ UINT32 Reserved2 : 13;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
a pointer to the last branch instruction that the processor executed prior\r
@endcode\r
@note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
-\r
+#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
@endcode\r
@note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
-\r
+#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
@endcode\r
@note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
-\r
+#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
@endcode\r
@note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
-\r
+#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
\r
/**\r
0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
-#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
-#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
-#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
+#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
+#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
+#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
+#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
-#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
-#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
-#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
+#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
+#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
+#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
+#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
-#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
-#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
-#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
+#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
+#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
+#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
+#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
-#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
-#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
-#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
+#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
+#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
+#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
+#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r
\r
MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
-#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
-#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
-#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
-#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
-#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
+#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
+#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
+#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
+#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
+#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
+#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
-#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
-#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
-#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
+#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
+#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
+#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
+#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
-#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
-#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
-#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
+#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
+#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
+#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
+#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
-#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
-#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
-#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
+#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
+#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
+#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
+#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r
\r
MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
-#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
-#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
-#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
-#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
-#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
+#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
+#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
+#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
+#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
+#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
+#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@endcode\r
@note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
-\r
+#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
-\r
+#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
-\r
+#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
-\r
+#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
-\r
+#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
-\r
+#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
-\r
+#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
-\r
+#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
-\r
+#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
-\r
+#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
-\r
+#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
-\r
+#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
-\r
+#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
-\r
+#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
-\r
+#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
-\r
+#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
-\r
+#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
-\r
+#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
-\r
+#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
-\r
+#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
-\r
+#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
-\r
+#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
-\r
+#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
-\r
+#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
-\r
+#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
-\r
+#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
\r
/**\r
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
@endcode\r
@note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
-\r
+#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
\r
/**\r
0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r
@endcode\r
@note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
-\r
+#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
-\r
+#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
-\r
+#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
-\r
+#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
-\r
+#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
-\r
+#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
-\r
+#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
-\r
+#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
-\r
+#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
-\r
+#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
-\r
+#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
@endcode\r
@note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
-\r
+#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
-#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
-#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
-#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
-#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
-#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
+#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
+#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
+#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
+#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
+#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
+#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
/// @}\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r
\r
@endcode\r
@note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r
**/\r
-#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
-\r
+#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
\r
/**\r
0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r
@endcode\r
@note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
+#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
///\r
/// [Bits 12:0] See Table 19-36.\r
///\r
- UINT32 EventNum:13;\r
- UINT32 Reserved1:11;\r
+ UINT32 EventNum : 13;\r
+ UINT32 Reserved1 : 11;\r
///\r
/// [Bit 24] UOP Tag Enables replay tagging when set.\r
///\r
- UINT32 UOP:1;\r
+ UINT32 UOP : 1;\r
///\r
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
/// that do not support Intel HyperThreading Technology.\r
///\r
- UINT32 ENABLE_PEBS_MY_THR:1;\r
+ UINT32 ENABLE_PEBS_MY_THR : 1;\r
///\r
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
/// processor when set; disables PEBS when clear (default). See Section\r
/// logical processor. This bit is reserved for IA-32 processors that do\r
/// not support Intel Hyper-Threading Technology.\r
///\r
- UINT32 ENABLE_PEBS_OTH_THR:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 ENABLE_PEBS_OTH_THR : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r
\r
@endcode\r
@note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r
**/\r
-#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
-\r
+#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
\r
/**\r
3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
/// @}\r
\r
-\r
/**\r
3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
record registers on the last branch record stack (6C0H-6CFH). This part of\r
MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
/// @}\r
\r
-\r
/**\r
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r
18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
-\r
+#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
\r
/**\r
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
-\r
+#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
\r
/**\r
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
-\r
+#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
\r
/**\r
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
-\r
+#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
\r
/**\r
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
-\r
+#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
\r
/**\r
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
-\r
+#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
\r
/**\r
3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
-\r
+#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
\r
/**\r
3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
-\r
+#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
\r
/**\r
6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
\r
/**\r
6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
\r
/**\r
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
\r
/**\r
6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
-\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
\r
/**\r
6. Shared. FSB Event Control and Counter Register (R/W).\r
@endcode\r
@note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
**/\r
-#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
\r
#endif\r
@endcode\r
@note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
\r
/**\r
See Section 2.22, "MSRs in Pentium Processors.".\r
@endcode\r
@note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
\r
/**\r
Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
@endcode\r
@note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
+#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
/// Pentium M processor.\r
///\r
- UINT32 DataErrorCheckingEnable:1;\r
+ UINT32 DataErrorCheckingEnable : 1;\r
///\r
/// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
/// the Pentium M processor.\r
///\r
- UINT32 ResponseErrorCheckingEnable:1;\r
+ UINT32 ResponseErrorCheckingEnable : 1;\r
///\r
/// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
/// M processor.\r
///\r
- UINT32 MCERR_DriveEnable:1;\r
+ UINT32 MCERR_DriveEnable : 1;\r
///\r
/// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
/// M processor.\r
///\r
- UINT32 AddressParityEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 AddressParityEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
/// the Pentium M processor.\r
///\r
- UINT32 BINIT_DriverEnable:1;\r
+ UINT32 BINIT_DriverEnable : 1;\r
///\r
/// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 OutputTriStateEnable:1;\r
+ UINT32 OutputTriStateEnable : 1;\r
///\r
/// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
///\r
- UINT32 ExecuteBIST:1;\r
+ UINT32 ExecuteBIST : 1;\r
///\r
/// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
/// Always 0 on the Pentium M processor.\r
///\r
- UINT32 MCERR_ObservationEnabled:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 MCERR_ObservationEnabled : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
/// Always 0 on the Pentium M processor.\r
///\r
- UINT32 BINIT_ObservationEnabled:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 BINIT_ObservationEnabled : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
/// Always 0 on the Pentium M processor.\r
///\r
- UINT32 ResetVector:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 ResetVector : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
/// processor.\r
///\r
- UINT32 APICClusterID:2;\r
+ UINT32 APICClusterID : 2;\r
///\r
/// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
/// 0 on the Pentium M processor.\r
///\r
- UINT32 SystemBusFrequency:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 SystemBusFrequency : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
/// M processor.\r
///\r
- UINT32 SymmetricArbitrationID:2;\r
+ UINT32 SymmetricArbitrationID : 2;\r
///\r
/// [Bits 26:22] Clock Frequency Ratio (R/O).\r
///\r
- UINT32 ClockFrequencyRatio:5;\r
- UINT32 Reserved7:5;\r
- UINT32 Reserved8:32;\r
+ UINT32 ClockFrequencyRatio : 5;\r
+ UINT32 Reserved7 : 5;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
-#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
-#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
-#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
-#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
-#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
-#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
-#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
+#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
+#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
+#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
+#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
+#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
+#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
+#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
+#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
/// @}\r
\r
-\r
/**\r
Reserved.\r
\r
@endcode\r
@note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
-\r
+#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
\r
/**\r
\r
@endcode\r
@note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
+#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
/// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
/// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
/// the cache data bus is always enabled.\r
///\r
- UINT32 ECCCheckEnable:1;\r
- UINT32 Reserved2:2;\r
+ UINT32 ECCCheckEnable : 1;\r
+ UINT32 Reserved2 : 2;\r
///\r
/// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved3:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved3 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved4:8;\r
- UINT32 Reserved5:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved4 : 8;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
\r
\r
@endcode\r
@note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
+#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
/// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
/// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
/// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
///\r
- UINT32 TM_SELECT:1;\r
- UINT32 Reserved2:15;\r
- UINT32 Reserved3:32;\r
+ UINT32 TM_SELECT : 1;\r
+ UINT32 Reserved2 : 15;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
\r
-\r
/**\r
Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:3;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
/// this bit enables the thermal control circuit (TCC) portion of the\r
/// this feature. The bit should not be confused with the on-demand\r
/// thermal control circuit enable bit.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
/// monitoring enabled 0 = Performance monitoring disabled.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
/// processor to indicate a pending break event within the processor 0 =\r
/// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
/// support branch trace storage (BTS) 0 = BTS is supported\r
///\r
- UINT32 FERR:1;\r
+ UINT32 FERR : 1;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (RO)\r
/// 1 = Processor doesn't support branch trace storage (BTS)\r
/// 0 = BTS is supported\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
/// Processor does not support processor event based sampling (PEBS); 0 =\r
/// PEBS is supported. The Pentium M processor does not support PEBS.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved5:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved5 : 3;\r
///\r
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
/// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
/// processor, this bit may be configured to be read-only.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved6:6;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved6 : 6;\r
///\r
/// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
/// disabled. xTPR messages are optional messages that allow the processor\r
/// to inform the chipset of its priority. The default is processor\r
/// specific.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:32;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
to the MSR containing the most recent branch record. See also: -\r
@endcode\r
@note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Debug Control (R/W) Controls how several debug features are used. Bit\r
@endcode\r
@note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
**/\r
-#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
-\r
+#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
\r
/**\r
Last Exception Record To Linear IP (R) This area contains a pointer to the\r
@endcode\r
@note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
-\r
+#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
\r
/**\r
Last Exception Record From Linear IP (R) Contains a pointer to the last\r
@endcode\r
@note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
-\r
+#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
\r
/**\r
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
-\r
+#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
\r
/**\r
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
@endcode\r
@note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
-\r
+#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
\r
/**\r
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
@endcode\r
@note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
-\r
+#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
\r
/**\r
See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
-\r
+#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
\r
/**\r
See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
@endcode\r
@note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
-\r
+#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
\r
/**\r
See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
@endcode\r
@note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
**/\r
-#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
+#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
\r
#endif\r
@endcode\r
@note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
**/\r
-#define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r
-\r
+#define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r
\r
/**\r
See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r
@endcode\r
@note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
**/\r
-#define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r
-\r
+#define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r
\r
/**\r
See Section 17.17, "Time-Stamp Counter.".\r
@endcode\r
@note MSR_PENTIUM_TSC is defined as TSC in SDM.\r
**/\r
-#define MSR_PENTIUM_TSC 0x00000010\r
-\r
+#define MSR_PENTIUM_TSC 0x00000010\r
\r
/**\r
See Section 18.6.9.1, "Control and Event Select Register (CESR).".\r
@endcode\r
@note MSR_PENTIUM_CESR is defined as CESR in SDM.\r
**/\r
-#define MSR_PENTIUM_CESR 0x00000011\r
-\r
+#define MSR_PENTIUM_CESR 0x00000011\r
\r
/**\r
Section 18.6.9.3, "Events Counted.".\r
MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r
@{\r
**/\r
-#define MSR_PENTIUM_CTR0 0x00000012\r
-#define MSR_PENTIUM_CTR1 0x00000013\r
+#define MSR_PENTIUM_CTR0 0x00000012\r
+#define MSR_PENTIUM_CTR1 0x00000013\r
/// @}\r
\r
#endif\r
@endcode\r
@note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
+#define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r
///\r
/// [Bits 31:0] SMI Count (R/O) Count SMIs.\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r
\r
-\r
/**\r
Package. Platform Information Contains power management and other model\r
specific features enumeration. See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
/// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r
/// This field cannot be used to limit package C-state to C3.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:9;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 9;\r
///\r
/// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C6/C7 requests to C3 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r
/// demoted C3.\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r
/// demoted C1.\r
///\r
- UINT32 C1Undemotion:1;\r
- UINT32 Reserved4:3;\r
- UINT32 Reserved5:32;\r
+ UINT32 C1Undemotion : 1;\r
+ UINT32 Reserved4 : 3;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r
/// address redirection is enabled, this is the IO port address reported\r
/// to the OS/software.\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
/// maximum C-State code name to be included when IO read to MWAIT\r
/// is the max C-State to include 001b - C6 is the max C-State to include\r
/// 010b - C7 is the max C-State to include.\r
///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 3;\r
+ UINT32 Reserved1 : 13;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
+#define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r
\r
MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
-#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r
/// @}\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
+#define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
+ UINT32 Reserved1 : 32;\r
///\r
/// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r
/// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r
///\r
- UINT32 CoreVoltage:16;\r
- UINT32 Reserved2:16;\r
+ UINT32 CoreVoltage : 16;\r
+ UINT32 Reserved2 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r
\r
-\r
/**\r
Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r
originally named IA32_THERM_CONTROL MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
+#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r
\r
/**\r
MSR information returned for MSR index\r
/// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r
/// increment.\r
///\r
- UINT32 OnDemandClockModulationDutyCycle:4;\r
+ UINT32 OnDemandClockModulationDutyCycle : 4;\r
///\r
/// [Bit 4] On demand Clock Modulation Enable (R/W).\r
///\r
- UINT32 OnDemandClockModulationEnable:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2:32;\r
+ UINT32 OnDemandClockModulationEnable : 1;\r
+ UINT32 Reserved1 : 27;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved4 : 1;\r
///\r
/// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved5:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved5 : 3;\r
///\r
/// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved6:8;\r
- UINT32 Reserved7:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved6 : 8;\r
+ UINT32 Reserved7 : 2;\r
///\r
/// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved8:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved8 : 3;\r
///\r
/// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved9:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved9 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Unique.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r
/// PROCHOT# will be asserted. The value is degree C.\r
///\r
- UINT32 TemperatureTarget:8;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 TemperatureTarget : 8;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r
/// disables the adjacent cache line prefetcher, which fetches the cache\r
/// line that comprises a cache line pair (128 bytes).\r
///\r
- UINT32 L2AdjacentCacheLinePrefetcherDisable:1;\r
+ UINT32 L2AdjacentCacheLinePrefetcherDisable : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r
/// data cache IP prefetcher, which uses sequential load history (based on\r
/// instruction Pointer of previous loads) to determine whether to\r
/// prefetch additional lines.\r
///\r
- UINT32 DCUIPPrefetcherDisable:1;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 DCUIPPrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
-\r
+#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r
\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W) See Section\r
@endcode\r
@note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
+#define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
that points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r
\r
/**\r
Core. See http://biosbits.org.\r
@endcode\r
@note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
-\r
+#define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r
\r
/**\r
Package. Always 0 (CMCI not supported).\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
-\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r
\r
/**\r
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 61] Thread. Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
Facilities.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r
///\r
- UINT32 PCM0_EN:1;\r
+ UINT32 PCM0_EN : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r
///\r
- UINT32 PCM1_EN:1;\r
+ UINT32 PCM1_EN : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r
///\r
- UINT32 PCM2_EN:1;\r
+ UINT32 PCM2_EN : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r
///\r
- UINT32 PCM3_EN:1;\r
+ UINT32 PCM3_EN : 1;\r
///\r
/// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r
/// 4).\r
///\r
- UINT32 PCM4_EN:1;\r
+ UINT32 PCM4_EN : 1;\r
///\r
/// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r
/// 5).\r
///\r
- UINT32 PCM5_EN:1;\r
+ UINT32 PCM5_EN : 1;\r
///\r
/// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r
/// 6).\r
///\r
- UINT32 PCM6_EN:1;\r
+ UINT32 PCM6_EN : 1;\r
///\r
/// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r
/// 7).\r
///\r
- UINT32 PCM7_EN:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 PCM7_EN : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r
///\r
- UINT32 FIXED_CTR0:1;\r
+ UINT32 FIXED_CTR0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r
///\r
- UINT32 FIXED_CTR1:1;\r
+ UINT32 FIXED_CTR1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r
///\r
- UINT32 FIXED_CTR2:1;\r
- UINT32 Reserved2:29;\r
+ UINT32 FIXED_CTR2 : 1;\r
+ UINT32 Reserved2 : 29;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:26;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
+#define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC0:1;\r
+ UINT32 PEBS_EN_PMC0 : 1;\r
///\r
/// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC1:1;\r
+ UINT32 PEBS_EN_PMC1 : 1;\r
///\r
/// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC2:1;\r
+ UINT32 PEBS_EN_PMC2 : 1;\r
///\r
/// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
///\r
- UINT32 PEBS_EN_PMC3:1;\r
- UINT32 Reserved1:28;\r
+ UINT32 PEBS_EN_PMC3 : 1;\r
+ UINT32 Reserved1 : 28;\r
///\r
/// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
///\r
- UINT32 LL_EN_PMC0:1;\r
+ UINT32 LL_EN_PMC0 : 1;\r
///\r
/// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
///\r
- UINT32 LL_EN_PMC1:1;\r
+ UINT32 LL_EN_PMC1 : 1;\r
///\r
/// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
///\r
- UINT32 LL_EN_PMC2:1;\r
+ UINT32 LL_EN_PMC2 : 1;\r
///\r
/// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
///\r
- UINT32 LL_EN_PMC3:1;\r
- UINT32 Reserved2:27;\r
+ UINT32 LL_EN_PMC3 : 1;\r
+ UINT32 Reserved2 : 27;\r
///\r
/// [Bit 63] Enable Precise Store. (R/W).\r
///\r
- UINT32 PS_EN:1;\r
+ UINT32 PS_EN : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
+#define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r
/// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
/// that will be counted. (R/W).\r
///\r
- UINT32 MinimumThreshold:16;\r
- UINT32 Reserved1:16;\r
- UINT32 Reserved2:32;\r
+ UINT32 MinimumThreshold : 16;\r
+ UINT32 Reserved1 : 16;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
-\r
+#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r
\r
/**\r
Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r
/// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r
/// hardware detected errors.\r
///\r
- UINT32 PCUHardwareError:1;\r
+ UINT32 PCUHardwareError : 1;\r
///\r
/// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r
/// controller detected errors.\r
///\r
- UINT32 PCUControllerError:1;\r
+ UINT32 PCUControllerError : 1;\r
///\r
/// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r
/// firmware detected errors.\r
///\r
- UINT32 PCUFirmwareError:1;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 PCUFirmwareError : 1;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r
\r
-\r
/**\r
Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
\r
**/\r
#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
"RAPL Interfaces.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
-\r
+#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
+#define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C3 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r
budget allocated for the package to exit from C6 to a C0 state, where\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
+#define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C6 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r
\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r
/// @}\r
\r
-\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
record registers on the last branch record stack. This part of the stack\r
MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
-#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r
/// @}\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
/// limit of 7 core active.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
/// limit of 8 core active.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU global control.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Slice 0 select.\r
///\r
- UINT32 PMI_Sel_Slice0:1;\r
+ UINT32 PMI_Sel_Slice0 : 1;\r
///\r
/// [Bit 1] Slice 1 select.\r
///\r
- UINT32 PMI_Sel_Slice1:1;\r
+ UINT32 PMI_Sel_Slice1 : 1;\r
///\r
/// [Bit 2] Slice 2 select.\r
///\r
- UINT32 PMI_Sel_Slice2:1;\r
+ UINT32 PMI_Sel_Slice2 : 1;\r
///\r
/// [Bit 3] Slice 3 select.\r
///\r
- UINT32 PMI_Sel_Slice3:1;\r
+ UINT32 PMI_Sel_Slice3 : 1;\r
///\r
/// [Bit 4] Slice 4 select.\r
///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Slice4 : 1;\r
+ UINT32 Reserved1 : 14;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 47:32] Current count.\r
///\r
- UINT32 CurrentCountHi:16;\r
- UINT32 Reserved:16;\r
+ UINT32 CurrentCountHi : 16;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r
/// [Bits 3:0] Report the number of C-Box units with performance counters,\r
/// including processor cores and processor graphics".\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
+#define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r
/// that should be used to decide if the package should be put into a\r
/// package C7 state.\r
///\r
- UINT32 TimeLimit:10;\r
+ UINT32 TimeLimit : 10;\r
///\r
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
/// unit of the interrupt response time limit. The following time unit\r
/// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r
/// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r
///\r
- UINT32 TimeUnit:3;\r
- UINT32 Reserved1:2;\r
+ UINT32 TimeUnit : 3;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
/// valid and can be used by the processor for package C-sate management.\r
///\r
- UINT32 Valid:1;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 Valid : 1;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
-\r
+#define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r
\r
/**\r
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r
\r
/**\r
Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r
\r
/**\r
Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
-\r
+#define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r
\r
/**\r
Package. Uncore C-Box 0, counter n event select MSR.\r
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box n, unit status for counter 0-3.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 0, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 1, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 1, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 2, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 2, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 3, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 3, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 4, counter n event select MSR.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-Box 4, performance counter n.\r
\r
MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r
@{\r
**/\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
-#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r
/// @}\r
\r
-\r
/**\r
Package. MC Bank Error Configuration (R/W).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
+#define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r
/// to log additional info in bits 36:32.\r
///\r
- UINT32 MemErrorLogEnable:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 MemErrorLogEnable : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
+#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r
\r
/**\r
MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r
/// counting logic for specific events requiring additional configuration,\r
/// see Table 19-17.\r
///\r
- UINT32 ENABLE_PEBS_NUM_ALT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 ENABLE_PEBS_NUM_ALT : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r
\r
-\r
/**\r
Package. Package RAPL Perf Status (R/O).\r
\r
@endcode\r
@note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r
\r
/**\r
Package. Uncore U-box UCLK fixed counter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r
\r
/**\r
Package. Uncore U-box perfmon event select for U-box counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r
\r
/**\r
Package. Uncore U-box perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r
\r
/**\r
Package. Uncore U-box perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
-\r
+#define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r
\r
/**\r
Package. Uncore PCU perfmon for PCU-box-wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r
\r
/**\r
Package. Uncore PCU perfmon event select for PCU counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r
\r
/**\r
Package. Uncore PCU perfmon box-wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r
\r
/**\r
Package. Uncore PCU perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r
\r
/**\r
Package. Uncore PCU perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r
\r
/**\r
Package. Uncore PCU perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r
\r
/**\r
Package. Uncore PCU perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
-\r
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r
\r
/**\r
Package. Uncore C-box 0 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r
\r
/**\r
Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r
\r
/**\r
Package. Uncore C-box 0 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r
\r
/**\r
Package. Uncore C-box 0 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
-\r
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r
\r
/**\r
Package. Uncore C-box 1 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r
\r
/**\r
Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r
\r
/**\r
Package. Uncore C-box 1 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r
\r
/**\r
Package. Uncore C-box 1 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
-\r
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r
\r
/**\r
Package. Uncore C-box 2 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r
\r
/**\r
Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r
\r
/**\r
Package. Uncore C-box 2 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r
\r
/**\r
Package. Uncore C-box 2 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
-\r
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r
\r
/**\r
Package. Uncore C-box 3 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r
\r
/**\r
Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r
\r
/**\r
Package. Uncore C-box 3 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r
\r
/**\r
Package. Uncore C-box 3 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
-\r
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r
\r
/**\r
Package. Uncore C-box 4 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r
\r
/**\r
Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r
\r
/**\r
Package. Uncore C-box 4 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r
\r
/**\r
Package. Uncore C-box 4 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
-\r
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r
\r
/**\r
Package. Uncore C-box 5 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r
\r
/**\r
Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r
\r
/**\r
Package. Uncore C-box 5 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r
\r
/**\r
Package. Uncore C-box 5 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
-\r
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r
\r
/**\r
Package. Uncore C-box 6 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r
\r
/**\r
Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r
\r
/**\r
Package. Uncore C-box 6 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r
\r
/**\r
Package. Uncore C-box 6 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
-\r
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r
\r
/**\r
Package. Uncore C-box 7 perfmon local box wide control.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r
\r
/**\r
Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r
\r
/**\r
Package. Uncore C-box 7 perfmon box wide filter.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 0.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 1.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 2.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
-\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r
\r
/**\r
Package. Uncore C-box 7 perfmon counter 3.\r
@endcode\r
@note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
-#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r
\r
#endif\r
@endcode\r
@note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
-#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
+#define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
///\r
- UINT32 MaximumQualifiedRatio:5;\r
- UINT32 Reserved2:19;\r
- UINT32 Reserved3:18;\r
+ UINT32 MaximumQualifiedRatio : 5;\r
+ UINT32 Reserved2 : 19;\r
+ UINT32 Reserved3 : 18;\r
///\r
/// [Bits 52:50] See Table 2-2.\r
///\r
- UINT32 PlatformId:3;\r
- UINT32 Reserved4:11;\r
+ UINT32 PlatformId : 3;\r
+ UINT32 Reserved4 : 11;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r
\r
-\r
/**\r
Module. Processor Hard Power-On Configuration (R/W) Writes ignored.\r
\r
@endcode\r
@note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
-#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
+#define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:32;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r
\r
-\r
/**\r
Core. SMI Counter (R/O).\r
\r
@endcode\r
@note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
+#define MSR_SILVERMONT_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r
/// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r
/// RESET.\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_SMI_COUNT_REGISTER;\r
\r
-\r
/**\r
Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.\r
\r
@endcode\r
@note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL\r
///\r
/// [Bit 0] Lock (R/WL).\r
///\r
- UINT32 Lock:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Lock : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Enable VMX outside SMX operation (R/WL).\r
///\r
- UINT32 EnableVmxOutsideSmx:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 EnableVmxOutsideSmx : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The From_IP part of the\r
MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
-#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
-#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
-#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
-#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
-#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
-#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
-#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r
/// @}\r
\r
-\r
/**\r
Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
record registers on the last branch record stack. The To_IP part of the\r
MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
-#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
-#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
-#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
-#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
-#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
-#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
-#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r
/// @}\r
\r
-\r
/**\r
Module. Scalable Bus Speed(RO) This field indicates the intended scalable\r
bus clock speed for processors based on Silvermont microarchitecture:.\r
@endcode\r
@note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
-#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
+#define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r
/// 0111B: 088.9 MHz\r
/// 1000B: 087.5 MHz\r
///\r
- UINT32 ScalableBusSpeed:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 ScalableBusSpeed : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
\r
-\r
/**\r
Package. Platform Information: Contains power management and other model\r
specific features enumeration. See http://biosbits.org.\r
AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
+#define MSR_SILVERMONT_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
/// of the maximum frequency that does not require turbo. Frequency =\r
/// ratio * Scalable Bus Frequency.\r
///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:16;\r
- UINT32 Reserved3:32;\r
+ UINT32 MaximumNon_TurboRatio : 8;\r
+ UINT32 Reserved2 : 16;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r
/// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
/// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r
/// IO_read instructions sent to IO register specified by\r
/// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r
/// until next reset.\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved3:16;\r
- UINT32 Reserved4:32;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved3 : 16;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Power Management IO Redirection in C-state (R/W) See\r
http://biosbits.org.\r
@endcode\r
@note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r
/// address redirection is enabled, this is the IO port address reported\r
/// to the OS/software.\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r
/// maximum C-State code name to be included when IO read to MWAIT\r
/// is the max C-State to include 110b - C6 is the max C-State to include\r
/// 111b - C7 is the max C-State to include.\r
///\r
- UINT32 CStateRange:3;\r
- UINT32 Reserved1:13;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 3;\r
+ UINT32 Reserved1 : 13;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Module.\r
\r
@endcode\r
@note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
-#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
+#define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r
/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
/// Indicates if the L2 is hardware-disabled.\r
///\r
- UINT32 L2HardwareEnabled:1;\r
- UINT32 Reserved1:7;\r
+ UINT32 L2HardwareEnabled : 1;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r
/// Disabled (default) Until this bit is set the processor will not\r
/// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
///\r
- UINT32 L2Enabled:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 L2Enabled : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
///\r
- UINT32 L2NotPresent:1;\r
- UINT32 Reserved3:8;\r
- UINT32 Reserved4:32;\r
+ UINT32 L2NotPresent : 1;\r
+ UINT32 Reserved3 : 8;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
+#define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See\r
/// Table 2-2. Default value is 0.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 2-2.\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
/// Table 2-2.\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors\r
/// that support Intel Turbo Boost Technology, the turbo mode feature is\r
/// in the processor. If power-on default value is 0, turbo mode is not\r
/// available.\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r
/// PROCHOT# activation temperature in degree C, The effective temperature\r
/// for thermal throttling or PROCHOT# activation is "Temperature Target"\r
/// + "Target Offset".\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r
/// adjust the throttling and PROCHOT# activation temperature from the\r
/// default target specified in TEMPERATURE_TARGET (bits 23:16).\r
///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
+ UINT32 TargetOffset : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL\r
/// L2 hardware prefetcher, which fetches additional lines of code or data\r
/// into the L2 cache.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r
/// the L1 data cache prefetcher, which fetches the next cache line into\r
/// L1 data cache.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
- UINT32 Reserved2:29;\r
- UINT32 Reserved3:32;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved2 : 29;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Module. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode (RW).\r
@endcode\r
@note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r
/// limit of 7 core active.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r
/// limit of 8 core active.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
"Filtering of Last Branch Records.".\r
@endcode\r
@note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_LBR_SELECT_REGISTER;\r
\r
-\r
/**\r
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r
points to the MSR containing the most recent branch record. See\r
@endcode\r
@note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r
@endcode\r
@note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Core. Last Exception Record To Linear IP (R) This area contains a pointer\r
@endcode\r
@note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r
\r
/**\r
Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r
@endcode\r
@note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
+#define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r
///\r
/// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
@endcode\r
@note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
-\r
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
@endcode\r
@note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
/**\r
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
@endcode\r
@note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
-#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
-\r
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.\r
**/\r
-#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
-\r
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r
@endcode\r
@note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r
/// represented by bits 3:0. Default value is 0101b, indicating power unit\r
/// is in 32 milliWatts increment.\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Energy Status Units. Energy related information (in\r
/// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 00101b,\r
/// indicating energy unit is in 32 microJoules increment.\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r
/// one second.\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. PKG RAPL Power Limit Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
+#define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r
/// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.\r
///\r
- UINT32 Limit:15;\r
+ UINT32 Limit : 15;\r
///\r
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r
/// RAPL Domain.".\r
///\r
- UINT32 Enable:1;\r
+ UINT32 Enable : 1;\r
///\r
/// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r
/// "Package RAPL Domain.".\r
///\r
- UINT32 ClampingLimit:1;\r
+ UINT32 ClampingLimit : 1;\r
///\r
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r
/// If 0 is specified in bits [23:17], defaults to 1 second window.\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
- UINT32 Reserved2:32;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved1 : 8;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r
and MSR_RAPL_POWER_UNIT in Table 2-8.\r
@endcode\r
@note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."\r
@endcode\r
@note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r
@endcode\r
@note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
-\r
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r
\r
/**\r
Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r
@endcode\r
@note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.\r
**/\r
-#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
-\r
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r
\r
/**\r
Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r
@endcode\r
@note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.\r
**/\r
-#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
-\r
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r
\r
/**\r
Package. PKG RAPL Parameter (R/0).\r
@endcode\r
@note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
+#define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r
/// The unit of this field is specified by the "Power Units" field of\r
/// MSR_RAPL_POWER_UNIT.\r
///\r
- UINT32 ThermalSpecPower:15;\r
- UINT32 Reserved1:17;\r
- UINT32 Reserved2:32;\r
+ UINT32 ThermalSpecPower : 15;\r
+ UINT32 Reserved1 : 17;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r
\r
-\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W).\r
\r
@endcode\r
@note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
+#define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r
/// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
/// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.\r
///\r
- UINT32 Limit:15;\r
+ UINT32 Limit : 15;\r
///\r
/// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r
/// RAPL Domains.".\r
///\r
- UINT32 Enable:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 Enable : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r
/// duration over which the average power must remain below\r
/// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r
/// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved2:8;\r
- UINT32 Reserved3:32;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved2 : 8;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r
\r
#endif\r
@endcode\r
@note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
- UINT32 Reserved:32;\r
+ UINT32 Maximum4C : 8;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
that points to the MSR containing the most recent branch record.\r
@endcode\r
@note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Core. Power Control Register See http://biosbits.org.\r
AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
+#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
/// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
/// point when all execution cores enter MWAIT (C1).\r
///\r
- UINT32 C1EEnable:1;\r
- UINT32 Reserved2:17;\r
+ UINT32 C1EEnable : 1;\r
+ UINT32 Reserved2 : 17;\r
///\r
/// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
/// disables the Race to Halt optimization and avoids this optimization\r
/// optimization. Default value is 1 for processors that do not support\r
/// Race to Halt optimization.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
/// disables the P-States energy efficiency optimization. Default value is\r
/// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
/// desired or OS maximize to the OS minimize performance setting.\r
///\r
- UINT32 DisableEnergyEfficiencyOptimization:1;\r
- UINT32 Reserved3:11;\r
- UINT32 Reserved4:32;\r
+ UINT32 DisableEnergyEfficiencyOptimization : 1;\r
+ UINT32 Reserved3 : 11;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
\r
//\r
// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
+#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
+\r
/**\r
Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
@endcode\r
@note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
+#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
\r
//\r
// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r
//\r
-#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
-\r
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
@endcode\r
@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Thread. Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
Version 4.".\r
@endcode\r
@note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
**/\r
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
\r
/**\r
MSR information returned for MSR index\r
///\r
/// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. Set 1 to clear ASCI.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
///\r
/// [Bit 63] Thread. Set 1 to clear CondChgd.\r
///\r
- UINT32 CondChgd:1;\r
+ UINT32 CondChgd : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
\r
-\r
/**\r
See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
Version 4.".\r
///\r
/// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
///\r
- UINT32 Ovf_PMC0:1;\r
+ UINT32 Ovf_PMC0 : 1;\r
///\r
/// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
///\r
- UINT32 Ovf_PMC1:1;\r
+ UINT32 Ovf_PMC1 : 1;\r
///\r
/// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
///\r
- UINT32 Ovf_PMC2:1;\r
+ UINT32 Ovf_PMC2 : 1;\r
///\r
/// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
///\r
- UINT32 Ovf_PMC3:1;\r
+ UINT32 Ovf_PMC3 : 1;\r
///\r
/// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
///\r
- UINT32 Ovf_PMC4:1;\r
+ UINT32 Ovf_PMC4 : 1;\r
///\r
/// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
///\r
- UINT32 Ovf_PMC5:1;\r
+ UINT32 Ovf_PMC5 : 1;\r
///\r
/// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
///\r
- UINT32 Ovf_PMC6:1;\r
+ UINT32 Ovf_PMC6 : 1;\r
///\r
/// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
///\r
- UINT32 Ovf_PMC7:1;\r
- UINT32 Reserved1:24;\r
+ UINT32 Ovf_PMC7 : 1;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
///\r
- UINT32 Ovf_FixedCtr0:1;\r
+ UINT32 Ovf_FixedCtr0 : 1;\r
///\r
/// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
///\r
- UINT32 Ovf_FixedCtr1:1;\r
+ UINT32 Ovf_FixedCtr1 : 1;\r
///\r
/// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
///\r
- UINT32 Ovf_FixedCtr2:1;\r
- UINT32 Reserved2:20;\r
+ UINT32 Ovf_FixedCtr2 : 1;\r
+ UINT32 Reserved2 : 20;\r
///\r
/// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
///\r
- UINT32 Trace_ToPA_PMI:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 Trace_ToPA_PMI : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
///\r
- UINT32 LBR_Frz:1;\r
+ UINT32 LBR_Frz : 1;\r
///\r
/// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
///\r
- UINT32 CTR_Frz:1;\r
+ UINT32 CTR_Frz : 1;\r
///\r
/// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
///\r
- UINT32 ASCI:1;\r
+ UINT32 ASCI : 1;\r
///\r
/// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
///\r
- UINT32 Ovf_Uncore:1;\r
+ UINT32 Ovf_Uncore : 1;\r
///\r
/// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
///\r
- UINT32 Ovf_BufDSSAVE:1;\r
- UINT32 Reserved4:1;\r
+ UINT32 Ovf_BufDSSAVE : 1;\r
+ UINT32 Reserved4 : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
\r
-\r
/**\r
Thread. FrontEnd Precise Event Condition Select (R/W).\r
\r
@endcode\r
@note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
**/\r
-#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
+#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
///\r
/// [Bits 2:0] Event Code Select.\r
///\r
- UINT32 EventCodeSelect:3;\r
- UINT32 Reserved1:1;\r
+ UINT32 EventCodeSelect : 3;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 4] Event Code Select High.\r
///\r
- UINT32 EventCodeSelectHigh:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 EventCodeSelectHigh : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
///\r
- UINT32 IDQ_Bubble_Length:12;\r
+ UINT32 IDQ_Bubble_Length : 12;\r
///\r
/// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
///\r
- UINT32 IDQ_Bubble_Width:3;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 IDQ_Bubble_Width : 3;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
\r
-\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
Domains.".\r
@endcode\r
@note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
@endcode\r
@note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
+#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
/// delivery means. The energy units are specified in the\r
/// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
///\r
- UINT32 TotalEnergy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 TotalEnergy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
\r
-\r
/**\r
Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
scalability. See Section 14.4.5.1.\r
@endcode\r
@note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
**/\r
-#define MSR_SKYLAKE_PPERF 0x0000064E\r
-\r
+#define MSR_SKYLAKE_PPERF 0x0000064E\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
+#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
/// operating system request due to assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
/// reduced below the operating system request due to residency state\r
/// regulation limit.\r
///\r
- UINT32 ResidencyStateRegulationStatus:1;\r
+ UINT32 ResidencyStateRegulationStatus : 1;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Running Average\r
/// Thermal Limit (RATL).\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from a\r
/// processor Voltage Regulator (VR).\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
/// reduced below the operating system request due to VR thermal design\r
/// current limit.\r
///\r
- UINT32 VRThermDesignCurrentStatus:1;\r
+ UINT32 VRThermDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
/// operating system request due to electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced below the operating system request due to\r
/// package/platform-level power limiting PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced below the operating system request due to\r
/// package/platform-level power limiting PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
/// below the operating system request due to multi-core turbo limits.\r
///\r
- UINT32 MaxTurboLimitStatus:1;\r
+ UINT32 MaxTurboLimitStatus : 1;\r
///\r
/// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
/// is reduced below the operating system request due to Turbo transition\r
/// attenuation. This prevents performance degradation due to frequent\r
/// operating ratio changes.\r
///\r
- UINT32 TurboTransitionAttenuationStatus:1;\r
- UINT32 Reserved3:2;\r
+ UINT32 TurboTransitionAttenuationStatus : 1;\r
+ UINT32 Reserved3 : 2;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 20] Residency State Regulation Log When set, indicates that the\r
/// Residency State Regulation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 ResidencyStateRegulationLog:1;\r
+ UINT32 ResidencyStateRegulationLog : 1;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR TDC Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package or Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
/// Limit Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MaxTurboLimitLog:1;\r
+ UINT32 MaxTurboLimitLog : 1;\r
///\r
/// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
/// Turbo Transition Attenuation Status bit has asserted since the log bit\r
/// was last cleared. This log bit will remain set until cleared by\r
/// software writing 0.\r
///\r
- UINT32 TurboTransitionAttenuationLog:1;\r
- UINT32 Reserved6:2;\r
- UINT32 Reserved7:32;\r
+ UINT32 TurboTransitionAttenuationLog : 1;\r
+ UINT32 Reserved6 : 2;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. HDC Configuration (R/W)..\r
\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
+#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
/// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
/// MSR_PKG_HDC_DEEP_RESIDENCY.\r
///\r
- UINT32 PKG_Cx_Monitor:3;\r
- UINT32 Reserved1:29;\r
- UINT32 Reserved2:32;\r
+ UINT32 PKG_Cx_Monitor : 3;\r
+ UINT32 Reserved1 : 29;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
\r
-\r
/**\r
Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
\r
@endcode\r
@note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
-\r
+#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
\r
/**\r
Package. Accumulate the cycles the package was in C2 state and at least one\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
-\r
+#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
\r
/**\r
Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
@endcode\r
@note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
**/\r
-#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
-\r
+#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
\r
/**\r
Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
@endcode\r
@note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
-\r
+#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
\r
/**\r
Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
@endcode\r
@note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
-\r
+#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
\r
/**\r
Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
@endcode\r
@note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
-\r
+#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
\r
/**\r
Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
@endcode\r
@note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
-\r
+#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
\r
/**\r
Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
@endcode\r
@note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
+#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
/// Power (TDP) and varies with product skus. The unit is specified in\r
/// MSR_RAPLPOWER_UNIT.\r
///\r
- UINT32 PlatformPowerLimit1:15;\r
+ UINT32 PlatformPowerLimit1 : 15;\r
///\r
/// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
/// processor to apply control policy such that the platform power does\r
/// not exceed Platform Power limit #1 over the time window specified by\r
/// Power Limit #1 Time Window.\r
///\r
- UINT32 EnablePlatformPowerLimit1:1;\r
+ UINT32 EnablePlatformPowerLimit1 : 1;\r
///\r
/// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
/// processor to go below the OS requested P states in order to maintain\r
/// the power below specified Platform Power Limit #1 value. This bit is\r
/// writeable only when CPUID (EAX=6):EAX[4] is set.\r
///\r
- UINT32 PlatformClampingLimitation1:1;\r
+ UINT32 PlatformClampingLimitation1 : 1;\r
///\r
/// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
/// duration of the time window over which Platform Power Limit 1 value\r
/// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
/// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
///\r
- UINT32 Time:7;\r
- UINT32 Reserved1:8;\r
+ UINT32 Time : 7;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
/// the platform must not exceed over the Short Duration time window\r
/// chosen by the processor. The recommended default value is 1.25 times\r
/// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
///\r
- UINT32 PlatformPowerLimit2:15;\r
+ UINT32 PlatformPowerLimit2 : 15;\r
///\r
/// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
/// processor to apply control policy such that the platform power does\r
/// not exceed Platform Power limit #2 over the Short Duration time window.\r
///\r
- UINT32 EnablePlatformPowerLimit2:1;\r
+ UINT32 EnablePlatformPowerLimit2 : 1;\r
///\r
/// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
/// processor to go below the OS requested P states in order to maintain\r
/// the power below specified Platform Power Limit #2 value.\r
///\r
- UINT32 PlatformClampingLimitation2:1;\r
- UINT32 Reserved2:14;\r
+ UINT32 PlatformClampingLimitation2 : 1;\r
+ UINT32 Reserved2 : 14;\r
///\r
/// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
/// until system RESET.\r
///\r
- UINT32 Lock:1;\r
+ UINT32 Lock : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
branch record registers on the last branch record stack. This part of the\r
MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
-#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
-#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
-#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
-#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
-#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
-#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
-#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
-#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
-#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
-#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
-#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
-#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
-#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
-#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
-#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
+#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
+#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
+#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
+#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
+#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
+#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
+#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
+#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
+#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
+#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
+#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
+#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
+#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
+#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
+#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
+#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
/// @}\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
(frequency refers to processor graphics frequency).\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
/// assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
/// thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced due to running average thermal limit.\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
/// to a thermal alert from a processor Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
/// reduced due to VR TDC limit.\r
///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
+ UINT32 VRThermalDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
/// electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced due to package/platform-level power limiting\r
/// PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced due to package/platform-level power limiting\r
/// PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
+ UINT32 PL2Status : 1;\r
///\r
/// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
/// graphics frequency is operating below target frequency.\r
///\r
- UINT32 InefficientOperationStatus:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 InefficientOperationStatus : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR Therm Alert Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL2 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
+ UINT32 PL2Log : 1;\r
///\r
/// [Bit 28] Inefficient Operation Log When set, indicates that the\r
/// Inefficient Operation Status bit has asserted since the log bit was\r
/// last cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 InefficientOperationLog:1;\r
- UINT32 Reserved6:3;\r
- UINT32 Reserved7:32;\r
+ UINT32 InefficientOperationLog : 1;\r
+ UINT32 Reserved6 : 3;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
(frequency refers to ring interconnect in the uncore).\r
@endcode\r
@note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
+#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
/// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
/// assertion of external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
/// thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:3;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 3;\r
///\r
/// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
/// is reduced due to running average thermal limit.\r
///\r
- UINT32 RunningAverageThermalLimitStatus:1;\r
+ UINT32 RunningAverageThermalLimitStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
/// to a thermal alert from a processor Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
///\r
/// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
/// reduced due to VR TDC limit.\r
///\r
- UINT32 VRThermalDesignCurrentStatus:1;\r
+ UINT32 VRThermalDesignCurrentStatus : 1;\r
///\r
/// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
/// electrical or other constraints.\r
///\r
- UINT32 OtherStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 OtherStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
/// set, frequency is reduced due to package/Platform-level power limiting\r
/// PL1.\r
///\r
- UINT32 PL1Status:1;\r
+ UINT32 PL1Status : 1;\r
///\r
/// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
/// set, frequency is reduced due to package/Platform-level power limiting\r
/// PL2/PL3.\r
///\r
- UINT32 PL2Status:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PL2Status : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 ThermalLog : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
/// the RATL Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 RunningAverageThermalLimitLog:1;\r
+ UINT32 RunningAverageThermalLimitLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
+ UINT32 VRThermAlertLog : 1;\r
///\r
/// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
/// VR Therm Alert Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 VRThermalDesignCurrentLog:1;\r
+ UINT32 VRThermalDesignCurrentLog : 1;\r
///\r
/// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
/// asserted since the log bit was last cleared. This log bit will remain\r
/// set until cleared by software writing 0.\r
///\r
- UINT32 OtherLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 OtherLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL1 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL1Log:1;\r
+ UINT32 PL1Log : 1;\r
///\r
/// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
/// indicates that the Package/Platform Level PL2 Power Limiting Status\r
/// bit has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PL2Log:1;\r
- UINT32 Reserved6:4;\r
- UINT32 Reserved7:32;\r
+ UINT32 PL2Log : 1;\r
+ UINT32 Reserved6 : 4;\r
+ UINT32 Reserved7 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
record registers on the last branch record stack. This part of the stack\r
MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
-#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
-#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
-#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
-#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
-#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
-#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
-#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
-#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
-#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
-#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
-#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
-#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
-#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
-#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
-#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
+#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
+#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
+#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
+#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
+#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
+#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
+#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
+#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
+#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
+#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
+#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
+#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
+#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
+#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
+#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
+#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
/// @}\r
\r
-\r
/**\r
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
of last branch record registers on the last branch record stack. This part\r
MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
@{\r
**/\r
-#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
-#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
-#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
-#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
-#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
-#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
-#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
-#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
-#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
-#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
-#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
-#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
-#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
-#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
-#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
-#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
-#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
-#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
-#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
-#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
-#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
-#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
-#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
-#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
-#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
-#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
-#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
-#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
-#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
-#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
-#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
-#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
+#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
+#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
+#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
+#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
+#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
+#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
+#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
+#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
+#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
+#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
+#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
+#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
+#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
+#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
+#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
+#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
+#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
+#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
+#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
+#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
+#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
+#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
+#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
+#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
+#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
+#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
+#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
+#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
+#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
+#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
+#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
+#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
/// @}\r
\r
-\r
/**\r
Package. Uncore fixed counter control (R/W).\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:20;\r
+ UINT32 Reserved1 : 20;\r
///\r
/// [Bit 20] Enable overflow propagation.\r
///\r
- UINT32 EnableOverflow:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 EnableOverflow : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 22] Enable counting.\r
///\r
- UINT32 EnableCounting:1;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved4:32;\r
+ UINT32 EnableCounting : 1;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore fixed counter.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
///\r
/// [Bits 31:0] Current count.\r
///\r
- UINT32 CurrentCount:32;\r
+ UINT32 CurrentCount : 32;\r
///\r
/// [Bits 43:32] Current count.\r
///\r
- UINT32 CurrentCountHi:12;\r
- UINT32 Reserved:20;\r
+ UINT32 CurrentCountHi : 12;\r
+ UINT32 Reserved : 20;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
\r
-\r
/**\r
Package. Uncore C-Box configuration information (R/O).\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
+#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
/// [Bits 3:0] Specifies the number of C-Box units with programmable\r
/// counters (including processor cores and processor graphics),.\r
///\r
- UINT32 CBox:4;\r
- UINT32 Reserved1:28;\r
- UINT32 Reserved2:32;\r
+ UINT32 CBox : 4;\r
+ UINT32 Reserved1 : 28;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. Uncore Arb unit, performance counter 0.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
\r
/**\r
Package. Uncore Arb unit, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
\r
/**\r
Package. Uncore Arb unit, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
\r
/**\r
Package. Uncore Arb unit, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
-\r
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
\r
/**\r
Package. Uncore C-Box 0, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
\r
/**\r
Package. Uncore C-Box 0, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
\r
/**\r
Package. Uncore C-Box 0, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
\r
/**\r
Package. Uncore C-Box 1, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
\r
/**\r
Package. Uncore C-Box 1, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
\r
/**\r
Package. Uncore C-Box 1, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
\r
/**\r
Package. Uncore C-Box 2, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
\r
/**\r
Package. Uncore C-Box 2, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
\r
/**\r
Package. Uncore C-Box 2, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
\r
/**\r
Package. Uncore C-Box 3, counter 0 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
\r
/**\r
Package. Uncore C-Box 3, counter 1 event select MSR.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 0.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
\r
/**\r
Package. Uncore C-Box 3, performance counter 1.\r
@endcode\r
@note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
-\r
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
\r
/**\r
Package. Uncore PMU global control.\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
///\r
/// [Bit 0] Slice 0 select.\r
///\r
- UINT32 PMI_Sel_Slice0:1;\r
+ UINT32 PMI_Sel_Slice0 : 1;\r
///\r
/// [Bit 1] Slice 1 select.\r
///\r
- UINT32 PMI_Sel_Slice1:1;\r
+ UINT32 PMI_Sel_Slice1 : 1;\r
///\r
/// [Bit 2] Slice 2 select.\r
///\r
- UINT32 PMI_Sel_Slice2:1;\r
+ UINT32 PMI_Sel_Slice2 : 1;\r
///\r
/// [Bit 3] Slice 3 select.\r
///\r
- UINT32 PMI_Sel_Slice3:1;\r
+ UINT32 PMI_Sel_Slice3 : 1;\r
///\r
/// [Bit 4] Slice 4select.\r
///\r
- UINT32 PMI_Sel_Slice4:1;\r
- UINT32 Reserved1:14;\r
- UINT32 Reserved2:10;\r
+ UINT32 PMI_Sel_Slice4 : 1;\r
+ UINT32 Reserved1 : 14;\r
+ UINT32 Reserved2 : 10;\r
///\r
/// [Bit 29] Enable all uncore counters.\r
///\r
- UINT32 EN:1;\r
+ UINT32 EN : 1;\r
///\r
/// [Bit 30] Enable wake on PMI.\r
///\r
- UINT32 WakePMI:1;\r
+ UINT32 WakePMI : 1;\r
///\r
/// [Bit 31] Enable Freezing counter when overflow.\r
///\r
- UINT32 FREEZE:1;\r
- UINT32 Reserved3:32;\r
+ UINT32 FREEZE : 1;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
\r
-\r
/**\r
Package. Uncore PMU main status.\r
\r
@endcode\r
@note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
///\r
/// [Bit 0] Fixed counter overflowed.\r
///\r
- UINT32 Fixed:1;\r
+ UINT32 Fixed : 1;\r
///\r
/// [Bit 1] An ARB counter overflowed.\r
///\r
- UINT32 ARB:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 ARB : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 3] A CBox counter overflowed (on any slice).\r
///\r
- UINT32 CBox:1;\r
- UINT32 Reserved2:28;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBox : 1;\r
+ UINT32 Reserved2 : 28;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. NPK Address Used by AET Messages (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
\r
/**\r
MSR information returned for MSR index\r
/// bit has to be set in order for the AET packets to be directed to NPK\r
/// MMIO.\r
///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved:17;\r
+ UINT32 Fix_Me_1 : 1;\r
+ UINT32 Reserved : 17;\r
///\r
/// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
///\r
- UINT32 ACPIBAR_BASE_ADDRESS:14;\r
+ UINT32 ACPIBAR_BASE_ADDRESS : 14;\r
///\r
/// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
///\r
- UINT32 Fix_Me_2:32;\r
+ UINT32 Fix_Me_2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
\r
-\r
/**\r
Core. Processor Reserved Memory Range Register - Physical Base Control\r
Register (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
///\r
/// [Bits 2:0] MemType PRMRR BASE MemType.\r
///\r
- UINT32 MemTypePRMRRBASEMemType:3;\r
- UINT32 Reserved1:9;\r
+ UINT32 MemTypePRMRRBASEMemType : 3;\r
+ UINT32 Reserved1 : 9;\r
///\r
/// [Bits 31:12] Base PRMRR Base Address.\r
///\r
- UINT32 BasePRMRRBaseAddress:20;\r
+ UINT32 BasePRMRRBaseAddress : 20;\r
///\r
/// [Bits 45:32] Base PRMRR Base Address.\r
///\r
- UINT32 Fix_Me_1:14;\r
- UINT32 Reserved2:18;\r
+ UINT32 Fix_Me_1 : 14;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
\r
-\r
/**\r
Core. Processor Reserved Memory Range Register - Physical Mask Control\r
Register (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:10;\r
+ UINT32 Reserved1 : 10;\r
///\r
/// [Bit 10] Lock Lock bit for the PRMRR.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 11] VLD Enable bit for the PRMRR.\r
///\r
- UINT32 VLD:1;\r
+ UINT32 VLD : 1;\r
///\r
/// [Bits 31:12] Mask PRMRR MASK bits.\r
///\r
- UINT32 Fix_Me_2:20;\r
+ UINT32 Fix_Me_2 : 20;\r
///\r
/// [Bits 45:32] Mask PRMRR MASK bits.\r
///\r
- UINT32 Fix_Me_3:14;\r
- UINT32 Reserved2:18;\r
+ UINT32 Fix_Me_3 : 14;\r
+ UINT32 Reserved2 : 18;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
\r
-\r
/**\r
Core. Valid PRMRR Configurations (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
///\r
/// [Bit 0] 1M supported MEE size.\r
///\r
- UINT32 Fix_Me_1:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 Fix_Me_1 : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 5] 32M supported MEE size.\r
///\r
- UINT32 Fix_Me_2:1;\r
+ UINT32 Fix_Me_2 : 1;\r
///\r
/// [Bit 6] 64M supported MEE size.\r
///\r
- UINT32 Fix_Me_3:1;\r
+ UINT32 Fix_Me_3 : 1;\r
///\r
/// [Bit 7] 128M supported MEE size.\r
///\r
- UINT32 Fix_Me_4:1;\r
- UINT32 Reserved2:24;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_4 : 1;\r
+ UINT32 Reserved2 : 24;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
\r
-\r
/**\r
Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
unauthorized reads and writes. Any IO access to this range is aborted. This\r
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:12;\r
+ UINT32 Reserved1 : 12;\r
///\r
/// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
/// base address memory range which is allocated to PRMRR memory.\r
///\r
- UINT32 Fix_Me_1:20;\r
+ UINT32 Fix_Me_1 : 20;\r
///\r
/// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
/// base address memory range which is allocated to PRMRR memory.\r
///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:25;\r
+ UINT32 Fix_Me_2 : 7;\r
+ UINT32 Reserved2 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
\r
-\r
/**\r
Package. (R/W) This register controls the size of the PRMRR range by\r
indicating which address bits must match the PRMRR base register value.\r
AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:10;\r
+ UINT32 Reserved1 : 10;\r
///\r
/// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
/// register, including itself.\r
///\r
- UINT32 Fix_Me_1:1;\r
+ UINT32 Fix_Me_1 : 1;\r
///\r
/// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
/// valid.\r
///\r
- UINT32 Fix_Me_2:1;\r
- UINT32 Reserved2:20;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_2 : 1;\r
+ UINT32 Reserved2 : 20;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
+#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
/// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 Fix_Me_1:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 Fix_Me_1 : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 Fix_Me_2:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 Fix_Me_2 : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Branch Monitoring Global Control (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
+#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
///\r
/// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
///\r
- UINT32 EnMonitoring:1;\r
+ UINT32 EnMonitoring : 1;\r
///\r
/// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
/// trip. The branch monitoring event handler is signaled via the existing\r
/// PMI signaling mechanism as programmed from the corresponding local\r
/// APIC LVT entry.\r
///\r
- UINT32 EnExcept:1;\r
+ UINT32 EnExcept : 1;\r
///\r
/// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
/// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
/// triggering condition occurs and this bit is enabled.\r
///\r
- UINT32 EnLBRFrz:1;\r
+ UINT32 EnLBRFrz : 1;\r
///\r
/// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
/// triggering and LBR freeze actions are disabled when operating at VMX\r
/// non-root operation.\r
///\r
- UINT32 DisableInGuest:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 DisableInGuest : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
/// 1023 are supported. Once the Window counter reaches the WindowSize\r
/// count both the Window Counter and all Branch Monitoring Counters are\r
/// cleared.\r
///\r
- UINT32 WindowSize:10;\r
- UINT32 Reserved2:6;\r
+ UINT32 WindowSize : 10;\r
+ UINT32 Reserved2 : 6;\r
///\r
/// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
/// Instructions retired. '01 = Branch instructions retired '10 = Return\r
/// instructions retired. '11 = Indirect branch instructions retired.\r
///\r
- UINT32 WindowCntSel:2;\r
+ UINT32 WindowCntSel : 2;\r
///\r
/// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
/// event triggering condition is true only if all enabled counters'\r
/// threshold conditions are true. When '0', the threshold tripping\r
/// condition is true if any enabled counters' threshold is true.\r
///\r
- UINT32 CntAndMode:1;\r
- UINT32 Reserved3:5;\r
- UINT32 Reserved4:32;\r
+ UINT32 CntAndMode : 1;\r
+ UINT32 Reserved3 : 5;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
+#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
/// Monitoring event signaling is blocked until this bit is cleared by\r
/// software.\r
///\r
- UINT32 BranchMonitoringEventSignaled:1;\r
+ UINT32 BranchMonitoringEventSignaled : 1;\r
///\r
/// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
/// considered valid for sampling by branch monitoring software.\r
///\r
- UINT32 LBRsValid:1;\r
- UINT32 Reserved1:6;\r
+ UINT32 LBRsValid : 1;\r
+ UINT32 Reserved1 : 6;\r
///\r
/// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
/// status bit is sticky and once set requires clearing by software.\r
/// Counter operation continues independent of the state of the bit.\r
///\r
- UINT32 CntrHit0:1;\r
+ UINT32 CntrHit0 : 1;\r
///\r
/// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
/// status bit is sticky and once set requires clearing by software.\r
/// Counter operation continues independent of the state of the bit.\r
///\r
- UINT32 CntrHit1:1;\r
- UINT32 Reserved2:6;\r
+ UINT32 CntrHit1 : 1;\r
+ UINT32 Reserved2 : 6;\r
///\r
/// [Bits 25:16] CountWindow The current value of the window counter. The\r
/// count value is frozen on a valid branch monitoring triggering\r
/// condition. This is a 10-bit unsigned value.\r
///\r
- UINT32 CountWindow:10;\r
- UINT32 Reserved3:6;\r
+ UINT32 CountWindow : 10;\r
+ UINT32 Reserved3 : 6;\r
///\r
/// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
/// occurrence of the event being counted. The count value is frozen on a\r
/// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
/// value 0x7F (+127) and minimum value 0x80 (-128).\r
///\r
- UINT32 Count0:8;\r
+ UINT32 Count0 : 8;\r
///\r
/// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
/// occurrence of the event being counted. The count value is frozen on a\r
/// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
/// value 0x7F (+127) and minimum value 0x80 (-128).\r
///\r
- UINT32 Count1:8;\r
- UINT32 Reserved4:16;\r
+ UINT32 Count1 : 8;\r
+ UINT32 Reserved4 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
processor specific C-state code names, unrelated to MWAIT extension C-state\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
-\r
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
\r
/**\r
Core. Core C3 Residency Counter (R/O). Will always return 0.\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
-\r
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
\r
/**\r
Package. Protected Processor Inventory Number Enable Control (R/W).\r
AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
+#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
///\r
/// [Bit 0] LockOut (R/WO) See Table 2-25.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) See Table 2-25.\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PPIN 0x0000004F\r
-\r
+#define MSR_SKYLAKE_PPIN 0x0000004F\r
\r
/**\r
Package. Platform Information Contains power management and other model\r
AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
+#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumNon_TurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNon_TurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 ProgrammableRatioLimit:1;\r
+ UINT32 ProgrammableRatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 ProgrammableTDPLimit:1;\r
+ UINT32 ProgrammableTDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
///\r
- UINT32 ProgrammableTJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 ProgrammableTJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
/// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
/// supported by the processor are available.\r
///\r
- UINT32 C_StateLimit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 C_StateLimit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 MWAITRedirectionEnable:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 MWAITRedirectionEnable : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
+ UINT32 CFGLock : 1;\r
///\r
/// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
/// will convert HALT or MWAT(C1) to MWAIT(C6).\r
///\r
- UINT32 AutomaticC_StateConversionEnable:1;\r
- UINT32 Reserved3:8;\r
+ UINT32 AutomaticC_StateConversionEnable : 1;\r
+ UINT32 Reserved3 : 8;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3StateAutoDemotionEnable:1;\r
+ UINT32 C3StateAutoDemotionEnable : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
+ UINT32 C1StateAutoDemotionEnable : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 EnableC3Undemotion:1;\r
+ UINT32 EnableC3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 EnableC1Undemotion:1;\r
+ UINT32 EnableC1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotionEnable:1;\r
+ UINT32 CStateDemotionEnable : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUnDemotionEnable:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUnDemotionEnable : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Global Machine Check Capability (R/O).\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
+#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P.\r
///\r
- UINT32 MCG_SER_P:1;\r
+ UINT32 MCG_SER_P : 1;\r
///\r
/// [Bit 25] MCG_EM_P.\r
///\r
- UINT32 MCG_EM_P:1;\r
+ UINT32 MCG_EM_P : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 MCG_ELOG_P : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
+#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface is\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface is\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package. Temperature Target.\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
/// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
/// point.\r
///\r
- UINT32 NUMCORE_0:8;\r
+ UINT32 NUMCORE_0 : 8;\r
///\r
/// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_1:8;\r
+ UINT32 NUMCORE_1 : 8;\r
///\r
/// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_2:8;\r
+ UINT32 NUMCORE_2 : 8;\r
///\r
/// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_3:8;\r
+ UINT32 NUMCORE_3 : 8;\r
///\r
/// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_4:8;\r
+ UINT32 NUMCORE_4 : 8;\r
///\r
/// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_5:8;\r
+ UINT32 NUMCORE_5 : 8;\r
///\r
/// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_6:8;\r
+ UINT32 NUMCORE_6 : 8;\r
///\r
/// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
/// frequency point.\r
///\r
- UINT32 NUMCORE_7:8;\r
+ UINT32 NUMCORE_7 : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
/// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
/// to enable DRAM RAPL mode 0 (Direct VR).\r
///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 Energy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
RAPL Domain.".\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Reserved (R/O) Reads return 0.\r
\r
Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
/// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
/// Local memory bandwidth monitoring. All other encoding reserved.\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bits 41:32] RMID (RW).\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved2 : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
THREAD. Resource Association Register (R/W).\r
\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
///\r
/// [Bits 9:0] RMID.\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved1 : 22;\r
///\r
/// [Bits 51:32] COS (R/W).\r
///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
+ UINT32 COS : 20;\r
+ UINT32 Reserved2 : 12;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >=0.\r
AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
\r
/**\r
MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
///\r
/// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved2 : 12;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
\r
-\r
#endif\r
@endcode\r
@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
+#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
@endcode\r
@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
/// limit of 1 core active.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
/// limit of 2 core active.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
/// limit of 3 core active.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
/// limit of 4 core active.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
/// limit of 5 core active.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
/// limit of 6 core active.\r
///\r
- UINT32 Maximum6C:8;\r
- UINT32 Reserved:16;\r
+ UINT32 Maximum6C : 8;\r
+ UINT32 Reserved : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. See Table 2-2.\r
\r
@endcode\r
@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
-#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
\r
#endif\r
@endcode\r
@note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
**/\r
-#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
+#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
///\r
/// [Bit 0] LockOut (R/WO) See Table 2-25.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) See Table 2-25.\r
@endcode\r
@note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
**/\r
-#define MSR_XEON_D_PPIN 0x0000004F\r
-\r
+#define MSR_XEON_D_PPIN 0x0000004F\r
\r
/**\r
Package. See http://biosbits.org.\r
@endcode\r
@note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
+#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:7;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 7;\r
///\r
/// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
///\r
- UINT32 PPIN_CAP:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 PPIN_CAP : 1;\r
+ UINT32 Reserved3 : 4;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
/// Table 2-25.\r
///\r
- UINT32 TDPLimit:1;\r
+ UINT32 TDPLimit : 1;\r
///\r
/// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
///\r
- UINT32 TJOFFSET:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:8;\r
+ UINT32 TJOFFSET : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved6:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved6 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@endcode\r
@note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
/// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
/// supported by the processor are available.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
+ UINT32 CFGLock : 1;\r
///\r
/// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
/// will convert HALT or MWAT(C1) to MWAIT(C6).\r
///\r
- UINT32 CStateConversion:1;\r
- UINT32 Reserved3:8;\r
+ UINT32 CStateConversion : 1;\r
+ UINT32 Reserved3 : 8;\r
///\r
/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C3AutoDemotion:1;\r
+ UINT32 C3AutoDemotion : 1;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
///\r
- UINT32 C1AutoDemotion:1;\r
+ UINT32 C1AutoDemotion : 1;\r
///\r
/// [Bit 27] Enable C3 Undemotion (R/W).\r
///\r
- UINT32 C3Undemotion:1;\r
+ UINT32 C3Undemotion : 1;\r
///\r
/// [Bit 28] Enable C1 Undemotion (R/W).\r
///\r
- UINT32 C1Undemotion:1;\r
+ UINT32 C1Undemotion : 1;\r
///\r
/// [Bit 29] Package C State Demotion Enable (R/W).\r
///\r
- UINT32 CStateDemotion:1;\r
+ UINT32 CStateDemotion : 1;\r
///\r
/// [Bit 30] Package C State UnDemotion Enable (R/W).\r
///\r
- UINT32 CStateUndemotion:1;\r
- UINT32 Reserved4:1;\r
- UINT32 Reserved5:32;\r
+ UINT32 CStateUndemotion : 1;\r
+ UINT32 Reserved4 : 1;\r
+ UINT32 Reserved5 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Thread. Global Machine Check Capability (R/O).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
+#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
///\r
/// [Bits 7:0] Count.\r
///\r
- UINT32 Count:8;\r
+ UINT32 Count : 8;\r
///\r
/// [Bit 8] MCG_CTL_P.\r
///\r
- UINT32 MCG_CTL_P:1;\r
+ UINT32 MCG_CTL_P : 1;\r
///\r
/// [Bit 9] MCG_EXT_P.\r
///\r
- UINT32 MCG_EXT_P:1;\r
+ UINT32 MCG_EXT_P : 1;\r
///\r
/// [Bit 10] MCP_CMCI_P.\r
///\r
- UINT32 MCP_CMCI_P:1;\r
+ UINT32 MCP_CMCI_P : 1;\r
///\r
/// [Bit 11] MCG_TES_P.\r
///\r
- UINT32 MCG_TES_P:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 MCG_TES_P : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 23:16] MCG_EXT_CNT.\r
///\r
- UINT32 MCG_EXT_CNT:8;\r
+ UINT32 MCG_EXT_CNT : 8;\r
///\r
/// [Bit 24] MCG_SER_P.\r
///\r
- UINT32 MCG_SER_P:1;\r
+ UINT32 MCG_SER_P : 1;\r
///\r
/// [Bit 25] MCG_EM_P.\r
///\r
- UINT32 MCG_EM_P:1;\r
+ UINT32 MCG_EM_P : 1;\r
///\r
/// [Bit 26] MCG_ELOG_P.\r
///\r
- UINT32 MCG_ELOG_P:1;\r
- UINT32 Reserved2:5;\r
- UINT32 Reserved3:32;\r
+ UINT32 MCG_ELOG_P : 1;\r
+ UINT32 Reserved2 : 5;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
\r
-\r
/**\r
THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
Enhancement. Accessible only while in SMM.\r
@endcode\r
@note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
+#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:26;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 26;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
///\r
- UINT32 TCCActivationOffset:4;\r
- UINT32 Reserved2:4;\r
- UINT32 Reserved3:32;\r
+ UINT32 TCCActivationOffset : 4;\r
+ UINT32 Reserved2 : 4;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
///\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
///\r
- UINT32 Maximum1C:8;\r
+ UINT32 Maximum1C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
///\r
- UINT32 Maximum2C:8;\r
+ UINT32 Maximum2C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
///\r
- UINT32 Maximum3C:8;\r
+ UINT32 Maximum3C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
///\r
- UINT32 Maximum4C:8;\r
+ UINT32 Maximum4C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
///\r
- UINT32 Maximum5C:8;\r
+ UINT32 Maximum5C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
///\r
- UINT32 Maximum6C:8;\r
+ UINT32 Maximum6C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
///\r
- UINT32 Maximum7C:8;\r
+ UINT32 Maximum7C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
///\r
- UINT32 Maximum8C:8;\r
+ UINT32 Maximum8C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
///\r
/// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
///\r
- UINT32 Maximum9C:8;\r
+ UINT32 Maximum9C : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
///\r
- UINT32 Maximum10C:8;\r
+ UINT32 Maximum10C : 8;\r
///\r
/// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
///\r
- UINT32 Maximum11C:8;\r
+ UINT32 Maximum11C : 8;\r
///\r
/// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
///\r
- UINT32 Maximum12C:8;\r
+ UINT32 Maximum12C : 8;\r
///\r
/// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
///\r
- UINT32 Maximum13C:8;\r
+ UINT32 Maximum13C : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
///\r
- UINT32 Maximum14C:8;\r
+ UINT32 Maximum14C : 8;\r
///\r
/// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
///\r
- UINT32 Maximum15C:8;\r
+ UINT32 Maximum15C : 8;\r
///\r
/// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
///\r
- UINT32 Maximum16C:8;\r
+ UINT32 Maximum16C : 8;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
\r
-\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
\r
@endcode\r
@note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
@endcode\r
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
+#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
/// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
/// to enable DRAM RAPL mode 0 (Direct VR).\r
///\r
- UINT32 Energy:32;\r
- UINT32 Reserved:32;\r
+ UINT32 Energy : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
\r
-\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
RAPL Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
/// reduced below the operating system request due to assertion of\r
/// external PROCHOT.\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
/// operating system request due to a thermal event.\r
///\r
- UINT32 ThermalStatus:1;\r
+ UINT32 ThermalStatus : 1;\r
///\r
/// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
/// reduced below the operating system request due to PBM limit.\r
///\r
- UINT32 PowerBudgetManagementStatus:1;\r
+ UINT32 PowerBudgetManagementStatus : 1;\r
///\r
/// [Bit 3] Platform Configuration Services Status (R0) When set,\r
/// frequency is reduced below the operating system request due to PCS\r
/// limit.\r
///\r
- UINT32 PlatformConfigurationServicesStatus:1;\r
- UINT32 Reserved1:1;\r
+ UINT32 PlatformConfigurationServicesStatus : 1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
/// When set, frequency is reduced below the operating system request\r
/// because the processor has detected that utilization is low.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
/// below the operating system request due to a thermal alert from the\r
/// Voltage Regulator.\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
/// reduced below the operating system request due to electrical design\r
/// point constraints (e.g. maximum electrical current consumption).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:1;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 1;\r
///\r
/// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
/// below the operating system request due to Multi-Core Turbo limits.\r
///\r
- UINT32 MultiCoreTurboStatus:1;\r
- UINT32 Reserved4:2;\r
+ UINT32 MultiCoreTurboStatus : 1;\r
+ UINT32 Reserved4 : 2;\r
///\r
/// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
/// below max non-turbo P1.\r
///\r
- UINT32 FrequencyP1Status:1;\r
+ UINT32 FrequencyP1Status : 1;\r
///\r
/// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
/// set, frequency is reduced below max n-core turbo frequency.\r
///\r
- UINT32 TurboFrequencyLimitingStatus:1;\r
+ UINT32 TurboFrequencyLimitingStatus : 1;\r
///\r
/// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
/// reduced below the operating system request.\r
///\r
- UINT32 FrequencyLimitingStatus:1;\r
+ UINT32 FrequencyLimitingStatus : 1;\r
///\r
/// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 PROCHOT_Log:1;\r
+ UINT32 PROCHOT_Log : 1;\r
///\r
/// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 ThermalLog:1;\r
+ UINT32 ThermalLog : 1;\r
///\r
/// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PowerBudgetManagementLog:1;\r
+ UINT32 PowerBudgetManagementLog : 1;\r
///\r
/// [Bit 19] Platform Configuration Services Log When set, indicates that\r
/// the PCS Status bit has asserted since the log bit was last cleared.\r
/// This log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 PlatformConfigurationServicesLog:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 PlatformConfigurationServicesLog : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
/// indicates that the AUBFC Status bit has asserted since the log bit was\r
/// last cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
///\r
/// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
/// Alert Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 VRThermAlertLog:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 VRThermAlertLog : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
/// Status bit has asserted since the log bit was last cleared. This log\r
/// bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 ElectricalDesignPointLog:1;\r
- UINT32 Reserved7:1;\r
+ UINT32 ElectricalDesignPointLog : 1;\r
+ UINT32 Reserved7 : 1;\r
///\r
/// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
/// Turbo Status bit has asserted since the log bit was last cleared. This\r
/// log bit will remain set until cleared by software writing 0.\r
///\r
- UINT32 MultiCoreTurboLog:1;\r
- UINT32 Reserved8:2;\r
+ UINT32 MultiCoreTurboLog : 1;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
/// Frequency P1 Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyP1Log:1;\r
+ UINT32 CoreFrequencyP1Log : 1;\r
///\r
/// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
/// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
/// has asserted since the log bit was last cleared. This log bit will\r
/// remain set until cleared by software writing 0.\r
///\r
- UINT32 TurboFrequencyLimitingLog:1;\r
+ UINT32 TurboFrequencyLimitingLog : 1;\r
///\r
/// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
/// Frequency Limiting Status bit has asserted since the log bit was last\r
/// cleared. This log bit will remain set until cleared by software\r
/// writing 0.\r
///\r
- UINT32 CoreFrequencyLimitingLog:1;\r
- UINT32 Reserved9:32;\r
+ UINT32 CoreFrequencyLimitingLog : 1;\r
+ UINT32 Reserved9 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
-\r
/**\r
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
ECX=0):EBX.RDT-M[bit 12] = 1.\r
@endcode\r
@note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
+#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
/// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
/// Local memory bandwidth monitoring All other encoding reserved.\r
///\r
- UINT32 EventID:8;\r
- UINT32 Reserved1:24;\r
+ UINT32 EventID : 8;\r
+ UINT32 Reserved1 : 24;\r
///\r
/// [Bits 41:32] RMID (RW).\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved2:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved2 : 22;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
\r
-\r
/**\r
THREAD. Resource Association Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
+#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
///\r
/// [Bits 9:0] RMID.\r
///\r
- UINT32 RMID:10;\r
- UINT32 Reserved1:22;\r
+ UINT32 RMID : 10;\r
+ UINT32 Reserved1 : 22;\r
///\r
/// [Bits 51:32] COS (R/W).\r
///\r
- UINT32 COS:20;\r
- UINT32 Reserved2:12;\r
+ UINT32 COS : 20;\r
+ UINT32 Reserved2 : 12;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
\r
-\r
/**\r
Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
ECX=1):EDX.COS_MAX[15:0] >= n.\r
MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
-#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
/// @}\r
\r
/**\r
///\r
/// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
///\r
- UINT32 CBM:20;\r
- UINT32 Reserved2:12;\r
- UINT32 Reserved3:32;\r
+ UINT32 CBM : 20;\r
+ UINT32 Reserved2 : 12;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
\r
-\r
/**\r
Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
RW if MSR_PLATFORM_INFO.[28] = 1.\r
@endcode\r
@note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
**/\r
-#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:32;\r
- UINT32 Reserved2:31;\r
+ UINT32 Reserved1 : 32;\r
+ UINT32 Reserved2 : 31;\r
///\r
/// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
/// the processor uses override configuration specified in\r
/// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
/// uses factory-set configuration (Default).\r
///\r
- UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
\r
-\r
/**\r
Package. Cache Allocation Technology Configuration (R/W).\r
\r
@endcode\r
@note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
**/\r
-#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
+#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
///\r
/// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
///\r
- UINT32 CAT:1;\r
- UINT32 Reserved1:31;\r
- UINT32 Reserved2:32;\r
+ UINT32 CAT : 1;\r
+ UINT32 Reserved1 : 31;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
\r
#endif\r
@endcode\r
@note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
+#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Thread. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Reserved Attempt to read/write will cause #UD.\r
@endcode\r
@note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
-\r
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box control MSR.\r
@endcode\r
@note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL 0x00000F40\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box status MSR.\r
@endcode\r
@note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS 0x00000F41\r
\r
/**\r
Package. Uncore C-box 8 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
-\r
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL 0x00000F42\r
\r
/**\r
Package. Uncore C-box 8 perfmon event select MSR.\r
MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
-#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL0 0x00000F50\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL1 0x00000F52\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL2 0x00000F54\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL3 0x00000F56\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL4 0x00000F58\r
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL5 0x00000F5A\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-box 8 perfmon counter MSR.\r
\r
MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
-#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
-#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
-#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
-#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
-#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
+#define MSR_XEON_E7_C8_PMON_CTR0 0x00000F51\r
+#define MSR_XEON_E7_C8_PMON_CTR1 0x00000F53\r
+#define MSR_XEON_E7_C8_PMON_CTR2 0x00000F55\r
+#define MSR_XEON_E7_C8_PMON_CTR3 0x00000F57\r
+#define MSR_XEON_E7_C8_PMON_CTR4 0x00000F59\r
+#define MSR_XEON_E7_C8_PMON_CTR5 0x00000F5B\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-box 9 perfmon local box control MSR.\r
\r
@endcode\r
@note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.\r
**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_CTRL 0x00000FC0\r
\r
/**\r
Package. Uncore C-box 9 perfmon local box status MSR.\r
@endcode\r
@note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.\r
**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_STATUS 0x00000FC1\r
\r
/**\r
Package. Uncore C-box 9 perfmon local box overflow control MSR.\r
@endcode\r
@note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
-#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
-\r
+#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL 0x00000FC2\r
\r
/**\r
Package. Uncore C-box 9 perfmon event select MSR.\r
MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
-#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL0 0x00000FD0\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL1 0x00000FD2\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL2 0x00000FD4\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL3 0x00000FD6\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL4 0x00000FD8\r
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL5 0x00000FDA\r
/// @}\r
\r
-\r
/**\r
Package. Uncore C-box 9 perfmon counter MSR.\r
\r
MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.\r
@{\r
**/\r
-#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
-#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
-#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
-#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
-#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
-#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
+#define MSR_XEON_E7_C9_PMON_CTR0 0x00000FD1\r
+#define MSR_XEON_E7_C9_PMON_CTR1 0x00000FD3\r
+#define MSR_XEON_E7_C9_PMON_CTR2 0x00000FD5\r
+#define MSR_XEON_E7_C9_PMON_CTR3 0x00000FD7\r
+#define MSR_XEON_E7_C9_PMON_CTR4 0x00000FD9\r
+#define MSR_XEON_E7_C9_PMON_CTR5 0x00000FDB\r
/// @}\r
\r
#endif\r
@endcode\r
@note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
-#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
+#define MSR_XEON_PHI_SMI_COUNT 0x00000034\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r
///\r
/// [Bits 31:0] SMI Count (R/O).\r
///\r
- UINT32 SMICount:32;\r
- UINT32 Reserved:32;\r
+ UINT32 SMICount : 32;\r
+ UINT32 Reserved : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_SMI_COUNT_REGISTER;\r
\r
/**\r
AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
+#define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r
/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r
/// prevent unauthorized modification to MSR_PPIN_CTL.\r
///\r
- UINT32 LockOut:1;\r
+ UINT32 LockOut : 1;\r
///\r
/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r
/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r
/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r
/// Default is 0.\r
///\r
- UINT32 Enable_PPIN:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 Enable_PPIN : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PPIN_CTL_REGISTER;\r
\r
-\r
/**\r
Package. Protected Processor Inventory Number (R/O). Protected Processor\r
Inventory Number (R/O) A unique value within a given CPUID\r
Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_PPIN 0x0000004F\r
+#define MSR_XEON_PHI_PPIN 0x0000004F\r
\r
/**\r
Package. Platform Information Contains power management and other model\r
@endcode\r
@note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
+#define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:8;\r
+ UINT32 Reserved1 : 8;\r
///\r
/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
/// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
/// MHz.\r
///\r
- UINT32 MaximumNonTurboRatio:8;\r
- UINT32 Reserved2:12;\r
+ UINT32 MaximumNonTurboRatio : 8;\r
+ UINT32 Reserved2 : 12;\r
///\r
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
/// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
/// Turbo mode is disabled.\r
///\r
- UINT32 RatioLimit:1;\r
+ UINT32 RatioLimit : 1;\r
///\r
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
/// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
/// and when set to 0, indicates TDP Limit for Turbo mode is not\r
/// programmable.\r
///\r
- UINT32 TDPLimit:1;\r
- UINT32 Reserved3:2;\r
- UINT32 Reserved4:8;\r
+ UINT32 TDPLimit : 1;\r
+ UINT32 Reserved3 : 2;\r
+ UINT32 Reserved4 : 8;\r
///\r
/// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
/// minimum ratio (maximum efficiency) that the processor can operates, in\r
/// units of 100MHz.\r
///\r
- UINT32 MaximumEfficiencyRatio:8;\r
- UINT32 Reserved5:16;\r
+ UINT32 MaximumEfficiencyRatio : 8;\r
+ UINT32 Reserved5 : 16;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r
\r
-\r
/**\r
Module. C-State Configuration Control (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r
/// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r
/// Retention 011b: C6 Retention 111b: No limit.\r
///\r
- UINT32 Limit:3;\r
- UINT32 Reserved1:7;\r
+ UINT32 Limit : 3;\r
+ UINT32 Reserved1 : 7;\r
///\r
/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
///\r
- UINT32 IO_MWAIT:1;\r
- UINT32 Reserved2:4;\r
+ UINT32 IO_MWAIT : 1;\r
+ UINT32 Reserved2 : 4;\r
///\r
/// [Bit 15] CFG Lock (R/WO).\r
///\r
- UINT32 CFGLock:1;\r
- UINT32 Reserved5:10;\r
+ UINT32 CFGLock : 1;\r
+ UINT32 Reserved5 : 10;\r
///\r
/// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r
/// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
/// auto-demote information.\r
///\r
- UINT32 C1StateAutoDemotionEnable:1;\r
- UINT32 Reserved6:1;\r
+ UINT32 C1StateAutoDemotionEnable : 1;\r
+ UINT32 Reserved6 : 1;\r
///\r
/// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r
/// Undemotion from Demoted C1.\r
///\r
- UINT32 C1StateAutoUndemotionEnable:1;\r
+ UINT32 C1StateAutoUndemotionEnable : 1;\r
///\r
/// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r
/// Package C state demotion.\r
///\r
- UINT32 PKGC_StateAutoDemotionEnable:1;\r
- UINT32 Reserved7:2;\r
- UINT32 Reserved4:32;\r
+ UINT32 PKGC_StateAutoDemotionEnable : 1;\r
+ UINT32 Reserved7 : 2;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
-\r
/**\r
Module. Power Management IO Redirection in C-state (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
-#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r
///\r
/// [Bits 15:0] LVL_2 Base Address (R/W).\r
///\r
- UINT32 Lvl2Base:16;\r
+ UINT32 Lvl2Base : 16;\r
///\r
/// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r
/// IO-redirection will be executed (0-127). Should be programmed based on\r
/// the number of LVLx registers existing in the chipset.\r
///\r
- UINT32 CStateRange:7;\r
- UINT32 Reserved3:9;\r
- UINT32 Reserved2:32;\r
+ UINT32 CStateRange : 7;\r
+ UINT32 Reserved3 : 9;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
-\r
/**\r
Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
handler to handle unsuccessful read of this MSR.\r
@endcode\r
@note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
-#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
+#define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r
/// 01b, AES instruction can be mis-configured if a privileged agent\r
/// unintentionally writes 11b.\r
///\r
- UINT32 AESConfiguration:2;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 AESConfiguration : 2;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r
\r
-\r
/**\r
Thread. MISC_FEATURE_ENABLES.\r
\r
AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:1;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r
/// MWAIT instructions do not cause invalid-opcode exceptions when\r
/// other than C0 or C1, the instruction operates as if EAX indicated the\r
/// C-state C1.\r
///\r
- UINT32 UserModeMonitorAndMwait:1;\r
- UINT32 Reserved2:30;\r
- UINT32 Reserved3:32;\r
+ UINT32 UserModeMonitorAndMwait : 1;\r
+ UINT32 Reserved2 : 30;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
**/\r
-#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r
/// set, that bank supports Enhanced MCA (Default all 0; does not support\r
/// EMCA).\r
///\r
- UINT32 BankSupport:32;\r
- UINT32 Reserved4:24;\r
+ UINT32 BankSupport : 32;\r
+ UINT32 Reserved4 : 24;\r
///\r
/// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r
///\r
- UINT32 TargetedSMI:1;\r
+ UINT32 TargetedSMI : 1;\r
///\r
/// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r
/// is supported.\r
///\r
- UINT32 SMM_CPU_SVRSTR:1;\r
+ UINT32 SMM_CPU_SVRSTR : 1;\r
///\r
/// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
/// SMM code access restriction is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 SMM_Code_Access_Chk:1;\r
+ UINT32 SMM_Code_Access_Chk : 1;\r
///\r
/// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
/// SMM long flow indicator is supported and a host-space interface\r
/// available to SMM handler.\r
///\r
- UINT32 Long_Flow_Indication:1;\r
- UINT32 Reserved3:4;\r
+ UINT32 Long_Flow_Indication : 1;\r
+ UINT32 Reserved3 : 4;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r
\r
-\r
/**\r
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r
functions to be enabled and disabled.\r
@endcode\r
@note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
+#define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r
///\r
/// [Bit 0] Fast-Strings Enable.\r
///\r
- UINT32 FastStrings:1;\r
- UINT32 Reserved1:2;\r
+ UINT32 FastStrings : 1;\r
+ UINT32 Reserved1 : 2;\r
///\r
/// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r
/// is 1.\r
///\r
- UINT32 AutomaticThermalControlCircuit:1;\r
- UINT32 Reserved2:3;\r
+ UINT32 AutomaticThermalControlCircuit : 1;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bit 7] Performance Monitoring Available (R).\r
///\r
- UINT32 PerformanceMonitoring:1;\r
- UINT32 Reserved3:3;\r
+ UINT32 PerformanceMonitoring : 1;\r
+ UINT32 Reserved3 : 3;\r
///\r
/// [Bit 11] Branch Trace Storage Unavailable (RO).\r
///\r
- UINT32 BTS:1;\r
+ UINT32 BTS : 1;\r
///\r
/// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r
///\r
- UINT32 PEBS:1;\r
- UINT32 Reserved4:3;\r
+ UINT32 PEBS : 1;\r
+ UINT32 Reserved4 : 3;\r
///\r
/// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r
///\r
- UINT32 EIST:1;\r
- UINT32 Reserved5:1;\r
+ UINT32 EIST : 1;\r
+ UINT32 Reserved5 : 1;\r
///\r
/// [Bit 18] ENABLE MONITOR FSM (R/W).\r
///\r
- UINT32 MONITOR:1;\r
- UINT32 Reserved6:3;\r
+ UINT32 MONITOR : 1;\r
+ UINT32 Reserved6 : 3;\r
///\r
/// [Bit 22] Limit CPUID Maxval (R/W).\r
///\r
- UINT32 LimitCpuidMaxval:1;\r
+ UINT32 LimitCpuidMaxval : 1;\r
///\r
/// [Bit 23] xTPR Message Disable (R/W).\r
///\r
- UINT32 xTPR_Message_Disable:1;\r
- UINT32 Reserved7:8;\r
- UINT32 Reserved8:2;\r
+ UINT32 xTPR_Message_Disable : 1;\r
+ UINT32 Reserved7 : 8;\r
+ UINT32 Reserved8 : 2;\r
///\r
/// [Bit 34] XD Bit Disable (R/W).\r
///\r
- UINT32 XD:1;\r
- UINT32 Reserved9:3;\r
+ UINT32 XD : 1;\r
+ UINT32 Reserved9 : 3;\r
///\r
/// [Bit 38] Turbo Mode Disable (R/W).\r
///\r
- UINT32 TurboModeDisable:1;\r
- UINT32 Reserved10:25;\r
+ UINT32 TurboModeDisable : 1;\r
+ UINT32 Reserved10 : 25;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r
\r
-\r
/**\r
Package.\r
\r
@endcode\r
@note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
-#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
+#define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved1:16;\r
+ UINT32 Reserved1 : 16;\r
///\r
/// [Bits 23:16] Temperature Target (R).\r
///\r
- UINT32 TemperatureTarget:8;\r
+ UINT32 TemperatureTarget : 8;\r
///\r
/// [Bits 29:24] Target Offset (R/W).\r
///\r
- UINT32 TargetOffset:6;\r
- UINT32 Reserved2:2;\r
- UINT32 Reserved3:32;\r
+ UINT32 TargetOffset : 6;\r
+ UINT32 Reserved2 : 2;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r
\r
-\r
/**\r
Miscellaneous Feature Control (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r
/// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r
/// L1 data cache prefetcher.\r
///\r
- UINT32 DCUHardwarePrefetcherDisable:1;\r
+ UINT32 DCUHardwarePrefetcherDisable : 1;\r
///\r
/// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r
/// L2 hardware prefetcher.\r
///\r
- UINT32 L2HardwarePrefetcherDisable:1;\r
- UINT32 Reserved1:30;\r
- UINT32 Reserved2:32;\r
+ UINT32 L2HardwarePrefetcherDisable : 1;\r
+ UINT32 Reserved1 : 30;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r
\r
-\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
-\r
+#define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r
\r
/**\r
Shared. Offcore Response Event Select Register (R/W).\r
@endcode\r
@note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
-#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
-\r
+#define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r
\r
/**\r
Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r
@endcode\r
@note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r
/// Individual bit fields\r
///\r
struct {\r
- UINT32 Reserved:1;\r
+ UINT32 Reserved : 1;\r
///\r
/// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r
/// processor cores which operates under the maximum ratio limit for group\r
/// 0.\r
///\r
- UINT32 MaxCoresGroup0:7;\r
+ UINT32 MaxCoresGroup0 : 7;\r
///\r
/// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r
/// ratio limit when the number of active cores are not more than the\r
/// group 0 maximum core count.\r
///\r
- UINT32 MaxRatioLimitGroup0:8;\r
+ UINT32 MaxRatioLimitGroup0 : 8;\r
///\r
/// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r
/// Group 1, which includes the specified number of additional cores plus\r
/// the cores in group 0, operates under the group 1 turbo max ratio limit\r
/// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r
///\r
- UINT32 MaxIncrementalCoresGroup1:5;\r
+ UINT32 MaxIncrementalCoresGroup1 : 5;\r
///\r
/// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// to Group 0.\r
///\r
- UINT32 DeltaRatioGroup1:3;\r
+ UINT32 DeltaRatioGroup1 : 3;\r
///\r
/// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r
/// Group 2, which includes the specified number of additional cores plus\r
/// all the cores in group 1, operates under the group 2 turbo max ratio\r
/// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r
///\r
- UINT32 MaxIncrementalCoresGroup2:5;\r
+ UINT32 MaxIncrementalCoresGroup2 : 5;\r
///\r
/// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 1.\r
///\r
- UINT32 DeltaRatioGroup2:3;\r
+ UINT32 DeltaRatioGroup2 : 3;\r
///\r
/// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r
/// Group 3, which includes the specified number of additional cores plus\r
/// all the cores in group 2, operates under the group 3 turbo max ratio\r
/// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r
///\r
- UINT32 MaxIncrementalCoresGroup3:5;\r
+ UINT32 MaxIncrementalCoresGroup3 : 5;\r
///\r
/// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 2.\r
///\r
- UINT32 DeltaRatioGroup3:3;\r
+ UINT32 DeltaRatioGroup3 : 3;\r
///\r
/// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r
/// Group 4, which includes the specified number of additional cores plus\r
/// all the cores in group 3, operates under the group 4 turbo max ratio\r
/// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r
///\r
- UINT32 MaxIncrementalCoresGroup4:5;\r
+ UINT32 MaxIncrementalCoresGroup4 : 5;\r
///\r
/// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 3.\r
///\r
- UINT32 DeltaRatioGroup4:3;\r
+ UINT32 DeltaRatioGroup4 : 3;\r
///\r
/// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r
/// Group 5, which includes the specified number of additional cores plus\r
/// all the cores in group 4, operates under the group 5 turbo max ratio\r
/// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r
///\r
- UINT32 MaxIncrementalCoresGroup5:5;\r
+ UINT32 MaxIncrementalCoresGroup5 : 5;\r
///\r
/// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 4.\r
///\r
- UINT32 DeltaRatioGroup5:3;\r
+ UINT32 DeltaRatioGroup5 : 3;\r
///\r
/// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r
/// Group 6, which includes the specified number of additional cores plus\r
/// all the cores in group 5, operates under the group 6 turbo max ratio\r
/// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r
///\r
- UINT32 MaxIncrementalCoresGroup6:5;\r
+ UINT32 MaxIncrementalCoresGroup6 : 5;\r
///\r
/// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r
/// integer specifying the ratio decrement relative to the Max ratio limit\r
/// for Group 5.\r
///\r
- UINT32 DeltaRatioGroup6:3;\r
+ UINT32 DeltaRatioGroup6 : 3;\r
} Bits;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Thread. Last Branch Record Filtering Select Register (R/W).\r
\r
@endcode\r
@note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
-#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
-\r
+#define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r
///\r
/// [Bit 0] CPL_EQ_0.\r
///\r
- UINT32 CPL_EQ_0:1;\r
+ UINT32 CPL_EQ_0 : 1;\r
///\r
/// [Bit 1] CPL_NEQ_0.\r
///\r
- UINT32 CPL_NEQ_0:1;\r
+ UINT32 CPL_NEQ_0 : 1;\r
///\r
/// [Bit 2] JCC.\r
///\r
- UINT32 JCC:1;\r
+ UINT32 JCC : 1;\r
///\r
/// [Bit 3] NEAR_REL_CALL.\r
///\r
- UINT32 NEAR_REL_CALL:1;\r
+ UINT32 NEAR_REL_CALL : 1;\r
///\r
/// [Bit 4] NEAR_IND_CALL.\r
///\r
- UINT32 NEAR_IND_CALL:1;\r
+ UINT32 NEAR_IND_CALL : 1;\r
///\r
/// [Bit 5] NEAR_RET.\r
///\r
- UINT32 NEAR_RET:1;\r
+ UINT32 NEAR_RET : 1;\r
///\r
/// [Bit 6] NEAR_IND_JMP.\r
///\r
- UINT32 NEAR_IND_JMP:1;\r
+ UINT32 NEAR_IND_JMP : 1;\r
///\r
/// [Bit 7] NEAR_REL_JMP.\r
///\r
- UINT32 NEAR_REL_JMP:1;\r
+ UINT32 NEAR_REL_JMP : 1;\r
///\r
/// [Bit 8] FAR_BRANCH.\r
///\r
- UINT32 FAR_BRANCH:1;\r
- UINT32 Reserved1:23;\r
- UINT32 Reserved2:32;\r
+ UINT32 FAR_BRANCH : 1;\r
+ UINT32 Reserved1 : 23;\r
+ UINT32 Reserved2 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_LBR_SELECT_REGISTER;\r
\r
/**\r
@endcode\r
@note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
-#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
-\r
+#define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r
\r
/**\r
Thread. Last Exception Record From Linear IP (R).\r
@endcode\r
@note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
-#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
-\r
+#define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r
\r
/**\r
Thread. Last Exception Record To Linear IP (R).\r
@endcode\r
@note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
-#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
-\r
+#define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r
\r
/**\r
Thread. See Table 2-2.\r
@endcode\r
@note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
-#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
-\r
+#define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r
\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
-\r
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r
\r
/**\r
Package. Package C6 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
-\r
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r
\r
/**\r
Package. Package C7 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
-\r
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r
\r
/**\r
Module. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
-\r
+#define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r
\r
/**\r
Module. Module C6 Residency Counter. (R/O).\r
@endcode\r
@note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
-\r
+#define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r
\r
/**\r
Core. Note: C-state values are processor specific C-state code names,\r
@endcode\r
@note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
-\r
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r
\r
/**\r
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r
@endcode\r
@note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
-\r
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r
\r
/**\r
Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r
@endcode\r
@note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r
**/\r
-#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
-\r
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r
\r
/**\r
Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
@endcode\r
@note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
+#define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r
///\r
/// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
///\r
- UINT32 PowerUnits:4;\r
- UINT32 Reserved1:4;\r
+ UINT32 PowerUnits : 4;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bits 12:8] Package. Energy Status Units Energy related information\r
/// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
/// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
/// micro-joules).\r
///\r
- UINT32 EnergyStatusUnits:5;\r
- UINT32 Reserved2:3;\r
+ UINT32 EnergyStatusUnits : 5;\r
+ UINT32 Reserved2 : 3;\r
///\r
/// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
/// Interfaces.".\r
///\r
- UINT32 TimeUnits:4;\r
- UINT32 Reserved3:12;\r
- UINT32 Reserved4:32;\r
+ UINT32 TimeUnits : 4;\r
+ UINT32 Reserved3 : 12;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r
\r
-\r
/**\r
Package. Note: C-state values are processor specific C-state code names,\r
unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r
@endcode\r
@note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
-\r
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r
\r
/**\r
Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r
@endcode\r
@note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
-\r
+#define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r
\r
/**\r
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
-\r
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r
\r
/**\r
Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
-\r
+#define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r
\r
/**\r
Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r
@endcode\r
@note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
-\r
+#define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r
\r
/**\r
Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
@endcode\r
@note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
-\r
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r
\r
/**\r
Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
-\r
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r
\r
/**\r
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
@endcode\r
@note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
-\r
+#define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r
\r
/**\r
Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
@endcode\r
@note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
-#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
-\r
+#define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r
\r
/**\r
Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
@endcode\r
**/\r
-#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r
/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
/// LLC/Ring.\r
///\r
- UINT32 MAX_RATIO:7;\r
- UINT32 Reserved1:1;\r
+ UINT32 MAX_RATIO : 7;\r
+ UINT32 Reserved1 : 1;\r
///\r
/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
/// possible ratio of the LLC/Ring.\r
///\r
- UINT32 MIN_RATIO:7;\r
- UINT32 Reserved2:17;\r
- UINT32 Reserved3:32;\r
+ UINT32 MIN_RATIO : 7;\r
+ UINT32 Reserved2 : 17;\r
+ UINT32 Reserved3 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
-\r
/**\r
Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
RAPL Domains.".\r
@endcode\r
@note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r
**/\r
-#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
-\r
+#define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r
\r
/**\r
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
@endcode\r
@note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
-#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
-\r
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r
\r
/**\r
Package. Base TDP Ratio (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r
\r
/**\r
Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r
\r
/**\r
Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
/**\r
Package. ConfigTDP Control (R/W) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
-#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
-\r
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r
\r
/**\r
Package. ConfigTDP Control (R/W) See Table 2-24.\r
@endcode\r
@note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
-#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
-\r
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
/**\r
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
@endcode\r
@note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
**/\r
-#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r
\r
/**\r
MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r
///\r
/// [Bit 0] PROCHOT Status (R0).\r
///\r
- UINT32 PROCHOT_Status:1;\r
+ UINT32 PROCHOT_Status : 1;\r
///\r
/// [Bit 1] Thermal Status (R0).\r
///\r
- UINT32 ThermalStatus:1;\r
- UINT32 Reserved1:4;\r
+ UINT32 ThermalStatus : 1;\r
+ UINT32 Reserved1 : 4;\r
///\r
/// [Bit 6] VR Therm Alert Status (R0).\r
///\r
- UINT32 VRThermAlertStatus:1;\r
- UINT32 Reserved2:1;\r
+ UINT32 VRThermAlertStatus : 1;\r
+ UINT32 Reserved2 : 1;\r
///\r
/// [Bit 8] Electrical Design Point Status (R0).\r
///\r
- UINT32 ElectricalDesignPointStatus:1;\r
- UINT32 Reserved3:23;\r
- UINT32 Reserved4:32;\r
+ UINT32 ElectricalDesignPointStatus : 1;\r
+ UINT32 Reserved3 : 23;\r
+ UINT32 Reserved4 : 32;\r
} Bits;\r
///\r
/// All bit fields as a 32-bit value\r
///\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
///\r
/// All bit fields as a 64-bit value\r
///\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r
\r
#endif\r
///\r
/// Default SMBASE address\r
///\r
-#define SMM_DEFAULT_SMBASE 0x30000\r
+#define SMM_DEFAULT_SMBASE 0x30000\r
\r
///\r
/// Offset of SMM handler from SMBASE\r
///\r
-#define SMM_HANDLER_OFFSET 0x8000\r
+#define SMM_HANDLER_OFFSET 0x8000\r
\r
///\r
/// Offset of SMRAM Save State Map from SMBASE\r
/// 32-bit SMRAM Save State Map\r
///\r
typedef struct {\r
- UINT8 Reserved[0x200]; // 7c00h\r
- // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
- // SMRAM Save State Maps are the same size\r
- UINT8 Reserved1[0xf8]; // 7e00h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved2[0x9C]; // 7f08h\r
- UINT32 IOMemAddr; // 7fa0h\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS; // 7fach\r
- UINT32 _SS; // 7fb0h\r
- UINT32 _DS; // 7fb4h\r
- UINT32 _FS; // 7fb8h\r
- UINT32 _GS; // 7fbch\r
- UINT32 Reserved3; // 7fc0h\r
- UINT32 _TR; // 7fc4h\r
- UINT32 _DR7; // 7fc8h\r
- UINT32 _DR6; // 7fcch\r
- UINT32 _EAX; // 7fd0h\r
- UINT32 _ECX; // 7fd4h\r
- UINT32 _EDX; // 7fd8h\r
- UINT32 _EBX; // 7fdch\r
- UINT32 _ESP; // 7fe0h\r
- UINT32 _EBP; // 7fe4h\r
- UINT32 _ESI; // 7fe8h\r
- UINT32 _EDI; // 7fech\r
- UINT32 _EIP; // 7ff0h\r
- UINT32 _EFLAGS; // 7ff4h\r
- UINT32 _CR3; // 7ff8h\r
- UINT32 _CR0; // 7ffch\r
+ UINT8 Reserved[0x200]; // 7c00h\r
+ // Padded an extra 0x200 bytes so 32-bit and 64-bit\r
+ // SMRAM Save State Maps are the same size\r
+ UINT8 Reserved1[0xf8]; // 7e00h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved2[0x9C]; // 7f08h\r
+ UINT32 IOMemAddr; // 7fa0h\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS; // 7fach\r
+ UINT32 _SS; // 7fb0h\r
+ UINT32 _DS; // 7fb4h\r
+ UINT32 _FS; // 7fb8h\r
+ UINT32 _GS; // 7fbch\r
+ UINT32 Reserved3; // 7fc0h\r
+ UINT32 _TR; // 7fc4h\r
+ UINT32 _DR7; // 7fc8h\r
+ UINT32 _DR6; // 7fcch\r
+ UINT32 _EAX; // 7fd0h\r
+ UINT32 _ECX; // 7fd4h\r
+ UINT32 _EDX; // 7fd8h\r
+ UINT32 _EBX; // 7fdch\r
+ UINT32 _ESP; // 7fe0h\r
+ UINT32 _EBP; // 7fe4h\r
+ UINT32 _ESI; // 7fe8h\r
+ UINT32 _EDI; // 7fech\r
+ UINT32 _EIP; // 7ff0h\r
+ UINT32 _EFLAGS; // 7ff4h\r
+ UINT32 _CR3; // 7ff8h\r
+ UINT32 _CR0; // 7ffch\r
} SMRAM_SAVE_STATE_MAP32;\r
\r
///\r
/// 64-bit SMRAM Save State Map\r
///\r
typedef struct {\r
- UINT8 Reserved1[0x1d0]; // 7c00h\r
- UINT32 GdtBaseHiDword; // 7dd0h\r
- UINT32 LdtBaseHiDword; // 7dd4h\r
- UINT32 IdtBaseHiDword; // 7dd8h\r
- UINT8 Reserved2[0xc]; // 7ddch\r
- UINT64 IO_EIP; // 7de8h\r
- UINT8 Reserved3[0x50]; // 7df0h\r
- UINT32 _CR4; // 7e40h\r
- UINT8 Reserved4[0x48]; // 7e44h\r
- UINT32 GdtBaseLoDword; // 7e8ch\r
- UINT32 Reserved5; // 7e90h\r
- UINT32 IdtBaseLoDword; // 7e94h\r
- UINT32 Reserved6; // 7e98h\r
- UINT32 LdtBaseLoDword; // 7e9ch\r
- UINT8 Reserved7[0x38]; // 7ea0h\r
- UINT64 EptVmxControl; // 7ed8h\r
- UINT32 EnEptVmxControl; // 7ee0h\r
- UINT8 Reserved8[0x14]; // 7ee4h\r
- UINT32 SMBASE; // 7ef8h\r
- UINT32 SMMRevId; // 7efch\r
- UINT16 IORestart; // 7f00h\r
- UINT16 AutoHALTRestart; // 7f02h\r
- UINT8 Reserved9[0x18]; // 7f04h\r
- UINT64 _R15; // 7f1ch\r
- UINT64 _R14;\r
- UINT64 _R13;\r
- UINT64 _R12;\r
- UINT64 _R11;\r
- UINT64 _R10;\r
- UINT64 _R9;\r
- UINT64 _R8;\r
- UINT64 _RAX; // 7f5ch\r
- UINT64 _RCX;\r
- UINT64 _RDX;\r
- UINT64 _RBX;\r
- UINT64 _RSP;\r
- UINT64 _RBP;\r
- UINT64 _RSI;\r
- UINT64 _RDI;\r
- UINT64 IOMemAddr; // 7f9ch\r
- UINT32 IOMisc; // 7fa4h\r
- UINT32 _ES; // 7fa8h\r
- UINT32 _CS;\r
- UINT32 _SS;\r
- UINT32 _DS;\r
- UINT32 _FS;\r
- UINT32 _GS;\r
- UINT32 _LDTR; // 7fc0h\r
- UINT32 _TR;\r
- UINT64 _DR7; // 7fc8h\r
- UINT64 _DR6;\r
- UINT64 _RIP; // 7fd8h\r
- UINT64 IA32_EFER; // 7fe0h\r
- UINT64 _RFLAGS; // 7fe8h\r
- UINT64 _CR3; // 7ff0h\r
- UINT64 _CR0; // 7ff8h\r
+ UINT8 Reserved1[0x1d0]; // 7c00h\r
+ UINT32 GdtBaseHiDword; // 7dd0h\r
+ UINT32 LdtBaseHiDword; // 7dd4h\r
+ UINT32 IdtBaseHiDword; // 7dd8h\r
+ UINT8 Reserved2[0xc]; // 7ddch\r
+ UINT64 IO_EIP; // 7de8h\r
+ UINT8 Reserved3[0x50]; // 7df0h\r
+ UINT32 _CR4; // 7e40h\r
+ UINT8 Reserved4[0x48]; // 7e44h\r
+ UINT32 GdtBaseLoDword; // 7e8ch\r
+ UINT32 Reserved5; // 7e90h\r
+ UINT32 IdtBaseLoDword; // 7e94h\r
+ UINT32 Reserved6; // 7e98h\r
+ UINT32 LdtBaseLoDword; // 7e9ch\r
+ UINT8 Reserved7[0x38]; // 7ea0h\r
+ UINT64 EptVmxControl; // 7ed8h\r
+ UINT32 EnEptVmxControl; // 7ee0h\r
+ UINT8 Reserved8[0x14]; // 7ee4h\r
+ UINT32 SMBASE; // 7ef8h\r
+ UINT32 SMMRevId; // 7efch\r
+ UINT16 IORestart; // 7f00h\r
+ UINT16 AutoHALTRestart; // 7f02h\r
+ UINT8 Reserved9[0x18]; // 7f04h\r
+ UINT64 _R15; // 7f1ch\r
+ UINT64 _R14;\r
+ UINT64 _R13;\r
+ UINT64 _R12;\r
+ UINT64 _R11;\r
+ UINT64 _R10;\r
+ UINT64 _R9;\r
+ UINT64 _R8;\r
+ UINT64 _RAX; // 7f5ch\r
+ UINT64 _RCX;\r
+ UINT64 _RDX;\r
+ UINT64 _RBX;\r
+ UINT64 _RSP;\r
+ UINT64 _RBP;\r
+ UINT64 _RSI;\r
+ UINT64 _RDI;\r
+ UINT64 IOMemAddr; // 7f9ch\r
+ UINT32 IOMisc; // 7fa4h\r
+ UINT32 _ES; // 7fa8h\r
+ UINT32 _CS;\r
+ UINT32 _SS;\r
+ UINT32 _DS;\r
+ UINT32 _FS;\r
+ UINT32 _GS;\r
+ UINT32 _LDTR; // 7fc0h\r
+ UINT32 _TR;\r
+ UINT64 _DR7; // 7fc8h\r
+ UINT64 _DR6;\r
+ UINT64 _RIP; // 7fd8h\r
+ UINT64 IA32_EFER; // 7fe0h\r
+ UINT64 _RFLAGS; // 7fe8h\r
+ UINT64 _CR3; // 7ff0h\r
+ UINT64 _CR0; // 7ff8h\r
} SMRAM_SAVE_STATE_MAP64;\r
\r
///\r
/// Union of 32-bit and 64-bit SMRAM Save State Maps\r
///\r
typedef union {\r
- SMRAM_SAVE_STATE_MAP32 x86;\r
- SMRAM_SAVE_STATE_MAP64 x64;\r
+ SMRAM_SAVE_STATE_MAP32 x86;\r
+ SMRAM_SAVE_STATE_MAP64 x64;\r
} SMRAM_SAVE_STATE_MAP;\r
\r
///\r
///\r
/// SMRAM Save State Map IOMisc I/O Length Values\r
///\r
-#define SMM_IO_LENGTH_BYTE 0x01\r
-#define SMM_IO_LENGTH_WORD 0x02\r
-#define SMM_IO_LENGTH_DWORD 0x04\r
+#define SMM_IO_LENGTH_BYTE 0x01\r
+#define SMM_IO_LENGTH_WORD 0x02\r
+#define SMM_IO_LENGTH_DWORD 0x04\r
\r
///\r
/// SMRAM Save State Map IOMisc I/O Instruction Type Values\r
///\r
-#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
-#define SMM_IO_TYPE_IN_DX 0x1\r
-#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
-#define SMM_IO_TYPE_OUT_DX 0x0\r
-#define SMM_IO_TYPE_INS 0x3\r
-#define SMM_IO_TYPE_OUTS 0x2\r
-#define SMM_IO_TYPE_REP_INS 0x7\r
-#define SMM_IO_TYPE_REP_OUTS 0x6\r
+#define SMM_IO_TYPE_IN_IMMEDIATE 0x9\r
+#define SMM_IO_TYPE_IN_DX 0x1\r
+#define SMM_IO_TYPE_OUT_IMMEDIATE 0x8\r
+#define SMM_IO_TYPE_OUT_DX 0x0\r
+#define SMM_IO_TYPE_INS 0x3\r
+#define SMM_IO_TYPE_OUTS 0x2\r
+#define SMM_IO_TYPE_REP_INS 0x7\r
+#define SMM_IO_TYPE_REP_OUTS 0x6\r
\r
///\r
/// SMRAM Save State Map IOMisc structure\r
///\r
typedef union {\r
struct {\r
- UINT32 SmiFlag:1;\r
- UINT32 Length:3;\r
- UINT32 Type:4;\r
- UINT32 Reserved1:8;\r
- UINT32 Port:16;\r
+ UINT32 SmiFlag : 1;\r
+ UINT32 Length : 3;\r
+ UINT32 Type : 4;\r
+ UINT32 Reserved1 : 8;\r
+ UINT32 Port : 16;\r
} Bits;\r
- UINT32 Uint32;\r
+ UINT32 Uint32;\r
} SMRAM_SAVE_STATE_IOMISC;\r
\r
#pragma pack ()\r
**/\r
\r
typedef struct {\r
- UINT32 Intel64ModeSupported :1; ///> bitfield\r
- UINT32 EptSupported :1; ///> bitfield\r
- UINT32 Reserved :30; ///> must be 0\r
+ UINT32 Intel64ModeSupported : 1; /// > bitfield\r
+ UINT32 EptSupported : 1; /// > bitfield\r
+ UINT32 Reserved : 30; /// > must be 0\r
} STM_FEAT;\r
\r
#define STM_SPEC_VERSION_MAJOR 1\r
#define STM_SPEC_VERSION_MINOR 0\r
\r
typedef struct {\r
- UINT8 StmSpecVerMajor;\r
- UINT8 StmSpecVerMinor;\r
+ UINT8 StmSpecVerMajor;\r
+ UINT8 StmSpecVerMinor;\r
///\r
/// Must be zero\r
///\r
- UINT16 Reserved;\r
- UINT32 StaticImageSize;\r
- UINT32 PerProcDynamicMemorySize;\r
- UINT32 AdditionalDynamicMemorySize;\r
- STM_FEAT StmFeatures;\r
- UINT32 NumberOfRevIDs;\r
- UINT32 StmSmmRevID[1];\r
+ UINT16 Reserved;\r
+ UINT32 StaticImageSize;\r
+ UINT32 PerProcDynamicMemorySize;\r
+ UINT32 AdditionalDynamicMemorySize;\r
+ STM_FEAT StmFeatures;\r
+ UINT32 NumberOfRevIDs;\r
+ UINT32 StmSmmRevID[1];\r
///\r
/// The total STM_HEADER should be 4K.\r
///\r
} SOFTWARE_STM_HEADER;\r
\r
typedef struct {\r
- MSEG_HEADER HwStmHdr;\r
- SOFTWARE_STM_HEADER SwStmHdr;\r
+ MSEG_HEADER HwStmHdr;\r
+ SOFTWARE_STM_HEADER SwStmHdr;\r
} STM_HEADER;\r
\r
-\r
/**\r
VMCALL API Numbers\r
API number convention: BIOS facing VMCALL interfaces have bit 16 clear\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_MAP_ADDRESS_RANGE 0x00000001\r
+#define STM_API_MAP_ADDRESS_RANGE 0x00000001\r
\r
/**\r
STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL\r
**/\r
typedef struct {\r
- UINT64 PhysicalAddress;\r
- UINT64 VirtualAddress;\r
- UINT32 PageCount;\r
- UINT32 PatCacheType;\r
+ UINT64 PhysicalAddress;\r
+ UINT64 VirtualAddress;\r
+ UINT32 PageCount;\r
+ UINT32 PatCacheType;\r
} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;\r
\r
/**\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002\r
+#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002\r
\r
/**\r
STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL\r
**/\r
typedef struct {\r
- UINT64 VirtualAddress;\r
- UINT32 Length;\r
+ UINT64 VirtualAddress;\r
+ UINT32 Length;\r
} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;\r
\r
-\r
/**\r
Since the normal OS environment runs with a different set of page tables than\r
the SMM guest, virtual mappings will certainly be different. In order to do a\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_ADDRESS_LOOKUP 0x00000003\r
+#define STM_API_ADDRESS_LOOKUP 0x00000003\r
\r
/**\r
STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL\r
**/\r
typedef struct {\r
- UINT64 InterruptedGuestVirtualAddress;\r
- UINT32 Length;\r
- UINT64 InterruptedCr3;\r
- UINT64 InterruptedEptp;\r
- UINT32 MapToSmmGuest:2;\r
- UINT32 InterruptedCr4Pae:1;\r
- UINT32 InterruptedCr4Pse:1;\r
- UINT32 InterruptedIa32eMode:1;\r
- UINT32 Reserved1:27;\r
- UINT32 Reserved2;\r
- UINT64 PhysicalAddress;\r
- UINT64 SmmGuestVirtualAddress;\r
+ UINT64 InterruptedGuestVirtualAddress;\r
+ UINT32 Length;\r
+ UINT64 InterruptedCr3;\r
+ UINT64 InterruptedEptp;\r
+ UINT32 MapToSmmGuest : 2;\r
+ UINT32 InterruptedCr4Pae : 1;\r
+ UINT32 InterruptedCr4Pse : 1;\r
+ UINT32 InterruptedIa32eMode : 1;\r
+ UINT32 Reserved1 : 27;\r
+ UINT32 Reserved2;\r
+ UINT64 PhysicalAddress;\r
+ UINT64 SmmGuestVirtualAddress;\r
} STM_ADDRESS_LOOKUP_DESCRIPTOR;\r
\r
/**\r
#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED 3\r
/// @}\r
\r
-\r
/**\r
When returning from a protection exception (see section 6.2), the SMM guest\r
can instruct the STM to take one of two paths. It can either request a value\r
Values 0x10..0xFFFFFFFF are reserved, do not use.\r
\r
**/\r
-#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004\r
-\r
+#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004\r
\r
/**\r
VMCALL API Numbers\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_START (BIT16 | 1)\r
+#define STM_API_START (BIT16 | 1)\r
\r
/**\r
Bit values for EDX input parameter to #STM_API_START VMCALL\r
#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF BIT0\r
/// @}\r
\r
-\r
/**\r
The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is\r
normally done as part of a full teardown of the SMX environment when the\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_STOP (BIT16 | 2)\r
-\r
+#define STM_API_STOP (BIT16 | 2)\r
\r
/**\r
The ProtectResourceVMCALL() is invoked by the MLE root to request protection\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_PROTECT_RESOURCE (BIT16 | 3)\r
-\r
+#define STM_API_PROTECT_RESOURCE (BIT16 | 3)\r
\r
/**\r
The UnProtectResourceVMCALL() is invoked by the MLE root to request that the\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)\r
-\r
+#define STM_API_UNPROTECT_RESOURCE (BIT16 | 4)\r
\r
/**\r
The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)\r
-\r
+#define STM_API_GET_BIOS_RESOURCES (BIT16 | 5)\r
\r
/**\r
The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)\r
+#define STM_API_MANAGE_VMCS_DATABASE (BIT16 | 6)\r
\r
/**\r
STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL\r
///\r
/// bits 11:0 are reserved and must be 0\r
///\r
- UINT64 VmcsPhysPointer;\r
- UINT32 DomainType :4;\r
- UINT32 XStatePolicy :2;\r
- UINT32 DegradationPolicy :4;\r
+ UINT64 VmcsPhysPointer;\r
+ UINT32 DomainType : 4;\r
+ UINT32 XStatePolicy : 2;\r
+ UINT32 DegradationPolicy : 4;\r
///\r
/// Must be 0\r
///\r
- UINT32 Reserved1 :22;\r
- UINT32 AddOrRemove;\r
+ UINT32 Reserved1 : 22;\r
+ UINT32 AddOrRemove;\r
} STM_VMCS_DATABASE_REQUEST;\r
\r
/**\r
#define STM_VMCS_DATABASE_REQUEST_REMOVE 0\r
/// @}\r
\r
-\r
/**\r
InitializeProtectionVMCALL() prepares the STM for setup of the initial\r
protection profile which is subsequently communicated via one or more\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)\r
+#define STM_API_INITIALIZE_PROTECTION (BIT16 | 7)\r
\r
/**\r
Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION\r
#define STM_RSC_MSR BIT3\r
/// @}\r
\r
-\r
/**\r
The ManageEventLogVMCALL() is invoked by the MLE root to control the logging\r
feature. It consists of several sub-functions to facilitate establishment of\r
\r
@note All other registers unmodified.\r
**/\r
-#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)\r
+#define STM_API_MANAGE_EVENT_LOG (BIT16 | 8)\r
\r
///\r
/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL\r
///\r
typedef struct {\r
- UINT32 SubFunctionIndex;\r
+ UINT32 SubFunctionIndex;\r
union {\r
struct {\r
- UINT32 PageCount;\r
+ UINT32 PageCount;\r
//\r
// number of elements is PageCount\r
//\r
- UINT64 Pages[];\r
+ UINT64 Pages[];\r
} LogBuffer;\r
//\r
// bitmap of EVENT_TYPE\r
Log Entry Header\r
**/\r
typedef struct {\r
- UINT32 EventSerialNumber;\r
- UINT16 Type;\r
- UINT16 Lock :1;\r
- UINT16 Valid :1;\r
- UINT16 ReadByMle :1;\r
- UINT16 Wrapped :1;\r
- UINT16 Reserved :12;\r
+ UINT32 EventSerialNumber;\r
+ UINT16 Type;\r
+ UINT16 Lock : 1;\r
+ UINT16 Valid : 1;\r
+ UINT16 ReadByMle : 1;\r
+ UINT16 Wrapped : 1;\r
+ UINT16 Reserved : 12;\r
} LOG_ENTRY_HEADER;\r
\r
/**\r
} EVENT_TYPE;\r
\r
typedef struct {\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
} ENTRY_EVT_LOG_STARTED;\r
\r
typedef struct {\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
} ENTRY_EVT_LOG_STOPPED;\r
\r
typedef struct {\r
- UINT32 VmcallApiNumber;\r
+ UINT32 VmcallApiNumber;\r
} ENTRY_EVT_LOG_INVALID_PARAM;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_MLE_RSC_PROT_GRANTED;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_MLE_RSC_PROT_DENIED;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_MLE_RSC_UNPROT;\r
\r
typedef struct {\r
- STM_RSC Resource;\r
+ STM_RSC Resource;\r
} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;\r
\r
typedef struct {\r
- UINT64 VmcsPhysPointer;\r
- UINT8 ExpectedDomainType;\r
- UINT8 DegradedDomainType;\r
+ UINT64 VmcsPhysPointer;\r
+ UINT8 ExpectedDomainType;\r
+ UINT8 DegradedDomainType;\r
} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;\r
\r
typedef union {\r
- ENTRY_EVT_LOG_STARTED Started;\r
- ENTRY_EVT_LOG_STOPPED Stopped;\r
- ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;\r
- ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;\r
- ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;\r
- ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;\r
- ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;\r
- ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;\r
- ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;\r
- ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;\r
+ ENTRY_EVT_LOG_STARTED Started;\r
+ ENTRY_EVT_LOG_STOPPED Stopped;\r
+ ENTRY_EVT_LOG_INVALID_PARAM InvalidParam;\r
+ ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION HandledProtectionException;\r
+ ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC BiosUnclaimedRsc;\r
+ ENTRY_EVT_MLE_RSC_PROT_GRANTED MleRscProtGranted;\r
+ ENTRY_EVT_MLE_RSC_PROT_DENIED MleRscProtDenied;\r
+ ENTRY_EVT_MLE_RSC_UNPROT MleRscUnprot;\r
+ ENTRY_EVT_MLE_RSC_UNPROT_ERROR MleRscUnprotError;\r
+ ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED MleDomainTypeDegraded;\r
} LOG_ENTRY_DATA;\r
\r
typedef struct {\r
- LOG_ENTRY_HEADER Hdr;\r
- LOG_ENTRY_DATA Data;\r
+ LOG_ENTRY_HEADER Hdr;\r
+ LOG_ENTRY_DATA Data;\r
} STM_LOG_ENTRY;\r
\r
/**\r
**/\r
#define STM_LOG_ENTRY_SIZE 256\r
\r
-\r
/**\r
STM Protection Exception Stack Frame Structures\r
**/\r
\r
typedef struct {\r
- UINT32 Rdi;\r
- UINT32 Rsi;\r
- UINT32 Rbp;\r
- UINT32 Rdx;\r
- UINT32 Rcx;\r
- UINT32 Rbx;\r
- UINT32 Rax;\r
- UINT32 Cr3;\r
- UINT32 Cr2;\r
- UINT32 Cr0;\r
- UINT32 VmcsExitInstructionInfo;\r
- UINT32 VmcsExitInstructionLength;\r
- UINT64 VmcsExitQualification;\r
+ UINT32 Rdi;\r
+ UINT32 Rsi;\r
+ UINT32 Rbp;\r
+ UINT32 Rdx;\r
+ UINT32 Rcx;\r
+ UINT32 Rbx;\r
+ UINT32 Rax;\r
+ UINT32 Cr3;\r
+ UINT32 Cr2;\r
+ UINT32 Cr0;\r
+ UINT32 VmcsExitInstructionInfo;\r
+ UINT32 VmcsExitInstructionLength;\r
+ UINT64 VmcsExitQualification;\r
///\r
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
///\r
- UINT32 ErrorCode;\r
- UINT32 Rip;\r
- UINT32 Cs;\r
- UINT32 Rflags;\r
- UINT32 Rsp;\r
- UINT32 Ss;\r
+ UINT32 ErrorCode;\r
+ UINT32 Rip;\r
+ UINT32 Cs;\r
+ UINT32 Rflags;\r
+ UINT32 Rsp;\r
+ UINT32 Ss;\r
} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;\r
\r
typedef struct {\r
- UINT64 R15;\r
- UINT64 R14;\r
- UINT64 R13;\r
- UINT64 R12;\r
- UINT64 R11;\r
- UINT64 R10;\r
- UINT64 R9;\r
- UINT64 R8;\r
- UINT64 Rdi;\r
- UINT64 Rsi;\r
- UINT64 Rbp;\r
- UINT64 Rdx;\r
- UINT64 Rcx;\r
- UINT64 Rbx;\r
- UINT64 Rax;\r
- UINT64 Cr8;\r
- UINT64 Cr3;\r
- UINT64 Cr2;\r
- UINT64 Cr0;\r
- UINT64 VmcsExitInstructionInfo;\r
- UINT64 VmcsExitInstructionLength;\r
- UINT64 VmcsExitQualification;\r
+ UINT64 R15;\r
+ UINT64 R14;\r
+ UINT64 R13;\r
+ UINT64 R12;\r
+ UINT64 R11;\r
+ UINT64 R10;\r
+ UINT64 R9;\r
+ UINT64 R8;\r
+ UINT64 Rdi;\r
+ UINT64 Rsi;\r
+ UINT64 Rbp;\r
+ UINT64 Rdx;\r
+ UINT64 Rcx;\r
+ UINT64 Rbx;\r
+ UINT64 Rax;\r
+ UINT64 Cr8;\r
+ UINT64 Cr3;\r
+ UINT64 Cr2;\r
+ UINT64 Cr0;\r
+ UINT64 VmcsExitInstructionInfo;\r
+ UINT64 VmcsExitInstructionLength;\r
+ UINT64 VmcsExitQualification;\r
///\r
/// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value\r
///\r
- UINT64 ErrorCode;\r
- UINT64 Rip;\r
- UINT64 Cs;\r
- UINT64 Rflags;\r
- UINT64 Rsp;\r
- UINT64 Ss;\r
+ UINT64 ErrorCode;\r
+ UINT64 Rip;\r
+ UINT64 Cs;\r
+ UINT64 Rflags;\r
+ UINT64 Rsp;\r
+ UINT64 Ss;\r
} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;\r
\r
typedef union {\r
- STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;\r
- STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;\r
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *Ia32StackFrame;\r
+ STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *X64StackFrame;\r
} STM_PROTECTION_EXCEPTION_STACK_FRAME;\r
\r
/**\r
**/\r
\r
typedef struct {\r
- UINT64 SpeRip;\r
- UINT64 SpeRsp;\r
- UINT16 SpeSs;\r
- UINT16 PageViolationException:1;\r
- UINT16 MsrViolationException:1;\r
- UINT16 RegisterViolationException:1;\r
- UINT16 IoViolationException:1;\r
- UINT16 PciViolationException:1;\r
- UINT16 Reserved1:11;\r
- UINT32 Reserved2;\r
+ UINT64 SpeRip;\r
+ UINT64 SpeRsp;\r
+ UINT16 SpeSs;\r
+ UINT16 PageViolationException : 1;\r
+ UINT16 MsrViolationException : 1;\r
+ UINT16 RegisterViolationException : 1;\r
+ UINT16 IoViolationException : 1;\r
+ UINT16 PciViolationException : 1;\r
+ UINT16 Reserved1 : 11;\r
+ UINT32 Reserved2;\r
} STM_PROTECTION_EXCEPTION_HANDLER;\r
\r
typedef struct {\r
- UINT8 ExecutionDisableOutsideSmrr:1;\r
- UINT8 Intel64Mode:1;\r
- UINT8 Cr4Pae : 1;\r
- UINT8 Cr4Pse : 1;\r
- UINT8 Reserved1 : 4;\r
+ UINT8 ExecutionDisableOutsideSmrr : 1;\r
+ UINT8 Intel64Mode : 1;\r
+ UINT8 Cr4Pae : 1;\r
+ UINT8 Cr4Pse : 1;\r
+ UINT8 Reserved1 : 4;\r
} STM_SMM_ENTRY_STATE;\r
\r
typedef struct {\r
- UINT8 SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint\r
- UINT8 ReinitializeVmcsRequired : 1; ///> BIOS request\r
- UINT8 Reserved2 : 6;\r
+ UINT8 SmramToVmcsRestoreRequired : 1; /// > BIOS restore hint\r
+ UINT8 ReinitializeVmcsRequired : 1; /// > BIOS request\r
+ UINT8 Reserved2 : 6;\r
} STM_SMM_RESUME_STATE;\r
\r
typedef struct {\r
- UINT8 DomainType : 4; ///> STM input to BIOS on each SMI\r
- UINT8 XStatePolicy : 2; ///> STM input to BIOS on each SMI\r
- UINT8 EptEnabled : 1;\r
- UINT8 Reserved3 : 1;\r
+ UINT8 DomainType : 4; /// > STM input to BIOS on each SMI\r
+ UINT8 XStatePolicy : 2; /// > STM input to BIOS on each SMI\r
+ UINT8 EptEnabled : 1;\r
+ UINT8 Reserved3 : 1;\r
} STM_SMM_STATE;\r
\r
#define TXT_SMM_PSD_OFFSET 0xfb00\r
#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0\r
\r
typedef struct {\r
- UINT64 Signature;\r
- UINT16 Size;\r
- UINT8 SmmDescriptorVerMajor;\r
- UINT8 SmmDescriptorVerMinor;\r
- UINT32 LocalApicId;\r
- STM_SMM_ENTRY_STATE SmmEntryState;\r
- STM_SMM_RESUME_STATE SmmResumeState;\r
- STM_SMM_STATE StmSmmState;\r
- UINT8 Reserved4;\r
- UINT16 SmmCs;\r
- UINT16 SmmDs;\r
- UINT16 SmmSs;\r
- UINT16 SmmOtherSegment;\r
- UINT16 SmmTr;\r
- UINT16 Reserved5;\r
- UINT64 SmmCr3;\r
- UINT64 SmmStmSetupRip;\r
- UINT64 SmmStmTeardownRip;\r
- UINT64 SmmSmiHandlerRip;\r
- UINT64 SmmSmiHandlerRsp;\r
- UINT64 SmmGdtPtr;\r
- UINT32 SmmGdtSize;\r
- UINT32 RequiredStmSmmRevId;\r
- STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;\r
- UINT64 Reserved6;\r
- UINT64 BiosHwResourceRequirementsPtr;\r
+ UINT64 Signature;\r
+ UINT16 Size;\r
+ UINT8 SmmDescriptorVerMajor;\r
+ UINT8 SmmDescriptorVerMinor;\r
+ UINT32 LocalApicId;\r
+ STM_SMM_ENTRY_STATE SmmEntryState;\r
+ STM_SMM_RESUME_STATE SmmResumeState;\r
+ STM_SMM_STATE StmSmmState;\r
+ UINT8 Reserved4;\r
+ UINT16 SmmCs;\r
+ UINT16 SmmDs;\r
+ UINT16 SmmSs;\r
+ UINT16 SmmOtherSegment;\r
+ UINT16 SmmTr;\r
+ UINT16 Reserved5;\r
+ UINT64 SmmCr3;\r
+ UINT64 SmmStmSetupRip;\r
+ UINT64 SmmStmTeardownRip;\r
+ UINT64 SmmSmiHandlerRip;\r
+ UINT64 SmmSmiHandlerRsp;\r
+ UINT64 SmmGdtPtr;\r
+ UINT32 SmmGdtSize;\r
+ UINT32 RequiredStmSmmRevId;\r
+ STM_PROTECTION_EXCEPTION_HANDLER StmProtectionExceptionHandler;\r
+ UINT64 Reserved6;\r
+ UINT64 BiosHwResourceRequirementsPtr;\r
// extend area\r
- UINT64 AcpiRsdp;\r
- UINT8 PhysicalAddressBits;\r
+ UINT64 AcpiRsdp;\r
+ UINT8 PhysicalAddressBits;\r
} TXT_PROCESSOR_SMM_DESCRIPTOR;\r
\r
#pragma pack ()\r
STM Resource Descriptor Header\r
**/\r
typedef struct {\r
- UINT32 RscType;\r
- UINT16 Length;\r
- UINT16 ReturnStatus:1;\r
- UINT16 Reserved:14;\r
- UINT16 IgnoreResource:1;\r
+ UINT32 RscType;\r
+ UINT16 Length;\r
+ UINT16 ReturnStatus : 1;\r
+ UINT16 Reserved : 14;\r
+ UINT16 IgnoreResource : 1;\r
} STM_RSC_DESC_HEADER;\r
\r
/**\r
STM Resource End Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 ResourceListContinuation;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 ResourceListContinuation;\r
} STM_RSC_END;\r
\r
/**\r
STM Resource Memory Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT32 RWXAttributes:3;\r
- UINT32 Reserved:29;\r
- UINT32 Reserved_2;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT32 RWXAttributes : 3;\r
+ UINT32 Reserved : 29;\r
+ UINT32 Reserved_2;\r
} STM_RSC_MEM_DESC;\r
\r
/**\r
STM Resource I/O Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT32 Reserved;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT32 Reserved;\r
} STM_RSC_IO_DESC;\r
\r
/**\r
STM Resource MMIO Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT64 Base;\r
- UINT64 Length;\r
- UINT32 RWXAttributes:3;\r
- UINT32 Reserved:29;\r
- UINT32 Reserved_2;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT32 RWXAttributes : 3;\r
+ UINT32 Reserved : 29;\r
+ UINT32 Reserved_2;\r
} STM_RSC_MMIO_DESC;\r
\r
/**\r
STM Resource MSR Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT32 MsrIndex;\r
- UINT32 KernelModeProcessing:1;\r
- UINT32 Reserved:31;\r
- UINT64 ReadMask;\r
- UINT64 WriteMask;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT32 MsrIndex;\r
+ UINT32 KernelModeProcessing : 1;\r
+ UINT32 Reserved : 31;\r
+ UINT64 ReadMask;\r
+ UINT64 WriteMask;\r
} STM_RSC_MSR_DESC;\r
\r
/**\r
///\r
/// Must be 1, indicating Hardware Device Path\r
///\r
- UINT8 Type;\r
+ UINT8 Type;\r
///\r
/// Must be 1, indicating PCI\r
///\r
- UINT8 Subtype;\r
+ UINT8 Subtype;\r
///\r
/// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6\r
///\r
- UINT16 Length;\r
- UINT8 PciFunction;\r
- UINT8 PciDevice;\r
+ UINT16 Length;\r
+ UINT8 PciFunction;\r
+ UINT8 PciDevice;\r
} STM_PCI_DEVICE_PATH_NODE;\r
\r
/**\r
STM Resource PCI Configuration Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 RWAttributes:2;\r
- UINT16 Reserved:14;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT8 OriginatingBusNumber;\r
- UINT8 LastNodeIndex;\r
- STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r
-//STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 RWAttributes : 2;\r
+ UINT16 Reserved : 14;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT8 OriginatingBusNumber;\r
+ UINT8 LastNodeIndex;\r
+ STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];\r
+ // STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1];\r
} STM_RSC_PCI_CFG_DESC;\r
\r
/**\r
STM Resource Trapped I/O Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT16 Base;\r
- UINT16 Length;\r
- UINT16 In:1;\r
- UINT16 Out:1;\r
- UINT16 Api:1;\r
- UINT16 Reserved1:13;\r
- UINT16 Reserved2;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT16 Base;\r
+ UINT16 Length;\r
+ UINT16 In : 1;\r
+ UINT16 Out : 1;\r
+ UINT16 Api : 1;\r
+ UINT16 Reserved1 : 13;\r
+ UINT16 Reserved2;\r
} STM_RSC_TRAPPED_IO_DESC;\r
\r
/**\r
STM Resource All Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
+ STM_RSC_DESC_HEADER Hdr;\r
} STM_RSC_ALL_RESOURCES_DESC;\r
\r
/**\r
STM Register Violation Descriptor\r
**/\r
typedef struct {\r
- STM_RSC_DESC_HEADER Hdr;\r
- UINT32 RegisterType;\r
- UINT32 Reserved;\r
- UINT64 ReadMask;\r
- UINT64 WriteMask;\r
+ STM_RSC_DESC_HEADER Hdr;\r
+ UINT32 RegisterType;\r
+ UINT32 Reserved;\r
+ UINT64 ReadMask;\r
+ UINT64 WriteMask;\r
} STM_REGISTER_VIOLATION_DESC;\r
\r
/**\r
Union of all STM resource types\r
**/\r
typedef union {\r
- STM_RSC_DESC_HEADER Header;\r
- STM_RSC_END End;\r
- STM_RSC_MEM_DESC Mem;\r
- STM_RSC_IO_DESC Io;\r
- STM_RSC_MMIO_DESC Mmio;\r
- STM_RSC_MSR_DESC Msr;\r
- STM_RSC_PCI_CFG_DESC PciCfg;\r
- STM_RSC_TRAPPED_IO_DESC TrappedIo;\r
- STM_RSC_ALL_RESOURCES_DESC All;\r
- STM_REGISTER_VIOLATION_DESC RegisterViolation;\r
+ STM_RSC_DESC_HEADER Header;\r
+ STM_RSC_END End;\r
+ STM_RSC_MEM_DESC Mem;\r
+ STM_RSC_IO_DESC Io;\r
+ STM_RSC_MMIO_DESC Mmio;\r
+ STM_RSC_MSR_DESC Msr;\r
+ STM_RSC_PCI_CFG_DESC PciCfg;\r
+ STM_RSC_TRAPPED_IO_DESC TrappedIo;\r
+ STM_RSC_ALL_RESOURCES_DESC All;\r
+ STM_REGISTER_VIOLATION_DESC RegisterViolation;\r
} STM_RSC;\r
\r
#pragma pack ()\r
/**\r
STM Status Codes\r
**/\r
-typedef UINT32 STM_STATUS;\r
+typedef UINT32 STM_STATUS;\r
\r
/**\r
Success code have BIT31 clear.\r
//\r
// Make sure we are using the correct packing rules per EFI specification\r
//\r
-#if !defined(__GNUC__)\r
-#pragma pack()\r
+#if !defined (__GNUC__)\r
+ #pragma pack()\r
#endif\r
\r
///\r
/// 8-byte unsigned value\r
///\r
-typedef unsigned long long UINT64 __attribute__ ((aligned (8)));\r
+typedef unsigned long long UINT64 __attribute__ ((aligned (8)));\r
///\r
/// 8-byte signed value\r
///\r
-typedef long long INT64 __attribute__ ((aligned (8)));\r
+typedef long long INT64 __attribute__ ((aligned (8)));\r
///\r
/// 4-byte unsigned value\r
///\r
-typedef unsigned int UINT32 __attribute__ ((aligned (4)));\r
+typedef unsigned int UINT32 __attribute__ ((aligned (4)));\r
///\r
/// 4-byte signed value\r
///\r
-typedef int INT32 __attribute__ ((aligned (4)));\r
+typedef int INT32 __attribute__ ((aligned (4)));\r
///\r
/// 2-byte unsigned value\r
///\r
-typedef unsigned short UINT16 __attribute__ ((aligned (2)));\r
+typedef unsigned short UINT16 __attribute__ ((aligned (2)));\r
///\r
/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
///\r
-typedef unsigned short CHAR16 __attribute__ ((aligned (2)));\r
+typedef unsigned short CHAR16 __attribute__ ((aligned (2)));\r
///\r
/// 2-byte signed value\r
///\r
-typedef short INT16 __attribute__ ((aligned (2)));\r
+typedef short INT16 __attribute__ ((aligned (2)));\r
///\r
/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
/// values are undefined.\r
///\r
-typedef unsigned char BOOLEAN;\r
+typedef unsigned char BOOLEAN;\r
///\r
/// 1-byte unsigned value\r
///\r
-typedef unsigned char UINT8;\r
+typedef unsigned char UINT8;\r
///\r
/// 1-byte Character\r
///\r
-typedef char CHAR8;\r
+typedef char CHAR8;\r
///\r
/// 1-byte signed value\r
///\r
-typedef signed char INT8;\r
+typedef signed char INT8;\r
///\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef UINT64 UINTN __attribute__ ((aligned (8)));\r
+typedef UINT64 UINTN __attribute__ ((aligned (8)));\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef INT64 INTN __attribute__ ((aligned (8)));\r
+typedef INT64 INTN __attribute__ ((aligned (8)));\r
\r
//\r
// Processor specific defines\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x8000000000000000ULL\r
+#define MAX_BIT 0x8000000000000000ULL\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
///\r
/// Maximum legal RV64 address\r
///\r
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
\r
///\r
/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)\r
///\r
-#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL\r
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL\r
\r
///\r
/// Maximum legal RISC-V INTN and UINTN values.\r
///\r
/// The stack alignment required for RISC-V\r
///\r
-#define CPU_STACK_ALIGNMENT 16\r
+#define CPU_STACK_ALIGNMENT 16\r
\r
///\r
/// Page allocation granularity for RISC-V\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
\r
//\r
// Modifier to ensure that all protocol member functions and EFI intrinsics\r
// EFI intrinsics are required to modify their member functions with EFIAPI.\r
//\r
#ifdef EFIAPI\r
- ///\r
- /// If EFIAPI is already defined, then we use that definition.\r
- ///\r
-#elif defined(__GNUC__)\r
- ///\r
- /// Define the standard calling convention regardless of optimization level\r
- /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI\r
- /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)\r
- /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for\r
- /// x64. Warning the assembly code in the MDE x64 does not follow the correct\r
- /// ABI for the standard x64 (x86-64) GCC.\r
- ///\r
- #define EFIAPI\r
+///\r
+/// If EFIAPI is already defined, then we use that definition.\r
+///\r
+#elif defined (__GNUC__)\r
+///\r
+/// Define the standard calling convention regardless of optimization level\r
+/// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI\r
+/// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)\r
+/// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for\r
+/// x64. Warning the assembly code in the MDE x64 does not follow the correct\r
+/// ABI for the standard x64 (x86-64) GCC.\r
+///\r
+#define EFIAPI\r
#else\r
- ///\r
- /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
- /// is the standard.\r
- ///\r
- #define EFIAPI\r
+///\r
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
+/// is the standard.\r
+///\r
+#define EFIAPI\r
#endif\r
\r
-#if defined(__GNUC__)\r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
+#if defined (__GNUC__)\r
+///\r
+/// For GNU assembly code, .global or .globl can declare global symbols.\r
+/// Define this macro to unify the usage.\r
+///\r
+#define ASM_GLOBAL .globl\r
#endif\r
\r
/**\r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
#define __USER_LABEL_PREFIX__\r
#include <Uefi/UefiSpec.h>\r
\r
#endif\r
-\r
\r
#pragma pack(1)\r
typedef struct {\r
- EFI_ACPI_DESCRIPTION_HEADER Header;\r
- GUID Identifier;\r
- UINT16 DataOffset;\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ GUID Identifier;\r
+ UINT16 DataOffset;\r
} EFI_ACPI_DATA_TABLE;\r
#pragma pack()\r
\r
#endif\r
-\r
///\r
/// 128-bit buffer containing a unique identifier value.\r
///\r
-typedef GUID EFI_GUID;\r
+typedef GUID EFI_GUID;\r
///\r
/// Function return status for EFI API.\r
///\r
-typedef RETURN_STATUS EFI_STATUS;\r
+typedef RETURN_STATUS EFI_STATUS;\r
///\r
/// A collection of related interfaces.\r
///\r
-typedef VOID *EFI_HANDLE;\r
+typedef VOID *EFI_HANDLE;\r
///\r
/// Handle to an event structure.\r
///\r
-typedef VOID *EFI_EVENT;\r
+typedef VOID *EFI_EVENT;\r
///\r
/// Task priority level.\r
///\r
-typedef UINTN EFI_TPL;\r
+typedef UINTN EFI_TPL;\r
///\r
/// Logical block address.\r
///\r
-typedef UINT64 EFI_LBA;\r
+typedef UINT64 EFI_LBA;\r
\r
///\r
/// 64-bit physical memory address.\r
///\r
-typedef UINT64 EFI_PHYSICAL_ADDRESS;\r
+typedef UINT64 EFI_PHYSICAL_ADDRESS;\r
\r
///\r
/// 64-bit virtual memory address.\r
///\r
-typedef UINT64 EFI_VIRTUAL_ADDRESS;\r
+typedef UINT64 EFI_VIRTUAL_ADDRESS;\r
\r
///\r
/// EFI Time Abstraction:\r
/// TimeZone: -1440 to 1440 or 2047\r
///\r
typedef struct {\r
- UINT16 Year;\r
- UINT8 Month;\r
- UINT8 Day;\r
- UINT8 Hour;\r
- UINT8 Minute;\r
- UINT8 Second;\r
- UINT8 Pad1;\r
- UINT32 Nanosecond;\r
- INT16 TimeZone;\r
- UINT8 Daylight;\r
- UINT8 Pad2;\r
+ UINT16 Year;\r
+ UINT8 Month;\r
+ UINT8 Day;\r
+ UINT8 Hour;\r
+ UINT8 Minute;\r
+ UINT8 Second;\r
+ UINT8 Pad1;\r
+ UINT32 Nanosecond;\r
+ INT16 TimeZone;\r
+ UINT8 Daylight;\r
+ UINT8 Pad2;\r
} EFI_TIME;\r
\r
-\r
///\r
/// 4-byte buffer. An IPv4 internet protocol address.\r
///\r
/// 32-byte buffer containing a network Media Access Control address.\r
///\r
typedef struct {\r
- UINT8 Addr[32];\r
+ UINT8 Addr[32];\r
} EFI_MAC_ADDRESS;\r
\r
///\r
/// An IPv4 or IPv6 internet protocol address.\r
///\r
typedef union {\r
- UINT32 Addr[4];\r
- EFI_IPv4_ADDRESS v4;\r
- EFI_IPv6_ADDRESS v6;\r
+ UINT32 Addr[4];\r
+ EFI_IPv4_ADDRESS v4;\r
+ EFI_IPv6_ADDRESS v6;\r
} EFI_IP_ADDRESS;\r
\r
-\r
///\r
/// Enumeration of EFI_STATUS.\r
///@{\r
#define EFI_COMPROMISED_DATA RETURN_COMPROMISED_DATA\r
#define EFI_HTTP_ERROR RETURN_HTTP_ERROR\r
\r
-#define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH\r
-#define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE\r
-#define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE\r
-#define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL\r
-#define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA\r
-#define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM\r
+#define EFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH\r
+#define EFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE\r
+#define EFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE\r
+#define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL\r
+#define EFI_WARN_STALE_DATA RETURN_WARN_STALE_DATA\r
+#define EFI_WARN_FILE_SYSTEM RETURN_WARN_FILE_SYSTEM\r
///@}\r
\r
///\r
/// Define macro to encode the status code.\r
///\r
-#define EFIERR(_a) ENCODE_ERROR(_a)\r
+#define EFIERR(_a) ENCODE_ERROR(_a)\r
\r
-#define EFI_ERROR(A) RETURN_ERROR(A)\r
+#define EFI_ERROR(A) RETURN_ERROR(A)\r
\r
///\r
/// ICMP error definitions\r
///\r
/// Tcp connection status definitions\r
///@{\r
-#define EFI_CONNECTION_FIN EFIERR(104)\r
-#define EFI_CONNECTION_RESET EFIERR(105)\r
-#define EFI_CONNECTION_REFUSED EFIERR(106)\r
+#define EFI_CONNECTION_FIN EFIERR(104)\r
+#define EFI_CONNECTION_RESET EFIERR(105)\r
+#define EFI_CONNECTION_REFUSED EFIERR(106)\r
///@}\r
\r
//\r
// 4KB. This should in no way be confused with the page size of the processor.\r
// An EFI_PAGE is just the quanta of memory in EFI.\r
//\r
-#define EFI_PAGE_SIZE SIZE_4KB\r
-#define EFI_PAGE_MASK 0xFFF\r
-#define EFI_PAGE_SHIFT 12\r
+#define EFI_PAGE_SIZE SIZE_4KB\r
+#define EFI_PAGE_MASK 0xFFF\r
+#define EFI_PAGE_SHIFT 12\r
\r
/**\r
Macro that converts a size, in bytes, to a number of EFI_PAGESs.\r
///\r
/// PE32+ Machine type for IA32 UEFI images.\r
///\r
-#define EFI_IMAGE_MACHINE_IA32 0x014C\r
+#define EFI_IMAGE_MACHINE_IA32 0x014C\r
\r
///\r
/// PE32+ Machine type for IA64 UEFI images.\r
///\r
-#define EFI_IMAGE_MACHINE_IA64 0x0200\r
+#define EFI_IMAGE_MACHINE_IA64 0x0200\r
\r
///\r
/// PE32+ Machine type for EBC UEFI images.\r
///\r
-#define EFI_IMAGE_MACHINE_EBC 0x0EBC\r
+#define EFI_IMAGE_MACHINE_EBC 0x0EBC\r
\r
///\r
/// PE32+ Machine type for X64 UEFI images.\r
///\r
-#define EFI_IMAGE_MACHINE_X64 0x8664\r
+#define EFI_IMAGE_MACHINE_X64 0x8664\r
\r
///\r
/// PE32+ Machine type for ARM mixed ARM and Thumb/Thumb2 images.\r
#define EFI_IMAGE_MACHINE_RISCV64 0x5064\r
#define EFI_IMAGE_MACHINE_RISCV128 0x5128\r
\r
-#if !defined(EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined(EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
-#if defined (MDE_CPU_IA32)\r
+#if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
+ #if defined (MDE_CPU_IA32)\r
\r
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
((Machine) == EFI_IMAGE_MACHINE_IA32)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)\r
\r
-#elif defined (MDE_CPU_X64)\r
+ #elif defined (MDE_CPU_X64)\r
\r
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
((Machine) == EFI_IMAGE_MACHINE_X64)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)\r
\r
-#elif defined (MDE_CPU_ARM)\r
+ #elif defined (MDE_CPU_ARM)\r
\r
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
\r
-#elif defined (MDE_CPU_AARCH64)\r
+ #elif defined (MDE_CPU_AARCH64)\r
\r
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
((Machine) == EFI_IMAGE_MACHINE_AARCH64)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
\r
-#elif defined (MDE_CPU_RISCV64)\r
+ #elif defined (MDE_CPU_RISCV64)\r
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \\r
((Machine) == EFI_IMAGE_MACHINE_RISCV64)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
\r
-#elif defined (MDE_CPU_EBC)\r
+ #elif defined (MDE_CPU_EBC)\r
\r
///\r
/// This is just to make sure you can cross compile with the EBC compiler.\r
/// It does not make sense to have a PE loader coded in EBC.\r
///\r
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)\r
\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
\r
+ #else\r
+ #error Unknown Processor Type\r
+ #endif\r
#else\r
-#error Unknown Processor Type\r
-#endif\r
-#else\r
-#if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)\r
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)\r
-#else\r
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)\r
-#endif\r
-#if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
-#else\r
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
-#endif\r
+ #if defined (EFI_IMAGE_MACHINE_TYPE_VALUE)\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_TYPE_VALUE)\r
+ #else\r
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) (FALSE)\r
+ #endif\r
+ #if defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)\r
+ #else\r
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)\r
+ #endif\r
#endif\r
\r
#endif\r
/// The primary GUID Partition Table Header must be\r
/// located in LBA 1 (i.e., the second logical block).\r
///\r
-#define PRIMARY_PART_HEADER_LBA 1\r
+#define PRIMARY_PART_HEADER_LBA 1\r
///\r
/// EFI Partition Table Signature: "EFI PART".\r
///\r
-#define EFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T')\r
+#define EFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T')\r
///\r
/// Minimum bytes reserve for EFI entry array buffer.\r
///\r
-#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384\r
+#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384\r
\r
#pragma pack(1)\r
\r
/// The table header for the GPT partition Table.\r
/// This header contains EFI_PTAB_HEADER_ID.\r
///\r
- EFI_TABLE_HEADER Header;\r
+ EFI_TABLE_HEADER Header;\r
///\r
/// The LBA that contains this data structure.\r
///\r
- EFI_LBA MyLBA;\r
+ EFI_LBA MyLBA;\r
///\r
/// LBA address of the alternate GUID Partition Table Header.\r
///\r
- EFI_LBA AlternateLBA;\r
+ EFI_LBA AlternateLBA;\r
///\r
/// The first usable logical block that may be used\r
/// by a partition described by a GUID Partition Entry.\r
///\r
- EFI_LBA FirstUsableLBA;\r
+ EFI_LBA FirstUsableLBA;\r
///\r
/// The last usable logical block that may be used\r
/// by a partition described by a GUID Partition Entry.\r
///\r
- EFI_LBA LastUsableLBA;\r
+ EFI_LBA LastUsableLBA;\r
///\r
/// GUID that can be used to uniquely identify the disk.\r
///\r
- EFI_GUID DiskGUID;\r
+ EFI_GUID DiskGUID;\r
///\r
/// The starting LBA of the GUID Partition Entry array.\r
///\r
- EFI_LBA PartitionEntryLBA;\r
+ EFI_LBA PartitionEntryLBA;\r
///\r
/// The number of Partition Entries in the GUID Partition Entry array.\r
///\r
- UINT32 NumberOfPartitionEntries;\r
+ UINT32 NumberOfPartitionEntries;\r
///\r
/// The size, in bytes, of each the GUID Partition\r
/// Entry structures in the GUID Partition Entry\r
/// array. This field shall be set to a value of 128 x 2^n where n is\r
/// an integer greater than or equal to zero (e.g., 128, 256, 512, etc.).\r
///\r
- UINT32 SizeOfPartitionEntry;\r
+ UINT32 SizeOfPartitionEntry;\r
///\r
/// The CRC32 of the GUID Partition Entry array.\r
/// Starts at PartitionEntryLBA and is\r
/// computed over a byte length of\r
/// NumberOfPartitionEntries * SizeOfPartitionEntry.\r
///\r
- UINT32 PartitionEntryArrayCRC32;\r
+ UINT32 PartitionEntryArrayCRC32;\r
} EFI_PARTITION_TABLE_HEADER;\r
\r
///\r
/// Unique ID that defines the purpose and type of this Partition. A value of\r
/// zero defines that this partition entry is not being used.\r
///\r
- EFI_GUID PartitionTypeGUID;\r
+ EFI_GUID PartitionTypeGUID;\r
///\r
/// GUID that is unique for every partition entry. Every partition ever\r
/// created will have a unique GUID.\r
/// This GUID must be assigned when the GUID Partition Entry is created.\r
///\r
- EFI_GUID UniquePartitionGUID;\r
+ EFI_GUID UniquePartitionGUID;\r
///\r
/// Starting LBA of the partition defined by this entry\r
///\r
- EFI_LBA StartingLBA;\r
+ EFI_LBA StartingLBA;\r
///\r
/// Ending LBA of the partition defined by this entry.\r
///\r
- EFI_LBA EndingLBA;\r
+ EFI_LBA EndingLBA;\r
///\r
/// Attribute bits, all bits reserved by UEFI\r
/// Bit 0: If this bit is set, the partition is required for the platform to function. The owner/creator of the\r
\r
#pragma pack()\r
#endif\r
-\r
-\r
///\r
/// The following types are currently defined:\r
///\r
-typedef VOID* EFI_HII_HANDLE;\r
-typedef CHAR16* EFI_STRING;\r
+typedef VOID *EFI_HII_HANDLE;\r
+typedef CHAR16 *EFI_STRING;\r
typedef UINT16 EFI_IMAGE_ID;\r
typedef UINT16 EFI_QUESTION_ID;\r
typedef UINT16 EFI_STRING_ID;\r
typedef UINT16 EFI_VARSTORE_ID;\r
typedef UINT16 EFI_ANIMATION_ID;\r
\r
-typedef UINT16 EFI_DEFAULT_ID;\r
-\r
-typedef UINT32 EFI_HII_FONT_STYLE;\r
-\r
+typedef UINT16 EFI_DEFAULT_ID;\r
\r
+typedef UINT32 EFI_HII_FONT_STYLE;\r
\r
#pragma pack(1)\r
\r
/// The header found at the start of each package list.\r
///\r
typedef struct {\r
- EFI_GUID PackageListGuid;\r
- UINT32 PackageLength;\r
+ EFI_GUID PackageListGuid;\r
+ UINT32 PackageLength;\r
} EFI_HII_PACKAGE_LIST_HEADER;\r
\r
///\r
/// The header found at the start of each package.\r
///\r
typedef struct {\r
- UINT32 Length:24;\r
- UINT32 Type:8;\r
+ UINT32 Length : 24;\r
+ UINT32 Type : 8;\r
// UINT8 Data[...];\r
} EFI_HII_PACKAGE_HEADER;\r
\r
//\r
// Value of HII package type\r
//\r
-#define EFI_HII_PACKAGE_TYPE_ALL 0x00\r
-#define EFI_HII_PACKAGE_TYPE_GUID 0x01\r
-#define EFI_HII_PACKAGE_FORMS 0x02\r
-#define EFI_HII_PACKAGE_STRINGS 0x04\r
-#define EFI_HII_PACKAGE_FONTS 0x05\r
-#define EFI_HII_PACKAGE_IMAGES 0x06\r
-#define EFI_HII_PACKAGE_SIMPLE_FONTS 0x07\r
-#define EFI_HII_PACKAGE_DEVICE_PATH 0x08\r
-#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09\r
-#define EFI_HII_PACKAGE_ANIMATIONS 0x0A\r
-#define EFI_HII_PACKAGE_END 0xDF\r
-#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0\r
-#define EFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF\r
+#define EFI_HII_PACKAGE_TYPE_ALL 0x00\r
+#define EFI_HII_PACKAGE_TYPE_GUID 0x01\r
+#define EFI_HII_PACKAGE_FORMS 0x02\r
+#define EFI_HII_PACKAGE_STRINGS 0x04\r
+#define EFI_HII_PACKAGE_FONTS 0x05\r
+#define EFI_HII_PACKAGE_IMAGES 0x06\r
+#define EFI_HII_PACKAGE_SIMPLE_FONTS 0x07\r
+#define EFI_HII_PACKAGE_DEVICE_PATH 0x08\r
+#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09\r
+#define EFI_HII_PACKAGE_ANIMATIONS 0x0A\r
+#define EFI_HII_PACKAGE_END 0xDF\r
+#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0\r
+#define EFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF\r
\r
//\r
// Definitions for Simplified Font Package\r
///\r
/// Contents of EFI_NARROW_GLYPH.Attributes.\r
///@{\r
-#define EFI_GLYPH_NON_SPACING 0x01\r
-#define EFI_GLYPH_WIDE 0x02\r
-#define EFI_GLYPH_HEIGHT 19\r
-#define EFI_GLYPH_WIDTH 8\r
+#define EFI_GLYPH_NON_SPACING 0x01\r
+#define EFI_GLYPH_WIDE 0x02\r
+#define EFI_GLYPH_HEIGHT 19\r
+#define EFI_GLYPH_WIDTH 8\r
///@}\r
\r
///\r
/// The Unicode representation of the glyph. The term weight is the\r
/// technical term for a character code.\r
///\r
- CHAR16 UnicodeWeight;\r
+ CHAR16 UnicodeWeight;\r
///\r
/// The data element containing the glyph definitions.\r
///\r
- UINT8 Attributes;\r
+ UINT8 Attributes;\r
///\r
/// The column major glyph representation of the character. Bits\r
/// with values of one indicate that the corresponding pixel is to be\r
/// on when normally displayed; those with zero are off.\r
///\r
- UINT8 GlyphCol1[EFI_GLYPH_HEIGHT];\r
+ UINT8 GlyphCol1[EFI_GLYPH_HEIGHT];\r
} EFI_NARROW_GLYPH;\r
\r
///\r
/// The Unicode representation of the glyph. The term weight is the\r
/// technical term for a character code.\r
///\r
- CHAR16 UnicodeWeight;\r
+ CHAR16 UnicodeWeight;\r
///\r
/// The data element containing the glyph definitions.\r
///\r
- UINT8 Attributes;\r
+ UINT8 Attributes;\r
///\r
/// The column major glyph representation of the character. Bits\r
/// with values of one indicate that the corresponding pixel is to be\r
/// on when normally displayed; those with zero are off.\r
///\r
- UINT8 GlyphCol1[EFI_GLYPH_HEIGHT];\r
+ UINT8 GlyphCol1[EFI_GLYPH_HEIGHT];\r
///\r
/// The column major glyph representation of the character. Bits\r
/// with values of one indicate that the corresponding pixel is to be\r
/// on when normally displayed; those with zero are off.\r
///\r
- UINT8 GlyphCol2[EFI_GLYPH_HEIGHT];\r
+ UINT8 GlyphCol2[EFI_GLYPH_HEIGHT];\r
///\r
/// Ensures that sizeof (EFI_WIDE_GLYPH) is twice the\r
/// sizeof (EFI_NARROW_GLYPH). The contents of Pad must\r
/// be zero.\r
///\r
- UINT8 Pad[3];\r
+ UINT8 Pad[3];\r
} EFI_WIDE_GLYPH;\r
\r
///\r
/// followed by a series of glyph structures.\r
///\r
typedef struct _EFI_HII_SIMPLE_FONT_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- UINT16 NumberOfNarrowGlyphs;\r
- UINT16 NumberOfWideGlyphs;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ UINT16 NumberOfNarrowGlyphs;\r
+ UINT16 NumberOfWideGlyphs;\r
// EFI_NARROW_GLYPH NarrowGlyphs[];\r
// EFI_WIDE_GLYPH WideGlyphs[];\r
} EFI_HII_SIMPLE_FONT_PACKAGE_HDR;\r
//\r
// Value for font style\r
//\r
-#define EFI_HII_FONT_STYLE_NORMAL 0x00000000\r
-#define EFI_HII_FONT_STYLE_BOLD 0x00000001\r
-#define EFI_HII_FONT_STYLE_ITALIC 0x00000002\r
-#define EFI_HII_FONT_STYLE_EMBOSS 0x00010000\r
-#define EFI_HII_FONT_STYLE_OUTLINE 0x00020000\r
-#define EFI_HII_FONT_STYLE_SHADOW 0x00040000\r
-#define EFI_HII_FONT_STYLE_UNDERLINE 0x00080000\r
-#define EFI_HII_FONT_STYLE_DBL_UNDER 0x00100000\r
+#define EFI_HII_FONT_STYLE_NORMAL 0x00000000\r
+#define EFI_HII_FONT_STYLE_BOLD 0x00000001\r
+#define EFI_HII_FONT_STYLE_ITALIC 0x00000002\r
+#define EFI_HII_FONT_STYLE_EMBOSS 0x00010000\r
+#define EFI_HII_FONT_STYLE_OUTLINE 0x00020000\r
+#define EFI_HII_FONT_STYLE_SHADOW 0x00040000\r
+#define EFI_HII_FONT_STYLE_UNDERLINE 0x00080000\r
+#define EFI_HII_FONT_STYLE_DBL_UNDER 0x00100000\r
\r
typedef struct _EFI_HII_GLYPH_INFO {\r
- UINT16 Width;\r
- UINT16 Height;\r
- INT16 OffsetX;\r
- INT16 OffsetY;\r
- INT16 AdvanceX;\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ INT16 OffsetX;\r
+ INT16 OffsetY;\r
+ INT16 AdvanceX;\r
} EFI_HII_GLYPH_INFO;\r
\r
///\r
/// information, the glyph bitmaps and the character map.\r
///\r
typedef struct _EFI_HII_FONT_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- UINT32 HdrSize;\r
- UINT32 GlyphBlockOffset;\r
- EFI_HII_GLYPH_INFO Cell;\r
- EFI_HII_FONT_STYLE FontStyle;\r
- CHAR16 FontFamily[1];\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ UINT32 HdrSize;\r
+ UINT32 GlyphBlockOffset;\r
+ EFI_HII_GLYPH_INFO Cell;\r
+ EFI_HII_FONT_STYLE FontStyle;\r
+ CHAR16 FontFamily[1];\r
} EFI_HII_FONT_PACKAGE_HDR;\r
\r
//\r
// Value of different glyph info block types\r
//\r
-#define EFI_HII_GIBT_END 0x00\r
-#define EFI_HII_GIBT_GLYPH 0x10\r
-#define EFI_HII_GIBT_GLYPHS 0x11\r
-#define EFI_HII_GIBT_GLYPH_DEFAULT 0x12\r
-#define EFI_HII_GIBT_GLYPHS_DEFAULT 0x13\r
-#define EFI_HII_GIBT_GLYPH_VARIABILITY 0x14\r
-#define EFI_HII_GIBT_DUPLICATE 0x20\r
-#define EFI_HII_GIBT_SKIP2 0x21\r
-#define EFI_HII_GIBT_SKIP1 0x22\r
-#define EFI_HII_GIBT_DEFAULTS 0x23\r
-#define EFI_HII_GIBT_EXT1 0x30\r
-#define EFI_HII_GIBT_EXT2 0x31\r
-#define EFI_HII_GIBT_EXT4 0x32\r
+#define EFI_HII_GIBT_END 0x00\r
+#define EFI_HII_GIBT_GLYPH 0x10\r
+#define EFI_HII_GIBT_GLYPHS 0x11\r
+#define EFI_HII_GIBT_GLYPH_DEFAULT 0x12\r
+#define EFI_HII_GIBT_GLYPHS_DEFAULT 0x13\r
+#define EFI_HII_GIBT_GLYPH_VARIABILITY 0x14\r
+#define EFI_HII_GIBT_DUPLICATE 0x20\r
+#define EFI_HII_GIBT_SKIP2 0x21\r
+#define EFI_HII_GIBT_SKIP1 0x22\r
+#define EFI_HII_GIBT_DEFAULTS 0x23\r
+#define EFI_HII_GIBT_EXT1 0x30\r
+#define EFI_HII_GIBT_EXT2 0x31\r
+#define EFI_HII_GIBT_EXT4 0x32\r
\r
typedef struct _EFI_HII_GLYPH_BLOCK {\r
- UINT8 BlockType;\r
+ UINT8 BlockType;\r
} EFI_HII_GLYPH_BLOCK;\r
\r
//\r
EFI_HII_GLYPH_BLOCK Header;\r
EFI_HII_GLYPH_INFO Cell;\r
UINT8 GlyphPackInBits;\r
- UINT8 BitmapData [1];\r
+ UINT8 BitmapData[1];\r
} EFI_HII_GIBT_VARIABILITY_BLOCK;\r
\r
typedef struct _EFI_HII_GIBT_SKIP1_BLOCK {\r
/// associated with the package list.\r
///\r
typedef struct _EFI_HII_DEVICE_PATH_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
// EFI_DEVICE_PATH_PROTOCOL DevicePath[];\r
} EFI_HII_DEVICE_PATH_PACKAGE_HDR;\r
\r
/// The GUID package is used to carry data where the format is defined by a GUID.\r
///\r
typedef struct _EFI_HII_GUID_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- EFI_GUID Guid;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ EFI_GUID Guid;\r
// Data per GUID definition may follow\r
} EFI_HII_GUID_PACKAGE_HDR;\r
\r
// Section 27.3.6\r
//\r
\r
-#define UEFI_CONFIG_LANG "x-UEFI"\r
-#define UEFI_CONFIG_LANG_2 "x-i-UEFI"\r
+#define UEFI_CONFIG_LANG "x-UEFI"\r
+#define UEFI_CONFIG_LANG_2 "x-i-UEFI"\r
\r
///\r
/// The fixed header consists of a standard record header and then the string identifiers\r
/// contained in this section and the offsets of the string and language information.\r
///\r
typedef struct _EFI_HII_STRING_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- UINT32 HdrSize;\r
- UINT32 StringInfoOffset;\r
- CHAR16 LanguageWindow[16];\r
- EFI_STRING_ID LanguageName;\r
- CHAR8 Language[1];\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ UINT32 HdrSize;\r
+ UINT32 StringInfoOffset;\r
+ CHAR16 LanguageWindow[16];\r
+ EFI_STRING_ID LanguageName;\r
+ CHAR8 Language[1];\r
} EFI_HII_STRING_PACKAGE_HDR;\r
\r
typedef struct {\r
- UINT8 BlockType;\r
+ UINT8 BlockType;\r
} EFI_HII_STRING_BLOCK;\r
\r
//\r
// Value of different string information block types\r
//\r
-#define EFI_HII_SIBT_END 0x00\r
-#define EFI_HII_SIBT_STRING_SCSU 0x10\r
-#define EFI_HII_SIBT_STRING_SCSU_FONT 0x11\r
-#define EFI_HII_SIBT_STRINGS_SCSU 0x12\r
-#define EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13\r
-#define EFI_HII_SIBT_STRING_UCS2 0x14\r
-#define EFI_HII_SIBT_STRING_UCS2_FONT 0x15\r
-#define EFI_HII_SIBT_STRINGS_UCS2 0x16\r
-#define EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17\r
-#define EFI_HII_SIBT_DUPLICATE 0x20\r
-#define EFI_HII_SIBT_SKIP2 0x21\r
-#define EFI_HII_SIBT_SKIP1 0x22\r
-#define EFI_HII_SIBT_EXT1 0x30\r
-#define EFI_HII_SIBT_EXT2 0x31\r
-#define EFI_HII_SIBT_EXT4 0x32\r
-#define EFI_HII_SIBT_FONT 0x40\r
+#define EFI_HII_SIBT_END 0x00\r
+#define EFI_HII_SIBT_STRING_SCSU 0x10\r
+#define EFI_HII_SIBT_STRING_SCSU_FONT 0x11\r
+#define EFI_HII_SIBT_STRINGS_SCSU 0x12\r
+#define EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13\r
+#define EFI_HII_SIBT_STRING_UCS2 0x14\r
+#define EFI_HII_SIBT_STRING_UCS2_FONT 0x15\r
+#define EFI_HII_SIBT_STRINGS_UCS2 0x16\r
+#define EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17\r
+#define EFI_HII_SIBT_DUPLICATE 0x20\r
+#define EFI_HII_SIBT_SKIP2 0x21\r
+#define EFI_HII_SIBT_SKIP1 0x22\r
+#define EFI_HII_SIBT_EXT1 0x30\r
+#define EFI_HII_SIBT_EXT2 0x31\r
+#define EFI_HII_SIBT_EXT4 0x32\r
+#define EFI_HII_SIBT_FONT 0x40\r
\r
//\r
// Definition of different string information block types\r
} EFI_HII_SIBT_EXT4_BLOCK;\r
\r
typedef struct _EFI_HII_SIBT_FONT_BLOCK {\r
- EFI_HII_SIBT_EXT2_BLOCK Header;\r
- UINT8 FontId;\r
- UINT16 FontSize;\r
- EFI_HII_FONT_STYLE FontStyle;\r
- CHAR16 FontName[1];\r
+ EFI_HII_SIBT_EXT2_BLOCK Header;\r
+ UINT8 FontId;\r
+ UINT16 FontSize;\r
+ EFI_HII_FONT_STYLE FontStyle;\r
+ CHAR16 FontName[1];\r
} EFI_HII_SIBT_FONT_BLOCK;\r
\r
typedef struct _EFI_HII_SIBT_SKIP1_BLOCK {\r
//\r
\r
typedef struct _EFI_HII_IMAGE_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- UINT32 ImageInfoOffset;\r
- UINT32 PaletteInfoOffset;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ UINT32 ImageInfoOffset;\r
+ UINT32 PaletteInfoOffset;\r
} EFI_HII_IMAGE_PACKAGE_HDR;\r
\r
typedef struct _EFI_HII_IMAGE_BLOCK {\r
- UINT8 BlockType;\r
+ UINT8 BlockType;\r
} EFI_HII_IMAGE_BLOCK;\r
\r
//\r
// Value of different image information block types\r
//\r
-#define EFI_HII_IIBT_END 0x00\r
-#define EFI_HII_IIBT_IMAGE_1BIT 0x10\r
-#define EFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11\r
-#define EFI_HII_IIBT_IMAGE_4BIT 0x12\r
-#define EFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13\r
-#define EFI_HII_IIBT_IMAGE_8BIT 0x14\r
-#define EFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15\r
-#define EFI_HII_IIBT_IMAGE_24BIT 0x16\r
-#define EFI_HII_IIBT_IMAGE_24BIT_TRANS 0x17\r
-#define EFI_HII_IIBT_IMAGE_JPEG 0x18\r
-#define EFI_HII_IIBT_IMAGE_PNG 0x19\r
-#define EFI_HII_IIBT_DUPLICATE 0x20\r
-#define EFI_HII_IIBT_SKIP2 0x21\r
-#define EFI_HII_IIBT_SKIP1 0x22\r
-#define EFI_HII_IIBT_EXT1 0x30\r
-#define EFI_HII_IIBT_EXT2 0x31\r
-#define EFI_HII_IIBT_EXT4 0x32\r
+#define EFI_HII_IIBT_END 0x00\r
+#define EFI_HII_IIBT_IMAGE_1BIT 0x10\r
+#define EFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11\r
+#define EFI_HII_IIBT_IMAGE_4BIT 0x12\r
+#define EFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13\r
+#define EFI_HII_IIBT_IMAGE_8BIT 0x14\r
+#define EFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15\r
+#define EFI_HII_IIBT_IMAGE_24BIT 0x16\r
+#define EFI_HII_IIBT_IMAGE_24BIT_TRANS 0x17\r
+#define EFI_HII_IIBT_IMAGE_JPEG 0x18\r
+#define EFI_HII_IIBT_IMAGE_PNG 0x19\r
+#define EFI_HII_IIBT_DUPLICATE 0x20\r
+#define EFI_HII_IIBT_SKIP2 0x21\r
+#define EFI_HII_IIBT_SKIP1 0x22\r
+#define EFI_HII_IIBT_EXT1 0x30\r
+#define EFI_HII_IIBT_EXT2 0x31\r
+#define EFI_HII_IIBT_EXT4 0x32\r
\r
//\r
// Definition of different image information block types\r
//\r
\r
typedef struct _EFI_HII_IIBT_END_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
} EFI_HII_IIBT_END_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_EXT1_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 BlockType2;\r
- UINT8 Length;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 BlockType2;\r
+ UINT8 Length;\r
} EFI_HII_IIBT_EXT1_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_EXT2_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 BlockType2;\r
- UINT16 Length;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 BlockType2;\r
+ UINT16 Length;\r
} EFI_HII_IIBT_EXT2_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_EXT4_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 BlockType2;\r
- UINT32 Length;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 BlockType2;\r
+ UINT32 Length;\r
} EFI_HII_IIBT_EXT4_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BASE {\r
- UINT16 Width;\r
- UINT16 Height;\r
- UINT8 Data[1];\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ UINT8 Data[1];\r
} EFI_HII_IIBT_IMAGE_1BIT_BASE;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_1BIT_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_1BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_1BIT_TRANS_BLOCK;\r
\r
typedef struct _EFI_HII_RGB_PIXEL {\r
- UINT8 b;\r
- UINT8 g;\r
- UINT8 r;\r
+ UINT8 b;\r
+ UINT8 g;\r
+ UINT8 r;\r
} EFI_HII_RGB_PIXEL;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BASE {\r
- UINT16 Width;\r
- UINT16 Height;\r
- EFI_HII_RGB_PIXEL Bitmap[1];\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ EFI_HII_RGB_PIXEL Bitmap[1];\r
} EFI_HII_IIBT_IMAGE_24BIT_BASE;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_24BIT_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_24BIT_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ EFI_HII_IIBT_IMAGE_24BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_24BIT_TRANS_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BASE {\r
- UINT16 Width;\r
- UINT16 Height;\r
- UINT8 Data[1];\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ UINT8 Data[1];\r
} EFI_HII_IIBT_IMAGE_4BIT_BASE;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_4BIT_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_4BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_4BIT_TRANS_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_8BIT_BASE {\r
- UINT16 Width;\r
- UINT16 Height;\r
- UINT8 Data[1];\r
+ UINT16 Width;\r
+ UINT16 Height;\r
+ UINT8 Data[1];\r
} EFI_HII_IIBT_IMAGE_8BIT_BASE;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_8BIT_PALETTE_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_8BIT_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_IMAGE_8BIT_TRANS_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 PaletteIndex;\r
- EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 PaletteIndex;\r
+ EFI_HII_IIBT_IMAGE_8BIT_BASE Bitmap;\r
} EFI_HII_IIBT_IMAGE_8BIT_TRAN_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_DUPLICATE_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- EFI_IMAGE_ID ImageId;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ EFI_IMAGE_ID ImageId;\r
} EFI_HII_IIBT_DUPLICATE_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_JPEG_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT32 Size;\r
- UINT8 Data[1];\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT32 Size;\r
+ UINT8 Data[1];\r
} EFI_HII_IIBT_JPEG_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_PNG_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT32 Size;\r
- UINT8 Data[1];\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT32 Size;\r
+ UINT8 Data[1];\r
} EFI_HII_IIBT_PNG_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_SKIP1_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT8 SkipCount;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT8 SkipCount;\r
} EFI_HII_IIBT_SKIP1_BLOCK;\r
\r
typedef struct _EFI_HII_IIBT_SKIP2_BLOCK {\r
- EFI_HII_IMAGE_BLOCK Header;\r
- UINT16 SkipCount;\r
+ EFI_HII_IMAGE_BLOCK Header;\r
+ UINT16 SkipCount;\r
} EFI_HII_IIBT_SKIP2_BLOCK;\r
\r
//\r
//\r
\r
typedef struct _EFI_HII_IMAGE_PALETTE_INFO_HEADER {\r
- UINT16 PaletteCount;\r
+ UINT16 PaletteCount;\r
} EFI_HII_IMAGE_PALETTE_INFO_HEADER;\r
\r
typedef struct _EFI_HII_IMAGE_PALETTE_INFO {\r
- UINT16 PaletteSize;\r
- EFI_HII_RGB_PIXEL PaletteValue[1];\r
+ UINT16 PaletteSize;\r
+ EFI_HII_RGB_PIXEL PaletteValue[1];\r
} EFI_HII_IMAGE_PALETTE_INFO;\r
\r
//\r
/// The Form package is used to carry form-based encoding data.\r
///\r
typedef struct _EFI_HII_FORM_PACKAGE_HDR {\r
- EFI_HII_PACKAGE_HEADER Header;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
// EFI_IFR_OP_HEADER OpCodeHeader;\r
// More op-codes follow\r
} EFI_HII_FORM_PACKAGE_HDR;\r
\r
typedef struct {\r
- UINT8 Hour;\r
- UINT8 Minute;\r
- UINT8 Second;\r
+ UINT8 Hour;\r
+ UINT8 Minute;\r
+ UINT8 Second;\r
} EFI_HII_TIME;\r
\r
typedef struct {\r
- UINT16 Year;\r
- UINT8 Month;\r
- UINT8 Day;\r
+ UINT16 Year;\r
+ UINT8 Month;\r
+ UINT8 Day;\r
} EFI_HII_DATE;\r
\r
typedef struct {\r
- EFI_QUESTION_ID QuestionId;\r
- EFI_FORM_ID FormId;\r
- EFI_GUID FormSetGuid;\r
- EFI_STRING_ID DevicePath;\r
+ EFI_QUESTION_ID QuestionId;\r
+ EFI_FORM_ID FormId;\r
+ EFI_GUID FormSetGuid;\r
+ EFI_STRING_ID DevicePath;\r
} EFI_HII_REF;\r
\r
typedef union {\r
- UINT8 u8;\r
- UINT16 u16;\r
- UINT32 u32;\r
- UINT64 u64;\r
- BOOLEAN b;\r
- EFI_HII_TIME time;\r
- EFI_HII_DATE date;\r
- EFI_STRING_ID string; ///< EFI_IFR_TYPE_STRING, EFI_IFR_TYPE_ACTION\r
- EFI_HII_REF ref; ///< EFI_IFR_TYPE_REF\r
+ UINT8 u8;\r
+ UINT16 u16;\r
+ UINT32 u32;\r
+ UINT64 u64;\r
+ BOOLEAN b;\r
+ EFI_HII_TIME time;\r
+ EFI_HII_DATE date;\r
+ EFI_STRING_ID string; ///< EFI_IFR_TYPE_STRING, EFI_IFR_TYPE_ACTION\r
+ EFI_HII_REF ref; ///< EFI_IFR_TYPE_REF\r
// UINT8 buffer[]; ///< EFI_IFR_TYPE_BUFFER\r
} EFI_IFR_TYPE_VALUE;\r
\r
//\r
// IFR Opcodes\r
//\r
-#define EFI_IFR_FORM_OP 0x01\r
-#define EFI_IFR_SUBTITLE_OP 0x02\r
-#define EFI_IFR_TEXT_OP 0x03\r
-#define EFI_IFR_IMAGE_OP 0x04\r
-#define EFI_IFR_ONE_OF_OP 0x05\r
-#define EFI_IFR_CHECKBOX_OP 0x06\r
-#define EFI_IFR_NUMERIC_OP 0x07\r
-#define EFI_IFR_PASSWORD_OP 0x08\r
-#define EFI_IFR_ONE_OF_OPTION_OP 0x09\r
-#define EFI_IFR_SUPPRESS_IF_OP 0x0A\r
-#define EFI_IFR_LOCKED_OP 0x0B\r
-#define EFI_IFR_ACTION_OP 0x0C\r
-#define EFI_IFR_RESET_BUTTON_OP 0x0D\r
-#define EFI_IFR_FORM_SET_OP 0x0E\r
-#define EFI_IFR_REF_OP 0x0F\r
-#define EFI_IFR_NO_SUBMIT_IF_OP 0x10\r
-#define EFI_IFR_INCONSISTENT_IF_OP 0x11\r
-#define EFI_IFR_EQ_ID_VAL_OP 0x12\r
-#define EFI_IFR_EQ_ID_ID_OP 0x13\r
-#define EFI_IFR_EQ_ID_VAL_LIST_OP 0x14\r
-#define EFI_IFR_AND_OP 0x15\r
-#define EFI_IFR_OR_OP 0x16\r
-#define EFI_IFR_NOT_OP 0x17\r
-#define EFI_IFR_RULE_OP 0x18\r
-#define EFI_IFR_GRAY_OUT_IF_OP 0x19\r
-#define EFI_IFR_DATE_OP 0x1A\r
-#define EFI_IFR_TIME_OP 0x1B\r
-#define EFI_IFR_STRING_OP 0x1C\r
-#define EFI_IFR_REFRESH_OP 0x1D\r
-#define EFI_IFR_DISABLE_IF_OP 0x1E\r
-#define EFI_IFR_ANIMATION_OP 0x1F\r
-#define EFI_IFR_TO_LOWER_OP 0x20\r
-#define EFI_IFR_TO_UPPER_OP 0x21\r
-#define EFI_IFR_MAP_OP 0x22\r
-#define EFI_IFR_ORDERED_LIST_OP 0x23\r
-#define EFI_IFR_VARSTORE_OP 0x24\r
-#define EFI_IFR_VARSTORE_NAME_VALUE_OP 0x25\r
-#define EFI_IFR_VARSTORE_EFI_OP 0x26\r
-#define EFI_IFR_VARSTORE_DEVICE_OP 0x27\r
-#define EFI_IFR_VERSION_OP 0x28\r
-#define EFI_IFR_END_OP 0x29\r
-#define EFI_IFR_MATCH_OP 0x2A\r
-#define EFI_IFR_GET_OP 0x2B\r
-#define EFI_IFR_SET_OP 0x2C\r
-#define EFI_IFR_READ_OP 0x2D\r
-#define EFI_IFR_WRITE_OP 0x2E\r
-#define EFI_IFR_EQUAL_OP 0x2F\r
-#define EFI_IFR_NOT_EQUAL_OP 0x30\r
-#define EFI_IFR_GREATER_THAN_OP 0x31\r
-#define EFI_IFR_GREATER_EQUAL_OP 0x32\r
-#define EFI_IFR_LESS_THAN_OP 0x33\r
-#define EFI_IFR_LESS_EQUAL_OP 0x34\r
-#define EFI_IFR_BITWISE_AND_OP 0x35\r
-#define EFI_IFR_BITWISE_OR_OP 0x36\r
-#define EFI_IFR_BITWISE_NOT_OP 0x37\r
-#define EFI_IFR_SHIFT_LEFT_OP 0x38\r
-#define EFI_IFR_SHIFT_RIGHT_OP 0x39\r
-#define EFI_IFR_ADD_OP 0x3A\r
-#define EFI_IFR_SUBTRACT_OP 0x3B\r
-#define EFI_IFR_MULTIPLY_OP 0x3C\r
-#define EFI_IFR_DIVIDE_OP 0x3D\r
-#define EFI_IFR_MODULO_OP 0x3E\r
-#define EFI_IFR_RULE_REF_OP 0x3F\r
-#define EFI_IFR_QUESTION_REF1_OP 0x40\r
-#define EFI_IFR_QUESTION_REF2_OP 0x41\r
-#define EFI_IFR_UINT8_OP 0x42\r
-#define EFI_IFR_UINT16_OP 0x43\r
-#define EFI_IFR_UINT32_OP 0x44\r
-#define EFI_IFR_UINT64_OP 0x45\r
-#define EFI_IFR_TRUE_OP 0x46\r
-#define EFI_IFR_FALSE_OP 0x47\r
-#define EFI_IFR_TO_UINT_OP 0x48\r
-#define EFI_IFR_TO_STRING_OP 0x49\r
-#define EFI_IFR_TO_BOOLEAN_OP 0x4A\r
-#define EFI_IFR_MID_OP 0x4B\r
-#define EFI_IFR_FIND_OP 0x4C\r
-#define EFI_IFR_TOKEN_OP 0x4D\r
-#define EFI_IFR_STRING_REF1_OP 0x4E\r
-#define EFI_IFR_STRING_REF2_OP 0x4F\r
-#define EFI_IFR_CONDITIONAL_OP 0x50\r
-#define EFI_IFR_QUESTION_REF3_OP 0x51\r
-#define EFI_IFR_ZERO_OP 0x52\r
-#define EFI_IFR_ONE_OP 0x53\r
-#define EFI_IFR_ONES_OP 0x54\r
-#define EFI_IFR_UNDEFINED_OP 0x55\r
-#define EFI_IFR_LENGTH_OP 0x56\r
-#define EFI_IFR_DUP_OP 0x57\r
-#define EFI_IFR_THIS_OP 0x58\r
-#define EFI_IFR_SPAN_OP 0x59\r
-#define EFI_IFR_VALUE_OP 0x5A\r
-#define EFI_IFR_DEFAULT_OP 0x5B\r
-#define EFI_IFR_DEFAULTSTORE_OP 0x5C\r
-#define EFI_IFR_FORM_MAP_OP 0x5D\r
-#define EFI_IFR_CATENATE_OP 0x5E\r
-#define EFI_IFR_GUID_OP 0x5F\r
-#define EFI_IFR_SECURITY_OP 0x60\r
-#define EFI_IFR_MODAL_TAG_OP 0x61\r
-#define EFI_IFR_REFRESH_ID_OP 0x62\r
-#define EFI_IFR_WARNING_IF_OP 0x63\r
-#define EFI_IFR_MATCH2_OP 0x64\r
+#define EFI_IFR_FORM_OP 0x01\r
+#define EFI_IFR_SUBTITLE_OP 0x02\r
+#define EFI_IFR_TEXT_OP 0x03\r
+#define EFI_IFR_IMAGE_OP 0x04\r
+#define EFI_IFR_ONE_OF_OP 0x05\r
+#define EFI_IFR_CHECKBOX_OP 0x06\r
+#define EFI_IFR_NUMERIC_OP 0x07\r
+#define EFI_IFR_PASSWORD_OP 0x08\r
+#define EFI_IFR_ONE_OF_OPTION_OP 0x09\r
+#define EFI_IFR_SUPPRESS_IF_OP 0x0A\r
+#define EFI_IFR_LOCKED_OP 0x0B\r
+#define EFI_IFR_ACTION_OP 0x0C\r
+#define EFI_IFR_RESET_BUTTON_OP 0x0D\r
+#define EFI_IFR_FORM_SET_OP 0x0E\r
+#define EFI_IFR_REF_OP 0x0F\r
+#define EFI_IFR_NO_SUBMIT_IF_OP 0x10\r
+#define EFI_IFR_INCONSISTENT_IF_OP 0x11\r
+#define EFI_IFR_EQ_ID_VAL_OP 0x12\r
+#define EFI_IFR_EQ_ID_ID_OP 0x13\r
+#define EFI_IFR_EQ_ID_VAL_LIST_OP 0x14\r
+#define EFI_IFR_AND_OP 0x15\r
+#define EFI_IFR_OR_OP 0x16\r
+#define EFI_IFR_NOT_OP 0x17\r
+#define EFI_IFR_RULE_OP 0x18\r
+#define EFI_IFR_GRAY_OUT_IF_OP 0x19\r
+#define EFI_IFR_DATE_OP 0x1A\r
+#define EFI_IFR_TIME_OP 0x1B\r
+#define EFI_IFR_STRING_OP 0x1C\r
+#define EFI_IFR_REFRESH_OP 0x1D\r
+#define EFI_IFR_DISABLE_IF_OP 0x1E\r
+#define EFI_IFR_ANIMATION_OP 0x1F\r
+#define EFI_IFR_TO_LOWER_OP 0x20\r
+#define EFI_IFR_TO_UPPER_OP 0x21\r
+#define EFI_IFR_MAP_OP 0x22\r
+#define EFI_IFR_ORDERED_LIST_OP 0x23\r
+#define EFI_IFR_VARSTORE_OP 0x24\r
+#define EFI_IFR_VARSTORE_NAME_VALUE_OP 0x25\r
+#define EFI_IFR_VARSTORE_EFI_OP 0x26\r
+#define EFI_IFR_VARSTORE_DEVICE_OP 0x27\r
+#define EFI_IFR_VERSION_OP 0x28\r
+#define EFI_IFR_END_OP 0x29\r
+#define EFI_IFR_MATCH_OP 0x2A\r
+#define EFI_IFR_GET_OP 0x2B\r
+#define EFI_IFR_SET_OP 0x2C\r
+#define EFI_IFR_READ_OP 0x2D\r
+#define EFI_IFR_WRITE_OP 0x2E\r
+#define EFI_IFR_EQUAL_OP 0x2F\r
+#define EFI_IFR_NOT_EQUAL_OP 0x30\r
+#define EFI_IFR_GREATER_THAN_OP 0x31\r
+#define EFI_IFR_GREATER_EQUAL_OP 0x32\r
+#define EFI_IFR_LESS_THAN_OP 0x33\r
+#define EFI_IFR_LESS_EQUAL_OP 0x34\r
+#define EFI_IFR_BITWISE_AND_OP 0x35\r
+#define EFI_IFR_BITWISE_OR_OP 0x36\r
+#define EFI_IFR_BITWISE_NOT_OP 0x37\r
+#define EFI_IFR_SHIFT_LEFT_OP 0x38\r
+#define EFI_IFR_SHIFT_RIGHT_OP 0x39\r
+#define EFI_IFR_ADD_OP 0x3A\r
+#define EFI_IFR_SUBTRACT_OP 0x3B\r
+#define EFI_IFR_MULTIPLY_OP 0x3C\r
+#define EFI_IFR_DIVIDE_OP 0x3D\r
+#define EFI_IFR_MODULO_OP 0x3E\r
+#define EFI_IFR_RULE_REF_OP 0x3F\r
+#define EFI_IFR_QUESTION_REF1_OP 0x40\r
+#define EFI_IFR_QUESTION_REF2_OP 0x41\r
+#define EFI_IFR_UINT8_OP 0x42\r
+#define EFI_IFR_UINT16_OP 0x43\r
+#define EFI_IFR_UINT32_OP 0x44\r
+#define EFI_IFR_UINT64_OP 0x45\r
+#define EFI_IFR_TRUE_OP 0x46\r
+#define EFI_IFR_FALSE_OP 0x47\r
+#define EFI_IFR_TO_UINT_OP 0x48\r
+#define EFI_IFR_TO_STRING_OP 0x49\r
+#define EFI_IFR_TO_BOOLEAN_OP 0x4A\r
+#define EFI_IFR_MID_OP 0x4B\r
+#define EFI_IFR_FIND_OP 0x4C\r
+#define EFI_IFR_TOKEN_OP 0x4D\r
+#define EFI_IFR_STRING_REF1_OP 0x4E\r
+#define EFI_IFR_STRING_REF2_OP 0x4F\r
+#define EFI_IFR_CONDITIONAL_OP 0x50\r
+#define EFI_IFR_QUESTION_REF3_OP 0x51\r
+#define EFI_IFR_ZERO_OP 0x52\r
+#define EFI_IFR_ONE_OP 0x53\r
+#define EFI_IFR_ONES_OP 0x54\r
+#define EFI_IFR_UNDEFINED_OP 0x55\r
+#define EFI_IFR_LENGTH_OP 0x56\r
+#define EFI_IFR_DUP_OP 0x57\r
+#define EFI_IFR_THIS_OP 0x58\r
+#define EFI_IFR_SPAN_OP 0x59\r
+#define EFI_IFR_VALUE_OP 0x5A\r
+#define EFI_IFR_DEFAULT_OP 0x5B\r
+#define EFI_IFR_DEFAULTSTORE_OP 0x5C\r
+#define EFI_IFR_FORM_MAP_OP 0x5D\r
+#define EFI_IFR_CATENATE_OP 0x5E\r
+#define EFI_IFR_GUID_OP 0x5F\r
+#define EFI_IFR_SECURITY_OP 0x60\r
+#define EFI_IFR_MODAL_TAG_OP 0x61\r
+#define EFI_IFR_REFRESH_ID_OP 0x62\r
+#define EFI_IFR_WARNING_IF_OP 0x63\r
+#define EFI_IFR_MATCH2_OP 0x64\r
\r
//\r
// Definitions of IFR Standard Headers\r
//\r
\r
typedef struct _EFI_IFR_OP_HEADER {\r
- UINT8 OpCode;\r
- UINT8 Length:7;\r
- UINT8 Scope:1;\r
+ UINT8 OpCode;\r
+ UINT8 Length : 7;\r
+ UINT8 Scope : 1;\r
} EFI_IFR_OP_HEADER;\r
\r
typedef struct _EFI_IFR_STATEMENT_HEADER {\r
- EFI_STRING_ID Prompt;\r
- EFI_STRING_ID Help;\r
+ EFI_STRING_ID Prompt;\r
+ EFI_STRING_ID Help;\r
} EFI_IFR_STATEMENT_HEADER;\r
\r
typedef struct _EFI_IFR_QUESTION_HEADER {\r
- EFI_IFR_STATEMENT_HEADER Header;\r
- EFI_QUESTION_ID QuestionId;\r
- EFI_VARSTORE_ID VarStoreId;\r
+ EFI_IFR_STATEMENT_HEADER Header;\r
+ EFI_QUESTION_ID QuestionId;\r
+ EFI_VARSTORE_ID VarStoreId;\r
union {\r
- EFI_STRING_ID VarName;\r
- UINT16 VarOffset;\r
+ EFI_STRING_ID VarName;\r
+ UINT16 VarOffset;\r
} VarStoreInfo;\r
- UINT8 Flags;\r
+ UINT8 Flags;\r
} EFI_IFR_QUESTION_HEADER;\r
\r
//\r
// Flag values of EFI_IFR_QUESTION_HEADER\r
//\r
-#define EFI_IFR_FLAG_READ_ONLY 0x01\r
-#define EFI_IFR_FLAG_CALLBACK 0x04\r
-#define EFI_IFR_FLAG_RESET_REQUIRED 0x10\r
-#define EFI_IFR_FLAG_REST_STYLE 0x20\r
-#define EFI_IFR_FLAG_RECONNECT_REQUIRED 0x40\r
-#define EFI_IFR_FLAG_OPTIONS_ONLY 0x80\r
+#define EFI_IFR_FLAG_READ_ONLY 0x01\r
+#define EFI_IFR_FLAG_CALLBACK 0x04\r
+#define EFI_IFR_FLAG_RESET_REQUIRED 0x10\r
+#define EFI_IFR_FLAG_REST_STYLE 0x20\r
+#define EFI_IFR_FLAG_RECONNECT_REQUIRED 0x40\r
+#define EFI_IFR_FLAG_OPTIONS_ONLY 0x80\r
\r
//\r
// Definition for Opcode Reference\r
// Section 27.3.8.3\r
//\r
typedef struct _EFI_IFR_DEFAULTSTORE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID DefaultName;\r
- UINT16 DefaultId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID DefaultName;\r
+ UINT16 DefaultId;\r
} EFI_IFR_DEFAULTSTORE;\r
\r
//\r
// Default Identifier of default store\r
//\r
-#define EFI_HII_DEFAULT_CLASS_STANDARD 0x0000\r
-#define EFI_HII_DEFAULT_CLASS_MANUFACTURING 0x0001\r
-#define EFI_HII_DEFAULT_CLASS_SAFE 0x0002\r
-#define EFI_HII_DEFAULT_CLASS_PLATFORM_BEGIN 0x4000\r
-#define EFI_HII_DEFAULT_CLASS_PLATFORM_END 0x7fff\r
-#define EFI_HII_DEFAULT_CLASS_HARDWARE_BEGIN 0x8000\r
-#define EFI_HII_DEFAULT_CLASS_HARDWARE_END 0xbfff\r
-#define EFI_HII_DEFAULT_CLASS_FIRMWARE_BEGIN 0xc000\r
-#define EFI_HII_DEFAULT_CLASS_FIRMWARE_END 0xffff\r
+#define EFI_HII_DEFAULT_CLASS_STANDARD 0x0000\r
+#define EFI_HII_DEFAULT_CLASS_MANUFACTURING 0x0001\r
+#define EFI_HII_DEFAULT_CLASS_SAFE 0x0002\r
+#define EFI_HII_DEFAULT_CLASS_PLATFORM_BEGIN 0x4000\r
+#define EFI_HII_DEFAULT_CLASS_PLATFORM_END 0x7fff\r
+#define EFI_HII_DEFAULT_CLASS_HARDWARE_BEGIN 0x8000\r
+#define EFI_HII_DEFAULT_CLASS_HARDWARE_END 0xbfff\r
+#define EFI_HII_DEFAULT_CLASS_FIRMWARE_BEGIN 0xc000\r
+#define EFI_HII_DEFAULT_CLASS_FIRMWARE_END 0xffff\r
\r
typedef struct _EFI_IFR_VARSTORE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_GUID Guid;\r
- EFI_VARSTORE_ID VarStoreId;\r
- UINT16 Size;\r
- UINT8 Name[1];\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_GUID Guid;\r
+ EFI_VARSTORE_ID VarStoreId;\r
+ UINT16 Size;\r
+ UINT8 Name[1];\r
} EFI_IFR_VARSTORE;\r
\r
typedef struct _EFI_IFR_VARSTORE_EFI {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_VARSTORE_ID VarStoreId;\r
- EFI_GUID Guid;\r
- UINT32 Attributes;\r
- UINT16 Size;\r
- UINT8 Name[1];\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_VARSTORE_ID VarStoreId;\r
+ EFI_GUID Guid;\r
+ UINT32 Attributes;\r
+ UINT16 Size;\r
+ UINT8 Name[1];\r
} EFI_IFR_VARSTORE_EFI;\r
\r
typedef struct _EFI_IFR_VARSTORE_NAME_VALUE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_VARSTORE_ID VarStoreId;\r
- EFI_GUID Guid;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_VARSTORE_ID VarStoreId;\r
+ EFI_GUID Guid;\r
} EFI_IFR_VARSTORE_NAME_VALUE;\r
\r
typedef struct _EFI_IFR_FORM_SET {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_GUID Guid;\r
- EFI_STRING_ID FormSetTitle;\r
- EFI_STRING_ID Help;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_GUID Guid;\r
+ EFI_STRING_ID FormSetTitle;\r
+ EFI_STRING_ID Help;\r
+ UINT8 Flags;\r
// EFI_GUID ClassGuid[];\r
} EFI_IFR_FORM_SET;\r
\r
typedef struct _EFI_IFR_END {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_END;\r
\r
typedef struct _EFI_IFR_FORM {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT16 FormId;\r
- EFI_STRING_ID FormTitle;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT16 FormId;\r
+ EFI_STRING_ID FormTitle;\r
} EFI_IFR_FORM;\r
\r
typedef struct _EFI_IFR_IMAGE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IMAGE_ID Id;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IMAGE_ID Id;\r
} EFI_IFR_IMAGE;\r
\r
typedef struct _EFI_IFR_MODAL_TAG {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MODAL_TAG;\r
\r
typedef struct _EFI_IFR_LOCKED {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_LOCKED;\r
\r
typedef struct _EFI_IFR_RULE {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 RuleId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 RuleId;\r
} EFI_IFR_RULE;\r
\r
typedef struct _EFI_IFR_DEFAULT {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT16 DefaultId;\r
- UINT8 Type;\r
- EFI_IFR_TYPE_VALUE Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT16 DefaultId;\r
+ UINT8 Type;\r
+ EFI_IFR_TYPE_VALUE Value;\r
} EFI_IFR_DEFAULT;\r
\r
typedef struct _EFI_IFR_DEFAULT_2 {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT16 DefaultId;\r
- UINT8 Type;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT16 DefaultId;\r
+ UINT8 Type;\r
} EFI_IFR_DEFAULT_2;\r
\r
typedef struct _EFI_IFR_VALUE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_VALUE;\r
\r
typedef struct _EFI_IFR_SUBTITLE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_STATEMENT_HEADER Statement;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_STATEMENT_HEADER Statement;\r
+ UINT8 Flags;\r
} EFI_IFR_SUBTITLE;\r
\r
-#define EFI_IFR_FLAGS_HORIZONTAL 0x01\r
+#define EFI_IFR_FLAGS_HORIZONTAL 0x01\r
\r
typedef struct _EFI_IFR_CHECKBOX {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 Flags;\r
} EFI_IFR_CHECKBOX;\r
\r
-#define EFI_IFR_CHECKBOX_DEFAULT 0x01\r
-#define EFI_IFR_CHECKBOX_DEFAULT_MFG 0x02\r
+#define EFI_IFR_CHECKBOX_DEFAULT 0x01\r
+#define EFI_IFR_CHECKBOX_DEFAULT_MFG 0x02\r
\r
typedef struct _EFI_IFR_TEXT {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_STATEMENT_HEADER Statement;\r
- EFI_STRING_ID TextTwo;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_STATEMENT_HEADER Statement;\r
+ EFI_STRING_ID TextTwo;\r
} EFI_IFR_TEXT;\r
\r
typedef struct _EFI_IFR_REF {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- EFI_FORM_ID FormId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_FORM_ID FormId;\r
} EFI_IFR_REF;\r
\r
typedef struct _EFI_IFR_REF2 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- EFI_FORM_ID FormId;\r
- EFI_QUESTION_ID QuestionId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_FORM_ID FormId;\r
+ EFI_QUESTION_ID QuestionId;\r
} EFI_IFR_REF2;\r
\r
typedef struct _EFI_IFR_REF3 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- EFI_FORM_ID FormId;\r
- EFI_QUESTION_ID QuestionId;\r
- EFI_GUID FormSetId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_FORM_ID FormId;\r
+ EFI_QUESTION_ID QuestionId;\r
+ EFI_GUID FormSetId;\r
} EFI_IFR_REF3;\r
\r
typedef struct _EFI_IFR_REF4 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- EFI_FORM_ID FormId;\r
- EFI_QUESTION_ID QuestionId;\r
- EFI_GUID FormSetId;\r
- EFI_STRING_ID DevicePath;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_FORM_ID FormId;\r
+ EFI_QUESTION_ID QuestionId;\r
+ EFI_GUID FormSetId;\r
+ EFI_STRING_ID DevicePath;\r
} EFI_IFR_REF4;\r
\r
typedef struct _EFI_IFR_REF5 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
} EFI_IFR_REF5;\r
\r
typedef struct _EFI_IFR_RESET_BUTTON {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_STATEMENT_HEADER Statement;\r
- EFI_DEFAULT_ID DefaultId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_STATEMENT_HEADER Statement;\r
+ EFI_DEFAULT_ID DefaultId;\r
} EFI_IFR_RESET_BUTTON;\r
\r
typedef struct _EFI_IFR_ACTION {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- EFI_STRING_ID QuestionConfig;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_STRING_ID QuestionConfig;\r
} EFI_IFR_ACTION;\r
\r
typedef struct _EFI_IFR_ACTION_1 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
} EFI_IFR_ACTION_1;\r
\r
typedef struct _EFI_IFR_DATE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 Flags;\r
} EFI_IFR_DATE;\r
\r
//\r
// Flags that describe the behavior of the question.\r
//\r
-#define EFI_QF_DATE_YEAR_SUPPRESS 0x01\r
-#define EFI_QF_DATE_MONTH_SUPPRESS 0x02\r
-#define EFI_QF_DATE_DAY_SUPPRESS 0x04\r
+#define EFI_QF_DATE_YEAR_SUPPRESS 0x01\r
+#define EFI_QF_DATE_MONTH_SUPPRESS 0x02\r
+#define EFI_QF_DATE_DAY_SUPPRESS 0x04\r
\r
-#define EFI_QF_DATE_STORAGE 0x30\r
-#define QF_DATE_STORAGE_NORMAL 0x00\r
-#define QF_DATE_STORAGE_TIME 0x10\r
-#define QF_DATE_STORAGE_WAKEUP 0x20\r
+#define EFI_QF_DATE_STORAGE 0x30\r
+#define QF_DATE_STORAGE_NORMAL 0x00\r
+#define QF_DATE_STORAGE_TIME 0x10\r
+#define QF_DATE_STORAGE_WAKEUP 0x20\r
\r
typedef union {\r
struct {\r
- UINT8 MinValue;\r
- UINT8 MaxValue;\r
- UINT8 Step;\r
+ UINT8 MinValue;\r
+ UINT8 MaxValue;\r
+ UINT8 Step;\r
} u8;\r
struct {\r
- UINT16 MinValue;\r
- UINT16 MaxValue;\r
- UINT16 Step;\r
+ UINT16 MinValue;\r
+ UINT16 MaxValue;\r
+ UINT16 Step;\r
} u16;\r
struct {\r
- UINT32 MinValue;\r
- UINT32 MaxValue;\r
- UINT32 Step;\r
+ UINT32 MinValue;\r
+ UINT32 MaxValue;\r
+ UINT32 Step;\r
} u32;\r
struct {\r
- UINT64 MinValue;\r
- UINT64 MaxValue;\r
- UINT64 Step;\r
+ UINT64 MinValue;\r
+ UINT64 MaxValue;\r
+ UINT64 Step;\r
} u64;\r
} MINMAXSTEP_DATA;\r
\r
typedef struct _EFI_IFR_NUMERIC {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 Flags;\r
- MINMAXSTEP_DATA data;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 Flags;\r
+ MINMAXSTEP_DATA data;\r
} EFI_IFR_NUMERIC;\r
\r
//\r
// Flags related to the numeric question\r
//\r
-#define EFI_IFR_NUMERIC_SIZE 0x03\r
-#define EFI_IFR_NUMERIC_SIZE_1 0x00\r
-#define EFI_IFR_NUMERIC_SIZE_2 0x01\r
-#define EFI_IFR_NUMERIC_SIZE_4 0x02\r
-#define EFI_IFR_NUMERIC_SIZE_8 0x03\r
+#define EFI_IFR_NUMERIC_SIZE 0x03\r
+#define EFI_IFR_NUMERIC_SIZE_1 0x00\r
+#define EFI_IFR_NUMERIC_SIZE_2 0x01\r
+#define EFI_IFR_NUMERIC_SIZE_4 0x02\r
+#define EFI_IFR_NUMERIC_SIZE_8 0x03\r
\r
-#define EFI_IFR_DISPLAY 0x30\r
-#define EFI_IFR_DISPLAY_INT_DEC 0x00\r
-#define EFI_IFR_DISPLAY_UINT_DEC 0x10\r
-#define EFI_IFR_DISPLAY_UINT_HEX 0x20\r
+#define EFI_IFR_DISPLAY 0x30\r
+#define EFI_IFR_DISPLAY_INT_DEC 0x00\r
+#define EFI_IFR_DISPLAY_UINT_DEC 0x10\r
+#define EFI_IFR_DISPLAY_UINT_HEX 0x20\r
\r
typedef struct _EFI_IFR_ONE_OF {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 Flags;\r
- MINMAXSTEP_DATA data;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 Flags;\r
+ MINMAXSTEP_DATA data;\r
} EFI_IFR_ONE_OF;\r
\r
typedef struct _EFI_IFR_STRING {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 MinSize;\r
- UINT8 MaxSize;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 MinSize;\r
+ UINT8 MaxSize;\r
+ UINT8 Flags;\r
} EFI_IFR_STRING;\r
\r
-#define EFI_IFR_STRING_MULTI_LINE 0x01\r
+#define EFI_IFR_STRING_MULTI_LINE 0x01\r
\r
typedef struct _EFI_IFR_PASSWORD {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT16 MinSize;\r
- UINT16 MaxSize;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT16 MinSize;\r
+ UINT16 MaxSize;\r
} EFI_IFR_PASSWORD;\r
\r
typedef struct _EFI_IFR_ORDERED_LIST {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 MaxContainers;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 MaxContainers;\r
+ UINT8 Flags;\r
} EFI_IFR_ORDERED_LIST;\r
\r
-#define EFI_IFR_UNIQUE_SET 0x01\r
-#define EFI_IFR_NO_EMPTY_SET 0x02\r
+#define EFI_IFR_UNIQUE_SET 0x01\r
+#define EFI_IFR_NO_EMPTY_SET 0x02\r
\r
typedef struct _EFI_IFR_TIME {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_IFR_QUESTION_HEADER Question;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_QUESTION_HEADER Question;\r
+ UINT8 Flags;\r
} EFI_IFR_TIME;\r
\r
//\r
// A bit-mask that determines which unique settings are active for this opcode.\r
//\r
-#define QF_TIME_HOUR_SUPPRESS 0x01\r
-#define QF_TIME_MINUTE_SUPPRESS 0x02\r
-#define QF_TIME_SECOND_SUPPRESS 0x04\r
+#define QF_TIME_HOUR_SUPPRESS 0x01\r
+#define QF_TIME_MINUTE_SUPPRESS 0x02\r
+#define QF_TIME_SECOND_SUPPRESS 0x04\r
\r
-#define QF_TIME_STORAGE 0x30\r
-#define QF_TIME_STORAGE_NORMAL 0x00\r
-#define QF_TIME_STORAGE_TIME 0x10\r
-#define QF_TIME_STORAGE_WAKEUP 0x20\r
+#define QF_TIME_STORAGE 0x30\r
+#define QF_TIME_STORAGE_NORMAL 0x00\r
+#define QF_TIME_STORAGE_TIME 0x10\r
+#define QF_TIME_STORAGE_WAKEUP 0x20\r
\r
typedef struct _EFI_IFR_DISABLE_IF {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_DISABLE_IF;\r
\r
typedef struct _EFI_IFR_SUPPRESS_IF {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_SUPPRESS_IF;\r
\r
typedef struct _EFI_IFR_GRAY_OUT_IF {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_GRAY_OUT_IF;\r
\r
typedef struct _EFI_IFR_INCONSISTENT_IF {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID Error;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID Error;\r
} EFI_IFR_INCONSISTENT_IF;\r
\r
typedef struct _EFI_IFR_NO_SUBMIT_IF {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID Error;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID Error;\r
} EFI_IFR_NO_SUBMIT_IF;\r
\r
typedef struct _EFI_IFR_WARNING_IF {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID Warning;\r
- UINT8 TimeOut;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID Warning;\r
+ UINT8 TimeOut;\r
} EFI_IFR_WARNING_IF;\r
\r
typedef struct _EFI_IFR_REFRESH {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 RefreshInterval;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 RefreshInterval;\r
} EFI_IFR_REFRESH;\r
\r
typedef struct _EFI_IFR_VARSTORE_DEVICE {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID DevicePath;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID DevicePath;\r
} EFI_IFR_VARSTORE_DEVICE;\r
\r
typedef struct _EFI_IFR_ONE_OF_OPTION {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID Option;\r
- UINT8 Flags;\r
- UINT8 Type;\r
- EFI_IFR_TYPE_VALUE Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID Option;\r
+ UINT8 Flags;\r
+ UINT8 Type;\r
+ EFI_IFR_TYPE_VALUE Value;\r
} EFI_IFR_ONE_OF_OPTION;\r
\r
//\r
// Types of the option's value.\r
//\r
-#define EFI_IFR_TYPE_NUM_SIZE_8 0x00\r
-#define EFI_IFR_TYPE_NUM_SIZE_16 0x01\r
-#define EFI_IFR_TYPE_NUM_SIZE_32 0x02\r
-#define EFI_IFR_TYPE_NUM_SIZE_64 0x03\r
-#define EFI_IFR_TYPE_BOOLEAN 0x04\r
-#define EFI_IFR_TYPE_TIME 0x05\r
-#define EFI_IFR_TYPE_DATE 0x06\r
-#define EFI_IFR_TYPE_STRING 0x07\r
-#define EFI_IFR_TYPE_OTHER 0x08\r
-#define EFI_IFR_TYPE_UNDEFINED 0x09\r
-#define EFI_IFR_TYPE_ACTION 0x0A\r
-#define EFI_IFR_TYPE_BUFFER 0x0B\r
-#define EFI_IFR_TYPE_REF 0x0C\r
-\r
-#define EFI_IFR_OPTION_DEFAULT 0x10\r
-#define EFI_IFR_OPTION_DEFAULT_MFG 0x20\r
+#define EFI_IFR_TYPE_NUM_SIZE_8 0x00\r
+#define EFI_IFR_TYPE_NUM_SIZE_16 0x01\r
+#define EFI_IFR_TYPE_NUM_SIZE_32 0x02\r
+#define EFI_IFR_TYPE_NUM_SIZE_64 0x03\r
+#define EFI_IFR_TYPE_BOOLEAN 0x04\r
+#define EFI_IFR_TYPE_TIME 0x05\r
+#define EFI_IFR_TYPE_DATE 0x06\r
+#define EFI_IFR_TYPE_STRING 0x07\r
+#define EFI_IFR_TYPE_OTHER 0x08\r
+#define EFI_IFR_TYPE_UNDEFINED 0x09\r
+#define EFI_IFR_TYPE_ACTION 0x0A\r
+#define EFI_IFR_TYPE_BUFFER 0x0B\r
+#define EFI_IFR_TYPE_REF 0x0C\r
+\r
+#define EFI_IFR_OPTION_DEFAULT 0x10\r
+#define EFI_IFR_OPTION_DEFAULT_MFG 0x20\r
\r
typedef struct _EFI_IFR_GUID {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_GUID Guid;\r
- //Optional Data Follows\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_GUID Guid;\r
+ // Optional Data Follows\r
} EFI_IFR_GUID;\r
\r
typedef struct _EFI_IFR_REFRESH_ID {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_GUID RefreshEventGroupId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_GUID RefreshEventGroupId;\r
} EFI_IFR_REFRESH_ID;\r
\r
typedef struct _EFI_IFR_DUP {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_DUP;\r
\r
typedef struct _EFI_IFR_EQ_ID_ID {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_QUESTION_ID QuestionId1;\r
- EFI_QUESTION_ID QuestionId2;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_QUESTION_ID QuestionId1;\r
+ EFI_QUESTION_ID QuestionId2;\r
} EFI_IFR_EQ_ID_ID;\r
\r
typedef struct _EFI_IFR_EQ_ID_VAL {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_QUESTION_ID QuestionId;\r
- UINT16 Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_QUESTION_ID QuestionId;\r
+ UINT16 Value;\r
} EFI_IFR_EQ_ID_VAL;\r
\r
typedef struct _EFI_IFR_EQ_ID_VAL_LIST {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_QUESTION_ID QuestionId;\r
- UINT16 ListLength;\r
- UINT16 ValueList[1];\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_QUESTION_ID QuestionId;\r
+ UINT16 ListLength;\r
+ UINT16 ValueList[1];\r
} EFI_IFR_EQ_ID_VAL_LIST;\r
\r
typedef struct _EFI_IFR_UINT8 {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 Value;\r
} EFI_IFR_UINT8;\r
\r
typedef struct _EFI_IFR_UINT16 {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT16 Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT16 Value;\r
} EFI_IFR_UINT16;\r
\r
typedef struct _EFI_IFR_UINT32 {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT32 Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT32 Value;\r
} EFI_IFR_UINT32;\r
\r
typedef struct _EFI_IFR_UINT64 {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT64 Value;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT64 Value;\r
} EFI_IFR_UINT64;\r
\r
typedef struct _EFI_IFR_QUESTION_REF1 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_QUESTION_ID QuestionId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_QUESTION_ID QuestionId;\r
} EFI_IFR_QUESTION_REF1;\r
\r
typedef struct _EFI_IFR_QUESTION_REF2 {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_QUESTION_REF2;\r
\r
typedef struct _EFI_IFR_QUESTION_REF3 {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_QUESTION_REF3;\r
\r
typedef struct _EFI_IFR_QUESTION_REF3_2 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID DevicePath;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID DevicePath;\r
} EFI_IFR_QUESTION_REF3_2;\r
\r
typedef struct _EFI_IFR_QUESTION_REF3_3 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID DevicePath;\r
- EFI_GUID Guid;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID DevicePath;\r
+ EFI_GUID Guid;\r
} EFI_IFR_QUESTION_REF3_3;\r
\r
typedef struct _EFI_IFR_RULE_REF {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 RuleId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 RuleId;\r
} EFI_IFR_RULE_REF;\r
\r
typedef struct _EFI_IFR_STRING_REF1 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_STRING_ID StringId;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_STRING_ID StringId;\r
} EFI_IFR_STRING_REF1;\r
\r
typedef struct _EFI_IFR_STRING_REF2 {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_STRING_REF2;\r
\r
typedef struct _EFI_IFR_THIS {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_THIS;\r
\r
typedef struct _EFI_IFR_TRUE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TRUE;\r
\r
typedef struct _EFI_IFR_FALSE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_FALSE;\r
\r
typedef struct _EFI_IFR_ONE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_ONE;\r
\r
typedef struct _EFI_IFR_ONES {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_ONES;\r
\r
typedef struct _EFI_IFR_ZERO {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_ZERO;\r
\r
typedef struct _EFI_IFR_UNDEFINED {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_UNDEFINED;\r
\r
typedef struct _EFI_IFR_VERSION {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_VERSION;\r
\r
typedef struct _EFI_IFR_LENGTH {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_LENGTH;\r
\r
typedef struct _EFI_IFR_NOT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_NOT;\r
\r
typedef struct _EFI_IFR_BITWISE_NOT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_BITWISE_NOT;\r
\r
typedef struct _EFI_IFR_TO_BOOLEAN {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TO_BOOLEAN;\r
\r
///\r
/// 2 = hexadecimal (lower-case alpha).\r
/// 3 = hexadecimal (upper-case alpha).\r
///@{\r
-#define EFI_IFR_STRING_UNSIGNED_DEC 0\r
-#define EFI_IFR_STRING_SIGNED_DEC 1\r
-#define EFI_IFR_STRING_LOWERCASE_HEX 2\r
-#define EFI_IFR_STRING_UPPERCASE_HEX 3\r
+#define EFI_IFR_STRING_UNSIGNED_DEC 0\r
+#define EFI_IFR_STRING_SIGNED_DEC 1\r
+#define EFI_IFR_STRING_LOWERCASE_HEX 2\r
+#define EFI_IFR_STRING_UPPERCASE_HEX 3\r
///@}\r
\r
///\r
/// 0 = ASCII.\r
/// 8 = Unicode.\r
///@{\r
-#define EFI_IFR_STRING_ASCII 0\r
-#define EFI_IFR_STRING_UNICODE 8\r
+#define EFI_IFR_STRING_ASCII 0\r
+#define EFI_IFR_STRING_UNICODE 8\r
///@}\r
\r
typedef struct _EFI_IFR_TO_STRING {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 Format;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 Format;\r
} EFI_IFR_TO_STRING;\r
\r
typedef struct _EFI_IFR_TO_UINT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TO_UINT;\r
\r
typedef struct _EFI_IFR_TO_UPPER {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TO_UPPER;\r
\r
typedef struct _EFI_IFR_TO_LOWER {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TO_LOWER;\r
\r
typedef struct _EFI_IFR_ADD {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_ADD;\r
\r
typedef struct _EFI_IFR_AND {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_AND;\r
\r
typedef struct _EFI_IFR_BITWISE_AND {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_BITWISE_AND;\r
\r
typedef struct _EFI_IFR_BITWISE_OR {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_BITWISE_OR;\r
\r
typedef struct _EFI_IFR_CATENATE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_CATENATE;\r
\r
typedef struct _EFI_IFR_DIVIDE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_DIVIDE;\r
\r
typedef struct _EFI_IFR_EQUAL {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_EQUAL;\r
\r
typedef struct _EFI_IFR_GREATER_EQUAL {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_GREATER_EQUAL;\r
\r
typedef struct _EFI_IFR_GREATER_THAN {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_GREATER_THAN;\r
\r
typedef struct _EFI_IFR_LESS_EQUAL {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_LESS_EQUAL;\r
\r
typedef struct _EFI_IFR_LESS_THAN {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_LESS_THAN;\r
\r
typedef struct _EFI_IFR_MATCH {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MATCH;\r
\r
typedef struct _EFI_IFR_MATCH2 {\r
- EFI_IFR_OP_HEADER Header;\r
- EFI_GUID SyntaxType;\r
+ EFI_IFR_OP_HEADER Header;\r
+ EFI_GUID SyntaxType;\r
} EFI_IFR_MATCH2;\r
\r
typedef struct _EFI_IFR_MULTIPLY {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MULTIPLY;\r
\r
typedef struct _EFI_IFR_MODULO {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MODULO;\r
\r
typedef struct _EFI_IFR_NOT_EQUAL {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_NOT_EQUAL;\r
\r
typedef struct _EFI_IFR_OR {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_OR;\r
\r
typedef struct _EFI_IFR_SHIFT_LEFT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_SHIFT_LEFT;\r
\r
typedef struct _EFI_IFR_SHIFT_RIGHT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_SHIFT_RIGHT;\r
\r
typedef struct _EFI_IFR_SUBTRACT {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_SUBTRACT;\r
\r
typedef struct _EFI_IFR_CONDITIONAL {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_CONDITIONAL;\r
\r
//\r
#define EFI_IFR_FF_CASE_INSENSITIVE 0x01\r
\r
typedef struct _EFI_IFR_FIND {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 Format;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 Format;\r
} EFI_IFR_FIND;\r
\r
typedef struct _EFI_IFR_MID {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MID;\r
\r
typedef struct _EFI_IFR_TOKEN {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_TOKEN;\r
\r
//\r
// Flags specifying whether to find the first matching string\r
// or the first non-matching string.\r
//\r
-#define EFI_IFR_FLAGS_FIRST_MATCHING 0x00\r
-#define EFI_IFR_FLAGS_FIRST_NON_MATCHING 0x01\r
+#define EFI_IFR_FLAGS_FIRST_MATCHING 0x00\r
+#define EFI_IFR_FLAGS_FIRST_NON_MATCHING 0x01\r
\r
typedef struct _EFI_IFR_SPAN {\r
- EFI_IFR_OP_HEADER Header;\r
- UINT8 Flags;\r
+ EFI_IFR_OP_HEADER Header;\r
+ UINT8 Flags;\r
} EFI_IFR_SPAN;\r
\r
typedef struct _EFI_IFR_SECURITY {\r
///\r
/// Standard opcode header, where Header.Op = EFI_IFR_SECURITY_OP.\r
///\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
///\r
/// Security permission level.\r
///\r
- EFI_GUID Permissions;\r
+ EFI_GUID Permissions;\r
} EFI_IFR_SECURITY;\r
\r
typedef struct _EFI_IFR_FORM_MAP_METHOD {\r
/// The string identifier which provides the human-readable name of\r
/// the configuration method for this standards map form.\r
///\r
- EFI_STRING_ID MethodTitle;\r
+ EFI_STRING_ID MethodTitle;\r
///\r
/// Identifier which uniquely specifies the configuration methods\r
/// associated with this standards map form.\r
///\r
- EFI_GUID MethodIdentifier;\r
+ EFI_GUID MethodIdentifier;\r
} EFI_IFR_FORM_MAP_METHOD;\r
\r
typedef struct _EFI_IFR_FORM_MAP {\r
/// The sequence that defines the type of opcode as well as the length\r
/// of the opcode being defined. Header.OpCode = EFI_IFR_FORM_MAP_OP.\r
///\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
///\r
/// The unique identifier for this particular form.\r
///\r
- EFI_FORM_ID FormId;\r
+ EFI_FORM_ID FormId;\r
///\r
/// One or more configuration method's name and unique identifier.\r
///\r
/// The sequence that defines the type of opcode as well as the length\r
/// of the opcode being defined. Header.OpCode = EFI_IFR_SET_OP.\r
///\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
///\r
/// Specifies the identifier of a previously declared variable store to\r
/// use when storing the question's value.\r
///\r
- EFI_VARSTORE_ID VarStoreId;\r
+ EFI_VARSTORE_ID VarStoreId;\r
union {\r
///\r
/// A 16-bit Buffer Storage offset.\r
///\r
/// Specifies the type used for storage.\r
///\r
- UINT8 VarStoreType;\r
+ UINT8 VarStoreType;\r
} EFI_IFR_SET;\r
\r
typedef struct _EFI_IFR_GET {\r
/// The sequence that defines the type of opcode as well as the length\r
/// of the opcode being defined. Header.OpCode = EFI_IFR_GET_OP.\r
///\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
///\r
/// Specifies the identifier of a previously declared variable store to\r
/// use when retrieving the value.\r
///\r
- EFI_VARSTORE_ID VarStoreId;\r
+ EFI_VARSTORE_ID VarStoreId;\r
union {\r
///\r
/// A 16-bit Buffer Storage offset.\r
///\r
/// Specifies the type used for storage.\r
///\r
- UINT8 VarStoreType;\r
+ UINT8 VarStoreType;\r
} EFI_IFR_GET;\r
\r
typedef struct _EFI_IFR_READ {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_READ;\r
\r
typedef struct _EFI_IFR_WRITE {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_WRITE;\r
\r
typedef struct _EFI_IFR_MAP {\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
} EFI_IFR_MAP;\r
//\r
// Definitions for Keyboard Package\r
///\r
/// Used to describe a physical key on a keyboard.\r
///\r
- EFI_KEY Key;\r
+ EFI_KEY Key;\r
///\r
/// Unicode character code for the Key.\r
///\r
- CHAR16 Unicode;\r
+ CHAR16 Unicode;\r
///\r
/// Unicode character code for the key with the shift key being held down.\r
///\r
- CHAR16 ShiftedUnicode;\r
+ CHAR16 ShiftedUnicode;\r
///\r
/// Unicode character code for the key with the Alt-GR being held down.\r
///\r
- CHAR16 AltGrUnicode;\r
+ CHAR16 AltGrUnicode;\r
///\r
/// Unicode character code for the key with the Alt-GR and shift keys being held down.\r
///\r
- CHAR16 ShiftedAltGrUnicode;\r
+ CHAR16 ShiftedAltGrUnicode;\r
///\r
/// Modifier keys are defined to allow for special functionality that is not necessarily\r
/// accomplished by a printable character. Many of these modifier keys are flags to toggle\r
/// certain state bits on and off inside of a keyboard driver.\r
///\r
- UINT16 Modifier;\r
- UINT16 AffectedAttribute;\r
+ UINT16 Modifier;\r
+ UINT16 AffectedAttribute;\r
} EFI_KEY_DESCRIPTOR;\r
\r
///\r
/// A key which is affected by all the standard shift modifiers.\r
/// Most keys would be expected to have this bit active.\r
///\r
-#define EFI_AFFECTED_BY_STANDARD_SHIFT 0x0001\r
+#define EFI_AFFECTED_BY_STANDARD_SHIFT 0x0001\r
\r
///\r
/// This key is affected by the caps lock so that if a keyboard driver\r
/// versus an "a" character. Having this bit turned on would tell\r
/// the keyboard driver to use the appropriate shifted state or not.\r
///\r
-#define EFI_AFFECTED_BY_CAPS_LOCK 0x0002\r
+#define EFI_AFFECTED_BY_CAPS_LOCK 0x0002\r
\r
///\r
/// Similar to the case of CAPS lock, if this bit is active, the key\r
/// is affected by the num lock being turned on.\r
///\r
-#define EFI_AFFECTED_BY_NUM_LOCK 0x0004\r
+#define EFI_AFFECTED_BY_NUM_LOCK 0x0004\r
\r
typedef struct {\r
- UINT16 LayoutLength;\r
- EFI_GUID Guid;\r
- UINT32 LayoutDescriptorStringOffset;\r
- UINT8 DescriptorCount;\r
+ UINT16 LayoutLength;\r
+ EFI_GUID Guid;\r
+ UINT32 LayoutDescriptorStringOffset;\r
+ UINT8 DescriptorCount;\r
// EFI_KEY_DESCRIPTOR Descriptors[];\r
} EFI_HII_KEYBOARD_LAYOUT;\r
\r
typedef struct {\r
- EFI_HII_PACKAGE_HEADER Header;\r
- UINT16 LayoutCount;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
+ UINT16 LayoutCount;\r
// EFI_HII_KEYBOARD_LAYOUT Layout[];\r
} EFI_HII_KEYBOARD_PACKAGE_HDR;\r
\r
//\r
// Modifier values\r
//\r
-#define EFI_NULL_MODIFIER 0x0000\r
-#define EFI_LEFT_CONTROL_MODIFIER 0x0001\r
-#define EFI_RIGHT_CONTROL_MODIFIER 0x0002\r
-#define EFI_LEFT_ALT_MODIFIER 0x0003\r
-#define EFI_RIGHT_ALT_MODIFIER 0x0004\r
-#define EFI_ALT_GR_MODIFIER 0x0005\r
-#define EFI_INSERT_MODIFIER 0x0006\r
-#define EFI_DELETE_MODIFIER 0x0007\r
-#define EFI_PAGE_DOWN_MODIFIER 0x0008\r
-#define EFI_PAGE_UP_MODIFIER 0x0009\r
-#define EFI_HOME_MODIFIER 0x000A\r
-#define EFI_END_MODIFIER 0x000B\r
-#define EFI_LEFT_SHIFT_MODIFIER 0x000C\r
-#define EFI_RIGHT_SHIFT_MODIFIER 0x000D\r
-#define EFI_CAPS_LOCK_MODIFIER 0x000E\r
-#define EFI_NUM_LOCK_MODIFIER 0x000F\r
-#define EFI_LEFT_ARROW_MODIFIER 0x0010\r
-#define EFI_RIGHT_ARROW_MODIFIER 0x0011\r
-#define EFI_DOWN_ARROW_MODIFIER 0x0012\r
-#define EFI_UP_ARROW_MODIFIER 0x0013\r
-#define EFI_NS_KEY_MODIFIER 0x0014\r
-#define EFI_NS_KEY_DEPENDENCY_MODIFIER 0x0015\r
-#define EFI_FUNCTION_KEY_ONE_MODIFIER 0x0016\r
-#define EFI_FUNCTION_KEY_TWO_MODIFIER 0x0017\r
-#define EFI_FUNCTION_KEY_THREE_MODIFIER 0x0018\r
-#define EFI_FUNCTION_KEY_FOUR_MODIFIER 0x0019\r
-#define EFI_FUNCTION_KEY_FIVE_MODIFIER 0x001A\r
-#define EFI_FUNCTION_KEY_SIX_MODIFIER 0x001B\r
-#define EFI_FUNCTION_KEY_SEVEN_MODIFIER 0x001C\r
-#define EFI_FUNCTION_KEY_EIGHT_MODIFIER 0x001D\r
-#define EFI_FUNCTION_KEY_NINE_MODIFIER 0x001E\r
-#define EFI_FUNCTION_KEY_TEN_MODIFIER 0x001F\r
-#define EFI_FUNCTION_KEY_ELEVEN_MODIFIER 0x0020\r
-#define EFI_FUNCTION_KEY_TWELVE_MODIFIER 0x0021\r
+#define EFI_NULL_MODIFIER 0x0000\r
+#define EFI_LEFT_CONTROL_MODIFIER 0x0001\r
+#define EFI_RIGHT_CONTROL_MODIFIER 0x0002\r
+#define EFI_LEFT_ALT_MODIFIER 0x0003\r
+#define EFI_RIGHT_ALT_MODIFIER 0x0004\r
+#define EFI_ALT_GR_MODIFIER 0x0005\r
+#define EFI_INSERT_MODIFIER 0x0006\r
+#define EFI_DELETE_MODIFIER 0x0007\r
+#define EFI_PAGE_DOWN_MODIFIER 0x0008\r
+#define EFI_PAGE_UP_MODIFIER 0x0009\r
+#define EFI_HOME_MODIFIER 0x000A\r
+#define EFI_END_MODIFIER 0x000B\r
+#define EFI_LEFT_SHIFT_MODIFIER 0x000C\r
+#define EFI_RIGHT_SHIFT_MODIFIER 0x000D\r
+#define EFI_CAPS_LOCK_MODIFIER 0x000E\r
+#define EFI_NUM_LOCK_MODIFIER 0x000F\r
+#define EFI_LEFT_ARROW_MODIFIER 0x0010\r
+#define EFI_RIGHT_ARROW_MODIFIER 0x0011\r
+#define EFI_DOWN_ARROW_MODIFIER 0x0012\r
+#define EFI_UP_ARROW_MODIFIER 0x0013\r
+#define EFI_NS_KEY_MODIFIER 0x0014\r
+#define EFI_NS_KEY_DEPENDENCY_MODIFIER 0x0015\r
+#define EFI_FUNCTION_KEY_ONE_MODIFIER 0x0016\r
+#define EFI_FUNCTION_KEY_TWO_MODIFIER 0x0017\r
+#define EFI_FUNCTION_KEY_THREE_MODIFIER 0x0018\r
+#define EFI_FUNCTION_KEY_FOUR_MODIFIER 0x0019\r
+#define EFI_FUNCTION_KEY_FIVE_MODIFIER 0x001A\r
+#define EFI_FUNCTION_KEY_SIX_MODIFIER 0x001B\r
+#define EFI_FUNCTION_KEY_SEVEN_MODIFIER 0x001C\r
+#define EFI_FUNCTION_KEY_EIGHT_MODIFIER 0x001D\r
+#define EFI_FUNCTION_KEY_NINE_MODIFIER 0x001E\r
+#define EFI_FUNCTION_KEY_TEN_MODIFIER 0x001F\r
+#define EFI_FUNCTION_KEY_ELEVEN_MODIFIER 0x0020\r
+#define EFI_FUNCTION_KEY_TWELVE_MODIFIER 0x0021\r
\r
//\r
// Keys that have multiple control functions based on modifier\r
// is still a nonprinting character, but might have an alternate\r
// control function like SYSREQUEST\r
//\r
-#define EFI_PRINT_MODIFIER 0x0022\r
-#define EFI_SYS_REQUEST_MODIFIER 0x0023\r
-#define EFI_SCROLL_LOCK_MODIFIER 0x0024\r
-#define EFI_PAUSE_MODIFIER 0x0025\r
-#define EFI_BREAK_MODIFIER 0x0026\r
+#define EFI_PRINT_MODIFIER 0x0022\r
+#define EFI_SYS_REQUEST_MODIFIER 0x0023\r
+#define EFI_SCROLL_LOCK_MODIFIER 0x0024\r
+#define EFI_PAUSE_MODIFIER 0x0025\r
+#define EFI_BREAK_MODIFIER 0x0026\r
\r
-#define EFI_LEFT_LOGO_MODIFIER 0x0027\r
-#define EFI_RIGHT_LOGO_MODIFIER 0x0028\r
-#define EFI_MENU_MODIFIER 0x0029\r
+#define EFI_LEFT_LOGO_MODIFIER 0x0027\r
+#define EFI_RIGHT_LOGO_MODIFIER 0x0028\r
+#define EFI_MENU_MODIFIER 0x0029\r
\r
///\r
/// Animation IFR opcode\r
/// Standard opcode header, where Header.OpCode is\r
/// EFI_IFR_ANIMATION_OP.\r
///\r
- EFI_IFR_OP_HEADER Header;\r
+ EFI_IFR_OP_HEADER Header;\r
///\r
/// Animation identifier in the HII database.\r
///\r
- EFI_ANIMATION_ID Id;\r
+ EFI_ANIMATION_ID Id;\r
} EFI_IFR_ANIMATION;\r
\r
///\r
///\r
/// Standard package header, where Header.Type = EFI_HII_PACKAGE_ANIMATIONS.\r
///\r
- EFI_HII_PACKAGE_HEADER Header;\r
+ EFI_HII_PACKAGE_HEADER Header;\r
///\r
/// Offset, relative to this header, of the animation information. If\r
/// this is zero, then there are no animation sequences in the package.\r
///\r
- UINT32 AnimationInfoOffset;\r
+ UINT32 AnimationInfoOffset;\r
} EFI_HII_ANIMATION_PACKAGE_HDR;\r
\r
///\r
/// with each block prefixed by a single byte header EFI_HII_ANIMATION_BLOCK.\r
///\r
typedef struct _EFI_HII_ANIMATION_BLOCK {\r
- UINT8 BlockType;\r
- //UINT8 BlockBody[];\r
+ UINT8 BlockType;\r
+ // UINT8 BlockBody[];\r
} EFI_HII_ANIMATION_BLOCK;\r
\r
///\r
/// Animation block types.\r
///\r
-#define EFI_HII_AIBT_END 0x00\r
-#define EFI_HII_AIBT_OVERLAY_IMAGES 0x10\r
-#define EFI_HII_AIBT_CLEAR_IMAGES 0x11\r
-#define EFI_HII_AIBT_RESTORE_SCRN 0x12\r
-#define EFI_HII_AIBT_OVERLAY_IMAGES_LOOP 0x18\r
-#define EFI_HII_AIBT_CLEAR_IMAGES_LOOP 0x19\r
-#define EFI_HII_AIBT_RESTORE_SCRN_LOOP 0x1A\r
-#define EFI_HII_AIBT_DUPLICATE 0x20\r
-#define EFI_HII_AIBT_SKIP2 0x21\r
-#define EFI_HII_AIBT_SKIP1 0x22\r
-#define EFI_HII_AIBT_EXT1 0x30\r
-#define EFI_HII_AIBT_EXT2 0x31\r
-#define EFI_HII_AIBT_EXT4 0x32\r
+#define EFI_HII_AIBT_END 0x00\r
+#define EFI_HII_AIBT_OVERLAY_IMAGES 0x10\r
+#define EFI_HII_AIBT_CLEAR_IMAGES 0x11\r
+#define EFI_HII_AIBT_RESTORE_SCRN 0x12\r
+#define EFI_HII_AIBT_OVERLAY_IMAGES_LOOP 0x18\r
+#define EFI_HII_AIBT_CLEAR_IMAGES_LOOP 0x19\r
+#define EFI_HII_AIBT_RESTORE_SCRN_LOOP 0x1A\r
+#define EFI_HII_AIBT_DUPLICATE 0x20\r
+#define EFI_HII_AIBT_SKIP2 0x21\r
+#define EFI_HII_AIBT_SKIP1 0x22\r
+#define EFI_HII_AIBT_EXT1 0x30\r
+#define EFI_HII_AIBT_EXT2 0x31\r
+#define EFI_HII_AIBT_EXT4 0x32\r
\r
///\r
/// Extended block headers used for variable sized animation records\r
///\r
/// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT1.\r
///\r
- EFI_HII_ANIMATION_BLOCK Header;\r
+ EFI_HII_ANIMATION_BLOCK Header;\r
///\r
/// The block type.\r
///\r
- UINT8 BlockType2;\r
+ UINT8 BlockType2;\r
///\r
/// Size of the animation block, in bytes, including the animation block header.\r
///\r
- UINT8 Length;\r
+ UINT8 Length;\r
} EFI_HII_AIBT_EXT1_BLOCK;\r
\r
typedef struct _EFI_HII_AIBT_EXT2_BLOCK {\r
///\r
/// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT2.\r
///\r
- EFI_HII_ANIMATION_BLOCK Header;\r
+ EFI_HII_ANIMATION_BLOCK Header;\r
///\r
/// The block type\r
///\r
- UINT8 BlockType2;\r
+ UINT8 BlockType2;\r
///\r
/// Size of the animation block, in bytes, including the animation block header.\r
///\r
- UINT16 Length;\r
+ UINT16 Length;\r
} EFI_HII_AIBT_EXT2_BLOCK;\r
\r
typedef struct _EFI_HII_AIBT_EXT4_BLOCK {\r
///\r
/// Standard animation header, where Header.BlockType = EFI_HII_AIBT_EXT4.\r
///\r
- EFI_HII_ANIMATION_BLOCK Header;\r
+ EFI_HII_ANIMATION_BLOCK Header;\r
///\r
/// The block type\r
///\r
- UINT8 BlockType2;\r
+ UINT8 BlockType2;\r
///\r
/// Size of the animation block, in bytes, including the animation block header.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
} EFI_HII_AIBT_EXT4_BLOCK;\r
\r
typedef struct _EFI_HII_ANIMATION_CELL {\r
/// The X offset from the upper left hand corner of the logical\r
/// window to position the indexed image.\r
///\r
- UINT16 OffsetX;\r
+ UINT16 OffsetX;\r
///\r
/// The Y offset from the upper left hand corner of the logical\r
/// window to position the indexed image.\r
///\r
- UINT16 OffsetY;\r
+ UINT16 OffsetY;\r
///\r
/// The image to display at the specified offset from the upper left\r
/// hand corner of the logical window.\r
///\r
- EFI_IMAGE_ID ImageId;\r
+ EFI_IMAGE_ID ImageId;\r
///\r
/// The number of milliseconds to delay after displaying the indexed\r
/// image and before continuing on to the next linked image. If value\r
/// is zero, no delay.\r
///\r
- UINT16 Delay;\r
+ UINT16 Delay;\r
} EFI_HII_ANIMATION_CELL;\r
\r
///\r
/// image that can be displayed alone. If the value is zero, no image\r
/// is displayed.\r
///\r
- EFI_IMAGE_ID DftImageId;\r
+ EFI_IMAGE_ID DftImageId;\r
///\r
/// The overall width of the set of images (logical window width).\r
///\r
- UINT16 Width;\r
+ UINT16 Width;\r
///\r
/// The overall height of the set of images (logical window height).\r
///\r
- UINT16 Height;\r
+ UINT16 Height;\r
///\r
/// The number of EFI_HII_ANIMATION_CELL contained in the\r
/// animation sequence.\r
///\r
- UINT16 CellCount;\r
+ UINT16 CellCount;\r
///\r
/// An array of CellCount animation cells.\r
///\r
- EFI_HII_ANIMATION_CELL AnimationCell[1];\r
+ EFI_HII_ANIMATION_CELL AnimationCell[1];\r
} EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK;\r
\r
///\r
/// image that can be displayed alone. If the value is zero, no image\r
/// is displayed.\r
///\r
- EFI_IMAGE_ID DftImageId;\r
+ EFI_IMAGE_ID DftImageId;\r
///\r
/// The overall width of the set of images (logical window width).\r
///\r
- UINT16 Width;\r
+ UINT16 Width;\r
///\r
/// The overall height of the set of images (logical window height).\r
///\r
- UINT16 Height;\r
+ UINT16 Height;\r
///\r
/// The number of EFI_HII_ANIMATION_CELL contained in the\r
/// animation sequence.\r
///\r
- UINT16 CellCount;\r
+ UINT16 CellCount;\r
///\r
/// The color to clear the logical window to before displaying the\r
/// indexed image.\r
///\r
- EFI_HII_RGB_PIXEL BackgndColor;\r
+ EFI_HII_RGB_PIXEL BackgndColor;\r
///\r
/// An array of CellCount animation cells.\r
///\r
- EFI_HII_ANIMATION_CELL AnimationCell[1];\r
+ EFI_HII_ANIMATION_CELL AnimationCell[1];\r
} EFI_HII_AIBT_CLEAR_IMAGES_BLOCK;\r
\r
///\r
/// image that can be displayed alone. If the value is zero, no image\r
/// is displayed.\r
///\r
- EFI_IMAGE_ID DftImageId;\r
+ EFI_IMAGE_ID DftImageId;\r
///\r
/// The overall width of the set of images (logical window width).\r
///\r
- UINT16 Width;\r
+ UINT16 Width;\r
///\r
/// The overall height of the set of images (logical window height).\r
///\r
- UINT16 Height;\r
+ UINT16 Height;\r
///\r
/// The number of EFI_HII_ANIMATION_CELL contained in the\r
/// animation sequence.\r
///\r
- UINT16 CellCount;\r
+ UINT16 CellCount;\r
///\r
/// An array of CellCount animation cells.\r
///\r
- EFI_HII_ANIMATION_CELL AnimationCell[1];\r
+ EFI_HII_ANIMATION_CELL AnimationCell[1];\r
} EFI_HII_AIBT_RESTORE_SCRN_BLOCK;\r
\r
///\r
/// An animation block to describe an animation sequence that continuously cycles,\r
/// and where one image is simply displayed over the previous image.\r
///\r
-typedef EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOCK;\r
+typedef EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOCK;\r
\r
///\r
/// An animation block to describe an animation sequence that continuously cycles,\r
/// and where the logical window is cleared to the specified color before\r
/// the next image is displayed.\r
///\r
-typedef EFI_HII_AIBT_CLEAR_IMAGES_BLOCK EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK;\r
+typedef EFI_HII_AIBT_CLEAR_IMAGES_BLOCK EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK;\r
\r
///\r
/// An animation block to describe an animation sequence that continuously cycles,\r
/// and where the screen is restored to the original state before\r
/// the next image is displayed.\r
///\r
-typedef EFI_HII_AIBT_RESTORE_SCRN_BLOCK EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK;\r
+typedef EFI_HII_AIBT_RESTORE_SCRN_BLOCK EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK;\r
\r
///\r
/// Assigns a new character value to a previously defined animation sequence.\r
/// The previously defined animation ID with the exact same\r
/// animation information.\r
///\r
- EFI_ANIMATION_ID AnimationId;\r
+ EFI_ANIMATION_ID AnimationId;\r
} EFI_HII_AIBT_DUPLICATE_BLOCK;\r
\r
///\r
///\r
/// The unsigned 8-bit value to add to AnimationIdCurrent.\r
///\r
- UINT8 SkipCount;\r
+ UINT8 SkipCount;\r
} EFI_HII_AIBT_SKIP1_BLOCK;\r
\r
///\r
///\r
/// The unsigned 16-bit value to add to AnimationIdCurrent.\r
///\r
- UINT16 SkipCount;\r
+ UINT16 SkipCount;\r
} EFI_HII_AIBT_SKIP2_BLOCK;\r
\r
#pragma pack()\r
\r
-\r
-\r
///\r
/// References to string tokens must use this macro to enable scanning for\r
/// token usages.\r
/// STRING_TOKEN is not defined in UEFI specification. But it is placed\r
/// here for the easy access by C files and VFR source files.\r
///\r
-#define STRING_TOKEN(t) t\r
+#define STRING_TOKEN(t) t\r
\r
///\r
/// IMAGE_TOKEN is not defined in UEFI specification. But it is placed\r
/// here for the easy access by C files and VFR source files.\r
///\r
-#define IMAGE_TOKEN(t) t\r
+#define IMAGE_TOKEN(t) t\r
\r
#endif\r
///\r
/// Attributes of variable.\r
///\r
-#define EFI_VARIABLE_NON_VOLATILE 0x00000001\r
-#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002\r
-#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004\r
+#define EFI_VARIABLE_NON_VOLATILE 0x00000001\r
+#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002\r
+#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004\r
///\r
/// This attribute is identified by the mnemonic 'HR'\r
/// elsewhere in this specification.\r
///\r
-#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008\r
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x00000008\r
///\r
/// Attributes of Authenticated Variable\r
///\r
-#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020\r
-#define EFI_VARIABLE_APPEND_WRITE 0x00000040\r
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x00000020\r
+#define EFI_VARIABLE_APPEND_WRITE 0x00000040\r
///\r
/// NOTE: EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and should be considered reserved.\r
///\r
-#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010\r
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x00000010\r
\r
#ifndef VFRCOMPILE\r
-#include <Guid/WinCertificate.h>\r
+ #include <Guid/WinCertificate.h>\r
///\r
/// Enumeration of memory types introduced in UEFI.\r
///\r
/// Unique signatures have been generated for the EFI System Table,\r
/// the EFI Boot Services Table, and the EFI Runtime Services Table.\r
///\r
- UINT64 Signature;\r
+ UINT64 Signature;\r
///\r
/// The revision of the EFI Specification to which this table\r
/// conforms. The upper 16 bits of this field contain the major\r
/// revision value, and the lower 16 bits contain the minor revision\r
/// value. The minor revision values are limited to the range of 00..99.\r
///\r
- UINT32 Revision;\r
+ UINT32 Revision;\r
///\r
/// The size, in bytes, of the entire table including the EFI_TABLE_HEADER.\r
///\r
- UINT32 HeaderSize;\r
+ UINT32 HeaderSize;\r
///\r
/// The 32-bit CRC for the entire table. This value is computed by\r
/// setting this field to 0, and computing the 32-bit CRC for HeaderSize bytes.\r
///\r
- UINT32 CRC32;\r
+ UINT32 CRC32;\r
///\r
/// Reserved field that must be set to 0.\r
///\r
- UINT32 Reserved;\r
+ UINT32 Reserved;\r
} EFI_TABLE_HEADER;\r
\r
///\r
/// replay. Incremented during each\r
/// "Write" access.\r
///\r
- UINT64 MonotonicCount;\r
+ UINT64 MonotonicCount;\r
///\r
/// Provides the authorization for the variable\r
/// access. It is a signature across the\r
/// associated with a public key that has been\r
/// provisioned via the key exchange.\r
///\r
- WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
} EFI_VARIABLE_AUTHENTICATION;\r
\r
///\r
/// For the TimeStamp value, components Pad1, Nanosecond, TimeZone, Daylight and\r
/// Pad2 shall be set to 0. This means that the time shall always be expressed in GMT.\r
///\r
- EFI_TIME TimeStamp;\r
+ EFI_TIME TimeStamp;\r
///\r
/// Only a CertType of EFI_CERT_TYPE_PKCS7_GUID is accepted.\r
///\r
- WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
- } EFI_VARIABLE_AUTHENTICATION_2;\r
+ WIN_CERTIFICATE_UEFI_GUID AuthInfo;\r
+} EFI_VARIABLE_AUTHENTICATION_2;\r
#endif // VFRCOMPILE\r
\r
#endif\r
///\r
/// UNDI ROM ID and devive ID signature.\r
///\r
-#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
+#define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
\r
///\r
/// BUS ROM ID signatures.\r
///\r
-#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r
-#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r
-#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r
-#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r
+#define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')\r
+#define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')\r
+#define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')\r
+#define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')\r
\r
#define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))\r
\r
(((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \\r
(((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))\r
\r
-\r
#define PXE_CPBSIZE_NOT_USED 0 ///< zero\r
#define PXE_DBSIZE_NOT_USED 0 ///< zero\r
#define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r
#define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero\r
#define PXE_CONST CONST\r
\r
-#define PXE_VOLATILE volatile\r
+#define PXE_VOLATILE volatile\r
\r
-typedef VOID PXE_VOID;\r
-typedef UINT8 PXE_UINT8;\r
-typedef UINT16 PXE_UINT16;\r
-typedef UINT32 PXE_UINT32;\r
-typedef UINTN PXE_UINTN;\r
+typedef VOID PXE_VOID;\r
+typedef UINT8 PXE_UINT8;\r
+typedef UINT16 PXE_UINT16;\r
+typedef UINT32 PXE_UINT32;\r
+typedef UINTN PXE_UINTN;\r
\r
///\r
/// Typedef unsigned long PXE_UINT64.\r
///\r
-typedef UINT64 PXE_UINT64;\r
+typedef UINT64 PXE_UINT64;\r
\r
typedef PXE_UINT8 PXE_BOOL;\r
-#define PXE_FALSE 0 ///< zero\r
-#define PXE_TRUE (!PXE_FALSE)\r
+#define PXE_FALSE 0 ///< zero\r
+#define PXE_TRUE (!PXE_FALSE)\r
\r
-typedef PXE_UINT16 PXE_OPCODE;\r
+typedef PXE_UINT16 PXE_OPCODE;\r
\r
///\r
/// Return UNDI operational state.\r
///\r
/// Change UNDI operational state from Started to Stopped.\r
///\r
-#define PXE_OPCODE_STOP 0x0002\r
+#define PXE_OPCODE_STOP 0x0002\r
\r
///\r
/// Get UNDI initialization information.\r
///\r
/// Changed UNDI operational state from Started to Initialized.\r
///\r
-#define PXE_OPCODE_INITIALIZE 0x0005\r
+#define PXE_OPCODE_INITIALIZE 0x0005\r
\r
///\r
/// Re-initialize the NIC H/W.\r
///\r
/// Change the UNDI operational state from Initialized to Started.\r
///\r
-#define PXE_OPCODE_SHUTDOWN 0x0007\r
+#define PXE_OPCODE_SHUTDOWN 0x0007\r
\r
///\r
/// Read & change state of external interrupt enables.\r
///\r
/// Read traffic statistics.\r
///\r
-#define PXE_OPCODE_STATISTICS 0x000B\r
+#define PXE_OPCODE_STATISTICS 0x000B\r
\r
///\r
/// Convert multicast IP address to multicast MAC address.\r
///\r
/// Read or change non-volatile storage on the NIC.\r
///\r
-#define PXE_OPCODE_NVDATA 0x000D\r
+#define PXE_OPCODE_NVDATA 0x000D\r
\r
///\r
/// Get & clear interrupt status.\r
///\r
-#define PXE_OPCODE_GET_STATUS 0x000E\r
+#define PXE_OPCODE_GET_STATUS 0x000E\r
\r
///\r
/// Fill media header in packet for transmit.\r
///\r
/// Transmit packet(s).\r
///\r
-#define PXE_OPCODE_TRANSMIT 0x0010\r
+#define PXE_OPCODE_TRANSMIT 0x0010\r
\r
///\r
/// Receive packet.\r
///\r
/// Last valid PXE UNDI OpCode number.\r
///\r
-#define PXE_OPCODE_LAST_VALID 0x0011\r
+#define PXE_OPCODE_LAST_VALID 0x0011\r
\r
-typedef PXE_UINT16 PXE_OPFLAGS;\r
+typedef PXE_UINT16 PXE_OPFLAGS;\r
\r
#define PXE_OPFLAGS_NOT_USED 0x0000\r
\r
/// Select whether to enable or disable external interrupt signals.\r
/// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.\r
///\r
-#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r
-#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r
-#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r
-#define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r
+#define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000\r
+#define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000\r
+#define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000\r
+#define PXE_OPFLAGS_INTERRUPT_READ 0x0000\r
\r
///\r
/// Enable receive interrupts. An external interrupt will be generated\r
/// after a complete non-error packet has been received.\r
///\r
-#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r
+#define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001\r
\r
///\r
/// Enable transmit interrupts. An external interrupt will be generated\r
/// Enable command interrupts. An external interrupt will be generated\r
/// when command execution stops.\r
///\r
-#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r
+#define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004\r
\r
///\r
/// Generate software interrupt. Setting this bit generates an external\r
/// To reset the contents of the multicast MAC address filter list,\r
/// set this OpFlag:\r
///\r
-#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r
+#define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000\r
\r
///\r
/// Enable unicast packet receiving. Packets sent to the current station\r
/// of the multicast MAC addresses in the multicast MAC address filter\r
/// list will be received. If the filter list is empty, no multicast\r
///\r
-#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
+#define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
\r
///\r
/// Enable promiscuous packet receiving. All packets will be received.\r
///\r
/// Select the type of non-volatile data operation.\r
///\r
-#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r
-#define PXE_OPFLAGS_NVDATA_READ 0x0000\r
-#define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r
+#define PXE_OPFLAGS_NVDATA_OPMASK 0x0001\r
+#define PXE_OPFLAGS_NVDATA_READ 0x0000\r
+#define PXE_OPFLAGS_NVDATA_WRITE 0x0001\r
\r
///\r
/// UNDI Get Status.\r
/// buffers. Do not plan on getting one buffer per interrupt. Some\r
/// NICs and UNDIs may transmit multiple buffers per interrupt.\r
///\r
-#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r
+#define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002\r
\r
///\r
/// Return current media status.\r
///\r
-#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004\r
+#define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004\r
\r
///\r
/// UNDI Fill Header.\r
#define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001\r
#define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000\r
\r
-#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r
-#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r
-#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r
+#define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002\r
+#define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002\r
+#define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000\r
\r
///\r
/// UNDI Receive.\r
///\r
/// PXE STATFLAGS.\r
///\r
-typedef PXE_UINT16 PXE_STATFLAGS;\r
+typedef PXE_UINT16 PXE_STATFLAGS;\r
\r
#define PXE_STATFLAGS_INITIALIZE 0x0000\r
\r
///\r
/// UNDI Get State.\r
///\r
-#define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r
-#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r
-#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r
-#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r
+#define PXE_STATFLAGS_GET_STATE_MASK 0x0003\r
+#define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002\r
+#define PXE_STATFLAGS_GET_STATE_STARTED 0x0001\r
+#define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000\r
\r
///\r
/// UNDI Start.\r
///\r
/// If set, receive interrupts are enabled.\r
///\r
-#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r
+#define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001\r
\r
///\r
/// If set, transmit interrupts are enabled.\r
///\r
/// If set, command interrupts are enabled.\r
///\r
-#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r
+#define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004\r
\r
///\r
/// UNDI Receive Filters.\r
/// If set, multicast packets that match up with the multicast address\r
/// filter list will be received.\r
///\r
-#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
+#define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004\r
\r
///\r
/// If set, all packets will be received.\r
///\r
/// Use to determine if an interrupt has occurred.\r
///\r
-#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r
-#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r
+#define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F\r
+#define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000\r
\r
///\r
/// If set, at least one receive interrupt occurred.\r
///\r
/// If set, at least one transmit interrupt occurred.\r
///\r
-#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r
+#define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002\r
\r
///\r
/// If set, at least one command interrupt occurred.\r
///\r
/// If set, at least one software interrupt occurred.\r
///\r
-#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r
+#define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008\r
\r
///\r
/// This flag is set if the transmitted buffer queue is empty. This flag\r
\r
///\r
/// UNDI Receive\r
-///.\r
+/// .\r
\r
///\r
/// No additional StatFlags.\r
///\r
-typedef PXE_UINT16 PXE_STATCODE;\r
+typedef PXE_UINT16 PXE_STATCODE;\r
\r
-#define PXE_STATCODE_INITIALIZE 0x0000\r
+#define PXE_STATCODE_INITIALIZE 0x0000\r
\r
///\r
/// Common StatCodes returned by all UNDI commands, UNDI protocol functions\r
/// and BC protocol functions.\r
///\r
-#define PXE_STATCODE_SUCCESS 0x0000\r
+#define PXE_STATCODE_SUCCESS 0x0000\r
\r
#define PXE_STATCODE_INVALID_CDB 0x0001\r
#define PXE_STATCODE_INVALID_CPB 0x0002\r
#define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012\r
#define PXE_STATCODE_NO_DATA 0x0013\r
\r
-typedef PXE_UINT16 PXE_IFNUM;\r
+typedef PXE_UINT16 PXE_IFNUM;\r
\r
///\r
/// This interface number must be passed to the S/W UNDI Start command.\r
///\r
-#define PXE_IFNUM_START 0x0000\r
+#define PXE_IFNUM_START 0x0000\r
\r
///\r
/// This interface number is returned by the S/W UNDI Get State and\r
/// Start commands if information in the CDB, CPB or DB is invalid.\r
///\r
-#define PXE_IFNUM_INVALID 0x0000\r
+#define PXE_IFNUM_INVALID 0x0000\r
\r
-typedef PXE_UINT16 PXE_CONTROL;\r
+typedef PXE_UINT16 PXE_CONTROL;\r
\r
///\r
/// Setting this flag directs the UNDI to queue this command for later\r
/// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL\r
/// error is returned.\r
///\r
-#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r
+#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002\r
\r
///\r
/// These two bit values are used to determine if there are more UNDI\r
#define PXE_CONTROL_LINK 0x0001\r
#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000\r
\r
-typedef PXE_UINT8 PXE_FRAME_TYPE;\r
+typedef PXE_UINT8 PXE_FRAME_TYPE;\r
\r
-#define PXE_FRAME_TYPE_NONE 0x00\r
-#define PXE_FRAME_TYPE_UNICAST 0x01\r
-#define PXE_FRAME_TYPE_BROADCAST 0x02\r
-#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03\r
-#define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r
-#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05\r
+#define PXE_FRAME_TYPE_NONE 0x00\r
+#define PXE_FRAME_TYPE_UNICAST 0x01\r
+#define PXE_FRAME_TYPE_BROADCAST 0x02\r
+#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03\r
+#define PXE_FRAME_TYPE_PROMISCUOUS 0x04\r
+#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05\r
\r
-#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST\r
+#define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST\r
\r
-typedef PXE_UINT32 PXE_IPV4;\r
+typedef PXE_UINT32 PXE_IPV4;\r
\r
-typedef PXE_UINT32 PXE_IPV6[4];\r
+typedef PXE_UINT32 PXE_IPV6[4];\r
#define PXE_MAC_LENGTH 32\r
\r
-typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r
+typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];\r
\r
-typedef PXE_UINT8 PXE_IFTYPE;\r
-typedef UINT16 PXE_MEDIA_PROTOCOL;\r
+typedef PXE_UINT8 PXE_IFTYPE;\r
+typedef UINT16 PXE_MEDIA_PROTOCOL;\r
\r
///\r
/// This information is from the ARP section of RFC 1700.\r
#define PXE_IFTYPE_FIBRE_CHANNEL 0x12\r
\r
typedef struct s_pxe_hw_undi {\r
- PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
- PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).\r
- PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.\r
- PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
- PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
- PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
- PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
- PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
- PXE_UINT8 reserved; ///< zero, not used.\r
- PXE_UINT32 Implementation; ///< implementation flags.\r
+ PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
+ PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).\r
+ PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.\r
+ PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
+ PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
+ PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
+ PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
+ PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
+ PXE_UINT8 reserved; ///< zero, not used.\r
+ PXE_UINT32 Implementation; ///< implementation flags.\r
///< reserved ///< vendor use.\r
///< UINT32 Status; ///< status port.\r
///< UINT32 Command; ///< command port.\r
///\r
/// If set, last command failed.\r
///\r
-#define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r
+#define PXE_HWSTAT_COMMAND_FAILED 0x20000000\r
\r
///\r
/// If set, identifies enabled receive filters.\r
///\r
-#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r
-#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r
-#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r
-#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r
-#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r
+#define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000\r
+#define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800\r
+#define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400\r
+#define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200\r
+#define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100\r
\r
///\r
/// If set, identifies enabled external interrupts.\r
///\r
-#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r
-#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r
-#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r
-#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r
+#define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080\r
+#define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040\r
+#define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020\r
+#define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010\r
\r
///\r
/// If set, identifies pending interrupts.\r
///\r
-#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r
-#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r
-#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r
-#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r
+#define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008\r
+#define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004\r
+#define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002\r
+#define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001\r
\r
///\r
/// Command port definitions.\r
///\r
/// Use these to enable/disable receive filters.\r
///\r
-#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r
-#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r
-#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r
-#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r
-#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r
+#define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000\r
+#define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800\r
+#define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400\r
+#define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200\r
+#define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100\r
\r
///\r
/// Use these to enable/disable external interrupts.\r
///\r
-#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r
-#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r
-#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r
-#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r
+#define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080\r
+#define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040\r
+#define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020\r
+#define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010\r
\r
///\r
/// Use these to clear pending external interrupts.\r
#define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001\r
\r
typedef struct s_pxe_sw_undi {\r
- PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
- PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).\r
- PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.\r
- PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
- PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
- PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
- PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
- PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
- PXE_UINT8 reserved1; ///< zero, not used.\r
- PXE_UINT32 Implementation; ///< Implementation flags.\r
- PXE_UINT64 EntryPoint; ///< API entry point.\r
- PXE_UINT8 reserved2[3]; ///< zero, not used.\r
- PXE_UINT8 BusCnt; ///< number of bustypes supported.\r
- PXE_UINT32 BusType[1]; ///< list of supported bustypes.\r
+ PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.\r
+ PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).\r
+ PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.\r
+ PXE_UINT8 Rev; ///< PXE_ROMID_REV.\r
+ PXE_UINT8 IFcnt; ///< physical connector count lower byte.\r
+ PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.\r
+ PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.\r
+ PXE_UINT8 IFcntExt; ///< physical connector count upper byte.\r
+ PXE_UINT8 reserved1; ///< zero, not used.\r
+ PXE_UINT32 Implementation; ///< Implementation flags.\r
+ PXE_UINT64 EntryPoint; ///< API entry point.\r
+ PXE_UINT8 reserved2[3]; ///< zero, not used.\r
+ PXE_UINT8 BusCnt; ///< number of bustypes supported.\r
+ PXE_UINT32 BusType[1]; ///< list of supported bustypes.\r
} PXE_SW_UNDI;\r
\r
typedef union u_pxe_undi {\r
- PXE_HW_UNDI hw;\r
- PXE_SW_UNDI sw;\r
+ PXE_HW_UNDI hw;\r
+ PXE_SW_UNDI sw;\r
} PXE_UNDI;\r
\r
///\r
/// Signature of !PXE structure.\r
///\r
-#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
+#define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')\r
\r
///\r
/// !PXE structure format revision\r
-///.\r
-#define PXE_ROMID_REV 0x02\r
+/// .\r
+#define PXE_ROMID_REV 0x02\r
\r
///\r
/// UNDI command interface revision. These are the values that get sent\r
/// in option 94 (Client Network Interface Identifier) in the DHCP Discover\r
/// and PXE Boot Server Request packets.\r
///\r
-#define PXE_ROMID_MAJORVER 0x03\r
-#define PXE_ROMID_MINORVER 0x01\r
+#define PXE_ROMID_MAJORVER 0x03\r
+#define PXE_ROMID_MINORVER 0x01\r
\r
///\r
/// Implementation flags.\r
#define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001\r
\r
typedef struct s_pxe_cdb {\r
- PXE_OPCODE OpCode;\r
- PXE_OPFLAGS OpFlags;\r
- PXE_UINT16 CPBsize;\r
- PXE_UINT16 DBsize;\r
- PXE_UINT64 CPBaddr;\r
- PXE_UINT64 DBaddr;\r
- PXE_STATCODE StatCode;\r
- PXE_STATFLAGS StatFlags;\r
- PXE_UINT16 IFnum;\r
- PXE_CONTROL Control;\r
+ PXE_OPCODE OpCode;\r
+ PXE_OPFLAGS OpFlags;\r
+ PXE_UINT16 CPBsize;\r
+ PXE_UINT16 DBsize;\r
+ PXE_UINT64 CPBaddr;\r
+ PXE_UINT64 DBaddr;\r
+ PXE_STATCODE StatCode;\r
+ PXE_STATFLAGS StatFlags;\r
+ PXE_UINT16 IFnum;\r
+ PXE_CONTROL Control;\r
} PXE_CDB;\r
\r
typedef union u_pxe_ip_addr {\r
- PXE_IPV6 IPv6;\r
- PXE_IPV4 IPv4;\r
+ PXE_IPV6 IPv6;\r
+ PXE_IPV4 IPv4;\r
} PXE_IP_ADDR;\r
\r
typedef union pxe_device {\r
/// See S/W UNDI ROMID structure definition for PCI and\r
/// PCC BusType definitions.\r
///\r
- PXE_UINT32 BusType;\r
+ PXE_UINT32 BusType;\r
\r
///\r
/// Bus, device & function numbers that locate this device.\r
///\r
- PXE_UINT16 Bus;\r
- PXE_UINT8 Device;\r
- PXE_UINT8 Function;\r
- }\r
- PCI, PCC;\r
-\r
+ PXE_UINT16 Bus;\r
+ PXE_UINT8 Device;\r
+ PXE_UINT8 Function;\r
+ } PCI, PCC;\r
} PXE_DEVICE;\r
\r
///\r
/// cpb and db definitions\r
///\r
-#define MAX_PCI_CONFIG_LEN 64 ///< # of dwords.\r
-#define MAX_EEPROM_LEN 128 ///< # of dwords.\r
-#define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done.\r
-#define MAX_MCAST_ADDRESS_CNT 8\r
+#define MAX_PCI_CONFIG_LEN 64 ///< # of dwords.\r
+#define MAX_EEPROM_LEN 128 ///< # of dwords.\r
+#define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done.\r
+#define MAX_MCAST_ADDRESS_CNT 8\r
\r
typedef struct s_pxe_cpb_start_30 {\r
///\r
///\r
/// This field cannot be set to zero.\r
///\r
- UINT64 Delay;\r
+ UINT64 Delay;\r
\r
///\r
/// PXE_VOID Block(UINT32 enable);\r
///\r
/// This field cannot be set to zero.\r
///\r
- UINT64 Block;\r
+ UINT64 Block;\r
\r
///\r
/// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);\r
/// This field can be set to zero if virtual and physical addresses\r
/// are equal.\r
///\r
- UINT64 Virt2Phys;\r
+ UINT64 Virt2Phys;\r
///\r
/// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,\r
/// UINT64 buf_addr);\r
///\r
/// This field can not be set to zero.\r
///\r
- UINT64 Mem_IO;\r
+ UINT64 Mem_IO;\r
} PXE_CPB_START_30;\r
\r
typedef struct s_pxe_cpb_start_31 {\r
///\r
/// This field cannot be set to zero.\r
///\r
- UINT64 Delay;\r
+ UINT64 Delay;\r
\r
///\r
/// PXE_VOID Block(UINT64 unq_id, UINT32 enable);\r
///\r
/// This field cannot be set to zero.\r
///\r
- UINT64 Block;\r
+ UINT64 Block;\r
\r
///\r
/// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);\r
/// This field can be set to zero if virtual and physical addresses\r
/// are equal.\r
///\r
- UINT64 Virt2Phys;\r
+ UINT64 Virt2Phys;\r
///\r
/// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,\r
/// UINT64 buf_addr);\r
///\r
/// This field can not be set to zero.\r
///\r
- UINT64 Mem_IO;\r
+ UINT64 Mem_IO;\r
///\r
/// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
/// UINT32 Direction, UINT64 mapped_addr);\r
///\r
/// This field can be set to zero if there is no mapping service available.\r
///\r
- UINT64 Map_Mem;\r
+ UINT64 Map_Mem;\r
\r
///\r
/// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
///\r
/// This field can be set to zero if there is no unmapping service available.\r
///\r
- UINT64 UnMap_Mem;\r
+ UINT64 UnMap_Mem;\r
\r
///\r
/// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,\r
///\r
/// This field can be set to zero if there is no service available.\r
///\r
- UINT64 Sync_Mem;\r
+ UINT64 Sync_Mem;\r
\r
///\r
/// protocol driver can provide anything for this Unique_ID, UNDI remembers\r
/// the ifnum and gives it back as a parameter to all the call-back routines\r
/// when calling for that interface!\r
///\r
- UINT64 Unique_ID;\r
+ UINT64 Unique_ID;\r
} PXE_CPB_START_31;\r
\r
-#define TO_AND_FROM_DEVICE 0\r
-#define FROM_DEVICE 1\r
-#define TO_DEVICE 2\r
+#define TO_AND_FROM_DEVICE 0\r
+#define FROM_DEVICE 1\r
+#define TO_DEVICE 2\r
\r
-#define PXE_DELAY_MILLISECOND 1000\r
-#define PXE_DELAY_SECOND 1000000\r
-#define PXE_IO_READ 0\r
-#define PXE_IO_WRITE 1\r
-#define PXE_MEM_READ 2\r
-#define PXE_MEM_WRITE 4\r
+#define PXE_DELAY_MILLISECOND 1000\r
+#define PXE_DELAY_SECOND 1000000\r
+#define PXE_IO_READ 0\r
+#define PXE_IO_WRITE 1\r
+#define PXE_MEM_READ 2\r
+#define PXE_MEM_WRITE 4\r
\r
typedef struct s_pxe_db_get_init_info {\r
///\r
/// If MemoryRequired is zero, the UNDI does not need and will not\r
/// use system memory to receive and transmit packets.\r
///\r
- PXE_UINT32 MemoryRequired;\r
+ PXE_UINT32 MemoryRequired;\r
\r
///\r
/// Maximum frame data length for Tx/Rx excluding the media header.\r
///\r
- PXE_UINT32 FrameDataLen;\r
+ PXE_UINT32 FrameDataLen;\r
\r
///\r
/// Supported link speeds are in units of mega bits. Common ethernet\r
/// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero\r
/// filled.\r
///\r
- PXE_UINT32 LinkSpeeds[4];\r
+ PXE_UINT32 LinkSpeeds[4];\r
\r
///\r
/// Number of non-volatile storage items.\r
///\r
- PXE_UINT32 NvCount;\r
+ PXE_UINT32 NvCount;\r
\r
///\r
/// Width of non-volatile storage item in bytes. 0, 1, 2 or 4\r
///\r
- PXE_UINT16 NvWidth;\r
+ PXE_UINT16 NvWidth;\r
\r
///\r
/// Media header length. This is the typical media header length for\r
/// this UNDI. This information is needed when allocating receive\r
/// and transmit buffers.\r
///\r
- PXE_UINT16 MediaHeaderLen;\r
+ PXE_UINT16 MediaHeaderLen;\r
\r
///\r
/// Number of bytes in the NIC hardware (MAC) address.\r
///\r
- PXE_UINT16 HWaddrLen;\r
+ PXE_UINT16 HWaddrLen;\r
\r
///\r
/// Maximum number of multicast MAC addresses in the multicast\r
/// MAC address filter list.\r
///\r
- PXE_UINT16 MCastFilterCnt;\r
+ PXE_UINT16 MCastFilterCnt;\r
\r
///\r
/// Default number and size of transmit and receive buffers that will\r
/// command. If MemoryRequired is zero, this allocation will come out of\r
/// memory on the NIC.\r
///\r
- PXE_UINT16 TxBufCnt;\r
- PXE_UINT16 TxBufSize;\r
- PXE_UINT16 RxBufCnt;\r
- PXE_UINT16 RxBufSize;\r
+ PXE_UINT16 TxBufCnt;\r
+ PXE_UINT16 TxBufSize;\r
+ PXE_UINT16 RxBufCnt;\r
+ PXE_UINT16 RxBufSize;\r
\r
///\r
/// Hardware interface types defined in the Assigned Numbers RFC\r
/// and used in DHCP and ARP packets.\r
/// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.\r
///\r
- PXE_UINT8 IFtype;\r
+ PXE_UINT8 IFtype;\r
\r
///\r
/// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.\r
///\r
- PXE_UINT8 SupportedDuplexModes;\r
+ PXE_UINT8 SupportedDuplexModes;\r
\r
///\r
/// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.\r
///\r
- PXE_UINT8 SupportedLoopBackModes;\r
+ PXE_UINT8 SupportedLoopBackModes;\r
} PXE_DB_GET_INIT_INFO;\r
\r
-#define PXE_MAX_TXRX_UNIT_ETHER 1500\r
+#define PXE_MAX_TXRX_UNIT_ETHER 1500\r
\r
-#define PXE_HWADDR_LEN_ETHER 0x0006\r
-#define PXE_MAC_HEADER_LEN_ETHER 0x000E\r
+#define PXE_HWADDR_LEN_ETHER 0x0006\r
+#define PXE_MAC_HEADER_LEN_ETHER 0x000E\r
\r
#define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1\r
#define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2\r
\r
-#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r
-#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r
+#define PXE_LOOPBACK_INTERNAL_SUPPORTED 1\r
+#define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2\r
\r
typedef struct s_pxe_pci_config_info {\r
///\r
/// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
/// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.\r
///\r
- UINT32 BusType;\r
+ UINT32 BusType;\r
\r
///\r
/// This identifies the PCI network device that this UNDI interface.\r
/// is bound to.\r
///\r
- UINT16 Bus;\r
- UINT8 Device;\r
- UINT8 Function;\r
+ UINT16 Bus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
\r
///\r
/// This is a copy of the PCI configuration space for this\r
/// network device.\r
///\r
union {\r
- UINT8 Byte[256];\r
- UINT16 Word[128];\r
- UINT32 Dword[64];\r
+ UINT8 Byte[256];\r
+ UINT16 Word[128];\r
+ UINT32 Dword[64];\r
} Config;\r
} PXE_PCI_CONFIG_INFO;\r
\r
/// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.\r
/// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.\r
///\r
- PXE_UINT32 BusType;\r
+ PXE_UINT32 BusType;\r
\r
///\r
/// This identifies the PCC network device that this UNDI interface\r
/// is bound to.\r
///\r
- PXE_UINT16 Bus;\r
- PXE_UINT8 Device;\r
- PXE_UINT8 Function;\r
+ PXE_UINT16 Bus;\r
+ PXE_UINT8 Device;\r
+ PXE_UINT8 Function;\r
\r
///\r
/// This is a copy of the PCC configuration space for this\r
/// network device.\r
///\r
union {\r
- PXE_UINT8 Byte[256];\r
- PXE_UINT16 Word[128];\r
- PXE_UINT32 Dword[64];\r
+ PXE_UINT8 Byte[256];\r
+ PXE_UINT16 Word[128];\r
+ PXE_UINT32 Dword[64];\r
} Config;\r
} PXE_PCC_CONFIG_INFO;\r
\r
typedef union u_pxe_db_get_config_info {\r
- PXE_PCI_CONFIG_INFO pci;\r
- PXE_PCC_CONFIG_INFO pcc;\r
+ PXE_PCI_CONFIG_INFO pci;\r
+ PXE_PCC_CONFIG_INFO pcc;\r
} PXE_DB_GET_CONFIG_INFO;\r
\r
typedef struct s_pxe_cpb_initialize {\r
/// be in contiguous physical memory and cannot be swapped out. The UNDI\r
/// will be using this for transmit and receive buffering.\r
///\r
- PXE_UINT64 MemoryAddr;\r
+ PXE_UINT64 MemoryAddr;\r
\r
///\r
/// MemoryLength must be greater than or equal to MemoryRequired\r
/// returned by the Get Init Info command.\r
///\r
- PXE_UINT32 MemoryLength;\r
+ PXE_UINT32 MemoryLength;\r
\r
///\r
/// Desired link speed in Mbit/sec. Common ethernet values are 10, 100\r
/// and 1000. Setting a value of zero will auto-detect and/or use the\r
/// default link speed (operation depends on UNDI/NIC functionality).\r
///\r
- PXE_UINT32 LinkSpeed;\r
+ PXE_UINT32 LinkSpeed;\r
\r
///\r
/// Suggested number and size of receive and transmit buffers to\r
/// If these fields are set to zero, the UNDI will allocate buffer\r
/// counts and sizes as it sees fit.\r
///\r
- PXE_UINT16 TxBufCnt;\r
- PXE_UINT16 TxBufSize;\r
- PXE_UINT16 RxBufCnt;\r
- PXE_UINT16 RxBufSize;\r
+ PXE_UINT16 TxBufCnt;\r
+ PXE_UINT16 TxBufSize;\r
+ PXE_UINT16 RxBufCnt;\r
+ PXE_UINT16 RxBufSize;\r
\r
///\r
/// The following configuration parameters are optional and must be zero\r
/// to use the default values.\r
///\r
- PXE_UINT8 DuplexMode;\r
+ PXE_UINT8 DuplexMode;\r
\r
- PXE_UINT8 LoopBackMode;\r
+ PXE_UINT8 LoopBackMode;\r
} PXE_CPB_INITIALIZE;\r
\r
-#define PXE_DUPLEX_DEFAULT 0x00\r
-#define PXE_FORCE_FULL_DUPLEX 0x01\r
-#define PXE_ENABLE_FULL_DUPLEX 0x02\r
-#define PXE_FORCE_HALF_DUPLEX 0x04\r
-#define PXE_DISABLE_FULL_DUPLEX 0x08\r
+#define PXE_DUPLEX_DEFAULT 0x00\r
+#define PXE_FORCE_FULL_DUPLEX 0x01\r
+#define PXE_ENABLE_FULL_DUPLEX 0x02\r
+#define PXE_FORCE_HALF_DUPLEX 0x04\r
+#define PXE_DISABLE_FULL_DUPLEX 0x08\r
\r
-#define LOOPBACK_NORMAL 0\r
-#define LOOPBACK_INTERNAL 1\r
-#define LOOPBACK_EXTERNAL 2\r
+#define LOOPBACK_NORMAL 0\r
+#define LOOPBACK_INTERNAL 1\r
+#define LOOPBACK_EXTERNAL 2\r
\r
typedef struct s_pxe_db_initialize {\r
///\r
/// Memory used by the UNDI and network device is allocated from the\r
/// lowest memory buffer address.\r
///\r
- PXE_UINT32 MemoryUsed;\r
+ PXE_UINT32 MemoryUsed;\r
\r
///\r
/// Actual number and size of receive and transmit buffers that were\r
/// allocated.\r
///\r
- PXE_UINT16 TxBufCnt;\r
- PXE_UINT16 TxBufSize;\r
- PXE_UINT16 RxBufCnt;\r
- PXE_UINT16 RxBufSize;\r
+ PXE_UINT16 TxBufCnt;\r
+ PXE_UINT16 TxBufSize;\r
+ PXE_UINT16 RxBufCnt;\r
+ PXE_UINT16 RxBufSize;\r
} PXE_DB_INITIALIZE;\r
\r
typedef struct s_pxe_cpb_receive_filters {\r
/// List of multicast MAC addresses. This list, if present, will\r
/// replace the existing multicast MAC address filter list.\r
///\r
- PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
+ PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
} PXE_CPB_RECEIVE_FILTERS;\r
\r
typedef struct s_pxe_db_receive_filters {\r
///\r
/// Filtered multicast MAC address list.\r
///\r
- PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
+ PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];\r
} PXE_DB_RECEIVE_FILTERS;\r
\r
typedef struct s_pxe_cpb_station_address {\r
/// If supplied and supported, the current station MAC address\r
/// will be changed.\r
///\r
- PXE_MAC_ADDR StationAddr;\r
+ PXE_MAC_ADDR StationAddr;\r
} PXE_CPB_STATION_ADDRESS;\r
\r
typedef struct s_pxe_dpb_station_address {\r
///\r
/// Current station MAC address.\r
///\r
- PXE_MAC_ADDR StationAddr;\r
+ PXE_MAC_ADDR StationAddr;\r
\r
///\r
/// Station broadcast MAC address.\r
///\r
- PXE_MAC_ADDR BroadcastAddr;\r
+ PXE_MAC_ADDR BroadcastAddr;\r
\r
///\r
/// Permanent station MAC address.\r
///\r
- PXE_MAC_ADDR PermanentAddr;\r
+ PXE_MAC_ADDR PermanentAddr;\r
} PXE_DB_STATION_ADDRESS;\r
\r
typedef struct s_pxe_db_statistics {\r
/// If bit 0x21 is set, Data[0x21] is collected.\r
/// Etc.\r
///\r
- PXE_UINT64 Supported;\r
+ PXE_UINT64 Supported;\r
\r
///\r
/// Statistic data.\r
///\r
- PXE_UINT64 Data[64];\r
+ PXE_UINT64 Data[64];\r
} PXE_DB_STATISTICS;\r
\r
///\r
///\r
/// Number of valid frames received and copied into receive buffers.\r
///\r
-#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r
+#define PXE_STATISTICS_RX_GOOD_FRAMES 0x01\r
\r
///\r
/// Number of frames below the minimum length for the media.\r
/// Number of frames longer than the maxminum length for the\r
/// media. This would be >1500 for ethernet.\r
///\r
-#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r
+#define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03\r
\r
///\r
/// Valid frames that were dropped because receive buffers were full.\r
/// Total number of bytes received. Includes frames with errors\r
/// and dropped frames.\r
///\r
-#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r
+#define PXE_STATISTICS_RX_TOTAL_BYTES 0x09\r
\r
///\r
/// Transmit statistics.\r
///\r
/// Number of collisions detection on this subnet.\r
///\r
-#define PXE_STATISTICS_COLLISIONS 0x14\r
+#define PXE_STATISTICS_COLLISIONS 0x14\r
\r
///\r
/// Number of frames destined for unsupported protocol.\r
///\r
-#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r
+#define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15\r
\r
///\r
/// Number of valid frames received that were duplicated.\r
///\r
-#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16\r
+#define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16\r
\r
///\r
/// Number of encrypted frames received that failed to decrypt.\r
///\r
-#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17\r
+#define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17\r
\r
///\r
/// Number of frames that failed to transmit after exceeding the retry limit.\r
///\r
-#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18\r
+#define PXE_STATISTICS_TX_ERROR_FRAMES 0x18\r
\r
///\r
/// Number of frames transmitted successfully after more than one attempt.\r
///\r
-#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19\r
+#define PXE_STATISTICS_TX_RETRY_FRAMES 0x19\r
\r
typedef struct s_pxe_cpb_mcast_ip_to_mac {\r
///\r
/// Multicast IP address to be converted to multicast MAC address.\r
///\r
- PXE_IP_ADDR IP;\r
+ PXE_IP_ADDR IP;\r
} PXE_CPB_MCAST_IP_TO_MAC;\r
\r
typedef struct s_pxe_db_mcast_ip_to_mac {\r
///\r
/// Multicast MAC address.\r
///\r
- PXE_MAC_ADDR MAC;\r
+ PXE_MAC_ADDR MAC;\r
} PXE_DB_MCAST_IP_TO_MAC;\r
\r
typedef struct s_pxe_cpb_nvdata_sparse {\r
///\r
/// Non-volatile storage address to be changed.\r
///\r
- PXE_UINT32 Addr;\r
+ PXE_UINT32 Addr;\r
\r
///\r
/// Data item to write into above storage address.\r
///\r
union {\r
- PXE_UINT8 Byte;\r
- PXE_UINT16 Word;\r
- PXE_UINT32 Dword;\r
+ PXE_UINT8 Byte;\r
+ PXE_UINT16 Word;\r
+ PXE_UINT32 Dword;\r
} Data;\r
} Item[MAX_EEPROM_LEN];\r
} PXE_CPB_NVDATA_SPARSE;\r
///\r
/// Array of byte-wide data items.\r
///\r
- PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
+ PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
\r
///\r
/// Array of word-wide data items.\r
///\r
- PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
+ PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
\r
///\r
/// Array of dword-wide data items.\r
///\r
- PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
+ PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
} PXE_CPB_NVDATA_BULK;\r
\r
typedef struct s_pxe_db_nvdata {\r
///\r
/// Array of byte-wide data items.\r
///\r
- PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
+ PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];\r
\r
///\r
/// Array of word-wide data items.\r
///\r
- PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
+ PXE_UINT16 Word[MAX_EEPROM_LEN << 1];\r
\r
///\r
/// Array of dword-wide data items.\r
///\r
- PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
+ PXE_UINT32 Dword[MAX_EEPROM_LEN];\r
} Data;\r
} PXE_DB_NVDATA;\r
\r
/// Length of next receive frame (header + data). If this is zero,\r
/// there is no next receive frame available.\r
///\r
- PXE_UINT32 RxFrameLen;\r
+ PXE_UINT32 RxFrameLen;\r
\r
///\r
/// Reserved, set to zero.\r
///\r
- PXE_UINT32 reserved;\r
+ PXE_UINT32 reserved;\r
\r
///\r
/// Addresses of transmitted buffers that need to be recycled.\r
///\r
- PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r
+ PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];\r
} PXE_DB_GET_STATUS;\r
\r
typedef struct s_pxe_cpb_fill_header {\r
/// Source and destination MAC addresses. These will be copied into\r
/// the media header without doing byte swapping.\r
///\r
- PXE_MAC_ADDR SrcAddr;\r
- PXE_MAC_ADDR DestAddr;\r
+ PXE_MAC_ADDR SrcAddr;\r
+ PXE_MAC_ADDR DestAddr;\r
\r
///\r
/// Address of first byte of media header. The first byte of packet data\r
/// follows the last byte of the media header.\r
///\r
- PXE_UINT64 MediaHeader;\r
+ PXE_UINT64 MediaHeader;\r
\r
///\r
/// Length of packet data in bytes (not including the media header).\r
///\r
- PXE_UINT32 PacketLen;\r
+ PXE_UINT32 PacketLen;\r
\r
///\r
/// Protocol type. This will be copied into the media header without\r
/// doing byte swapping. Protocol type numbers can be obtained from\r
/// the Assigned Numbers RFC 1700.\r
///\r
- PXE_UINT16 Protocol;\r
+ PXE_UINT16 Protocol;\r
\r
///\r
/// Length of the media header in bytes.\r
///\r
- PXE_UINT16 MediaHeaderLen;\r
+ PXE_UINT16 MediaHeaderLen;\r
} PXE_CPB_FILL_HEADER;\r
\r
-#define PXE_PROTOCOL_ETHERNET_IP 0x0800\r
-#define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r
-#define MAX_XMIT_FRAGMENTS 16\r
+#define PXE_PROTOCOL_ETHERNET_IP 0x0800\r
+#define PXE_PROTOCOL_ETHERNET_ARP 0x0806\r
+#define MAX_XMIT_FRAGMENTS 16\r
\r
typedef struct s_pxe_cpb_fill_header_fragmented {\r
///\r
/// Source and destination MAC addresses. These will be copied into\r
/// the media header without doing byte swapping.\r
///\r
- PXE_MAC_ADDR SrcAddr;\r
- PXE_MAC_ADDR DestAddr;\r
+ PXE_MAC_ADDR SrcAddr;\r
+ PXE_MAC_ADDR DestAddr;\r
\r
///\r
/// Length of packet data in bytes (not including the media header).\r
///\r
- PXE_UINT32 PacketLen;\r
+ PXE_UINT32 PacketLen;\r
\r
///\r
/// Protocol type. This will be copied into the media header without\r
/// doing byte swapping. Protocol type numbers can be obtained from\r
/// the Assigned Numbers RFC 1700.\r
///\r
- PXE_MEDIA_PROTOCOL Protocol;\r
+ PXE_MEDIA_PROTOCOL Protocol;\r
\r
///\r
/// Length of the media header in bytes.\r
///\r
- PXE_UINT16 MediaHeaderLen;\r
+ PXE_UINT16 MediaHeaderLen;\r
\r
///\r
/// Number of packet fragment descriptors.\r
///\r
- PXE_UINT16 FragCnt;\r
+ PXE_UINT16 FragCnt;\r
\r
///\r
/// Reserved, must be set to zero.\r
///\r
- PXE_UINT16 reserved;\r
+ PXE_UINT16 reserved;\r
\r
///\r
/// Array of packet fragment descriptors. The first byte of the media\r
///\r
/// Address of this packet fragment.\r
///\r
- PXE_UINT64 FragAddr;\r
+ PXE_UINT64 FragAddr;\r
\r
///\r
/// Length of this packet fragment.\r
///\r
- PXE_UINT32 FragLen;\r
+ PXE_UINT32 FragLen;\r
\r
///\r
/// Reserved, must be set to zero.\r
///\r
- PXE_UINT32 reserved;\r
+ PXE_UINT32 reserved;\r
} FragDesc[MAX_XMIT_FRAGMENTS];\r
-}\r
-PXE_CPB_FILL_HEADER_FRAGMENTED;\r
+} PXE_CPB_FILL_HEADER_FRAGMENTED;\r
\r
typedef struct s_pxe_cpb_transmit {\r
///\r
/// Address of first byte of frame buffer. This is also the first byte\r
/// of the media header.\r
///\r
- PXE_UINT64 FrameAddr;\r
+ PXE_UINT64 FrameAddr;\r
\r
///\r
/// Length of the data portion of the frame buffer in bytes. Do not\r
/// include the length of the media header.\r
///\r
- PXE_UINT32 DataLen;\r
+ PXE_UINT32 DataLen;\r
\r
///\r
/// Length of the media header in bytes.\r
///\r
- PXE_UINT16 MediaheaderLen;\r
+ PXE_UINT16 MediaheaderLen;\r
\r
///\r
/// Reserved, must be zero.\r
///\r
- PXE_UINT16 reserved;\r
+ PXE_UINT16 reserved;\r
} PXE_CPB_TRANSMIT;\r
\r
typedef struct s_pxe_cpb_transmit_fragments {\r
///\r
/// Length of packet data in bytes (not including the media header).\r
///\r
- PXE_UINT32 FrameLen;\r
+ PXE_UINT32 FrameLen;\r
\r
///\r
/// Length of the media header in bytes.\r
///\r
- PXE_UINT16 MediaheaderLen;\r
+ PXE_UINT16 MediaheaderLen;\r
\r
///\r
/// Number of packet fragment descriptors.\r
///\r
- PXE_UINT16 FragCnt;\r
+ PXE_UINT16 FragCnt;\r
\r
///\r
/// Array of frame fragment descriptors. The first byte of the first\r
///\r
/// Address of this frame fragment.\r
///\r
- PXE_UINT64 FragAddr;\r
+ PXE_UINT64 FragAddr;\r
\r
///\r
/// Length of this frame fragment.\r
///\r
- PXE_UINT32 FragLen;\r
+ PXE_UINT32 FragLen;\r
\r
///\r
/// Reserved, must be set to zero.\r
///\r
- PXE_UINT32 reserved;\r
+ PXE_UINT32 reserved;\r
} FragDesc[MAX_XMIT_FRAGMENTS];\r
-}\r
-PXE_CPB_TRANSMIT_FRAGMENTS;\r
+} PXE_CPB_TRANSMIT_FRAGMENTS;\r
\r
typedef struct s_pxe_cpb_receive {\r
///\r
/// Address of first byte of receive buffer. This is also the first byte\r
/// of the frame header.\r
///\r
- PXE_UINT64 BufferAddr;\r
+ PXE_UINT64 BufferAddr;\r
\r
///\r
/// Length of receive buffer. This must be large enough to hold the\r
/// received frame (media header + data). If the length of smaller than\r
/// the received frame, data will be lost.\r
///\r
- PXE_UINT32 BufferLen;\r
+ PXE_UINT32 BufferLen;\r
\r
///\r
/// Reserved, must be set to zero.\r
///\r
- PXE_UINT32 reserved;\r
+ PXE_UINT32 reserved;\r
} PXE_CPB_RECEIVE;\r
\r
typedef struct s_pxe_db_receive {\r
///\r
/// Source and destination MAC addresses from media header.\r
///\r
- PXE_MAC_ADDR SrcAddr;\r
- PXE_MAC_ADDR DestAddr;\r
+ PXE_MAC_ADDR SrcAddr;\r
+ PXE_MAC_ADDR DestAddr;\r
\r
///\r
/// Length of received frame. May be larger than receive buffer size.\r
/// The receive buffer will not be overwritten. This is how to tell\r
/// if data was lost because the receive buffer was too small.\r
///\r
- PXE_UINT32 FrameLen;\r
+ PXE_UINT32 FrameLen;\r
\r
///\r
/// Protocol type from media header.\r
///\r
- PXE_MEDIA_PROTOCOL Protocol;\r
+ PXE_MEDIA_PROTOCOL Protocol;\r
\r
///\r
/// Length of media header in received frame.\r
///\r
- PXE_UINT16 MediaHeaderLen;\r
+ PXE_UINT16 MediaHeaderLen;\r
\r
///\r
/// Type of receive frame.\r
///\r
- PXE_FRAME_TYPE Type;\r
+ PXE_FRAME_TYPE Type;\r
\r
///\r
/// Reserved, must be zero.\r
///\r
- PXE_UINT8 reserved[7];\r
-\r
+ PXE_UINT8 reserved[7];\r
} PXE_DB_RECEIVE;\r
\r
#pragma pack()\r
//\r
// Memory cacheability attributes\r
//\r
-#define EFI_MEMORY_UC 0x0000000000000001ULL\r
-#define EFI_MEMORY_WC 0x0000000000000002ULL\r
-#define EFI_MEMORY_WT 0x0000000000000004ULL\r
-#define EFI_MEMORY_WB 0x0000000000000008ULL\r
-#define EFI_MEMORY_UCE 0x0000000000000010ULL\r
+#define EFI_MEMORY_UC 0x0000000000000001ULL\r
+#define EFI_MEMORY_WC 0x0000000000000002ULL\r
+#define EFI_MEMORY_WT 0x0000000000000004ULL\r
+#define EFI_MEMORY_WB 0x0000000000000008ULL\r
+#define EFI_MEMORY_UCE 0x0000000000000010ULL\r
//\r
// Physical memory protection attributes\r
//\r
// Note: UEFI spec 2.5 and following: use EFI_MEMORY_RO as write-protected physical memory\r
// protection attribute. Also, EFI_MEMORY_WP means cacheability attribute.\r
//\r
-#define EFI_MEMORY_WP 0x0000000000001000ULL\r
-#define EFI_MEMORY_RP 0x0000000000002000ULL\r
-#define EFI_MEMORY_XP 0x0000000000004000ULL\r
-#define EFI_MEMORY_RO 0x0000000000020000ULL\r
+#define EFI_MEMORY_WP 0x0000000000001000ULL\r
+#define EFI_MEMORY_RP 0x0000000000002000ULL\r
+#define EFI_MEMORY_XP 0x0000000000004000ULL\r
+#define EFI_MEMORY_RO 0x0000000000020000ULL\r
//\r
// Physical memory persistence attribute.\r
// The memory region supports byte-addressable non-volatility.\r
//\r
-#define EFI_MEMORY_NV 0x0000000000008000ULL\r
+#define EFI_MEMORY_NV 0x0000000000008000ULL\r
//\r
// The memory region provides higher reliability relative to other memory in the system.\r
// If all memory has the same reliability, then this bit is not used.\r
//\r
-#define EFI_MEMORY_MORE_RELIABLE 0x0000000000010000ULL\r
+#define EFI_MEMORY_MORE_RELIABLE 0x0000000000010000ULL\r
\r
//\r
// Note: UEFI spec 2.8 and following:\r
// The SPM attribute serves as a hint to the OS to avoid allocating this\r
// memory for core OS data or code that can not be relocated.\r
//\r
-#define EFI_MEMORY_SP 0x0000000000040000ULL\r
+#define EFI_MEMORY_SP 0x0000000000040000ULL\r
//\r
// If this flag is set, the memory region is capable of being\r
// protected with the CPU's memory cryptographic\r
// cryptographic capabilities or the CPU does not support CPU\r
// memory cryptographic capabilities.\r
//\r
-#define EFI_MEMORY_CPU_CRYPTO 0x0000000000080000ULL\r
+#define EFI_MEMORY_CPU_CRYPTO 0x0000000000080000ULL\r
\r
//\r
// Runtime memory attribute\r
//\r
-#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL\r
+#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL\r
\r
//\r
// Attributes bitmasks, grouped by type\r
//\r
-#define EFI_CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)\r
-#define EFI_MEMORY_ACCESS_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)\r
-#define EFI_MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_ACCESS_MASK | EFI_MEMORY_SP | EFI_MEMORY_CPU_CRYPTO)\r
+#define EFI_CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)\r
+#define EFI_MEMORY_ACCESS_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)\r
+#define EFI_MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_ACCESS_MASK | EFI_MEMORY_SP | EFI_MEMORY_CPU_CRYPTO)\r
\r
///\r
/// Memory descriptor version number.\r
///\r
-#define EFI_MEMORY_DESCRIPTOR_VERSION 1\r
+#define EFI_MEMORY_DESCRIPTOR_VERSION 1\r
\r
///\r
/// Definition of an EFI memory descriptor.\r
/// Type EFI_MEMORY_TYPE is defined in the\r
/// AllocatePages() function description.\r
///\r
- UINT32 Type;\r
+ UINT32 Type;\r
///\r
/// Physical address of the first byte in the memory region. PhysicalStart must be\r
/// aligned on a 4 KiB boundary, and must not be above 0xfffffffffffff000. Type\r
/// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function description\r
///\r
- EFI_PHYSICAL_ADDRESS PhysicalStart;\r
+ EFI_PHYSICAL_ADDRESS PhysicalStart;\r
///\r
/// Virtual address of the first byte in the memory region.\r
/// VirtualStart must be aligned on a 4 KiB boundary,\r
/// and must not be above 0xfffffffffffff000.\r
///\r
- EFI_VIRTUAL_ADDRESS VirtualStart;\r
+ EFI_VIRTUAL_ADDRESS VirtualStart;\r
///\r
/// NumberOfPagesNumber of 4 KiB pages in the memory region.\r
/// NumberOfPages must not be 0, and must not be any value\r
/// that would represent a memory page with a start address,\r
/// either physical or virtual, above 0xfffffffffffff000.\r
///\r
- UINT64 NumberOfPages;\r
+ UINT64 NumberOfPages;\r
///\r
/// Attributes of the memory region that describe the bit mask of capabilities\r
/// for that memory region, and not necessarily the current settings for that\r
/// memory region.\r
///\r
- UINT64 Attribute;\r
+ UINT64 Attribute;\r
} EFI_MEMORY_DESCRIPTOR;\r
\r
/**\r
IN EFI_HANDLE ChildHandle OPTIONAL\r
);\r
\r
-\r
-\r
//\r
// ConvertPointer DebugDisposition type.\r
//\r
-#define EFI_OPTIONAL_PTR 0x00000001\r
+#define EFI_OPTIONAL_PTR 0x00000001\r
\r
/**\r
Determines the new virtual address that is to be used on subsequent memory accesses.\r
IN OUT VOID **Address\r
);\r
\r
-\r
//\r
// These types can be ORed together as needed - for example,\r
// EVT_TIMER might be Ored with EVT_NOTIFY_WAIT or\r
// EVT_NOTIFY_SIGNAL.\r
//\r
-#define EVT_TIMER 0x80000000\r
-#define EVT_RUNTIME 0x40000000\r
-#define EVT_NOTIFY_WAIT 0x00000100\r
-#define EVT_NOTIFY_SIGNAL 0x00000200\r
+#define EVT_TIMER 0x80000000\r
+#define EVT_RUNTIME 0x40000000\r
+#define EVT_NOTIFY_WAIT 0x00000100\r
+#define EVT_NOTIFY_SIGNAL 0x00000200\r
\r
-#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201\r
-#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202\r
+#define EVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201\r
+#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202\r
\r
//\r
// The event's NotifyContext pointer points to a runtime memory\r
// address.\r
// The event is deprecated in UEFI2.0 and later specifications.\r
//\r
-#define EVT_RUNTIME_CONTEXT 0x20000000\r
-\r
+#define EVT_RUNTIME_CONTEXT 0x20000000\r
\r
/**\r
Invoke a notification event\r
IN EFI_EVENT Event\r
);\r
\r
-\r
//\r
// Task priority level\r
//\r
-#define TPL_APPLICATION 4\r
-#define TPL_CALLBACK 8\r
-#define TPL_NOTIFY 16\r
-#define TPL_HIGH_LEVEL 31\r
-\r
+#define TPL_APPLICATION 4\r
+#define TPL_CALLBACK 8\r
+#define TPL_NOTIFY 16\r
+#define TPL_HIGH_LEVEL 31\r
\r
/**\r
Raises a task's priority level and returns its previous level.\r
IN VOID *Data\r
);\r
\r
-\r
///\r
/// This provides the capabilities of the\r
/// real time clock device as exposed through the EFI interfaces.\r
/// value would be 1 Hz, or 1, to indicate that the device only reports\r
/// the time to the resolution of 1 second.\r
///\r
- UINT32 Resolution;\r
+ UINT32 Resolution;\r
///\r
/// Provides the timekeeping accuracy of the real-time clock in an\r
/// error rate of 1E-6 parts per million. For a clock with an accuracy\r
/// of 50 parts per million, the value in this field would be\r
/// 50,000,000.\r
///\r
- UINT32 Accuracy;\r
+ UINT32 Accuracy;\r
///\r
/// A TRUE indicates that a time set operation clears the device's\r
/// time below the Resolution reporting level. A FALSE\r
/// device is not cleared when the time is set. Normal PC-AT CMOS\r
/// RTC devices set this value to FALSE.\r
///\r
- BOOLEAN SetsToZero;\r
+ BOOLEAN SetsToZero;\r
} EFI_TIME_CAPABILITIES;\r
\r
/**\r
OUT VOID **Interface\r
);\r
\r
-#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001\r
-#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002\r
-#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004\r
-#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008\r
-#define EFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010\r
-#define EFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020\r
+#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL 0x00000001\r
+#define EFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002\r
+#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004\r
+#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008\r
+#define EFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010\r
+#define EFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020\r
\r
/**\r
Queries a handle to determine if it supports a specified protocol. If the protocol is supported by the\r
IN UINT32 Attributes\r
);\r
\r
-\r
/**\r
Closes a protocol on a handle that was opened using OpenProtocol().\r
\r
/// EFI Oprn Protocol Information Entry\r
///\r
typedef struct {\r
- EFI_HANDLE AgentHandle;\r
- EFI_HANDLE ControllerHandle;\r
- UINT32 Attributes;\r
- UINT32 OpenCount;\r
+ EFI_HANDLE AgentHandle;\r
+ EFI_HANDLE ControllerHandle;\r
+ UINT32 Attributes;\r
+ UINT32 OpenCount;\r
} EFI_OPEN_PROTOCOL_INFORMATION_ENTRY;\r
\r
/**\r
///\r
/// Length in bytes of the data pointed to by DataBlock/ContinuationPointer.\r
///\r
- UINT64 Length;\r
+ UINT64 Length;\r
union {\r
///\r
/// Physical address of the data block. This member of the union is\r
/// used if Length is not equal to zero.\r
///\r
- EFI_PHYSICAL_ADDRESS DataBlock;\r
+ EFI_PHYSICAL_ADDRESS DataBlock;\r
///\r
/// Physical address of another block of\r
/// EFI_CAPSULE_BLOCK_DESCRIPTOR structures. This\r
/// member of the union is used if Length is equal to zero. If\r
/// ContinuationPointer is zero this entry represents the end of the list.\r
///\r
- EFI_PHYSICAL_ADDRESS ContinuationPointer;\r
+ EFI_PHYSICAL_ADDRESS ContinuationPointer;\r
} Union;\r
} EFI_CAPSULE_BLOCK_DESCRIPTOR;\r
\r
///\r
/// A GUID that defines the contents of a capsule.\r
///\r
- EFI_GUID CapsuleGuid;\r
+ EFI_GUID CapsuleGuid;\r
///\r
/// The size of the capsule header. This may be larger than the size of\r
/// the EFI_CAPSULE_HEADER since CapsuleGuid may imply\r
/// extended header entries\r
///\r
- UINT32 HeaderSize;\r
+ UINT32 HeaderSize;\r
///\r
/// Bit-mapped list describing the capsule attributes. The Flag values\r
/// of 0x0000 - 0xFFFF are defined by CapsuleGuid. Flag values\r
/// of 0x10000 - 0xFFFFFFFF are defined by this specification\r
///\r
- UINT32 Flags;\r
+ UINT32 Flags;\r
///\r
/// Size in bytes of the capsule.\r
///\r
- UINT32 CapsuleImageSize;\r
+ UINT32 CapsuleImageSize;\r
} EFI_CAPSULE_HEADER;\r
\r
///\r
///\r
/// the size of the array of capsules.\r
///\r
- UINT32 CapsuleArrayNumber;\r
+ UINT32 CapsuleArrayNumber;\r
///\r
/// Point to an array of capsules that contain the same CapsuleGuid value.\r
///\r
- VOID* CapsulePtr[1];\r
+ VOID *CapsulePtr[1];\r
} EFI_CAPSULE_TABLE;\r
\r
-#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000\r
-#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000\r
-#define CAPSULE_FLAGS_INITIATE_RESET 0x00040000\r
+#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000\r
+#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE 0x00020000\r
+#define CAPSULE_FLAGS_INITIATE_RESET 0x00040000\r
\r
/**\r
Passes capsules to the firmware with both virtual and physical mapping. Depending on the intended\r
///\r
/// The table header for the EFI Runtime Services Table.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
\r
//\r
// Time Services\r
//\r
- EFI_GET_TIME GetTime;\r
- EFI_SET_TIME SetTime;\r
- EFI_GET_WAKEUP_TIME GetWakeupTime;\r
- EFI_SET_WAKEUP_TIME SetWakeupTime;\r
+ EFI_GET_TIME GetTime;\r
+ EFI_SET_TIME SetTime;\r
+ EFI_GET_WAKEUP_TIME GetWakeupTime;\r
+ EFI_SET_WAKEUP_TIME SetWakeupTime;\r
\r
//\r
// Virtual Memory Services\r
//\r
- EFI_SET_VIRTUAL_ADDRESS_MAP SetVirtualAddressMap;\r
- EFI_CONVERT_POINTER ConvertPointer;\r
+ EFI_SET_VIRTUAL_ADDRESS_MAP SetVirtualAddressMap;\r
+ EFI_CONVERT_POINTER ConvertPointer;\r
\r
//\r
// Variable Services\r
//\r
- EFI_GET_VARIABLE GetVariable;\r
- EFI_GET_NEXT_VARIABLE_NAME GetNextVariableName;\r
- EFI_SET_VARIABLE SetVariable;\r
+ EFI_GET_VARIABLE GetVariable;\r
+ EFI_GET_NEXT_VARIABLE_NAME GetNextVariableName;\r
+ EFI_SET_VARIABLE SetVariable;\r
\r
//\r
// Miscellaneous Services\r
//\r
- EFI_GET_NEXT_HIGH_MONO_COUNT GetNextHighMonotonicCount;\r
- EFI_RESET_SYSTEM ResetSystem;\r
+ EFI_GET_NEXT_HIGH_MONO_COUNT GetNextHighMonotonicCount;\r
+ EFI_RESET_SYSTEM ResetSystem;\r
\r
//\r
// UEFI 2.0 Capsule Services\r
//\r
- EFI_UPDATE_CAPSULE UpdateCapsule;\r
- EFI_QUERY_CAPSULE_CAPABILITIES QueryCapsuleCapabilities;\r
+ EFI_UPDATE_CAPSULE UpdateCapsule;\r
+ EFI_QUERY_CAPSULE_CAPABILITIES QueryCapsuleCapabilities;\r
\r
//\r
// Miscellaneous UEFI 2.0 Service\r
//\r
- EFI_QUERY_VARIABLE_INFO QueryVariableInfo;\r
+ EFI_QUERY_VARIABLE_INFO QueryVariableInfo;\r
} EFI_RUNTIME_SERVICES;\r
\r
-\r
-#define EFI_BOOT_SERVICES_SIGNATURE SIGNATURE_64 ('B','O','O','T','S','E','R','V')\r
-#define EFI_BOOT_SERVICES_REVISION EFI_SPECIFICATION_VERSION\r
+#define EFI_BOOT_SERVICES_SIGNATURE SIGNATURE_64 ('B','O','O','T','S','E','R','V')\r
+#define EFI_BOOT_SERVICES_REVISION EFI_SPECIFICATION_VERSION\r
\r
///\r
/// EFI Boot Services Table.\r
///\r
/// The table header for the EFI Boot Services Table.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
\r
//\r
// Task Priority Services\r
//\r
- EFI_RAISE_TPL RaiseTPL;\r
- EFI_RESTORE_TPL RestoreTPL;\r
+ EFI_RAISE_TPL RaiseTPL;\r
+ EFI_RESTORE_TPL RestoreTPL;\r
\r
//\r
// Memory Services\r
//\r
- EFI_ALLOCATE_PAGES AllocatePages;\r
- EFI_FREE_PAGES FreePages;\r
- EFI_GET_MEMORY_MAP GetMemoryMap;\r
- EFI_ALLOCATE_POOL AllocatePool;\r
- EFI_FREE_POOL FreePool;\r
+ EFI_ALLOCATE_PAGES AllocatePages;\r
+ EFI_FREE_PAGES FreePages;\r
+ EFI_GET_MEMORY_MAP GetMemoryMap;\r
+ EFI_ALLOCATE_POOL AllocatePool;\r
+ EFI_FREE_POOL FreePool;\r
\r
//\r
// Event & Timer Services\r
//\r
- EFI_CREATE_EVENT CreateEvent;\r
- EFI_SET_TIMER SetTimer;\r
- EFI_WAIT_FOR_EVENT WaitForEvent;\r
- EFI_SIGNAL_EVENT SignalEvent;\r
- EFI_CLOSE_EVENT CloseEvent;\r
- EFI_CHECK_EVENT CheckEvent;\r
+ EFI_CREATE_EVENT CreateEvent;\r
+ EFI_SET_TIMER SetTimer;\r
+ EFI_WAIT_FOR_EVENT WaitForEvent;\r
+ EFI_SIGNAL_EVENT SignalEvent;\r
+ EFI_CLOSE_EVENT CloseEvent;\r
+ EFI_CHECK_EVENT CheckEvent;\r
\r
//\r
// Protocol Handler Services\r
//\r
- EFI_INSTALL_PROTOCOL_INTERFACE InstallProtocolInterface;\r
- EFI_REINSTALL_PROTOCOL_INTERFACE ReinstallProtocolInterface;\r
- EFI_UNINSTALL_PROTOCOL_INTERFACE UninstallProtocolInterface;\r
- EFI_HANDLE_PROTOCOL HandleProtocol;\r
- VOID *Reserved;\r
- EFI_REGISTER_PROTOCOL_NOTIFY RegisterProtocolNotify;\r
- EFI_LOCATE_HANDLE LocateHandle;\r
- EFI_LOCATE_DEVICE_PATH LocateDevicePath;\r
- EFI_INSTALL_CONFIGURATION_TABLE InstallConfigurationTable;\r
+ EFI_INSTALL_PROTOCOL_INTERFACE InstallProtocolInterface;\r
+ EFI_REINSTALL_PROTOCOL_INTERFACE ReinstallProtocolInterface;\r
+ EFI_UNINSTALL_PROTOCOL_INTERFACE UninstallProtocolInterface;\r
+ EFI_HANDLE_PROTOCOL HandleProtocol;\r
+ VOID *Reserved;\r
+ EFI_REGISTER_PROTOCOL_NOTIFY RegisterProtocolNotify;\r
+ EFI_LOCATE_HANDLE LocateHandle;\r
+ EFI_LOCATE_DEVICE_PATH LocateDevicePath;\r
+ EFI_INSTALL_CONFIGURATION_TABLE InstallConfigurationTable;\r
\r
//\r
// Image Services\r
//\r
- EFI_IMAGE_LOAD LoadImage;\r
- EFI_IMAGE_START StartImage;\r
- EFI_EXIT Exit;\r
- EFI_IMAGE_UNLOAD UnloadImage;\r
- EFI_EXIT_BOOT_SERVICES ExitBootServices;\r
+ EFI_IMAGE_LOAD LoadImage;\r
+ EFI_IMAGE_START StartImage;\r
+ EFI_EXIT Exit;\r
+ EFI_IMAGE_UNLOAD UnloadImage;\r
+ EFI_EXIT_BOOT_SERVICES ExitBootServices;\r
\r
//\r
// Miscellaneous Services\r
//\r
- EFI_GET_NEXT_MONOTONIC_COUNT GetNextMonotonicCount;\r
- EFI_STALL Stall;\r
- EFI_SET_WATCHDOG_TIMER SetWatchdogTimer;\r
+ EFI_GET_NEXT_MONOTONIC_COUNT GetNextMonotonicCount;\r
+ EFI_STALL Stall;\r
+ EFI_SET_WATCHDOG_TIMER SetWatchdogTimer;\r
\r
//\r
// DriverSupport Services\r
//\r
- EFI_CONNECT_CONTROLLER ConnectController;\r
- EFI_DISCONNECT_CONTROLLER DisconnectController;\r
+ EFI_CONNECT_CONTROLLER ConnectController;\r
+ EFI_DISCONNECT_CONTROLLER DisconnectController;\r
\r
//\r
// Open and Close Protocol Services\r
//\r
- EFI_OPEN_PROTOCOL OpenProtocol;\r
- EFI_CLOSE_PROTOCOL CloseProtocol;\r
- EFI_OPEN_PROTOCOL_INFORMATION OpenProtocolInformation;\r
+ EFI_OPEN_PROTOCOL OpenProtocol;\r
+ EFI_CLOSE_PROTOCOL CloseProtocol;\r
+ EFI_OPEN_PROTOCOL_INFORMATION OpenProtocolInformation;\r
\r
//\r
// Library Services\r
//\r
- EFI_PROTOCOLS_PER_HANDLE ProtocolsPerHandle;\r
- EFI_LOCATE_HANDLE_BUFFER LocateHandleBuffer;\r
- EFI_LOCATE_PROTOCOL LocateProtocol;\r
- EFI_INSTALL_MULTIPLE_PROTOCOL_INTERFACES InstallMultipleProtocolInterfaces;\r
- EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES UninstallMultipleProtocolInterfaces;\r
+ EFI_PROTOCOLS_PER_HANDLE ProtocolsPerHandle;\r
+ EFI_LOCATE_HANDLE_BUFFER LocateHandleBuffer;\r
+ EFI_LOCATE_PROTOCOL LocateProtocol;\r
+ EFI_INSTALL_MULTIPLE_PROTOCOL_INTERFACES InstallMultipleProtocolInterfaces;\r
+ EFI_UNINSTALL_MULTIPLE_PROTOCOL_INTERFACES UninstallMultipleProtocolInterfaces;\r
\r
//\r
// 32-bit CRC Services\r
//\r
- EFI_CALCULATE_CRC32 CalculateCrc32;\r
+ EFI_CALCULATE_CRC32 CalculateCrc32;\r
\r
//\r
// Miscellaneous Services\r
//\r
- EFI_COPY_MEM CopyMem;\r
- EFI_SET_MEM SetMem;\r
- EFI_CREATE_EVENT_EX CreateEventEx;\r
+ EFI_COPY_MEM CopyMem;\r
+ EFI_SET_MEM SetMem;\r
+ EFI_CREATE_EVENT_EX CreateEventEx;\r
} EFI_BOOT_SERVICES;\r
\r
///\r
///\r
/// The 128-bit GUID value that uniquely identifies the system configuration table.\r
///\r
- EFI_GUID VendorGuid;\r
+ EFI_GUID VendorGuid;\r
///\r
/// A pointer to the table associated with VendorGuid.\r
///\r
- VOID *VendorTable;\r
+ VOID *VendorTable;\r
} EFI_CONFIGURATION_TABLE;\r
\r
///\r
///\r
/// The table header for the EFI System Table.\r
///\r
- EFI_TABLE_HEADER Hdr;\r
+ EFI_TABLE_HEADER Hdr;\r
///\r
/// A pointer to a null terminated string that identifies the vendor\r
/// that produces the system firmware for the platform.\r
///\r
- CHAR16 *FirmwareVendor;\r
+ CHAR16 *FirmwareVendor;\r
///\r
/// A firmware vendor specific value that identifies the revision\r
/// of the system firmware for the platform.\r
///\r
- UINT32 FirmwareRevision;\r
+ UINT32 FirmwareRevision;\r
///\r
/// The handle for the active console input device. This handle must support\r
/// EFI_SIMPLE_TEXT_INPUT_PROTOCOL and EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL.\r
///\r
- EFI_HANDLE ConsoleInHandle;\r
+ EFI_HANDLE ConsoleInHandle;\r
///\r
/// A pointer to the EFI_SIMPLE_TEXT_INPUT_PROTOCOL interface that is\r
/// associated with ConsoleInHandle.\r
///\r
- EFI_SIMPLE_TEXT_INPUT_PROTOCOL *ConIn;\r
+ EFI_SIMPLE_TEXT_INPUT_PROTOCOL *ConIn;\r
///\r
/// The handle for the active console output device.\r
///\r
- EFI_HANDLE ConsoleOutHandle;\r
+ EFI_HANDLE ConsoleOutHandle;\r
///\r
/// A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface\r
/// that is associated with ConsoleOutHandle.\r
///\r
- EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *ConOut;\r
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *ConOut;\r
///\r
/// The handle for the active standard error console device.\r
/// This handle must support the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL.\r
///\r
- EFI_HANDLE StandardErrorHandle;\r
+ EFI_HANDLE StandardErrorHandle;\r
///\r
/// A pointer to the EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL interface\r
/// that is associated with StandardErrorHandle.\r
///\r
- EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *StdErr;\r
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *StdErr;\r
///\r
/// A pointer to the EFI Runtime Services Table.\r
///\r
- EFI_RUNTIME_SERVICES *RuntimeServices;\r
+ EFI_RUNTIME_SERVICES *RuntimeServices;\r
///\r
/// A pointer to the EFI Boot Services Table.\r
///\r
- EFI_BOOT_SERVICES *BootServices;\r
+ EFI_BOOT_SERVICES *BootServices;\r
///\r
/// The number of system configuration tables in the buffer ConfigurationTable.\r
///\r
- UINTN NumberOfTableEntries;\r
+ UINTN NumberOfTableEntries;\r
///\r
/// A pointer to the system configuration tables.\r
/// The number of entries in the table is NumberOfTableEntries.\r
///\r
- EFI_CONFIGURATION_TABLE *ConfigurationTable;\r
+ EFI_CONFIGURATION_TABLE *ConfigurationTable;\r
} EFI_SYSTEM_TABLE;\r
\r
/**\r
/// The attributes for this load option entry. All unused bits must be zero\r
/// and are reserved by the UEFI specification for future growth.\r
///\r
- UINT32 Attributes;\r
+ UINT32 Attributes;\r
///\r
/// Length in bytes of the FilePathList. OptionalData starts at offset\r
/// sizeof(UINT32) + sizeof(UINT16) + StrSize(Description) + FilePathListLength\r
/// of the EFI_LOAD_OPTION descriptor.\r
///\r
- UINT16 FilePathListLength;\r
+ UINT16 FilePathListLength;\r
///\r
/// The user readable description for the load option.\r
/// This field ends with a Null character.\r
//\r
// EFI Load Options Attributes\r
//\r
-#define LOAD_OPTION_ACTIVE 0x00000001\r
-#define LOAD_OPTION_FORCE_RECONNECT 0x00000002\r
-#define LOAD_OPTION_HIDDEN 0x00000008\r
-#define LOAD_OPTION_CATEGORY 0x00001F00\r
+#define LOAD_OPTION_ACTIVE 0x00000001\r
+#define LOAD_OPTION_FORCE_RECONNECT 0x00000002\r
+#define LOAD_OPTION_HIDDEN 0x00000008\r
+#define LOAD_OPTION_CATEGORY 0x00001F00\r
\r
-#define LOAD_OPTION_CATEGORY_BOOT 0x00000000\r
-#define LOAD_OPTION_CATEGORY_APP 0x00000100\r
+#define LOAD_OPTION_CATEGORY_BOOT 0x00000000\r
+#define LOAD_OPTION_CATEGORY_APP 0x00000100\r
\r
-#define EFI_BOOT_OPTION_SUPPORT_KEY 0x00000001\r
-#define EFI_BOOT_OPTION_SUPPORT_APP 0x00000002\r
-#define EFI_BOOT_OPTION_SUPPORT_SYSPREP 0x00000010\r
-#define EFI_BOOT_OPTION_SUPPORT_COUNT 0x00000300\r
+#define EFI_BOOT_OPTION_SUPPORT_KEY 0x00000001\r
+#define EFI_BOOT_OPTION_SUPPORT_APP 0x00000002\r
+#define EFI_BOOT_OPTION_SUPPORT_SYSPREP 0x00000010\r
+#define EFI_BOOT_OPTION_SUPPORT_COUNT 0x00000300\r
\r
///\r
/// EFI Boot Key Data\r
///\r
/// Indicates the revision of the EFI_KEY_OPTION structure. This revision level should be 0.\r
///\r
- UINT32 Revision : 8;\r
+ UINT32 Revision : 8;\r
///\r
/// Either the left or right Shift keys must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 ShiftPressed : 1;\r
+ UINT32 ShiftPressed : 1;\r
///\r
/// Either the left or right Control keys must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 ControlPressed : 1;\r
+ UINT32 ControlPressed : 1;\r
///\r
/// Either the left or right Alt keys must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 AltPressed : 1;\r
+ UINT32 AltPressed : 1;\r
///\r
/// Either the left or right Logo keys must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 LogoPressed : 1;\r
+ UINT32 LogoPressed : 1;\r
///\r
/// The Menu key must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 MenuPressed : 1;\r
+ UINT32 MenuPressed : 1;\r
///\r
/// The SysReq key must be pressed (1) or must not be pressed (0).\r
///\r
- UINT32 SysReqPressed : 1;\r
- UINT32 Reserved : 16;\r
+ UINT32 SysReqPressed : 1;\r
+ UINT32 Reserved : 16;\r
///\r
/// Specifies the actual number of entries in EFI_KEY_OPTION.Keys, from 0-3. If\r
/// zero, then only the shift state is considered. If more than one, then the boot option will\r
/// only be launched if all of the specified keys are pressed with the same shift state.\r
///\r
- UINT32 InputKeyCount : 2;\r
+ UINT32 InputKeyCount : 2;\r
} Options;\r
- UINT32 PackedValue;\r
+ UINT32 PackedValue;\r
} EFI_BOOT_KEY_DATA;\r
\r
///\r
///\r
/// Specifies options about how the key will be processed.\r
///\r
- EFI_BOOT_KEY_DATA KeyData;\r
+ EFI_BOOT_KEY_DATA KeyData;\r
///\r
/// The CRC-32 which should match the CRC-32 of the entire EFI_LOAD_OPTION to\r
/// which BootOption refers. If the CRC-32s do not match this value, then this key\r
/// option is ignored.\r
///\r
- UINT32 BootOptionCrc;\r
+ UINT32 BootOptionCrc;\r
///\r
/// The Boot#### option which will be invoked if this key is pressed and the boot option\r
/// is active (LOAD_OPTION_ACTIVE is set).\r
///\r
- UINT16 BootOption;\r
+ UINT16 BootOption;\r
///\r
/// The key codes to compare against those returned by the\r
/// EFI_SIMPLE_TEXT_INPUT and EFI_SIMPLE_TEXT_INPUT_EX protocols.\r
/// The number of key codes (0-3) is specified by the EFI_KEY_CODE_COUNT field in KeyOptions.\r
///\r
- //EFI_INPUT_KEY Keys[];\r
+ // EFI_INPUT_KEY Keys[];\r
} EFI_KEY_OPTION;\r
#pragma pack()\r
\r
//\r
// EFI File location to boot from on removable media devices\r
//\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"\r
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"\r
-\r
-#if !defined(EFI_REMOVABLE_MEDIA_FILE_NAME)\r
-#if defined (MDE_CPU_IA32)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32\r
-#elif defined (MDE_CPU_X64)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64\r
-#elif defined (MDE_CPU_EBC)\r
-#elif defined (MDE_CPU_ARM)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM\r
-#elif defined (MDE_CPU_AARCH64)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64\r
-#elif defined (MDE_CPU_RISCV64)\r
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64\r
-#else\r
- #error Unknown Processor Type\r
-#endif\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"\r
+\r
+#if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)\r
+ #if defined (MDE_CPU_IA32)\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32\r
+ #elif defined (MDE_CPU_X64)\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64\r
+ #elif defined (MDE_CPU_EBC)\r
+ #elif defined (MDE_CPU_ARM)\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM\r
+ #elif defined (MDE_CPU_AARCH64)\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64\r
+ #elif defined (MDE_CPU_RISCV64)\r
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64\r
+ #else\r
+ #error Unknown Processor Type\r
+ #endif\r
#endif\r
\r
//\r
// The directory within the active EFI System Partition defined for delivery of capsule to firmware\r
//\r
-#define EFI_CAPSULE_FILE_DIRECTORY L"\\EFI\\UpdateCapsule\\"\r
+#define EFI_CAPSULE_FILE_DIRECTORY L"\\EFI\\UpdateCapsule\\"\r
\r
#include <Uefi/UefiPxe.h>\r
#include <Uefi/UefiGpt.h>\r
//\r
// Make sure we are using the correct packing rules per EFI specification\r
//\r
-#if !defined(__GNUC__)\r
-#pragma pack()\r
+#if !defined (__GNUC__)\r
+ #pragma pack()\r
#endif\r
\r
-#if defined(__GNUC__) && defined(__pic__) && !defined(USING_LTO) && !defined(__APPLE__)\r
+#if defined (__GNUC__) && defined (__pic__) && !defined (USING_LTO) && !defined (__APPLE__)\r
//\r
// Mark all symbol declarations and references as hidden, meaning they will\r
// not be subject to symbol preemption. This allows the compiler to refer to\r
// references can be resolved locally, and so there is no need to set the\r
// pragma in that case (and doing so will cause other issues).\r
//\r
-#pragma GCC visibility push (hidden)\r
+ #pragma GCC visibility push (hidden)\r
#endif\r
\r
-#if defined(__INTEL_COMPILER)\r
+#if defined (__INTEL_COMPILER)\r
//\r
// Disable ICC's remark #869: "Parameter" was never referenced warning.\r
// This is legal ANSI C code so we disable the remark that is turned on with -Wall\r
//\r
-#pragma warning ( disable : 869 )\r
+ #pragma warning ( disable : 869 )\r
\r
//\r
// Disable ICC's remark #1418: external function definition with no prior declaration.\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 1418 )\r
+ #pragma warning ( disable : 1418 )\r
\r
//\r
// Disable ICC's remark #1419: external declaration in primary source file\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 1419 )\r
+ #pragma warning ( disable : 1419 )\r
\r
//\r
// Disable ICC's remark #593: "Variable" was set but never used.\r
// This is legal ANSI C code so we disable the remark that is turned on with /W4\r
//\r
-#pragma warning ( disable : 593 )\r
+ #pragma warning ( disable : 593 )\r
\r
#endif\r
\r
-\r
-#if defined(_MSC_EXTENSIONS)\r
+#if defined (_MSC_EXTENSIONS)\r
\r
//\r
// Disable warning that make it impossible to compile at /W4\r
//\r
// Disabling bitfield type checking warnings.\r
//\r
-#pragma warning ( disable : 4214 )\r
+ #pragma warning ( disable : 4214 )\r
\r
//\r
// Disabling the unreferenced formal parameter warnings.\r
//\r
-#pragma warning ( disable : 4100 )\r
+ #pragma warning ( disable : 4100 )\r
\r
//\r
// Disable slightly different base types warning as CHAR8 * can not be set\r
// to a constant string.\r
//\r
-#pragma warning ( disable : 4057 )\r
+ #pragma warning ( disable : 4057 )\r
\r
//\r
// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning\r
//\r
-#pragma warning ( disable : 4127 )\r
+ #pragma warning ( disable : 4127 )\r
\r
//\r
// This warning is caused by functions defined but not used. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4505 )\r
+ #pragma warning ( disable : 4505 )\r
\r
//\r
// This warning is caused by empty (after preprocessing) source file. For precompiled header only.\r
//\r
-#pragma warning ( disable : 4206 )\r
+ #pragma warning ( disable : 4206 )\r
\r
-#if defined(_MSC_VER) && _MSC_VER >= 1800\r
+ #if defined (_MSC_VER) && _MSC_VER >= 1800\r
\r
//\r
// Disable these warnings for VS2013.\r
// This warning is for potentially uninitialized local variable, and it may cause false\r
// positive issues in VS2013 and VS2015 build\r
//\r
-#pragma warning ( disable : 4701 )\r
+ #pragma warning ( disable : 4701 )\r
\r
//\r
// This warning is for potentially uninitialized local pointer variable, and it may cause\r
// false positive issues in VS2013 and VS2015 build\r
//\r
-#pragma warning ( disable : 4703 )\r
+ #pragma warning ( disable : 4703 )\r
\r
-#endif\r
+ #endif\r
\r
#endif\r
\r
+#if defined (_MSC_EXTENSIONS)\r
+//\r
+// use Microsoft C compiler dependent integer width types\r
+//\r
\r
-#if defined(_MSC_EXTENSIONS)\r
- //\r
- // use Microsoft C compiler dependent integer width types\r
- //\r
-\r
- ///\r
- /// 8-byte unsigned value\r
- ///\r
- typedef unsigned __int64 UINT64;\r
- ///\r
- /// 8-byte signed value\r
- ///\r
- typedef __int64 INT64;\r
- ///\r
- /// 4-byte unsigned value\r
- ///\r
- typedef unsigned __int32 UINT32;\r
- ///\r
- /// 4-byte signed value\r
- ///\r
- typedef __int32 INT32;\r
- ///\r
- /// 2-byte unsigned value\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value\r
- ///\r
- typedef signed char INT8;\r
+///\r
+/// 8-byte unsigned value\r
+///\r
+typedef unsigned __int64 UINT64;\r
+///\r
+/// 8-byte signed value\r
+///\r
+typedef __int64 INT64;\r
+///\r
+/// 4-byte unsigned value\r
+///\r
+typedef unsigned __int32 UINT32;\r
+///\r
+/// 4-byte signed value\r
+///\r
+typedef __int32 INT32;\r
+///\r
+/// 2-byte unsigned value\r
+///\r
+typedef unsigned short UINT16;\r
+///\r
+/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
+///\r
+typedef unsigned short CHAR16;\r
+///\r
+/// 2-byte signed value\r
+///\r
+typedef short INT16;\r
+///\r
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
+/// values are undefined.\r
+///\r
+typedef unsigned char BOOLEAN;\r
+///\r
+/// 1-byte unsigned value\r
+///\r
+typedef unsigned char UINT8;\r
+///\r
+/// 1-byte Character\r
+///\r
+typedef char CHAR8;\r
+///\r
+/// 1-byte signed value\r
+///\r
+typedef signed char INT8;\r
#else\r
- ///\r
- /// 8-byte unsigned value\r
- ///\r
- typedef unsigned long long UINT64;\r
- ///\r
- /// 8-byte signed value\r
- ///\r
- typedef long long INT64;\r
- ///\r
- /// 4-byte unsigned value\r
- ///\r
- typedef unsigned int UINT32;\r
- ///\r
- /// 4-byte signed value\r
- ///\r
- typedef int INT32;\r
- ///\r
- /// 2-byte unsigned value\r
- ///\r
- typedef unsigned short UINT16;\r
- ///\r
- /// 2-byte Character. Unless otherwise specified all strings are stored in the\r
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
- ///\r
- typedef unsigned short CHAR16;\r
- ///\r
- /// 2-byte signed value\r
- ///\r
- typedef short INT16;\r
- ///\r
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
- /// values are undefined.\r
- ///\r
- typedef unsigned char BOOLEAN;\r
- ///\r
- /// 1-byte unsigned value\r
- ///\r
- typedef unsigned char UINT8;\r
- ///\r
- /// 1-byte Character\r
- ///\r
- typedef char CHAR8;\r
- ///\r
- /// 1-byte signed value\r
- ///\r
- typedef signed char INT8;\r
+///\r
+/// 8-byte unsigned value\r
+///\r
+typedef unsigned long long UINT64;\r
+///\r
+/// 8-byte signed value\r
+///\r
+typedef long long INT64;\r
+///\r
+/// 4-byte unsigned value\r
+///\r
+typedef unsigned int UINT32;\r
+///\r
+/// 4-byte signed value\r
+///\r
+typedef int INT32;\r
+///\r
+/// 2-byte unsigned value\r
+///\r
+typedef unsigned short UINT16;\r
+///\r
+/// 2-byte Character. Unless otherwise specified all strings are stored in the\r
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.\r
+///\r
+typedef unsigned short CHAR16;\r
+///\r
+/// 2-byte signed value\r
+///\r
+typedef short INT16;\r
+///\r
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other\r
+/// values are undefined.\r
+///\r
+typedef unsigned char BOOLEAN;\r
+///\r
+/// 1-byte unsigned value\r
+///\r
+typedef unsigned char UINT8;\r
+///\r
+/// 1-byte Character\r
+///\r
+typedef char CHAR8;\r
+///\r
+/// 1-byte signed value\r
+///\r
+typedef signed char INT8;\r
#endif\r
\r
///\r
/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef UINT64 UINTN;\r
+typedef UINT64 UINTN;\r
///\r
/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,\r
/// 8 bytes on supported 64-bit processor instructions)\r
///\r
-typedef INT64 INTN;\r
-\r
+typedef INT64 INTN;\r
\r
//\r
// Processor specific defines\r
///\r
/// A value of native width with the highest bit set.\r
///\r
-#define MAX_BIT 0x8000000000000000ULL\r
+#define MAX_BIT 0x8000000000000000ULL\r
///\r
/// A value of native width with the two highest bits set.\r
///\r
///\r
/// Maximum legal x64 address\r
///\r
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL\r
\r
///\r
/// Maximum usable address at boot time\r
///\r
-#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
+#define MAX_ALLOC_ADDRESS MAX_ADDRESS\r
\r
///\r
/// Maximum legal x64 INTN and UINTN values.\r
///\r
/// Minimum legal x64 INTN value.\r
///\r
-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)\r
+#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)\r
\r
///\r
/// The stack alignment required for x64\r
///\r
-#define CPU_STACK_ALIGNMENT 16\r
+#define CPU_STACK_ALIGNMENT 16\r
\r
///\r
/// Page allocation granularity for x64\r
///\r
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)\r
\r
//\r
// Modifier to ensure that all protocol member functions and EFI intrinsics\r
// EFI intrinsics are required to modify their member functions with EFIAPI.\r
//\r
#ifdef EFIAPI\r
- ///\r
- /// If EFIAPI is already defined, then we use that definition.\r
- ///\r
-#elif defined(_MSC_EXTENSIONS)\r
- ///\r
- /// Microsoft* compiler specific method for EFIAPI calling convention.\r
- ///\r
- #define EFIAPI __cdecl\r
-#elif defined(__GNUC__)\r
- ///\r
- /// Define the standard calling convention regardless of optimization level.\r
- /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI\r
- /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)\r
- /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for\r
- /// x64. Warning the assembly code in the MDE x64 does not follow the correct\r
- /// ABI for the standard x64 (x86-64) GCC.\r
- ///\r
- #define EFIAPI\r
+///\r
+/// If EFIAPI is already defined, then we use that definition.\r
+///\r
+#elif defined (_MSC_EXTENSIONS)\r
+///\r
+/// Microsoft* compiler specific method for EFIAPI calling convention.\r
+///\r
+#define EFIAPI __cdecl\r
+#elif defined (__GNUC__)\r
+///\r
+/// Define the standard calling convention regardless of optimization level.\r
+/// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI\r
+/// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)\r
+/// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for\r
+/// x64. Warning the assembly code in the MDE x64 does not follow the correct\r
+/// ABI for the standard x64 (x86-64) GCC.\r
+///\r
+#define EFIAPI\r
#else\r
- ///\r
- /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
- /// is the standard.\r
- ///\r
- #define EFIAPI\r
+///\r
+/// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI\r
+/// is the standard.\r
+///\r
+#define EFIAPI\r
#endif\r
\r
-#if defined(__GNUC__) || defined(__clang__)\r
- ///\r
- /// For GNU assembly code, .global or .globl can declare global symbols.\r
- /// Define this macro to unify the usage.\r
- ///\r
- #define ASM_GLOBAL .globl\r
+#if defined (__GNUC__) || defined (__clang__)\r
+///\r
+/// For GNU assembly code, .global or .globl can declare global symbols.\r
+/// Define this macro to unify the usage.\r
+///\r
+#define ASM_GLOBAL .globl\r
#endif\r
\r
/**\r
@return The pointer to the first instruction of a function given a function pointer.\r
\r
**/\r
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)\r
\r
#ifndef __USER_LABEL_PREFIX__\r
#define __USER_LABEL_PREFIX__\r
#endif\r
\r
#endif\r
-\r
VOID\r
)\r
{\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return Address;\r
}\r
\r
VOID\r
)\r
{\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return Address;\r
}\r
\r
VOID\r
)\r
{\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return Address;\r
}\r
\r
VOID\r
)\r
{\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
return Address;\r
}\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
return Address;\r
}\r
\r
VOID\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
return Address;\r
}\r
\r
VOID\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
}\r
\r
/**\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
return Address;\r
}\r
\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
+ DEBUG ((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));\r
return Address;\r
}\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
if (Length == 0) {\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
- UINT32 RegEbx;\r
- UINT32 RegEdx;\r
- UINTN CacheLineSize;\r
- UINTN Start;\r
- UINTN End;\r
+ UINT32 RegEbx;\r
+ UINT32 RegEdx;\r
+ UINTN CacheLineSize;\r
+ UINTN Start;\r
+ UINTN End;\r
\r
if (Length == 0) {\r
return Address;\r
//\r
// Calculate the cache line alignment\r
//\r
- End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);\r
+ End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);\r
Start &= ~((UINTN)CacheLineSize - 1);\r
\r
do {\r
- Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;\r
+ Start = (UINTN)AsmFlushCacheLine ((VOID *)Start) + CacheLineSize;\r
} while (Start != End);\r
+\r
return Address;\r
}\r
\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
return WriteBackInvalidateDataCacheRange (Address, Length);\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
//\r
VOID *\r
EFIAPI\r
InvalidateInstructionCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
WriteBackInvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
WriteBackDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
VOID *\r
EFIAPI\r
InvalidateDataCacheRange (\r
- IN VOID *Address,\r
- IN UINTN Length\r
+ IN VOID *Address,\r
+ IN UINTN Length\r
)\r
{\r
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r
\r
**/\r
\r
-\r
-\r
/**\r
Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r
\r
mov cr3, eax\r
}\r
}\r
-\r
{\r
AsmWriteCr3 (AsmReadCr3 ());\r
}\r
-\r
\r
**/\r
\r
-\r
/**\r
Places the CPU in a sleep state until an interrupt is received.\r
\r
hlt\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
/**\r
Places the CPU in a sleep state until an interrupt is received.\r
\r
{\r
__asm__ __volatile__ ("hlt"::: "memory");\r
}\r
-\r
{\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
{\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
return Buffer;\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
return FALSE;\r
}\r
-\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
/**\r
The constructor function initialize the Serial Port Library\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
//\r
// If Format is NULL, then ASSERT().\r
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
//\r
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
-\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/ExtractGuidedSectionLib.h>\r
\r
-#define EXTRACT_HANDLER_INFO_SIGNATURE SIGNATURE_32 ('E', 'G', 'S', 'I')\r
+#define EXTRACT_HANDLER_INFO_SIGNATURE SIGNATURE_32 ('E', 'G', 'S', 'I')\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 NumberOfExtractHandler;\r
- GUID *ExtractHandlerGuidTable;\r
- EXTRACT_GUIDED_SECTION_DECODE_HANDLER *ExtractDecodeHandlerTable;\r
- EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *ExtractGetInfoHandlerTable;\r
+ UINT32 Signature;\r
+ UINT32 NumberOfExtractHandler;\r
+ GUID *ExtractHandlerGuidTable;\r
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER *ExtractDecodeHandlerTable;\r
+ EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *ExtractGetInfoHandlerTable;\r
} EXTRACT_GUIDED_SECTION_HANDLER_INFO;\r
\r
/**\r
**/\r
RETURN_STATUS\r
GetExtractGuidedSectionHandlerInfo (\r
- IN OUT EXTRACT_GUIDED_SECTION_HANDLER_INFO **InfoPointer\r
+ IN OUT EXTRACT_GUIDED_SECTION_HANDLER_INFO **InfoPointer\r
)\r
{\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
//\r
// Set the available memory address to handler info.\r
//\r
- HandlerInfo = (EXTRACT_GUIDED_SECTION_HANDLER_INFO*)(VOID*)(UINTN) PcdGet64 (PcdGuidedExtractHandlerTableAddress);\r
+ HandlerInfo = (EXTRACT_GUIDED_SECTION_HANDLER_INFO *)(VOID *)(UINTN)PcdGet64 (PcdGuidedExtractHandlerTableAddress);\r
if (HandlerInfo == NULL) {\r
*InfoPointer = NULL;\r
return EFI_OUT_OF_RESOURCES;\r
//\r
// Init HandlerInfo structure\r
//\r
- HandlerInfo->NumberOfExtractHandler = 0;\r
- HandlerInfo->ExtractHandlerGuidTable = (GUID *) (HandlerInfo + 1);\r
- HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
- );\r
- HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
- sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
- );\r
+ HandlerInfo->NumberOfExtractHandler = 0;\r
+ HandlerInfo->ExtractHandlerGuidTable = (GUID *)(HandlerInfo + 1);\r
+ HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
+ );\r
+ HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
+ sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
+ );\r
*InfoPointer = HandlerInfo;\r
return RETURN_SUCCESS;\r
}\r
OUT GUID **ExtractHandlerGuidTable\r
)\r
{\r
- RETURN_STATUS Status;\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ RETURN_STATUS Status;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
ASSERT (ExtractHandlerGuidTable != NULL);\r
\r
IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler\r
)\r
{\r
- UINT32 Index;\r
- RETURN_STATUS Status;\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ UINT32 Index;\r
+ RETURN_STATUS Status;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
//\r
// Check input parameter\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {\r
//\r
// If the guided handler has been registered before, only update its handler.\r
//\r
- HandlerInfo->ExtractDecodeHandlerTable [Index] = DecodeHandler;\r
- HandlerInfo->ExtractGetInfoHandlerTable [Index] = GetInfoHandler;\r
+ HandlerInfo->ExtractDecodeHandlerTable[Index] = DecodeHandler;\r
+ HandlerInfo->ExtractGetInfoHandlerTable[Index] = GetInfoHandler;\r
return RETURN_SUCCESS;\r
}\r
}\r
// Register new Handler and guid value.\r
//\r
CopyGuid (HandlerInfo->ExtractHandlerGuidTable + HandlerInfo->NumberOfExtractHandler, SectionGuid);\r
- HandlerInfo->ExtractDecodeHandlerTable [HandlerInfo->NumberOfExtractHandler] = DecodeHandler;\r
- HandlerInfo->ExtractGetInfoHandlerTable [HandlerInfo->NumberOfExtractHandler++] = GetInfoHandler;\r
+ HandlerInfo->ExtractDecodeHandlerTable[HandlerInfo->NumberOfExtractHandler] = DecodeHandler;\r
+ HandlerInfo->ExtractGetInfoHandlerTable[HandlerInfo->NumberOfExtractHandler++] = GetInfoHandler;\r
\r
return RETURN_SUCCESS;\r
}\r
OUT UINT16 *SectionAttribute\r
)\r
{\r
- UINT32 Index;\r
- RETURN_STATUS Status;\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ RETURN_STATUS Status;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
//\r
// Check input parameter\r
}\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {\r
//\r
// Call the match handler to get information for the input section data.\r
//\r
- return HandlerInfo->ExtractGetInfoHandlerTable [Index] (\r
- InputSection,\r
- OutputBufferSize,\r
- ScratchBufferSize,\r
- SectionAttribute\r
- );\r
+ return HandlerInfo->ExtractGetInfoHandlerTable[Index](\r
+ InputSection,\r
+ OutputBufferSize,\r
+ ScratchBufferSize,\r
+ SectionAttribute\r
+ );\r
}\r
}\r
\r
OUT UINT32 *AuthenticationStatus\r
)\r
{\r
- UINT32 Index;\r
- RETURN_STATUS Status;\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ RETURN_STATUS Status;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
//\r
// Check input parameter\r
}\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered Extract handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {\r
//\r
// Call the match handler to extract raw data for the input guided section.\r
//\r
- return HandlerInfo->ExtractDecodeHandlerTable [Index] (\r
- InputSection,\r
- OutputBuffer,\r
- ScratchBuffer,\r
- AuthenticationStatus\r
- );\r
+ return HandlerInfo->ExtractDecodeHandlerTable[Index](\r
+ InputSection,\r
+ OutputBuffer,\r
+ ScratchBuffer,\r
+ AuthenticationStatus\r
+ );\r
}\r
}\r
\r
OUT EXTRACT_GUIDED_SECTION_DECODE_HANDLER *DecodeHandler OPTIONAL\r
)\r
{\r
- UINT32 Index;\r
- RETURN_STATUS Status;\r
- EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ UINT32 Index;\r
+ RETURN_STATUS Status;\r
+ EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
//\r
// Check input parameter\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {\r
-\r
//\r
// If the guided handler has been registered before, then return the registered handlers.\r
//\r
if (GetInfoHandler != NULL) {\r
*GetInfoHandler = HandlerInfo->ExtractGetInfoHandlerTable[Index];\r
}\r
+\r
if (DecodeHandler != NULL) {\r
*DecodeHandler = HandlerInfo->ExtractDecodeHandlerTable[Index];\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
}\r
+\r
return RETURN_NOT_FOUND;\r
}\r
#ifndef __BASEIOLIB_INTRINSIC_INTERNAL_H_\r
#define __BASEIOLIB_INTRINSIC_INTERNAL_H_\r
\r
-\r
-\r
#include <Base.h>\r
\r
#include <Library/IoLib.h>\r
UINT8\r
EFIAPI\r
IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+ return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT16\r
EFIAPI\r
IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+ return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT32\r
EFIAPI\r
IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
UINT32\r
EFIAPI\r
IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
UINT32\r
EFIAPI\r
IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT64\r
EFIAPI\r
IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
UINT64\r
EFIAPI\r
IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
UINT64\r
EFIAPI\r
IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT8\r
EFIAPI\r
MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT16\r
EFIAPI\r
MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT32\r
EFIAPI\r
MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT64\r
EFIAPI\r
MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
UINT64\r
EFIAPI\r
MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
UINT64\r
EFIAPI\r
MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
/**\r
Reads an 8-bit MMIO register.\r
\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT8 Value;\r
- BOOLEAN Flag;\r
+ UINT8 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- Value = *(volatile UINT8*)Address;\r
+ Value = *(volatile UINT8 *)Address;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- *(volatile UINT8*)Address = Value;\r
+ *(volatile UINT8 *)Address = Value;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT16 Value;\r
- BOOLEAN Flag;\r
+ UINT16 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 1) == 0);\r
Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- Value = *(volatile UINT16*)Address;\r
+ Value = *(volatile UINT16 *)Address;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 1) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- *(volatile UINT16*)Address = Value;\r
+ *(volatile UINT16 *)Address = Value;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT32 Value;\r
- BOOLEAN Flag;\r
+ UINT32 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- Value = *(volatile UINT32*)Address;\r
+ Value = *(volatile UINT32 *)Address;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- *(volatile UINT32*)Address = Value;\r
+ *(volatile UINT32 *)Address = Value;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT64 Value;\r
- BOOLEAN Flag;\r
+ UINT64 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- Value = *(volatile UINT64*)Address;\r
+ Value = *(volatile UINT64 *)Address;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);\r
if (Flag) {\r
MemoryFence ();\r
- *(volatile UINT64*)Address = Value;\r
+ *(volatile UINT64 *)Address = Value;\r
MemoryFence ();\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
\r
return Value;\r
}\r
-\r
UINT8\r
EFIAPI\r
MmioRead8Internal (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
MmioWrite8Internal (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioRead16Internal (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
MmioWrite16Internal (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioRead32Internal (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
MmioWrite32Internal (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioRead64Internal (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
MmioWrite64Internal (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT8 Value;\r
- BOOLEAN Flag;\r
+ UINT8 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
if (Flag) {\r
Value = MmioRead8Internal (Address);\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
if (Flag) {\r
MmioWrite8Internal (Address, Value);\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- BOOLEAN Flag;\r
- UINT16 Value;\r
+ BOOLEAN Flag;\r
+ UINT16 Value;\r
\r
ASSERT ((Address & 1) == 0);\r
\r
if (Flag) {\r
Value = MmioRead16Internal (Address);\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 1) == 0);\r
\r
if (Flag) {\r
MmioWrite16Internal (Address, Value);\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- BOOLEAN Flag;\r
- UINT32 Value;\r
+ BOOLEAN Flag;\r
+ UINT32 Value;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
if (Flag) {\r
Value = MmioRead32Internal (Address);\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
if (Flag) {\r
MmioWrite32Internal (Address, Value);\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- BOOLEAN Flag;\r
- UINT64 Value;\r
+ BOOLEAN Flag;\r
+ UINT64 Value;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
if (Flag) {\r
Value = MmioRead64Internal (Address);\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
if (Flag) {\r
MmioWrite64Internal (Address, Value);\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
\r
return Value;\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseIoLibIntrinsicInternal.h"\r
\r
/**\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- UINT8 Data;\r
- BOOLEAN Flag;\r
+ UINT8 Data;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeIoRead (FilterWidth8, Port, &Data);\r
if (Flag) {\r
__asm__ __volatile__ ("inb %w1,%b0" : "=a" (Data) : "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoRead (FilterWidth8, Port, &Data);\r
\r
return Data;\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeIoWrite (FilterWidth8, Port, &Value);\r
if (Flag) {\r
__asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoWrite (FilterWidth8, Port, &Value);\r
\r
- return Value;;\r
+ return Value;\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
UINT16 Data;\r
\r
Flag = FilterBeforeIoRead (FilterWidth16, Port, &Data);\r
if (Flag) {\r
- __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));\r
+ __asm__ __volatile__ ("inw %w1,%w0" : "=a" (Data) : "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoRead (FilterWidth16, Port, &Data);\r
\r
return Data;\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
-\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Port & 1) == 0);\r
\r
if (Flag) {\r
__asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoWrite (FilterWidth16, Port, &Value);\r
\r
- return Value;;\r
+ return Value;\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
UINT32 Data;\r
if (Flag) {\r
__asm__ __volatile__ ("inl %w1,%0" : "=a" (Data) : "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoRead (FilterWidth32, Port, &Data);\r
\r
return Data;\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
BOOLEAN Flag;\r
if (Flag) {\r
__asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port));\r
}\r
+\r
FilterAfterIoWrite (FilterWidth32, Port, &Value);\r
\r
return Value;\r
}\r
-\r
UINT8 *\r
EFIAPI\r
MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ReturnBuffer = Buffer;\r
\r
UINT16 *\r
EFIAPI\r
MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead16 (StartAddress);\r
+ *(Buffer++) = MmioRead16 (StartAddress);\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
UINT32 *\r
EFIAPI\r
MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead32 (StartAddress);\r
+ *(Buffer++) = MmioRead32 (StartAddress);\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead64 (StartAddress);\r
+ *(Buffer++) = MmioRead64 (StartAddress);\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to the MMIO region by using 8-bit access.\r
\r
UINT8 *\r
EFIAPI\r
MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
)\r
{\r
- VOID* ReturnBuffer;\r
+ VOID *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- ReturnBuffer = (UINT8 *) Buffer;\r
+ ReturnBuffer = (UINT8 *)Buffer;\r
\r
while (Length-- != 0) {\r
- MmioWrite8 (StartAddress++, *(Buffer++));\r
+ MmioWrite8 (StartAddress++, *(Buffer++));\r
}\r
\r
return ReturnBuffer;\r
-\r
}\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT16 *) Buffer;\r
+ ReturnBuffer = (UINT16 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite16 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to the MMIO region by using 32-bit access.\r
\r
UINT32 *\r
EFIAPI\r
MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT32 *) Buffer;\r
+ ReturnBuffer = (UINT32 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite32 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT64 *) Buffer;\r
+ ReturnBuffer = (UINT64 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite64 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
#include "BaseIoLibIntrinsicInternal.h"\r
\r
//\r
// Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
//\r
\r
-int _inp (unsigned short port);\r
-unsigned short _inpw (unsigned short port);\r
-unsigned long _inpd (unsigned short port);\r
-int _outp (unsigned short port, int databyte );\r
-unsigned short _outpw (unsigned short port, unsigned short dataword );\r
-unsigned long _outpd (unsigned short port, unsigned long dataword );\r
-void _ReadWriteBarrier (void);\r
+int\r
+_inp (\r
+ unsigned short port\r
+ );\r
+\r
+unsigned short\r
+_inpw (\r
+ unsigned short port\r
+ );\r
+\r
+unsigned long\r
+_inpd (\r
+ unsigned short port\r
+ );\r
+\r
+int\r
+_outp (\r
+ unsigned short port,\r
+ int databyte\r
+ );\r
+\r
+unsigned short\r
+_outpw (\r
+ unsigned short port,\r
+ unsigned short dataword\r
+ );\r
+\r
+unsigned long\r
+_outpd (\r
+ unsigned short port,\r
+ unsigned long dataword\r
+ );\r
+\r
+void\r
+_ReadWriteBarrier (\r
+ void\r
+ );\r
\r
#pragma intrinsic(_inp)\r
#pragma intrinsic(_inpw)\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- UINT8 Value;\r
- BOOLEAN Flag;\r
+ UINT8 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeIoRead (FilterWidth8, Port, &Value);\r
if (Flag) {\r
Value = (UINT8)_inp ((UINT16)Port);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterAfterIoRead (FilterWidth8, Port, &Value);\r
\r
return Value;\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
- Flag = FilterBeforeIoWrite(FilterWidth8, Port, &Value);\r
+ Flag = FilterBeforeIoWrite (FilterWidth8, Port, &Value);\r
if (Flag) {\r
_ReadWriteBarrier ();\r
(UINT8)_outp ((UINT16)Port, Value);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterAfterIoWrite (FilterWidth8, Port, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- UINT16 Value;\r
- BOOLEAN Flag;\r
+ UINT16 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Port & 1) == 0);\r
\r
Value = _inpw ((UINT16)Port);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterBeforeIoRead (FilterWidth16, Port, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Port & 1) == 0);\r
\r
- Flag = FilterBeforeIoWrite(FilterWidth16, Port, &Value);\r
+ Flag = FilterBeforeIoWrite (FilterWidth16, Port, &Value);\r
if (Flag) {\r
_ReadWriteBarrier ();\r
_outpw ((UINT16)Port, Value);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterAfterIoWrite (FilterWidth16, Port, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- UINT32 Value;\r
- BOOLEAN Flag;\r
+ UINT32 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Port & 3) == 0);\r
\r
- Flag = FilterBeforeIoRead(FilterWidth32, Port, &Value);\r
+ Flag = FilterBeforeIoRead (FilterWidth32, Port, &Value);\r
if (Flag) {\r
_ReadWriteBarrier ();\r
Value = _inpd ((UINT16)Port);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterAfterIoRead (FilterWidth32, Port, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Port & 3) == 0);\r
\r
- Flag = FilterBeforeIoWrite(FilterWidth32, Port, &Value);\r
+ Flag = FilterBeforeIoWrite (FilterWidth32, Port, &Value);\r
if (Flag) {\r
_ReadWriteBarrier ();\r
_outpd ((UINT16)Port, Value);\r
_ReadWriteBarrier ();\r
}\r
+\r
FilterAfterIoWrite (FilterWidth32, Port, &Value);\r
\r
return Value;\r
\r
**/\r
\r
-\r
//\r
// Include common header file for this module.\r
//\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT8 Value;\r
- BOOLEAN Flag;\r
+ UINT8 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);\r
if (Flag) {\r
- Value = *(volatile UINT8*)Address;\r
+ Value = *(volatile UINT8 *)Address;\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);\r
if (Flag) {\r
- *(volatile UINT8*)Address = Value;\r
+ *(volatile UINT8 *)Address = Value;\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth8, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT16 Value;\r
- BOOLEAN Flag;\r
+ UINT16 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 1) == 0);\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);\r
if (Flag) {\r
- Value = *(volatile UINT16*)Address;\r
+ Value = *(volatile UINT16 *)Address;\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 1) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);\r
if (Flag) {\r
- *(volatile UINT16*)Address = Value;\r
+ *(volatile UINT16 *)Address = Value;\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth16, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT32 Value;\r
- BOOLEAN Flag;\r
+ UINT32 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);\r
if (Flag) {\r
- Value = *(volatile UINT32*)Address;\r
+ Value = *(volatile UINT32 *)Address;\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 3) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);\r
if (Flag) {\r
- *(volatile UINT32*)Address = Value;\r
+ *(volatile UINT32 *)Address = Value;\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth32, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINT64 Value;\r
- BOOLEAN Flag;\r
+ UINT64 Value;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);\r
if (Flag) {\r
- Value = *(volatile UINT64*)Address;\r
+ Value = *(volatile UINT64 *)Address;\r
}\r
+\r
FilterAfterMmIoRead (FilterWidth64, Address, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
ASSERT ((Address & 7) == 0);\r
\r
Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);\r
if (Flag) {\r
- *(volatile UINT64*)Address = Value;\r
+ *(volatile UINT64 *)Address = Value;\r
}\r
+\r
FilterAfterMmIoWrite (FilterWidth64, Address, &Value);\r
\r
return Value;\r
}\r
-\r
UINT64\r
EFIAPI\r
ARShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 64);\r
IN VOID *NewStack\r
);\r
\r
-\r
/**\r
Transfers control to a function starting with a new stack.\r
\r
UINT16\r
EFIAPI\r
ReadUnaligned16 (\r
- IN CONST UINT16 *Buffer\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- volatile UINT8 LowerByte;\r
- volatile UINT8 HigherByte;\r
+ volatile UINT8 LowerByte;\r
+ volatile UINT8 HigherByte;\r
\r
ASSERT (Buffer != NULL);\r
\r
- LowerByte = ((UINT8*)Buffer)[0];\r
- HigherByte = ((UINT8*)Buffer)[1];\r
+ LowerByte = ((UINT8 *)Buffer)[0];\r
+ HigherByte = ((UINT8 *)Buffer)[1];\r
\r
return (UINT16)(LowerByte | (HigherByte << 8));\r
}\r
UINT16\r
EFIAPI\r
WriteUnaligned16 (\r
- OUT UINT16 *Buffer,\r
- IN UINT16 Value\r
+ OUT UINT16 *Buffer,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
\r
- ((volatile UINT8*)Buffer)[0] = (UINT8)Value;\r
- ((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);\r
+ ((volatile UINT8 *)Buffer)[0] = (UINT8)Value;\r
+ ((volatile UINT8 *)Buffer)[1] = (UINT8)(Value >> 8);\r
\r
return Value;\r
}\r
UINT32\r
EFIAPI\r
ReadUnaligned24 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
\r
return (UINT32)(\r
- ReadUnaligned16 ((UINT16*)Buffer) |\r
- (((UINT8*)Buffer)[2] << 16)\r
- );\r
+ ReadUnaligned16 ((UINT16 *)Buffer) |\r
+ (((UINT8 *)Buffer)[2] << 16)\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
WriteUnaligned24 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
\r
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
- *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)Value);\r
+ *(UINT8 *)((UINT16 *)Buffer + 1) = (UINT8)(Value >> 16);\r
return Value;\r
}\r
\r
UINT32\r
EFIAPI\r
ReadUnaligned32 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
UINT16 LowerBytes;\r
\r
ASSERT (Buffer != NULL);\r
\r
- LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);\r
- HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);\r
+ LowerBytes = ReadUnaligned16 ((UINT16 *)Buffer);\r
+ HigherBytes = ReadUnaligned16 ((UINT16 *)Buffer + 1);\r
\r
- return (UINT32) (LowerBytes | (HigherBytes << 16));\r
+ return (UINT32)(LowerBytes | (HigherBytes << 16));\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
WriteUnaligned32 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
\r
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);\r
- WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)Value);\r
+ WriteUnaligned16 ((UINT16 *)Buffer + 1, (UINT16)(Value >> 16));\r
return Value;\r
}\r
\r
UINT64\r
EFIAPI\r
ReadUnaligned64 (\r
- IN CONST UINT64 *Buffer\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
UINT32 LowerBytes;\r
\r
ASSERT (Buffer != NULL);\r
\r
- LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);\r
- HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);\r
+ LowerBytes = ReadUnaligned32 ((UINT32 *)Buffer);\r
+ HigherBytes = ReadUnaligned32 ((UINT32 *)Buffer + 1);\r
\r
- return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));\r
+ return (UINT64)(LowerBytes | LShiftU64 (HigherBytes, 32));\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
WriteUnaligned64 (\r
- OUT UINT64 *Buffer,\r
- IN UINT64 Value\r
+ OUT UINT64 *Buffer,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
\r
- WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);\r
- WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)Value);\r
+ WriteUnaligned32 ((UINT32 *)Buffer + 1, (UINT32)RShiftU64 (Value, 32));\r
return Value;\r
}\r
UINT64\r
EFIAPI\r
InternalMathLShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathRShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathARShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathLRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathRRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathSwapBytes64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathMultU64x32 (\r
- IN UINT64 Multiplicand,\r
- IN UINT32 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathMultU64x64 (\r
- IN UINT64 Multiplicand,\r
- IN UINT64 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathDivU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
InternalMathModU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathDivRemU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor,\r
- OUT UINT32 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalMathDivRemU64x64 (\r
- IN UINT64 Dividend,\r
- IN UINT64 Divisor,\r
- OUT UINT64 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
);\r
\r
/**\r
INT64\r
EFIAPI\r
InternalMathDivRemS64x64 (\r
- IN INT64 Dividend,\r
- IN INT64 Divisor,\r
- OUT INT64 *Remainder OPTIONAL\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
);\r
\r
/**\r
IN VA_LIST Marker\r
);\r
\r
-\r
/**\r
Worker function that returns a bit field from Operand.\r
\r
UINTN\r
EFIAPI\r
BitFieldReadUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
);\r
\r
-\r
/**\r
Worker function that reads a bit field from Operand, performs a bitwise OR,\r
and returns the result.\r
UINTN\r
EFIAPI\r
BitFieldOrUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINTN OrData\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN OrData\r
);\r
\r
-\r
/**\r
Worker function that reads a bit field from Operand, performs a bitwise AND,\r
and returns the result.\r
UINTN\r
EFIAPI\r
BitFieldAndUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINTN AndData\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN AndData\r
);\r
\r
-\r
/**\r
Worker function that checks ASSERT condition for JumpBuffer\r
\r
IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
);\r
\r
-\r
/**\r
Restores the CPU context that was saved with SetJump().\r
\r
IN UINTN Value\r
);\r
\r
-\r
/**\r
Check if a Unicode character is a decimal character.\r
\r
BOOLEAN\r
EFIAPI\r
InternalIsDecimalDigitCharacter (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
);\r
\r
-\r
/**\r
Convert a Unicode character to numerical value.\r
\r
UINTN\r
EFIAPI\r
InternalHexCharToUintn (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
);\r
\r
-\r
/**\r
Check if a Unicode character is a hexadecimal character.\r
\r
BOOLEAN\r
EFIAPI\r
InternalIsHexaDecimalDigitCharacter (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
);\r
\r
-\r
/**\r
Check if a ASCII character is a decimal character.\r
\r
BOOLEAN\r
EFIAPI\r
InternalAsciiIsDecimalDigitCharacter (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
);\r
\r
-\r
/**\r
Check if a ASCII character is a hexadecimal character.\r
\r
BOOLEAN\r
EFIAPI\r
InternalAsciiIsHexaDecimalDigitCharacter (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
);\r
\r
-\r
/**\r
Convert a ASCII character to numerical value.\r
\r
UINTN\r
EFIAPI\r
InternalAsciiHexCharToUintn (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
);\r
\r
-\r
//\r
// Ia32 and x64 specific functions\r
//\r
VOID\r
EFIAPI\r
InternalX86ReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86WriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86ReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86WriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86FxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86FxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86EnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86DisablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
InternalX86RdRand16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
InternalX86RdRand32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
InternalX86RdRand64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
#else\r
UINTN\r
EFIAPI\r
InternalBaseLibBitFieldReadUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
//\r
UINTN\r
EFIAPI\r
InternalBaseLibBitFieldOrUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINTN OrData\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN OrData\r
)\r
{\r
//\r
// ~((UINTN)-2 << EndBit) is a mask in which bit[0] thru bit[EndBit]\r
// are 1's while bit[EndBit + 1] thru the most significant bit are 0's.\r
//\r
- return Operand | ((OrData << StartBit) & ~((UINTN) -2 << EndBit));\r
+ return Operand | ((OrData << StartBit) & ~((UINTN)-2 << EndBit));\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
InternalBaseLibBitFieldAndUint (\r
- IN UINTN Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINTN AndData\r
+ IN UINTN Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINTN AndData\r
)\r
{\r
//\r
UINT8\r
EFIAPI\r
BitFieldRead8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT (EndBit < 8);\r
UINT8\r
EFIAPI\r
BitFieldWrite8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (EndBit < 8);\r
UINT8\r
EFIAPI\r
BitFieldOr8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT (EndBit < 8);\r
UINT8\r
EFIAPI\r
BitFieldAnd8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
ASSERT (EndBit < 8);\r
UINT8\r
EFIAPI\r
BitFieldAndThenOr8 (\r
- IN UINT8 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT8 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT (EndBit < 8);\r
UINT16\r
EFIAPI\r
BitFieldRead16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT (EndBit < 16);\r
UINT16\r
EFIAPI\r
BitFieldWrite16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (EndBit < 16);\r
UINT16\r
EFIAPI\r
BitFieldOr16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT (EndBit < 16);\r
UINT16\r
EFIAPI\r
BitFieldAnd16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
ASSERT (EndBit < 16);\r
UINT16\r
EFIAPI\r
BitFieldAndThenOr16 (\r
- IN UINT16 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT16 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT (EndBit < 16);\r
UINT32\r
EFIAPI\r
BitFieldRead32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT (EndBit < 32);\r
UINT32\r
EFIAPI\r
BitFieldWrite32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (EndBit < 32);\r
UINT32\r
EFIAPI\r
BitFieldOr32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT (EndBit < 32);\r
UINT32\r
EFIAPI\r
BitFieldAnd32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT (EndBit < 32);\r
UINT32\r
EFIAPI\r
BitFieldAndThenOr32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT (EndBit < 32);\r
UINT64\r
EFIAPI\r
BitFieldRead64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT (EndBit < 64);\r
UINT64\r
EFIAPI\r
BitFieldWrite64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (EndBit < 64);\r
UINT64\r
EFIAPI\r
BitFieldOr64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
UINT64 Value1;\r
ASSERT (RShiftU64 (OrData, EndBit - StartBit) == (RShiftU64 (OrData, EndBit - StartBit) & 1));\r
\r
Value1 = LShiftU64 (OrData, StartBit);\r
- Value2 = LShiftU64 ((UINT64) - 2, EndBit);\r
+ Value2 = LShiftU64 ((UINT64)-2, EndBit);\r
\r
return Operand | (Value1 & ~Value2);\r
}\r
UINT64\r
EFIAPI\r
BitFieldAnd64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
UINT64 Value1;\r
UINT64\r
EFIAPI\r
BitFieldAndThenOr64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
ASSERT (EndBit < 64);\r
UINT8\r
EFIAPI\r
BitFieldCountOnes32 (\r
- IN UINT32 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
- UINT32 Count;\r
+ UINT32 Count;\r
\r
ASSERT (EndBit < 32);\r
ASSERT (StartBit <= EndBit);\r
\r
- Count = BitFieldRead32 (Operand, StartBit, EndBit);\r
+ Count = BitFieldRead32 (Operand, StartBit, EndBit);\r
Count -= ((Count >> 1) & 0x55555555);\r
- Count = (Count & 0x33333333) + ((Count >> 2) & 0x33333333);\r
+ Count = (Count & 0x33333333) + ((Count >> 2) & 0x33333333);\r
Count += Count >> 4;\r
Count &= 0x0F0F0F0F;\r
Count += Count >> 8;\r
Count += Count >> 16;\r
\r
- return (UINT8) Count & 0x3F;\r
+ return (UINT8)Count & 0x3F;\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
BitFieldCountOnes64 (\r
- IN UINT64 Operand,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Operand,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
- UINT64 BitField;\r
- UINT8 Count;\r
+ UINT64 BitField;\r
+ UINT8 Count;\r
\r
ASSERT (EndBit < 64);\r
ASSERT (StartBit <= EndBit);\r
\r
BitField = BitFieldRead64 (Operand, StartBit, EndBit);\r
- Count = BitFieldCountOnes32 ((UINT32) BitField, 0, 31);\r
- Count += BitFieldCountOnes32 ((UINT32) RShiftU64(BitField, 32), 0, 31);\r
+ Count = BitFieldCountOnes32 ((UINT32)BitField, 0, 31);\r
+ Count += BitFieldCountOnes32 ((UINT32)RShiftU64 (BitField, 32), 0, 31);\r
\r
return Count;\r
}\r
-\r
UINT8\r
EFIAPI\r
CalculateSum8 (\r
- IN CONST UINT8 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT8 Sum;\r
- UINTN Count;\r
+ UINT8 Sum;\r
+ UINTN Count;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));\r
\r
for (Sum = 0, Count = 0; Count < Length; Count++) {\r
- Sum = (UINT8) (Sum + *(Buffer + Count));\r
+ Sum = (UINT8)(Sum + *(Buffer + Count));\r
}\r
\r
return Sum;\r
}\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer\r
of 8-bit values.\r
UINT8\r
EFIAPI\r
CalculateCheckSum8 (\r
- IN CONST UINT8 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT8 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT8 CheckSum;\r
+ UINT8 CheckSum;\r
\r
CheckSum = CalculateSum8 (Buffer, Length);\r
\r
//\r
// Return the checksum based on 2's complement.\r
//\r
- return (UINT8) (0x100 - CheckSum);\r
+ return (UINT8)(0x100 - CheckSum);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
CalculateSum16 (\r
- IN CONST UINT16 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT16 Sum;\r
- UINTN Count;\r
- UINTN Total;\r
+ UINT16 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (((UINTN) Buffer & 0x1) == 0);\r
+ ASSERT (((UINTN)Buffer & 0x1) == 0);\r
ASSERT ((Length & 0x1) == 0);\r
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));\r
\r
Total = Length / sizeof (*Buffer);\r
for (Sum = 0, Count = 0; Count < Total; Count++) {\r
- Sum = (UINT16) (Sum + *(Buffer + Count));\r
+ Sum = (UINT16)(Sum + *(Buffer + Count));\r
}\r
\r
return Sum;\r
}\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
16-bit values.\r
UINT16\r
EFIAPI\r
CalculateCheckSum16 (\r
- IN CONST UINT16 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT16 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT16 CheckSum;\r
+ UINT16 CheckSum;\r
\r
CheckSum = CalculateSum16 (Buffer, Length);\r
\r
//\r
// Return the checksum based on 2's complement.\r
//\r
- return (UINT16) (0x10000 - CheckSum);\r
+ return (UINT16)(0x10000 - CheckSum);\r
}\r
\r
-\r
/**\r
Returns the sum of all elements in a buffer of 32-bit values. During\r
calculation, the carry bits are dropped.\r
UINT32\r
EFIAPI\r
CalculateSum32 (\r
- IN CONST UINT32 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT32 Sum;\r
- UINTN Count;\r
- UINTN Total;\r
+ UINT32 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (((UINTN) Buffer & 0x3) == 0);\r
+ ASSERT (((UINTN)Buffer & 0x3) == 0);\r
ASSERT ((Length & 0x3) == 0);\r
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));\r
\r
Total = Length / sizeof (*Buffer);\r
for (Sum = 0, Count = 0; Count < Total; Count++) {\r
return Sum;\r
}\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
32-bit values.\r
UINT32\r
EFIAPI\r
CalculateCheckSum32 (\r
- IN CONST UINT32 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT32 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT32 CheckSum;\r
+ UINT32 CheckSum;\r
\r
CheckSum = CalculateSum32 (Buffer, Length);\r
\r
//\r
// Return the checksum based on 2's complement.\r
//\r
- return (UINT32) ((UINT32)(-1) - CheckSum + 1);\r
+ return (UINT32)((UINT32)(-1) - CheckSum + 1);\r
}\r
\r
-\r
/**\r
Returns the sum of all elements in a buffer of 64-bit values. During\r
calculation, the carry bits are dropped.\r
UINT64\r
EFIAPI\r
CalculateSum64 (\r
- IN CONST UINT64 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT64 Sum;\r
- UINTN Count;\r
- UINTN Total;\r
+ UINT64 Sum;\r
+ UINTN Count;\r
+ UINTN Total;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (((UINTN) Buffer & 0x7) == 0);\r
+ ASSERT (((UINTN)Buffer & 0x7) == 0);\r
ASSERT ((Length & 0x7) == 0);\r
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));\r
\r
Total = Length / sizeof (*Buffer);\r
for (Sum = 0, Count = 0; Count < Total; Count++) {\r
return Sum;\r
}\r
\r
-\r
/**\r
Returns the two's complement checksum of all elements in a buffer of\r
64-bit values.\r
UINT64\r
EFIAPI\r
CalculateCheckSum64 (\r
- IN CONST UINT64 *Buffer,\r
- IN UINTN Length\r
+ IN CONST UINT64 *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
- UINT64 CheckSum;\r
+ UINT64 CheckSum;\r
\r
CheckSum = CalculateSum64 (Buffer, Length);\r
\r
//\r
// Return the checksum based on 2's complement.\r
//\r
- return (UINT64) ((UINT64)(-1) - CheckSum + 1);\r
+ return (UINT64)((UINT64)(-1) - CheckSum + 1);\r
}\r
\r
GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mCrcTable[256] = {\r
**/\r
UINT32\r
EFIAPI\r
-CalculateCrc32(\r
- IN VOID *Buffer,\r
- IN UINTN Length\r
+CalculateCrc32 (\r
+ IN VOID *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
UINTN Index;\r
UINT8 *Ptr;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1));\r
+ ASSERT (Length <= (MAX_ADDRESS - ((UINTN)Buffer) + 1));\r
\r
//\r
// Compute CRC\r
//\r
Crc = 0xffffffff;\r
for (Index = 0, Ptr = Buffer; Index < Length; Index++, Ptr++) {\r
- Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr];\r
+ Crc = (Crc >> 8) ^ mCrcTable[(UINT8)Crc ^ *Ptr];\r
}\r
\r
return Crc ^ 0xffffffff;\r
Hack function for passing GCC build.\r
**/\r
VOID\r
-__chkstk()\r
+__chkstk (\r
+ )\r
{\r
}\r
-\r
\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Disables CPU interrupts and returns the interrupt state prior to the disable\r
operation.\r
VOID\r
)\r
{\r
- BOOLEAN InterruptState;\r
+ BOOLEAN InterruptState;\r
\r
InterruptState = GetInterruptState ();\r
DisableInterrupts ();\r
BOOLEAN\r
EFIAPI\r
SetInterruptState (\r
- IN BOOLEAN InterruptState\r
+ IN BOOLEAN InterruptState\r
)\r
{\r
if (InterruptState) {\r
} else {\r
DisableInterrupts ();\r
}\r
+\r
return InterruptState;\r
}\r
\r
**/\r
\r
-\r
-\r
#include <Base.h>\r
#include <Library/BaseLib.h>\r
\r
volatile UINTN Index;\r
\r
for (Index = 0; Index == 0;) {\r
- CpuPause();\r
+ CpuPause ();\r
}\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INT64\r
EFIAPI\r
DivS64x64Remainder (\r
- IN INT64 Dividend,\r
- IN INT64 Divisor,\r
- OUT INT64 *Remainder OPTIONAL\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
)\r
{\r
ASSERT (Divisor != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
DivU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
ASSERT (Divisor != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
DivU64x32Remainder (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor,\r
- OUT UINT32 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
)\r
{\r
ASSERT (Divisor != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
DivU64x64Remainder (\r
- IN UINT64 Dividend,\r
- IN UINT64 Divisor,\r
- OUT UINT64 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
)\r
{\r
ASSERT (Divisor != 0);\r
extern\r
UINT64\r
_break (\r
- CHAR8 BreakCode\r
+ CHAR8 BreakCode\r
);\r
\r
/**\r
)\r
{\r
}\r
-\r
\r
**/\r
\r
-\r
/**\r
Uses as a barrier to stop speculative execution.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
-PathRemoveLastItem(\r
- IN OUT CHAR16 *Path\r
+PathRemoveLastItem (\r
+ IN OUT CHAR16 *Path\r
)\r
{\r
- CHAR16 *Walker;\r
- CHAR16 *LastSlash;\r
+ CHAR16 *Walker;\r
+ CHAR16 *LastSlash;\r
+\r
//\r
// get directory name from path... ('chop' off extra)\r
//\r
for ( Walker = Path, LastSlash = NULL\r
- ; Walker != NULL && *Walker != CHAR_NULL\r
- ; Walker++\r
- ){\r
- if (*Walker == L'\\' && *(Walker + 1) != CHAR_NULL) {\r
+ ; Walker != NULL && *Walker != CHAR_NULL\r
+ ; Walker++\r
+ )\r
+ {\r
+ if ((*Walker == L'\\') && (*(Walker + 1) != CHAR_NULL)) {\r
LastSlash = Walker+1;\r
- } else if (*Walker == L':' && *(Walker + 1) != L'\\' && *(Walker + 1) != CHAR_NULL) {\r
+ } else if ((*Walker == L':') && (*(Walker + 1) != L'\\') && (*(Walker + 1) != CHAR_NULL)) {\r
LastSlash = Walker+1;\r
}\r
}\r
+\r
if (LastSlash != NULL) {\r
*LastSlash = CHAR_NULL;\r
return (TRUE);\r
}\r
+\r
return (FALSE);\r
}\r
\r
\r
@return Returns Path, otherwise returns NULL to indicate that an error has occurred.\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
-PathCleanUpDirectories(\r
- IN CHAR16 *Path\r
-)\r
+PathCleanUpDirectories (\r
+ IN CHAR16 *Path\r
+ )\r
{\r
CHAR16 *TempString;\r
\r
while ((TempString = StrStr (Path, L"\\.\\")) != NULL) {\r
CopyMem (TempString, TempString + 2, StrSize (TempString + 2));\r
}\r
+\r
if ((StrLen (Path) >= 2) && (StrCmp (Path + StrLen (Path) - 2, L"\\.") == 0)) {\r
Path[StrLen (Path) - 1] = CHAR_NULL;\r
}\r
//\r
// Remove all the "\..". E.g.: fs0:\abc\..\def\..\r
//\r
- while (((TempString = StrStr(Path, L"\\..")) != NULL) &&\r
+ while (((TempString = StrStr (Path, L"\\..")) != NULL) &&\r
((*(TempString + 3) == L'\\') || (*(TempString + 3) == CHAR_NULL))\r
- ) {\r
+ )\r
+ {\r
*(TempString + 1) = CHAR_NULL;\r
- PathRemoveLastItem(Path);\r
+ PathRemoveLastItem (Path);\r
if (*(TempString + 3) != CHAR_NULL) {\r
CopyMem (Path + StrLen (Path), TempString + 4, StrSize (TempString + 4));\r
}\r
\r
return Path;\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT32\r
EFIAPI\r
GetPowerOfTwo32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
)\r
{\r
if (0 == Operand) {\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
GetPowerOfTwo64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
)\r
{\r
if (Operand == 0) {\r
return 0;\r
}\r
\r
- return LShiftU64 (1, (UINTN) HighBitSet64 (Operand));\r
+ return LShiftU64 (1, (UINTN)HighBitSet64 (Operand));\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INTN\r
EFIAPI\r
HighBitSet32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
)\r
{\r
- INTN BitIndex;\r
+ INTN BitIndex;\r
\r
if (Operand == 0) {\r
- return - 1;\r
+ return -1;\r
}\r
- for (BitIndex = 31; (INT32)Operand > 0; BitIndex--, Operand <<= 1);\r
+\r
+ for (BitIndex = 31; (INT32)Operand > 0; BitIndex--, Operand <<= 1) {\r
+ }\r
+\r
return BitIndex;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INTN\r
EFIAPI\r
HighBitSet64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
)\r
{\r
if (Operand == (UINT32)Operand) {\r
// Operand is really a 64-bit integer\r
//\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
- return HighBitSet32 (((UINT32*)&Operand)[1]) + 32;\r
+ return HighBitSet32 (((UINT32 *)&Operand)[1]) + 32;\r
} else {\r
return HighBitSet32 ((UINT32)RShiftU64 (Operand, 32)) + 32;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Shifts a 64-bit integer right between 0 and 63 bits. The high bits\r
are filled with original integer's bit 63. The shifted value is returned.\r
UINT64\r
EFIAPI\r
InternalMathARShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
_asm {\r
sar edx, cl\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-void __debugbreak (VOID);\r
+void\r
+__debugbreak (\r
+ VOID\r
+ );\r
\r
#pragma intrinsic(__debugbreak)\r
\r
{\r
__debugbreak ();\r
}\r
-\r
UINT32\r
EFIAPI\r
AsmCpuid (\r
- IN UINT32 Index,\r
- OUT UINT32 *RegisterEax OPTIONAL,\r
- OUT UINT32 *RegisterEbx OPTIONAL,\r
- OUT UINT32 *RegisterEcx OPTIONAL,\r
- OUT UINT32 *RegisterEdx OPTIONAL\r
+ IN UINT32 Index,\r
+ OUT UINT32 *RegisterEax OPTIONAL,\r
+ OUT UINT32 *RegisterEbx OPTIONAL,\r
+ OUT UINT32 *RegisterEcx OPTIONAL,\r
+ OUT UINT32 *RegisterEdx OPTIONAL\r
)\r
{\r
_asm {\r
UINT32\r
EFIAPI\r
AsmCpuidEx (\r
- IN UINT32 Index,\r
- IN UINT32 SubIndex,\r
- OUT UINT32 *RegisterEax OPTIONAL,\r
- OUT UINT32 *RegisterEbx OPTIONAL,\r
- OUT UINT32 *RegisterEcx OPTIONAL,\r
- OUT UINT32 *RegisterEdx OPTIONAL\r
+ IN UINT32 Index,\r
+ IN UINT32 SubIndex,\r
+ OUT UINT32 *RegisterEax OPTIONAL,\r
+ OUT UINT32 *RegisterEbx OPTIONAL,\r
+ OUT UINT32 *RegisterEcx OPTIONAL,\r
+ OUT UINT32 *RegisterEdx OPTIONAL\r
)\r
{\r
_asm {\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Requests CPU to pause for a short period of time.\r
\r
pause\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Disables CPU interrupts.\r
\r
cli\r
}\r
}\r
-\r
function after paging is disabled.\r
\r
**/\r
-__declspec (naked)\r
+__declspec(naked)\r
VOID\r
EFIAPI\r
InternalX86DisablePaging32 (\r
INT64\r
EFIAPI\r
InternalMathDivRemS64x64 (\r
- IN INT64 Dividend,\r
- IN INT64 Divisor,\r
- OUT INT64 *Remainder OPTIONAL\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
)\r
{\r
- INT64 Quot;\r
+ INT64 Quot;\r
\r
Quot = InternalMathDivRemU64x64 (\r
- (UINT64) (Dividend >= 0 ? Dividend : -Dividend),\r
- (UINT64) (Divisor >= 0 ? Divisor : -Divisor),\r
- (UINT64 *) Remainder\r
+ (UINT64)(Dividend >= 0 ? Dividend : -Dividend),\r
+ (UINT64)(Divisor >= 0 ? Divisor : -Divisor),\r
+ (UINT64 *)Remainder\r
);\r
- if (Remainder != NULL && Dividend < 0) {\r
+ if ((Remainder != NULL) && (Dividend < 0)) {\r
*Remainder = -*Remainder;\r
}\r
+\r
return (Dividend ^ Divisor) >= 0 ? Quot : -Quot;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
InternalMathDivU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
_asm {\r
pop edx ; restore high-order dword of the quotient\r
}\r
}\r
-\r
UINT64\r
EFIAPI\r
InternalMathDivRemU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor,\r
- OUT UINT32 *Remainder\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder\r
)\r
{\r
_asm {\r
pop edx\r
}\r
}\r
-\r
mov cr0, eax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Enables CPU interrupts for the smallest window required to capture any\r
pending interrupts.\r
cli\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Enables CPU interrupts.\r
\r
sti\r
}\r
}\r
-\r
function after paging is enabled.\r
\r
**/\r
-__declspec (naked)\r
+__declspec(naked)\r
VOID\r
EFIAPI\r
InternalX86EnablePaging32 (\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Flushes a cache line from all the instruction and data caches within the\r
coherency domain of the CPU.\r
VOID *\r
EFIAPI\r
AsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
)\r
{\r
//\r
\r
return LinearAddress;\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Restores the current floating point/SSE/SSE2 context from a buffer.\r
\r
VOID\r
EFIAPI\r
InternalX86FxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
)\r
{\r
_asm {\r
fxrstor [eax]\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Save the current floating point/SSE/SSE2 context to a buffer.\r
\r
VOID\r
EFIAPI\r
InternalX86FxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
)\r
{\r
_asm {\r
fxsave [eax]\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
)\r
{\r
- UINTN Eflags;\r
+ UINTN Eflags;\r
\r
__asm__ __volatile__ (\r
"pushfl \n\t"\r
"popl %0 "\r
: "=r" (Eflags)\r
- );\r
+ );\r
\r
return Eflags;\r
}\r
VOID\r
EFIAPI\r
InternalX86FxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
)\r
{\r
__asm__ __volatile__ (\r
"fxsave %0"\r
:\r
: "m" (*Buffer) // %0\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Restores the current floating point/SSE/SSE2 context from a buffer.\r
\r
VOID\r
EFIAPI\r
InternalX86FxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
)\r
{\r
__asm__ __volatile__ (\r
"fxrstor %0"\r
:\r
: "m" (*Buffer) // %0\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
"pop %%eax \n\t"\r
"pop %%edx \n\t"\r
: "=A" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm0 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm0" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm1 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm1" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm2 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm2" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm3 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm3" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm4 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm4" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm5 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm5" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm6 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm6" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm7 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movq %0, %%mm7" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
__asm__ __volatile__ (\r
"rdtsc"\r
: "=A" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
#include <Library/RegisterFilterLib.h>\r
\r
__asm__ __volatile__ ("sti"::: "memory");\r
}\r
\r
-\r
/**\r
Disables CPU interrupts.\r
\r
UINT64\r
EFIAPI\r
AsmReadMsr64 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
- UINT64 Data;\r
- BOOLEAN Flag;\r
+ UINT64 Data;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrRead (Index, &Data);\r
if (Flag) {\r
"rdmsr"\r
: "=A" (Data) // %0\r
: "c" (Index) // %1\r
- );\r
+ );\r
}\r
+\r
FilterAfterMsrRead (Index, &Data);\r
\r
return Data;\r
UINT64\r
EFIAPI\r
AsmWriteMsr64 (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
)\r
{\r
BOOLEAN Flag;\r
:\r
: "c" (Index),\r
"A" (Value)\r
- );\r
+ );\r
}\r
+\r
FilterAfterMsrWrite (Index, &Value);\r
\r
return Value;\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%cr0,%0"\r
: "=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of the Control Register 2 (CR2).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%cr2, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%cr3, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of the Control Register 4 (CR4).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%cr4, %0"\r
: "=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 0 (CR0).\r
\r
"movl %0, %%cr0"\r
:\r
: "r" (Cr0)\r
- );\r
+ );\r
return Cr0;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 2 (CR2).\r
\r
"movl %0, %%cr2"\r
:\r
: "r" (Cr2)\r
- );\r
+ );\r
return Cr2;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 3 (CR3).\r
\r
"movl %0, %%cr3"\r
:\r
: "r" (Cr3)\r
- );\r
+ );\r
return Cr3;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 4 (CR4).\r
\r
"movl %0, %%cr4"\r
:\r
: "r" (Cr4)\r
- );\r
+ );\r
return Cr4;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 0 (DR0).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr0, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 1 (DR1).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr1, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 2 (DR2).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr2, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 3 (DR3).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr3, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 4 (DR4).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr4, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 5 (DR5).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr5, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 6 (DR6).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr6, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 7 (DR7).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"movl %%dr7, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 0 (DR0).\r
\r
"movl %0, %%dr0"\r
:\r
: "r" (Dr0)\r
- );\r
+ );\r
return Dr0;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 1 (DR1).\r
\r
"movl %0, %%dr1"\r
:\r
: "r" (Dr1)\r
- );\r
+ );\r
return Dr1;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 2 (DR2).\r
\r
"movl %0, %%dr2"\r
:\r
: "r" (Dr2)\r
- );\r
+ );\r
return Dr2;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 3 (DR3).\r
\r
"movl %0, %%dr3"\r
:\r
: "r" (Dr3)\r
- );\r
+ );\r
return Dr3;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 4 (DR4).\r
\r
"movl %0, %%dr4"\r
:\r
: "r" (Dr4)\r
- );\r
+ );\r
return Dr4;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 5 (DR5).\r
\r
"movl %0, %%dr5"\r
:\r
: "r" (Dr5)\r
- );\r
+ );\r
return Dr5;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 6 (DR6).\r
\r
"movl %0, %%dr6"\r
:\r
: "r" (Dr6)\r
- );\r
+ );\r
return Dr6;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 7 (DR7).\r
\r
"movl %0, %%dr7"\r
:\r
: "r" (Dr7)\r
- );\r
+ );\r
return Dr7;\r
}\r
\r
-\r
/**\r
Reads the current value of Code Segment Register (CS).\r
\r
__asm__ __volatile__ (\r
"mov %%cs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Data Segment Register (DS).\r
\r
__asm__ __volatile__ (\r
"mov %%ds, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Extra Segment Register (ES).\r
\r
__asm__ __volatile__ (\r
"mov %%es, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of FS Data Segment Register (FS).\r
\r
__asm__ __volatile__ (\r
"mov %%fs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of GS Data Segment Register (GS).\r
\r
__asm__ __volatile__ (\r
"mov %%gs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Stack Segment Register (SS).\r
\r
__asm__ __volatile__ (\r
"mov %%ss, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Task Register (TR).\r
\r
__asm__ __volatile__ (\r
"str %0"\r
: "=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86ReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
__asm__ __volatile__ (\r
"sgdt %0"\r
: "=m" (*Gdtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86WriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lgdt %0"\r
:\r
: "m" (*Gdtr)\r
- );\r
-\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86ReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
__asm__ __volatile__ (\r
"sidt %0"\r
: "=m" (*Idtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86WriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lidt %0"\r
:\r
: "m" (*Idtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
__asm__ __volatile__ (\r
"sldt %0"\r
: "=g" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes the current Local Descriptor Table Register (GDTR) selector.\r
\r
VOID\r
EFIAPI\r
AsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lldtw %0"\r
:\r
: "g" (Ldtr) // %0\r
- );\r
+ );\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
AsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
UINT64 Data;\r
"rdpmc"\r
: "=A" (Data)\r
: "c" (Index)\r
- );\r
+ );\r
\r
return Data;\r
}\r
)\r
{\r
__asm__ __volatile__ ("invd":::"memory");\r
-\r
}\r
\r
-\r
/**\r
Flushes a cache line from all the instruction and data caches within the\r
coherency domain of the CPU.\r
VOID *\r
EFIAPI\r
AsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
)\r
{\r
UINT32 RegEdx;\r
return LinearAddress;\r
}\r
\r
-\r
__asm__ __volatile__ (\r
"clflush (%0)"\r
: "+a" (LinearAddress)\r
:\r
: "memory"\r
- );\r
+ );\r
\r
return LinearAddress;\r
}\r
{\r
BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
\r
- JumpBuffer.Eip = (UINTN)EntryPoint;\r
- JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID*);\r
- JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2);\r
- ((VOID**)JumpBuffer.Esp)[1] = Context1;\r
- ((VOID**)JumpBuffer.Esp)[2] = Context2;\r
+ JumpBuffer.Eip = (UINTN)EntryPoint;\r
+ JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID *);\r
+ JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2);\r
+ ((VOID **)JumpBuffer.Esp)[1] = Context1;\r
+ ((VOID **)JumpBuffer.Esp)[2] = Context2;\r
\r
LongJump (&JumpBuffer, (UINTN)-1);\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Executes a INVD instruction.\r
\r
invd\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Rotates a 64-bit integer left between 0 and 63 bits, filling\r
the low bits with the high bits that were rotated.\r
UINT64\r
EFIAPI\r
InternalMathLRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
_asm {\r
mov ecx, eax\r
mov eax, edx\r
mov edx, ecx\r
-L0:\r
+ L0 :\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Shifts a 64-bit integer left between 0 and 63 bits. The low bits\r
are filled with zeros. The shifted value is returned.\r
UINT64\r
EFIAPI\r
InternalMathLShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
_asm {\r
shl eax, cl\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Divides a 64-bit unsigned integer by a 32-bit unsigned integer and\r
generates a 32-bit unsigned remainder.\r
UINT32\r
EFIAPI\r
InternalMathModU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
_asm {\r
UINTN\r
EFIAPI\r
AsmMonitor (\r
- IN UINTN RegisterEax,\r
- IN UINTN RegisterEcx,\r
- IN UINTN RegisterEdx\r
+ IN UINTN RegisterEax,\r
+ IN UINTN RegisterEcx,\r
+ IN UINTN RegisterEdx\r
)\r
{\r
_asm {\r
_emit 0xc8\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Multiples a 64-bit unsigned integer by a 32-bit unsigned integer\r
and generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
InternalMathMultU64x32 (\r
- IN UINT64 Multiplicand,\r
- IN UINT32 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
)\r
{\r
_asm {\r
add edx, ecx\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer\r
and generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
InternalMathMultU64x64 (\r
- IN UINT64 Multiplicand,\r
- IN UINT64 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
)\r
{\r
_asm {\r
add edx, ebx\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmMwait (\r
- IN UINTN RegisterEax,\r
- IN UINTN RegisterEcx\r
+ IN UINTN RegisterEax,\r
+ IN UINTN RegisterEcx\r
)\r
{\r
_asm {\r
_emit 0xC9\r
}\r
}\r
-\r
VOID\r
EFIAPI\r
InternalX86DisablePaging64 (\r
- IN UINT16 CodeSelector,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 CodeSelector,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
)\r
{\r
//\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Rotates a 64-bit integer right between 0 and 63 bits, filling\r
the high bits with the high low bits that were rotated.\r
UINT64\r
EFIAPI\r
InternalMathRRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
_asm {\r
L0:\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Shifts a 64-bit integer right between 0 and 63 bits. This high bits\r
are filled with zeros. The shifted value is returned.\r
UINT64\r
EFIAPI\r
InternalMathRShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
_asm {\r
shr edx, cl\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of the Control Register 0 (CR0).\r
\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of the Control Register 2 (CR2).\r
\r
mov eax, cr2\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of the Control Register 3 (CR3).\r
\r
mov eax, cr3\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of the Control Register 4 (CR4).\r
\r
_emit 0xE0\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Code Segment Register (CS).\r
\r
mov ax, cs\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 0 (DR0).\r
\r
mov eax, dr0\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 1 (DR1).\r
\r
mov eax, dr1\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 2 (DR2).\r
\r
mov eax, dr2\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 3 (DR3).\r
\r
mov eax, dr3\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 4 (DR4).\r
\r
_emit 0xe0\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 5 (DR5).\r
\r
_emit 0xe8\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 6 (DR6).\r
\r
mov eax, dr6\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Debug Register 7 (DR7).\r
\r
mov eax, dr7\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Data Segment Register (DS).\r
\r
mov ax, ds\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of the EFLAGS register.\r
\r
pop eax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of ES Data Segment Register (ES).\r
\r
mov ax, es\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of FS Data Segment Register (FS).\r
\r
mov ax, fs\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
sgdt fword ptr [eax]\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of GS Data Segment Register (GS).\r
\r
mov ax, gs\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86ReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
_asm {\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
sldt ax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include <Library/RegisterFilterLib.h>\r
\r
/**\r
IN UINT32 Index\r
)\r
{\r
- UINT64 Value;\r
- BOOLEAN Flag;\r
+ UINT64 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrRead (Index, &Value);\r
if (Flag) {\r
Value = AsmReadMsr64Internal (Index);\r
}\r
+\r
FilterAfterMsrRead (Index, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
AsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
_asm {\r
rdpmc\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Stack Segment Register (SS).\r
\r
mov ax, ss\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Task Register (TR).\r
\r
str ax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
rdtsc\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Switches the endianess of a 64-bit integer.\r
\r
UINT64\r
EFIAPI\r
InternalMathSwapBytes64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
)\r
{\r
_asm {\r
bswap edx\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Executes a WBINVD instruction.\r
\r
wbinvd\r
}\r
}\r
-\r
mov cr0, eax\r
}\r
}\r
-\r
mov cr2, eax\r
}\r
}\r
-\r
mov cr3, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr0 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr0, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr1 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr1, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr2 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr2, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr3 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr3, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr4 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
_emit 0xe0\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr5 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
_emit 0xe8\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr6 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr6, eax\r
}\r
}\r
-\r
UINTN\r
EFIAPI\r
AsmWriteDr7 (\r
- IN UINTN Value\r
+ IN UINTN Value\r
)\r
{\r
_asm {\r
mov dr7, eax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86WriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
_asm {\r
lgdt fword ptr [eax]\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
InternalX86WriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
_asm {\r
popfd\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current Local Descriptor Table Register (GDTR) selector.\r
\r
VOID\r
EFIAPI\r
AsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
)\r
{\r
_asm {\r
lldt ax\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm0 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm1 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm2 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm3 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm4 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm5 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm6 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm7 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
_asm {\r
emms\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
#include <Library/RegisterFilterLib.h>\r
\r
/**\r
IN UINT64 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrWrite (Index, &Value);\r
if (Flag) {\r
wrmsr\r
}\r
}\r
+\r
FilterAfterMsrWrite (Index, &Value);\r
\r
return Value;\r
}\r
-\r
UINT32\r
EFIAPI\r
LRotU32 (\r
- IN UINT32 Operand,\r
- IN UINTN Count\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 32);\r
UINT64\r
EFIAPI\r
LRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 64);\r
UINT64\r
EFIAPI\r
LShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 64);\r
\r
**/\r
#if !defined (MDEPKG_NDEBUG)\r
- #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList) \\r
+#define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList) \\r
do { \\r
if (FeaturePcdGet (PcdVerifyNodeInList)) { \\r
ASSERT (InList == IsNodeInList ((FirstEntry), (SecondEntry))); \\r
} \\r
} while (FALSE)\r
#else\r
- #define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList)\r
+#define ASSERT_VERIFY_NODE_IN_VALID_LIST(FirstEntry, SecondEntry, InList)\r
#endif\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
IsNodeInList (\r
- IN CONST LIST_ENTRY *FirstEntry,\r
- IN CONST LIST_ENTRY *SecondEntry\r
+ IN CONST LIST_ENTRY *FirstEntry,\r
+ IN CONST LIST_ENTRY *SecondEntry\r
)\r
{\r
UINTN Count;\r
LIST_ENTRY *\r
EFIAPI\r
InitializeListHead (\r
- IN OUT LIST_ENTRY *ListHead\r
+ IN OUT LIST_ENTRY *ListHead\r
)\r
\r
{\r
ASSERT (ListHead != NULL);\r
\r
ListHead->ForwardLink = ListHead;\r
- ListHead->BackLink = ListHead;\r
+ ListHead->BackLink = ListHead;\r
return ListHead;\r
}\r
\r
LIST_ENTRY *\r
EFIAPI\r
InsertHeadList (\r
- IN OUT LIST_ENTRY *ListHead,\r
- IN OUT LIST_ENTRY *Entry\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
)\r
{\r
//\r
//\r
ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);\r
\r
- Entry->ForwardLink = ListHead->ForwardLink;\r
- Entry->BackLink = ListHead;\r
+ Entry->ForwardLink = ListHead->ForwardLink;\r
+ Entry->BackLink = ListHead;\r
Entry->ForwardLink->BackLink = Entry;\r
- ListHead->ForwardLink = Entry;\r
+ ListHead->ForwardLink = Entry;\r
return ListHead;\r
}\r
\r
LIST_ENTRY *\r
EFIAPI\r
InsertTailList (\r
- IN OUT LIST_ENTRY *ListHead,\r
- IN OUT LIST_ENTRY *Entry\r
+ IN OUT LIST_ENTRY *ListHead,\r
+ IN OUT LIST_ENTRY *Entry\r
)\r
{\r
//\r
//\r
ASSERT_VERIFY_NODE_IN_VALID_LIST (ListHead, Entry, FALSE);\r
\r
- Entry->ForwardLink = ListHead;\r
- Entry->BackLink = ListHead->BackLink;\r
+ Entry->ForwardLink = ListHead;\r
+ Entry->BackLink = ListHead->BackLink;\r
Entry->BackLink->ForwardLink = Entry;\r
- ListHead->BackLink = Entry;\r
+ ListHead->BackLink = Entry;\r
return ListHead;\r
}\r
\r
LIST_ENTRY *\r
EFIAPI\r
GetFirstNode (\r
- IN CONST LIST_ENTRY *List\r
+ IN CONST LIST_ENTRY *List\r
)\r
{\r
//\r
LIST_ENTRY *\r
EFIAPI\r
GetNextNode (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
)\r
{\r
//\r
LIST_ENTRY *\r
EFIAPI\r
GetPreviousNode (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
)\r
{\r
//\r
BOOLEAN\r
EFIAPI\r
IsListEmpty (\r
- IN CONST LIST_ENTRY *ListHead\r
+ IN CONST LIST_ENTRY *ListHead\r
)\r
{\r
//\r
BOOLEAN\r
EFIAPI\r
IsNull (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
)\r
{\r
//\r
BOOLEAN\r
EFIAPI\r
IsNodeAtEnd (\r
- IN CONST LIST_ENTRY *List,\r
- IN CONST LIST_ENTRY *Node\r
+ IN CONST LIST_ENTRY *List,\r
+ IN CONST LIST_ENTRY *Node\r
)\r
{\r
//\r
LIST_ENTRY *\r
EFIAPI\r
SwapListEntries (\r
- IN OUT LIST_ENTRY *FirstEntry,\r
- IN OUT LIST_ENTRY *SecondEntry\r
+ IN OUT LIST_ENTRY *FirstEntry,\r
+ IN OUT LIST_ENTRY *SecondEntry\r
)\r
{\r
- LIST_ENTRY *Ptr;\r
+ LIST_ENTRY *Ptr;\r
\r
if (FirstEntry == SecondEntry) {\r
return SecondEntry;\r
LIST_ENTRY *\r
EFIAPI\r
RemoveEntryList (\r
- IN CONST LIST_ENTRY *Entry\r
+ IN CONST LIST_ENTRY *Entry\r
)\r
{\r
ASSERT (!IsListEmpty (Entry));\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INTN\r
EFIAPI\r
LowBitSet32 (\r
- IN UINT32 Operand\r
+ IN UINT32 Operand\r
)\r
{\r
- INTN BitIndex;\r
+ INTN BitIndex;\r
\r
if (Operand == 0) {\r
return -1;\r
}\r
\r
- for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1);\r
+ for (BitIndex = 0; 0 == (Operand & 1); BitIndex++, Operand >>= 1) {\r
+ }\r
+\r
return BitIndex;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INTN\r
EFIAPI\r
LowBitSet64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
)\r
{\r
- INTN BitIndex;\r
+ INTN BitIndex;\r
\r
if (Operand == 0) {\r
return -1;\r
\r
for (BitIndex = 0;\r
(Operand & 1) == 0;\r
- BitIndex++, Operand = RShiftU64 (Operand, 1));\r
+ BitIndex++, Operand = RShiftU64 (Operand, 1))\r
+ {\r
+ }\r
+\r
return BitIndex;\r
}\r
UINT64\r
EFIAPI\r
InternalMathLShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
return Operand << Count;\r
UINT64\r
EFIAPI\r
InternalMathRShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
return Operand >> Count;\r
UINT64\r
EFIAPI\r
InternalMathARShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
INTN TestValue;\r
((INTN)Operand < 0 ? ~((UINTN)-1 >> Count) : 0);\r
}\r
\r
-\r
/**\r
Rotates a 64-bit integer left between 0 and 63 bits, filling\r
the low bits with the high bits that were rotated.\r
UINT64\r
EFIAPI\r
InternalMathLRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
return (Operand << Count) | (Operand >> (64 - Count));\r
UINT64\r
EFIAPI\r
InternalMathRRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
return (Operand >> Count) | (Operand << (64 - Count));\r
UINT64\r
EFIAPI\r
InternalMathSwapBytes64 (\r
- IN UINT64 Operand\r
+ IN UINT64 Operand\r
)\r
{\r
UINT64 LowerBytes;\r
UINT64 HigherBytes;\r
\r
- LowerBytes = (UINT64) SwapBytes32 ((UINT32) Operand);\r
- HigherBytes = (UINT64) SwapBytes32 ((UINT32) (Operand >> 32));\r
+ LowerBytes = (UINT64)SwapBytes32 ((UINT32)Operand);\r
+ HigherBytes = (UINT64)SwapBytes32 ((UINT32)(Operand >> 32));\r
\r
return (LowerBytes << 32 | HigherBytes);\r
}\r
UINT64\r
EFIAPI\r
InternalMathMultU64x32 (\r
- IN UINT64 Multiplicand,\r
- IN UINT32 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
)\r
{\r
return Multiplicand * Multiplier;\r
}\r
\r
-\r
/**\r
Multiplies a 64-bit unsigned integer by a 64-bit unsigned integer\r
and generates a 64-bit unsigned result.\r
UINT64\r
EFIAPI\r
InternalMathMultU64x64 (\r
- IN UINT64 Multiplicand,\r
- IN UINT64 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
)\r
{\r
return Multiplicand * Multiplier;\r
UINT64\r
EFIAPI\r
InternalMathDivU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
return Dividend / Divisor;\r
UINT32\r
EFIAPI\r
InternalMathModU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
return (UINT32)(Dividend % Divisor);\r
UINT64\r
EFIAPI\r
InternalMathDivRemU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor,\r
- OUT UINT32 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor,\r
+ OUT UINT32 *Remainder OPTIONAL\r
)\r
{\r
if (Remainder != NULL) {\r
*Remainder = (UINT32)(Dividend % Divisor);\r
}\r
+\r
return Dividend / Divisor;\r
}\r
\r
UINT64\r
EFIAPI\r
InternalMathDivRemU64x64 (\r
- IN UINT64 Dividend,\r
- IN UINT64 Divisor,\r
- OUT UINT64 *Remainder OPTIONAL\r
+ IN UINT64 Dividend,\r
+ IN UINT64 Divisor,\r
+ OUT UINT64 *Remainder OPTIONAL\r
)\r
{\r
if (Remainder != NULL) {\r
*Remainder = Dividend % Divisor;\r
}\r
+\r
return Dividend / Divisor;\r
}\r
\r
INT64\r
EFIAPI\r
InternalMathDivRemS64x64 (\r
- IN INT64 Dividend,\r
- IN INT64 Divisor,\r
- OUT INT64 *Remainder OPTIONAL\r
+ IN INT64 Dividend,\r
+ IN INT64 Divisor,\r
+ OUT INT64 *Remainder OPTIONAL\r
)\r
{\r
if (Remainder != NULL) {\r
*Remainder = Dividend % Divisor;\r
}\r
+\r
return Dividend / Divisor;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT32\r
EFIAPI\r
ModU64x32 (\r
- IN UINT64 Dividend,\r
- IN UINT32 Divisor\r
+ IN UINT64 Dividend,\r
+ IN UINT32 Divisor\r
)\r
{\r
ASSERT (Divisor != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
INT64\r
EFIAPI\r
MultS64x64 (\r
- IN INT64 Multiplicand,\r
- IN INT64 Multiplier\r
+ IN INT64 Multiplicand,\r
+ IN INT64 Multiplier\r
)\r
{\r
- return (INT64)MultU64x64 ((UINT64) Multiplicand, (UINT64) Multiplier);\r
+ return (INT64)MultU64x64 ((UINT64)Multiplicand, (UINT64)Multiplier);\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
MultU64x32 (\r
- IN UINT64 Multiplicand,\r
- IN UINT32 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT32 Multiplier\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
Result = InternalMathMultU64x32 (Multiplicand, Multiplier);\r
\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
MultU64x64 (\r
- IN UINT64 Multiplicand,\r
- IN UINT64 Multiplier\r
+ IN UINT64 Multiplicand,\r
+ IN UINT64 Multiplier\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
Result = InternalMathMultU64x64 (Multiplicand, Multiplier);\r
\r
VOID\r
EFIAPI\r
QuickSort (\r
- IN OUT VOID *BufferToSort,\r
- IN CONST UINTN Count,\r
- IN CONST UINTN ElementSize,\r
- IN BASE_SORT_COMPARE CompareFunction,\r
- OUT VOID *BufferOneElement\r
+ IN OUT VOID *BufferToSort,\r
+ IN CONST UINTN Count,\r
+ IN CONST UINTN ElementSize,\r
+ IN BASE_SORT_COMPARE CompareFunction,\r
+ OUT VOID *BufferOneElement\r
)\r
{\r
- VOID *Pivot;\r
- UINTN LoopCount;\r
- UINTN NextSwapLocation;\r
+ VOID *Pivot;\r
+ UINTN LoopCount;\r
+ UINTN NextSwapLocation;\r
\r
ASSERT (BufferToSort != NULL);\r
ASSERT (CompareFunction != NULL);\r
//\r
// pick a pivot (we choose last element)\r
//\r
- Pivot = ((UINT8*) BufferToSort + ((Count - 1) * ElementSize));\r
+ Pivot = ((UINT8 *)BufferToSort + ((Count - 1) * ElementSize));\r
\r
//\r
// Now get the pivot such that all on "left" are below it\r
//\r
// if the element is less than or equal to the pivot\r
//\r
- if (CompareFunction ((VOID*) ((UINT8*) BufferToSort + ((LoopCount) * ElementSize)), Pivot) <= 0){\r
+ if (CompareFunction ((VOID *)((UINT8 *)BufferToSort + ((LoopCount) * ElementSize)), Pivot) <= 0) {\r
//\r
// swap\r
//\r
- CopyMem (BufferOneElement, (UINT8*) BufferToSort + (NextSwapLocation * ElementSize), ElementSize);\r
- CopyMem ((UINT8*) BufferToSort + (NextSwapLocation * ElementSize), (UINT8*) BufferToSort + ((LoopCount) * ElementSize), ElementSize);\r
- CopyMem ((UINT8*) BufferToSort + ((LoopCount)*ElementSize), BufferOneElement, ElementSize);\r
+ CopyMem (BufferOneElement, (UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), ElementSize);\r
+ CopyMem ((UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), (UINT8 *)BufferToSort + ((LoopCount) * ElementSize), ElementSize);\r
+ CopyMem ((UINT8 *)BufferToSort + ((LoopCount)*ElementSize), BufferOneElement, ElementSize);\r
\r
//\r
// increment NextSwapLocation\r
NextSwapLocation++;\r
}\r
}\r
+\r
//\r
// swap pivot to it's final position (NextSwapLocation)\r
//\r
CopyMem (BufferOneElement, Pivot, ElementSize);\r
- CopyMem (Pivot, (UINT8*) BufferToSort + (NextSwapLocation * ElementSize), ElementSize);\r
- CopyMem ((UINT8*) BufferToSort + (NextSwapLocation * ElementSize), BufferOneElement, ElementSize);\r
+ CopyMem (Pivot, (UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), ElementSize);\r
+ CopyMem ((UINT8 *)BufferToSort + (NextSwapLocation * ElementSize), BufferOneElement, ElementSize);\r
\r
//\r
// Now recurse on 2 partial lists. neither of these will have the 'pivot' element\r
UINT32\r
EFIAPI\r
RRotU32 (\r
- IN UINT32 Operand,\r
- IN UINTN Count\r
+ IN UINT32 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 32);\r
UINT64\r
EFIAPI\r
RRotU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 64);\r
UINT64\r
EFIAPI\r
RShiftU64 (\r
- IN UINT64 Operand,\r
- IN UINTN Count\r
+ IN UINT64 Operand,\r
+ IN UINTN Count\r
)\r
{\r
ASSERT (Count < 64);\r
\r
#include "BaseLibInternals.h"\r
\r
-extern VOID RiscVCpuBreakpoint (VOID);\r
+extern VOID\r
+RiscVCpuBreakpoint (\r
+ VOID\r
+ );\r
\r
/**\r
Generates a breakpoint on the CPU.\r
\r
#include "BaseLibInternals.h"\r
\r
-extern VOID RiscVCpuPause (VOID);\r
-\r
+extern VOID\r
+RiscVCpuPause (\r
+ VOID\r
+ );\r
\r
/**\r
Requests CPU to pause for a short period of time.\r
{\r
RiscVCpuPause ();\r
}\r
-\r
**/\r
#include "BaseLibInternals.h"\r
\r
-extern VOID RiscVDisableSupervisorModeInterrupts (VOID);\r
+extern VOID\r
+RiscVDisableSupervisorModeInterrupts (\r
+ VOID\r
+ );\r
\r
/**\r
Disables CPU interrupts.\r
{\r
RiscVDisableSupervisorModeInterrupts ();\r
}\r
-\r
\r
#include "BaseLibInternals.h"\r
\r
-extern VOID RiscVEnableSupervisorModeInterrupt (VOID);\r
+extern VOID\r
+RiscVEnableSupervisorModeInterrupt (\r
+ VOID\r
+ );\r
\r
/**\r
Enables CPU interrupts.\r
{\r
RiscVEnableSupervisorModeInterrupt ();\r
}\r
-\r
\r
#include "BaseLibInternals.h"\r
\r
-extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);\r
+extern UINT32\r
+RiscVGetSupervisorModeInterrupts (\r
+ VOID\r
+ );\r
\r
/**\r
Retrieves the current CPU interrupt state.\r
VOID\r
)\r
{\r
- unsigned long RetValue;\r
+ unsigned long RetValue;\r
\r
RetValue = RiscVGetSupervisorModeInterrupts ();\r
- return RetValue? TRUE: FALSE;\r
+ return RetValue ? TRUE : FALSE;\r
}\r
-\r
-\r
{\r
BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
\r
- DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \\r
- EntryPoint, Context1, Context2, NewStack));\r
+ DEBUG ((\r
+ DEBUG_INFO,\r
+ "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \\r
+ EntryPoint,\r
+ Context1,\r
+ Context2,\r
+ NewStack\r
+ ));\r
JumpBuffer.RA = (UINTN)EntryPoint;\r
JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);\r
JumpBuffer.S0 = (UINT64)(UINTN)Context1;\r
JumpBuffer.S1 = (UINT64)(UINTN)Context2;\r
LongJump (&JumpBuffer, (UINTN)-1);\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
}\r
**/\r
BOOLEAN\r
InternalSafeStringIsOverlap (\r
- IN VOID *Base1,\r
- IN UINTN Size1,\r
- IN VOID *Base2,\r
- IN UINTN Size2\r
+ IN VOID *Base1,\r
+ IN UINTN Size1,\r
+ IN VOID *Base2,\r
+ IN UINTN Size2\r
)\r
{\r
if ((((UINTN)Base1 >= (UINTN)Base2) && ((UINTN)Base1 < (UINTN)Base2 + Size2)) ||\r
- (((UINTN)Base2 >= (UINTN)Base1) && ((UINTN)Base2 < (UINTN)Base1 + Size1))) {\r
+ (((UINTN)Base2 >= (UINTN)Base1) && ((UINTN)Base2 < (UINTN)Base1 + Size1)))\r
+ {\r
return TRUE;\r
}\r
+\r
return FALSE;\r
}\r
\r
IN UINTN Size2\r
)\r
{\r
- return !InternalSafeStringIsOverlap (Str1, Size1 * sizeof(CHAR16), Str2, Size2 * sizeof(CHAR16));\r
+ return !InternalSafeStringIsOverlap (Str1, Size1 * sizeof (CHAR16), Str2, Size2 * sizeof (CHAR16));\r
}\r
\r
/**\r
**/\r
BOOLEAN\r
InternalSafeStringNoAsciiStrOverlap (\r
- IN CHAR8 *Str1,\r
- IN UINTN Size1,\r
- IN CHAR8 *Str2,\r
- IN UINTN Size2\r
+ IN CHAR8 *Str1,\r
+ IN UINTN Size1,\r
+ IN CHAR8 *Str2,\r
+ IN UINTN Size2\r
)\r
{\r
return !InternalSafeStringIsOverlap (Str1, Size1, Str2, Size2);\r
UINTN\r
EFIAPI\r
StrnLenS (\r
- IN CONST CHAR16 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN MaxSize\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// If String is a null pointer or MaxSize is 0, then the StrnLenS function returns zero.\r
if (Length >= MaxSize - 1) {\r
return MaxSize;\r
}\r
+\r
Length++;\r
}\r
+\r
return Length;\r
}\r
\r
UINTN\r
EFIAPI\r
StrnSizeS (\r
- IN CONST CHAR16 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN MaxSize\r
)\r
{\r
//\r
RETURN_STATUS\r
EFIAPI\r
StrCpyS (\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
while (*Source != 0) {\r
*(Destination++) = *(Source++);\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
StrnCpyS (\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
+\r
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
//\r
*(Destination++) = *(Source++);\r
SourceLen--;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
StrCatS (\r
- IN OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source\r
+ IN OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source\r
)\r
{\r
- UINTN DestLen;\r
- UINTN CopyLen;\r
- UINTN SourceLen;\r
+ UINTN DestLen;\r
+ UINTN CopyLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrCatS.\r
while (*Source != 0) {\r
*(Destination++) = *(Source++);\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
StrnCatS (\r
- IN OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length\r
+ IN OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length\r
)\r
{\r
- UINTN DestLen;\r
- UINTN CopyLen;\r
- UINTN SourceLen;\r
+ UINTN DestLen;\r
+ UINTN CopyLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// Let CopyLen denote the value DestMax - StrnLenS(Destination, DestMax) upon entry to StrnCatS.\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
+\r
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoStrOverlap (Destination, DestMax, (CHAR16 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
//\r
*(Destination++) = *(Source++);\r
SourceLen--;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
StrDecimalToUintnS (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
)\r
{\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. Neither String nor Data shall be a null pointer.\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
\r
//\r
if (*Data > ((MAX_UINTN - (*String - L'0')) / 10)) {\r
*Data = MAX_UINTN;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
StrDecimalToUint64S (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
)\r
{\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. Neither String nor Data shall be a null pointer.\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
\r
//\r
if (*Data > DivU64x32 (MAX_UINT64 - (*String - L'0'), 10)) {\r
*Data = MAX_UINT64;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
StrHexToUintnS (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
)\r
{\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. Neither String nor Data shall be a null pointer.\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
\r
//\r
*Data = 0;\r
return RETURN_SUCCESS;\r
}\r
+\r
//\r
// Skip the 'X'\r
//\r
if (*Data > ((MAX_UINTN - InternalHexCharToUintn (*String)) >> 4)) {\r
*Data = MAX_UINTN;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
StrHexToUint64S (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
)\r
{\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. Neither String nor Data shall be a null pointer.\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
\r
//\r
*Data = 0;\r
return RETURN_SUCCESS;\r
}\r
+\r
//\r
// Skip the 'X'\r
//\r
if (*Data > RShiftU64 (MAX_UINT64 - InternalHexCharToUintn (*String), 4)) {\r
*Data = MAX_UINT64;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) String;\r
+ *EndPointer = (CHAR16 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
StrToIpv6Address (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT IPv6_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT IPv6_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN AddressIndex;\r
- UINTN Uintn;\r
- IPv6_ADDRESS LocalAddress;\r
- UINT8 LocalPrefixLength;\r
- CONST CHAR16 *Pointer;\r
- CHAR16 *End;\r
- UINTN CompressStart;\r
- BOOLEAN ExpectPrefix;\r
+ RETURN_STATUS Status;\r
+ UINTN AddressIndex;\r
+ UINTN Uintn;\r
+ IPv6_ADDRESS LocalAddress;\r
+ UINT8 LocalPrefixLength;\r
+ CONST CHAR16 *Pointer;\r
+ CHAR16 *End;\r
+ UINTN CompressStart;\r
+ BOOLEAN ExpectPrefix;\r
\r
LocalPrefixLength = MAX_UINT8;\r
CompressStart = ARRAY_SIZE (Address->Addr);\r
ExpectPrefix = FALSE;\r
\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. None of String or Guid shall be a null pointer.\r
return RETURN_UNSUPPORTED;\r
}\r
\r
- if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {\r
+ if ((CompressStart != ARRAY_SIZE (Address->Addr)) || (AddressIndex == ARRAY_SIZE (Address->Addr))) {\r
//\r
// "::" can only appear once.\r
// "::" can only appear when address is not full length.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
Pointer++;\r
}\r
}\r
// Get X.\r
//\r
Status = StrHexToUintnS (Pointer, &End, &Uintn);\r
- if (RETURN_ERROR (Status) || End - Pointer > 4) {\r
+ if (RETURN_ERROR (Status) || (End - Pointer > 4)) {\r
//\r
// Number of hexadecimal digit characters is no more than 4.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
Pointer = End;\r
//\r
// Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.\r
//\r
ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));\r
- LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);\r
- LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;\r
- AddressIndex += 2;\r
+ LocalAddress.Addr[AddressIndex] = (UINT8)((UINT16)Uintn >> 8);\r
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8)Uintn;\r
+ AddressIndex += 2;\r
} else {\r
//\r
// Get P, then exit the loop.\r
//\r
Status = StrDecimalToUintnS (Pointer, &End, &Uintn);\r
- if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {\r
+ if (RETURN_ERROR (Status) || (End == Pointer) || (Uintn > 128)) {\r
//\r
// Prefix length should not exceed 128.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalPrefixLength = (UINT8) Uintn;\r
- Pointer = End;\r
+\r
+ LocalPrefixLength = (UINT8)Uintn;\r
+ Pointer = End;\r
break;\r
}\r
}\r
//\r
break;\r
}\r
+\r
Pointer++;\r
}\r
\r
- if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||\r
- (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))\r
- ) {\r
+ if (((AddressIndex == ARRAY_SIZE (Address->Addr)) && (CompressStart != ARRAY_SIZE (Address->Addr))) ||\r
+ ((AddressIndex != ARRAY_SIZE (Address->Addr)) && (CompressStart == ARRAY_SIZE (Address->Addr)))\r
+ )\r
+ {\r
//\r
// Full length of address shall not have compressing zeros.\r
// Non-full length of address shall have compressing zeros.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);\r
ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);\r
if (AddressIndex > CompressStart) {\r
if (PrefixLength != NULL) {\r
*PrefixLength = LocalPrefixLength;\r
}\r
+\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR16 *) Pointer;\r
+ *EndPointer = (CHAR16 *)Pointer;\r
}\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
StrToIpv4Address (\r
- IN CONST CHAR16 *String,\r
- OUT CHAR16 **EndPointer OPTIONAL,\r
- OUT IPv4_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR16 *String,\r
+ OUT CHAR16 **EndPointer OPTIONAL,\r
+ OUT IPv4_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN AddressIndex;\r
- UINTN Uintn;\r
- IPv4_ADDRESS LocalAddress;\r
- UINT8 LocalPrefixLength;\r
- CHAR16 *Pointer;\r
+ RETURN_STATUS Status;\r
+ UINTN AddressIndex;\r
+ UINTN Uintn;\r
+ IPv4_ADDRESS LocalAddress;\r
+ UINT8 LocalPrefixLength;\r
+ CHAR16 *Pointer;\r
\r
LocalPrefixLength = MAX_UINT8;\r
\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. None of String or Guid shall be a null pointer.\r
SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);\r
\r
- for (Pointer = (CHAR16 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {\r
+ for (Pointer = (CHAR16 *)String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {\r
if (!InternalIsDecimalDigitCharacter (*Pointer)) {\r
//\r
// D or P contains invalid characters.\r
//\r
// Get D or P.\r
//\r
- Status = StrDecimalToUintnS ((CONST CHAR16 *) Pointer, &Pointer, &Uintn);\r
+ Status = StrDecimalToUintnS ((CONST CHAR16 *)Pointer, &Pointer, &Uintn);\r
if (RETURN_ERROR (Status)) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if (AddressIndex == ARRAY_SIZE (Address->Addr)) {\r
//\r
// It's P.\r
if (Uintn > 32) {\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalPrefixLength = (UINT8) Uintn;\r
+\r
+ LocalPrefixLength = (UINT8)Uintn;\r
} else {\r
//\r
// It's D.\r
if (Uintn > MAX_UINT8) {\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;\r
+\r
+ LocalAddress.Addr[AddressIndex] = (UINT8)Uintn;\r
AddressIndex++;\r
}\r
\r
if (PrefixLength != NULL) {\r
*PrefixLength = LocalPrefixLength;\r
}\r
+\r
if (EndPointer != NULL) {\r
*EndPointer = Pointer;\r
}\r
RETURN_STATUS\r
EFIAPI\r
StrToGuid (\r
- IN CONST CHAR16 *String,\r
- OUT GUID *Guid\r
+ IN CONST CHAR16 *String,\r
+ OUT GUID *Guid\r
)\r
{\r
- RETURN_STATUS Status;\r
- GUID LocalGuid;\r
+ RETURN_STATUS Status;\r
+ GUID LocalGuid;\r
\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. None of String or Guid shall be a null pointer.\r
//\r
// Get aabbccdd in big-endian.\r
//\r
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != L'-') {\r
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *)&LocalGuid.Data1, sizeof (LocalGuid.Data1));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data1)] != L'-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);\r
- String += 2 * sizeof (LocalGuid.Data1) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data1) + 1;\r
\r
//\r
// Get eeff in big-endian.\r
//\r
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != L'-') {\r
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *)&LocalGuid.Data2, sizeof (LocalGuid.Data2));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data2)] != L'-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);\r
- String += 2 * sizeof (LocalGuid.Data2) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data2) + 1;\r
\r
//\r
// Get gghh in big-endian.\r
//\r
- Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != L'-') {\r
+ Status = StrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *)&LocalGuid.Data3, sizeof (LocalGuid.Data3));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data3)] != L'-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);\r
- String += 2 * sizeof (LocalGuid.Data3) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data3) + 1;\r
\r
//\r
// Get iijj.\r
//\r
Status = StrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);\r
- if (RETURN_ERROR (Status) || String[2 * 2] != L'-') {\r
+ if (RETURN_ERROR (Status) || (String[2 * 2] != L'-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
String += 2 * 2 + 1;\r
\r
//\r
RETURN_STATUS\r
EFIAPI\r
StrHexToBytes (\r
- IN CONST CHAR16 *String,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer,\r
- IN UINTN MaxBufferSize\r
+ IN CONST CHAR16 *String,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN MaxBufferSize\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
//\r
// 1. None of String or Buffer shall be a null pointer.\r
break;\r
}\r
}\r
+\r
if (Index != Length) {\r
return RETURN_UNSUPPORTED;\r
}\r
//\r
// Convert the hex string to bytes.\r
//\r
- for(Index = 0; Index < Length; Index++) {\r
-\r
+ for (Index = 0; Index < Length; Index++) {\r
//\r
// For even characters, write the upper nibble for each buffer byte,\r
// and for even characters, the lower nibble.\r
//\r
if ((Index & BIT0) == 0) {\r
- Buffer[Index / 2] = (UINT8) InternalHexCharToUintn (String[Index]) << 4;\r
+ Buffer[Index / 2] = (UINT8)InternalHexCharToUintn (String[Index]) << 4;\r
} else {\r
- Buffer[Index / 2] |= (UINT8) InternalHexCharToUintn (String[Index]);\r
+ Buffer[Index / 2] |= (UINT8)InternalHexCharToUintn (String[Index]);\r
}\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
UINTN\r
EFIAPI\r
AsciiStrnLenS (\r
- IN CONST CHAR8 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN MaxSize\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
//\r
// If String is a null pointer or MaxSize is 0, then the AsciiStrnLenS function returns zero.\r
if (Length >= MaxSize - 1) {\r
return MaxSize;\r
}\r
+\r
Length++;\r
}\r
+\r
return Length;\r
}\r
\r
UINTN\r
EFIAPI\r
AsciiStrnSizeS (\r
- IN CONST CHAR8 *String,\r
- IN UINTN MaxSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN MaxSize\r
)\r
{\r
//\r
IN CONST CHAR8 *Source\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
while (*Source != 0) {\r
*(Destination++) = *(Source++);\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
IN UINTN Length\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
+\r
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
//\r
*(Destination++) = *(Source++);\r
SourceLen--;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
IN CONST CHAR8 *Source\r
)\r
{\r
- UINTN DestLen;\r
- UINTN CopyLen;\r
- UINTN SourceLen;\r
+ UINTN DestLen;\r
+ UINTN CopyLen;\r
+ UINTN SourceLen;\r
\r
//\r
// Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrCatS.\r
while (*Source != 0) {\r
*(Destination++) = *(Source++);\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
IN UINTN Length\r
)\r
{\r
- UINTN DestLen;\r
- UINTN CopyLen;\r
- UINTN SourceLen;\r
+ UINTN DestLen;\r
+ UINTN CopyLen;\r
+ UINTN SourceLen;\r
\r
//\r
// Let CopyLen denote the value DestMax - AsciiStrnLenS(Destination, DestMax) upon entry to AsciiStrnCatS.\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
+\r
SAFE_STRING_CONSTRAINT_CHECK (InternalSafeStringNoAsciiStrOverlap (Destination, DestMax, (CHAR8 *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
//\r
*(Destination++) = *(Source++);\r
SourceLen--;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrDecimalToUintnS (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
)\r
{\r
//\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
\r
//\r
if (*Data > ((MAX_UINTN - (*String - '0')) / 10)) {\r
*Data = MAX_UINTN;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrDecimalToUint64S (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
)\r
{\r
//\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
\r
//\r
if (*Data > DivU64x32 (MAX_UINT64 - (*String - '0'), 10)) {\r
*Data = MAX_UINT64;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToUintnS (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINTN *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINTN *Data\r
)\r
{\r
//\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
\r
//\r
*Data = 0;\r
return RETURN_SUCCESS;\r
}\r
+\r
//\r
// Skip the 'X'\r
//\r
if (*Data > ((MAX_UINTN - InternalAsciiHexCharToUintn (*String)) >> 4)) {\r
*Data = MAX_UINTN;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToUint64S (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT UINT64 *Data\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT UINT64 *Data\r
)\r
{\r
//\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
\r
//\r
*Data = 0;\r
return RETURN_SUCCESS;\r
}\r
+\r
//\r
// Skip the 'X'\r
//\r
if (*Data > RShiftU64 (MAX_UINT64 - InternalAsciiHexCharToUintn (*String), 4)) {\r
*Data = MAX_UINT64;\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_UNSUPPORTED;\r
}\r
\r
}\r
\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) String;\r
+ *EndPointer = (CHAR8 *)String;\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
RETURN_STATUS\r
EFIAPI\r
UnicodeStrToAsciiStrS (\r
- IN CONST CHAR16 *Source,\r
- OUT CHAR8 *Destination,\r
- IN UINTN DestMax\r
+ IN CONST CHAR16 *Source,\r
+ OUT CHAR8 *Destination,\r
+ IN UINTN DestMax\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
if (ASCII_RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
+\r
if (RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
//\r
// 5. Copying shall not take place between objects that overlap.\r
//\r
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);\r
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof (CHAR16)), RETURN_ACCESS_DENIED);\r
\r
//\r
// convert string\r
// non-zero value in the upper 8 bits, then ASSERT().\r
//\r
ASSERT (*Source < 0x100);\r
- *(Destination++) = (CHAR8) *(Source++);\r
+ *(Destination++) = (CHAR8)*(Source++);\r
}\r
+\r
*Destination = '\0';\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
UnicodeStrnToAsciiStrS (\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Length,\r
- OUT CHAR8 *Destination,\r
- IN UINTN DestMax,\r
- OUT UINTN *DestinationLength\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Length,\r
+ OUT CHAR8 *Destination,\r
+ IN UINTN DestMax,\r
+ OUT UINTN *DestinationLength\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Source & BIT0) == 0);\r
+ ASSERT (((UINTN)Source & BIT0) == 0);\r
\r
//\r
// 1. None of Destination, Source or DestinationLength shall be a null\r
SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
+\r
if (RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof(CHAR16)), RETURN_ACCESS_DENIED);\r
+\r
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax, (VOID *)Source, (SourceLen + 1) * sizeof (CHAR16)), RETURN_ACCESS_DENIED);\r
\r
*DestinationLength = 0;\r
\r
// 8 bits, then ASSERT().\r
//\r
ASSERT (*Source < 0x100);\r
- *(Destination++) = (CHAR8) *(Source++);\r
+ *(Destination++) = (CHAR8)*(Source++);\r
SourceLen--;\r
(*DestinationLength)++;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToUnicodeStrS (\r
- IN CONST CHAR8 *Source,\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax\r
+ IN CONST CHAR8 *Source,\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
\r
//\r
// 1. Neither Destination nor Source shall be a null pointer.\r
if (RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
+\r
if (ASCII_RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
//\r
// 5. Copying shall not take place between objects that overlap.\r
//\r
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof (CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
//\r
// Convert string\r
while (*Source != '\0') {\r
*(Destination++) = (CHAR16)(UINT8)*(Source++);\r
}\r
+\r
*Destination = '\0';\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrnToUnicodeStrS (\r
- IN CONST CHAR8 *Source,\r
- IN UINTN Length,\r
- OUT CHAR16 *Destination,\r
- IN UINTN DestMax,\r
- OUT UINTN *DestinationLength\r
+ IN CONST CHAR8 *Source,\r
+ IN UINTN Length,\r
+ OUT CHAR16 *Destination,\r
+ IN UINTN DestMax,\r
+ OUT UINTN *DestinationLength\r
)\r
{\r
- UINTN SourceLen;\r
+ UINTN SourceLen;\r
\r
- ASSERT (((UINTN) Destination & BIT0) == 0);\r
+ ASSERT (((UINTN)Destination & BIT0) == 0);\r
\r
//\r
// 1. None of Destination, Source or DestinationLength shall be a null\r
SAFE_STRING_CONSTRAINT_CHECK ((Length <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
}\r
+\r
if (ASCII_RSIZE_MAX != 0) {\r
SAFE_STRING_CONSTRAINT_CHECK ((Length <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((DestMax <= ASCII_RSIZE_MAX), RETURN_INVALID_PARAMETER);\r
if (SourceLen > Length) {\r
SourceLen = Length;\r
}\r
- SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof(CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
+\r
+ SAFE_STRING_CONSTRAINT_CHECK (!InternalSafeStringIsOverlap (Destination, DestMax * sizeof (CHAR16), (VOID *)Source, SourceLen + 1), RETURN_ACCESS_DENIED);\r
\r
*DestinationLength = 0;\r
\r
SourceLen--;\r
(*DestinationLength)++;\r
}\r
+\r
*Destination = 0;\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToIpv6Address (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT IPv6_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT IPv6_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN AddressIndex;\r
- UINTN Uintn;\r
- IPv6_ADDRESS LocalAddress;\r
- UINT8 LocalPrefixLength;\r
- CONST CHAR8 *Pointer;\r
- CHAR8 *End;\r
- UINTN CompressStart;\r
- BOOLEAN ExpectPrefix;\r
+ RETURN_STATUS Status;\r
+ UINTN AddressIndex;\r
+ UINTN Uintn;\r
+ IPv6_ADDRESS LocalAddress;\r
+ UINT8 LocalPrefixLength;\r
+ CONST CHAR8 *Pointer;\r
+ CHAR8 *End;\r
+ UINTN CompressStart;\r
+ BOOLEAN ExpectPrefix;\r
\r
LocalPrefixLength = MAX_UINT8;\r
CompressStart = ARRAY_SIZE (Address->Addr);\r
return RETURN_UNSUPPORTED;\r
}\r
\r
- if (CompressStart != ARRAY_SIZE (Address->Addr) || AddressIndex == ARRAY_SIZE (Address->Addr)) {\r
+ if ((CompressStart != ARRAY_SIZE (Address->Addr)) || (AddressIndex == ARRAY_SIZE (Address->Addr))) {\r
//\r
// "::" can only appear once.\r
// "::" can only appear when address is not full length.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
Pointer++;\r
}\r
}\r
// Get X.\r
//\r
Status = AsciiStrHexToUintnS (Pointer, &End, &Uintn);\r
- if (RETURN_ERROR (Status) || End - Pointer > 4) {\r
+ if (RETURN_ERROR (Status) || (End - Pointer > 4)) {\r
//\r
// Number of hexadecimal digit characters is no more than 4.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
Pointer = End;\r
//\r
// Uintn won't exceed MAX_UINT16 if number of hexadecimal digit characters is no more than 4.\r
//\r
ASSERT (AddressIndex + 1 < ARRAY_SIZE (Address->Addr));\r
- LocalAddress.Addr[AddressIndex] = (UINT8) ((UINT16) Uintn >> 8);\r
- LocalAddress.Addr[AddressIndex + 1] = (UINT8) Uintn;\r
- AddressIndex += 2;\r
+ LocalAddress.Addr[AddressIndex] = (UINT8)((UINT16)Uintn >> 8);\r
+ LocalAddress.Addr[AddressIndex + 1] = (UINT8)Uintn;\r
+ AddressIndex += 2;\r
} else {\r
//\r
// Get P, then exit the loop.\r
//\r
Status = AsciiStrDecimalToUintnS (Pointer, &End, &Uintn);\r
- if (RETURN_ERROR (Status) || End == Pointer || Uintn > 128) {\r
+ if (RETURN_ERROR (Status) || (End == Pointer) || (Uintn > 128)) {\r
//\r
// Prefix length should not exceed 128.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalPrefixLength = (UINT8) Uintn;\r
- Pointer = End;\r
+\r
+ LocalPrefixLength = (UINT8)Uintn;\r
+ Pointer = End;\r
break;\r
}\r
}\r
//\r
break;\r
}\r
+\r
Pointer++;\r
}\r
\r
- if ((AddressIndex == ARRAY_SIZE (Address->Addr) && CompressStart != ARRAY_SIZE (Address->Addr)) ||\r
- (AddressIndex != ARRAY_SIZE (Address->Addr) && CompressStart == ARRAY_SIZE (Address->Addr))\r
- ) {\r
+ if (((AddressIndex == ARRAY_SIZE (Address->Addr)) && (CompressStart != ARRAY_SIZE (Address->Addr))) ||\r
+ ((AddressIndex != ARRAY_SIZE (Address->Addr)) && (CompressStart == ARRAY_SIZE (Address->Addr)))\r
+ )\r
+ {\r
//\r
// Full length of address shall not have compressing zeros.\r
// Non-full length of address shall have compressing zeros.\r
//\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
CopyMem (&Address->Addr[0], &LocalAddress.Addr[0], CompressStart);\r
ZeroMem (&Address->Addr[CompressStart], ARRAY_SIZE (Address->Addr) - AddressIndex);\r
if (AddressIndex > CompressStart) {\r
&LocalAddress.Addr[CompressStart],\r
AddressIndex - CompressStart\r
);\r
-\r
}\r
\r
if (PrefixLength != NULL) {\r
*PrefixLength = LocalPrefixLength;\r
}\r
+\r
if (EndPointer != NULL) {\r
- *EndPointer = (CHAR8 *) Pointer;\r
+ *EndPointer = (CHAR8 *)Pointer;\r
}\r
\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToIpv4Address (\r
- IN CONST CHAR8 *String,\r
- OUT CHAR8 **EndPointer OPTIONAL,\r
- OUT IPv4_ADDRESS *Address,\r
- OUT UINT8 *PrefixLength OPTIONAL\r
+ IN CONST CHAR8 *String,\r
+ OUT CHAR8 **EndPointer OPTIONAL,\r
+ OUT IPv4_ADDRESS *Address,\r
+ OUT UINT8 *PrefixLength OPTIONAL\r
)\r
{\r
- RETURN_STATUS Status;\r
- UINTN AddressIndex;\r
- UINTN Uintn;\r
- IPv4_ADDRESS LocalAddress;\r
- UINT8 LocalPrefixLength;\r
- CHAR8 *Pointer;\r
+ RETURN_STATUS Status;\r
+ UINTN AddressIndex;\r
+ UINTN Uintn;\r
+ IPv4_ADDRESS LocalAddress;\r
+ UINT8 LocalPrefixLength;\r
+ CHAR8 *Pointer;\r
\r
LocalPrefixLength = MAX_UINT8;\r
\r
SAFE_STRING_CONSTRAINT_CHECK ((String != NULL), RETURN_INVALID_PARAMETER);\r
SAFE_STRING_CONSTRAINT_CHECK ((Address != NULL), RETURN_INVALID_PARAMETER);\r
\r
- for (Pointer = (CHAR8 *) String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {\r
+ for (Pointer = (CHAR8 *)String, AddressIndex = 0; AddressIndex < ARRAY_SIZE (Address->Addr) + 1;) {\r
if (!InternalAsciiIsDecimalDigitCharacter (*Pointer)) {\r
//\r
// D or P contains invalid characters.\r
//\r
// Get D or P.\r
//\r
- Status = AsciiStrDecimalToUintnS ((CONST CHAR8 *) Pointer, &Pointer, &Uintn);\r
+ Status = AsciiStrDecimalToUintnS ((CONST CHAR8 *)Pointer, &Pointer, &Uintn);\r
if (RETURN_ERROR (Status)) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if (AddressIndex == ARRAY_SIZE (Address->Addr)) {\r
//\r
// It's P.\r
if (Uintn > 32) {\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalPrefixLength = (UINT8) Uintn;\r
+\r
+ LocalPrefixLength = (UINT8)Uintn;\r
} else {\r
//\r
// It's D.\r
if (Uintn > MAX_UINT8) {\r
return RETURN_UNSUPPORTED;\r
}\r
- LocalAddress.Addr[AddressIndex] = (UINT8) Uintn;\r
+\r
+ LocalAddress.Addr[AddressIndex] = (UINT8)Uintn;\r
AddressIndex++;\r
}\r
\r
if (PrefixLength != NULL) {\r
*PrefixLength = LocalPrefixLength;\r
}\r
+\r
if (EndPointer != NULL) {\r
*EndPointer = Pointer;\r
}\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrToGuid (\r
- IN CONST CHAR8 *String,\r
- OUT GUID *Guid\r
+ IN CONST CHAR8 *String,\r
+ OUT GUID *Guid\r
)\r
{\r
- RETURN_STATUS Status;\r
- GUID LocalGuid;\r
+ RETURN_STATUS Status;\r
+ GUID LocalGuid;\r
\r
//\r
// None of String or Guid shall be a null pointer.\r
//\r
// Get aabbccdd in big-endian.\r
//\r
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *) &LocalGuid.Data1, sizeof (LocalGuid.Data1));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data1)] != '-') {\r
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data1), (UINT8 *)&LocalGuid.Data1, sizeof (LocalGuid.Data1));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data1)] != '-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data1 = SwapBytes32 (LocalGuid.Data1);\r
- String += 2 * sizeof (LocalGuid.Data1) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data1) + 1;\r
\r
//\r
// Get eeff in big-endian.\r
//\r
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *) &LocalGuid.Data2, sizeof (LocalGuid.Data2));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data2)] != '-') {\r
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data2), (UINT8 *)&LocalGuid.Data2, sizeof (LocalGuid.Data2));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data2)] != '-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data2 = SwapBytes16 (LocalGuid.Data2);\r
- String += 2 * sizeof (LocalGuid.Data2) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data2) + 1;\r
\r
//\r
// Get gghh in big-endian.\r
//\r
- Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *) &LocalGuid.Data3, sizeof (LocalGuid.Data3));\r
- if (RETURN_ERROR (Status) || String[2 * sizeof (LocalGuid.Data3)] != '-') {\r
+ Status = AsciiStrHexToBytes (String, 2 * sizeof (LocalGuid.Data3), (UINT8 *)&LocalGuid.Data3, sizeof (LocalGuid.Data3));\r
+ if (RETURN_ERROR (Status) || (String[2 * sizeof (LocalGuid.Data3)] != '-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// Convert big-endian to little-endian.\r
//\r
LocalGuid.Data3 = SwapBytes16 (LocalGuid.Data3);\r
- String += 2 * sizeof (LocalGuid.Data3) + 1;\r
+ String += 2 * sizeof (LocalGuid.Data3) + 1;\r
\r
//\r
// Get iijj.\r
//\r
Status = AsciiStrHexToBytes (String, 2 * 2, &LocalGuid.Data4[0], 2);\r
- if (RETURN_ERROR (Status) || String[2 * 2] != '-') {\r
+ if (RETURN_ERROR (Status) || (String[2 * 2] != '-')) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
String += 2 * 2 + 1;\r
\r
//\r
RETURN_STATUS\r
EFIAPI\r
AsciiStrHexToBytes (\r
- IN CONST CHAR8 *String,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer,\r
- IN UINTN MaxBufferSize\r
+ IN CONST CHAR8 *String,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN MaxBufferSize\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
//\r
// 1. None of String or Buffer shall be a null pointer.\r
break;\r
}\r
}\r
+\r
if (Index != Length) {\r
return RETURN_UNSUPPORTED;\r
}\r
//\r
// Convert the hex string to bytes.\r
//\r
- for(Index = 0; Index < Length; Index++) {\r
-\r
+ for (Index = 0; Index < Length; Index++) {\r
//\r
// For even characters, write the upper nibble for each buffer byte,\r
// and for even characters, the lower nibble.\r
//\r
if ((Index & BIT0) == 0) {\r
- Buffer[Index / 2] = (UINT8) InternalAsciiHexCharToUintn (String[Index]) << 4;\r
+ Buffer[Index / 2] = (UINT8)InternalAsciiHexCharToUintn (String[Index]) << 4;\r
} else {\r
- Buffer[Index / 2] |= (UINT8) InternalAsciiHexCharToUintn (String[Index]);\r
+ Buffer[Index / 2] |= (UINT8)InternalAsciiHexCharToUintn (String[Index]);\r
}\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Returns the length of a Null-terminated Unicode string.\r
\r
UINTN\r
EFIAPI\r
StrLen (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
ASSERT (String != NULL);\r
- ASSERT (((UINTN) String & BIT0) == 0);\r
+ ASSERT (((UINTN)String & BIT0) == 0);\r
\r
for (Length = 0; *String != L'\0'; String++, Length++) {\r
//\r
ASSERT (Length < PcdGet32 (PcdMaximumUnicodeStringLength));\r
}\r
}\r
+\r
return Length;\r
}\r
\r
UINTN\r
EFIAPI\r
StrSize (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
return (StrLen (String) + 1) * sizeof (*String);\r
INTN\r
EFIAPI\r
StrCmp (\r
- IN CONST CHAR16 *FirstString,\r
- IN CONST CHAR16 *SecondString\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString\r
)\r
{\r
//\r
FirstString++;\r
SecondString++;\r
}\r
+\r
return *FirstString - *SecondString;\r
}\r
\r
INTN\r
EFIAPI\r
StrnCmp (\r
- IN CONST CHAR16 *FirstString,\r
- IN CONST CHAR16 *SecondString,\r
- IN UINTN Length\r
+ IN CONST CHAR16 *FirstString,\r
+ IN CONST CHAR16 *SecondString,\r
+ IN UINTN Length\r
)\r
{\r
if (Length == 0) {\r
while ((*FirstString != L'\0') &&\r
(*SecondString != L'\0') &&\r
(*FirstString == *SecondString) &&\r
- (Length > 1)) {\r
+ (Length > 1))\r
+ {\r
FirstString++;\r
SecondString++;\r
Length--;\r
return *FirstString - *SecondString;\r
}\r
\r
-\r
/**\r
Returns the first occurrence of a Null-terminated Unicode sub-string\r
in a Null-terminated Unicode string.\r
CHAR16 *\r
EFIAPI\r
StrStr (\r
- IN CONST CHAR16 *String,\r
- IN CONST CHAR16 *SearchString\r
+ IN CONST CHAR16 *String,\r
+ IN CONST CHAR16 *SearchString\r
)\r
{\r
- CONST CHAR16 *FirstMatch;\r
- CONST CHAR16 *SearchStringTmp;\r
+ CONST CHAR16 *FirstMatch;\r
+ CONST CHAR16 *SearchStringTmp;\r
\r
//\r
// ASSERT both strings are less long than PcdMaximumUnicodeStringLength.\r
ASSERT (StrSize (SearchString) != 0);\r
\r
if (*SearchString == L'\0') {\r
- return (CHAR16 *) String;\r
+ return (CHAR16 *)String;\r
}\r
\r
while (*String != L'\0') {\r
SearchStringTmp = SearchString;\r
- FirstMatch = String;\r
+ FirstMatch = String;\r
\r
- while ((*String == *SearchStringTmp)\r
- && (*String != L'\0')) {\r
+ while ( (*String == *SearchStringTmp)\r
+ && (*String != L'\0'))\r
+ {\r
String++;\r
SearchStringTmp++;\r
}\r
\r
if (*SearchStringTmp == L'\0') {\r
- return (CHAR16 *) FirstMatch;\r
+ return (CHAR16 *)FirstMatch;\r
}\r
\r
if (*String == L'\0') {\r
BOOLEAN\r
EFIAPI\r
InternalIsDecimalDigitCharacter (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
)\r
{\r
- return (BOOLEAN) (Char >= L'0' && Char <= L'9');\r
+ return (BOOLEAN)(Char >= L'0' && Char <= L'9');\r
}\r
\r
/**\r
CHAR16\r
EFIAPI\r
CharToUpper (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
)\r
{\r
- if (Char >= L'a' && Char <= L'z') {\r
- return (CHAR16) (Char - (L'a' - L'A'));\r
+ if ((Char >= L'a') && (Char <= L'z')) {\r
+ return (CHAR16)(Char - (L'a' - L'A'));\r
}\r
\r
return Char;\r
UINTN\r
EFIAPI\r
InternalHexCharToUintn (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
)\r
{\r
if (InternalIsDecimalDigitCharacter (Char)) {\r
BOOLEAN\r
EFIAPI\r
InternalIsHexaDecimalDigitCharacter (\r
- IN CHAR16 Char\r
+ IN CHAR16 Char\r
)\r
{\r
-\r
- return (BOOLEAN) (InternalIsDecimalDigitCharacter (Char) ||\r
- (Char >= L'A' && Char <= L'F') ||\r
- (Char >= L'a' && Char <= L'f'));\r
+ return (BOOLEAN)(InternalIsDecimalDigitCharacter (Char) ||\r
+ (Char >= L'A' && Char <= L'F') ||\r
+ (Char >= L'a' && Char <= L'f'));\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
StrDecimalToUintn (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
- UINTN Result;\r
+ UINTN Result;\r
\r
- StrDecimalToUintnS (String, (CHAR16 **) NULL, &Result);\r
+ StrDecimalToUintnS (String, (CHAR16 **)NULL, &Result);\r
return Result;\r
}\r
\r
-\r
/**\r
Convert a Null-terminated Unicode decimal string to a value of\r
type UINT64.\r
UINT64\r
EFIAPI\r
StrDecimalToUint64 (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
- StrDecimalToUint64S (String, (CHAR16 **) NULL, &Result);\r
+ StrDecimalToUint64S (String, (CHAR16 **)NULL, &Result);\r
return Result;\r
}\r
\r
UINTN\r
EFIAPI\r
StrHexToUintn (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
- UINTN Result;\r
+ UINTN Result;\r
\r
- StrHexToUintnS (String, (CHAR16 **) NULL, &Result);\r
+ StrHexToUintnS (String, (CHAR16 **)NULL, &Result);\r
return Result;\r
}\r
\r
-\r
/**\r
Convert a Null-terminated Unicode hexadecimal string to a value of type UINT64.\r
\r
UINT64\r
EFIAPI\r
StrHexToUint64 (\r
- IN CONST CHAR16 *String\r
+ IN CONST CHAR16 *String\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
- StrHexToUint64S (String, (CHAR16 **) NULL, &Result);\r
+ StrHexToUint64S (String, (CHAR16 **)NULL, &Result);\r
return Result;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
InternalAsciiIsDecimalDigitCharacter (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
)\r
{\r
- return (BOOLEAN) (Char >= '0' && Char <= '9');\r
+ return (BOOLEAN)(Char >= '0' && Char <= '9');\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
InternalAsciiIsHexaDecimalDigitCharacter (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
)\r
{\r
-\r
- return (BOOLEAN) (InternalAsciiIsDecimalDigitCharacter (Char) ||\r
- (Char >= 'A' && Char <= 'F') ||\r
- (Char >= 'a' && Char <= 'f'));\r
+ return (BOOLEAN)(InternalAsciiIsDecimalDigitCharacter (Char) ||\r
+ (Char >= 'A' && Char <= 'F') ||\r
+ (Char >= 'a' && Char <= 'f'));\r
}\r
\r
-\r
/**\r
Returns the length of a Null-terminated ASCII string.\r
\r
UINTN\r
EFIAPI\r
AsciiStrLen (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
ASSERT (String != NULL);\r
\r
ASSERT (Length < PcdGet32 (PcdMaximumAsciiStringLength));\r
}\r
}\r
+\r
return Length;\r
}\r
\r
UINTN\r
EFIAPI\r
AsciiStrSize (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
return (AsciiStrLen (String) + 1) * sizeof (*String);\r
INTN\r
EFIAPI\r
AsciiStrCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
)\r
{\r
//\r
CHAR8\r
EFIAPI\r
AsciiCharToUpper (\r
- IN CHAR8 Chr\r
+ IN CHAR8 Chr\r
)\r
{\r
- return (UINT8) ((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);\r
+ return (UINT8)((Chr >= 'a' && Chr <= 'z') ? Chr - ('a' - 'A') : Chr);\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
InternalAsciiHexCharToUintn (\r
- IN CHAR8 Char\r
+ IN CHAR8 Char\r
)\r
{\r
if (InternalIsDecimalDigitCharacter (Char)) {\r
return (10 + AsciiCharToUpper (Char) - 'A');\r
}\r
\r
-\r
/**\r
Performs a case insensitive comparison of two Null-terminated ASCII strings,\r
and returns the difference between the first mismatched ASCII characters.\r
INTN\r
EFIAPI\r
AsciiStriCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString\r
)\r
{\r
CHAR8 UpperFirstString;\r
INTN\r
EFIAPI\r
AsciiStrnCmp (\r
- IN CONST CHAR8 *FirstString,\r
- IN CONST CHAR8 *SecondString,\r
- IN UINTN Length\r
+ IN CONST CHAR8 *FirstString,\r
+ IN CONST CHAR8 *SecondString,\r
+ IN UINTN Length\r
)\r
{\r
if (Length == 0) {\r
while ((*FirstString != '\0') &&\r
(*SecondString != '\0') &&\r
(*FirstString == *SecondString) &&\r
- (Length > 1)) {\r
+ (Length > 1))\r
+ {\r
FirstString++;\r
SecondString++;\r
Length--;\r
}\r
+\r
return *FirstString - *SecondString;\r
}\r
\r
-\r
/**\r
Returns the first occurrence of a Null-terminated ASCII sub-string\r
in a Null-terminated ASCII string.\r
CHAR8 *\r
EFIAPI\r
AsciiStrStr (\r
- IN CONST CHAR8 *String,\r
- IN CONST CHAR8 *SearchString\r
+ IN CONST CHAR8 *String,\r
+ IN CONST CHAR8 *SearchString\r
)\r
{\r
- CONST CHAR8 *FirstMatch;\r
- CONST CHAR8 *SearchStringTmp;\r
+ CONST CHAR8 *FirstMatch;\r
+ CONST CHAR8 *SearchStringTmp;\r
\r
//\r
// ASSERT both strings are less long than PcdMaximumAsciiStringLength\r
ASSERT (AsciiStrSize (SearchString) != 0);\r
\r
if (*SearchString == '\0') {\r
- return (CHAR8 *) String;\r
+ return (CHAR8 *)String;\r
}\r
\r
while (*String != '\0') {\r
SearchStringTmp = SearchString;\r
- FirstMatch = String;\r
+ FirstMatch = String;\r
\r
- while ((*String == *SearchStringTmp)\r
- && (*String != '\0')) {\r
+ while ( (*String == *SearchStringTmp)\r
+ && (*String != '\0'))\r
+ {\r
String++;\r
SearchStringTmp++;\r
}\r
\r
if (*SearchStringTmp == '\0') {\r
- return (CHAR8 *) FirstMatch;\r
+ return (CHAR8 *)FirstMatch;\r
}\r
\r
if (*String == '\0') {\r
UINTN\r
EFIAPI\r
AsciiStrDecimalToUintn (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
- UINTN Result;\r
+ UINTN Result;\r
\r
- AsciiStrDecimalToUintnS (String, (CHAR8 **) NULL, &Result);\r
+ AsciiStrDecimalToUintnS (String, (CHAR8 **)NULL, &Result);\r
return Result;\r
}\r
\r
-\r
/**\r
Convert a Null-terminated ASCII decimal string to a value of type\r
UINT64.\r
UINT64\r
EFIAPI\r
AsciiStrDecimalToUint64 (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
- AsciiStrDecimalToUint64S (String, (CHAR8 **) NULL, &Result);\r
+ AsciiStrDecimalToUint64S (String, (CHAR8 **)NULL, &Result);\r
return Result;\r
}\r
\r
UINTN\r
EFIAPI\r
AsciiStrHexToUintn (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
- UINTN Result;\r
+ UINTN Result;\r
\r
- AsciiStrHexToUintnS (String, (CHAR8 **) NULL, &Result);\r
+ AsciiStrHexToUintnS (String, (CHAR8 **)NULL, &Result);\r
return Result;\r
}\r
\r
-\r
/**\r
Convert a Null-terminated ASCII hexadecimal string to a value of type UINT64.\r
\r
UINT64\r
EFIAPI\r
AsciiStrHexToUint64 (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
- AsciiStrHexToUint64S (String, (CHAR8 **) NULL, &Result);\r
+ AsciiStrHexToUint64S (String, (CHAR8 **)NULL, &Result);\r
return Result;\r
}\r
\r
-\r
-STATIC CHAR8 EncodingTable[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"\r
+STATIC CHAR8 EncodingTable[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"\r
"abcdefghijklmnopqrstuvwxyz"\r
"0123456789+/";\r
\r
EFIAPI\r
Base64Encode (\r
IN CONST UINT8 *Source,\r
- IN UINTN SourceLength,\r
+ IN UINTN SourceLength,\r
OUT CHAR8 *Destination OPTIONAL,\r
IN OUT UINTN *DestinationSize\r
)\r
{\r
-\r
- UINTN RequiredSize;\r
- UINTN Left;\r
+ UINTN RequiredSize;\r
+ UINTN Left;\r
\r
//\r
// Check pointers, and SourceLength is valid\r
*DestinationSize = 1;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
+\r
*DestinationSize = 1;\r
- *Destination = '\0';\r
+ *Destination = '\0';\r
return RETURN_SUCCESS;\r
}\r
\r
//\r
// Check if SourceLength or DestinationSize is valid\r
//\r
- if ((SourceLength >= (MAX_ADDRESS - (UINTN)Source)) || (*DestinationSize >= (MAX_ADDRESS - (UINTN)Destination))){\r
+ if ((SourceLength >= (MAX_ADDRESS - (UINTN)Source)) || (*DestinationSize >= (MAX_ADDRESS - (UINTN)Destination))) {\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
// 4 ascii per 3 bytes + NULL\r
//\r
RequiredSize = ((SourceLength + 2) / 3) * 4 + 1;\r
- if ((Destination == NULL) || *DestinationSize < RequiredSize) {\r
+ if ((Destination == NULL) || (*DestinationSize < RequiredSize)) {\r
*DestinationSize = RequiredSize;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
// Encode 24 bits (three bytes) into 4 ascii characters\r
//\r
while (Left >= 3) {\r
-\r
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2 ];\r
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];\r
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];\r
*Destination++ = EncodingTable[((Source[1] & 0x0f) << 2) + ((Source[2] & 0xc0) >> 6)];\r
- *Destination++ = EncodingTable[( Source[2] & 0x3f)];\r
- Left -= 3;\r
- Source += 3;\r
+ *Destination++ = EncodingTable[(Source[2] & 0x3f)];\r
+ Left -= 3;\r
+ Source += 3;\r
}\r
\r
//\r
//\r
// One more data byte, two pad characters\r
//\r
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];\r
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];\r
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4)];\r
*Destination++ = '=';\r
*Destination++ = '=';\r
//\r
// Two more data bytes, and one pad character\r
//\r
- *Destination++ = EncodingTable[( Source[0] & 0xfc) >> 2];\r
+ *Destination++ = EncodingTable[(Source[0] & 0xfc) >> 2];\r
*Destination++ = EncodingTable[((Source[0] & 0x03) << 4) + ((Source[1] & 0xf0) >> 4)];\r
*Destination++ = EncodingTable[((Source[1] & 0x0f) << 2)];\r
*Destination++ = '=';\r
break;\r
- }\r
+ }\r
+\r
//\r
// Add terminating NULL\r
//\r
RETURN_STATUS\r
EFIAPI\r
Base64Decode (\r
- IN CONST CHAR8 *Source OPTIONAL,\r
- IN UINTN SourceSize,\r
- OUT UINT8 *Destination OPTIONAL,\r
- IN OUT UINTN *DestinationSize\r
+ IN CONST CHAR8 *Source OPTIONAL,\r
+ IN UINTN SourceSize,\r
+ OUT UINT8 *Destination OPTIONAL,\r
+ IN OUT UINTN *DestinationSize\r
)\r
{\r
- BOOLEAN PaddingMode;\r
- UINTN SixBitGroupsConsumed;\r
- UINT32 Accumulator;\r
- UINTN OriginalDestinationSize;\r
- UINTN SourceIndex;\r
- CHAR8 SourceChar;\r
- UINT32 Base64Value;\r
- UINT8 DestinationOctet;\r
+ BOOLEAN PaddingMode;\r
+ UINTN SixBitGroupsConsumed;\r
+ UINT32 Accumulator;\r
+ UINTN OriginalDestinationSize;\r
+ UINTN SourceIndex;\r
+ CHAR8 SourceChar;\r
+ UINT32 Base64Value;\r
+ UINT8 DestinationOctet;\r
\r
if (DestinationSize == NULL) {\r
return RETURN_INVALID_PARAMETER;\r
//\r
// Check for overlap.\r
//\r
- if (Source != NULL && Destination != NULL) {\r
+ if ((Source != NULL) && (Destination != NULL)) {\r
//\r
// Both arrays have been provided, and we know from earlier that each array\r
// is valid in itself.\r
//\r
// Whitespace is ignored at all positions (regardless of padding mode).\r
//\r
- if (SourceChar == '\t' || SourceChar == '\n' || SourceChar == '\v' ||\r
- SourceChar == '\f' || SourceChar == '\r' || SourceChar == ' ') {\r
+ if ((SourceChar == '\t') || (SourceChar == '\n') || (SourceChar == '\v') ||\r
+ (SourceChar == '\f') || (SourceChar == '\r') || (SourceChar == ' '))\r
+ {\r
continue;\r
}\r
\r
// "=" padding characters.\r
//\r
if (PaddingMode) {\r
- if (SourceChar == '=' && SixBitGroupsConsumed == 3) {\r
+ if ((SourceChar == '=') && (SixBitGroupsConsumed == 3)) {\r
SixBitGroupsConsumed = 0;\r
continue;\r
}\r
+\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
// When not in padding mode, decode Base64Value based on RFC4648, "Table 1:\r
// The Base 64 Alphabet".\r
//\r
- if ('A' <= SourceChar && SourceChar <= 'Z') {\r
+ if (('A' <= SourceChar) && (SourceChar <= 'Z')) {\r
Base64Value = SourceChar - 'A';\r
- } else if ('a' <= SourceChar && SourceChar <= 'z') {\r
+ } else if (('a' <= SourceChar) && (SourceChar <= 'z')) {\r
Base64Value = 26 + (SourceChar - 'a');\r
- } else if ('0' <= SourceChar && SourceChar <= '9') {\r
+ } else if (('0' <= SourceChar) && (SourceChar <= '9')) {\r
Base64Value = 52 + (SourceChar - '0');\r
} else if (SourceChar == '+') {\r
Base64Value = 62;\r
Accumulator = (Accumulator << 6) | Base64Value;\r
SixBitGroupsConsumed++;\r
switch (SixBitGroupsConsumed) {\r
- case 1:\r
- //\r
- // No octet to spill after consuming the first 6-bit group of the\r
- // quantum; advance to the next source character.\r
- //\r
- continue;\r
- case 2:\r
- //\r
- // 12 bits accumulated (6 pending + 6 new); prepare for spilling an\r
- // octet. 4 bits remain pending.\r
- //\r
- DestinationOctet = (UINT8)(Accumulator >> 4);\r
- Accumulator &= 0xF;\r
- break;\r
- case 3:\r
- //\r
- // 10 bits accumulated (4 pending + 6 new); prepare for spilling an\r
- // octet. 2 bits remain pending.\r
- //\r
- DestinationOctet = (UINT8)(Accumulator >> 2);\r
- Accumulator &= 0x3;\r
- break;\r
- default:\r
- ASSERT (SixBitGroupsConsumed == 4);\r
- //\r
- // 8 bits accumulated (2 pending + 6 new); prepare for spilling an octet.\r
- // The quantum is complete, 0 bits remain pending.\r
- //\r
- DestinationOctet = (UINT8)Accumulator;\r
- Accumulator = 0;\r
- SixBitGroupsConsumed = 0;\r
- break;\r
+ case 1:\r
+ //\r
+ // No octet to spill after consuming the first 6-bit group of the\r
+ // quantum; advance to the next source character.\r
+ //\r
+ continue;\r
+ case 2:\r
+ //\r
+ // 12 bits accumulated (6 pending + 6 new); prepare for spilling an\r
+ // octet. 4 bits remain pending.\r
+ //\r
+ DestinationOctet = (UINT8)(Accumulator >> 4);\r
+ Accumulator &= 0xF;\r
+ break;\r
+ case 3:\r
+ //\r
+ // 10 bits accumulated (4 pending + 6 new); prepare for spilling an\r
+ // octet. 2 bits remain pending.\r
+ //\r
+ DestinationOctet = (UINT8)(Accumulator >> 2);\r
+ Accumulator &= 0x3;\r
+ break;\r
+ default:\r
+ ASSERT (SixBitGroupsConsumed == 4);\r
+ //\r
+ // 8 bits accumulated (2 pending + 6 new); prepare for spilling an octet.\r
+ // The quantum is complete, 0 bits remain pending.\r
+ //\r
+ DestinationOctet = (UINT8)Accumulator;\r
+ Accumulator = 0;\r
+ SixBitGroupsConsumed = 0;\r
+ break;\r
}\r
\r
//\r
ASSERT (Destination != NULL);\r
Destination[*DestinationSize] = DestinationOctet;\r
}\r
+\r
(*DestinationSize)++;\r
\r
//\r
if (*DestinationSize <= OriginalDestinationSize) {\r
return RETURN_SUCCESS;\r
}\r
+\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
UINT8\r
EFIAPI\r
DecimalToBcd8 (\r
- IN UINT8 Value\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (Value < 100);\r
- return (UINT8) (((Value / 10) << 4) | (Value % 10));\r
+ return (UINT8)(((Value / 10) << 4) | (Value % 10));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
BcdToDecimal8 (\r
- IN UINT8 Value\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (Value < 0xa0);\r
ASSERT ((Value & 0xf) < 0xa);\r
- return (UINT8) ((Value >> 4) * 10 + (Value & 0xf));\r
+ return (UINT8)((Value >> 4) * 10 + (Value & 0xf));\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT16\r
EFIAPI\r
SwapBytes16 (\r
- IN UINT16 Value\r
+ IN UINT16 Value\r
)\r
{\r
- return (UINT16) ((Value<< 8) | (Value>> 8));\r
+ return (UINT16)((Value<< 8) | (Value>> 8));\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT32\r
EFIAPI\r
SwapBytes32 (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
)\r
{\r
UINT32 LowerBytes;\r
UINT32 HigherBytes;\r
\r
- LowerBytes = (UINT32) SwapBytes16 ((UINT16) Value);\r
- HigherBytes = (UINT32) SwapBytes16 ((UINT16) (Value >> 16));\r
+ LowerBytes = (UINT32)SwapBytes16 ((UINT16)Value);\r
+ HigherBytes = (UINT32)SwapBytes16 ((UINT16)(Value >> 16));\r
\r
return (LowerBytes << 16 | HigherBytes);\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
UINT64\r
EFIAPI\r
SwapBytes64 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
return InternalMathSwapBytes64 (Value);\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
ASSERT (EntryPoint != NULL);\r
ASSERT (NewStack != NULL);\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Reads a 16-bit value from memory that may be unaligned.\r
\r
UINT16\r
EFIAPI\r
ReadUnaligned16 (\r
- IN CONST UINT16 *Buffer\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT16\r
EFIAPI\r
WriteUnaligned16 (\r
- OUT UINT16 *Buffer,\r
- IN UINT16 Value\r
+ OUT UINT16 *Buffer,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT32\r
EFIAPI\r
ReadUnaligned24 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT32\r
EFIAPI\r
WriteUnaligned24 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT32\r
EFIAPI\r
ReadUnaligned32 (\r
- IN CONST UINT32 *Buffer\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT32\r
EFIAPI\r
WriteUnaligned32 (\r
- OUT UINT32 *Buffer,\r
- IN UINT32 Value\r
+ OUT UINT32 *Buffer,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT64\r
EFIAPI\r
ReadUnaligned64 (\r
- IN CONST UINT64 *Buffer\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
UINT64\r
EFIAPI\r
WriteUnaligned64 (\r
- OUT UINT64 *Buffer,\r
- IN UINT64 Value\r
+ OUT UINT64 *Buffer,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (Buffer != NULL);\r
///\r
/// Module global variable for simple system emulation of interrupt state\r
///\r
-STATIC BOOLEAN mUnitTestHostBaseLibInterruptState;\r
+STATIC BOOLEAN mUnitTestHostBaseLibInterruptState;\r
\r
/**\r
Enables CPU interrupts.\r
\r
**/\r
\r
-\r
/**\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-void __debugbreak (VOID);\r
+void\r
+__debugbreak (\r
+ VOID\r
+ );\r
\r
#pragma intrinsic(__debugbreak)\r
\r
{\r
__debugbreak ();\r
}\r
-\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
-\r
-\r
/**\r
Used to serialize load and store operations.\r
\r
__asm__ __volatile__ ("":::"memory");\r
}\r
\r
-\r
/**\r
Requests CPU to pause for a short period of time.\r
\r
__asm__ __volatile__ ("pause");\r
}\r
\r
-\r
/**\r
Generates a breakpoint on the CPU.\r
\r
__asm__ __volatile__ ("int $3");\r
}\r
\r
-\r
/**\r
Reads the current value of the EFLAGS register.\r
\r
VOID\r
)\r
{\r
- UINTN Eflags;\r
+ UINTN Eflags;\r
\r
__asm__ __volatile__ (\r
"pushfq \n\t"\r
"pop %0 "\r
: "=r" (Eflags) // %0\r
- );\r
+ );\r
\r
return Eflags;\r
}\r
VOID\r
EFIAPI\r
InternalX86FxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
)\r
{\r
__asm__ __volatile__ (\r
"fxsave %0"\r
:\r
: "m" (*Buffer) // %0\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Restores the current floating point/SSE/SSE2 context from a buffer.\r
\r
VOID\r
EFIAPI\r
InternalX86FxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
)\r
{\r
__asm__ __volatile__ (\r
"fxrstor %0"\r
:\r
: "m" (*Buffer) // %0\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #0 (MM0).\r
\r
__asm__ __volatile__ (\r
"movd %%mm0, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #1 (MM1).\r
\r
__asm__ __volatile__ (\r
"movd %%mm1, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #2 (MM2).\r
\r
__asm__ __volatile__ (\r
"movd %%mm2, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #3 (MM3).\r
\r
__asm__ __volatile__ (\r
"movd %%mm3, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #4 (MM4).\r
\r
__asm__ __volatile__ (\r
"movd %%mm4, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #5 (MM5).\r
\r
__asm__ __volatile__ (\r
"movd %%mm5, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #6 (MM6).\r
\r
__asm__ __volatile__ (\r
"movd %%mm6, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of 64-bit MMX Register #7 (MM7).\r
\r
__asm__ __volatile__ (\r
"movd %%mm7, %0 \n\t"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #0 (MM0).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm0 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm0" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #1 (MM1).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm1 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm1" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #2 (MM2).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm2 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm2" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #3 (MM3).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm3 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm3" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #4 (MM4).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm4 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm4" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #5 (MM5).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm5 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm5" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #6 (MM6).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm6 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm6" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current value of 64-bit MMX Register #7 (MM7).\r
\r
VOID\r
EFIAPI\r
AsmWriteMm7 (\r
- IN UINT64 Value\r
+ IN UINT64 Value\r
)\r
{\r
__asm__ __volatile__ (\r
"movd %0, %%mm7" // %0\r
:\r
: "m" (Value)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current value of Time Stamp Counter (TSC).\r
\r
"rdtsc"\r
: "=a" (LowData),\r
"=d" (HiData)\r
- );\r
+ );\r
\r
return (((UINT64)HiData) << 32) | LowData;\r
}\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
#include <Library/RegisterFilterLib.h>\r
\r
__asm__ __volatile__ ("sti"::: "memory");\r
}\r
\r
-\r
/**\r
Disables CPU interrupts.\r
\r
UINT64\r
EFIAPI\r
AsmReadMsr64 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
- UINT32 LowData;\r
- UINT32 HighData;\r
- UINT64 Value;\r
- BOOLEAN Flag;\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+ UINT64 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrRead (Index, &Value);\r
if (Flag) {\r
: "=a" (LowData), // %0\r
"=d" (HighData) // %1\r
: "c" (Index) // %2\r
- );\r
+ );\r
Value = (((UINT64)HighData) << 32) | LowData;\r
}\r
+\r
FilterAfterMsrRead (Index, &Value);\r
\r
return Value;\r
UINT64\r
EFIAPI\r
AsmWriteMsr64 (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
)\r
{\r
- UINT32 LowData;\r
- UINT32 HighData;\r
- BOOLEAN Flag;\r
+ UINT32 LowData;\r
+ UINT32 HighData;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrWrite (Index, &Value);\r
if (Flag) {\r
: "c" (Index),\r
"a" (LowData),\r
"d" (HighData)\r
- );\r
+ );\r
}\r
+\r
FilterAfterMsrWrite (Index, &Value);\r
\r
return Value;\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%cr0,%0"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of the Control Register 2 (CR2).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%cr2, %0"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%cr3, %0"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of the Control Register 4 (CR4).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%cr4, %0"\r
: "=r" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 0 (CR0).\r
\r
"mov %0, %%cr0"\r
:\r
: "r" (Cr0)\r
- );\r
+ );\r
return Cr0;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 2 (CR2).\r
\r
"mov %0, %%cr2"\r
:\r
: "r" (Cr2)\r
- );\r
+ );\r
return Cr2;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 3 (CR3).\r
\r
"mov %0, %%cr3"\r
:\r
: "r" (Cr3)\r
- );\r
+ );\r
return Cr3;\r
}\r
\r
-\r
/**\r
Writes a value to Control Register 4 (CR4).\r
\r
"mov %0, %%cr4"\r
:\r
: "r" (Cr4)\r
- );\r
+ );\r
return Cr4;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 0 (DR0).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr0, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 1 (DR1).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr1, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 2 (DR2).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr2, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 3 (DR3).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr3, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 4 (DR4).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr4, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 5 (DR5).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr5, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 6 (DR6).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr6, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Debug Register 7 (DR7).\r
\r
VOID\r
)\r
{\r
- UINTN Data;\r
+ UINTN Data;\r
\r
__asm__ __volatile__ (\r
"mov %%dr7, %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 0 (DR0).\r
\r
"mov %0, %%dr0"\r
:\r
: "r" (Dr0)\r
- );\r
+ );\r
return Dr0;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 1 (DR1).\r
\r
"mov %0, %%dr1"\r
:\r
: "r" (Dr1)\r
- );\r
+ );\r
return Dr1;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 2 (DR2).\r
\r
"mov %0, %%dr2"\r
:\r
: "r" (Dr2)\r
- );\r
+ );\r
return Dr2;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 3 (DR3).\r
\r
"mov %0, %%dr3"\r
:\r
: "r" (Dr3)\r
- );\r
+ );\r
return Dr3;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 4 (DR4).\r
\r
"mov %0, %%dr4"\r
:\r
: "r" (Dr4)\r
- );\r
+ );\r
return Dr4;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 5 (DR5).\r
\r
"mov %0, %%dr5"\r
:\r
: "r" (Dr5)\r
- );\r
+ );\r
return Dr5;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 6 (DR6).\r
\r
"mov %0, %%dr6"\r
:\r
: "r" (Dr6)\r
- );\r
+ );\r
return Dr6;\r
}\r
\r
-\r
/**\r
Writes a value to Debug Register 7 (DR7).\r
\r
"mov %0, %%dr7"\r
:\r
: "r" (Dr7)\r
- );\r
+ );\r
return Dr7;\r
}\r
\r
-\r
/**\r
Reads the current value of Code Segment Register (CS).\r
\r
__asm__ __volatile__ (\r
"mov %%cs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Data Segment Register (DS).\r
\r
__asm__ __volatile__ (\r
"mov %%ds, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Extra Segment Register (ES).\r
\r
__asm__ __volatile__ (\r
"mov %%es, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of FS Data Segment Register (FS).\r
\r
__asm__ __volatile__ (\r
"mov %%fs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of GS Data Segment Register (GS).\r
\r
__asm__ __volatile__ (\r
"mov %%gs, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Stack Segment Register (SS).\r
\r
__asm__ __volatile__ (\r
"mov %%ss, %0"\r
:"=a" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current value of Task Register (TR).\r
\r
__asm__ __volatile__ (\r
"str %0"\r
: "=r" (Data)\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Reads the current Global Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86ReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
__asm__ __volatile__ (\r
"sgdt %0"\r
: "=m" (*Gdtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current Global Descriptor Table Register (GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86WriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lgdt %0"\r
:\r
: "m" (*Gdtr)\r
- );\r
-\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86ReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
__asm__ __volatile__ (\r
"sidt %0"\r
: "=m" (*Idtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Writes the current Interrupt Descriptor Table Register(GDTR) descriptor.\r
\r
VOID\r
EFIAPI\r
InternalX86WriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lidt %0"\r
:\r
: "m" (*Idtr)\r
- );\r
+ );\r
}\r
\r
-\r
/**\r
Reads the current Local Descriptor Table Register(LDTR) selector.\r
\r
__asm__ __volatile__ (\r
"sldt %0"\r
: "=g" (Data) // %0\r
- );\r
+ );\r
\r
return Data;\r
}\r
\r
-\r
/**\r
Writes the current Local Descriptor Table Register (GDTR) selector.\r
\r
VOID\r
EFIAPI\r
AsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
)\r
{\r
__asm__ __volatile__ (\r
"lldtw %0"\r
:\r
: "g" (Ldtr) // %0\r
- );\r
+ );\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
AsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
UINT32 LowData;\r
: "=a" (LowData),\r
"=d" (HiData)\r
: "c" (Index)\r
- );\r
+ );\r
\r
return (((UINT64)HiData) << 32) | LowData;\r
}\r
UINTN\r
EFIAPI\r
AsmMonitor (\r
- IN UINTN Eax,\r
- IN UINTN Ecx,\r
- IN UINTN Edx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
)\r
{\r
__asm__ __volatile__ (\r
: "a" (Eax),\r
"c" (Ecx),\r
"d" (Edx)\r
- );\r
+ );\r
\r
return Eax;\r
}\r
UINTN\r
EFIAPI\r
AsmMwait (\r
- IN UINTN Eax,\r
- IN UINTN Ecx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
)\r
{\r
__asm__ __volatile__ (\r
:\r
: "a" (Eax),\r
"c" (Ecx)\r
- );\r
+ );\r
\r
return Eax;\r
}\r
)\r
{\r
__asm__ __volatile__ ("invd":::"memory");\r
-\r
}\r
\r
-\r
/**\r
Flushes a cache line from all the instruction and data caches within the\r
coherency domain of the CPU.\r
VOID *\r
EFIAPI\r
AsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
)\r
{\r
__asm__ __volatile__ (\r
:\r
: "r" (LinearAddress)\r
: "memory"\r
- );\r
+ );\r
\r
- return LinearAddress;\r
+ return LinearAddress;\r
}\r
ASSERT (FALSE);\r
}\r
\r
-\r
/**\r
Enables the 64-bit paging mode on the CPU.\r
\r
VOID\r
EFIAPI\r
InternalX86EnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
)\r
{\r
//\r
\r
#include <Library/RegisterFilterLib.h>\r
\r
-unsigned __int64 __readmsr (int register);\r
+unsigned __int64\r
+__readmsr (\r
+ int register\r
+ );\r
\r
#pragma intrinsic(__readmsr)\r
\r
IN UINT32 Index\r
)\r
{\r
- UINT64 Value;\r
- BOOLEAN Flag;\r
+ UINT64 Value;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrRead (Index, &Value);\r
if (Flag) {\r
Value = __readmsr (Index);\r
}\r
+\r
FilterAfterMsrRead (Index, &Value);\r
\r
return Value;\r
}\r
-\r
\r
#include <Library/RegisterFilterLib.h>\r
\r
-void __writemsr (unsigned long Register, unsigned __int64 Value);\r
+void\r
+__writemsr (\r
+ unsigned long Register,\r
+ unsigned __int64 Value\r
+ );\r
\r
#pragma intrinsic(__writemsr)\r
\r
IN UINT64 Value\r
)\r
{\r
- BOOLEAN Flag;\r
+ BOOLEAN Flag;\r
\r
Flag = FilterBeforeMsrWrite (Index, &Value);\r
if (Flag) {\r
__writemsr (Index, Value);\r
}\r
+\r
FilterAfterMsrWrite (Index, &Value);\r
\r
return Value;\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmDisablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
)\r
{\r
ASSERT (EntryPoint != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmEnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
)\r
{\r
ASSERT (EntryPoint != 0);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmFxRestore (\r
- IN CONST IA32_FX_BUFFER *Buffer\r
+ IN CONST IA32_FX_BUFFER *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
//\r
// Check the flag recorded by AsmFxSave()\r
//\r
- ASSERT (0xAA5555AA == *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]));\r
+ ASSERT (0xAA5555AA == *(UINT32 *)(&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]));\r
\r
InternalX86FxRestore (Buffer);\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmFxSave (\r
- OUT IA32_FX_BUFFER *Buffer\r
+ OUT IA32_FX_BUFFER *Buffer\r
)\r
{\r
ASSERT (Buffer != NULL);\r
//\r
// Mark one flag at end of Buffer, it will be check by AsmFxRestor()\r
//\r
- *(UINT32 *) (&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]) = 0xAA5555AA;\r
+ *(UINT32 *)(&Buffer->Buffer[sizeof (Buffer->Buffer) - 4]) = 0xAA5555AA;\r
}\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Retrieves the current CPU interrupt state.\r
\r
VOID\r
)\r
{\r
- IA32_EFLAGS32 EFlags;\r
+ IA32_EFLAGS32 EFlags;\r
\r
EFlags.UintN = AsmReadEflags ();\r
return (BOOLEAN)(1 == EFlags.Bits.IF);\r
}\r
-\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Used to serialize load and store operations.\r
\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-\r
/**\r
Returns the lower 32-bits of a Machine Specific Register(MSR).\r
\r
UINT32\r
EFIAPI\r
AsmReadMsr32 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
return (UINT32)AsmReadMsr64 (Index);\r
UINT32\r
EFIAPI\r
AsmWriteMsr32 (\r
- IN UINT32 Index,\r
- IN UINT32 Value\r
+ IN UINT32 Index,\r
+ IN UINT32 Value\r
)\r
{\r
return (UINT32)AsmWriteMsr64 (Index, Value);\r
UINT32\r
EFIAPI\r
AsmMsrOr32 (\r
- IN UINT32 Index,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINT32 OrData\r
)\r
{\r
return (UINT32)AsmMsrOr64 (Index, OrData);\r
UINT32\r
EFIAPI\r
AsmMsrAnd32 (\r
- IN UINT32 Index,\r
- IN UINT32 AndData\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData\r
)\r
{\r
return (UINT32)AsmMsrAnd64 (Index, AndData);\r
UINT32\r
EFIAPI\r
AsmMsrAndThenOr32 (\r
- IN UINT32 Index,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return (UINT32)AsmMsrAndThenOr64 (Index, AndData, OrData);\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldRead32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (AsmReadMsr32 (Index), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldWrite32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (EndBit < sizeof (Value) * 8);\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldOr32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT (EndBit < sizeof (OrData) * 8);\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldAnd32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT (EndBit < sizeof (AndData) * 8);\r
UINT32\r
EFIAPI\r
AsmMsrBitFieldAndThenOr32 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT (EndBit < sizeof (AndData) * 8);\r
UINT64\r
EFIAPI\r
AsmMsrOr64 (\r
- IN UINT32 Index,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINT64 OrData\r
)\r
{\r
return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) | OrData);\r
UINT64\r
EFIAPI\r
AsmMsrAnd64 (\r
- IN UINT32 Index,\r
- IN UINT64 AndData\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData\r
)\r
{\r
return AsmWriteMsr64 (Index, AsmReadMsr64 (Index) & AndData);\r
UINT64\r
EFIAPI\r
AsmMsrAndThenOr64 (\r
- IN UINT32 Index,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return AsmWriteMsr64 (Index, (AsmReadMsr64 (Index) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldRead64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (AsmReadMsr64 (Index), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldWrite64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return AsmWriteMsr64 (\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldOr64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return AsmWriteMsr64 (\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldAnd64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return AsmWriteMsr64 (\r
UINT64\r
EFIAPI\r
AsmMsrBitFieldAndThenOr64 (\r
- IN UINT32 Index,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINT32 Index,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return AsmWriteMsr64 (\r
VOID\r
EFIAPI\r
PatchInstructionX86 (\r
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
- IN UINT64 PatchValue,\r
- IN UINTN ValueSize\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
)\r
{\r
//\r
ASSERT ((UINTN)InstructionEnd > ValueSize);\r
\r
switch (ValueSize) {\r
- case 1:\r
- ASSERT (PatchValue <= MAX_UINT8);\r
- *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;\r
- break;\r
-\r
- case 2:\r
- ASSERT (PatchValue <= MAX_UINT16);\r
- WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);\r
- break;\r
-\r
- case 4:\r
- ASSERT (PatchValue <= MAX_UINT32);\r
- WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);\r
- break;\r
-\r
- case 8:\r
- WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);\r
- break;\r
-\r
- default:\r
- ASSERT (FALSE);\r
+ case 1:\r
+ ASSERT (PatchValue <= MAX_UINT8);\r
+ *((UINT8 *)(UINTN)InstructionEnd - 1) = (UINT8)PatchValue;\r
+ break;\r
+\r
+ case 2:\r
+ ASSERT (PatchValue <= MAX_UINT16);\r
+ WriteUnaligned16 ((UINT16 *)(UINTN)InstructionEnd - 1, (UINT16)PatchValue);\r
+ break;\r
+\r
+ case 4:\r
+ ASSERT (PatchValue <= MAX_UINT32);\r
+ WriteUnaligned32 ((UINT32 *)(UINTN)InstructionEnd - 1, (UINT32)PatchValue);\r
+ break;\r
+\r
+ case 8:\r
+ WriteUnaligned64 ((UINT64 *)(UINTN)InstructionEnd - 1, PatchValue);\r
+ break;\r
+\r
+ default:\r
+ ASSERT (FALSE);\r
}\r
}\r
BOOLEAN\r
EFIAPI\r
AsmRdRand16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
ASSERT (Rand != NULL);\r
BOOLEAN\r
EFIAPI\r
AsmRdRand32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
ASSERT (Rand != NULL);\r
BOOLEAN\r
EFIAPI\r
AsmRdRand64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
ASSERT (Rand != NULL);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
ASSERT (Gdtr != NULL);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
ASSERT (Idtr != NULL);\r
\r
**/\r
\r
-\r
#include "BaseLibInternals.h"\r
\r
-extern CONST UINT8 m16Start;\r
-extern CONST UINT16 m16Size;\r
-extern CONST UINT16 mThunk16Attr;\r
-extern CONST UINT16 m16Gdt;\r
-extern CONST UINT16 m16GdtrBase;\r
-extern CONST UINT16 mTransition;\r
+extern CONST UINT8 m16Start;\r
+extern CONST UINT16 m16Size;\r
+extern CONST UINT16 mThunk16Attr;\r
+extern CONST UINT16 m16Gdt;\r
+extern CONST UINT16 m16GdtrBase;\r
+extern CONST UINT16 mTransition;\r
\r
/**\r
Invokes 16-bit code in big real mode and returns the updated register set.\r
IA32_REGISTER_SET *\r
EFIAPI\r
InternalAsmThunk16 (\r
- IN IA32_REGISTER_SET *RegisterSet,\r
- IN OUT VOID *Transition\r
+ IN IA32_REGISTER_SET *RegisterSet,\r
+ IN OUT VOID *Transition\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
AsmGetThunk16Properties (\r
- OUT UINT32 *RealModeBufferSize,\r
- OUT UINT32 *ExtraStackSize\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
)\r
{\r
ASSERT (RealModeBufferSize != NULL);\r
VOID\r
EFIAPI\r
AsmPrepareThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
- IA32_SEGMENT_DESCRIPTOR *RealModeGdt;\r
+ IA32_SEGMENT_DESCRIPTOR *RealModeGdt;\r
\r
ASSERT (ThunkContext != NULL);\r
ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);\r
// RealModeGdt[2]: Data Segment\r
// RealModeGdt[3]: Call Gate\r
//\r
- RealModeGdt = (IA32_SEGMENT_DESCRIPTOR*)(\r
- (UINTN)ThunkContext->RealModeBuffer + m16Gdt);\r
+ RealModeGdt = (IA32_SEGMENT_DESCRIPTOR *)(\r
+ (UINTN)ThunkContext->RealModeBuffer + m16Gdt);\r
\r
//\r
// Update Code & Data Segment Descriptor\r
//\r
// Update transition code entry point offset\r
//\r
- *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=\r
+ *(UINT32 *)((UINTN)ThunkContext->RealModeBuffer + mTransition) +=\r
(UINT32)(UINTN)ThunkContext->RealModeBuffer & 0xf;\r
\r
//\r
// Set segment limits to 64KB\r
//\r
RealModeGdt[1].Bits.LimitHigh = 0;\r
- RealModeGdt[1].Bits.G = 0;\r
+ RealModeGdt[1].Bits.G = 0;\r
RealModeGdt[2].Bits.LimitHigh = 0;\r
- RealModeGdt[2].Bits.G = 0;\r
+ RealModeGdt[2].Bits.G = 0;\r
}\r
\r
//\r
// Update GDTBASE for this thunk context\r
//\r
- *(VOID**)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;\r
+ *(VOID **)((UINTN)ThunkContext->RealModeBuffer + m16GdtrBase) = RealModeGdt;\r
\r
//\r
// Update Thunk Attributes\r
//\r
- *(UINT32*)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =\r
+ *(UINT32 *)((UINTN)ThunkContext->RealModeBuffer + mThunk16Attr) =\r
ThunkContext->ThunkAttributes;\r
}\r
\r
VOID\r
EFIAPI\r
AsmThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
- IA32_REGISTER_SET *UpdatedRegs;\r
+ IA32_REGISTER_SET *UpdatedRegs;\r
\r
ASSERT (ThunkContext != NULL);\r
ASSERT ((UINTN)ThunkContext->RealModeBuffer < 0x100000);\r
ASSERT (ThunkContext->RealModeBufferSize >= m16Size);\r
ASSERT ((UINTN)ThunkContext->RealModeBuffer + m16Size <= 0x100000);\r
- ASSERT (((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \\r
- (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)));\r
+ ASSERT (\r
+ ((ThunkContext->ThunkAttributes & (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL)) != \\r
+ (THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 | THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL))\r
+ );\r
\r
UpdatedRegs = InternalAsmThunk16 (\r
ThunkContext->RealModeState,\r
VOID\r
EFIAPI\r
AsmPrepareAndThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
AsmPrepareThunk16 (ThunkContext);\r
UINT32\r
EFIAPI\r
UnitTestHostBaseLibAsmCpuid (\r
- IN UINT32 Index,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
)\r
{\r
if (Eax != NULL) {\r
*Eax = 0;\r
}\r
+\r
if (Ebx != NULL) {\r
*Ebx = 0;\r
}\r
+\r
if (Ecx != NULL) {\r
*Ecx = 0;\r
}\r
+\r
if (Edx != NULL) {\r
*Edx = 0;\r
}\r
+\r
return Index;\r
}\r
\r
UINT32\r
EFIAPI\r
UnitTestHostBaseLibAsmCpuidEx (\r
- IN UINT32 Index,\r
- IN UINT32 SubIndex,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ IN UINT32 SubIndex,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
)\r
{\r
if (Eax != NULL) {\r
*Eax = 0;\r
}\r
+\r
if (Ebx != NULL) {\r
*Ebx = 0;\r
}\r
+\r
if (Ecx != NULL) {\r
*Ecx = 0;\r
}\r
+\r
if (Edx != NULL) {\r
*Edx = 0;\r
}\r
+\r
return Index;\r
}\r
\r
UINT64\r
EFIAPI\r
UnitTestHostBaseLibAsmReadMsr64 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
if (Index < 0x1000) {\r
return mUnitTestHostBaseLibMsr[0][Index];\r
}\r
- if (Index >= 0xC0000000 && Index < 0xC0001000) {\r
+\r
+ if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {\r
return mUnitTestHostBaseLibMsr[1][Index];\r
}\r
+\r
return 0;\r
}\r
\r
UINT64\r
EFIAPI\r
UnitTestHostBaseLibAsmWriteMsr64 (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
)\r
{\r
if (Index < 0x1000) {\r
mUnitTestHostBaseLibMsr[0][Index] = Value;\r
}\r
- if (Index >= 0xC0000000 && Index < 0xC0001000) {\r
+\r
+ if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {\r
mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;\r
}\r
+\r
return Value;\r
}\r
\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
Gdtr = &mUnitTestHostBaseLibGdtr;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmWriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
Idtr = &mUnitTestHostBaseLibIdtr;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmWriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
)\r
{\r
mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;\r
UINT64\r
EFIAPI\r
UnitTestHostBaseLibAsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
return 0;\r
UINTN\r
EFIAPI\r
UnitTestHostBaseLibAsmMonitor (\r
- IN UINTN Eax,\r
- IN UINTN Ecx,\r
- IN UINTN Edx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
)\r
{\r
return Eax;\r
UINTN\r
EFIAPI\r
UnitTestHostBaseLibAsmMwait (\r
- IN UINTN Eax,\r
- IN UINTN Ecx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
)\r
{\r
return Eax;\r
VOID *\r
EFIAPI\r
UnitTestHostBaseLibAsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
)\r
{\r
return LinearAddress;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmEnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
)\r
{\r
SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmDisablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
)\r
{\r
SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmGetThunk16Properties (\r
- OUT UINT32 *RealModeBufferSize,\r
- OUT UINT32 *ExtraStackSize\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
)\r
{\r
*RealModeBufferSize = 0;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmPrepareThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
}\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
}\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmPrepareAndThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
}\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibAsmWriteTr (\r
- IN UINT16 Selector\r
+ IN UINT16 Selector\r
)\r
{\r
mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;\r
VOID\r
EFIAPI\r
UnitTestHostBaseLibPatchInstructionX86 (\r
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
- IN UINT64 PatchValue,\r
- IN UINTN ValueSize\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
)\r
{\r
}\r
UINT32\r
EFIAPI\r
AsmCpuid (\r
- IN UINT32 Index,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);\r
UINT32\r
EFIAPI\r
AsmCpuidEx (\r
- IN UINT32 Index,\r
- IN UINT32 SubIndex,\r
- OUT UINT32 *Eax OPTIONAL,\r
- OUT UINT32 *Ebx OPTIONAL,\r
- OUT UINT32 *Ecx OPTIONAL,\r
- OUT UINT32 *Edx OPTIONAL\r
+ IN UINT32 Index,\r
+ IN UINT32 SubIndex,\r
+ OUT UINT32 *Eax OPTIONAL,\r
+ OUT UINT32 *Ebx OPTIONAL,\r
+ OUT UINT32 *Ecx OPTIONAL,\r
+ OUT UINT32 *Edx OPTIONAL\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);\r
UINT64\r
EFIAPI\r
AsmReadMsr64 (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);\r
UINT64\r
EFIAPI\r
AsmWriteMsr64 (\r
- IN UINT32 Index,\r
- IN UINT64 Value\r
+ IN UINT32 Index,\r
+ IN UINT64 Value\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);\r
VOID\r
EFIAPI\r
AsmReadGdtr (\r
- OUT IA32_DESCRIPTOR *Gdtr\r
+ OUT IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);\r
VOID\r
EFIAPI\r
AsmWriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);\r
VOID\r
EFIAPI\r
AsmReadIdtr (\r
- OUT IA32_DESCRIPTOR *Idtr\r
+ OUT IA32_DESCRIPTOR *Idtr\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);\r
VOID\r
EFIAPI\r
AsmWriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);\r
VOID\r
EFIAPI\r
AsmWriteLdtr (\r
- IN UINT16 Ldtr\r
+ IN UINT16 Ldtr\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);\r
UINT64\r
EFIAPI\r
AsmReadPmc (\r
- IN UINT32 Index\r
+ IN UINT32 Index\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);\r
UINTN\r
EFIAPI\r
AsmMonitor (\r
- IN UINTN Eax,\r
- IN UINTN Ecx,\r
- IN UINTN Edx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx,\r
+ IN UINTN Edx\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);\r
UINTN\r
EFIAPI\r
AsmMwait (\r
- IN UINTN Eax,\r
- IN UINTN Ecx\r
+ IN UINTN Eax,\r
+ IN UINTN Ecx\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);\r
VOID *\r
EFIAPI\r
AsmFlushCacheLine (\r
- IN VOID *LinearAddress\r
+ IN VOID *LinearAddress\r
)\r
{\r
return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);\r
VOID\r
EFIAPI\r
AsmEnablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT64 EntryPoint,\r
- IN UINT64 Context1 OPTIONAL,\r
- IN UINT64 Context2 OPTIONAL,\r
- IN UINT64 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT64 EntryPoint,\r
+ IN UINT64 Context1 OPTIONAL,\r
+ IN UINT64 Context2 OPTIONAL,\r
+ IN UINT64 NewStack\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r
VOID\r
EFIAPI\r
AsmDisablePaging64 (\r
- IN UINT16 Cs,\r
- IN UINT32 EntryPoint,\r
- IN UINT32 Context1 OPTIONAL,\r
- IN UINT32 Context2 OPTIONAL,\r
- IN UINT32 NewStack\r
+ IN UINT16 Cs,\r
+ IN UINT32 EntryPoint,\r
+ IN UINT32 Context1 OPTIONAL,\r
+ IN UINT32 Context2 OPTIONAL,\r
+ IN UINT32 NewStack\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r
VOID\r
EFIAPI\r
AsmGetThunk16Properties (\r
- OUT UINT32 *RealModeBufferSize,\r
- OUT UINT32 *ExtraStackSize\r
+ OUT UINT32 *RealModeBufferSize,\r
+ OUT UINT32 *ExtraStackSize\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);\r
VOID\r
EFIAPI\r
AsmPrepareThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);\r
VOID\r
EFIAPI\r
AsmThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);\r
VOID\r
EFIAPI\r
AsmPrepareAndThunk16 (\r
- IN OUT THUNK_CONTEXT *ThunkContext\r
+ IN OUT THUNK_CONTEXT *ThunkContext\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);\r
VOID\r
EFIAPI\r
AsmWriteTr (\r
- IN UINT16 Selector\r
+ IN UINT16 Selector\r
)\r
{\r
gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);\r
VOID\r
EFIAPI\r
PatchInstructionX86 (\r
- OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
- IN UINT64 PatchValue,\r
- IN UINTN ValueSize\r
+ OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
+ IN UINT64 PatchValue,\r
+ IN UINTN ValueSize\r
)\r
{\r
gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmWriteGdtr (\r
- IN CONST IA32_DESCRIPTOR *Gdtr\r
+ IN CONST IA32_DESCRIPTOR *Gdtr\r
)\r
{\r
ASSERT (Gdtr != NULL);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "BaseLibInternals.h"\r
\r
/**\r
VOID\r
EFIAPI\r
AsmWriteIdtr (\r
- IN CONST IA32_DESCRIPTOR *Idtr\r
+ IN CONST IA32_DESCRIPTOR *Idtr\r
)\r
{\r
ASSERT (Idtr != NULL);\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
\r
**/\r
\r
-\r
-\r
-\r
#include "MemLibInternals.h"\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
)\r
{\r
//\r
// volatile to prevent the optimizer from replacing this function with\r
// the intrinsic memcpy()\r
//\r
- volatile UINT8 *Destination8;\r
- CONST UINT8 *Source8;\r
- volatile UINT32 *Destination32;\r
- CONST UINT32 *Source32;\r
- volatile UINT64 *Destination64;\r
- CONST UINT64 *Source64;\r
- UINTN Alignment;\r
+ volatile UINT8 *Destination8;\r
+ CONST UINT8 *Source8;\r
+ volatile UINT32 *Destination32;\r
+ CONST UINT32 *Source32;\r
+ volatile UINT64 *Destination64;\r
+ CONST UINT64 *Source64;\r
+ UINTN Alignment;\r
\r
if ((((UINTN)DestinationBuffer & 0x7) == 0) && (((UINTN)SourceBuffer & 0x7) == 0) && (Length >= 8)) {\r
if (SourceBuffer > DestinationBuffer) {\r
- Destination64 = (UINT64*)DestinationBuffer;\r
- Source64 = (CONST UINT64*)SourceBuffer;\r
+ Destination64 = (UINT64 *)DestinationBuffer;\r
+ Source64 = (CONST UINT64 *)SourceBuffer;\r
while (Length >= 8) {\r
*(Destination64++) = *(Source64++);\r
- Length -= 8;\r
+ Length -= 8;\r
}\r
\r
// Finish if there are still some bytes to copy\r
- Destination8 = (UINT8*)Destination64;\r
- Source8 = (CONST UINT8*)Source64;\r
+ Destination8 = (UINT8 *)Destination64;\r
+ Source8 = (CONST UINT8 *)Source64;\r
while (Length-- != 0) {\r
*(Destination8++) = *(Source8++);\r
}\r
} else if (SourceBuffer < DestinationBuffer) {\r
- Destination64 = (UINT64*)((UINTN)DestinationBuffer + Length);\r
- Source64 = (CONST UINT64*)((UINTN)SourceBuffer + Length);\r
+ Destination64 = (UINT64 *)((UINTN)DestinationBuffer + Length);\r
+ Source64 = (CONST UINT64 *)((UINTN)SourceBuffer + Length);\r
\r
// Destination64 and Source64 were aligned on a 64-bit boundary\r
// but if length is not a multiple of 8 bytes then they won't be\r
\r
Alignment = Length & 0x7;\r
if (Alignment != 0) {\r
- Destination8 = (UINT8*)Destination64;\r
- Source8 = (CONST UINT8*)Source64;\r
+ Destination8 = (UINT8 *)Destination64;\r
+ Source8 = (CONST UINT8 *)Source64;\r
\r
while (Alignment-- != 0) {\r
*(--Destination8) = *(--Source8);\r
--Length;\r
}\r
- Destination64 = (UINT64*)Destination8;\r
- Source64 = (CONST UINT64*)Source8;\r
+\r
+ Destination64 = (UINT64 *)Destination8;\r
+ Source64 = (CONST UINT64 *)Source8;\r
}\r
\r
while (Length > 0) {\r
*(--Destination64) = *(--Source64);\r
- Length -= 8;\r
+ Length -= 8;\r
}\r
}\r
} else if ((((UINTN)DestinationBuffer & 0x3) == 0) && (((UINTN)SourceBuffer & 0x3) == 0) && (Length >= 4)) {\r
if (SourceBuffer > DestinationBuffer) {\r
- Destination32 = (UINT32*)DestinationBuffer;\r
- Source32 = (CONST UINT32*)SourceBuffer;\r
+ Destination32 = (UINT32 *)DestinationBuffer;\r
+ Source32 = (CONST UINT32 *)SourceBuffer;\r
while (Length >= 4) {\r
*(Destination32++) = *(Source32++);\r
- Length -= 4;\r
+ Length -= 4;\r
}\r
\r
// Finish if there are still some bytes to copy\r
- Destination8 = (UINT8*)Destination32;\r
- Source8 = (CONST UINT8*)Source32;\r
+ Destination8 = (UINT8 *)Destination32;\r
+ Source8 = (CONST UINT8 *)Source32;\r
while (Length-- != 0) {\r
*(Destination8++) = *(Source8++);\r
}\r
} else if (SourceBuffer < DestinationBuffer) {\r
- Destination32 = (UINT32*)((UINTN)DestinationBuffer + Length);\r
- Source32 = (CONST UINT32*)((UINTN)SourceBuffer + Length);\r
+ Destination32 = (UINT32 *)((UINTN)DestinationBuffer + Length);\r
+ Source32 = (CONST UINT32 *)((UINTN)SourceBuffer + Length);\r
\r
// Destination32 and Source32 were aligned on a 32-bit boundary\r
// but if length is not a multiple of 4 bytes then they won't be\r
\r
Alignment = Length & 0x3;\r
if (Alignment != 0) {\r
- Destination8 = (UINT8*)Destination32;\r
- Source8 = (CONST UINT8*)Source32;\r
+ Destination8 = (UINT8 *)Destination32;\r
+ Source8 = (CONST UINT8 *)Source32;\r
\r
while (Alignment-- != 0) {\r
*(--Destination8) = *(--Source8);\r
--Length;\r
}\r
- Destination32 = (UINT32*)Destination8;\r
- Source32 = (CONST UINT32*)Source8;\r
+\r
+ Destination32 = (UINT32 *)Destination8;\r
+ Source32 = (CONST UINT32 *)Source8;\r
}\r
\r
while (Length > 0) {\r
*(--Destination32) = *(--Source32);\r
- Length -= 4;\r
+ Length -= 4;\r
}\r
}\r
} else {\r
if (SourceBuffer > DestinationBuffer) {\r
- Destination8 = (UINT8*)DestinationBuffer;\r
- Source8 = (CONST UINT8*)SourceBuffer;\r
+ Destination8 = (UINT8 *)DestinationBuffer;\r
+ Source8 = (CONST UINT8 *)SourceBuffer;\r
while (Length-- != 0) {\r
*(Destination8++) = *(Source8++);\r
}\r
} else if (SourceBuffer < DestinationBuffer) {\r
- Destination8 = (UINT8*)DestinationBuffer + (Length - 1);\r
- Source8 = (CONST UINT8*)SourceBuffer + (Length - 1);\r
+ Destination8 = (UINT8 *)DestinationBuffer + (Length - 1);\r
+ Source8 = (CONST UINT8 *)SourceBuffer + (Length - 1);\r
while (Length-- != 0) {\r
*(Destination8--) = *(Source8--);\r
}\r
}\r
}\r
+\r
return DestinationBuffer;\r
}\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT16*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT16 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT32*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT32 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT64*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT64 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
return InternalMemSetMem (Buffer, Length, 0);\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
)\r
{\r
while ((--Length != 0) &&\r
- (*(INT8*)DestinationBuffer == *(INT8*)SourceBuffer)) {\r
- DestinationBuffer = (INT8*)DestinationBuffer + 1;\r
- SourceBuffer = (INT8*)SourceBuffer + 1;\r
+ (*(INT8 *)DestinationBuffer == *(INT8 *)SourceBuffer))\r
+ {\r
+ DestinationBuffer = (INT8 *)DestinationBuffer + 1;\r
+ SourceBuffer = (INT8 *)SourceBuffer + 1;\r
}\r
- return (INTN)*(UINT8*)DestinationBuffer - (INTN)*(UINT8*)SourceBuffer;\r
+\r
+ return (INTN)*(UINT8 *)DestinationBuffer - (INTN)*(UINT8 *)SourceBuffer;\r
}\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
)\r
{\r
- CONST UINT8 *Pointer;\r
+ CONST UINT8 *Pointer;\r
\r
- Pointer = (CONST UINT8*)Buffer;\r
+ Pointer = (CONST UINT8 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST UINT16 *Pointer;\r
+ CONST UINT16 *Pointer;\r
\r
- Pointer = (CONST UINT16*)Buffer;\r
+ Pointer = (CONST UINT16 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST UINT32 *Pointer;\r
+ CONST UINT32 *Pointer;\r
\r
- Pointer = (CONST UINT32*)Buffer;\r
+ Pointer = (CONST UINT32 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST UINT64 *Pointer;\r
+ CONST UINT64 *Pointer;\r
\r
- Pointer = (CONST UINT64*)Buffer;\r
+ Pointer = (CONST UINT64 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
IN UINTN Length\r
)\r
{\r
- CONST UINT8 *BufferData;\r
- UINTN Index;\r
+ CONST UINT8 *BufferData;\r
+ UINTN Index;\r
\r
BufferData = Buffer;\r
for (Index = 0; Index < Length; Index++) {\r
return FALSE;\r
}\r
}\r
+\r
return TRUE;\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
#include "MemLibInternals.h"\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
)\r
{\r
//\r
// volatile to prevent the optimizer from replacing this function with\r
// the intrinsic memset()\r
//\r
- volatile UINT8 *Pointer8;\r
- volatile UINT32 *Pointer32;\r
- volatile UINT64 *Pointer64;\r
- UINT32 Value32;\r
- UINT64 Value64;\r
+ volatile UINT8 *Pointer8;\r
+ volatile UINT32 *Pointer32;\r
+ volatile UINT64 *Pointer64;\r
+ UINT32 Value32;\r
+ UINT64 Value64;\r
\r
if ((((UINTN)Buffer & 0x7) == 0) && (Length >= 8)) {\r
// Generate the 64bit value\r
Value32 = (Value << 24) | (Value << 16) | (Value << 8) | Value;\r
Value64 = LShiftU64 (Value32, 32) | Value32;\r
\r
- Pointer64 = (UINT64*)Buffer;\r
+ Pointer64 = (UINT64 *)Buffer;\r
while (Length >= 8) {\r
*(Pointer64++) = Value64;\r
- Length -= 8;\r
+ Length -= 8;\r
}\r
\r
// Finish with bytes if needed\r
- Pointer8 = (UINT8*)Pointer64;\r
+ Pointer8 = (UINT8 *)Pointer64;\r
} else if ((((UINTN)Buffer & 0x3) == 0) && (Length >= 4)) {\r
// Generate the 32bit value\r
Value32 = (Value << 24) | (Value << 16) | (Value << 8) | Value;\r
\r
- Pointer32 = (UINT32*)Buffer;\r
+ Pointer32 = (UINT32 *)Buffer;\r
while (Length >= 4) {\r
*(Pointer32++) = Value32;\r
- Length -= 4;\r
+ Length -= 4;\r
}\r
\r
// Finish with bytes if needed\r
- Pointer8 = (UINT8*)Pointer32;\r
+ Pointer8 = (UINT8 *)Pointer32;\r
} else {\r
- Pointer8 = (UINT8*)Buffer;\r
+ Pointer8 = (UINT8 *)Buffer;\r
}\r
+\r
while (Length-- > 0) {\r
*(Pointer8++) = Value;\r
}\r
+\r
return Buffer;\r
}\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (InternalMemCompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST UINT16 *Pointer;\r
+ CONST UINT16 *Pointer;\r
\r
- Pointer = (CONST UINT16*)Buffer;\r
+ Pointer = (CONST UINT16 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST UINT32 *Pointer;\r
+ CONST UINT32 *Pointer;\r
\r
- Pointer = (CONST UINT32*)Buffer;\r
+ Pointer = (CONST UINT32 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST UINT64 *Pointer;\r
+ CONST UINT64 *Pointer;\r
\r
- Pointer = (CONST UINT64*)Buffer;\r
+ Pointer = (CONST UINT64 *)Buffer;\r
do {\r
if (*Pointer == Value) {\r
return Pointer;\r
}\r
+\r
++Pointer;\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
IN UINTN Length\r
)\r
{\r
- CONST UINT8 *BufferData;\r
- UINTN Index;\r
+ CONST UINT8 *BufferData;\r
+ UINTN Index;\r
\r
BufferData = Buffer;\r
for (Index = 0; Index < Length; Index++) {\r
return FALSE;\r
}\r
}\r
+\r
return TRUE;\r
}\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ OUT VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
// header. Beside completing the types, we introduce typedefs here that reflect\r
// the implementation closely.\r
//\r
-typedef ORDERED_COLLECTION RED_BLACK_TREE;\r
-typedef ORDERED_COLLECTION_ENTRY RED_BLACK_TREE_NODE;\r
-typedef ORDERED_COLLECTION_USER_COMPARE RED_BLACK_TREE_USER_COMPARE;\r
-typedef ORDERED_COLLECTION_KEY_COMPARE RED_BLACK_TREE_KEY_COMPARE;\r
+typedef ORDERED_COLLECTION RED_BLACK_TREE;\r
+typedef ORDERED_COLLECTION_ENTRY RED_BLACK_TREE_NODE;\r
+typedef ORDERED_COLLECTION_USER_COMPARE RED_BLACK_TREE_USER_COMPARE;\r
+typedef ORDERED_COLLECTION_KEY_COMPARE RED_BLACK_TREE_KEY_COMPARE;\r
\r
struct ORDERED_COLLECTION {\r
- RED_BLACK_TREE_NODE *Root;\r
- RED_BLACK_TREE_USER_COMPARE UserStructCompare;\r
- RED_BLACK_TREE_KEY_COMPARE KeyCompare;\r
+ RED_BLACK_TREE_NODE *Root;\r
+ RED_BLACK_TREE_USER_COMPARE UserStructCompare;\r
+ RED_BLACK_TREE_KEY_COMPARE KeyCompare;\r
};\r
\r
struct ORDERED_COLLECTION_ENTRY {\r
- VOID *UserStruct;\r
- RED_BLACK_TREE_NODE *Parent;\r
- RED_BLACK_TREE_NODE *Left;\r
- RED_BLACK_TREE_NODE *Right;\r
- RED_BLACK_TREE_COLOR Color;\r
+ VOID *UserStruct;\r
+ RED_BLACK_TREE_NODE *Parent;\r
+ RED_BLACK_TREE_NODE *Left;\r
+ RED_BLACK_TREE_NODE *Right;\r
+ RED_BLACK_TREE_COLOR Color;\r
};\r
\r
-\r
/**\r
Retrieve the user structure linked by the specified tree node.\r
\r
VOID *\r
EFIAPI\r
OrderedCollectionUserStruct (\r
- IN CONST RED_BLACK_TREE_NODE *Node\r
+ IN CONST RED_BLACK_TREE_NODE *Node\r
)\r
{\r
return Node->UserStruct;\r
**/\r
VOID\r
RedBlackTreeValidate (\r
- IN CONST RED_BLACK_TREE *Tree\r
+ IN CONST RED_BLACK_TREE *Tree\r
);\r
\r
-\r
/**\r
Allocate and initialize the RED_BLACK_TREE structure.\r
\r
RED_BLACK_TREE *\r
EFIAPI\r
OrderedCollectionInit (\r
- IN RED_BLACK_TREE_USER_COMPARE UserStructCompare,\r
- IN RED_BLACK_TREE_KEY_COMPARE KeyCompare\r
+ IN RED_BLACK_TREE_USER_COMPARE UserStructCompare,\r
+ IN RED_BLACK_TREE_KEY_COMPARE KeyCompare\r
)\r
{\r
- RED_BLACK_TREE *Tree;\r
+ RED_BLACK_TREE *Tree;\r
\r
Tree = AllocatePool (sizeof *Tree);\r
if (Tree == NULL) {\r
if (FeaturePcdGet (PcdValidateOrderedCollection)) {\r
RedBlackTreeValidate (Tree);\r
}\r
+\r
return Tree;\r
}\r
\r
-\r
/**\r
Check whether the tree is empty (has no nodes).\r
\r
BOOLEAN\r
EFIAPI\r
OrderedCollectionIsEmpty (\r
- IN CONST RED_BLACK_TREE *Tree\r
+ IN CONST RED_BLACK_TREE *Tree\r
)\r
{\r
return (BOOLEAN)(Tree->Root == NULL);\r
}\r
\r
-\r
/**\r
Uninitialize and release an empty RED_BLACK_TREE structure.\r
\r
VOID\r
EFIAPI\r
OrderedCollectionUninit (\r
- IN RED_BLACK_TREE *Tree\r
+ IN RED_BLACK_TREE *Tree\r
)\r
{\r
ASSERT (OrderedCollectionIsEmpty (Tree));\r
FreePool (Tree);\r
}\r
\r
-\r
/**\r
Look up the tree node that links the user structure that matches the\r
specified standalone key.\r
RED_BLACK_TREE_NODE *\r
EFIAPI\r
OrderedCollectionFind (\r
- IN CONST RED_BLACK_TREE *Tree,\r
- IN CONST VOID *StandaloneKey\r
+ IN CONST RED_BLACK_TREE *Tree,\r
+ IN CONST VOID *StandaloneKey\r
)\r
{\r
- RED_BLACK_TREE_NODE *Node;\r
+ RED_BLACK_TREE_NODE *Node;\r
\r
Node = Tree->Root;\r
while (Node != NULL) {\r
- INTN Result;\r
+ INTN Result;\r
\r
Result = Tree->KeyCompare (StandaloneKey, Node->UserStruct);\r
if (Result == 0) {\r
break;\r
}\r
+\r
Node = (Result < 0) ? Node->Left : Node->Right;\r
}\r
+\r
return Node;\r
}\r
\r
-\r
/**\r
Find the tree node of the minimum user structure stored in the tree.\r
\r
RED_BLACK_TREE_NODE *\r
EFIAPI\r
OrderedCollectionMin (\r
- IN CONST RED_BLACK_TREE *Tree\r
+ IN CONST RED_BLACK_TREE *Tree\r
)\r
{\r
- RED_BLACK_TREE_NODE *Node;\r
+ RED_BLACK_TREE_NODE *Node;\r
\r
Node = Tree->Root;\r
if (Node == NULL) {\r
return NULL;\r
}\r
+\r
while (Node->Left != NULL) {\r
Node = Node->Left;\r
}\r
+\r
return Node;\r
}\r
\r
-\r
/**\r
Find the tree node of the maximum user structure stored in the tree.\r
\r
RED_BLACK_TREE_NODE *\r
EFIAPI\r
OrderedCollectionMax (\r
- IN CONST RED_BLACK_TREE *Tree\r
+ IN CONST RED_BLACK_TREE *Tree\r
)\r
{\r
- RED_BLACK_TREE_NODE *Node;\r
+ RED_BLACK_TREE_NODE *Node;\r
\r
Node = Tree->Root;\r
if (Node == NULL) {\r
return NULL;\r
}\r
+\r
while (Node->Right != NULL) {\r
Node = Node->Right;\r
}\r
+\r
return Node;\r
}\r
\r
-\r
/**\r
Get the tree node of the least user structure that is greater than the one\r
linked by Node.\r
RED_BLACK_TREE_NODE *\r
EFIAPI\r
OrderedCollectionNext (\r
- IN CONST RED_BLACK_TREE_NODE *Node\r
+ IN CONST RED_BLACK_TREE_NODE *Node\r
)\r
{\r
- RED_BLACK_TREE_NODE *Walk;\r
- CONST RED_BLACK_TREE_NODE *Child;\r
+ RED_BLACK_TREE_NODE *Walk;\r
+ CONST RED_BLACK_TREE_NODE *Child;\r
\r
if (Node == NULL) {\r
return NULL;\r
while (Walk->Left != NULL) {\r
Walk = Walk->Left;\r
}\r
+\r
return Walk;\r
}\r
\r
// ascending to the left).\r
//\r
Child = Node;\r
- Walk = Child->Parent;\r
+ Walk = Child->Parent;\r
while (Walk != NULL && Child == Walk->Right) {\r
Child = Walk;\r
- Walk = Child->Parent;\r
+ Walk = Child->Parent;\r
}\r
+\r
return Walk;\r
}\r
\r
-\r
/**\r
Get the tree node of the greatest user structure that is less than the one\r
linked by Node.\r
RED_BLACK_TREE_NODE *\r
EFIAPI\r
OrderedCollectionPrev (\r
- IN CONST RED_BLACK_TREE_NODE *Node\r
+ IN CONST RED_BLACK_TREE_NODE *Node\r
)\r
{\r
- RED_BLACK_TREE_NODE *Walk;\r
- CONST RED_BLACK_TREE_NODE *Child;\r
+ RED_BLACK_TREE_NODE *Walk;\r
+ CONST RED_BLACK_TREE_NODE *Child;\r
\r
if (Node == NULL) {\r
return NULL;\r
while (Walk->Right != NULL) {\r
Walk = Walk->Right;\r
}\r
+\r
return Walk;\r
}\r
\r
// ascending to the right).\r
//\r
Child = Node;\r
- Walk = Child->Parent;\r
+ Walk = Child->Parent;\r
while (Walk != NULL && Child == Walk->Left) {\r
Child = Walk;\r
- Walk = Child->Parent;\r
+ Walk = Child->Parent;\r
}\r
+\r
return Walk;\r
}\r
\r
-\r
/**\r
Rotate tree nodes around Pivot to the right.\r
\r
**/\r
VOID\r
RedBlackTreeRotateRight (\r
- IN OUT RED_BLACK_TREE_NODE *Pivot,\r
- OUT RED_BLACK_TREE_NODE **NewRoot\r
+ IN OUT RED_BLACK_TREE_NODE *Pivot,\r
+ OUT RED_BLACK_TREE_NODE **NewRoot\r
)\r
{\r
- RED_BLACK_TREE_NODE *Parent;\r
- RED_BLACK_TREE_NODE *LeftChild;\r
- RED_BLACK_TREE_NODE *LeftRightChild;\r
+ RED_BLACK_TREE_NODE *Parent;\r
+ RED_BLACK_TREE_NODE *LeftChild;\r
+ RED_BLACK_TREE_NODE *LeftRightChild;\r
\r
Parent = Pivot->Parent;\r
LeftChild = Pivot->Left;\r
if (LeftRightChild != NULL) {\r
LeftRightChild->Parent = Pivot;\r
}\r
+\r
LeftChild->Parent = Parent;\r
if (Parent == NULL) {\r
*NewRoot = LeftChild;\r
Parent->Right = LeftChild;\r
}\r
}\r
+\r
LeftChild->Right = Pivot;\r
- Pivot->Parent = LeftChild;\r
+ Pivot->Parent = LeftChild;\r
}\r
\r
-\r
/**\r
Rotate tree nodes around Pivot to the left.\r
\r
**/\r
VOID\r
RedBlackTreeRotateLeft (\r
- IN OUT RED_BLACK_TREE_NODE *Pivot,\r
- OUT RED_BLACK_TREE_NODE **NewRoot\r
+ IN OUT RED_BLACK_TREE_NODE *Pivot,\r
+ OUT RED_BLACK_TREE_NODE **NewRoot\r
)\r
{\r
- RED_BLACK_TREE_NODE *Parent;\r
- RED_BLACK_TREE_NODE *RightChild;\r
- RED_BLACK_TREE_NODE *RightLeftChild;\r
+ RED_BLACK_TREE_NODE *Parent;\r
+ RED_BLACK_TREE_NODE *RightChild;\r
+ RED_BLACK_TREE_NODE *RightLeftChild;\r
\r
Parent = Pivot->Parent;\r
RightChild = Pivot->Right;\r
if (RightLeftChild != NULL) {\r
RightLeftChild->Parent = Pivot;\r
}\r
+\r
RightChild->Parent = Parent;\r
if (Parent == NULL) {\r
*NewRoot = RightChild;\r
Parent->Right = RightChild;\r
}\r
}\r
+\r
RightChild->Left = Pivot;\r
- Pivot->Parent = RightChild;\r
+ Pivot->Parent = RightChild;\r
}\r
\r
-\r
/**\r
Insert (link) a user structure into the tree.\r
\r
RETURN_STATUS\r
EFIAPI\r
OrderedCollectionInsert (\r
- IN OUT RED_BLACK_TREE *Tree,\r
- OUT RED_BLACK_TREE_NODE **Node OPTIONAL,\r
- IN VOID *UserStruct\r
+ IN OUT RED_BLACK_TREE *Tree,\r
+ OUT RED_BLACK_TREE_NODE **Node OPTIONAL,\r
+ IN VOID *UserStruct\r
)\r
{\r
- RED_BLACK_TREE_NODE *Tmp;\r
- RED_BLACK_TREE_NODE *Parent;\r
- INTN Result;\r
- RETURN_STATUS Status;\r
- RED_BLACK_TREE_NODE *NewRoot;\r
+ RED_BLACK_TREE_NODE *Tmp;\r
+ RED_BLACK_TREE_NODE *Parent;\r
+ INTN Result;\r
+ RETURN_STATUS Status;\r
+ RED_BLACK_TREE_NODE *NewRoot;\r
\r
- Tmp = Tree->Root;\r
+ Tmp = Tree->Root;\r
Parent = NULL;\r
Result = 0;\r
\r
if (Result == 0) {\r
break;\r
}\r
+\r
Parent = Tmp;\r
- Tmp = (Result < 0) ? Tmp->Left : Tmp->Right;\r
+ Tmp = (Result < 0) ? Tmp->Left : Tmp->Right;\r
}\r
\r
if (Tmp != NULL) {\r
if (Node != NULL) {\r
*Node = Tmp;\r
}\r
+\r
Status = RETURN_ALREADY_STARTED;\r
goto Done;\r
}\r
Status = RETURN_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
+\r
if (Node != NULL) {\r
*Node = Tmp;\r
}\r
// If there's no parent, the new node is the root node in the tree.\r
//\r
Tmp->Parent = Parent;\r
- Tmp->Left = NULL;\r
- Tmp->Right = NULL;\r
+ Tmp->Left = NULL;\r
+ Tmp->Right = NULL;\r
if (Parent == NULL) {\r
Tree->Root = Tmp;\r
Tmp->Color = RedBlackTreeBlack;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
goto Done;\r
}\r
+\r
if (Result < 0) {\r
Parent->Left = Tmp;\r
} else {\r
Parent->Right = Tmp;\r
}\r
+\r
Tmp->Color = RedBlackTreeRed;\r
\r
//\r
\r
NewRoot = Tree->Root;\r
while (Tmp != NewRoot && Parent->Color == RedBlackTreeRed) {\r
- RED_BLACK_TREE_NODE *GrandParent;\r
- RED_BLACK_TREE_NODE *Uncle;\r
+ RED_BLACK_TREE_NODE *GrandParent;\r
+ RED_BLACK_TREE_NODE *Uncle;\r
\r
//\r
// Tmp is not the root node. Tmp is red. Tmp's parent is red. (Breaking\r
\r
if (Parent == GrandParent->Left) {\r
Uncle = GrandParent->Right;\r
- if (Uncle != NULL && Uncle->Color == RedBlackTreeRed) {\r
+ if ((Uncle != NULL) && (Uncle->Color == RedBlackTreeRed)) {\r
//\r
// GrandParent (black)\r
// / \_\r
// Tmp (red)\r
//\r
\r
- Parent->Color = RedBlackTreeBlack;\r
- Uncle->Color = RedBlackTreeBlack;\r
+ Parent->Color = RedBlackTreeBlack;\r
+ Uncle->Color = RedBlackTreeBlack;\r
GrandParent->Color = RedBlackTreeRed;\r
\r
//\r
// and we will have broken property #5, by coloring the root red. We'll\r
// restore property #5 after the loop, without breaking any others.\r
//\r
- Tmp = GrandParent;\r
+ Tmp = GrandParent;\r
Parent = Tmp->Parent;\r
} else {\r
//\r
ASSERT (GrandParent == Parent->Parent);\r
}\r
\r
- Parent->Color = RedBlackTreeBlack;\r
+ Parent->Color = RedBlackTreeBlack;\r
GrandParent->Color = RedBlackTreeRed;\r
\r
//\r
// Symmetrical to the other branch.\r
//\r
Uncle = GrandParent->Left;\r
- if (Uncle != NULL && Uncle->Color == RedBlackTreeRed) {\r
- Parent->Color = RedBlackTreeBlack;\r
- Uncle->Color = RedBlackTreeBlack;\r
+ if ((Uncle != NULL) && (Uncle->Color == RedBlackTreeRed)) {\r
+ Parent->Color = RedBlackTreeBlack;\r
+ Uncle->Color = RedBlackTreeBlack;\r
GrandParent->Color = RedBlackTreeRed;\r
- Tmp = GrandParent;\r
- Parent = Tmp->Parent;\r
+ Tmp = GrandParent;\r
+ Parent = Tmp->Parent;\r
} else {\r
if (Tmp == Parent->Left) {\r
Tmp = Parent;\r
Parent = Tmp->Parent;\r
ASSERT (GrandParent == Parent->Parent);\r
}\r
- Parent->Color = RedBlackTreeBlack;\r
+\r
+ Parent->Color = RedBlackTreeBlack;\r
GrandParent->Color = RedBlackTreeRed;\r
RedBlackTreeRotateLeft (GrandParent, &NewRoot);\r
}\r
}\r
\r
NewRoot->Color = RedBlackTreeBlack;\r
- Tree->Root = NewRoot;\r
- Status = RETURN_SUCCESS;\r
+ Tree->Root = NewRoot;\r
+ Status = RETURN_SUCCESS;\r
\r
Done:\r
if (FeaturePcdGet (PcdValidateOrderedCollection)) {\r
RedBlackTreeValidate (Tree);\r
}\r
+\r
return Status;\r
}\r
\r
-\r
/**\r
Check if a node is black, allowing for leaf nodes (see property #2).\r
\r
**/\r
BOOLEAN\r
NodeIsNullOrBlack (\r
- IN CONST RED_BLACK_TREE_NODE *Node\r
+ IN CONST RED_BLACK_TREE_NODE *Node\r
)\r
{\r
return (BOOLEAN)(Node == NULL || Node->Color == RedBlackTreeBlack);\r
}\r
\r
-\r
/**\r
Delete a node from the tree, unlinking the associated user structure.\r
\r
VOID\r
EFIAPI\r
OrderedCollectionDelete (\r
- IN OUT RED_BLACK_TREE *Tree,\r
- IN RED_BLACK_TREE_NODE *Node,\r
- OUT VOID **UserStruct OPTIONAL\r
+ IN OUT RED_BLACK_TREE *Tree,\r
+ IN RED_BLACK_TREE_NODE *Node,\r
+ OUT VOID **UserStruct OPTIONAL\r
)\r
{\r
- RED_BLACK_TREE_NODE *NewRoot;\r
- RED_BLACK_TREE_NODE *OrigLeftChild;\r
- RED_BLACK_TREE_NODE *OrigRightChild;\r
- RED_BLACK_TREE_NODE *OrigParent;\r
- RED_BLACK_TREE_NODE *Child;\r
- RED_BLACK_TREE_NODE *Parent;\r
- RED_BLACK_TREE_COLOR ColorOfUnlinked;\r
+ RED_BLACK_TREE_NODE *NewRoot;\r
+ RED_BLACK_TREE_NODE *OrigLeftChild;\r
+ RED_BLACK_TREE_NODE *OrigRightChild;\r
+ RED_BLACK_TREE_NODE *OrigParent;\r
+ RED_BLACK_TREE_NODE *Child;\r
+ RED_BLACK_TREE_NODE *Parent;\r
+ RED_BLACK_TREE_COLOR ColorOfUnlinked;\r
\r
NewRoot = Tree->Root;\r
OrigLeftChild = Node->Left,\r
// - Parent will point to the *position* of the original parent of the node\r
// that we will have unlinked.\r
//\r
- if (OrigLeftChild == NULL || OrigRightChild == NULL) {\r
+ if ((OrigLeftChild == NULL) || (OrigRightChild == NULL)) {\r
//\r
// Node has at most one child. We can connect that child (if any) with\r
// Node's parent (if any), unlinking Node. This will preserve ordering\r
// because the subtree rooted in Node's child (if any) remains on the same\r
// side of Node's parent (if any) that Node was before.\r
//\r
- Parent = OrigParent;\r
- Child = (OrigLeftChild != NULL) ? OrigLeftChild : OrigRightChild;\r
+ Parent = OrigParent;\r
+ Child = (OrigLeftChild != NULL) ? OrigLeftChild : OrigRightChild;\r
ColorOfUnlinked = Node->Color;\r
\r
if (Child != NULL) {\r
Child->Parent = Parent;\r
}\r
+\r
if (OrigParent == NULL) {\r
NewRoot = Child;\r
} else {\r
// of Node's parent as Node itself. The relinking doesn't change this\r
// relation.\r
//\r
- RED_BLACK_TREE_NODE *ToRelink;\r
+ RED_BLACK_TREE_NODE *ToRelink;\r
\r
ToRelink = OrigRightChild;\r
if (ToRelink->Left == NULL) {\r
// F <--- Child\r
//\r
Parent = OrigRightChild;\r
- Child = OrigRightChild->Right;\r
+ Child = OrigRightChild->Right;\r
} else {\r
do {\r
ToRelink = ToRelink->Left;\r
// \_\r
// D <--- Child\r
Parent = ToRelink->Parent;\r
- Child = ToRelink->Right;\r
+ Child = ToRelink->Right;\r
\r
//\r
// Unlink Node's successor (ie. ToRelink):\r
//\r
//\r
//\r
- ToRelink->Right = OrigRightChild;\r
+ ToRelink->Right = OrigRightChild;\r
OrigRightChild->Parent = ToRelink;\r
}\r
\r
// | D <--- Child\r
// Child\r
//\r
- ToRelink->Left = OrigLeftChild;\r
+ ToRelink->Left = OrigLeftChild;\r
OrigLeftChild->Parent = ToRelink;\r
\r
//\r
// Rotations in the loop preserve property #4.\r
//\r
while (Child != NewRoot && NodeIsNullOrBlack (Child)) {\r
- RED_BLACK_TREE_NODE *Sibling;\r
- RED_BLACK_TREE_NODE *LeftNephew;\r
- RED_BLACK_TREE_NODE *RightNephew;\r
+ RED_BLACK_TREE_NODE *Sibling;\r
+ RED_BLACK_TREE_NODE *LeftNephew;\r
+ RED_BLACK_TREE_NODE *RightNephew;\r
\r
if (Child == Parent->Left) {\r
Sibling = Parent->Right;\r
// b:C b:E Child,2b:A Sibling,b:C\r
//\r
Sibling->Color = RedBlackTreeBlack;\r
- Parent->Color = RedBlackTreeRed;\r
+ Parent->Color = RedBlackTreeRed;\r
RedBlackTreeRotateLeft (Parent, &NewRoot);\r
Sibling = Parent->Right;\r
//\r
// node.)\r
//\r
ASSERT (Sibling->Color == RedBlackTreeBlack);\r
- LeftNephew = Sibling->Left;\r
+ LeftNephew = Sibling->Left;\r
RightNephew = Sibling->Right;\r
if (NodeIsNullOrBlack (LeftNephew) &&\r
- NodeIsNullOrBlack (RightNephew)) {\r
+ NodeIsNullOrBlack (RightNephew))\r
+ {\r
//\r
// In this case we can "steal" one black value from Child and Sibling\r
// each, and pass it to Parent. "Stealing" means that Sibling (black\r
// LeftNephew,b:C RightNephew,b:E b:C b:E\r
//\r
Sibling->Color = RedBlackTreeRed;\r
- Child = Parent;\r
- Parent = Parent->Parent;\r
+ Child = Parent;\r
+ Parent = Parent->Parent;\r
//\r
// Continue ascending.\r
//\r
// b:C b:E b:E b:G\r
//\r
LeftNephew->Color = RedBlackTreeBlack;\r
- Sibling->Color = RedBlackTreeRed;\r
+ Sibling->Color = RedBlackTreeRed;\r
RedBlackTreeRotateRight (Sibling, &NewRoot);\r
- Sibling = Parent->Right;\r
+ Sibling = Parent->Right;\r
RightNephew = Sibling->Right;\r
//\r
// These operations ensure that...\r
//\r
}\r
+\r
//\r
// ... RightNephew is definitely red here, plus Sibling is (still)\r
// black and non-NULL.\r
// y:C RightNephew,r:E b:A y:C\r
//\r
//\r
- Sibling->Color = Parent->Color;\r
- Parent->Color = RedBlackTreeBlack;\r
+ Sibling->Color = Parent->Color;\r
+ Parent->Color = RedBlackTreeBlack;\r
RightNephew->Color = RedBlackTreeBlack;\r
RedBlackTreeRotateLeft (Parent, &NewRoot);\r
Child = NewRoot;\r
ASSERT (Sibling != NULL);\r
if (Sibling->Color == RedBlackTreeRed) {\r
Sibling->Color = RedBlackTreeBlack;\r
- Parent->Color = RedBlackTreeRed;\r
+ Parent->Color = RedBlackTreeRed;\r
RedBlackTreeRotateRight (Parent, &NewRoot);\r
Sibling = Parent->Left;\r
ASSERT (Sibling != NULL);\r
\r
ASSERT (Sibling->Color == RedBlackTreeBlack);\r
RightNephew = Sibling->Right;\r
- LeftNephew = Sibling->Left;\r
+ LeftNephew = Sibling->Left;\r
if (NodeIsNullOrBlack (RightNephew) &&\r
- NodeIsNullOrBlack (LeftNephew)) {\r
+ NodeIsNullOrBlack (LeftNephew))\r
+ {\r
Sibling->Color = RedBlackTreeRed;\r
- Child = Parent;\r
- Parent = Parent->Parent;\r
+ Child = Parent;\r
+ Parent = Parent->Parent;\r
} else {\r
if (NodeIsNullOrBlack (LeftNephew)) {\r
RightNephew->Color = RedBlackTreeBlack;\r
- Sibling->Color = RedBlackTreeRed;\r
+ Sibling->Color = RedBlackTreeRed;\r
RedBlackTreeRotateLeft (Sibling, &NewRoot);\r
- Sibling = Parent->Left;\r
+ Sibling = Parent->Left;\r
LeftNephew = Sibling->Left;\r
}\r
+\r
ASSERT (LeftNephew != NULL);\r
ASSERT (LeftNephew->Color == RedBlackTreeRed);\r
ASSERT (Sibling != NULL);\r
ASSERT (Sibling->Color == RedBlackTreeBlack);\r
- Sibling->Color = Parent->Color;\r
- Parent->Color = RedBlackTreeBlack;\r
+ Sibling->Color = Parent->Color;\r
+ Parent->Color = RedBlackTreeBlack;\r
LeftNephew->Color = RedBlackTreeBlack;\r
RedBlackTreeRotateRight (Parent, &NewRoot);\r
Child = NewRoot;\r
}\r
}\r
\r
-\r
/**\r
Recursively check the red-black tree properties #1 to #4 on a node.\r
\r
**/\r
UINT32\r
RedBlackTreeRecursiveCheck (\r
- IN CONST RED_BLACK_TREE_NODE *Node\r
+ IN CONST RED_BLACK_TREE_NODE *Node\r
)\r
{\r
- UINT32 LeftHeight;\r
- UINT32 RightHeight;\r
+ UINT32 LeftHeight;\r
+ UINT32 RightHeight;\r
\r
//\r
// property #2\r
//\r
// property #4\r
//\r
- LeftHeight = RedBlackTreeRecursiveCheck (Node->Left);\r
+ LeftHeight = RedBlackTreeRecursiveCheck (Node->Left);\r
RightHeight = RedBlackTreeRecursiveCheck (Node->Right);\r
ASSERT (LeftHeight == RightHeight);\r
\r
return (Node->Color == RedBlackTreeBlack) + LeftHeight;\r
}\r
\r
-\r
/**\r
A slow function that asserts that the tree is a valid red-black tree, and\r
that it orders user structures correctly.\r
**/\r
VOID\r
RedBlackTreeValidate (\r
- IN CONST RED_BLACK_TREE *Tree\r
+ IN CONST RED_BLACK_TREE *Tree\r
)\r
{\r
- UINT32 BlackHeight;\r
- UINT32 ForwardCount;\r
- UINT32 BackwardCount;\r
- CONST RED_BLACK_TREE_NODE *Last;\r
- CONST RED_BLACK_TREE_NODE *Node;\r
+ UINT32 BlackHeight;\r
+ UINT32 ForwardCount;\r
+ UINT32 BackwardCount;\r
+ CONST RED_BLACK_TREE_NODE *Last;\r
+ CONST RED_BLACK_TREE_NODE *Node;\r
\r
DEBUG ((DEBUG_VERBOSE, "%a: Tree=%p\n", __FUNCTION__, Tree));\r
\r
//\r
// forward ordering\r
//\r
- Last = OrderedCollectionMin (Tree);\r
+ Last = OrderedCollectionMin (Tree);\r
ForwardCount = (Last != NULL);\r
for (Node = OrderedCollectionNext (Last); Node != NULL;\r
- Node = OrderedCollectionNext (Last)) {\r
+ Node = OrderedCollectionNext (Last))\r
+ {\r
ASSERT (Tree->UserStructCompare (Last->UserStruct, Node->UserStruct) < 0);\r
Last = Node;\r
++ForwardCount;\r
//\r
// backward ordering\r
//\r
- Last = OrderedCollectionMax (Tree);\r
+ Last = OrderedCollectionMax (Tree);\r
BackwardCount = (Last != NULL);\r
for (Node = OrderedCollectionPrev (Last); Node != NULL;\r
- Node = OrderedCollectionPrev (Last)) {\r
+ Node = OrderedCollectionPrev (Last))\r
+ {\r
ASSERT (Tree->UserStructCompare (Last->UserStruct, Node->UserStruct) > 0);\r
Last = Node;\r
++BackwardCount;\r
\r
ASSERT (ForwardCount == BackwardCount);\r
\r
- DEBUG ((DEBUG_VERBOSE, "%a: Tree=%p BlackHeight=%Ld Count=%Ld\n",\r
- __FUNCTION__, Tree, (INT64)BlackHeight, (INT64)ForwardCount));\r
+ DEBUG ((\r
+ DEBUG_VERBOSE,\r
+ "%a: Tree=%p BlackHeight=%Ld Count=%Ld\n",\r
+ __FUNCTION__,\r
+ Tree,\r
+ (INT64)BlackHeight,\r
+ (INT64)ForwardCount\r
+ ));\r
}\r
#include <Library/PcdLib.h>\r
#include <Library/BaseMemoryLib.h>\r
\r
-\r
/**\r
This function provides a means by which SKU support can be established in the PCD infrastructure.\r
\r
UINTN\r
EFIAPI\r
LibPcdSetSku (\r
- IN UINTN SkuId\r
+ IN UINTN SkuId\r
)\r
{\r
ASSERT (FALSE);\r
UINT8\r
EFIAPI\r
LibPcdGet8 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGet16 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT32\r
EFIAPI\r
LibPcdGet32 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGet64 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetPtr (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetBool (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetSize (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGetEx8 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGetEx16 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
Returns the 32-bit value for the token specified by TokenNumber and Guid.\r
If Guid is NULL, then ASSERT().\r
UINT32\r
EFIAPI\r
LibPcdGetEx32 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGetEx64 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetExPtr (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetExBool (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetExSize (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
/**\r
This function provides a means by which to set a value for a given PCD token.\r
\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet8S (\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet16S (\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet32S (\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet64S (\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetPtrS (\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetBoolS (\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx8S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx16S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx32S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx64S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExPtrS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN VOID *Buffer\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (FALSE);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExBoolS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
LibPcdCallbackOnSet (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
ASSERT (FALSE);\r
}\r
\r
-\r
-\r
/**\r
Disable a notification function that was established with LibPcdCallbackonSet().\r
\r
VOID\r
EFIAPI\r
LibPcdCancelCallback (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
ASSERT (FALSE);\r
}\r
\r
-\r
-\r
/**\r
Retrieves the next token in a token space.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetNextToken (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (FALSE);\r
return 0;\r
}\r
\r
-\r
-\r
/**\r
Used to retrieve the list of available PCD token space GUIDs.\r
\r
return NULL;\r
}\r
\r
-\r
/**\r
Sets a value of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtr (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrS (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtrAndSize (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
*SizeOfPatchVariable = *SizeOfBuffer;\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrAndSizeS (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
VOID\r
EFIAPI\r
LibPcdGetInfo (\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
LibPcdGetInfoEx (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
ASSERT (FALSE);\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/BaseLib.h>\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r
ASSERT (((A) & (~0xffff0ff | (M))) == 0)\r
\r
/**\r
UINT8\r
EFIAPI\r
PciCf8Read8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
UINT8\r
EFIAPI\r
PciCf8Write8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoWrite8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8Or8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoOr8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8And8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAnd8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8AndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAndThenOr8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8BitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldRead8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8BitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldWrite8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8BitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldOr8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT8\r
EFIAPI\r
PciCf8BitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAnd8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
**/\r
UINT8\r
EFIAPI\r
-PciCf8BitFieldAndThenOr8(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+PciCf8BitFieldAndThenOr8 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAndThenOr8 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r
UINT16\r
EFIAPI\r
PciCf8Read16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
UINT16\r
EFIAPI\r
PciCf8Write16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoWrite16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8Or16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoOr16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8And16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAnd16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8AndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAndThenOr16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8BitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldRead16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8BitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldWrite16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8BitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldOr16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT16\r
EFIAPI\r
PciCf8BitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAnd16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
**/\r
UINT16\r
EFIAPI\r
-PciCf8BitFieldAndThenOr16(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+PciCf8BitFieldAndThenOr16 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAndThenOr16 (\r
PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r
UINT32\r
EFIAPI\r
PciCf8Read32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoRead32 (PCI_CONFIGURATION_DATA_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
UINT32\r
EFIAPI\r
PciCf8Write32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoWrite32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8Or32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoOr32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8And32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAnd32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8AndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoAndThenOr32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8BitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldRead32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8BitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldWrite32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8BitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldOr32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
UINT32\r
EFIAPI\r
PciCf8BitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAnd32 (\r
PCI_CONFIGURATION_DATA_PORT,\r
**/\r
UINT32\r
EFIAPI\r
-PciCf8BitFieldAndThenOr32(\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+PciCf8BitFieldAndThenOr32 (\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
BOOLEAN InterruptState;\r
\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
InterruptState = SaveAndDisableInterrupts ();\r
- AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
+ AddressPort = IoRead32 (PCI_CONFIGURATION_ADDRESS_PORT);\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r
Result = IoBitFieldAndThenOr32 (\r
- PCI_CONFIGURATION_DATA_PORT,\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ PCI_CONFIGURATION_DATA_PORT,\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, AddressPort);\r
SetInterruptState (InterruptState);\r
return Result;\r
UINTN\r
EFIAPI\r
PciCf8ReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
- WriteUnaligned16 ((UINT16 *)Buffer, (UINT16) PciCf8Read16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciCf8Read16 (StartAddress));\r
\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Read as many double words as possible\r
//\r
- WriteUnaligned32 ((UINT32 *)Buffer, (UINT32) PciCf8Read32 (StartAddress));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciCf8Read32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Read the last remaining word if exist\r
//\r
- WriteUnaligned16 ((UINT16 *)Buffer, (UINT16) PciCf8Read16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciCf8Read16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciCf8WriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r
+ PciCf8Write8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
- PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Write as many double words as possible\r
//\r
- PciCf8Write32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ PciCf8Write32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Write the last remaining word if exist\r
//\r
- PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciCf8Write16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r
+ PciCf8Write8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
-\r
/**\r
Assert the validity of a PCI address. A valid PCI address should contain 1's\r
only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real\r
@return The base address of PCI Express.\r
\r
**/\r
-VOID*\r
+VOID *\r
GetPciExpressBaseAddress (\r
VOID\r
)\r
{\r
- return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
+ return (VOID *)(UINTN)PcdGet64 (PcdPciExpressBaseAddress);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- return (UINTN) PcdGet64 (PcdPciExpressBaseSize);\r
+ return (UINTN)PcdGet64 (PcdPciExpressBaseSize);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
- return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+\r
+ return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
- return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+\r
+ return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
- return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+\r
+ return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
- return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+\r
+ return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldRead8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldWrite8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldAnd8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT8) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr8 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
- return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+\r
+ return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
- return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+\r
+ return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
- return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+\r
+ return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
- return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+\r
+ return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldRead16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldWrite16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldAnd16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT16) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr16 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
- return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r
+\r
+ return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
- return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r
+\r
+ return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
- return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r
+\r
+ return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
- return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r
+\r
+ return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
AndData,\r
OrData\r
);\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldRead32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit\r
);\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldWrite32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
Value\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
OrData\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldAnd32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
- if (Address >= PcdPciExpressBaseSize()) {\r
- return (UINT32) -1;\r
+ if (Address >= PcdPciExpressBaseSize ()) {\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr32 (\r
- (UINTN) GetPciExpressBaseAddress () + Address,\r
+ (UINTN)GetPciExpressBaseAddress () + Address,\r
StartBit,\r
EndBit,\r
AndData,\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- if (StartAddress >= PcdPciExpressBaseSize()) {\r
- return (UINTN) -1;\r
+ if (StartAddress >= PcdPciExpressBaseSize ()) {\r
+ return (UINTN)-1;\r
}\r
+\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Read as many double words as possible\r
//\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r
\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Read the last remaining word if exist\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- if (StartAddress >= PcdPciExpressBaseSize()) {\r
- return (UINTN) -1;\r
+ if (StartAddress >= PcdPciExpressBaseSize ()) {\r
+ return (UINTN)-1;\r
}\r
+\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
if (Size == 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Write as many double words as possible\r
//\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Write the last remaining word if exist\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/PciLib.h>\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciCf8Read8 (Address);\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return PciCf8Write8 (Address, Value);\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciCf8Or8 (Address, OrData);\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciCf8And8 (Address, AndData);\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciCf8AndThenOr8 (Address, AndData, OrData);\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciCf8Read16 (Address);\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
return PciCf8Write16 (Address, Value);\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciCf8Or16 (Address, OrData);\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciCf8And16 (Address, AndData);\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciCf8AndThenOr16 (Address, AndData, OrData);\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciCf8Read32 (Address);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
return PciCf8Write32 (Address, Value);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciCf8Or32 (Address, OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciCf8And32 (Address, AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciCf8AndThenOr32 (Address, AndData, OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
return PciCf8ReadBuffer (StartAddress, Size, Buffer);\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
return PciCf8WriteBuffer (StartAddress, Size, Buffer);\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/PciLib.h>\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciExpressRead8 (Address);\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return PciExpressWrite8 (Address, Value);\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciExpressOr8 (Address, OrData);\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciExpressAnd8 (Address, AndData);\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciExpressAndThenOr8 (Address, AndData, OrData);\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciExpressRead16 (Address);\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
return PciExpressWrite16 (Address, Value);\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciExpressOr16 (Address, OrData);\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciExpressAnd16 (Address, AndData);\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciExpressAndThenOr16 (Address, AndData, OrData);\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return PciExpressRead32 (Address);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
return PciExpressWrite32 (Address, Value);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciExpressOr32 (Address, OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciExpressAnd32 (Address, AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciExpressAndThenOr32 (Address, AndData, OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
return PciExpressReadBuffer (StartAddress, Size, Buffer);\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \\r
ASSERT (((A) & (0xfffffffff0000000ULL | (M))) == 0)\r
\r
/**\r
\r
@param A The address to convert.\r
**/\r
-#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) A)\r
+#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) A)\r
\r
/**\r
Register a PCI device so PCI configuration registers may be accessed after\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8) (PciSegmentRead8 (Address) | OrData));\r
+ return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*) Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*) Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*) Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*) Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/PeCoffGetEntryPointLib.h>\r
\r
#include <IndustryStandard/PeImage.h>\r
\r
-#define PE_COFF_IMAGE_ALIGN_SIZE 4\r
+#define PE_COFF_IMAGE_ALIGN_SIZE 4\r
\r
/**\r
Retrieves and returns a pointer to the entry point to a PE/COFF image that has been loaded\r
OUT VOID **EntryPoint\r
)\r
{\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_DOS_HEADER *DosHdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
\r
ASSERT (Pe32Data != NULL);\r
ASSERT (EntryPoint != NULL);\r
//\r
// DOS image header is present, so read the PE header after the DOS image header.\r
//\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)Pe32Data + (UINTN)((DosHdr->e_lfanew) & 0x0ffff));\r
} else {\r
//\r
// DOS image header is not present, so PE header is at the image base.\r
// AddressOfEntryPoint is common for PE32 & PE32+\r
//\r
if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {\r
- *EntryPoint = (VOID *)((UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
+ *EntryPoint = (VOID *)((UINTN)Pe32Data + (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) + sizeof (EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
return RETURN_SUCCESS;\r
} else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
*EntryPoint = (VOID *)((UINTN)Pe32Data + (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));\r
return RETURN_UNSUPPORTED;\r
}\r
\r
-\r
/**\r
Returns the machine type of a PE/COFF image.\r
\r
//\r
// DOS image header is present, so read the PE header after the DOS image header.\r
//\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)Pe32Data + (UINTN)((DosHdr->e_lfanew) & 0x0ffff));\r
} else {\r
//\r
// DOS image header is not present, so PE header is at the image base.\r
\r
if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {\r
return Hdr.Te->Machine;\r
- } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
+ } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
return Hdr.Pe32->FileHeader.Machine;\r
}\r
\r
IN VOID *Pe32Data\r
)\r
{\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- EFI_IMAGE_DATA_DIRECTORY *DirectoryEntry;\r
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
- UINTN DirCount;\r
- VOID *CodeViewEntryPointer;\r
- INTN TEImageAdjust;\r
- UINT32 NumberOfRvaAndSizes;\r
- UINT16 Magic;\r
+ EFI_IMAGE_DOS_HEADER *DosHdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_DATA_DIRECTORY *DirectoryEntry;\r
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
+ UINTN DirCount;\r
+ VOID *CodeViewEntryPointer;\r
+ INTN TEImageAdjust;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ UINT16 Magic;\r
\r
ASSERT (Pe32Data != NULL);\r
\r
//\r
// DOS image header is present, so read the PE header after the DOS image header.\r
//\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)Pe32Data + (UINTN)((DosHdr->e_lfanew) & 0x0ffff));\r
} else {\r
//\r
// DOS image header is not present, so PE header is at the image base.\r
\r
if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {\r
if (Hdr.Te->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG].VirtualAddress != 0) {\r
- DirectoryEntry = &Hdr.Te->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG];\r
- TEImageAdjust = sizeof (EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;\r
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)((UINTN) Hdr.Te +\r
- Hdr.Te->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG].VirtualAddress +\r
- TEImageAdjust);\r
+ DirectoryEntry = &Hdr.Te->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG];\r
+ TEImageAdjust = sizeof (EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize;\r
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)((UINTN)Hdr.Te +\r
+ Hdr.Te->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG].VirtualAddress +\r
+ TEImageAdjust);\r
}\r
} else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
//\r
// generate PE32+ image with PE32 Magic.\r
//\r
switch (Hdr.Pe32->FileHeader.Machine) {\r
- case IMAGE_FILE_MACHINE_I386:\r
- //\r
- // Assume PE32 image with IA32 Machine field.\r
- //\r
- Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;\r
- break;\r
- case IMAGE_FILE_MACHINE_X64:\r
- case IMAGE_FILE_MACHINE_IA64:\r
- //\r
- // Assume PE32+ image with x64 or IA64 Machine field\r
- //\r
- Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;\r
- break;\r
- default:\r
- //\r
- // For unknow Machine field, use Magic in optional Header\r
- //\r
- Magic = Hdr.Pe32->OptionalHeader.Magic;\r
+ case IMAGE_FILE_MACHINE_I386:\r
+ //\r
+ // Assume PE32 image with IA32 Machine field.\r
+ //\r
+ Magic = EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC;\r
+ break;\r
+ case IMAGE_FILE_MACHINE_X64:\r
+ case IMAGE_FILE_MACHINE_IA64:\r
+ //\r
+ // Assume PE32+ image with x64 or IA64 Machine field\r
+ //\r
+ Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;\r
+ break;\r
+ default:\r
+ //\r
+ // For unknow Machine field, use Magic in optional Header\r
+ //\r
+ Magic = Hdr.Pe32->OptionalHeader.Magic;\r
}\r
\r
if (Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) {\r
// Use PE32 offset get Debug Directory Entry\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG]);\r
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *) ((UINTN) Pe32Data + DirectoryEntry->VirtualAddress);\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG]);\r
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)((UINTN)Pe32Data + DirectoryEntry->VirtualAddress);\r
} else if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {\r
//\r
// Use PE32+ offset get Debug Directory Entry\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG]);\r
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *) ((UINTN) Pe32Data + DirectoryEntry->VirtualAddress);\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG]);\r
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)((UINTN)Pe32Data + DirectoryEntry->VirtualAddress);\r
}\r
\r
if (NumberOfRvaAndSizes <= EFI_IMAGE_DIRECTORY_ENTRY_DEBUG) {\r
DirectoryEntry = NULL;\r
- DebugEntry = NULL;\r
+ DebugEntry = NULL;\r
}\r
} else {\r
return NULL;\r
}\r
\r
- if (DebugEntry == NULL || DirectoryEntry == NULL) {\r
+ if ((DebugEntry == NULL) || (DirectoryEntry == NULL)) {\r
return NULL;\r
}\r
\r
for (DirCount = 0; DirCount < DirectoryEntry->Size; DirCount += sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY), DebugEntry++) {\r
if (DebugEntry->Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {\r
if (DebugEntry->SizeOfData > 0) {\r
- CodeViewEntryPointer = (VOID *) ((UINTN) DebugEntry->RVA + ((UINTN)Pe32Data) + (UINTN)TEImageAdjust);\r
- switch (* (UINT32 *) CodeViewEntryPointer) {\r
- case CODEVIEW_SIGNATURE_NB10:\r
- return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY));\r
- case CODEVIEW_SIGNATURE_RSDS:\r
- return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY));\r
- case CODEVIEW_SIGNATURE_MTOC:\r
- return (VOID *) ((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));\r
- default:\r
- break;\r
+ CodeViewEntryPointer = (VOID *)((UINTN)DebugEntry->RVA + ((UINTN)Pe32Data) + (UINTN)TEImageAdjust);\r
+ switch (*(UINT32 *)CodeViewEntryPointer) {\r
+ case CODEVIEW_SIGNATURE_NB10:\r
+ return (VOID *)((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY));\r
+ case CODEVIEW_SIGNATURE_RSDS:\r
+ return (VOID *)((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY));\r
+ case CODEVIEW_SIGNATURE_MTOC:\r
+ return (VOID *)((CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY));\r
+ default:\r
+ break;\r
}\r
}\r
}\r
UINT32\r
EFIAPI\r
PeCoffGetSizeOfHeaders (\r
- IN VOID *Pe32Data\r
+ IN VOID *Pe32Data\r
)\r
{\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- UINTN SizeOfHeaders;\r
+ EFI_IMAGE_DOS_HEADER *DosHdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ UINTN SizeOfHeaders;\r
\r
ASSERT (Pe32Data != NULL);\r
\r
//\r
// DOS image header is present, so read the PE header after the DOS image header.\r
//\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN) Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)Pe32Data + (UINTN)((DosHdr->e_lfanew) & 0x0ffff));\r
} else {\r
//\r
// DOS image header is not present, so PE header is at the image base.\r
SizeOfHeaders = 0;\r
}\r
\r
- return (UINT32) SizeOfHeaders;\r
+ return (UINT32)SizeOfHeaders;\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
PeCoffSearchImageBase (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINTN Pe32Data;\r
+ UINTN Pe32Data;\r
\r
Pe32Data = 0;\r
\r
DEBUG_CODE_BEGIN ();\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_DOS_HEADER *DosHdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
\r
- //\r
- // Find Image Base\r
- //\r
- Pe32Data = Address & ~(PE_COFF_IMAGE_ALIGN_SIZE - 1);\r
- while (Pe32Data != 0) {\r
- DosHdr = (EFI_IMAGE_DOS_HEADER *) Pe32Data;\r
- if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {\r
- //\r
- // DOS image header is present, so read the PE header after the DOS image header.\r
- //\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN) ((DosHdr->e_lfanew) & 0x0ffff));\r
- //\r
- // Make sure PE header address does not overflow and is less than the initial address.\r
- //\r
- if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < Address)) {\r
- if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
- break;\r
- }\r
- }\r
- } else {\r
- //\r
- // DOS image header is not present, TE header is at the image base.\r
- //\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;\r
- if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&\r
- ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_IA64) ||\r
- (Hdr.Te->Machine == IMAGE_FILE_MACHINE_EBC) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_X64) ||\r
- (Hdr.Te->Machine == IMAGE_FILE_MACHINE_ARM64) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED))\r
- ) {\r
+ //\r
+ // Find Image Base\r
+ //\r
+ Pe32Data = Address & ~(PE_COFF_IMAGE_ALIGN_SIZE - 1);\r
+ while (Pe32Data != 0) {\r
+ DosHdr = (EFI_IMAGE_DOS_HEADER *)Pe32Data;\r
+ if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) {\r
+ //\r
+ // DOS image header is present, so read the PE header after the DOS image header.\r
+ //\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Pe32Data + (UINTN)((DosHdr->e_lfanew) & 0x0ffff));\r
+ //\r
+ // Make sure PE header address does not overflow and is less than the initial address.\r
+ //\r
+ if (((UINTN)Hdr.Pe32 > Pe32Data) && ((UINTN)Hdr.Pe32 < Address)) {\r
+ if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
break;\r
}\r
}\r
-\r
+ } else {\r
//\r
- // Not found the image base, check the previous aligned address\r
+ // DOS image header is not present, TE header is at the image base.\r
//\r
- Pe32Data -= PE_COFF_IMAGE_ALIGN_SIZE;\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)Pe32Data;\r
+ if ((Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) &&\r
+ ((Hdr.Te->Machine == IMAGE_FILE_MACHINE_I386) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_IA64) ||\r
+ (Hdr.Te->Machine == IMAGE_FILE_MACHINE_EBC) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_X64) ||\r
+ (Hdr.Te->Machine == IMAGE_FILE_MACHINE_ARM64) || (Hdr.Te->Machine == IMAGE_FILE_MACHINE_ARMTHUMB_MIXED))\r
+ )\r
+ {\r
+ break;\r
+ }\r
}\r
+\r
+ //\r
+ // Not found the image base, check the previous aligned address\r
+ //\r
+ Pe32Data -= PE_COFF_IMAGE_ALIGN_SIZE;\r
+ }\r
+\r
DEBUG_CODE_END ();\r
\r
return Pe32Data;\r
#include "BasePeCoffLibInternals.h"\r
#include <Library/BaseLib.h>\r
\r
-\r
/**\r
Pass in a pointer to an ARM MOVT or MOVW immediate instruciton and\r
return the immediate data encoded in the instruction.\r
**/\r
UINT16\r
ThumbMovtImmediateAddress (\r
- IN UINT16 *Instruction\r
+ IN UINT16 *Instruction\r
)\r
{\r
UINT32 Movt;\r
return Address;\r
}\r
\r
-\r
/**\r
Update an ARM MOVT or MOVW immediate instruction immediate data.\r
\r
**/\r
VOID\r
ThumbMovtImmediatePatch (\r
- IN OUT UINT16 *Instruction,\r
- IN UINT16 Address\r
+ IN OUT UINT16 *Instruction,\r
+ IN UINT16 Address\r
)\r
{\r
UINT16 Patch;\r
\r
// First 16-bit chunk of instruciton\r
- Patch = ((Address >> 12) & 0x000f); // imm4\r
+ Patch = ((Address >> 12) & 0x000f); // imm4\r
Patch |= (((Address & BIT11) != 0) ? BIT10 : 0); // i\r
// Mask out instruction bits and or in address\r
*(Instruction) = (*Instruction & ~0x040f) | Patch;\r
*Instruction = (*Instruction & ~0x70ff) | Patch;\r
}\r
\r
-\r
-\r
/**\r
Pass in a pointer to an ARM MOVW/MOVT instruciton pair and\r
return the immediate data encoded in the two` instruction.\r
**/\r
UINT32\r
ThumbMovwMovtImmediateAddress (\r
- IN UINT16 *Instructions\r
+ IN UINT16 *Instructions\r
)\r
{\r
UINT16 *Word;\r
return (ThumbMovtImmediateAddress (Top) << 16) + ThumbMovtImmediateAddress (Word);\r
}\r
\r
-\r
/**\r
Update an ARM MOVW/MOVT immediate instruction instruction pair.\r
\r
**/\r
VOID\r
ThumbMovwMovtImmediatePatch (\r
- IN OUT UINT16 *Instructions,\r
- IN UINT32 Address\r
+ IN OUT UINT16 *Instructions,\r
+ IN UINT32 Address\r
)\r
{\r
UINT16 *Word;\r
ThumbMovtImmediatePatch (Top, (UINT16)(Address >> 16));\r
}\r
\r
-\r
-\r
/**\r
Performs an ARM-based specific relocation fixup and is a no-op on other\r
instruction sets.\r
**/\r
RETURN_STATUS\r
PeCoffLoaderRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
- UINT16 *Fixup16;\r
- UINT32 FixupVal;\r
+ UINT16 *Fixup16;\r
+ UINT32 FixupVal;\r
\r
- Fixup16 = (UINT16 *) Fixup;\r
+ Fixup16 = (UINT16 *)Fixup;\r
\r
switch ((*Reloc) >> 12) {\r
+ case EFI_IMAGE_REL_BASED_ARM_MOV32T:\r
+ FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;\r
+ ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);\r
+\r
+ if (*FixupData != NULL) {\r
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));\r
+ // Fixup16 is not aligned so we must copy it. Thumb instructions are streams of 16 bytes.\r
+ CopyMem (*FixupData, Fixup16, sizeof (UINT64));\r
+ *FixupData = *FixupData + sizeof (UINT64);\r
+ }\r
\r
- case EFI_IMAGE_REL_BASED_ARM_MOV32T:\r
- FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;\r
- ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);\r
-\r
- if (*FixupData != NULL) {\r
- *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));\r
- // Fixup16 is not aligned so we must copy it. Thumb instructions are streams of 16 bytes.\r
- CopyMem (*FixupData, Fixup16, sizeof (UINT64));\r
- *FixupData = *FixupData + sizeof(UINT64);\r
- }\r
- break;\r
-\r
- case EFI_IMAGE_REL_BASED_ARM_MOV32A:\r
- ASSERT (FALSE);\r
- // break omitted - ARM instruction encoding not implemented\r
- default:\r
- return RETURN_UNSUPPORTED;\r
+ break;\r
+\r
+ case EFI_IMAGE_REL_BASED_ARM_MOV32A:\r
+ ASSERT (FALSE);\r
+ // break omitted - ARM instruction encoding not implemented\r
+ default:\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_SUCCESS;\r
**/\r
RETURN_STATUS\r
PeHotRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
UINT16 *Fixup16;\r
Fixup16 = (UINT16 *)Fixup;\r
\r
switch ((*Reloc) >> 12) {\r
-\r
- case EFI_IMAGE_REL_BASED_ARM_MOV32T:\r
- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));\r
- if (*(UINT64 *) (*FixupData) == ReadUnaligned64 ((UINT64 *)Fixup16)) {\r
- FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;\r
- ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);\r
- }\r
- *FixupData = *FixupData + sizeof(UINT64);\r
- break;\r
-\r
- case EFI_IMAGE_REL_BASED_ARM_MOV32A:\r
- ASSERT (FALSE);\r
+ case EFI_IMAGE_REL_BASED_ARM_MOV32T:\r
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));\r
+ if (*(UINT64 *)(*FixupData) == ReadUnaligned64 ((UINT64 *)Fixup16)) {\r
+ FixupVal = ThumbMovwMovtImmediateAddress (Fixup16) + (UINT32)Adjust;\r
+ ThumbMovwMovtImmediatePatch (Fixup16, FixupVal);\r
+ }\r
+\r
+ *FixupData = *FixupData + sizeof (UINT64);\r
+ break;\r
+\r
+ case EFI_IMAGE_REL_BASED_ARM_MOV32A:\r
+ ASSERT (FALSE);\r
// break omitted - ARM instruction encoding not implemented\r
- default:\r
- DEBUG ((DEBUG_ERROR, "PeHotRelocateEx:unknown fixed type\n"));\r
- return RETURN_UNSUPPORTED;\r
+ default:\r
+ DEBUG ((DEBUG_ERROR, "PeHotRelocateEx:unknown fixed type\n"));\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
return RETURN_SUCCESS;\r
**/\r
VOID\r
PeCoffLoaderAdjustOffsetForTeImage (\r
- EFI_IMAGE_SECTION_HEADER *SectionHeader,\r
- UINT32 TeStrippedOffset\r
+ EFI_IMAGE_SECTION_HEADER *SectionHeader,\r
+ UINT32 TeStrippedOffset\r
)\r
{\r
SectionHeader->VirtualAddress -= TeStrippedOffset;\r
OUT EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr\r
)\r
{\r
- RETURN_STATUS Status;\r
- EFI_IMAGE_DOS_HEADER DosHdr;\r
- UINTN Size;\r
- UINTN ReadSize;\r
- UINT32 SectionHeaderOffset;\r
- UINT32 Index;\r
- UINT32 HeaderWithoutDataDir;\r
- CHAR8 BufferData;\r
- UINTN NumberOfSections;\r
+ RETURN_STATUS Status;\r
+ EFI_IMAGE_DOS_HEADER DosHdr;\r
+ UINTN Size;\r
+ UINTN ReadSize;\r
+ UINT32 SectionHeaderOffset;\r
+ UINT32 Index;\r
+ UINT32 HeaderWithoutDataDir;\r
+ CHAR8 BufferData;\r
+ UINTN NumberOfSections;\r
EFI_IMAGE_SECTION_HEADER SectionHeader;\r
\r
//\r
// Read the DOS image header to check for its existence\r
//\r
- Size = sizeof (EFI_IMAGE_DOS_HEADER);\r
+ Size = sizeof (EFI_IMAGE_DOS_HEADER);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- 0,\r
- &Size,\r
- &DosHdr\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ 0,\r
+ &Size,\r
+ &DosHdr\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
// determines if this is a PE32 or PE32+ image. The magic is in the same\r
// location in both images.\r
//\r
- Size = sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION);\r
+ Size = sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- ImageContext->PeCoffHeaderOffset,\r
- &Size,\r
- Hdr.Pe32\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ ImageContext->PeCoffHeaderOffset,\r
+ &Size,\r
+ Hdr.Pe32\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
// Use Signature to figure out if we understand the image format\r
//\r
if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE) {\r
- ImageContext->IsTeImage = TRUE;\r
- ImageContext->Machine = Hdr.Te->Machine;\r
- ImageContext->ImageType = (UINT16)(Hdr.Te->Subsystem);\r
+ ImageContext->IsTeImage = TRUE;\r
+ ImageContext->Machine = Hdr.Te->Machine;\r
+ ImageContext->ImageType = (UINT16)(Hdr.Te->Subsystem);\r
//\r
// For TeImage, SectionAlignment is undefined to be set to Zero\r
// ImageSize can be calculated.\r
//\r
- ImageContext->ImageSize = 0;\r
- ImageContext->SectionAlignment = 0;\r
- ImageContext->SizeOfHeaders = sizeof (EFI_TE_IMAGE_HEADER) + (UINTN)Hdr.Te->BaseOfCode - (UINTN)Hdr.Te->StrippedSize;\r
+ ImageContext->ImageSize = 0;\r
+ ImageContext->SectionAlignment = 0;\r
+ ImageContext->SizeOfHeaders = sizeof (EFI_TE_IMAGE_HEADER) + (UINTN)Hdr.Te->BaseOfCode - (UINTN)Hdr.Te->StrippedSize;\r
\r
//\r
// Check the StrippedSize.\r
//\r
// Read last byte of Hdr.Te->SizeOfHeaders from the file.\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- ImageContext->SizeOfHeaders - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ ImageContext->SizeOfHeaders - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
// TE Image Data Directory Entry size is non-zero, but the Data Directory Virtual Address is zero.\r
// This case is not a valid TE image.\r
//\r
- if ((Hdr.Te->DataDirectory[0].Size != 0 && Hdr.Te->DataDirectory[0].VirtualAddress == 0) ||\r
- (Hdr.Te->DataDirectory[1].Size != 0 && Hdr.Te->DataDirectory[1].VirtualAddress == 0)) {\r
+ if (((Hdr.Te->DataDirectory[0].Size != 0) && (Hdr.Te->DataDirectory[0].VirtualAddress == 0)) ||\r
+ ((Hdr.Te->DataDirectory[1].Size != 0) && (Hdr.Te->DataDirectory[1].VirtualAddress == 0)))\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
+ } else if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) {\r
ImageContext->IsTeImage = FALSE;\r
- ImageContext->Machine = Hdr.Pe32->FileHeader.Machine;\r
+ ImageContext->Machine = Hdr.Pe32->FileHeader.Machine;\r
\r
if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) {\r
//\r
//\r
HeaderWithoutDataDir = sizeof (EFI_IMAGE_OPTIONAL_HEADER32) - sizeof (EFI_IMAGE_DATA_DIRECTORY) * EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES;\r
if (((UINT32)Hdr.Pe32->FileHeader.SizeOfOptionalHeader - HeaderWithoutDataDir) !=\r
- Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes * sizeof (EFI_IMAGE_DATA_DIRECTORY)) {\r
+ Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes * sizeof (EFI_IMAGE_DATA_DIRECTORY))\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if ((Hdr.Pe32->OptionalHeader.SizeOfImage - SectionHeaderOffset) / EFI_IMAGE_SIZEOF_SECTION_HEADER <= Hdr.Pe32->FileHeader.NumberOfSections) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if (Hdr.Pe32->OptionalHeader.SizeOfHeaders >= Hdr.Pe32->OptionalHeader.SizeOfImage) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if ((Hdr.Pe32->OptionalHeader.SizeOfHeaders - SectionHeaderOffset) / EFI_IMAGE_SIZEOF_SECTION_HEADER < (UINT32)Hdr.Pe32->FileHeader.NumberOfSections) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
//\r
// 4.2 Read last byte of Hdr.Pe32.OptionalHeader.SizeOfHeaders from the file.\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- Hdr.Pe32->OptionalHeader.SizeOfHeaders - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ Hdr.Pe32->OptionalHeader.SizeOfHeaders - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
//\r
// Check the member data to avoid overflow.\r
//\r
- if ((UINT32) (~0) - Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress <\r
- Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size) {\r
+ if ((UINT32)(~0) - Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress <\r
+ Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size)\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
//\r
// Read last byte of section header from file\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress +\r
- Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress +\r
+ Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
}\r
//\r
// Use PE32 offset\r
//\r
- ImageContext->ImageType = Hdr.Pe32->OptionalHeader.Subsystem;\r
- ImageContext->ImageSize = (UINT64)Hdr.Pe32->OptionalHeader.SizeOfImage;\r
- ImageContext->SectionAlignment = Hdr.Pe32->OptionalHeader.SectionAlignment;\r
- ImageContext->SizeOfHeaders = Hdr.Pe32->OptionalHeader.SizeOfHeaders;\r
-\r
+ ImageContext->ImageType = Hdr.Pe32->OptionalHeader.Subsystem;\r
+ ImageContext->ImageSize = (UINT64)Hdr.Pe32->OptionalHeader.SizeOfImage;\r
+ ImageContext->SectionAlignment = Hdr.Pe32->OptionalHeader.SectionAlignment;\r
+ ImageContext->SizeOfHeaders = Hdr.Pe32->OptionalHeader.SizeOfHeaders;\r
} else if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {\r
//\r
// 1. Check FileHeader.NumberOfRvaAndSizes filed.\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
//\r
// 2. Check the FileHeader.SizeOfOptionalHeader field.\r
// OptionalHeader.NumberOfRvaAndSizes is not bigger than 16, so\r
//\r
HeaderWithoutDataDir = sizeof (EFI_IMAGE_OPTIONAL_HEADER64) - sizeof (EFI_IMAGE_DATA_DIRECTORY) * EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES;\r
if (((UINT32)Hdr.Pe32Plus->FileHeader.SizeOfOptionalHeader - HeaderWithoutDataDir) !=\r
- Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes * sizeof (EFI_IMAGE_DATA_DIRECTORY)) {\r
+ Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes * sizeof (EFI_IMAGE_DATA_DIRECTORY))\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if ((Hdr.Pe32Plus->OptionalHeader.SizeOfImage - SectionHeaderOffset) / EFI_IMAGE_SIZEOF_SECTION_HEADER <= Hdr.Pe32Plus->FileHeader.NumberOfSections) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if (Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders >= Hdr.Pe32Plus->OptionalHeader.SizeOfImage) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if ((Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders - SectionHeaderOffset) / EFI_IMAGE_SIZEOF_SECTION_HEADER < (UINT32)Hdr.Pe32Plus->FileHeader.NumberOfSections) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
//\r
// 4.2 Read last byte of Hdr.Pe32Plus.OptionalHeader.SizeOfHeaders from the file.\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
//\r
// Check the member data to avoid overflow.\r
//\r
- if ((UINT32) (~0) - Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress <\r
- Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size) {\r
+ if ((UINT32)(~0) - Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress <\r
+ Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size)\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
//\r
// Read last byte of section header from file\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress +\r
- Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].VirtualAddress +\r
+ Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_SECURITY].Size - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
}\r
//\r
// Use PE32+ offset\r
//\r
- ImageContext->ImageType = Hdr.Pe32Plus->OptionalHeader.Subsystem;\r
- ImageContext->ImageSize = (UINT64) Hdr.Pe32Plus->OptionalHeader.SizeOfImage;\r
- ImageContext->SectionAlignment = Hdr.Pe32Plus->OptionalHeader.SectionAlignment;\r
- ImageContext->SizeOfHeaders = Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders;\r
+ ImageContext->ImageType = Hdr.Pe32Plus->OptionalHeader.Subsystem;\r
+ ImageContext->ImageSize = (UINT64)Hdr.Pe32Plus->OptionalHeader.SizeOfImage;\r
+ ImageContext->SectionAlignment = Hdr.Pe32Plus->OptionalHeader.SectionAlignment;\r
+ ImageContext->SizeOfHeaders = Hdr.Pe32Plus->OptionalHeader.SizeOfHeaders;\r
} else {\r
ImageContext->ImageError = IMAGE_ERROR_INVALID_MACHINE_TYPE;\r
return RETURN_UNSUPPORTED;\r
// Check each section field.\r
//\r
if (ImageContext->IsTeImage) {\r
- SectionHeaderOffset = sizeof(EFI_TE_IMAGE_HEADER);\r
- NumberOfSections = (UINTN) (Hdr.Te->NumberOfSections);\r
+ SectionHeaderOffset = sizeof (EFI_TE_IMAGE_HEADER);\r
+ NumberOfSections = (UINTN)(Hdr.Te->NumberOfSections);\r
} else {\r
SectionHeaderOffset = ImageContext->PeCoffHeaderOffset + sizeof (UINT32) + sizeof (EFI_IMAGE_FILE_HEADER) + Hdr.Pe32->FileHeader.SizeOfOptionalHeader;\r
- NumberOfSections = (UINTN) (Hdr.Pe32->FileHeader.NumberOfSections);\r
+ NumberOfSections = (UINTN)(Hdr.Pe32->FileHeader.NumberOfSections);\r
}\r
\r
for (Index = 0; Index < NumberOfSections; Index++) {\r
//\r
// Read section header from file\r
//\r
- Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
+ Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- SectionHeaderOffset,\r
- &Size,\r
- &SectionHeader\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ SectionHeaderOffset,\r
+ &Size,\r
+ &SectionHeader\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
//\r
// Section data should bigger than the Pe header.\r
//\r
- if (SectionHeader.VirtualAddress < ImageContext->SizeOfHeaders ||\r
- SectionHeader.PointerToRawData < ImageContext->SizeOfHeaders) {\r
+ if ((SectionHeader.VirtualAddress < ImageContext->SizeOfHeaders) ||\r
+ (SectionHeader.PointerToRawData < ImageContext->SizeOfHeaders))\r
+ {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
//\r
// Check the member data to avoid overflow.\r
//\r
- if ((UINT32) (~0) - SectionHeader.PointerToRawData < SectionHeader.SizeOfRawData) {\r
+ if ((UINT32)(~0) - SectionHeader.PointerToRawData < SectionHeader.SizeOfRawData) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
// Base on the ImageRead function to check the section data field.\r
// Read the last byte to make sure the data is in the image region.\r
//\r
- Size = 1;\r
+ Size = 1;\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- SectionHeader.PointerToRawData + SectionHeader.SizeOfRawData - 1,\r
- &Size,\r
- &BufferData\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ SectionHeader.PointerToRawData + SectionHeader.SizeOfRawData - 1,\r
+ &Size,\r
+ &BufferData\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
}\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Retrieves information about a PE/COFF image.\r
\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- RETURN_STATUS Status;\r
- EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- EFI_IMAGE_DATA_DIRECTORY *DebugDirectoryEntry;\r
- UINTN Size;\r
- UINTN ReadSize;\r
- UINTN Index;\r
- UINTN DebugDirectoryEntryRva;\r
- UINTN DebugDirectoryEntryFileOffset;\r
- UINTN SectionHeaderOffset;\r
- EFI_IMAGE_SECTION_HEADER SectionHeader;\r
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY DebugEntry;\r
- UINT32 NumberOfRvaAndSizes;\r
- UINT32 TeStrippedOffset;\r
+ RETURN_STATUS Status;\r
+ EFI_IMAGE_OPTIONAL_HEADER_UNION HdrData;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_DATA_DIRECTORY *DebugDirectoryEntry;\r
+ UINTN Size;\r
+ UINTN ReadSize;\r
+ UINTN Index;\r
+ UINTN DebugDirectoryEntryRva;\r
+ UINTN DebugDirectoryEntryFileOffset;\r
+ UINTN SectionHeaderOffset;\r
+ EFI_IMAGE_SECTION_HEADER SectionHeader;\r
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY DebugEntry;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ UINT32 TeStrippedOffset;\r
\r
if (ImageContext == NULL) {\r
return RETURN_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Assume success\r
//\r
- ImageContext->ImageError = IMAGE_ERROR_SUCCESS;\r
+ ImageContext->ImageError = IMAGE_ERROR_SUCCESS;\r
\r
Hdr.Union = &HdrData;\r
- Status = PeCoffLoaderGetPeHeader (ImageContext, Hdr);\r
+ Status = PeCoffLoaderGetPeHeader (ImageContext, Hdr);\r
if (RETURN_ERROR (Status)) {\r
return Status;\r
}\r
ImageContext->ImageAddress = Hdr.Pe32Plus->OptionalHeader.ImageBase;\r
}\r
} else {\r
- TeStrippedOffset = (UINT32)Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
+ TeStrippedOffset = (UINT32)Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
ImageContext->ImageAddress = (PHYSICAL_ADDRESS)(Hdr.Te->ImageBase + TeStrippedOffset);\r
}\r
\r
}\r
\r
if (NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_DEBUG) {\r
-\r
DebugDirectoryEntryRva = DebugDirectoryEntry->VirtualAddress;\r
\r
//\r
//\r
// Read section header from file\r
//\r
- Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
+ Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- SectionHeaderOffset,\r
- &Size,\r
- &SectionHeader\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ SectionHeaderOffset,\r
+ &Size,\r
+ &SectionHeader\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
- if (DebugDirectoryEntryRva >= SectionHeader.VirtualAddress &&\r
- DebugDirectoryEntryRva < SectionHeader.VirtualAddress + SectionHeader.Misc.VirtualSize) {\r
-\r
+ if ((DebugDirectoryEntryRva >= SectionHeader.VirtualAddress) &&\r
+ (DebugDirectoryEntryRva < SectionHeader.VirtualAddress + SectionHeader.Misc.VirtualSize))\r
+ {\r
DebugDirectoryEntryFileOffset = DebugDirectoryEntryRva - SectionHeader.VirtualAddress + SectionHeader.PointerToRawData;\r
break;\r
}\r
//\r
// Read next debug directory entry\r
//\r
- Size = sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
+ Size = sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- DebugDirectoryEntryFileOffset + Index,\r
- &Size,\r
- &DebugEntry\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ DebugDirectoryEntryFileOffset + Index,\r
+ &Size,\r
+ &DebugEntry\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
// ImageContext->ImageSize when DebugEntry.RVA == 0.\r
//\r
if (DebugEntry.Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {\r
- ImageContext->DebugDirectoryEntryRva = (UINT32) (DebugDirectoryEntryRva + Index);\r
- if (DebugEntry.RVA == 0 && DebugEntry.FileOffset != 0) {\r
+ ImageContext->DebugDirectoryEntryRva = (UINT32)(DebugDirectoryEntryRva + Index);\r
+ if ((DebugEntry.RVA == 0) && (DebugEntry.FileOffset != 0)) {\r
ImageContext->ImageSize += DebugEntry.SizeOfData;\r
}\r
\r
}\r
}\r
} else {\r
+ DebugDirectoryEntry = &Hdr.Te->DataDirectory[1];\r
+ DebugDirectoryEntryRva = DebugDirectoryEntry->VirtualAddress;\r
+ SectionHeaderOffset = (UINTN)(sizeof (EFI_TE_IMAGE_HEADER));\r
\r
- DebugDirectoryEntry = &Hdr.Te->DataDirectory[1];\r
- DebugDirectoryEntryRva = DebugDirectoryEntry->VirtualAddress;\r
- SectionHeaderOffset = (UINTN)(sizeof (EFI_TE_IMAGE_HEADER));\r
-\r
- DebugDirectoryEntryFileOffset = 0;\r
+ DebugDirectoryEntryFileOffset = 0;\r
\r
for (Index = 0; Index < Hdr.Te->NumberOfSections;) {\r
//\r
// Read section header from file\r
//\r
- Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
+ Size = sizeof (EFI_IMAGE_SECTION_HEADER);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- SectionHeaderOffset,\r
- &Size,\r
- &SectionHeader\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ SectionHeaderOffset,\r
+ &Size,\r
+ &SectionHeader\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
- if (DebugDirectoryEntryRva >= SectionHeader.VirtualAddress &&\r
- DebugDirectoryEntryRva < SectionHeader.VirtualAddress + SectionHeader.Misc.VirtualSize) {\r
+ if ((DebugDirectoryEntryRva >= SectionHeader.VirtualAddress) &&\r
+ (DebugDirectoryEntryRva < SectionHeader.VirtualAddress + SectionHeader.Misc.VirtualSize))\r
+ {\r
DebugDirectoryEntryFileOffset = DebugDirectoryEntryRva -\r
SectionHeader.VirtualAddress +\r
SectionHeader.PointerToRawData -\r
// File offset of the debug directory was found, if this is not the last\r
// section, then skip to the last section for calculating the image size.\r
//\r
- if (Index < (UINTN) Hdr.Te->NumberOfSections - 1) {\r
+ if (Index < (UINTN)Hdr.Te->NumberOfSections - 1) {\r
SectionHeaderOffset += (Hdr.Te->NumberOfSections - 1 - Index) * sizeof (EFI_IMAGE_SECTION_HEADER);\r
- Index = Hdr.Te->NumberOfSections - 1;\r
+ Index = Hdr.Te->NumberOfSections - 1;\r
continue;\r
}\r
}\r
//\r
// Read next debug directory entry\r
//\r
- Size = sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
+ Size = sizeof (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);\r
ReadSize = Size;\r
- Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- DebugDirectoryEntryFileOffset + Index,\r
- &Size,\r
- &DebugEntry\r
- );\r
+ Status = ImageContext->ImageRead (\r
+ ImageContext->Handle,\r
+ DebugDirectoryEntryFileOffset + Index,\r
+ &Size,\r
+ &DebugEntry\r
+ );\r
if (RETURN_ERROR (Status) || (Size != ReadSize)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
if (Size != ReadSize) {\r
Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return Status;\r
}\r
\r
if (DebugEntry.Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {\r
- ImageContext->DebugDirectoryEntryRva = (UINT32) (DebugDirectoryEntryRva + Index);\r
+ ImageContext->DebugDirectoryEntryRva = (UINT32)(DebugDirectoryEntryRva + Index);\r
return RETURN_SUCCESS;\r
}\r
}\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Converts an image address to the loaded address.\r
\r
**/\r
VOID *\r
PeCoffLoaderImageAddress (\r
- IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
- IN UINTN Address,\r
- IN UINTN TeStrippedOffset\r
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN UINTN Address,\r
+ IN UINTN TeStrippedOffset\r
)\r
{\r
//\r
return NULL;\r
}\r
\r
- return (CHAR8 *)((UINTN) ImageContext->ImageAddress + Address - TeStrippedOffset);\r
+ return (CHAR8 *)((UINTN)ImageContext->ImageAddress + Address - TeStrippedOffset);\r
}\r
\r
/**\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- RETURN_STATUS Status;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- EFI_IMAGE_DATA_DIRECTORY *RelocDir;\r
- UINT64 Adjust;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBaseOrg;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBase;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBaseEnd;\r
- UINT16 *Reloc;\r
- UINT16 *RelocEnd;\r
- CHAR8 *Fixup;\r
- CHAR8 *FixupBase;\r
- UINT16 *Fixup16;\r
- UINT32 *Fixup32;\r
- UINT64 *Fixup64;\r
- CHAR8 *FixupData;\r
- PHYSICAL_ADDRESS BaseAddress;\r
- UINT32 NumberOfRvaAndSizes;\r
- UINT32 TeStrippedOffset;\r
+ RETURN_STATUS Status;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ EFI_IMAGE_DATA_DIRECTORY *RelocDir;\r
+ UINT64 Adjust;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBaseOrg;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBase;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBaseEnd;\r
+ UINT16 *Reloc;\r
+ UINT16 *RelocEnd;\r
+ CHAR8 *Fixup;\r
+ CHAR8 *FixupBase;\r
+ UINT16 *Fixup16;\r
+ UINT32 *Fixup32;\r
+ UINT64 *Fixup64;\r
+ CHAR8 *FixupData;\r
+ PHYSICAL_ADDRESS BaseAddress;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ UINT32 TeStrippedOffset;\r
\r
ASSERT (ImageContext != NULL);\r
\r
}\r
\r
if (!(ImageContext->IsTeImage)) {\r
- Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)ImageContext->ImageAddress + ImageContext->PeCoffHeaderOffset);\r
+ Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)ImageContext->ImageAddress + ImageContext->PeCoffHeaderOffset);\r
TeStrippedOffset = 0;\r
\r
if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) {\r
}\r
\r
NumberOfRvaAndSizes = Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes;\r
- RelocDir = &Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
+ RelocDir = &Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
} else {\r
//\r
// Use PE32+ offset\r
//\r
- Adjust = (UINT64) BaseAddress - Hdr.Pe32Plus->OptionalHeader.ImageBase;\r
+ Adjust = (UINT64)BaseAddress - Hdr.Pe32Plus->OptionalHeader.ImageBase;\r
if (Adjust != 0) {\r
Hdr.Pe32Plus->OptionalHeader.ImageBase = (UINT64)BaseAddress;\r
}\r
\r
NumberOfRvaAndSizes = Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes;\r
- RelocDir = &Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
+ RelocDir = &Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
}\r
\r
//\r
RelocDir = NULL;\r
}\r
} else {\r
- Hdr.Te = (EFI_TE_IMAGE_HEADER *)(UINTN)(ImageContext->ImageAddress);\r
- TeStrippedOffset = (UINT32)Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
- Adjust = (UINT64) (BaseAddress - (Hdr.Te->ImageBase + TeStrippedOffset));\r
+ Hdr.Te = (EFI_TE_IMAGE_HEADER *)(UINTN)(ImageContext->ImageAddress);\r
+ TeStrippedOffset = (UINT32)Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
+ Adjust = (UINT64)(BaseAddress - (Hdr.Te->ImageBase + TeStrippedOffset));\r
if (Adjust != 0) {\r
- Hdr.Te->ImageBase = (UINT64) (BaseAddress - TeStrippedOffset);\r
+ Hdr.Te->ImageBase = (UINT64)(BaseAddress - TeStrippedOffset);\r
}\r
\r
//\r
}\r
\r
if ((RelocDir != NULL) && (RelocDir->Size > 0)) {\r
- RelocBase = (EFI_IMAGE_BASE_RELOCATION *) PeCoffLoaderImageAddress (ImageContext, RelocDir->VirtualAddress, TeStrippedOffset);\r
- RelocBaseEnd = (EFI_IMAGE_BASE_RELOCATION *) PeCoffLoaderImageAddress (ImageContext,\r
- RelocDir->VirtualAddress + RelocDir->Size - 1,\r
- TeStrippedOffset\r
- );\r
- if (RelocBase == NULL || RelocBaseEnd == NULL || (UINTN) RelocBaseEnd < (UINTN) RelocBase) {\r
+ RelocBase = (EFI_IMAGE_BASE_RELOCATION *)PeCoffLoaderImageAddress (ImageContext, RelocDir->VirtualAddress, TeStrippedOffset);\r
+ RelocBaseEnd = (EFI_IMAGE_BASE_RELOCATION *)PeCoffLoaderImageAddress (\r
+ ImageContext,\r
+ RelocDir->VirtualAddress + RelocDir->Size - 1,\r
+ TeStrippedOffset\r
+ );\r
+ if ((RelocBase == NULL) || (RelocBaseEnd == NULL) || ((UINTN)RelocBaseEnd < (UINTN)RelocBase)) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
//\r
RelocBase = RelocBaseEnd = NULL;\r
}\r
+\r
RelocBaseOrg = RelocBase;\r
\r
//\r
// Run the relocation information and apply the fixups\r
//\r
FixupData = ImageContext->FixupData;\r
- while ((UINTN) RelocBase < (UINTN) RelocBaseEnd) {\r
-\r
- Reloc = (UINT16 *) ((CHAR8 *) RelocBase + sizeof (EFI_IMAGE_BASE_RELOCATION));\r
+ while ((UINTN)RelocBase < (UINTN)RelocBaseEnd) {\r
+ Reloc = (UINT16 *)((CHAR8 *)RelocBase + sizeof (EFI_IMAGE_BASE_RELOCATION));\r
//\r
// Add check for RelocBase->SizeOfBlock field.\r
//\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
+\r
if ((UINTN)RelocBase > MAX_ADDRESS - RelocBase->SizeOfBlock) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
\r
- RelocEnd = (UINT16 *) ((CHAR8 *) RelocBase + RelocBase->SizeOfBlock);\r
+ RelocEnd = (UINT16 *)((CHAR8 *)RelocBase + RelocBase->SizeOfBlock);\r
if ((UINTN)RelocEnd > (UINTN)RelocBaseOrg + RelocDir->Size) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
+\r
FixupBase = PeCoffLoaderImageAddress (ImageContext, RelocBase->VirtualAddress, TeStrippedOffset);\r
if (FixupBase == NULL) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
//\r
// Run this relocation record\r
//\r
- while ((UINTN) Reloc < (UINTN) RelocEnd) {\r
+ while ((UINTN)Reloc < (UINTN)RelocEnd) {\r
Fixup = PeCoffLoaderImageAddress (ImageContext, RelocBase->VirtualAddress + (*Reloc & 0xFFF), TeStrippedOffset);\r
if (Fixup == NULL) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
+\r
switch ((*Reloc) >> 12) {\r
- case EFI_IMAGE_REL_BASED_ABSOLUTE:\r
- break;\r
+ case EFI_IMAGE_REL_BASED_ABSOLUTE:\r
+ break;\r
+\r
+ case EFI_IMAGE_REL_BASED_HIGH:\r
+ Fixup16 = (UINT16 *)Fixup;\r
+ *Fixup16 = (UINT16)(*Fixup16 + ((UINT16)((UINT32)Adjust >> 16)));\r
+ if (FixupData != NULL) {\r
+ *(UINT16 *)FixupData = *Fixup16;\r
+ FixupData = FixupData + sizeof (UINT16);\r
+ }\r
\r
- case EFI_IMAGE_REL_BASED_HIGH:\r
- Fixup16 = (UINT16 *) Fixup;\r
- *Fixup16 = (UINT16) (*Fixup16 + ((UINT16) ((UINT32) Adjust >> 16)));\r
- if (FixupData != NULL) {\r
- *(UINT16 *) FixupData = *Fixup16;\r
- FixupData = FixupData + sizeof (UINT16);\r
- }\r
- break;\r
+ break;\r
\r
- case EFI_IMAGE_REL_BASED_LOW:\r
- Fixup16 = (UINT16 *) Fixup;\r
- *Fixup16 = (UINT16) (*Fixup16 + (UINT16) Adjust);\r
- if (FixupData != NULL) {\r
- *(UINT16 *) FixupData = *Fixup16;\r
- FixupData = FixupData + sizeof (UINT16);\r
- }\r
- break;\r
+ case EFI_IMAGE_REL_BASED_LOW:\r
+ Fixup16 = (UINT16 *)Fixup;\r
+ *Fixup16 = (UINT16)(*Fixup16 + (UINT16)Adjust);\r
+ if (FixupData != NULL) {\r
+ *(UINT16 *)FixupData = *Fixup16;\r
+ FixupData = FixupData + sizeof (UINT16);\r
+ }\r
\r
- case EFI_IMAGE_REL_BASED_HIGHLOW:\r
- Fixup32 = (UINT32 *) Fixup;\r
- *Fixup32 = *Fixup32 + (UINT32) Adjust;\r
- if (FixupData != NULL) {\r
- FixupData = ALIGN_POINTER (FixupData, sizeof (UINT32));\r
- *(UINT32 *)FixupData = *Fixup32;\r
- FixupData = FixupData + sizeof (UINT32);\r
- }\r
- break;\r
+ break;\r
\r
- case EFI_IMAGE_REL_BASED_DIR64:\r
- Fixup64 = (UINT64 *) Fixup;\r
- *Fixup64 = *Fixup64 + (UINT64) Adjust;\r
- if (FixupData != NULL) {\r
- FixupData = ALIGN_POINTER (FixupData, sizeof(UINT64));\r
- *(UINT64 *)(FixupData) = *Fixup64;\r
- FixupData = FixupData + sizeof(UINT64);\r
- }\r
- break;\r
+ case EFI_IMAGE_REL_BASED_HIGHLOW:\r
+ Fixup32 = (UINT32 *)Fixup;\r
+ *Fixup32 = *Fixup32 + (UINT32)Adjust;\r
+ if (FixupData != NULL) {\r
+ FixupData = ALIGN_POINTER (FixupData, sizeof (UINT32));\r
+ *(UINT32 *)FixupData = *Fixup32;\r
+ FixupData = FixupData + sizeof (UINT32);\r
+ }\r
\r
- default:\r
- //\r
- // The common code does not handle some of the stranger IPF relocations\r
- // PeCoffLoaderRelocateImageEx () adds support for these complex fixups\r
- // on IPF and is a No-Op on other architectures.\r
- //\r
- Status = PeCoffLoaderRelocateImageEx (Reloc, Fixup, &FixupData, Adjust);\r
- if (RETURN_ERROR (Status)) {\r
- ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
- return Status;\r
- }\r
+ break;\r
+\r
+ case EFI_IMAGE_REL_BASED_DIR64:\r
+ Fixup64 = (UINT64 *)Fixup;\r
+ *Fixup64 = *Fixup64 + (UINT64)Adjust;\r
+ if (FixupData != NULL) {\r
+ FixupData = ALIGN_POINTER (FixupData, sizeof (UINT64));\r
+ *(UINT64 *)(FixupData) = *Fixup64;\r
+ FixupData = FixupData + sizeof (UINT64);\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ //\r
+ // The common code does not handle some of the stranger IPF relocations\r
+ // PeCoffLoaderRelocateImageEx () adds support for these complex fixups\r
+ // on IPF and is a No-Op on other architectures.\r
+ //\r
+ Status = PeCoffLoaderRelocateImageEx (Reloc, Fixup, &FixupData, Adjust);\r
+ if (RETURN_ERROR (Status)) {\r
+ ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
+ return Status;\r
+ }\r
}\r
\r
//\r
//\r
// Next reloc block\r
//\r
- RelocBase = (EFI_IMAGE_BASE_RELOCATION *) RelocEnd;\r
+ RelocBase = (EFI_IMAGE_BASE_RELOCATION *)RelocEnd;\r
}\r
+\r
ASSERT ((UINTN)FixupData <= (UINTN)ImageContext->FixupData + ImageContext->FixupDataSize);\r
\r
//\r
// Adjust the EntryPoint to match the linked-to address\r
//\r
if (ImageContext->DestinationAddress != 0) {\r
- ImageContext->EntryPoint -= (UINT64) ImageContext->ImageAddress;\r
- ImageContext->EntryPoint += (UINT64) ImageContext->DestinationAddress;\r
+ ImageContext->EntryPoint -= (UINT64)ImageContext->ImageAddress;\r
+ ImageContext->EntryPoint += (UINT64)ImageContext->DestinationAddress;\r
}\r
}\r
\r
IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext\r
)\r
{\r
- RETURN_STATUS Status;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- PE_COFF_LOADER_IMAGE_CONTEXT CheckContext;\r
- EFI_IMAGE_SECTION_HEADER *FirstSection;\r
- EFI_IMAGE_SECTION_HEADER *Section;\r
- UINTN NumberOfSections;\r
- UINTN Index;\r
- CHAR8 *Base;\r
- CHAR8 *End;\r
- EFI_IMAGE_DATA_DIRECTORY *DirectoryEntry;\r
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
- UINTN Size;\r
- UINT32 TempDebugEntryRva;\r
- UINT32 NumberOfRvaAndSizes;\r
- EFI_IMAGE_RESOURCE_DIRECTORY *ResourceDirectory;\r
- EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *ResourceDirectoryEntry;\r
- EFI_IMAGE_RESOURCE_DIRECTORY_STRING *ResourceDirectoryString;\r
- EFI_IMAGE_RESOURCE_DATA_ENTRY *ResourceDataEntry;\r
- CHAR16 *String;\r
- UINT32 Offset;\r
- UINT32 TeStrippedOffset;\r
+ RETURN_STATUS Status;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT CheckContext;\r
+ EFI_IMAGE_SECTION_HEADER *FirstSection;\r
+ EFI_IMAGE_SECTION_HEADER *Section;\r
+ UINTN NumberOfSections;\r
+ UINTN Index;\r
+ CHAR8 *Base;\r
+ CHAR8 *End;\r
+ EFI_IMAGE_DATA_DIRECTORY *DirectoryEntry;\r
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;\r
+ UINTN Size;\r
+ UINT32 TempDebugEntryRva;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_RESOURCE_DIRECTORY *ResourceDirectory;\r
+ EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *ResourceDirectoryEntry;\r
+ EFI_IMAGE_RESOURCE_DIRECTORY_STRING *ResourceDirectoryString;\r
+ EFI_IMAGE_RESOURCE_DATA_ENTRY *ResourceDataEntry;\r
+ CHAR16 *String;\r
+ UINT32 Offset;\r
+ UINT32 TeStrippedOffset;\r
\r
ASSERT (ImageContext != NULL);\r
\r
ImageContext->ImageError = IMAGE_ERROR_INVALID_IMAGE_SIZE;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
+\r
if (ImageContext->ImageAddress == 0) {\r
//\r
// Image cannot be loaded into 0 address.\r
ImageContext->ImageError = IMAGE_ERROR_INVALID_IMAGE_ADDRESS;\r
return RETURN_INVALID_PARAMETER;\r
}\r
+\r
//\r
// If there's no relocations, then make sure it's not a runtime driver,\r
// and that it's being loaded at the linked address.\r
ImageContext->ImageError = IMAGE_ERROR_INVALID_SUBSYSTEM;\r
return RETURN_LOAD_ERROR;\r
}\r
+\r
//\r
// If the image does not contain relocations, and the requested load address\r
// is not the linked address, then return an error.\r
return RETURN_INVALID_PARAMETER;\r
}\r
}\r
+\r
//\r
// Make sure the allocated space has the proper section alignment\r
//\r
return RETURN_INVALID_PARAMETER;\r
}\r
}\r
+\r
//\r
// Read the entire PE/COFF or TE header into memory\r
//\r
if (!(ImageContext->IsTeImage)) {\r
Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- 0,\r
- &ImageContext->SizeOfHeaders,\r
- (VOID *) (UINTN) ImageContext->ImageAddress\r
- );\r
+ ImageContext->Handle,\r
+ 0,\r
+ &ImageContext->SizeOfHeaders,\r
+ (VOID *)(UINTN)ImageContext->ImageAddress\r
+ );\r
\r
Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)((UINTN)ImageContext->ImageAddress + ImageContext->PeCoffHeaderOffset);\r
\r
- FirstSection = (EFI_IMAGE_SECTION_HEADER *) (\r
- (UINTN)ImageContext->ImageAddress +\r
- ImageContext->PeCoffHeaderOffset +\r
- sizeof(UINT32) +\r
- sizeof(EFI_IMAGE_FILE_HEADER) +\r
- Hdr.Pe32->FileHeader.SizeOfOptionalHeader\r
- );\r
- NumberOfSections = (UINTN) (Hdr.Pe32->FileHeader.NumberOfSections);\r
+ FirstSection = (EFI_IMAGE_SECTION_HEADER *)(\r
+ (UINTN)ImageContext->ImageAddress +\r
+ ImageContext->PeCoffHeaderOffset +\r
+ sizeof (UINT32) +\r
+ sizeof (EFI_IMAGE_FILE_HEADER) +\r
+ Hdr.Pe32->FileHeader.SizeOfOptionalHeader\r
+ );\r
+ NumberOfSections = (UINTN)(Hdr.Pe32->FileHeader.NumberOfSections);\r
TeStrippedOffset = 0;\r
} else {\r
Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- 0,\r
- &ImageContext->SizeOfHeaders,\r
- (void *)(UINTN)ImageContext->ImageAddress\r
- );\r
-\r
- Hdr.Te = (EFI_TE_IMAGE_HEADER *)(UINTN)(ImageContext->ImageAddress);\r
- FirstSection = (EFI_IMAGE_SECTION_HEADER *) (\r
- (UINTN)ImageContext->ImageAddress +\r
- sizeof(EFI_TE_IMAGE_HEADER)\r
- );\r
- NumberOfSections = (UINTN) (Hdr.Te->NumberOfSections);\r
- TeStrippedOffset = (UINT32) Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
+ ImageContext->Handle,\r
+ 0,\r
+ &ImageContext->SizeOfHeaders,\r
+ (void *)(UINTN)ImageContext->ImageAddress\r
+ );\r
+\r
+ Hdr.Te = (EFI_TE_IMAGE_HEADER *)(UINTN)(ImageContext->ImageAddress);\r
+ FirstSection = (EFI_IMAGE_SECTION_HEADER *)(\r
+ (UINTN)ImageContext->ImageAddress +\r
+ sizeof (EFI_TE_IMAGE_HEADER)\r
+ );\r
+ NumberOfSections = (UINTN)(Hdr.Te->NumberOfSections);\r
+ TeStrippedOffset = (UINT32)Hdr.Te->StrippedSize - sizeof (EFI_TE_IMAGE_HEADER);\r
}\r
\r
if (RETURN_ERROR (Status)) {\r
//\r
// Read the section\r
//\r
- Size = (UINTN) Section->Misc.VirtualSize;\r
+ Size = (UINTN)Section->Misc.VirtualSize;\r
if ((Size == 0) || (Size > Section->SizeOfRawData)) {\r
- Size = (UINTN) Section->SizeOfRawData;\r
+ Size = (UINTN)Section->SizeOfRawData;\r
}\r
\r
//\r
\r
if (Section->SizeOfRawData > 0) {\r
Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- Section->PointerToRawData - TeStrippedOffset,\r
- &Size,\r
- Base\r
- );\r
+ ImageContext->Handle,\r
+ Section->PointerToRawData - TeStrippedOffset,\r
+ &Size,\r
+ Base\r
+ );\r
if (RETURN_ERROR (Status)) {\r
ImageContext->ImageError = IMAGE_ERROR_IMAGE_READ;\r
return Status;\r
// Use PE32 offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
} else {\r
//\r
// Use PE32+ offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC];\r
}\r
\r
//\r
DirectoryEntry = &Hdr.Te->DataDirectory[0];\r
ImageContext->FixupDataSize = DirectoryEntry->Size / sizeof (UINT16) * sizeof (UINT64);\r
}\r
+\r
//\r
// Consumer must allocate a buffer for the relocation fixup log.\r
// Only used for runtime drivers.\r
//\r
if (ImageContext->DebugDirectoryEntryRva != 0) {\r
DebugEntry = PeCoffLoaderImageAddress (\r
- ImageContext,\r
- ImageContext->DebugDirectoryEntryRva,\r
- TeStrippedOffset\r
- );\r
+ ImageContext,\r
+ ImageContext->DebugDirectoryEntryRva,\r
+ TeStrippedOffset\r
+ );\r
if (DebugEntry == NULL) {\r
ImageContext->ImageError = IMAGE_ERROR_FAILED_RELOCATION;\r
return RETURN_LOAD_ERROR;\r
}\r
\r
TempDebugEntryRva = DebugEntry->RVA;\r
- if (DebugEntry->RVA == 0 && DebugEntry->FileOffset != 0) {\r
+ if ((DebugEntry->RVA == 0) && (DebugEntry->FileOffset != 0)) {\r
Section--;\r
if ((UINTN)Section->SizeOfRawData < Section->Misc.VirtualSize) {\r
TempDebugEntryRva = Section->VirtualAddress + Section->Misc.VirtualSize;\r
}\r
\r
if (DebugEntry->RVA == 0) {\r
- Size = DebugEntry->SizeOfData;\r
+ Size = DebugEntry->SizeOfData;\r
Status = ImageContext->ImageRead (\r
- ImageContext->Handle,\r
- DebugEntry->FileOffset - TeStrippedOffset,\r
- &Size,\r
- ImageContext->CodeView\r
- );\r
+ ImageContext->Handle,\r
+ DebugEntry->FileOffset - TeStrippedOffset,\r
+ &Size,\r
+ ImageContext->CodeView\r
+ );\r
//\r
// Should we apply fix up to this field according to the size difference between PE and TE?\r
// Because now we maintain TE header fields unfixed, this field will also remain as they are\r
DebugEntry->RVA = TempDebugEntryRva;\r
}\r
\r
- switch (*(UINT32 *) ImageContext->CodeView) {\r
- case CODEVIEW_SIGNATURE_NB10:\r
- if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY)) {\r
- ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
- return RETURN_UNSUPPORTED;\r
- }\r
- ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);\r
- break;\r
+ switch (*(UINT32 *)ImageContext->CodeView) {\r
+ case CODEVIEW_SIGNATURE_NB10:\r
+ if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY)) {\r
+ ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
\r
- case CODEVIEW_SIGNATURE_RSDS:\r
- if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY)) {\r
- ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
- return RETURN_UNSUPPORTED;\r
- }\r
- ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);\r
- break;\r
+ ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);\r
+ break;\r
\r
- case CODEVIEW_SIGNATURE_MTOC:\r
- if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY)) {\r
- ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
- return RETURN_UNSUPPORTED;\r
- }\r
- ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);\r
- break;\r
+ case CODEVIEW_SIGNATURE_RSDS:\r
+ if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY)) {\r
+ ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
+\r
+ ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);\r
+ break;\r
+\r
+ case CODEVIEW_SIGNATURE_MTOC:\r
+ if (DebugEntry->SizeOfData < sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY)) {\r
+ ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
+ return RETURN_UNSUPPORTED;\r
+ }\r
\r
- default:\r
- break;\r
+ ImageContext->PdbPointer = (CHAR8 *)ImageContext->CodeView + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);\r
+ break;\r
+\r
+ default:\r
+ break;\r
}\r
}\r
}\r
// Use PE32 offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE];\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE];\r
} else {\r
//\r
// Use PE32+ offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes;\r
- DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE];\r
+ DirectoryEntry = (EFI_IMAGE_DATA_DIRECTORY *)&Hdr.Pe32Plus->OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE];\r
}\r
\r
- if (NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE && DirectoryEntry->Size != 0) {\r
+ if ((NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE) && (DirectoryEntry->Size != 0)) {\r
Base = PeCoffLoaderImageAddress (ImageContext, DirectoryEntry->VirtualAddress, 0);\r
if (Base != NULL) {\r
- ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *) Base;\r
- Offset = sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) *\r
- (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
+ ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *)Base;\r
+ Offset = sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) *\r
+ (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
if (Offset > DirectoryEntry->Size) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *) (ResourceDirectory + 1);\r
+\r
+ ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *)(ResourceDirectory + 1);\r
\r
for (Index = 0; Index < ResourceDirectory->NumberOfNamedEntries; Index++) {\r
if (ResourceDirectoryEntry->u1.s.NameIsString) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectoryString = (EFI_IMAGE_RESOURCE_DIRECTORY_STRING *) (Base + ResourceDirectoryEntry->u1.s.NameOffset);\r
- String = &ResourceDirectoryString->String[0];\r
\r
- if (ResourceDirectoryString->Length == 3 &&\r
- String[0] == L'H' &&\r
- String[1] == L'I' &&\r
- String[2] == L'I') {\r
+ ResourceDirectoryString = (EFI_IMAGE_RESOURCE_DIRECTORY_STRING *)(Base + ResourceDirectoryEntry->u1.s.NameOffset);\r
+ String = &ResourceDirectoryString->String[0];\r
+\r
+ if ((ResourceDirectoryString->Length == 3) &&\r
+ (String[0] == L'H') &&\r
+ (String[1] == L'I') &&\r
+ (String[2] == L'I'))\r
+ {\r
//\r
// Resource Type "HII" found\r
//\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *) (Base + ResourceDirectoryEntry->u2.s.OffsetToDirectory);\r
- Offset = ResourceDirectoryEntry->u2.s.OffsetToDirectory + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) +\r
- sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) * (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
+\r
+ ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *)(Base + ResourceDirectoryEntry->u2.s.OffsetToDirectory);\r
+ Offset = ResourceDirectoryEntry->u2.s.OffsetToDirectory + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) +\r
+ sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) * (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
if (Offset > DirectoryEntry->Size) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *) (ResourceDirectory + 1);\r
+\r
+ ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *)(ResourceDirectory + 1);\r
\r
if (ResourceDirectoryEntry->u2.s.DataIsDirectory) {\r
//\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *) (Base + ResourceDirectoryEntry->u2.s.OffsetToDirectory);\r
- Offset = ResourceDirectoryEntry->u2.s.OffsetToDirectory + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) +\r
- sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) * (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
+\r
+ ResourceDirectory = (EFI_IMAGE_RESOURCE_DIRECTORY *)(Base + ResourceDirectoryEntry->u2.s.OffsetToDirectory);\r
+ Offset = ResourceDirectoryEntry->u2.s.OffsetToDirectory + sizeof (EFI_IMAGE_RESOURCE_DIRECTORY) +\r
+ sizeof (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY) * (ResourceDirectory->NumberOfNamedEntries + ResourceDirectory->NumberOfIdEntries);\r
if (Offset > DirectoryEntry->Size) {\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *) (ResourceDirectory + 1);\r
+\r
+ ResourceDirectoryEntry = (EFI_IMAGE_RESOURCE_DIRECTORY_ENTRY *)(ResourceDirectory + 1);\r
}\r
}\r
\r
ImageContext->ImageError = IMAGE_ERROR_UNSUPPORTED;\r
return RETURN_UNSUPPORTED;\r
}\r
- ResourceDataEntry = (EFI_IMAGE_RESOURCE_DATA_ENTRY *) (Base + ResourceDirectoryEntry->u2.OffsetToData);\r
- ImageContext->HiiResourceData = (PHYSICAL_ADDRESS) (UINTN) PeCoffLoaderImageAddress (ImageContext, ResourceDataEntry->OffsetToData, 0);\r
+\r
+ ResourceDataEntry = (EFI_IMAGE_RESOURCE_DATA_ENTRY *)(Base + ResourceDirectoryEntry->u2.OffsetToData);\r
+ ImageContext->HiiResourceData = (PHYSICAL_ADDRESS)(UINTN)PeCoffLoaderImageAddress (ImageContext, ResourceDataEntry->OffsetToData, 0);\r
break;\r
}\r
}\r
}\r
+\r
ResourceDirectoryEntry++;\r
}\r
}\r
return Status;\r
}\r
\r
-\r
/**\r
Reapply fixups on a fixed up PE32/PE32+ image to allow virutal calling at EFI\r
runtime.\r
VOID\r
EFIAPI\r
PeCoffLoaderRelocateImageForRuntime (\r
- IN PHYSICAL_ADDRESS ImageBase,\r
- IN PHYSICAL_ADDRESS VirtImageBase,\r
- IN UINTN ImageSize,\r
- IN VOID *RelocationData\r
+ IN PHYSICAL_ADDRESS ImageBase,\r
+ IN PHYSICAL_ADDRESS VirtImageBase,\r
+ IN UINTN ImageSize,\r
+ IN VOID *RelocationData\r
)\r
{\r
- CHAR8 *OldBase;\r
- CHAR8 *NewBase;\r
- EFI_IMAGE_DOS_HEADER *DosHdr;\r
- EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
- UINT32 NumberOfRvaAndSizes;\r
- EFI_IMAGE_DATA_DIRECTORY *DataDirectory;\r
- EFI_IMAGE_DATA_DIRECTORY *RelocDir;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBase;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBaseEnd;\r
- EFI_IMAGE_BASE_RELOCATION *RelocBaseOrig;\r
- UINT16 *Reloc;\r
- UINT16 *RelocEnd;\r
- CHAR8 *Fixup;\r
- CHAR8 *FixupBase;\r
- UINT16 *Fixup16;\r
- UINT32 *Fixup32;\r
- UINT64 *Fixup64;\r
- CHAR8 *FixupData;\r
- UINTN Adjust;\r
- RETURN_STATUS Status;\r
- PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
-\r
- if (RelocationData == NULL || ImageBase == 0x0 || VirtImageBase == 0x0) {\r
+ CHAR8 *OldBase;\r
+ CHAR8 *NewBase;\r
+ EFI_IMAGE_DOS_HEADER *DosHdr;\r
+ EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr;\r
+ UINT32 NumberOfRvaAndSizes;\r
+ EFI_IMAGE_DATA_DIRECTORY *DataDirectory;\r
+ EFI_IMAGE_DATA_DIRECTORY *RelocDir;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBase;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBaseEnd;\r
+ EFI_IMAGE_BASE_RELOCATION *RelocBaseOrig;\r
+ UINT16 *Reloc;\r
+ UINT16 *RelocEnd;\r
+ CHAR8 *Fixup;\r
+ CHAR8 *FixupBase;\r
+ UINT16 *Fixup16;\r
+ UINT32 *Fixup32;\r
+ UINT64 *Fixup64;\r
+ CHAR8 *FixupData;\r
+ UINTN Adjust;\r
+ RETURN_STATUS Status;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+\r
+ if ((RelocationData == NULL) || (ImageBase == 0x0) || (VirtImageBase == 0x0)) {\r
return;\r
}\r
\r
OldBase = (CHAR8 *)((UINTN)ImageBase);\r
NewBase = (CHAR8 *)((UINTN)VirtImageBase);\r
- Adjust = (UINTN) NewBase - (UINTN) OldBase;\r
+ Adjust = (UINTN)NewBase - (UINTN)OldBase;\r
\r
ImageContext.ImageAddress = ImageBase;\r
- ImageContext.ImageSize = ImageSize;\r
+ ImageContext.ImageSize = ImageSize;\r
\r
//\r
// Find the image's relocate dir info\r
//\r
// Not a valid PE image so Exit\r
//\r
- return ;\r
+ return;\r
}\r
\r
if (Hdr.Pe32->OptionalHeader.Magic == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) {\r
// Use PE32 offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32->OptionalHeader.NumberOfRvaAndSizes;\r
- DataDirectory = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32->OptionalHeader.DataDirectory[0]);\r
+ DataDirectory = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32->OptionalHeader.DataDirectory[0]);\r
} else {\r
//\r
// Use PE32+ offset\r
//\r
NumberOfRvaAndSizes = Hdr.Pe32Plus->OptionalHeader.NumberOfRvaAndSizes;\r
- DataDirectory = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32Plus->OptionalHeader.DataDirectory[0]);\r
+ DataDirectory = (EFI_IMAGE_DATA_DIRECTORY *)&(Hdr.Pe32Plus->OptionalHeader.DataDirectory[0]);\r
}\r
\r
//\r
// is present in the image. You have to check the NumberOfRvaAndSizes in\r
// the optional header to verify a desired directory entry is there.\r
//\r
- RelocBase = NULL;\r
+ RelocBase = NULL;\r
RelocBaseEnd = NULL;\r
if (NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC) {\r
- RelocDir = DataDirectory + EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC;\r
+ RelocDir = DataDirectory + EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC;\r
if ((RelocDir != NULL) && (RelocDir->Size > 0)) {\r
- RelocBase = (EFI_IMAGE_BASE_RELOCATION *) PeCoffLoaderImageAddress (&ImageContext, RelocDir->VirtualAddress, 0);\r
- RelocBaseEnd = (EFI_IMAGE_BASE_RELOCATION *) PeCoffLoaderImageAddress (&ImageContext,\r
- RelocDir->VirtualAddress + RelocDir->Size - 1,\r
- 0\r
- );\r
+ RelocBase = (EFI_IMAGE_BASE_RELOCATION *)PeCoffLoaderImageAddress (&ImageContext, RelocDir->VirtualAddress, 0);\r
+ RelocBaseEnd = (EFI_IMAGE_BASE_RELOCATION *)PeCoffLoaderImageAddress (\r
+ &ImageContext,\r
+ RelocDir->VirtualAddress + RelocDir->Size - 1,\r
+ 0\r
+ );\r
}\r
- if (RelocBase == NULL || RelocBaseEnd == NULL || (UINTN) RelocBaseEnd < (UINTN) RelocBase) {\r
+\r
+ if ((RelocBase == NULL) || (RelocBaseEnd == NULL) || ((UINTN)RelocBaseEnd < (UINTN)RelocBase)) {\r
//\r
// relocation block is not valid, just return\r
//\r
// Cannot find relocations, cannot continue to relocate the image, ASSERT for this invalid image.\r
//\r
ASSERT (FALSE);\r
- return ;\r
+ return;\r
}\r
\r
//\r
// by code will not be fixed up, since that would set them back to\r
// defaults.\r
//\r
- FixupData = RelocationData;\r
+ FixupData = RelocationData;\r
RelocBaseOrig = RelocBase;\r
- while ((UINTN) RelocBase < (UINTN) RelocBaseEnd) {\r
+ while ((UINTN)RelocBase < (UINTN)RelocBaseEnd) {\r
//\r
// Add check for RelocBase->SizeOfBlock field.\r
//\r
return;\r
}\r
\r
- Reloc = (UINT16 *) ((UINT8 *) RelocBase + sizeof (EFI_IMAGE_BASE_RELOCATION));\r
- RelocEnd = (UINT16 *) ((UINT8 *) RelocBase + RelocBase->SizeOfBlock);\r
+ Reloc = (UINT16 *)((UINT8 *)RelocBase + sizeof (EFI_IMAGE_BASE_RELOCATION));\r
+ RelocEnd = (UINT16 *)((UINT8 *)RelocBase + RelocBase->SizeOfBlock);\r
if ((UINTN)RelocEnd > (UINTN)RelocBaseOrig + RelocDir->Size) {\r
return;\r
}\r
//\r
// Run this relocation record\r
//\r
- while ((UINTN) Reloc < (UINTN) RelocEnd) {\r
-\r
+ while ((UINTN)Reloc < (UINTN)RelocEnd) {\r
Fixup = PeCoffLoaderImageAddress (&ImageContext, RelocBase->VirtualAddress + (*Reloc & 0xFFF), 0);\r
if (Fixup == NULL) {\r
return;\r
}\r
+\r
switch ((*Reloc) >> 12) {\r
+ case EFI_IMAGE_REL_BASED_ABSOLUTE:\r
+ break;\r
\r
- case EFI_IMAGE_REL_BASED_ABSOLUTE:\r
- break;\r
+ case EFI_IMAGE_REL_BASED_HIGH:\r
+ Fixup16 = (UINT16 *)Fixup;\r
+ if (*(UINT16 *)FixupData == *Fixup16) {\r
+ *Fixup16 = (UINT16)(*Fixup16 + ((UINT16)((UINT32)Adjust >> 16)));\r
+ }\r
\r
- case EFI_IMAGE_REL_BASED_HIGH:\r
- Fixup16 = (UINT16 *) Fixup;\r
- if (*(UINT16 *) FixupData == *Fixup16) {\r
- *Fixup16 = (UINT16) (*Fixup16 + ((UINT16) ((UINT32) Adjust >> 16)));\r
- }\r
+ FixupData = FixupData + sizeof (UINT16);\r
+ break;\r
\r
- FixupData = FixupData + sizeof (UINT16);\r
- break;\r
-\r
- case EFI_IMAGE_REL_BASED_LOW:\r
- Fixup16 = (UINT16 *) Fixup;\r
- if (*(UINT16 *) FixupData == *Fixup16) {\r
- *Fixup16 = (UINT16) (*Fixup16 + ((UINT16) Adjust & 0xffff));\r
- }\r
+ case EFI_IMAGE_REL_BASED_LOW:\r
+ Fixup16 = (UINT16 *)Fixup;\r
+ if (*(UINT16 *)FixupData == *Fixup16) {\r
+ *Fixup16 = (UINT16)(*Fixup16 + ((UINT16)Adjust & 0xffff));\r
+ }\r
\r
- FixupData = FixupData + sizeof (UINT16);\r
- break;\r
+ FixupData = FixupData + sizeof (UINT16);\r
+ break;\r
\r
- case EFI_IMAGE_REL_BASED_HIGHLOW:\r
- Fixup32 = (UINT32 *) Fixup;\r
- FixupData = ALIGN_POINTER (FixupData, sizeof (UINT32));\r
- if (*(UINT32 *) FixupData == *Fixup32) {\r
- *Fixup32 = *Fixup32 + (UINT32) Adjust;\r
- }\r
+ case EFI_IMAGE_REL_BASED_HIGHLOW:\r
+ Fixup32 = (UINT32 *)Fixup;\r
+ FixupData = ALIGN_POINTER (FixupData, sizeof (UINT32));\r
+ if (*(UINT32 *)FixupData == *Fixup32) {\r
+ *Fixup32 = *Fixup32 + (UINT32)Adjust;\r
+ }\r
\r
- FixupData = FixupData + sizeof (UINT32);\r
- break;\r
+ FixupData = FixupData + sizeof (UINT32);\r
+ break;\r
\r
- case EFI_IMAGE_REL_BASED_DIR64:\r
- Fixup64 = (UINT64 *)Fixup;\r
- FixupData = ALIGN_POINTER (FixupData, sizeof (UINT64));\r
- if (*(UINT64 *) FixupData == *Fixup64) {\r
- *Fixup64 = *Fixup64 + (UINT64)Adjust;\r
- }\r
+ case EFI_IMAGE_REL_BASED_DIR64:\r
+ Fixup64 = (UINT64 *)Fixup;\r
+ FixupData = ALIGN_POINTER (FixupData, sizeof (UINT64));\r
+ if (*(UINT64 *)FixupData == *Fixup64) {\r
+ *Fixup64 = *Fixup64 + (UINT64)Adjust;\r
+ }\r
\r
- FixupData = FixupData + sizeof (UINT64);\r
- break;\r
+ FixupData = FixupData + sizeof (UINT64);\r
+ break;\r
\r
- default:\r
- //\r
- // Only Itanium requires ConvertPeImage_Ex\r
- //\r
- Status = PeHotRelocateImageEx (Reloc, Fixup, &FixupData, Adjust);\r
- if (RETURN_ERROR (Status)) {\r
- return ;\r
- }\r
+ default:\r
+ //\r
+ // Only Itanium requires ConvertPeImage_Ex\r
+ //\r
+ Status = PeHotRelocateImageEx (Reloc, Fixup, &FixupData, Adjust);\r
+ if (RETURN_ERROR (Status)) {\r
+ return;\r
+ }\r
}\r
+\r
//\r
// Next relocation record\r
//\r
Reloc += 1;\r
}\r
+\r
//\r
// next reloc block\r
//\r
- RelocBase = (EFI_IMAGE_BASE_RELOCATION *) RelocEnd;\r
+ RelocBase = (EFI_IMAGE_BASE_RELOCATION *)RelocEnd;\r
}\r
}\r
}\r
\r
-\r
/**\r
Reads contents of a PE/COFF image from a buffer in system memory.\r
\r
RETURN_STATUS\r
EFIAPI\r
PeCoffLoaderImageReadFromMemory (\r
- IN VOID *FileHandle,\r
- IN UINTN FileOffset,\r
- IN OUT UINTN *ReadSize,\r
- OUT VOID *Buffer\r
+ IN VOID *FileHandle,\r
+ IN UINTN FileOffset,\r
+ IN OUT UINTN *ReadSize,\r
+ OUT VOID *Buffer\r
)\r
{\r
ASSERT (ReadSize != NULL);\r
//\r
// Macro definitions for RISC-V architecture.\r
//\r
-#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))\r
-#define RISCV_IMM_BITS 12\r
-#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)\r
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))\r
+#define RISCV_IMM_BITS 12\r
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)\r
#define RISCV_CONST_HIGH_PART(VALUE) \\r
(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))\r
\r
-\r
/**\r
Performs an Itanium-based specific relocation fixup and is a no-op on other\r
instruction sets.\r
**/\r
RETURN_STATUS\r
PeCoffLoaderRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
);\r
\r
-\r
/**\r
Performs an Itanium-based specific re-relocation fixup and is a no-op on other\r
instruction sets. This is used to re-relocated the image into the EFI virtual\r
**/\r
RETURN_STATUS\r
PeHotRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
);\r
\r
-\r
/**\r
Returns TRUE if the machine type of PE/COFF image is supported. Supported\r
does not mean the image can be executed it means the PE/COFF loader supports\r
**/\r
VOID *\r
PeCoffLoaderImageAddress (\r
- IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
- IN UINTN Address,\r
- IN UINTN TeStrippedOffset\r
+ IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext,\r
+ IN UINTN Address,\r
+ IN UINTN TeStrippedOffset\r
);\r
\r
#endif\r
\r
#include "BasePeCoffLibInternals.h"\r
\r
-\r
/**\r
Performs an Itanium-based specific relocation fixup and is a no-op on other\r
instruction sets.\r
**/\r
RETURN_STATUS\r
PeCoffLoaderRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
)\r
{\r
if ((Machine == IMAGE_FILE_MACHINE_I386) || (Machine == IMAGE_FILE_MACHINE_X64) ||\r
- (Machine == IMAGE_FILE_MACHINE_EBC) || (Machine == IMAGE_FILE_MACHINE_ARM64)) {\r
+ (Machine == IMAGE_FILE_MACHINE_EBC) || (Machine == IMAGE_FILE_MACHINE_ARM64))\r
+ {\r
return TRUE;\r
}\r
\r
**/\r
RETURN_STATUS\r
PeHotRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
}\r
-\r
**/\r
RETURN_STATUS\r
PeCoffLoaderRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
- UINT32 Value;\r
- UINT32 Value2;\r
- UINT32 *RiscVHi20Fixup;\r
+ UINT32 Value;\r
+ UINT32 Value2;\r
+ UINT32 *RiscVHi20Fixup;\r
\r
switch ((*Reloc) >> 12) {\r
- case EFI_IMAGE_REL_BASED_RISCV_HI20:\r
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:\r
*(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;\r
break;\r
\r
- case EFI_IMAGE_REL_BASED_RISCV_LOW12I:\r
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:\r
RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));\r
if (RiscVHi20Fixup != NULL) {\r
-\r
- Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);\r
- Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));\r
+ Value = (UINT32)(RV_X (*RiscVHi20Fixup, 12, 20) << 12);\r
+ Value2 = (UINT32)(RV_X (*(UINT32 *)Fixup, 20, 12));\r
if (Value2 & (RISCV_IMM_REACH/2)) {\r
Value2 |= ~(RISCV_IMM_REACH-1);\r
}\r
- Value += Value2;\r
- Value += (UINT32)Adjust;\r
- Value2 = RISCV_CONST_HIGH_PART (Value);\r
- *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\\r
- (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));\r
- *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\\r
+\r
+ Value += Value2;\r
+ Value += (UINT32)Adjust;\r
+ Value2 = RISCV_CONST_HIGH_PART (Value);\r
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \\r
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));\r
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \\r
(RV_X (*(UINT32 *)Fixup, 0, 20));\r
}\r
+\r
break;\r
\r
- case EFI_IMAGE_REL_BASED_RISCV_LOW12S:\r
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:\r
RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));\r
if (RiscVHi20Fixup != NULL) {\r
- Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);\r
- Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));\r
+ Value = (UINT32)(RV_X (*RiscVHi20Fixup, 12, 20) << 12);\r
+ Value2 = (UINT32)(RV_X (*(UINT32 *)Fixup, 7, 5) | (RV_X (*(UINT32 *)Fixup, 25, 7) << 5));\r
if (Value2 & (RISCV_IMM_REACH/2)) {\r
Value2 |= ~(RISCV_IMM_REACH-1);\r
}\r
- Value += Value2;\r
- Value += (UINT32)Adjust;\r
- Value2 = RISCV_CONST_HIGH_PART (Value);\r
+\r
+ Value += Value2;\r
+ Value += (UINT32)Adjust;\r
+ Value2 = RISCV_CONST_HIGH_PART (Value);\r
*(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \\r
- (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));\r
- Value2 = *(UINT32 *)Fixup & 0x01fff07f;\r
- Value &= RISCV_IMM_REACH - 1;\r
- *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));\r
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));\r
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;\r
+ Value &= RISCV_IMM_REACH - 1;\r
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X (Value, 0, 5) << 7) | (RV_X (Value, 5, 7) << 25)));\r
}\r
+\r
break;\r
\r
- default:\r
+ default:\r
return RETURN_UNSUPPORTED;\r
-\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
\r
**/\r
RETURN_STATUS\r
PeHotRelocateImageEx (\r
- IN UINT16 *Reloc,\r
- IN OUT CHAR8 *Fixup,\r
- IN OUT CHAR8 **FixupData,\r
- IN UINT64 Adjust\r
+ IN UINT16 *Reloc,\r
+ IN OUT CHAR8 *Fixup,\r
+ IN OUT CHAR8 **FixupData,\r
+ IN UINT64 Adjust\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
-\r
#include <Library/PerformanceLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
UINTN\r
EFIAPI\r
GetPerformanceMeasurement (\r
- IN UINTN LogEntryKey,\r
- OUT CONST VOID **Handle,\r
- OUT CONST CHAR8 **Token,\r
- OUT CONST CHAR8 **Module,\r
- OUT UINT64 *StartTimeStamp,\r
- OUT UINT64 *EndTimeStamp\r
+ IN UINTN LogEntryKey,\r
+ OUT CONST VOID **Handle,\r
+ OUT CONST CHAR8 **Token,\r
+ OUT CONST CHAR8 **Module,\r
+ OUT UINT64 *StartTimeStamp,\r
+ OUT UINT64 *EndTimeStamp\r
)\r
{\r
ASSERT (Handle != NULL);\r
UINTN\r
EFIAPI\r
GetPerformanceMeasurementEx (\r
- IN UINTN LogEntryKey,\r
- OUT CONST VOID **Handle,\r
- OUT CONST CHAR8 **Token,\r
- OUT CONST CHAR8 **Module,\r
- OUT UINT64 *StartTimeStamp,\r
- OUT UINT64 *EndTimeStamp,\r
- OUT UINT32 *Identifier\r
+ IN UINTN LogEntryKey,\r
+ OUT CONST VOID **Handle,\r
+ OUT CONST CHAR8 **Token,\r
+ OUT CONST CHAR8 **Module,\r
+ OUT UINT64 *StartTimeStamp,\r
+ OUT UINT64 *EndTimeStamp,\r
+ OUT UINT32 *Identifier\r
)\r
{\r
ASSERT (Handle != NULL);\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPerformanceLibraryPropertyMask) & PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPerformanceLibraryPropertyMask) & PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
LogPerformanceMeasurementEnabled (\r
- IN CONST UINTN Type\r
+ IN CONST UINTN Type\r
)\r
{\r
//\r
// When Performance measurement is enabled and the type is not filtered, the performance can be logged.\r
//\r
- if (PerformanceMeasurementEnabled () && (PcdGet8(PcdPerformanceLibraryPropertyMask) & Type) == 0) {\r
+ if (PerformanceMeasurementEnabled () && ((PcdGet8 (PcdPerformanceLibraryPropertyMask) & Type) == 0)) {\r
return TRUE;\r
}\r
+\r
return FALSE;\r
}\r
IN UINT32 Value\r
)\r
{\r
- DEBUG((DEBUG_INFO, "POST %08x\n", Value));\r
+ DEBUG ((DEBUG_INFO, "POST %08x\n", Value));\r
return Value;\r
}\r
\r
-\r
/**\r
Sends an 32-bit value to a POST and associated ASCII string.\r
\r
IN CONST CHAR8 *Description OPTIONAL\r
)\r
{\r
- DEBUG((DEBUG_INFO, "POST %08x - %s\n", Value, Description));\r
+ DEBUG ((DEBUG_INFO, "POST %08x - %s\n", Value, Description));\r
return Value;\r
}\r
\r
-\r
/**\r
Returns TRUE if POST Codes are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if POST code descriptions are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
}\r
)\r
{\r
switch (PcdGet8 (PcdPort80DataWidth)) {\r
- case 8:\r
- IoWrite8 (0x80, (UINT8)(Value));\r
- break;\r
- case 16:\r
- IoWrite16 (0x80, (UINT16)(Value));\r
- break;\r
- case 32:\r
- IoWrite32 (0x80, Value);\r
- break;\r
- default:\r
- //\r
- // Assert on the invalid data width\r
- //\r
- ASSERT (FALSE);\r
- break;\r
+ case 8:\r
+ IoWrite8 (0x80, (UINT8)(Value));\r
+ break;\r
+ case 16:\r
+ IoWrite16 (0x80, (UINT16)(Value));\r
+ break;\r
+ case 32:\r
+ IoWrite32 (0x80, Value);\r
+ break;\r
+ default:\r
+ //\r
+ // Assert on the invalid data width\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
\r
return Value;\r
}\r
\r
-\r
/**\r
Sends an 32-bit value to a POST and associated ASCII string.\r
\r
return Value;\r
}\r
\r
-\r
/**\r
Returns TRUE if POST Codes are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if POST code descriptions are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
}\r
// A NULL VA_LIST can not be passed into BasePrintLibSPrintMarker() because some\r
// compilers define VA_LIST to be a structure.\r
//\r
-VA_LIST gNullVaList;\r
+VA_LIST gNullVaList;\r
\r
-#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)\r
+#define ASSERT_UNICODE_BUFFER(Buffer) ASSERT ((((UINTN) (Buffer)) & 0x01) == 0)\r
\r
/**\r
Produces a Null-terminated Unicode string in an output buffer based on\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN NumberOfPrinted;\r
+ VA_LIST Marker;\r
+ UINTN NumberOfPrinted;\r
\r
VA_START (Marker, FormatString);\r
NumberOfPrinted = UnicodeVSPrint (StartOfBuffer, BufferSize, FormatString, Marker);\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN NumberOfPrinted;\r
+ VA_LIST Marker;\r
+ UINTN NumberOfPrinted;\r
\r
VA_START (Marker, FormatString);\r
NumberOfPrinted = UnicodeVSPrintAsciiFormat (StartOfBuffer, BufferSize, FormatString, Marker);\r
return NumberOfPrinted;\r
}\r
\r
-\r
/**\r
Converts a decimal value to a Null-terminated Unicode string.\r
\r
IN UINTN Width\r
)\r
{\r
- ASSERT_UNICODE_BUFFER(Buffer);\r
+ ASSERT_UNICODE_BUFFER (Buffer);\r
return BasePrintLibConvertValueToStringS ((CHAR8 *)Buffer, BufferSize, Flags, Value, Width, 2);\r
}\r
\r
UINTN\r
EFIAPI\r
AsciiVSPrint (\r
- OUT CHAR8 *StartOfBuffer,\r
- IN UINTN BufferSize,\r
- IN CONST CHAR8 *FormatString,\r
- IN VA_LIST Marker\r
+ OUT CHAR8 *StartOfBuffer,\r
+ IN UINTN BufferSize,\r
+ IN CONST CHAR8 *FormatString,\r
+ IN VA_LIST Marker\r
)\r
{\r
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, Marker, NULL);\r
UINTN\r
EFIAPI\r
AsciiBSPrint (\r
- OUT CHAR8 *StartOfBuffer,\r
- IN UINTN BufferSize,\r
- IN CONST CHAR8 *FormatString,\r
- IN BASE_LIST Marker\r
+ OUT CHAR8 *StartOfBuffer,\r
+ IN UINTN BufferSize,\r
+ IN CONST CHAR8 *FormatString,\r
+ IN BASE_LIST Marker\r
)\r
{\r
return BasePrintLibSPrintMarker (StartOfBuffer, BufferSize, 0, FormatString, gNullVaList, Marker);\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN NumberOfPrinted;\r
+ VA_LIST Marker;\r
+ UINTN NumberOfPrinted;\r
\r
VA_START (Marker, FormatString);\r
NumberOfPrinted = AsciiVSPrint (StartOfBuffer, BufferSize, FormatString, Marker);\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN NumberOfPrinted;\r
+ VA_LIST Marker;\r
+ UINTN NumberOfPrinted;\r
\r
VA_START (Marker, FormatString);\r
NumberOfPrinted = AsciiVSPrintUnicodeFormat (StartOfBuffer, BufferSize, FormatString, Marker);\r
RETURN_STATUS\r
EFIAPI\r
AsciiValueToStringS (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN BufferSize,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width\r
)\r
{\r
return BasePrintLibConvertValueToStringS (Buffer, BufferSize, Flags, Value, Width, 1);\r
UINTN\r
EFIAPI\r
SPrintLength (\r
- IN CONST CHAR16 *FormatString,\r
+ IN CONST CHAR16 *FormatString,\r
IN VA_LIST Marker\r
)\r
{\r
UINTN\r
EFIAPI\r
SPrintLengthAsciiFormat (\r
- IN CONST CHAR8 *FormatString,\r
- IN VA_LIST Marker\r
+ IN CONST CHAR8 *FormatString,\r
+ IN VA_LIST Marker\r
)\r
{\r
return BasePrintLibSPrintMarker (NULL, 0, OUTPUT_UNICODE | COUNT_ONLY_NO_PRINT, (CHAR8 *)FormatString, Marker, NULL);\r
\r
#include "PrintLibInternal.h"\r
\r
-#define WARNING_STATUS_NUMBER 5\r
-#define ERROR_STATUS_NUMBER 33\r
+#define WARNING_STATUS_NUMBER 5\r
+#define ERROR_STATUS_NUMBER 33\r
\r
//\r
// Safe print checks\r
//\r
-#define RSIZE_MAX (PcdGet32 (PcdMaximumUnicodeStringLength))\r
-#define ASCII_RSIZE_MAX (PcdGet32 (PcdMaximumAsciiStringLength))\r
+#define RSIZE_MAX (PcdGet32 (PcdMaximumUnicodeStringLength))\r
+#define ASCII_RSIZE_MAX (PcdGet32 (PcdMaximumAsciiStringLength))\r
\r
#define SAFE_PRINT_CONSTRAINT_CHECK(Expression, RetVal) \\r
do { \\r
} \\r
} while (FALSE)\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mHexStr[] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mHexStr[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };\r
\r
//\r
// Longest string: RETURN_WARN_BUFFER_TOO_SMALL => 24 characters plus NUL byte\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mWarningString[][24+1] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mWarningString[][24+1] = {\r
"Success", // RETURN_SUCCESS = 0\r
"Warning Unknown Glyph", // RETURN_WARN_UNKNOWN_GLYPH = 1\r
"Warning Delete Failure", // RETURN_WARN_DELETE_FAILURE = 2\r
//\r
// Longest string: RETURN_INCOMPATIBLE_VERSION => 20 characters plus NUL byte\r
//\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 mErrorString[][20+1] = {\r
"Load Error", // RETURN_LOAD_ERROR = 1 | MAX_BIT\r
"Invalid Parameter", // RETURN_INVALID_PARAMETER = 2 | MAX_BIT\r
"Unsupported", // RETURN_UNSUPPORTED = 3 | MAX_BIT\r
"Compromised Data" // RETURN_COMPROMISED_DATA = 33 | MAX_BIT\r
};\r
\r
-\r
/**\r
Internal function that places the character into the Buffer.\r
\r
**/\r
CHAR8 *\r
BasePrintLibFillBuffer (\r
- OUT CHAR8 *Buffer,\r
- IN CHAR8 *EndBuffer,\r
- IN INTN Length,\r
- IN UINTN Character,\r
- IN INTN Increment\r
+ OUT CHAR8 *Buffer,\r
+ IN CHAR8 *EndBuffer,\r
+ IN INTN Length,\r
+ IN UINTN Character,\r
+ IN INTN Increment\r
)\r
{\r
INTN Index;\r
\r
for (Index = 0; Index < Length && Buffer < EndBuffer; Index++) {\r
- *Buffer = (CHAR8) Character;\r
+ *Buffer = (CHAR8)Character;\r
if (Increment != 1) {\r
*(Buffer + 1) = (CHAR8)(Character >> 8);\r
}\r
+\r
Buffer += Increment;\r
}\r
\r
//\r
*Buffer = 0;\r
do {\r
- Value = (INT64)DivU64x32Remainder ((UINT64)Value, (UINT32)Radix, &Remainder);\r
+ Value = (INT64)DivU64x32Remainder ((UINT64)Value, (UINT32)Radix, &Remainder);\r
*(++Buffer) = mHexStr[Remainder];\r
} while (Value != 0);\r
\r
**/\r
UINTN\r
BasePrintLibConvertValueToString (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width,\r
- IN UINTN Increment\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width,\r
+ IN UINTN Increment\r
)\r
{\r
CHAR8 *OriginalBuffer;\r
//\r
// Width is 0 or COMMA_TYPE is set, PREFIX_ZERO is ignored.\r
//\r
- if (Width == 0 || (Flags & COMMA_TYPE) != 0) {\r
- Flags &= ~((UINTN) PREFIX_ZERO);\r
+ if ((Width == 0) || ((Flags & COMMA_TYPE) != 0)) {\r
+ Flags &= ~((UINTN)PREFIX_ZERO);\r
}\r
+\r
//\r
// If Width is 0 then a width of MAXIMUM_VALUE_CHARACTERS is assumed.\r
//\r
if (Width == 0) {\r
Width = MAXIMUM_VALUE_CHARACTERS - 1;\r
}\r
+\r
//\r
// Set the tag for the end of the input Buffer.\r
//\r
// Convert decimal negative\r
//\r
if ((Value < 0) && ((Flags & RADIX_HEX) == 0)) {\r
- Value = -Value;\r
+ Value = -Value;\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, '-', Increment);\r
Width--;\r
}\r
//\r
// Count the length of the value string.\r
//\r
- Radix = ((Flags & RADIX_HEX) == 0)? 10 : 16;\r
+ Radix = ((Flags & RADIX_HEX) == 0) ? 10 : 16;\r
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);\r
- Count = ValueBufferPtr - ValueBuffer;\r
+ Count = ValueBufferPtr - ValueBuffer;\r
\r
//\r
// Append Zero\r
if (Digits != 0) {\r
Digits = 3 - Digits;\r
}\r
+\r
for (Index = 0; Index < Count; Index++) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, *ValueBufferPtr--, Increment);\r
if ((Flags & COMMA_TYPE) != 0) {\r
**/\r
RETURN_STATUS\r
BasePrintLibConvertValueToStringS (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN BufferSize,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width,\r
- IN UINTN Increment\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width,\r
+ IN UINTN Increment\r
)\r
{\r
CHAR8 *EndBuffer;\r
//\r
// Width is 0 or COMMA_TYPE is set, PREFIX_ZERO is ignored.\r
//\r
- if (Width == 0 || (Flags & COMMA_TYPE) != 0) {\r
- Flags &= ~((UINTN) PREFIX_ZERO);\r
+ if ((Width == 0) || ((Flags & COMMA_TYPE) != 0)) {\r
+ Flags &= ~((UINTN)PREFIX_ZERO);\r
}\r
+\r
//\r
// If Width is 0 then a width of MAXIMUM_VALUE_CHARACTERS is assumed.\r
//\r
// Count the characters of the output string.\r
//\r
Count = 0;\r
- Radix = ((Flags & RADIX_HEX) == 0)? 10 : 16;\r
+ Radix = ((Flags & RADIX_HEX) == 0) ? 10 : 16;\r
\r
if ((Flags & PREFIX_ZERO) != 0) {\r
Count = Width;\r
} else {\r
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);\r
}\r
+\r
Digits = ValueBufferPtr - ValueBuffer;\r
Count += Digits;\r
\r
// Convert decimal negative\r
//\r
if ((Value < 0) && ((Flags & RADIX_HEX) == 0)) {\r
- Value = -Value;\r
+ Value = -Value;\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, '-', Increment);\r
Width--;\r
}\r
// Count the length of the value string.\r
//\r
ValueBufferPtr = BasePrintLibValueToString (ValueBuffer, Value, Radix);\r
- Count = ValueBufferPtr - ValueBuffer;\r
+ Count = ValueBufferPtr - ValueBuffer;\r
\r
//\r
// Append Zero\r
if (Digits != 0) {\r
Digits = 3 - Digits;\r
}\r
+\r
for (Index = 0; Index < Count; Index++) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, *ValueBufferPtr--, Increment);\r
if ((Flags & COMMA_TYPE) != 0) {\r
IN BASE_LIST BaseListMarker OPTIONAL\r
)\r
{\r
- CHAR8 *OriginalBuffer;\r
- CHAR8 *EndBuffer;\r
- CHAR8 ValueBuffer[MAXIMUM_VALUE_CHARACTERS];\r
- UINT32 BytesPerOutputCharacter;\r
- UINTN BytesPerFormatCharacter;\r
- UINTN FormatMask;\r
- UINTN FormatCharacter;\r
- UINTN Width;\r
- UINTN Precision;\r
- INT64 Value;\r
- CONST CHAR8 *ArgumentString;\r
- UINTN Character;\r
- GUID *TmpGuid;\r
- TIME *TmpTime;\r
- UINTN Count;\r
- UINTN ArgumentMask;\r
- INTN BytesPerArgumentCharacter;\r
- UINTN ArgumentCharacter;\r
- BOOLEAN Done;\r
- UINTN Index;\r
- CHAR8 Prefix;\r
- BOOLEAN ZeroPad;\r
- BOOLEAN Comma;\r
- UINTN Digits;\r
- UINTN Radix;\r
- RETURN_STATUS Status;\r
- UINT32 GuidData1;\r
- UINT16 GuidData2;\r
- UINT16 GuidData3;\r
- UINTN LengthToReturn;\r
+ CHAR8 *OriginalBuffer;\r
+ CHAR8 *EndBuffer;\r
+ CHAR8 ValueBuffer[MAXIMUM_VALUE_CHARACTERS];\r
+ UINT32 BytesPerOutputCharacter;\r
+ UINTN BytesPerFormatCharacter;\r
+ UINTN FormatMask;\r
+ UINTN FormatCharacter;\r
+ UINTN Width;\r
+ UINTN Precision;\r
+ INT64 Value;\r
+ CONST CHAR8 *ArgumentString;\r
+ UINTN Character;\r
+ GUID *TmpGuid;\r
+ TIME *TmpTime;\r
+ UINTN Count;\r
+ UINTN ArgumentMask;\r
+ INTN BytesPerArgumentCharacter;\r
+ UINTN ArgumentCharacter;\r
+ BOOLEAN Done;\r
+ UINTN Index;\r
+ CHAR8 Prefix;\r
+ BOOLEAN ZeroPad;\r
+ BOOLEAN Comma;\r
+ UINTN Digits;\r
+ UINTN Radix;\r
+ RETURN_STATUS Status;\r
+ UINT32 GuidData1;\r
+ UINT16 GuidData2;\r
+ UINT16 GuidData3;\r
+ UINTN LengthToReturn;\r
\r
//\r
// If you change this code be sure to match the 2 versions of this function.\r
if (RSIZE_MAX != 0) {\r
SAFE_PRINT_CONSTRAINT_CHECK ((BufferSize <= RSIZE_MAX), 0);\r
}\r
+\r
BytesPerOutputCharacter = 2;\r
} else {\r
if (ASCII_RSIZE_MAX != 0) {\r
SAFE_PRINT_CONSTRAINT_CHECK ((BufferSize <= ASCII_RSIZE_MAX), 0);\r
}\r
+\r
BytesPerOutputCharacter = 1;\r
}\r
\r
if (RSIZE_MAX != 0) {\r
SAFE_PRINT_CONSTRAINT_CHECK ((StrnLenS ((CHAR16 *)Format, RSIZE_MAX + 1) <= RSIZE_MAX), 0);\r
}\r
+\r
BytesPerFormatCharacter = 2;\r
- FormatMask = 0xffff;\r
+ FormatMask = 0xffff;\r
} else {\r
if (ASCII_RSIZE_MAX != 0) {\r
SAFE_PRINT_CONSTRAINT_CHECK ((AsciiStrnLenS (Format, ASCII_RSIZE_MAX + 1) <= ASCII_RSIZE_MAX), 0);\r
}\r
+\r
BytesPerFormatCharacter = 1;\r
- FormatMask = 0xff;\r
+ FormatMask = 0xff;\r
}\r
\r
if ((Flags & COUNT_ONLY_NO_PRINT) != 0) {\r
}\r
\r
LengthToReturn = 0;\r
- EndBuffer = NULL;\r
+ EndBuffer = NULL;\r
OriginalBuffer = NULL;\r
\r
//\r
if ((Buffer != NULL) && (Buffer >= EndBuffer)) {\r
break;\r
}\r
+\r
//\r
// Clear all the flag bits except those that may have been passed in\r
//\r
- Flags &= (UINTN) (OUTPUT_UNICODE | FORMAT_UNICODE | COUNT_ONLY_NO_PRINT);\r
+ Flags &= (UINTN)(OUTPUT_UNICODE | FORMAT_UNICODE | COUNT_ONLY_NO_PRINT);\r
\r
//\r
// Set the default width to zero, and the default precision to 1\r
Digits = 0;\r
\r
switch (FormatCharacter) {\r
- case '%':\r
- //\r
- // Parse Flags and Width\r
- //\r
- for (Done = FALSE; !Done; ) {\r
- Format += BytesPerFormatCharacter;\r
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
+ case '%':\r
+ //\r
+ // Parse Flags and Width\r
+ //\r
+ for (Done = FALSE; !Done; ) {\r
+ Format += BytesPerFormatCharacter;\r
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
+ switch (FormatCharacter) {\r
+ case '.':\r
+ Flags |= PRECISION;\r
+ break;\r
+ case '-':\r
+ Flags |= LEFT_JUSTIFY;\r
+ break;\r
+ case '+':\r
+ Flags |= PREFIX_SIGN;\r
+ break;\r
+ case ' ':\r
+ Flags |= PREFIX_BLANK;\r
+ break;\r
+ case ',':\r
+ Flags |= COMMA_TYPE;\r
+ break;\r
+ case 'L':\r
+ case 'l':\r
+ Flags |= LONG_TYPE;\r
+ break;\r
+ case '*':\r
+ if ((Flags & PRECISION) == 0) {\r
+ Flags |= PAD_TO_WIDTH;\r
+ if (BaseListMarker == NULL) {\r
+ Width = VA_ARG (VaListMarker, UINTN);\r
+ } else {\r
+ Width = BASE_ARG (BaseListMarker, UINTN);\r
+ }\r
+ } else {\r
+ if (BaseListMarker == NULL) {\r
+ Precision = VA_ARG (VaListMarker, UINTN);\r
+ } else {\r
+ Precision = BASE_ARG (BaseListMarker, UINTN);\r
+ }\r
+ }\r
+\r
+ break;\r
+ case '0':\r
+ if ((Flags & PRECISION) == 0) {\r
+ Flags |= PREFIX_ZERO;\r
+ }\r
+\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9':\r
+ for (Count = 0; ((FormatCharacter >= '0') && (FormatCharacter <= '9')); ) {\r
+ Count = (Count * 10) + FormatCharacter - '0';\r
+ Format += BytesPerFormatCharacter;\r
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
+ }\r
+\r
+ Format -= BytesPerFormatCharacter;\r
+ if ((Flags & PRECISION) == 0) {\r
+ Flags |= PAD_TO_WIDTH;\r
+ Width = Count;\r
+ } else {\r
+ Precision = Count;\r
+ }\r
+\r
+ break;\r
+\r
+ case '\0':\r
+ //\r
+ // Make no output if Format string terminates unexpectedly when\r
+ // looking up for flag, width, precision and type.\r
+ //\r
+ Format -= BytesPerFormatCharacter;\r
+ Precision = 0;\r
+ //\r
+ // break skipped on purpose.\r
+ //\r
+ default:\r
+ Done = TRUE;\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Handle each argument type\r
+ //\r
switch (FormatCharacter) {\r
- case '.':\r
- Flags |= PRECISION;\r
- break;\r
- case '-':\r
- Flags |= LEFT_JUSTIFY;\r
- break;\r
- case '+':\r
- Flags |= PREFIX_SIGN;\r
- break;\r
- case ' ':\r
- Flags |= PREFIX_BLANK;\r
- break;\r
- case ',':\r
- Flags |= COMMA_TYPE;\r
- break;\r
- case 'L':\r
- case 'l':\r
- Flags |= LONG_TYPE;\r
- break;\r
- case '*':\r
- if ((Flags & PRECISION) == 0) {\r
- Flags |= PAD_TO_WIDTH;\r
- if (BaseListMarker == NULL) {\r
- Width = VA_ARG (VaListMarker, UINTN);\r
- } else {\r
- Width = BASE_ARG (BaseListMarker, UINTN);\r
- }\r
- } else {\r
- if (BaseListMarker == NULL) {\r
- Precision = VA_ARG (VaListMarker, UINTN);\r
- } else {\r
- Precision = BASE_ARG (BaseListMarker, UINTN);\r
+ case 'p':\r
+ //\r
+ // Flag space, +, 0, L & l are invalid for type p.\r
+ //\r
+ Flags &= ~((UINTN)(PREFIX_BLANK | PREFIX_SIGN | PREFIX_ZERO | LONG_TYPE));\r
+ if (sizeof (VOID *) > 4) {\r
+ Flags |= LONG_TYPE;\r
}\r
- }\r
- break;\r
- case '0':\r
- if ((Flags & PRECISION) == 0) {\r
- Flags |= PREFIX_ZERO;\r
- }\r
- case '1':\r
- case '2':\r
- case '3':\r
- case '4':\r
- case '5':\r
- case '6':\r
- case '7':\r
- case '8':\r
- case '9':\r
- for (Count = 0; ((FormatCharacter >= '0') && (FormatCharacter <= '9')); ){\r
- Count = (Count * 10) + FormatCharacter - '0';\r
- Format += BytesPerFormatCharacter;\r
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
- }\r
- Format -= BytesPerFormatCharacter;\r
- if ((Flags & PRECISION) == 0) {\r
- Flags |= PAD_TO_WIDTH;\r
- Width = Count;\r
- } else {\r
- Precision = Count;\r
- }\r
- break;\r
\r
- case '\0':\r
//\r
- // Make no output if Format string terminates unexpectedly when\r
- // looking up for flag, width, precision and type.\r
+ // break skipped on purpose\r
+ //\r
+ case 'X':\r
+ Flags |= PREFIX_ZERO;\r
//\r
- Format -= BytesPerFormatCharacter;\r
- Precision = 0;\r
+ // break skipped on purpose\r
//\r
- // break skipped on purpose.\r
+ case 'x':\r
+ Flags |= RADIX_HEX;\r
//\r
- default:\r
- Done = TRUE;\r
- break;\r
- }\r
- }\r
+ // break skipped on purpose\r
+ //\r
+ case 'u':\r
+ if ((Flags & RADIX_HEX) == 0) {\r
+ Flags &= ~((UINTN)(PREFIX_SIGN));\r
+ Flags |= UNSIGNED_TYPE;\r
+ }\r
\r
- //\r
- // Handle each argument type\r
- //\r
- switch (FormatCharacter) {\r
- case 'p':\r
- //\r
- // Flag space, +, 0, L & l are invalid for type p.\r
- //\r
- Flags &= ~((UINTN) (PREFIX_BLANK | PREFIX_SIGN | PREFIX_ZERO | LONG_TYPE));\r
- if (sizeof (VOID *) > 4) {\r
- Flags |= LONG_TYPE;\r
- }\r
- //\r
- // break skipped on purpose\r
- //\r
- case 'X':\r
- Flags |= PREFIX_ZERO;\r
- //\r
- // break skipped on purpose\r
- //\r
- case 'x':\r
- Flags |= RADIX_HEX;\r
- //\r
- // break skipped on purpose\r
- //\r
- case 'u':\r
- if ((Flags & RADIX_HEX) == 0) {\r
- Flags &= ~((UINTN) (PREFIX_SIGN));\r
- Flags |= UNSIGNED_TYPE;\r
- }\r
- //\r
- // break skipped on purpose\r
- //\r
- case 'd':\r
- if ((Flags & LONG_TYPE) == 0) {\r
//\r
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
- // This assumption is made so the format string definition is compatible with the ANSI C\r
- // Specification for formatted strings. It is recommended that the Base Types be used\r
- // everywhere, but in this one case, compliance with ANSI C is more important, and\r
- // provides an implementation that is compatible with that largest possible set of CPU\r
- // architectures. This is why the type "int" is used in this one case.\r
+ // break skipped on purpose\r
//\r
- if (BaseListMarker == NULL) {\r
- Value = VA_ARG (VaListMarker, int);\r
- } else {\r
- Value = BASE_ARG (BaseListMarker, int);\r
- }\r
- } else {\r
- if (BaseListMarker == NULL) {\r
- Value = VA_ARG (VaListMarker, INT64);\r
- } else {\r
- Value = BASE_ARG (BaseListMarker, INT64);\r
- }\r
- }\r
- if ((Flags & PREFIX_BLANK) != 0) {\r
- Prefix = ' ';\r
- }\r
- if ((Flags & PREFIX_SIGN) != 0) {\r
- Prefix = '+';\r
- }\r
- if ((Flags & COMMA_TYPE) != 0) {\r
- Comma = TRUE;\r
- }\r
- if ((Flags & RADIX_HEX) == 0) {\r
- Radix = 10;\r
- if (Comma) {\r
- Flags &= ~((UINTN) PREFIX_ZERO);\r
- Precision = 1;\r
- }\r
- if (Value < 0 && (Flags & UNSIGNED_TYPE) == 0) {\r
- Flags |= PREFIX_SIGN;\r
- Prefix = '-';\r
- Value = -Value;\r
- } else if ((Flags & UNSIGNED_TYPE) != 0 && (Flags & LONG_TYPE) == 0) {\r
+ case 'd':\r
+ if ((Flags & LONG_TYPE) == 0) {\r
+ //\r
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
+ // This assumption is made so the format string definition is compatible with the ANSI C\r
+ // Specification for formatted strings. It is recommended that the Base Types be used\r
+ // everywhere, but in this one case, compliance with ANSI C is more important, and\r
+ // provides an implementation that is compatible with that largest possible set of CPU\r
+ // architectures. This is why the type "int" is used in this one case.\r
+ //\r
+ if (BaseListMarker == NULL) {\r
+ Value = VA_ARG (VaListMarker, int);\r
+ } else {\r
+ Value = BASE_ARG (BaseListMarker, int);\r
+ }\r
+ } else {\r
+ if (BaseListMarker == NULL) {\r
+ Value = VA_ARG (VaListMarker, INT64);\r
+ } else {\r
+ Value = BASE_ARG (BaseListMarker, INT64);\r
+ }\r
+ }\r
+\r
+ if ((Flags & PREFIX_BLANK) != 0) {\r
+ Prefix = ' ';\r
+ }\r
+\r
+ if ((Flags & PREFIX_SIGN) != 0) {\r
+ Prefix = '+';\r
+ }\r
+\r
+ if ((Flags & COMMA_TYPE) != 0) {\r
+ Comma = TRUE;\r
+ }\r
+\r
+ if ((Flags & RADIX_HEX) == 0) {\r
+ Radix = 10;\r
+ if (Comma) {\r
+ Flags &= ~((UINTN)PREFIX_ZERO);\r
+ Precision = 1;\r
+ }\r
+\r
+ if ((Value < 0) && ((Flags & UNSIGNED_TYPE) == 0)) {\r
+ Flags |= PREFIX_SIGN;\r
+ Prefix = '-';\r
+ Value = -Value;\r
+ } else if (((Flags & UNSIGNED_TYPE) != 0) && ((Flags & LONG_TYPE) == 0)) {\r
+ //\r
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
+ // This assumption is made so the format string definition is compatible with the ANSI C\r
+ // Specification for formatted strings. It is recommended that the Base Types be used\r
+ // everywhere, but in this one case, compliance with ANSI C is more important, and\r
+ // provides an implementation that is compatible with that largest possible set of CPU\r
+ // architectures. This is why the type "unsigned int" is used in this one case.\r
+ //\r
+ Value = (unsigned int)Value;\r
+ }\r
+ } else {\r
+ Radix = 16;\r
+ Comma = FALSE;\r
+ if (((Flags & LONG_TYPE) == 0) && (Value < 0)) {\r
+ //\r
+ // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
+ // This assumption is made so the format string definition is compatible with the ANSI C\r
+ // Specification for formatted strings. It is recommended that the Base Types be used\r
+ // everywhere, but in this one case, compliance with ANSI C is more important, and\r
+ // provides an implementation that is compatible with that largest possible set of CPU\r
+ // architectures. This is why the type "unsigned int" is used in this one case.\r
+ //\r
+ Value = (unsigned int)Value;\r
+ }\r
+ }\r
+\r
//\r
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
- // This assumption is made so the format string definition is compatible with the ANSI C\r
- // Specification for formatted strings. It is recommended that the Base Types be used\r
- // everywhere, but in this one case, compliance with ANSI C is more important, and\r
- // provides an implementation that is compatible with that largest possible set of CPU\r
- // architectures. This is why the type "unsigned int" is used in this one case.\r
+ // Convert Value to a reversed string\r
//\r
- Value = (unsigned int)Value;\r
- }\r
- } else {\r
- Radix = 16;\r
- Comma = FALSE;\r
- if ((Flags & LONG_TYPE) == 0 && Value < 0) {\r
+ Count = BasePrintLibValueToString (ValueBuffer, Value, Radix) - ValueBuffer;\r
+ if ((Value == 0) && (Precision == 0)) {\r
+ Count = 0;\r
+ }\r
+\r
+ ArgumentString = (CHAR8 *)ValueBuffer + Count;\r
+\r
+ Digits = Count % 3;\r
+ if (Digits != 0) {\r
+ Digits = 3 - Digits;\r
+ }\r
+\r
+ if (Comma && (Count != 0)) {\r
+ Count += ((Count - 1) / 3);\r
+ }\r
+\r
+ if (Prefix != 0) {\r
+ Count++;\r
+ Precision++;\r
+ }\r
+\r
+ Flags |= ARGUMENT_REVERSED;\r
+ ZeroPad = TRUE;\r
+ if ((Flags & PREFIX_ZERO) != 0) {\r
+ if ((Flags & LEFT_JUSTIFY) == 0) {\r
+ if ((Flags & PAD_TO_WIDTH) != 0) {\r
+ if ((Flags & PRECISION) == 0) {\r
+ Precision = Width;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ break;\r
+\r
+ case 's':\r
+ case 'S':\r
+ Flags |= ARGUMENT_UNICODE;\r
+ //\r
+ // break skipped on purpose\r
+ //\r
+ case 'a':\r
+ if (BaseListMarker == NULL) {\r
+ ArgumentString = VA_ARG (VaListMarker, CHAR8 *);\r
+ } else {\r
+ ArgumentString = BASE_ARG (BaseListMarker, CHAR8 *);\r
+ }\r
+\r
+ if (ArgumentString == NULL) {\r
+ Flags &= ~((UINTN)ARGUMENT_UNICODE);\r
+ ArgumentString = "<null string>";\r
+ }\r
+\r
//\r
- // 'd', 'u', 'x', and 'X' that are not preceded by 'l' or 'L' are assumed to be type "int".\r
- // This assumption is made so the format string definition is compatible with the ANSI C\r
- // Specification for formatted strings. It is recommended that the Base Types be used\r
- // everywhere, but in this one case, compliance with ANSI C is more important, and\r
- // provides an implementation that is compatible with that largest possible set of CPU\r
- // architectures. This is why the type "unsigned int" is used in this one case.\r
+ // Set the default precision for string to be zero if not specified.\r
//\r
- Value = (unsigned int)Value;\r
- }\r
- }\r
- //\r
- // Convert Value to a reversed string\r
- //\r
- Count = BasePrintLibValueToString (ValueBuffer, Value, Radix) - ValueBuffer;\r
- if (Value == 0 && Precision == 0) {\r
- Count = 0;\r
- }\r
- ArgumentString = (CHAR8 *)ValueBuffer + Count;\r
+ if ((Flags & PRECISION) == 0) {\r
+ Precision = 0;\r
+ }\r
\r
- Digits = Count % 3;\r
- if (Digits != 0) {\r
- Digits = 3 - Digits;\r
- }\r
- if (Comma && Count != 0) {\r
- Count += ((Count - 1) / 3);\r
- }\r
- if (Prefix != 0) {\r
- Count++;\r
- Precision++;\r
- }\r
- Flags |= ARGUMENT_REVERSED;\r
- ZeroPad = TRUE;\r
- if ((Flags & PREFIX_ZERO) != 0) {\r
- if ((Flags & LEFT_JUSTIFY) == 0) {\r
- if ((Flags & PAD_TO_WIDTH) != 0) {\r
- if ((Flags & PRECISION) == 0) {\r
- Precision = Width;\r
+ break;\r
+\r
+ case 'c':\r
+ if (BaseListMarker == NULL) {\r
+ Character = VA_ARG (VaListMarker, UINTN) & 0xffff;\r
+ } else {\r
+ Character = BASE_ARG (BaseListMarker, UINTN) & 0xffff;\r
+ }\r
+\r
+ ArgumentString = (CHAR8 *)&Character;\r
+ Flags |= ARGUMENT_UNICODE;\r
+ break;\r
+\r
+ case 'g':\r
+ if (BaseListMarker == NULL) {\r
+ TmpGuid = VA_ARG (VaListMarker, GUID *);\r
+ } else {\r
+ TmpGuid = BASE_ARG (BaseListMarker, GUID *);\r
+ }\r
+\r
+ if (TmpGuid == NULL) {\r
+ ArgumentString = "<null guid>";\r
+ } else {\r
+ GuidData1 = ReadUnaligned32 (&(TmpGuid->Data1));\r
+ GuidData2 = ReadUnaligned16 (&(TmpGuid->Data2));\r
+ GuidData3 = ReadUnaligned16 (&(TmpGuid->Data3));\r
+ BasePrintLibSPrint (\r
+ ValueBuffer,\r
+ MAXIMUM_VALUE_CHARACTERS,\r
+ 0,\r
+ "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x",\r
+ GuidData1,\r
+ GuidData2,\r
+ GuidData3,\r
+ TmpGuid->Data4[0],\r
+ TmpGuid->Data4[1],\r
+ TmpGuid->Data4[2],\r
+ TmpGuid->Data4[3],\r
+ TmpGuid->Data4[4],\r
+ TmpGuid->Data4[5],\r
+ TmpGuid->Data4[6],\r
+ TmpGuid->Data4[7]\r
+ );\r
+ ArgumentString = ValueBuffer;\r
+ }\r
+\r
+ break;\r
+\r
+ case 't':\r
+ if (BaseListMarker == NULL) {\r
+ TmpTime = VA_ARG (VaListMarker, TIME *);\r
+ } else {\r
+ TmpTime = BASE_ARG (BaseListMarker, TIME *);\r
+ }\r
+\r
+ if (TmpTime == NULL) {\r
+ ArgumentString = "<null time>";\r
+ } else {\r
+ BasePrintLibSPrint (\r
+ ValueBuffer,\r
+ MAXIMUM_VALUE_CHARACTERS,\r
+ 0,\r
+ "%02d/%02d/%04d %02d:%02d",\r
+ TmpTime->Month,\r
+ TmpTime->Day,\r
+ TmpTime->Year,\r
+ TmpTime->Hour,\r
+ TmpTime->Minute\r
+ );\r
+ ArgumentString = ValueBuffer;\r
+ }\r
+\r
+ break;\r
+\r
+ case 'r':\r
+ if (BaseListMarker == NULL) {\r
+ Status = VA_ARG (VaListMarker, RETURN_STATUS);\r
+ } else {\r
+ Status = BASE_ARG (BaseListMarker, RETURN_STATUS);\r
+ }\r
+\r
+ ArgumentString = ValueBuffer;\r
+ if (RETURN_ERROR (Status)) {\r
+ //\r
+ // Clear error bit\r
+ //\r
+ Index = Status & ~MAX_BIT;\r
+ if ((Index > 0) && (Index <= ERROR_STATUS_NUMBER)) {\r
+ ArgumentString = mErrorString[Index - 1];\r
+ }\r
+ } else {\r
+ Index = Status;\r
+ if (Index <= WARNING_STATUS_NUMBER) {\r
+ ArgumentString = mWarningString[Index];\r
}\r
}\r
- }\r
- }\r
- break;\r
\r
- case 's':\r
- case 'S':\r
- Flags |= ARGUMENT_UNICODE;\r
- //\r
- // break skipped on purpose\r
- //\r
- case 'a':\r
- if (BaseListMarker == NULL) {\r
- ArgumentString = VA_ARG (VaListMarker, CHAR8 *);\r
- } else {\r
- ArgumentString = BASE_ARG (BaseListMarker, CHAR8 *);\r
- }\r
- if (ArgumentString == NULL) {\r
- Flags &= ~((UINTN) ARGUMENT_UNICODE);\r
- ArgumentString = "<null string>";\r
- }\r
- //\r
- // Set the default precision for string to be zero if not specified.\r
- //\r
- if ((Flags & PRECISION) == 0) {\r
- Precision = 0;\r
- }\r
- break;\r
+ if (ArgumentString == ValueBuffer) {\r
+ BasePrintLibSPrint ((CHAR8 *)ValueBuffer, MAXIMUM_VALUE_CHARACTERS, 0, "%08X", Status);\r
+ }\r
\r
- case 'c':\r
- if (BaseListMarker == NULL) {\r
- Character = VA_ARG (VaListMarker, UINTN) & 0xffff;\r
- } else {\r
- Character = BASE_ARG (BaseListMarker, UINTN) & 0xffff;\r
- }\r
- ArgumentString = (CHAR8 *)&Character;\r
- Flags |= ARGUMENT_UNICODE;\r
- break;\r
+ break;\r
\r
- case 'g':\r
- if (BaseListMarker == NULL) {\r
- TmpGuid = VA_ARG (VaListMarker, GUID *);\r
- } else {\r
- TmpGuid = BASE_ARG (BaseListMarker, GUID *);\r
- }\r
- if (TmpGuid == NULL) {\r
- ArgumentString = "<null guid>";\r
- } else {\r
- GuidData1 = ReadUnaligned32 (&(TmpGuid->Data1));\r
- GuidData2 = ReadUnaligned16 (&(TmpGuid->Data2));\r
- GuidData3 = ReadUnaligned16 (&(TmpGuid->Data3));\r
- BasePrintLibSPrint (\r
- ValueBuffer,\r
- MAXIMUM_VALUE_CHARACTERS,\r
- 0,\r
- "%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x",\r
- GuidData1,\r
- GuidData2,\r
- GuidData3,\r
- TmpGuid->Data4[0],\r
- TmpGuid->Data4[1],\r
- TmpGuid->Data4[2],\r
- TmpGuid->Data4[3],\r
- TmpGuid->Data4[4],\r
- TmpGuid->Data4[5],\r
- TmpGuid->Data4[6],\r
- TmpGuid->Data4[7]\r
- );\r
- ArgumentString = ValueBuffer;\r
- }\r
- break;\r
+ case '\r':\r
+ Format += BytesPerFormatCharacter;\r
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
+ if (FormatCharacter == '\n') {\r
+ //\r
+ // Translate '\r\n' to '\r\n'\r
+ //\r
+ ArgumentString = "\r\n";\r
+ } else {\r
+ //\r
+ // Translate '\r' to '\r'\r
+ //\r
+ ArgumentString = "\r";\r
+ Format -= BytesPerFormatCharacter;\r
+ }\r
\r
- case 't':\r
- if (BaseListMarker == NULL) {\r
- TmpTime = VA_ARG (VaListMarker, TIME *);\r
- } else {\r
- TmpTime = BASE_ARG (BaseListMarker, TIME *);\r
- }\r
- if (TmpTime == NULL) {\r
- ArgumentString = "<null time>";\r
- } else {\r
- BasePrintLibSPrint (\r
- ValueBuffer,\r
- MAXIMUM_VALUE_CHARACTERS,\r
- 0,\r
- "%02d/%02d/%04d %02d:%02d",\r
- TmpTime->Month,\r
- TmpTime->Day,\r
- TmpTime->Year,\r
- TmpTime->Hour,\r
- TmpTime->Minute\r
- );\r
- ArgumentString = ValueBuffer;\r
- }\r
- break;\r
+ break;\r
\r
- case 'r':\r
- if (BaseListMarker == NULL) {\r
- Status = VA_ARG (VaListMarker, RETURN_STATUS);\r
- } else {\r
- Status = BASE_ARG (BaseListMarker, RETURN_STATUS);\r
- }\r
- ArgumentString = ValueBuffer;\r
- if (RETURN_ERROR (Status)) {\r
- //\r
- // Clear error bit\r
- //\r
- Index = Status & ~MAX_BIT;\r
- if (Index > 0 && Index <= ERROR_STATUS_NUMBER) {\r
- ArgumentString = mErrorString [Index - 1];\r
- }\r
- } else {\r
- Index = Status;\r
- if (Index <= WARNING_STATUS_NUMBER) {\r
- ArgumentString = mWarningString [Index];\r
- }\r
- }\r
- if (ArgumentString == ValueBuffer) {\r
- BasePrintLibSPrint ((CHAR8 *) ValueBuffer, MAXIMUM_VALUE_CHARACTERS, 0, "%08X", Status);\r
+ case '\n':\r
+ //\r
+ // Translate '\n' to '\r\n' and '\n\r' to '\r\n'\r
+ //\r
+ ArgumentString = "\r\n";\r
+ Format += BytesPerFormatCharacter;\r
+ FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
+ if (FormatCharacter != '\r') {\r
+ Format -= BytesPerFormatCharacter;\r
+ }\r
+\r
+ break;\r
+\r
+ case '%':\r
+ default:\r
+ //\r
+ // if the type is '%' or unknown, then print it to the screen\r
+ //\r
+ ArgumentString = (CHAR8 *)&FormatCharacter;\r
+ Flags |= ARGUMENT_UNICODE;\r
+ break;\r
}\r
+\r
break;\r
\r
case '\r':\r
- Format += BytesPerFormatCharacter;\r
+ Format += BytesPerFormatCharacter;\r
FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
if (FormatCharacter == '\n') {\r
//\r
// Translate '\r' to '\r'\r
//\r
ArgumentString = "\r";\r
- Format -= BytesPerFormatCharacter;\r
+ Format -= BytesPerFormatCharacter;\r
}\r
+\r
break;\r
\r
case '\n':\r
//\r
// Translate '\n' to '\r\n' and '\n\r' to '\r\n'\r
//\r
- ArgumentString = "\r\n";\r
- Format += BytesPerFormatCharacter;\r
+ ArgumentString = "\r\n";\r
+ Format += BytesPerFormatCharacter;\r
FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
if (FormatCharacter != '\r') {\r
- Format -= BytesPerFormatCharacter;\r
+ Format -= BytesPerFormatCharacter;\r
}\r
+\r
break;\r
\r
- case '%':\r
default:\r
- //\r
- // if the type is '%' or unknown, then print it to the screen\r
- //\r
ArgumentString = (CHAR8 *)&FormatCharacter;\r
- Flags |= ARGUMENT_UNICODE;\r
+ Flags |= ARGUMENT_UNICODE;\r
break;\r
- }\r
- break;\r
-\r
- case '\r':\r
- Format += BytesPerFormatCharacter;\r
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
- if (FormatCharacter == '\n') {\r
- //\r
- // Translate '\r\n' to '\r\n'\r
- //\r
- ArgumentString = "\r\n";\r
- } else {\r
- //\r
- // Translate '\r' to '\r'\r
- //\r
- ArgumentString = "\r";\r
- Format -= BytesPerFormatCharacter;\r
- }\r
- break;\r
-\r
- case '\n':\r
- //\r
- // Translate '\n' to '\r\n' and '\n\r' to '\r\n'\r
- //\r
- ArgumentString = "\r\n";\r
- Format += BytesPerFormatCharacter;\r
- FormatCharacter = ((*Format & 0xff) | ((BytesPerFormatCharacter == 1) ? 0 : (*(Format + 1) << 8))) & FormatMask;\r
- if (FormatCharacter != '\r') {\r
- Format -= BytesPerFormatCharacter;\r
- }\r
- break;\r
-\r
- default:\r
- ArgumentString = (CHAR8 *)&FormatCharacter;\r
- Flags |= ARGUMENT_UNICODE;\r
- break;\r
}\r
\r
//\r
// Retrieve the ArgumentString attriubutes\r
//\r
if ((Flags & ARGUMENT_UNICODE) != 0) {\r
- ArgumentMask = 0xffff;\r
+ ArgumentMask = 0xffff;\r
BytesPerArgumentCharacter = 2;\r
} else {\r
- ArgumentMask = 0xff;\r
+ ArgumentMask = 0xff;\r
BytesPerArgumentCharacter = 1;\r
}\r
+\r
if ((Flags & ARGUMENT_REVERSED) != 0) {\r
BytesPerArgumentCharacter = -BytesPerArgumentCharacter;\r
} else {\r
// ArgumentString is either null-terminated, or it contains Precision characters\r
//\r
for (Count = 0;\r
- (ArgumentString[Count * BytesPerArgumentCharacter] != '\0' ||\r
- (BytesPerArgumentCharacter > 1 &&\r
- ArgumentString[Count * BytesPerArgumentCharacter + 1]!= '\0')) &&\r
- (Count < Precision || ((Flags & PRECISION) == 0));\r
- Count++) {\r
+ (ArgumentString[Count * BytesPerArgumentCharacter] != '\0' ||\r
+ (BytesPerArgumentCharacter > 1 &&\r
+ ArgumentString[Count * BytesPerArgumentCharacter + 1] != '\0')) &&\r
+ (Count < Precision || ((Flags & PRECISION) == 0));\r
+ Count++)\r
+ {\r
ArgumentCharacter = ((ArgumentString[Count * BytesPerArgumentCharacter] & 0xff) | ((ArgumentString[Count * BytesPerArgumentCharacter + 1]) << 8)) & ArgumentMask;\r
if (ArgumentCharacter == 0) {\r
break;\r
//\r
if ((Flags & (PAD_TO_WIDTH | LEFT_JUSTIFY)) == (PAD_TO_WIDTH)) {\r
LengthToReturn += ((Width - Precision) * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Width - Precision, ' ', BytesPerOutputCharacter);\r
}\r
}\r
if (ZeroPad) {\r
if (Prefix != 0) {\r
LengthToReturn += (1 * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, Prefix, BytesPerOutputCharacter);\r
}\r
}\r
+\r
LengthToReturn += ((Precision - Count) * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Precision - Count, '0', BytesPerOutputCharacter);\r
}\r
} else {\r
LengthToReturn += ((Precision - Count) * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Precision - Count, ' ', BytesPerOutputCharacter);\r
}\r
+\r
if (Prefix != 0) {\r
LengthToReturn += (1 * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, Prefix, BytesPerOutputCharacter);\r
}\r
}\r
//\r
while (Index < Count &&\r
(ArgumentString[0] != '\0' ||\r
- (BytesPerArgumentCharacter > 1 && ArgumentString[1] != '\0'))) {\r
+ (BytesPerArgumentCharacter > 1 && ArgumentString[1] != '\0')))\r
+ {\r
ArgumentCharacter = ((*ArgumentString & 0xff) | (((UINT8)*(ArgumentString + 1)) << 8)) & ArgumentMask;\r
\r
LengthToReturn += (1 * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, ArgumentCharacter, BytesPerOutputCharacter);\r
}\r
- ArgumentString += BytesPerArgumentCharacter;\r
+\r
+ ArgumentString += BytesPerArgumentCharacter;\r
Index++;\r
if (Comma) {\r
Digits++;\r
Index++;\r
if (Index < Count) {\r
LengthToReturn += (1 * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, 1, ',', BytesPerOutputCharacter);\r
}\r
}\r
//\r
if ((Flags & (PAD_TO_WIDTH | LEFT_JUSTIFY)) == (PAD_TO_WIDTH | LEFT_JUSTIFY)) {\r
LengthToReturn += ((Width - Precision) * BytesPerOutputCharacter);\r
- if ((Flags & COUNT_ONLY_NO_PRINT) == 0 && Buffer != NULL) {\r
+ if (((Flags & COUNT_ONLY_NO_PRINT) == 0) && (Buffer != NULL)) {\r
Buffer = BasePrintLibFillBuffer (Buffer, EndBuffer, Width - Precision, ' ', BytesPerOutputCharacter);\r
}\r
}\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
\r
-\r
//\r
// Print primitives\r
//\r
-#define PREFIX_SIGN BIT1\r
-#define PREFIX_BLANK BIT2\r
-#define LONG_TYPE BIT4\r
-#define OUTPUT_UNICODE BIT6\r
-#define FORMAT_UNICODE BIT8\r
-#define PAD_TO_WIDTH BIT9\r
-#define ARGUMENT_UNICODE BIT10\r
-#define PRECISION BIT11\r
-#define ARGUMENT_REVERSED BIT12\r
-#define COUNT_ONLY_NO_PRINT BIT13\r
-#define UNSIGNED_TYPE BIT14\r
+#define PREFIX_SIGN BIT1\r
+#define PREFIX_BLANK BIT2\r
+#define LONG_TYPE BIT4\r
+#define OUTPUT_UNICODE BIT6\r
+#define FORMAT_UNICODE BIT8\r
+#define PAD_TO_WIDTH BIT9\r
+#define ARGUMENT_UNICODE BIT10\r
+#define PRECISION BIT11\r
+#define ARGUMENT_REVERSED BIT12\r
+#define COUNT_ONLY_NO_PRINT BIT13\r
+#define UNSIGNED_TYPE BIT14\r
\r
//\r
// Record date and time information\r
//\r
typedef struct {\r
- UINT16 Year;\r
- UINT8 Month;\r
- UINT8 Day;\r
- UINT8 Hour;\r
- UINT8 Minute;\r
- UINT8 Second;\r
- UINT8 Pad1;\r
- UINT32 Nanosecond;\r
- INT16 TimeZone;\r
- UINT8 Daylight;\r
- UINT8 Pad2;\r
+ UINT16 Year;\r
+ UINT8 Month;\r
+ UINT8 Day;\r
+ UINT8 Hour;\r
+ UINT8 Minute;\r
+ UINT8 Second;\r
+ UINT8 Pad1;\r
+ UINT32 Nanosecond;\r
+ INT16 TimeZone;\r
+ UINT8 Daylight;\r
+ UINT8 Pad2;\r
} TIME;\r
\r
/**\r
**/\r
CHAR8 *\r
BasePrintLibFillBuffer (\r
- OUT CHAR8 *Buffer,\r
- IN CHAR8 *EndBuffer,\r
- IN INTN Length,\r
- IN UINTN Character,\r
- IN INTN Increment\r
+ OUT CHAR8 *Buffer,\r
+ IN CHAR8 *EndBuffer,\r
+ IN INTN Length,\r
+ IN UINTN Character,\r
+ IN INTN Increment\r
);\r
\r
/**\r
**/\r
UINTN\r
BasePrintLibConvertValueToString (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width,\r
- IN UINTN Increment\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width,\r
+ IN UINTN Increment\r
);\r
\r
/**\r
**/\r
RETURN_STATUS\r
BasePrintLibConvertValueToStringS (\r
- IN OUT CHAR8 *Buffer,\r
- IN UINTN BufferSize,\r
- IN UINTN Flags,\r
- IN INT64 Value,\r
- IN UINTN Width,\r
- IN UINTN Increment\r
+ IN OUT CHAR8 *Buffer,\r
+ IN UINTN BufferSize,\r
+ IN UINTN Flags,\r
+ IN INT64 Value,\r
+ IN UINTN Width,\r
+ IN UINTN Increment\r
);\r
\r
#endif\r
return FALSE;\r
}\r
\r
-\r
/**\r
Extracts ASSERT() information from a status code structure.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Extracts DEBUG() information from a status code structure.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Reports a status code.\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Reports a status code with a Device Path Protocol as the extended data.\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Reports a status code with an extended data buffer.\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Reports a status code with full parameters.\r
\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_PROGRESS_CODE are enabled\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_ERROR_CODE are enabled\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Returns TRUE if status codes of type EFI_DEBUG_CODE are enabled\r
\r
{\r
return FALSE;\r
}\r
-\r
BOOLEAN\r
EFIAPI\r
ArmRndr (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
/**\r
#include "ArmRng.h"\r
#include "BaseRngLibInternals.h"\r
\r
-STATIC BOOLEAN mRndrSupported;\r
+STATIC BOOLEAN mRndrSupported;\r
\r
//\r
// Bit mask used to determine if RNDR instruction is supported.\r
//\r
-#define RNDR_MASK ((UINT64)MAX_UINT16 << 60U)\r
+#define RNDR_MASK ((UINT64)MAX_UINT16 << 60U)\r
\r
/**\r
The constructor function checks whether or not RNDR instruction is supported\r
VOID\r
)\r
{\r
- UINT64 Isar0;\r
+ UINT64 Isar0;\r
+\r
//\r
// Determine RNDR support by examining bits 63:60 of the ISAR0 register returned by\r
// MSR. A non-zero value indicates that the processor supports the RNDR instruction.\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
- UINT64 Rand64;\r
+ UINT64 Rand64;\r
\r
if (ArchGetRandomNumber64 (&Rand64)) {\r
*Rand = Rand64 & MAX_UINT16;\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
- UINT64 Rand64;\r
+ UINT64 Rand64;\r
\r
if (ArchGetRandomNumber64 (&Rand64)) {\r
*Rand = Rand64 & MAX_UINT32;\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
return ArmRndr (Rand);\r
// Uses the recommended value defined in Section 7.3.17 of "Intel 64 and IA-32\r
// Architectures Software Developer's Manual".\r
//\r
-#define GETRANDOM_RETRY_LIMIT 10\r
-\r
+#define GETRANDOM_RETRY_LIMIT 10\r
\r
/**\r
Generates a 16-bit random number.\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
UINT32 Index;\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
UINT32 Index;\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
UINT32 Index;\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber128 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
ASSERT (Rand != NULL);\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
);\r
\r
/**\r
#if defined (MDE_CPU_AARCH64)\r
\r
// RNDR, Random Number\r
-#define RNDR S3_3_C2_C4_0\r
+#define RNDR S3_3_C2_C4_0\r
\r
#endif\r
\r
-#endif // BASE_RNGLIB_INTERNALS_H_\r
+#endif // BASE_RNGLIB_INTERNALS_H_\r
//\r
// Bit mask used to determine if RdRand instruction is supported.\r
//\r
-#define RDRAND_MASK BIT30\r
+#define RDRAND_MASK BIT30\r
\r
-\r
-STATIC BOOLEAN mRdRandSupported;\r
+STATIC BOOLEAN mRdRandSupported;\r
\r
/**\r
The constructor function checks whether or not RDRAND instruction is supported\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
return AsmRdRand16 (Rand);\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
return AsmRdRand32 (Rand);\r
BOOLEAN\r
EFIAPI\r
ArchGetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
return AsmRdRand64 (Rand);\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
ASSERT (FALSE);\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber128 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
ASSERT (FALSE);\r
#include <Library/DebugLib.h>\r
#include <Library/TimerLib.h>\r
\r
-#define DEFAULT_DELAY_TIME_IN_MICROSECONDS 10\r
+#define DEFAULT_DELAY_TIME_IN_MICROSECONDS 10\r
\r
/**\r
Using the TimerLib GetPerformanceCounterProperties() we delay\r
VOID\r
)\r
{\r
- UINT64 CounterHz;\r
+ UINT64 CounterHz;\r
\r
// Get the counter properties\r
CounterHz = GetPerformanceCounterProperties (NULL, NULL);\r
// Make sure we won't divide by zero\r
if (CounterHz == 0) {\r
- ASSERT(CounterHz != 0); // Assert so the developer knows something is wrong\r
+ ASSERT (CounterHz != 0); // Assert so the developer knows something is wrong\r
return DEFAULT_DELAY_TIME_IN_MICROSECONDS;\r
}\r
+\r
// Calculate the minimum delay based on 1.5 microseconds divided by the hertz.\r
// We calculate the length of a cycle (1/CounterHz) and multiply it by 1.5 microseconds\r
// This ensures that the performance counter has increased by at least one\r
- return (UINT32)(MAX (DivU64x64Remainder (1500000,CounterHz, NULL), 1));\r
+ return (UINT32)(MAX (DivU64x64Remainder (1500000, CounterHz, NULL), 1));\r
}\r
\r
-\r
/**\r
Generates a 16-bit random number.\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber16 (\r
- OUT UINT16 *Rand\r
+ OUT UINT16 *Rand\r
)\r
{\r
UINT32 Index;\r
- UINT8 *RandPtr;\r
+ UINT8 *RandPtr;\r
UINT32 DelayInMicroSeconds;\r
\r
ASSERT (Rand != NULL);\r
if (Rand == NULL) {\r
return FALSE;\r
}\r
+\r
DelayInMicroSeconds = CalculateMinimumDecentDelayInMicroseconds ();\r
- RandPtr = (UINT8*)Rand;\r
+ RandPtr = (UINT8 *)Rand;\r
// Get 2 bytes of random ish data\r
- for (Index = 0; Index < sizeof(UINT16); Index ++) {\r
+ for (Index = 0; Index < sizeof (UINT16); Index++) {\r
*RandPtr = (UINT8)(GetPerformanceCounter () & 0xFF);\r
// Delay to give the performance counter a chance to change\r
MicroSecondDelay (DelayInMicroSeconds);\r
RandPtr++;\r
}\r
+\r
return TRUE;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
UINT32 Index;\r
- UINT8 *RandPtr;\r
+ UINT8 *RandPtr;\r
UINT32 DelayInMicroSeconds;\r
\r
ASSERT (Rand != NULL);\r
return FALSE;\r
}\r
\r
- RandPtr = (UINT8 *) Rand;\r
+ RandPtr = (UINT8 *)Rand;\r
DelayInMicroSeconds = CalculateMinimumDecentDelayInMicroseconds ();\r
// Get 4 bytes of random ish data\r
- for (Index = 0; Index < sizeof(UINT32); Index ++) {\r
+ for (Index = 0; Index < sizeof (UINT32); Index++) {\r
*RandPtr = (UINT8)(GetPerformanceCounter () & 0xFF);\r
// Delay to give the performance counter a chance to change\r
MicroSecondDelay (DelayInMicroSeconds);\r
RandPtr++;\r
}\r
+\r
return TRUE;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
UINT32 Index;\r
- UINT8 *RandPtr;\r
+ UINT8 *RandPtr;\r
UINT32 DelayInMicroSeconds;\r
\r
ASSERT (Rand != NULL);\r
return FALSE;\r
}\r
\r
- RandPtr = (UINT8 *)Rand;\r
+ RandPtr = (UINT8 *)Rand;\r
DelayInMicroSeconds = CalculateMinimumDecentDelayInMicroseconds ();\r
// Get 8 bytes of random ish data\r
- for (Index = 0; Index < sizeof(UINT64); Index ++) {\r
+ for (Index = 0; Index < sizeof (UINT64); Index++) {\r
*RandPtr = (UINT8)(GetPerformanceCounter () & 0xFF);\r
// Delay to give the performance counter a chance to change\r
MicroSecondDelay (DelayInMicroSeconds);\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber128 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
ASSERT (Rand != NULL);\r
\r
**/\r
\r
-\r
#include <Base.h>\r
#include <Library/S3BootScriptLib.h>\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveIoWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveIoReadWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveMemWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for a memory modify operation into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveMemReadWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for a PCI configuration space write operation into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciCfgWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciCfgReadWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for a PCI configuration space modify operation into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciCfg2Write (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT16 Segment,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT16 Segment,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for a PCI configuration space modify operation into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciCfg2ReadWrite (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT16 Segment,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT16 Segment,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for an SMBus command execution into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveSmbusExecute (\r
- IN UINTN SmBusAddress,\r
- IN EFI_SMBUS_OPERATION Operation,\r
- IN UINTN *Length,\r
- IN VOID *Buffer\r
+ IN UINTN SmBusAddress,\r
+ IN EFI_SMBUS_OPERATION Operation,\r
+ IN UINTN *Length,\r
+ IN VOID *Buffer\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for an execution stall on the processor into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveStall (\r
- IN UINTN Duration\r
+ IN UINTN Duration\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for dispatching specified arbitrary code into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveDispatch (\r
- IN VOID *EntryPoint\r
+ IN VOID *EntryPoint\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for dispatching specified arbitrary code into a specified boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveDispatch2 (\r
- IN VOID *EntryPoint,\r
- IN VOID *Context\r
+ IN VOID *EntryPoint,\r
+ IN VOID *Context\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveMemPoll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *BitMask,\r
- IN VOID *BitValue,\r
- IN UINTN Duration,\r
- IN UINT64 LoopTimes\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *BitMask,\r
+ IN VOID *BitValue,\r
+ IN UINTN Duration,\r
+ IN UINT64 LoopTimes\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveInformation (\r
- IN UINT32 InformationLength,\r
- IN VOID *Information\r
+ IN UINT32 InformationLength,\r
+ IN VOID *Information\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for I/O reads the I/O location and continues when the exit criteria is satisfied or after a\r
defined duration.\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveIoPoll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
IN VOID *Data,\r
IN VOID *DataMask,\r
- IN UINT64 Delay\r
+ IN UINT64 Delay\r
)\r
{\r
return RETURN_SUCCESS;\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePciPoll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask,\r
- IN UINT64 Delay\r
- )\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask,\r
+ IN UINT64 Delay\r
+ )\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Adds a record for PCI configuration space reads and continues when the exit criteria is satisfied or\r
after a defined duration.\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSavePci2Poll (\r
- IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT16 Segment,\r
- IN UINT64 Address,\r
- IN VOID *Data,\r
- IN VOID *DataMask,\r
- IN UINT64 Delay\r
+ IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
+ IN UINT16 Segment,\r
+ IN UINT64 Address,\r
+ IN VOID *Data,\r
+ IN VOID *DataMask,\r
+ IN UINT64 Delay\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Save ASCII string information specified by Buffer to\r
boot script with opcode EFI_BOOT_SCRIPT_INFORMATION_OPCODE\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptSaveInformationAsciiString (\r
- IN CONST CHAR8 *String\r
+ IN CONST CHAR8 *String\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
This is an function to close the S3 boot script table. The function could only be called in\r
BOOT time phase. To comply with the Framework spec definition on\r
@return the base address of the new copy of the boot script table.\r
\r
**/\r
-UINT8*\r
+UINT8 *\r
EFIAPI\r
S3BootScriptCloseTable (\r
VOID\r
{\r
return 0;\r
}\r
+\r
/**\r
Executes the S3 boot script table.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptExecute (\r
- VOID\r
+ VOID\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Move the last boot script entry to the position\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptMoveLastOpcode (\r
- IN BOOLEAN BeforeOrAfter,\r
- IN OUT VOID **Position OPTIONAL\r
-)\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN OUT VOID **Position OPTIONAL\r
+ )\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Find a label within the boot script table and, if not present, optionally create it.\r
\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptLabel (\r
- IN BOOLEAN BeforeOrAfter,\r
- IN BOOLEAN CreateIfNotFound,\r
- IN OUT VOID **Position OPTIONAL,\r
- IN CONST CHAR8 *Label\r
+ IN BOOLEAN BeforeOrAfter,\r
+ IN BOOLEAN CreateIfNotFound,\r
+ IN OUT VOID **Position OPTIONAL,\r
+ IN CONST CHAR8 *Label\r
)\r
{\r
return RETURN_SUCCESS;\r
}\r
+\r
/**\r
Compare two positions in the boot script table and return their relative position.\r
@param Position1 The positions in the boot script table to compare\r
RETURN_STATUS\r
EFIAPI\r
S3BootScriptCompare (\r
- IN UINT8 *Position1,\r
- IN UINT8 *Position2,\r
- OUT UINTN *RelativePosition\r
+ IN UINT8 *Position1,\r
+ IN UINT8 *Position2,\r
+ OUT UINTN *RelativePosition\r
)\r
{\r
return RETURN_SUCCESS;\r
#include <Library/IoLib.h>\r
#include <Library/S3BootScriptLib.h>\r
\r
-\r
/**\r
Saves an I/O port value to the boot script.\r
\r
VOID\r
InternalSaveIoWriteValueToBootScript (\r
IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINTN Port,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSaveIoWrite (\r
Width,\r
**/\r
UINT8\r
InternalSaveIoWrite8ValueToBootScript (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
InternalSaveIoWriteValueToBootScript (S3BootScriptWidthUint8, Port, &Value);\r
UINT8\r
EFIAPI\r
S3IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoRead8 (Port));\r
UINT8\r
EFIAPI\r
S3IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoWrite8 (Port, Value));\r
UINT8\r
EFIAPI\r
S3IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoOr8 (Port, OrData));\r
UINT8\r
EFIAPI\r
S3IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoAnd8 (Port, AndData));\r
UINT8\r
EFIAPI\r
S3IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoAndThenOr8 (Port, AndData, OrData));\r
UINT8\r
EFIAPI\r
S3IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoBitFieldRead8 (Port, StartBit, EndBit));\r
UINT8\r
EFIAPI\r
S3IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoBitFieldWrite8 (Port, StartBit, EndBit, Value));\r
UINT8\r
EFIAPI\r
S3IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoBitFieldOr8 (Port, StartBit, EndBit, OrData));\r
UINT8\r
EFIAPI\r
S3IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoBitFieldAnd8 (Port, StartBit, EndBit, AndData));\r
UINT8\r
EFIAPI\r
S3IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveIoWrite8ValueToBootScript (Port, IoBitFieldAndThenOr8 (Port, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT16\r
InternalSaveIoWrite16ValueToBootScript (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
InternalSaveIoWriteValueToBootScript (S3BootScriptWidthUint16, Port, &Value);\r
UINT16\r
EFIAPI\r
S3IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoRead16 (Port));\r
UINT16\r
EFIAPI\r
S3IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoWrite16 (Port, Value));\r
UINT16\r
EFIAPI\r
S3IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoOr16 (Port, OrData));\r
UINT16\r
EFIAPI\r
S3IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoAnd16 (Port, AndData));\r
UINT16\r
EFIAPI\r
S3IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoAndThenOr16 (Port, AndData, OrData));\r
UINT16\r
EFIAPI\r
S3IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoBitFieldRead16 (Port, StartBit, EndBit));\r
UINT16\r
EFIAPI\r
S3IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoBitFieldWrite16 (Port, StartBit, EndBit, Value));\r
UINT16\r
EFIAPI\r
S3IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoBitFieldOr16 (Port, StartBit, EndBit, OrData));\r
UINT16\r
EFIAPI\r
S3IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoBitFieldAnd16 (Port, StartBit, EndBit, AndData));\r
UINT16\r
EFIAPI\r
S3IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveIoWrite16ValueToBootScript (Port, IoBitFieldAndThenOr16 (Port, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT32\r
InternalSaveIoWrite32ValueToBootScript (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
InternalSaveIoWriteValueToBootScript (S3BootScriptWidthUint32, Port, &Value);\r
UINT32\r
EFIAPI\r
S3IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoRead32 (Port));\r
UINT32\r
EFIAPI\r
S3IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoWrite32 (Port, Value));\r
UINT32\r
EFIAPI\r
S3IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoOr32 (Port, OrData));\r
UINT32\r
EFIAPI\r
S3IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoAnd32 (Port, AndData));\r
UINT32\r
EFIAPI\r
S3IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoAndThenOr32 (Port, AndData, OrData));\r
UINT32\r
EFIAPI\r
S3IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoBitFieldRead32 (Port, StartBit, EndBit));\r
UINT32\r
EFIAPI\r
S3IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoBitFieldWrite32 (Port, StartBit, EndBit, Value));\r
UINT32\r
EFIAPI\r
S3IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoBitFieldOr32 (Port, StartBit, EndBit, OrData));\r
UINT32\r
EFIAPI\r
S3IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoBitFieldAnd32 (Port, StartBit, EndBit, AndData));\r
UINT32\r
EFIAPI\r
S3IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveIoWrite32ValueToBootScript (Port, IoBitFieldAndThenOr32 (Port, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT64\r
InternalSaveIoWrite64ValueToBootScript (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
InternalSaveIoWriteValueToBootScript (S3BootScriptWidthUint64, Port, &Value);\r
UINT64\r
EFIAPI\r
S3IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoRead64 (Port));\r
UINT64\r
EFIAPI\r
S3IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoWrite64 (Port, Value));\r
UINT64\r
EFIAPI\r
S3IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoOr64 (Port, OrData));\r
UINT64\r
EFIAPI\r
S3IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoAnd64 (Port, AndData));\r
UINT64\r
EFIAPI\r
S3IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoAndThenOr64 (Port, AndData, OrData));\r
UINT64\r
EFIAPI\r
S3IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoBitFieldRead64 (Port, StartBit, EndBit));\r
UINT64\r
EFIAPI\r
S3IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoBitFieldWrite64 (Port, StartBit, EndBit, Value));\r
UINT64\r
EFIAPI\r
S3IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoBitFieldOr64 (Port, StartBit, EndBit, OrData));\r
UINT64\r
EFIAPI\r
S3IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoBitFieldAnd64 (Port, StartBit, EndBit, AndData));\r
UINT64\r
EFIAPI\r
S3IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveIoWrite64ValueToBootScript (Port, IoBitFieldAndThenOr64 (Port, StartBit, EndBit, AndData, OrData));\r
VOID\r
InternalSaveMmioWriteValueToBootScript (\r
IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINTN Address,\r
- IN VOID *Buffer\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSaveMemWrite (\r
Width,\r
**/\r
UINT8\r
InternalSaveMmioWrite8ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
InternalSaveMmioWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r
UINT8\r
EFIAPI\r
S3MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioRead8 (Address));\r
UINT8\r
EFIAPI\r
S3MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioWrite8 (Address, Value));\r
UINT8\r
EFIAPI\r
S3MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioOr8 (Address, OrData));\r
UINT8\r
EFIAPI\r
S3MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioAnd8 (Address, AndData));\r
UINT8\r
EFIAPI\r
S3MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioAndThenOr8 (Address, AndData, OrData));\r
UINT8\r
EFIAPI\r
S3MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioBitFieldRead8 (Address, StartBit, EndBit));\r
UINT8\r
EFIAPI\r
S3MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioBitFieldWrite8 (Address, StartBit, EndBit, Value));\r
UINT8\r
EFIAPI\r
S3MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioBitFieldOr8 (Address, StartBit, EndBit, OrData));\r
UINT8\r
EFIAPI\r
S3MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r
UINT8\r
EFIAPI\r
S3MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSaveMmioWrite8ValueToBootScript (Address, MmioBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT16\r
InternalSaveMmioWrite16ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
InternalSaveMmioWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r
UINT16\r
EFIAPI\r
S3MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioRead16 (Address));\r
UINT16\r
EFIAPI\r
S3MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioWrite16 (Address, Value));\r
UINT16\r
EFIAPI\r
S3MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioOr16 (Address, OrData));\r
UINT16\r
EFIAPI\r
S3MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioAnd16 (Address, AndData));\r
UINT16\r
EFIAPI\r
S3MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioAndThenOr16 (Address, AndData, OrData));\r
UINT16\r
EFIAPI\r
S3MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioBitFieldRead16 (Address, StartBit, EndBit));\r
UINT16\r
EFIAPI\r
S3MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioBitFieldWrite16 (Address, StartBit, EndBit, Value));\r
UINT16\r
EFIAPI\r
S3MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioBitFieldOr16 (Address, StartBit, EndBit, OrData));\r
UINT16\r
EFIAPI\r
S3MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r
UINT16\r
EFIAPI\r
S3MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSaveMmioWrite16ValueToBootScript (Address, MmioBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT32\r
InternalSaveMmioWrite32ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
InternalSaveMmioWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r
UINT32\r
EFIAPI\r
S3MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioRead32 (Address));\r
UINT32\r
EFIAPI\r
S3MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioWrite32 (Address, Value));\r
UINT32\r
EFIAPI\r
S3MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioOr32 (Address, OrData));\r
UINT32\r
EFIAPI\r
S3MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioAnd32 (Address, AndData));\r
UINT32\r
EFIAPI\r
S3MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioAndThenOr32 (Address, AndData, OrData));\r
UINT32\r
EFIAPI\r
S3MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioBitFieldRead32 (Address, StartBit, EndBit));\r
UINT32\r
EFIAPI\r
S3MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioBitFieldWrite32 (Address, StartBit, EndBit, Value));\r
UINT32\r
EFIAPI\r
S3MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioBitFieldOr32 (Address, StartBit, EndBit, OrData));\r
UINT32\r
EFIAPI\r
S3MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r
UINT32\r
EFIAPI\r
S3MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSaveMmioWrite32ValueToBootScript (Address, MmioBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT64\r
InternalSaveMmioWrite64ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
InternalSaveMmioWriteValueToBootScript (S3BootScriptWidthUint64, Address, &Value);\r
UINT64\r
EFIAPI\r
S3MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioRead64 (Address));\r
UINT64\r
EFIAPI\r
S3MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioWrite64 (Address, Value));\r
UINT64\r
EFIAPI\r
S3MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioOr64 (Address, OrData));\r
UINT64\r
EFIAPI\r
S3MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioAnd64 (Address, AndData));\r
UINT64\r
EFIAPI\r
S3MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioAndThenOr64 (Address, AndData, OrData));\r
UINT64\r
EFIAPI\r
S3MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioBitFieldRead64 (Address, StartBit, EndBit));\r
UINT64\r
EFIAPI\r
S3MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioBitFieldWrite64 (Address, StartBit, EndBit, Value));\r
UINT64\r
EFIAPI\r
S3MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioBitFieldOr64 (Address, StartBit, EndBit, OrData));\r
UINT64\r
EFIAPI\r
S3MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioBitFieldAnd64 (Address, StartBit, EndBit, AndData));\r
UINT64\r
EFIAPI\r
S3MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return InternalSaveMmioWrite64ValueToBootScript (Address, MmioBitFieldAndThenOr64 (Address, StartBit, EndBit, AndData, OrData));\r
UINT8 *\r
EFIAPI\r
S3MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioReadBuffer8 (StartAddress, Length, Buffer);\r
UINT16 *\r
EFIAPI\r
S3MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
- RETURN_STATUS Status;\r
+ UINT16 *ReturnBuffer;\r
+ RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioReadBuffer16 (StartAddress, Length, Buffer);\r
\r
UINT32 *\r
EFIAPI\r
S3MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioReadBuffer32 (StartAddress, Length, Buffer);\r
UINT64 *\r
EFIAPI\r
S3MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioReadBuffer64 (StartAddress, Length, Buffer);\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 8-bit access\r
and saves the value in the S3 script to be replayed on S3 resume.\r
UINT8 *\r
EFIAPI\r
S3MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioWriteBuffer8 (StartAddress, Length, Buffer);\r
UINT16 *\r
EFIAPI\r
S3MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioWriteBuffer16 (StartAddress, Length, Buffer);\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 32-bit access\r
and saves the value in the S3 script to be replayed on S3 resume.\r
UINT32 *\r
EFIAPI\r
S3MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioWriteBuffer32 (StartAddress, Length, Buffer);\r
UINT64 *\r
EFIAPI\r
S3MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
RETURN_STATUS Status;\r
\r
ReturnBuffer = MmioWriteBuffer64 (StartAddress, Length, Buffer);\r
\r
return ReturnBuffer;\r
}\r
-\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/DebugLib.h>\r
VOID\r
InternalSavePciWriteValueToBootScript (\r
IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINTN Address,\r
- IN VOID *Buffer\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfgWrite (\r
Width,\r
- PCILIB_TO_COMMON_ADDRESS(Address),\r
+ PCILIB_TO_COMMON_ADDRESS (Address),\r
1,\r
Buffer\r
);\r
**/\r
UINT8\r
InternalSavePciWrite8ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r
UINT8\r
EFIAPI\r
S3PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciRead8 (Address));\r
UINT8\r
EFIAPI\r
S3PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciWrite8 (Address, Value));\r
UINT8\r
EFIAPI\r
S3PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciOr8 (Address, OrData));\r
UINT8\r
EFIAPI\r
S3PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciAnd8 (Address, AndData));\r
UINT8\r
EFIAPI\r
S3PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciAndThenOr8 (Address, AndData, OrData));\r
UINT8\r
EFIAPI\r
S3PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldRead8 (Address, StartBit, EndBit));\r
UINT8\r
EFIAPI\r
S3PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldWrite8 (Address, StartBit, EndBit, Value));\r
UINT8\r
EFIAPI\r
S3PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldOr8 (Address, StartBit, EndBit, OrData));\r
UINT8\r
EFIAPI\r
S3PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r
UINT8\r
EFIAPI\r
S3PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT16\r
InternalSavePciWrite16ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r
UINT16\r
EFIAPI\r
S3PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciRead16 (Address));\r
UINT16\r
EFIAPI\r
S3PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciWrite16 (Address, Value));\r
UINT16\r
EFIAPI\r
S3PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciOr16 (Address, OrData));\r
UINT16\r
EFIAPI\r
S3PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciAnd16 (Address, AndData));\r
UINT16\r
EFIAPI\r
S3PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciAndThenOr16 (Address, AndData, OrData));\r
UINT16\r
EFIAPI\r
S3PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldRead16 (Address, StartBit, EndBit));\r
UINT16\r
EFIAPI\r
S3PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldWrite16 (Address, StartBit, EndBit, Value));\r
UINT16\r
EFIAPI\r
S3PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldOr16 (Address, StartBit, EndBit, OrData));\r
UINT16\r
EFIAPI\r
S3PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r
UINT16\r
EFIAPI\r
S3PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT32\r
InternalSavePciWrite32ValueToBootScript (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r
UINT32\r
EFIAPI\r
S3PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciRead32 (Address));\r
UINT32\r
EFIAPI\r
S3PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciWrite32 (Address, Value));\r
UINT32\r
EFIAPI\r
S3PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciOr32 (Address, OrData));\r
UINT32\r
EFIAPI\r
S3PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciAnd32 (Address, AndData));\r
UINT32\r
EFIAPI\r
S3PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciAndThenOr32 (Address, AndData, OrData));\r
UINT32\r
EFIAPI\r
S3PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldRead32 (Address, StartBit, EndBit));\r
UINT32\r
EFIAPI\r
S3PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldWrite32 (Address, StartBit, EndBit, Value));\r
UINT32\r
EFIAPI\r
S3PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldOr32 (Address, StartBit, EndBit, OrData));\r
UINT32\r
EFIAPI\r
S3PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r
UINT32\r
EFIAPI\r
S3PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r
UINTN\r
EFIAPI\r
S3PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfgWrite (\r
S3BootScriptWidthUint8,\r
PciReadBuffer (StartAddress, Size, Buffer),\r
Buffer\r
);\r
- ASSERT (Status == RETURN_SUCCESS);\r
+ ASSERT (Status == RETURN_SUCCESS);\r
\r
return Size;\r
}\r
UINTN\r
EFIAPI\r
S3PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfgWrite (\r
S3BootScriptWidthUint8,\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/DebugLib.h>\r
VOID\r
InternalSavePciSegmentWriteValueToBootScript (\r
IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r
- IN UINT64 Address,\r
- IN VOID *Buffer\r
+ IN UINT64 Address,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfg2Write (\r
Width,\r
**/\r
UINT8\r
InternalSavePciSegmentWrite8ValueToBootScript (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r
UINT8\r
EFIAPI\r
S3PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));\r
UINT8\r
EFIAPI\r
S3PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));\r
UINT8\r
EFIAPI\r
S3PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));\r
UINT8\r
EFIAPI\r
S3PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));\r
UINT8\r
EFIAPI\r
S3PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r
**/\r
UINT16\r
InternalSavePciSegmentWrite16ValueToBootScript (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r
UINT16\r
EFIAPI\r
S3PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));\r
UINT16\r
EFIAPI\r
S3PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));\r
UINT16\r
EFIAPI\r
S3PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));\r
UINT16\r
EFIAPI\r
S3PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));\r
UINT16\r
EFIAPI\r
S3PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
-\r
-\r
/**\r
Saves a 32-bit PCI configuration value to the boot script.\r
\r
**/\r
UINT32\r
InternalSavePciSegmentWrite32ValueToBootScript (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r
UINT32\r
EFIAPI\r
S3PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));\r
UINT32\r
EFIAPI\r
S3PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));\r
UINT32\r
EFIAPI\r
S3PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));\r
UINT32\r
EFIAPI\r
S3PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));\r
UINT32\r
EFIAPI\r
S3PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r
UINTN\r
EFIAPI\r
S3PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfg2Write (\r
S3BootScriptWidthUint8,\r
UINTN\r
EFIAPI\r
S3PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSavePciCfg2Write (\r
S3BootScriptWidthUint8,\r
\r
**/\r
\r
-\r
#include <Base.h>\r
\r
#include <Library/DebugLib.h>\r
**/\r
VOID\r
InternalSaveSmBusExecToBootScript (\r
- IN EFI_SMBUS_OPERATION SmbusOperation,\r
- IN UINTN SmBusAddress,\r
- IN UINTN Length,\r
- IN OUT VOID *Buffer\r
+ IN EFI_SMBUS_OPERATION SmbusOperation,\r
+ IN UINTN SmBusAddress,\r
+ IN UINTN Length,\r
+ IN OUT VOID *Buffer\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSaveSmbusExecute (\r
SmBusAddress,\r
SmbusOperation,\r
- &Length,\r
+ &Length,\r
Buffer\r
);\r
ASSERT (Status == RETURN_SUCCESS);\r
VOID\r
EFIAPI\r
S3SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
SmBusQuickRead (SmBusAddress, Status);\r
VOID\r
EFIAPI\r
S3SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
SmBusQuickWrite (SmBusAddress, Status);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
Byte = SmBusReceiveByte (SmBusAddress, Status);\r
\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
Byte = SmBusSendByte (SmBusAddress, Value, Status);\r
\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
Byte = SmBusReadDataByte (SmBusAddress, Status);\r
\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
Byte = SmBusWriteDataByte (SmBusAddress, Value, Status);\r
\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
Length = SmBusReadBlock (SmBusAddress, Buffer, Status);\r
\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
Length = SmBusBlockProcessCall (SmBusAddress, WriteBuffer, ReadBuffer, Status);\r
\r
#include <Library/S3BootScriptLib.h>\r
#include <Library/S3StallLib.h>\r
\r
-\r
/**\r
Stalls the CPU for at least the given number of microseconds and and saves\r
the value in the S3 script to be replayed on S3 resume.\r
UINTN\r
EFIAPI\r
S3Stall (\r
- IN UINTN MicroSeconds\r
+ IN UINTN MicroSeconds\r
)\r
{\r
- RETURN_STATUS Status;\r
+ RETURN_STATUS Status;\r
\r
Status = S3BootScriptSaveStall (MicroSecondDelay (MicroSeconds));\r
ASSERT (Status == RETURN_SUCCESS);\r
\r
return MicroSeconds;\r
}\r
-\r
-\r
#include <Library/SafeIntLib.h>\r
#include <Library/BaseLib.h>\r
\r
-\r
//\r
// Magnitude of MIN_INT64 as expressed by a UINT64 number.\r
//\r
-#define MIN_INT64_MAGNITUDE (((UINT64)(- (MIN_INT64 + 1))) + 1)\r
+#define MIN_INT64_MAGNITUDE (((UINT64)(- (MIN_INT64 + 1))) + 1)\r
\r
//\r
// Conversion functions\r
\r
if (Operand >= 0) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINTN)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT8) && (Operand <= MAX_INT8)) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_INT8)) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT8)) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINTN)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT8) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT16) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT8) && (Operand <= MAX_INT8)) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_INT8)) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT8)) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT16) && (Operand <= MAX_INT16)) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT16)) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT8) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT16) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT16) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT32) {\r
*Result = (INT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT8) && (Operand <= MAX_INT8)) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_INT8)) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT8)) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT16) && (Operand <= MAX_INT16)) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT16)) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINTN)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT8) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT16) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT16) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT32) {\r
*Result = (INT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INTN) {\r
*Result = (INTN)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT8) && (Operand <= MAX_INT8)) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_INT8)) {\r
*Result = (CHAR8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT8)) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT16) && (Operand <= MAX_INT16)) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT16)) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= MIN_INT32) && (Operand <= MAX_INT32)) {\r
*Result = (INT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Operand >= 0) && (Operand <= MAX_UINT32)) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand >= 0) {\r
*Result = (UINT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT8) {\r
*Result = (INT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = CHAR8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT8) {\r
*Result = (UINT8)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT16) {\r
*Result = (INT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT16) {\r
*Result = (UINT16)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT32) {\r
*Result = (INT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_UINT32) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INTN) {\r
*Result = (INTN)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Operand <= MAX_INT64) {\r
*Result = (INT64)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = INT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (((UINT8)(Augend + Addend)) >= Augend) {\r
*Result = (UINT8)(Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (((UINT16)(Augend + Addend)) >= Augend) {\r
*Result = (UINT16)(Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Augend + Addend) >= Augend) {\r
*Result = (Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if ((Augend + Addend) >= Augend) {\r
*Result = (Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Minuend >= Subtrahend) {\r
*Result = (UINT8)(Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT8_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Minuend >= Subtrahend) {\r
*Result = (UINT16)(Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT16_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Minuend >= Subtrahend) {\r
*Result = (Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Minuend >= Subtrahend) {\r
*Result = (Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
{\r
UINT64 IntermediateResult;\r
\r
- IntermediateResult = ((UINT64) Multiplicand) *((UINT64) Multiplier);\r
+ IntermediateResult = ((UINT64)Multiplicand) *((UINT64)Multiplier);\r
\r
return SafeUint64ToUint32 (IntermediateResult, Result);\r
}\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
- ProductAD = 0;\r
- ProductBC = 0;\r
- ProductBD = 0;\r
+ ProductAD = 0;\r
+ ProductBC = 0;\r
+ ProductBD = 0;\r
UnsignedResult = 0;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
\r
//\r
// 64x64 into 128 is like 32.32 x 32.32.\r
DwordD = (UINT32)Multiplier;\r
\r
*Result = (((UINT64)DwordB) *(UINT64)DwordD);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
//\r
// a * c must be 0 or there would be bits set in the high 64-bits\r
//\r
if ((DwordA == 0) ||\r
- (DwordC == 0)) {\r
+ (DwordC == 0))\r
+ {\r
DwordD = (UINT32)Multiplier;\r
\r
//\r
\r
if (!RETURN_ERROR (SafeUint64Add (UnsignedResult, ProductBD, &UnsignedResult))) {\r
*Result = UnsignedResult;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
}\r
}\r
}\r
if (RETURN_ERROR (Status)) {\r
*Result = UINT64_ERROR;\r
}\r
+\r
return Status;\r
}\r
\r
\r
Augend32 = (INT32)Augend;\r
Addend32 = (INT32)Addend;\r
- if (Augend32 < 0 || Augend32 > MAX_INT8) {\r
+ if ((Augend32 < 0) || (Augend32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
- if (Addend32 < 0 || Addend32 > MAX_INT8) {\r
+\r
+ if ((Addend32 < 0) || (Addend32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
// 0 >= (MIN_INT64 - Addend) > MIN_INT64\r
//\r
if (((Addend > 0) && (Augend > (MAX_INT64 - Addend))) ||\r
- ((Addend < 0) && (Augend < (MIN_INT64 - Addend)))) {\r
+ ((Addend < 0) && (Augend < (MIN_INT64 - Addend))))\r
+ {\r
*Result = INT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
} else {\r
*Result = Augend + Addend;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
}\r
\r
return Status;\r
\r
Minuend32 = (INT32)Minuend;\r
Subtrahend32 = (INT32)Subtrahend;\r
- if (Minuend32 < 0 || Minuend32 > MAX_INT8) {\r
+ if ((Minuend32 < 0) || (Minuend32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
- if (Subtrahend32 < 0 || Subtrahend32 > MAX_INT8) {\r
+\r
+ if ((Subtrahend32 < 0) || (Subtrahend32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
// -1 = (MAX_INT64 + MIN_INT64) <= (MAX_INT64 + Subtrahend) < MAX_INT64\r
//\r
if (((Subtrahend > 0) && (Minuend < (MIN_INT64 + Subtrahend))) ||\r
- ((Subtrahend < 0) && (Minuend > (MAX_INT64 + Subtrahend)))) {\r
+ ((Subtrahend < 0) && (Minuend > (MAX_INT64 + Subtrahend))))\r
+ {\r
*Result = INT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
} else {\r
*Result = Minuend - Subtrahend;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
}\r
\r
return Status;\r
\r
Multiplicand32 = (INT32)Multiplicand;\r
Multiplier32 = (INT32)Multiplier;\r
- if (Multiplicand32 < 0 || Multiplicand32 > MAX_INT8) {\r
+ if ((Multiplicand32 < 0) || (Multiplicand32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
- if (Multiplier32 < 0 || Multiplier32 > MAX_INT8) {\r
+\r
+ if ((Multiplier32 < 0) || (Multiplier32 > MAX_INT8)) {\r
*Result = CHAR8_ERROR;\r
return RETURN_BUFFER_TOO_SMALL;\r
}\r
//\r
// Avoid negating the most negative number.\r
//\r
- UnsignedMultiplicand = ((UINT64)(- (Multiplicand + 1))) + 1;\r
+ UnsignedMultiplicand = ((UINT64)(-(Multiplicand + 1))) + 1;\r
} else {\r
UnsignedMultiplicand = (UINT64)Multiplicand;\r
}\r
//\r
// Avoid negating the most negative number.\r
//\r
- UnsignedMultiplier = ((UINT64)(- (Multiplier + 1))) + 1;\r
+ UnsignedMultiplier = ((UINT64)(-(Multiplier + 1))) + 1;\r
} else {\r
UnsignedMultiplier = (UINT64)Multiplier;\r
}\r
if ((Multiplicand < 0) != (Multiplier < 0)) {\r
if (UnsignedResult > MIN_INT64_MAGNITUDE) {\r
*Result = INT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
} else if (UnsignedResult == MIN_INT64_MAGNITUDE) {\r
*Result = MIN_INT64;\r
} else {\r
- *Result = - ((INT64)UnsignedResult);\r
+ *Result = -((INT64)UnsignedResult);\r
}\r
} else {\r
if (UnsignedResult > MAX_INT64) {\r
*Result = INT64_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
} else {\r
*Result = (INT64)UnsignedResult;\r
}\r
} else {\r
*Result = INT64_ERROR;\r
}\r
+\r
return Status;\r
}\r
-\r
\r
if (Operand >= 0) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
OUT UINTN *Result\r
)\r
{\r
- return SafeUint64ToUint32 ((UINT64) Operand, (UINT32 *)Result);\r
+ return SafeUint64ToUint32 ((UINT64)Operand, (UINT32 *)Result);\r
}\r
\r
/**\r
\r
if ((Augend + Addend) >= Augend) {\r
*Result = (Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
\r
if (Minuend >= Subtrahend) {\r
*Result = (Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
{\r
UINT64 IntermediateResult;\r
\r
- IntermediateResult = ((UINT64) Multiplicand) *((UINT64) Multiplier);\r
+ IntermediateResult = ((UINT64)Multiplicand) *((UINT64)Multiplier);\r
\r
return SafeUint64ToUintn (IntermediateResult, Result);\r
}\r
{\r
return SafeInt64ToIntn (MultS64x64 (Multiplicand, Multiplier), Result);\r
}\r
-\r
OUT UINTN *Result\r
)\r
{\r
- return SafeInt32ToUint64 (Operand, (UINT64 *) Result);\r
+ return SafeInt32ToUint64 (Operand, (UINT64 *)Result);\r
}\r
\r
/**\r
OUT INT32 *Result\r
)\r
{\r
- return SafeInt64ToInt32 ((INT64) Operand, Result);\r
+ return SafeInt64ToInt32 ((INT64)Operand, Result);\r
}\r
\r
/**\r
{\r
return SafeInt64Mult ((INT64)Multiplicand, (INT64)Multiplier, (INT64 *)Result);\r
}\r
-\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt32ToUint32 (Operand, (UINT32 *)Result);\r
}\r
- return SafeInt32ToUint64 (Operand, (UINT64 *) Result);\r
+\r
+ return SafeInt32ToUint64 (Operand, (UINT64 *)Result);\r
}\r
\r
/**\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeUint32ToInt32 (Operand, (INT32 *)Result);\r
}\r
+\r
*Result = Operand;\r
return RETURN_SUCCESS;\r
}\r
*Result = (INT32)Operand;\r
return RETURN_SUCCESS;\r
}\r
- return SafeInt64ToInt32 ((INT64) Operand, Result);\r
+\r
+ return SafeInt64ToInt32 ((INT64)Operand, Result);\r
}\r
\r
/**\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
if (Operand >= 0) {\r
*Result = (UINT32)Operand;\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINT32_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
}\r
+\r
return SafeInt64ToUint32 ((INT64)Operand, Result);\r
}\r
\r
*Result = (UINT32)Operand;\r
return RETURN_SUCCESS;\r
}\r
+\r
return SafeUint64ToUint32 ((UINT64)Operand, Result);\r
}\r
\r
*Result = (INT64)Operand;\r
return RETURN_SUCCESS;\r
}\r
+\r
return SafeUint64ToInt64 ((UINT64)Operand, Result);\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt64ToInt32 (Operand, (INT32 *)Result);\r
}\r
+\r
*Result = (INTN)Operand;\r
return RETURN_SUCCESS;\r
}\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt64ToUint32 (Operand, (UINT32 *)Result);\r
}\r
+\r
return SafeInt64ToUint64 (Operand, (UINT64 *)Result);\r
}\r
\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
- return SafeUint64ToUint32 ((UINT64) Operand, (UINT32 *)Result);\r
+ return SafeUint64ToUint32 ((UINT64)Operand, (UINT32 *)Result);\r
}\r
+\r
*Result = Operand;\r
return RETURN_SUCCESS;\r
}\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
if ((UINT32)(Augend + Addend) >= Augend) {\r
*Result = (Augend + Addend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
}\r
+\r
return SafeUint64Add ((UINT64)Augend, (UINT64)Addend, (UINT64 *)Result);\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
if (Minuend >= Subtrahend) {\r
*Result = (Minuend - Subtrahend);\r
- Status = RETURN_SUCCESS;\r
+ Status = RETURN_SUCCESS;\r
} else {\r
*Result = UINTN_ERROR;\r
- Status = RETURN_BUFFER_TOO_SMALL;\r
+ Status = RETURN_BUFFER_TOO_SMALL;\r
}\r
\r
return Status;\r
}\r
+\r
return SafeUint64Sub ((UINT64)Minuend, (UINT64)Subtrahend, (UINT64 *)Result);\r
}\r
\r
UINT64 IntermediateResult;\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
- IntermediateResult = ((UINT64) Multiplicand) *((UINT64) Multiplier);\r
+ IntermediateResult = ((UINT64)Multiplicand) *((UINT64)Multiplier);\r
\r
return SafeUint64ToUintn (IntermediateResult, Result);\r
}\r
+\r
return SafeUint64Mult ((UINT64)Multiplicand, (UINT64)Multiplier, (UINT64 *)Result);\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt64ToIntn (((INT64)Augend) + ((INT64)Addend), Result);\r
}\r
+\r
return SafeInt64Add ((INT64)Augend, (INT64)Addend, (INT64 *)Result);\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt64ToIntn (((INT64)Minuend) - ((INT64)Subtrahend), Result);\r
}\r
+\r
return SafeInt64Sub ((INT64)Minuend, (INT64)Subtrahend, (INT64 *)Result);\r
}\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
return SafeInt64ToIntn (((INT64)Multiplicand) *((INT64)Multiplier), Result);\r
}\r
+\r
return SafeInt64Mult ((INT64)Multiplicand, (INT64)Multiplier, (INT64 *)Result);\r
}\r
-\r
\r
**/\r
\r
-\r
#include <Base.h>\r
#include <Library/SerialPortLib.h>\r
\r
UINTN\r
EFIAPI\r
SerialPortWrite (\r
- IN UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
+ IN UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
{\r
return 0;\r
}\r
\r
-\r
/**\r
Read data from serial device and save the datas in buffer.\r
\r
UINTN\r
EFIAPI\r
SerialPortRead (\r
- OUT UINT8 *Buffer,\r
- IN UINTN NumberOfBytes\r
-)\r
+ OUT UINT8 *Buffer,\r
+ IN UINTN NumberOfBytes\r
+ )\r
{\r
return 0;\r
}\r
RETURN_STATUS\r
EFIAPI\r
SerialPortSetControl (\r
- IN UINT32 Control\r
+ IN UINT32 Control\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
RETURN_STATUS\r
EFIAPI\r
SerialPortGetControl (\r
- OUT UINT32 *Control\r
+ OUT UINT32 *Control\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
RETURN_STATUS\r
EFIAPI\r
SerialPortSetAttributes (\r
- IN OUT UINT64 *BaudRate,\r
- IN OUT UINT32 *ReceiveFifoDepth,\r
- IN OUT UINT32 *Timeout,\r
- IN OUT EFI_PARITY_TYPE *Parity,\r
- IN OUT UINT8 *DataBits,\r
- IN OUT EFI_STOP_BITS_TYPE *StopBits\r
+ IN OUT UINT64 *BaudRate,\r
+ IN OUT UINT32 *ReceiveFifoDepth,\r
+ IN OUT UINT32 *Timeout,\r
+ IN OUT EFI_PARITY_TYPE *Parity,\r
+ IN OUT UINT8 *DataBits,\r
+ IN OUT EFI_STOP_BITS_TYPE *StopBits\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
}\r
-\r
VOID\r
EFIAPI\r
SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
VOID\r
EFIAPI\r
SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
\r
if (Status != NULL) {\r
*Status = RETURN_UNSUPPORTED;\r
}\r
+\r
return 0;\r
}\r
#include <Library/PcdLib.h>\r
\r
/// "canary" value that is inserted by the compiler into the stack frame.\r
-VOID *__stack_chk_guard = (VOID*)0x0AFF;\r
+VOID *__stack_chk_guard = (VOID *)0x0AFF;\r
\r
// If ASLR was enabled we could use\r
-//void (*__stack_chk_guard)(void) = __stack_chk_fail;\r
+// void (*__stack_chk_guard)(void) = __stack_chk_fail;\r
\r
/**\r
Error path for compiler generated stack "canary" value check code. If the\r
**/\r
VOID\r
__stack_chk_fail (\r
- VOID\r
- )\r
+ VOID\r
+ )\r
{\r
- UINT8 DebugPropertyMask;\r
+ UINT8 DebugPropertyMask;\r
\r
- DEBUG ((DEBUG_ERROR, "STACK FAULT: Buffer Overflow in function %a.\n", __builtin_return_address(0)));\r
+ DEBUG ((DEBUG_ERROR, "STACK FAULT: Buffer Overflow in function %a.\n", __builtin_return_address (0)));\r
\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings even if\r
if ((DebugPropertyMask & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
} else if ((DebugPropertyMask & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
- CpuDeadLoop ();\r
+ CpuDeadLoop ();\r
}\r
}\r
\r
**/\r
\r
-extern int __BaseStackCheckNull;\r
+extern int __BaseStackCheckNull;\r
UINT32\r
EFIAPI\r
InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
);\r
\r
-\r
/**\r
Performs an atomic decrement of an 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 16-bit unsigned integer.\r
\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
);\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
);\r
\r
/**\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
return *Value != CompareValue ? *Value :\r
- ((*Value = ExchangeValue), CompareValue);\r
+ ((*Value = ExchangeValue), CompareValue);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
return *Value != CompareValue ? *Value :\r
- ((*Value = ExchangeValue), CompareValue);\r
+ ((*Value = ExchangeValue), CompareValue);\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
return *Value != CompareValue ? *Value :\r
- ((*Value = ExchangeValue), CompareValue);\r
+ ((*Value = ExchangeValue), CompareValue);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
return ++*Value;\r
UINT32\r
EFIAPI\r
InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
return --*Value;\r
\r
**/\r
\r
-\r
-\r
/**\r
Performs an atomic increment of an 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
UINT32 Result;\r
: // no inputs that aren't also outputs\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return Result;\r
}\r
\r
-\r
/**\r
Performs an atomic decrement of an 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
- UINT32 Result;\r
+ UINT32 Result;\r
\r
__asm__ __volatile__ (\r
"movl $-1, %%eax \n\t"\r
: // no inputs that aren't also outputs\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return Result;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 16-bit unsigned integer.\r
\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
: "q" (ExchangeValue) // %2\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
: "q" (ExchangeValue) // %2\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
"c" ((UINT32) (ExchangeValue >> 32)) // %3\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Performs an atomic compare exchange operation on a 16-bit unsigned integer.\r
\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
_asm {\r
lock cmpxchg [ecx], dx\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
_asm {\r
lock cmpxchg [ecx], edx\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
_asm {\r
// In processors based on Intel NetBurst microarchitecture, use two cache lines\r
//\r
ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
- if (ModelId <= 0x04 || ModelId == 0x06) {\r
+ if ((ModelId <= 0x04) || (ModelId == 0x06)) {\r
CacheLineSize *= 2;\r
}\r
}\r
\r
return CacheLineSize;\r
}\r
-\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-long _InterlockedDecrement(\r
- long * lpAddend\r
-);\r
+long\r
+_InterlockedDecrement (\r
+ long *lpAddend\r
+ );\r
\r
#pragma intrinsic(_InterlockedDecrement)\r
\r
UINT32\r
EFIAPI\r
InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
return _InterlockedDecrement ((long *)(Value));\r
}\r
-\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-long _InterlockedIncrement(\r
- long * lpAddend\r
-);\r
+long\r
+_InterlockedIncrement (\r
+ long *lpAddend\r
+ );\r
\r
#pragma intrinsic(_InterlockedIncrement)\r
\r
UINT32\r
EFIAPI\r
InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
return _InterlockedIncrement ((long *)(Value));\r
}\r
-\r
\r
#include "BaseSynchronizationLibInternals.h"\r
\r
-#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
+#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
\r
/**\r
Retrieves the architecture specific spin lock alignment requirements for\r
SPIN_LOCK *\r
EFIAPI\r
InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
+ OUT SPIN_LOCK *SpinLock\r
)\r
{\r
ASSERT (SpinLock != NULL);\r
SPIN_LOCK *\r
EFIAPI\r
AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
UINT64 Current;\r
//\r
// Get the current timer value\r
//\r
- Current = GetPerformanceCounter();\r
+ Current = GetPerformanceCounter ();\r
\r
//\r
// Initialize local variables\r
if (Cycle < 0) {\r
Cycle = -Cycle;\r
}\r
+\r
Cycle++;\r
\r
while (!AcquireSpinLockOrFail (SpinLock)) {\r
CpuPause ();\r
Previous = Current;\r
- Current = GetPerformanceCounter();\r
- Delta = (INT64) (Current - Previous);\r
+ Current = GetPerformanceCounter ();\r
+ Delta = (INT64)(Current - Previous);\r
if (Start > End) {\r
Delta = -Delta;\r
}\r
+\r
if (Delta < 0) {\r
Delta += Cycle;\r
}\r
+\r
Total += Delta;\r
ASSERT (Total < Timeout);\r
}\r
}\r
+\r
return SpinLock;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
+ SPIN_LOCK LockValue;\r
\r
ASSERT (SpinLock != NULL);\r
\r
ASSERT (SPIN_LOCK_ACQUIRED == LockValue || SPIN_LOCK_RELEASED == LockValue);\r
\r
return (BOOLEAN)(\r
- InterlockedCompareExchangePointer (\r
- (VOID**)SpinLock,\r
- (VOID*)SPIN_LOCK_RELEASED,\r
- (VOID*)SPIN_LOCK_ACQUIRED\r
- ) == (VOID*)SPIN_LOCK_RELEASED\r
- );\r
+ InterlockedCompareExchangePointer (\r
+ (VOID **)SpinLock,\r
+ (VOID *)SPIN_LOCK_RELEASED,\r
+ (VOID *)SPIN_LOCK_ACQUIRED\r
+ ) == (VOID *)SPIN_LOCK_RELEASED\r
+ );\r
}\r
\r
/**\r
SPIN_LOCK *\r
EFIAPI\r
ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
+ SPIN_LOCK LockValue;\r
\r
ASSERT (SpinLock != NULL);\r
\r
UINT32\r
EFIAPI\r
InterlockedIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT16\r
EFIAPI\r
InterlockedCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT64\r
EFIAPI\r
InterlockedCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
VOID *\r
EFIAPI\r
InterlockedCompareExchangePointer (\r
- IN OUT VOID * volatile *Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
+ IN OUT VOID *volatile *Value,\r
+ IN VOID *CompareValue,\r
+ IN VOID *ExchangeValue\r
)\r
{\r
UINT8 SizeOfValue;\r
\r
switch (SizeOfValue) {\r
case sizeof (UINT32):\r
- return (VOID*)(UINTN)InterlockedCompareExchange32 (\r
- (volatile UINT32 *)Value,\r
- (UINT32)(UINTN)CompareValue,\r
- (UINT32)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (\r
+ (volatile UINT32 *)Value,\r
+ (UINT32)(UINTN)CompareValue,\r
+ (UINT32)(UINTN)ExchangeValue\r
+ );\r
case sizeof (UINT64):\r
- return (VOID*)(UINTN)InterlockedCompareExchange64 (\r
- (volatile UINT64 *)Value,\r
- (UINT64)(UINTN)CompareValue,\r
- (UINT64)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (\r
+ (volatile UINT64 *)Value,\r
+ (UINT64)(UINTN)CompareValue,\r
+ (UINT64)(UINTN)ExchangeValue\r
+ );\r
default:\r
ASSERT (FALSE);\r
return NULL;\r
//\r
// GCC inline assembly for Read Write Barrier\r
//\r
-#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)\r
+#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)\r
\r
-#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
+#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
\r
/**\r
Retrieves the architecture specific spin lock alignment requirements for\r
SPIN_LOCK *\r
EFIAPI\r
InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
+ OUT SPIN_LOCK *SpinLock\r
)\r
{\r
ASSERT (SpinLock != NULL);\r
\r
- _ReadWriteBarrier();\r
+ _ReadWriteBarrier ();\r
*SpinLock = SPIN_LOCK_RELEASED;\r
- _ReadWriteBarrier();\r
+ _ReadWriteBarrier ();\r
\r
return SpinLock;\r
}\r
SPIN_LOCK *\r
EFIAPI\r
AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
UINT64 Current;\r
//\r
// Get the current timer value\r
//\r
- Current = GetPerformanceCounter();\r
+ Current = GetPerformanceCounter ();\r
\r
//\r
// Initialize local variables\r
if (Cycle < 0) {\r
Cycle = -Cycle;\r
}\r
+\r
Cycle++;\r
\r
while (!AcquireSpinLockOrFail (SpinLock)) {\r
CpuPause ();\r
Previous = Current;\r
- Current = GetPerformanceCounter();\r
- Delta = (INT64) (Current - Previous);\r
+ Current = GetPerformanceCounter ();\r
+ Delta = (INT64)(Current - Previous);\r
if (Start > End) {\r
Delta = -Delta;\r
}\r
+\r
if (Delta < 0) {\r
Delta += Cycle;\r
}\r
+\r
Total += Delta;\r
ASSERT (Total < Timeout);\r
}\r
}\r
+\r
return SpinLock;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
- VOID *Result;\r
+ SPIN_LOCK LockValue;\r
+ VOID *Result;\r
\r
ASSERT (SpinLock != NULL);\r
\r
\r
_ReadWriteBarrier ();\r
Result = InterlockedCompareExchangePointer (\r
- (VOID**)SpinLock,\r
- (VOID*)SPIN_LOCK_RELEASED,\r
- (VOID*)SPIN_LOCK_ACQUIRED\r
- );\r
+ (VOID **)SpinLock,\r
+ (VOID *)SPIN_LOCK_RELEASED,\r
+ (VOID *)SPIN_LOCK_ACQUIRED\r
+ );\r
\r
_ReadWriteBarrier ();\r
- return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);\r
+ return (BOOLEAN)(Result == (VOID *)SPIN_LOCK_RELEASED);\r
}\r
\r
/**\r
SPIN_LOCK *\r
EFIAPI\r
ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
+ SPIN_LOCK LockValue;\r
\r
ASSERT (SpinLock != NULL);\r
\r
UINT32\r
EFIAPI\r
InterlockedIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT16\r
EFIAPI\r
InterlockedCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT64\r
EFIAPI\r
InterlockedCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
VOID *\r
EFIAPI\r
InterlockedCompareExchangePointer (\r
- IN OUT VOID * volatile *Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
+ IN OUT VOID *volatile *Value,\r
+ IN VOID *CompareValue,\r
+ IN VOID *ExchangeValue\r
)\r
{\r
UINT8 SizeOfValue;\r
\r
switch (SizeOfValue) {\r
case sizeof (UINT32):\r
- return (VOID*)(UINTN)InterlockedCompareExchange32 (\r
- (volatile UINT32 *)Value,\r
- (UINT32)(UINTN)CompareValue,\r
- (UINT32)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (\r
+ (volatile UINT32 *)Value,\r
+ (UINT32)(UINTN)CompareValue,\r
+ (UINT32)(UINTN)ExchangeValue\r
+ );\r
case sizeof (UINT64):\r
- return (VOID*)(UINTN)InterlockedCompareExchange64 (\r
- (volatile UINT64 *)Value,\r
- (UINT64)(UINTN)CompareValue,\r
- (UINT64)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (\r
+ (volatile UINT64 *)Value,\r
+ (UINT64)(UINTN)CompareValue,\r
+ (UINT64)(UINTN)ExchangeValue\r
+ );\r
default:\r
ASSERT (FALSE);\r
return NULL;\r
Microsoft Visual Studio 7.1 Function Prototypes for read write barrier Intrinsics.\r
**/\r
\r
-void _ReadWriteBarrier (void);\r
-#pragma intrinsic(_ReadWriteBarrier)\r
+void\r
+_ReadWriteBarrier (\r
+ void\r
+ );\r
\r
+#pragma intrinsic(_ReadWriteBarrier)\r
\r
-#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
-#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
+#define SPIN_LOCK_RELEASED ((UINTN) 1)\r
+#define SPIN_LOCK_ACQUIRED ((UINTN) 2)\r
\r
/**\r
Retrieves the architecture specific spin lock alignment requirements for\r
SPIN_LOCK *\r
EFIAPI\r
InitializeSpinLock (\r
- OUT SPIN_LOCK *SpinLock\r
+ OUT SPIN_LOCK *SpinLock\r
)\r
{\r
ASSERT (SpinLock != NULL);\r
\r
- _ReadWriteBarrier();\r
+ _ReadWriteBarrier ();\r
*SpinLock = SPIN_LOCK_RELEASED;\r
- _ReadWriteBarrier();\r
+ _ReadWriteBarrier ();\r
\r
return SpinLock;\r
}\r
SPIN_LOCK *\r
EFIAPI\r
AcquireSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
UINT64 Current;\r
//\r
// Get the current timer value\r
//\r
- Current = GetPerformanceCounter();\r
+ Current = GetPerformanceCounter ();\r
\r
//\r
// Initialize local variables\r
if (Cycle < 0) {\r
Cycle = -Cycle;\r
}\r
+\r
Cycle++;\r
\r
while (!AcquireSpinLockOrFail (SpinLock)) {\r
CpuPause ();\r
Previous = Current;\r
- Current = GetPerformanceCounter();\r
- Delta = (INT64) (Current - Previous);\r
+ Current = GetPerformanceCounter ();\r
+ Delta = (INT64)(Current - Previous);\r
if (Start > End) {\r
Delta = -Delta;\r
}\r
+\r
if (Delta < 0) {\r
Delta += Cycle;\r
}\r
+\r
Total += Delta;\r
ASSERT (Total < Timeout);\r
}\r
}\r
+\r
return SpinLock;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
AcquireSpinLockOrFail (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
- VOID *Result;\r
+ SPIN_LOCK LockValue;\r
+ VOID *Result;\r
\r
ASSERT (SpinLock != NULL);\r
\r
\r
_ReadWriteBarrier ();\r
Result = InterlockedCompareExchangePointer (\r
- (VOID**)SpinLock,\r
- (VOID*)SPIN_LOCK_RELEASED,\r
- (VOID*)SPIN_LOCK_ACQUIRED\r
- );\r
+ (VOID **)SpinLock,\r
+ (VOID *)SPIN_LOCK_RELEASED,\r
+ (VOID *)SPIN_LOCK_ACQUIRED\r
+ );\r
\r
_ReadWriteBarrier ();\r
- return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);\r
+ return (BOOLEAN)(Result == (VOID *)SPIN_LOCK_RELEASED);\r
}\r
\r
/**\r
SPIN_LOCK *\r
EFIAPI\r
ReleaseSpinLock (\r
- IN OUT SPIN_LOCK *SpinLock\r
+ IN OUT SPIN_LOCK *SpinLock\r
)\r
{\r
- SPIN_LOCK LockValue;\r
+ SPIN_LOCK LockValue;\r
\r
ASSERT (SpinLock != NULL);\r
\r
UINT32\r
EFIAPI\r
InterlockedIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT16\r
EFIAPI\r
InterlockedCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT32\r
EFIAPI\r
InterlockedCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
UINT64\r
EFIAPI\r
InterlockedCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
ASSERT (Value != NULL);\r
VOID *\r
EFIAPI\r
InterlockedCompareExchangePointer (\r
- IN OUT VOID * volatile *Value,\r
- IN VOID *CompareValue,\r
- IN VOID *ExchangeValue\r
+ IN OUT VOID *volatile *Value,\r
+ IN VOID *CompareValue,\r
+ IN VOID *ExchangeValue\r
)\r
{\r
UINT8 SizeOfValue;\r
\r
- SizeOfValue = (UINT8) sizeof (*Value);\r
+ SizeOfValue = (UINT8)sizeof (*Value);\r
\r
switch (SizeOfValue) {\r
case sizeof (UINT32):\r
- return (VOID*)(UINTN)InterlockedCompareExchange32 (\r
- (volatile UINT32*)Value,\r
- (UINT32)(UINTN)CompareValue,\r
- (UINT32)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange32 (\r
+ (volatile UINT32 *)Value,\r
+ (UINT32)(UINTN)CompareValue,\r
+ (UINT32)(UINTN)ExchangeValue\r
+ );\r
case sizeof (UINT64):\r
- return (VOID*)(UINTN)InterlockedCompareExchange64 (\r
- (volatile UINT64*)Value,\r
- (UINT64)(UINTN)CompareValue,\r
- (UINT64)(UINTN)ExchangeValue\r
- );\r
+ return (VOID *)(UINTN)InterlockedCompareExchange64 (\r
+ (volatile UINT64 *)Value,\r
+ (UINT64)(UINTN)CompareValue,\r
+ (UINT64)(UINTN)ExchangeValue\r
+ );\r
default:\r
ASSERT (FALSE);\r
return NULL;\r
\r
**/\r
\r
-\r
-\r
/**\r
Performs an atomic increment of an 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncIncrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
UINT32 Result;\r
: // no inputs that aren't also outputs\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return Result;\r
}\r
\r
-\r
/**\r
Performs an atomic decrement of an 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncDecrement (\r
- IN volatile UINT32 *Value\r
+ IN volatile UINT32 *Value\r
)\r
{\r
- UINT32 Result;\r
+ UINT32 Result;\r
\r
__asm__ __volatile__ (\r
"movl $-1, %%eax \n\t"\r
: // no inputs that aren't also outputs\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return Result;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 16-bit unsigned integer.\r
\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN OUT volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN OUT volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
: "r" (ExchangeValue) // %2\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 32-bit unsigned integer.\r
\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN OUT volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN OUT volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
: "r" (ExchangeValue) // %2\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
\r
-\r
/**\r
Performs an atomic compare exchange operation on a 64-bit unsigned integer.\r
\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN OUT volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN OUT volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
__asm__ __volatile__ (\r
: "r" (ExchangeValue) // %2\r
: "memory",\r
"cc"\r
- );\r
+ );\r
\r
return CompareValue;\r
}\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-__int16 _InterlockedCompareExchange16(\r
- __int16 volatile * Destination,\r
- __int16 Exchange,\r
- __int16 Comperand\r
-);\r
+__int16\r
+_InterlockedCompareExchange16 (\r
+ __int16 volatile *Destination,\r
+ __int16 Exchange,\r
+ __int16 Comperand\r
+ );\r
\r
#pragma intrinsic(_InterlockedCompareExchange16)\r
\r
UINT16\r
EFIAPI\r
InternalSyncCompareExchange16 (\r
- IN volatile UINT16 *Value,\r
- IN UINT16 CompareValue,\r
- IN UINT16 ExchangeValue\r
+ IN volatile UINT16 *Value,\r
+ IN UINT16 CompareValue,\r
+ IN UINT16 ExchangeValue\r
)\r
{\r
return _InterlockedCompareExchange16 (Value, ExchangeValue, CompareValue);\r
}\r
-\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-long _InterlockedCompareExchange(\r
- long volatile * Destination,\r
- long Exchange,\r
- long Comperand\r
-);\r
+long\r
+_InterlockedCompareExchange (\r
+ long volatile *Destination,\r
+ long Exchange,\r
+ long Comperand\r
+ );\r
\r
#pragma intrinsic(_InterlockedCompareExchange)\r
\r
UINT32\r
EFIAPI\r
InternalSyncCompareExchange32 (\r
- IN volatile UINT32 *Value,\r
- IN UINT32 CompareValue,\r
- IN UINT32 ExchangeValue\r
+ IN volatile UINT32 *Value,\r
+ IN UINT32 CompareValue,\r
+ IN UINT32 ExchangeValue\r
)\r
{\r
return _InterlockedCompareExchange (Value, ExchangeValue, CompareValue);\r
}\r
-\r
Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.\r
**/\r
\r
-__int64 _InterlockedCompareExchange64(\r
- __int64 volatile * Destination,\r
- __int64 Exchange,\r
- __int64 Comperand\r
-);\r
+__int64\r
+_InterlockedCompareExchange64 (\r
+ __int64 volatile *Destination,\r
+ __int64 Exchange,\r
+ __int64 Comperand\r
+ );\r
\r
#pragma intrinsic(_InterlockedCompareExchange64)\r
\r
UINT64\r
EFIAPI\r
InternalSyncCompareExchange64 (\r
- IN volatile UINT64 *Value,\r
- IN UINT64 CompareValue,\r
- IN UINT64 ExchangeValue\r
+ IN volatile UINT64 *Value,\r
+ IN UINT64 CompareValue,\r
+ IN UINT64 ExchangeValue\r
)\r
{\r
return _InterlockedCompareExchange64 (Value, ExchangeValue, CompareValue);\r
}\r
-\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
+ IN UINTN MicroSeconds\r
)\r
{\r
ASSERT (FALSE);\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
+ IN UINTN NanoSeconds\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue OPTIONAL,\r
- OUT UINT64 *EndValue OPTIONAL\r
+ OUT UINT64 *StartValue OPTIONAL,\r
+ OUT UINT64 *EndValue OPTIONAL\r
)\r
{\r
ASSERT (FALSE);\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
+ IN UINT64 Ticks\r
)\r
{\r
ASSERT (FALSE);\r
//\r
// Left shift NumOfBits of bits in advance\r
//\r
- Sd->mBitBuf = (UINT32) LShiftU64 (((UINT64)Sd->mBitBuf), NumOfBits);\r
+ Sd->mBitBuf = (UINT32)LShiftU64 (((UINT64)Sd->mBitBuf), NumOfBits);\r
\r
//\r
// Copy data needed in bytes into mSbuBitBuf\r
//\r
while (NumOfBits > Sd->mBitCount) {\r
- NumOfBits = (UINT16) (NumOfBits - Sd->mBitCount);\r
- Sd->mBitBuf |= (UINT32) LShiftU64 (((UINT64)Sd->mSubBitBuf), NumOfBits);\r
+ NumOfBits = (UINT16)(NumOfBits - Sd->mBitCount);\r
+ Sd->mBitBuf |= (UINT32)LShiftU64 (((UINT64)Sd->mSubBitBuf), NumOfBits);\r
\r
if (Sd->mCompSize > 0) {\r
//\r
// Get 1 byte into SubBitBuf\r
//\r
Sd->mCompSize--;\r
- Sd->mSubBitBuf = Sd->mSrcBase[Sd->mInBuf++];\r
- Sd->mBitCount = 8;\r
-\r
+ Sd->mSubBitBuf = Sd->mSrcBase[Sd->mInBuf++];\r
+ Sd->mBitCount = 8;\r
} else {\r
//\r
// No more bits from the source, just pad zero bit.\r
//\r
- Sd->mSubBitBuf = 0;\r
- Sd->mBitCount = 8;\r
-\r
+ Sd->mSubBitBuf = 0;\r
+ Sd->mBitCount = 8;\r
}\r
}\r
\r
//\r
// Calculate additional bit count read to update mBitCount\r
//\r
- Sd->mBitCount = (UINT16) (Sd->mBitCount - NumOfBits);\r
+ Sd->mBitCount = (UINT16)(Sd->mBitCount - NumOfBits);\r
\r
//\r
// Copy NumOfBits of bits from mSubBitBuf into mBitBuf\r
//\r
// Pop NumOfBits of Bits from Left\r
//\r
- OutBits = (UINT32) (Sd->mBitBuf >> (BITBUFSIZ - NumOfBits));\r
+ OutBits = (UINT32)(Sd->mBitBuf >> (BITBUFSIZ - NumOfBits));\r
\r
//\r
// Fill up mBitBuf from source\r
\r
for (Index = 0; Index < NumOfChar; Index++) {\r
if (BitLen[Index] > 16) {\r
- return (UINT16) BAD_TABLE;\r
+ return (UINT16)BAD_TABLE;\r
}\r
+\r
Count[BitLen[Index]]++;\r
}\r
\r
Start[1] = 0;\r
\r
for (Index = 1; Index <= 16; Index++) {\r
- WordOfStart = Start[Index];\r
- WordOfCount = Count[Index];\r
- Start[Index + 1] = (UINT16) (WordOfStart + (WordOfCount << (16 - Index)));\r
+ WordOfStart = Start[Index];\r
+ WordOfCount = Count[Index];\r
+ Start[Index + 1] = (UINT16)(WordOfStart + (WordOfCount << (16 - Index)));\r
}\r
\r
if (Start[17] != 0) {\r
/*(1U << 16)*/\r
- return (UINT16) BAD_TABLE;\r
+ return (UINT16)BAD_TABLE;\r
}\r
\r
- JuBits = (UINT16) (16 - TableBits);\r
+ JuBits = (UINT16)(16 - TableBits);\r
\r
Weight[0] = 0;\r
for (Index = 1; Index <= TableBits; Index++) {\r
Start[Index] >>= JuBits;\r
- Weight[Index] = (UINT16) (1U << (TableBits - Index));\r
+ Weight[Index] = (UINT16)(1U << (TableBits - Index));\r
}\r
\r
while (Index <= 16) {\r
- Weight[Index] = (UINT16) (1U << (16 - Index));\r
+ Weight[Index] = (UINT16)(1U << (16 - Index));\r
Index++;\r
}\r
\r
- Index = (UINT16) (Start[TableBits + 1] >> JuBits);\r
+ Index = (UINT16)(Start[TableBits + 1] >> JuBits);\r
\r
if (Index != 0) {\r
- Index3 = (UINT16) (1U << TableBits);\r
+ Index3 = (UINT16)(1U << TableBits);\r
if (Index < Index3) {\r
SetMem16 (Table + Index, (Index3 - Index) * sizeof (*Table), 0);\r
}\r
}\r
\r
- Avail = NumOfChar;\r
- Mask = (UINT16) (1U << (15 - TableBits));\r
- MaxTableLength = (UINT16) (1U << TableBits);\r
+ Avail = NumOfChar;\r
+ Mask = (UINT16)(1U << (15 - TableBits));\r
+ MaxTableLength = (UINT16)(1U << TableBits);\r
\r
for (Char = 0; Char < NumOfChar; Char++) {\r
-\r
Len = BitLen[Char];\r
- if (Len == 0 || Len >= 17) {\r
+ if ((Len == 0) || (Len >= 17)) {\r
continue;\r
}\r
\r
- NextCode = (UINT16) (Start[Len] + Weight[Len]);\r
+ NextCode = (UINT16)(Start[Len] + Weight[Len]);\r
\r
if (Len <= TableBits) {\r
-\r
- if (Start[Len] >= NextCode || NextCode > MaxTableLength){\r
- return (UINT16) BAD_TABLE;\r
+ if ((Start[Len] >= NextCode) || (NextCode > MaxTableLength)) {\r
+ return (UINT16)BAD_TABLE;\r
}\r
\r
for (Index = Start[Len]; Index < NextCode; Index++) {\r
Table[Index] = Char;\r
}\r
-\r
} else {\r
-\r
Index3 = Start[Len];\r
Pointer = &Table[Index3 >> JuBits];\r
- Index = (UINT16) (Len - TableBits);\r
+ Index = (UINT16)(Len - TableBits);\r
\r
while (Index != 0) {\r
- if (*Pointer == 0 && Avail < (2 * NC - 1)) {\r
+ if ((*Pointer == 0) && (Avail < (2 * NC - 1))) {\r
Sd->mRight[Avail] = Sd->mLeft[Avail] = 0;\r
- *Pointer = Avail++;\r
+ *Pointer = Avail++;\r
}\r
\r
if (*Pointer < (2 * NC - 1)) {\r
}\r
\r
*Pointer = Char;\r
-\r
}\r
\r
Start[Len] = NextCode;\r
}\r
+\r
//\r
// Succeeds\r
//\r
Mask = 1U << (BITBUFSIZ - 1 - 8);\r
\r
do {\r
-\r
if ((Sd->mBitBuf & Mask) != 0) {\r
Val = Sd->mRight[Val];\r
} else {\r
Mask >>= 1;\r
} while (Val >= MAXNP);\r
}\r
+\r
//\r
// Advance what we have read\r
//\r
\r
Pos = Val;\r
if (Val > 1) {\r
- Pos = (UINT32) ((1U << (Val - 1)) + GetBits (Sd, (UINT16) (Val - 1)));\r
+ Pos = (UINT32)((1U << (Val - 1)) + GetBits (Sd, (UINT16)(Val - 1)));\r
}\r
\r
return Pos;\r
//\r
// Read Extra Set Code Length Array size\r
//\r
- Number = (UINT16) GetBits (Sd, nbit);\r
+ Number = (UINT16)GetBits (Sd, nbit);\r
\r
if (Number == 0) {\r
//\r
// This represents only Huffman code used\r
//\r
- CharC = (UINT16) GetBits (Sd, nbit);\r
+ CharC = (UINT16)GetBits (Sd, nbit);\r
\r
- SetMem16 (&Sd->mPTTable[0] , sizeof (Sd->mPTTable), CharC);\r
+ SetMem16 (&Sd->mPTTable[0], sizeof (Sd->mPTTable), CharC);\r
\r
SetMem (Sd->mPTLen, nn, 0);\r
\r
Index = 0;\r
\r
while (Index < Number && Index < NPT) {\r
-\r
- CharC = (UINT16) (Sd->mBitBuf >> (BITBUFSIZ - 3));\r
+ CharC = (UINT16)(Sd->mBitBuf >> (BITBUFSIZ - 3));\r
\r
//\r
// If a code length is less than 7, then it is encoded as a 3-bit\r
}\r
}\r
\r
- FillBuf (Sd, (UINT16) ((CharC < 7) ? 3 : CharC - 3));\r
+ FillBuf (Sd, (UINT16)((CharC < 7) ? 3 : CharC - 3));\r
\r
- Sd->mPTLen[Index++] = (UINT8) CharC;\r
+ Sd->mPTLen[Index++] = (UINT8)CharC;\r
\r
//\r
// For Code&Len Set,\r
// zero lengths after the third length.\r
//\r
if (Index == Special) {\r
- CharC = (UINT16) GetBits (Sd, 2);\r
- while ((INT16) (--CharC) >= 0 && Index < NPT) {\r
+ CharC = (UINT16)GetBits (Sd, 2);\r
+ while ((INT16)(--CharC) >= 0 && Index < NPT) {\r
Sd->mPTLen[Index++] = 0;\r
}\r
}\r
SCRATCH_DATA *Sd\r
)\r
{\r
- UINT16 Number;\r
- UINT16 CharC;\r
- UINT16 Index;\r
- UINT32 Mask;\r
+ UINT16 Number;\r
+ UINT16 CharC;\r
+ UINT16 Index;\r
+ UINT32 Mask;\r
\r
- Number = (UINT16) GetBits (Sd, CBIT);\r
+ Number = (UINT16)GetBits (Sd, CBIT);\r
\r
if (Number == 0) {\r
//\r
// This represents only Huffman code used\r
//\r
- CharC = (UINT16) GetBits (Sd, CBIT);\r
+ CharC = (UINT16)GetBits (Sd, CBIT);\r
\r
SetMem (Sd->mCLen, NC, 0);\r
SetMem16 (&Sd->mCTable[0], sizeof (Sd->mCTable), CharC);\r
\r
- return ;\r
+ return;\r
}\r
\r
Index = 0;\r
Mask = 1U << (BITBUFSIZ - 1 - 8);\r
\r
do {\r
-\r
if (Mask & Sd->mBitBuf) {\r
CharC = Sd->mRight[CharC];\r
} else {\r
}\r
\r
Mask >>= 1;\r
-\r
} while (CharC >= NT);\r
}\r
+\r
//\r
// Advance what we have read\r
//\r
FillBuf (Sd, Sd->mPTLen[CharC]);\r
\r
if (CharC <= 2) {\r
-\r
if (CharC == 0) {\r
CharC = 1;\r
} else if (CharC == 1) {\r
- CharC = (UINT16) (GetBits (Sd, 4) + 3);\r
+ CharC = (UINT16)(GetBits (Sd, 4) + 3);\r
} else if (CharC == 2) {\r
- CharC = (UINT16) (GetBits (Sd, CBIT) + 20);\r
+ CharC = (UINT16)(GetBits (Sd, CBIT) + 20);\r
}\r
\r
- while ((INT16) (--CharC) >= 0 && Index < NC) {\r
+ while ((INT16)(--CharC) >= 0 && Index < NC) {\r
Sd->mCLen[Index++] = 0;\r
}\r
-\r
} else {\r
-\r
- Sd->mCLen[Index++] = (UINT8) (CharC - 2);\r
-\r
+ Sd->mCLen[Index++] = (UINT8)(CharC - 2);\r
}\r
}\r
\r
\r
MakeTable (Sd, NC, Sd->mCLen, 12, Sd->mCTable);\r
\r
- return ;\r
+ return;\r
}\r
\r
/**\r
// Starting a new block\r
// Read BlockSize from block header\r
//\r
- Sd->mBlockSize = (UINT16) GetBits (Sd, 16);\r
+ Sd->mBlockSize = (UINT16)GetBits (Sd, 16);\r
\r
//\r
// Read in the Extra Set Code Length Array,\r
// Read in the Position Set Code Length Array,\r
// Generate the Huffman code mapping table for the Position Set.\r
//\r
- Sd->mBadTableFlag = ReadPTLen (Sd, MAXNP, Sd->mPBit, (UINT16) (-1));\r
+ Sd->mBadTableFlag = ReadPTLen (Sd, MAXNP, Sd->mPBit, (UINT16)(-1));\r
if (Sd->mBadTableFlag != 0) {\r
return 0;\r
}\r
Mask >>= 1;\r
} while (Index2 >= NC);\r
}\r
+\r
//\r
// Advance what we have read\r
//\r
UINT32 DataIdx;\r
UINT16 CharC;\r
\r
- BytesRemain = (UINT16) (-1);\r
+ BytesRemain = (UINT16)(-1);\r
\r
- DataIdx = 0;\r
+ DataIdx = 0;\r
\r
- for (;;) {\r
+ for ( ; ;) {\r
//\r
// Get one code from mBitBuf\r
//\r
//\r
// Write orignal character into mDstBase\r
//\r
- Sd->mDstBase[Sd->mOutBuf++] = (UINT8) CharC;\r
+ Sd->mDstBase[Sd->mOutBuf++] = (UINT8)CharC;\r
}\r
-\r
} else {\r
//\r
// Process a Pointer\r
//\r
- CharC = (UINT16) (CharC - (BIT8 - THRESHOLD));\r
+ CharC = (UINT16)(CharC - (BIT8 - THRESHOLD));\r
\r
//\r
// Get string length\r
//\r
// Locate string position\r
//\r
- DataIdx = Sd->mOutBuf - DecodeP (Sd) - 1;\r
+ DataIdx = Sd->mOutBuf - DecodeP (Sd) - 1;\r
\r
//\r
// Write BytesRemain of bytes into mDstBase\r
//\r
BytesRemain--;\r
\r
- while ((INT16) (BytesRemain) >= 0) {\r
+ while ((INT16)(BytesRemain) >= 0) {\r
if (Sd->mOutBuf >= Sd->mOrigSize) {\r
goto Done;\r
}\r
+\r
if (DataIdx >= Sd->mOrigSize) {\r
- Sd->mBadTableFlag = (UINT16) BAD_TABLE;\r
+ Sd->mBadTableFlag = (UINT16)BAD_TABLE;\r
goto Done;\r
}\r
+\r
Sd->mDstBase[Sd->mOutBuf++] = Sd->mDstBase[DataIdx++];\r
\r
BytesRemain--;\r
}\r
+\r
//\r
// Once mOutBuf is fully filled, directly return\r
//\r
}\r
\r
Done:\r
- return ;\r
+ return;\r
}\r
\r
/**\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
- CompressedSize = ReadUnaligned32 ((UINT32 *)Source);\r
- if (SourceSize < (CompressedSize + 8) || (CompressedSize + 8) < 8) {\r
+ CompressedSize = ReadUnaligned32 ((UINT32 *)Source);\r
+ if ((SourceSize < (CompressedSize + 8)) || ((CompressedSize + 8) < 8)) {\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
- *ScratchSize = sizeof (SCRATCH_DATA);\r
+ *ScratchSize = sizeof (SCRATCH_DATA);\r
*DestinationSize = ReadUnaligned32 ((UINT32 *)Source + 1);\r
\r
return RETURN_SUCCESS;\r
IN UINT32 Version\r
)\r
{\r
- UINT32 CompSize;\r
- UINT32 OrigSize;\r
- SCRATCH_DATA *Sd;\r
- CONST UINT8 *Src;\r
- UINT8 *Dst;\r
+ UINT32 CompSize;\r
+ UINT32 OrigSize;\r
+ SCRATCH_DATA *Sd;\r
+ CONST UINT8 *Src;\r
+ UINT8 *Dst;\r
\r
ASSERT (Source != NULL);\r
ASSERT (Destination != NULL);\r
ASSERT (Scratch != NULL);\r
ASSERT (Version == 1 || Version == 2);\r
\r
- Src = Source;\r
- Dst = Destination;\r
+ Src = Source;\r
+ Dst = Destination;\r
\r
- Sd = (SCRATCH_DATA *) Scratch;\r
+ Sd = (SCRATCH_DATA *)Scratch;\r
\r
- CompSize = Src[0] + (Src[1] << 8) + (Src[2] << 16) + (Src[3] << 24);\r
- OrigSize = Src[4] + (Src[5] << 8) + (Src[6] << 16) + (Src[7] << 24);\r
+ CompSize = Src[0] + (Src[1] << 8) + (Src[2] << 16) + (Src[3] << 24);\r
+ OrigSize = Src[4] + (Src[5] << 8) + (Src[6] << 16) + (Src[7] << 24);\r
\r
//\r
// If compressed file size is 0, return\r
// For Tiano de/compression algorithm(Version 2), mPBit = 5\r
//\r
switch (Version) {\r
- case 1 :\r
+ case 1:\r
Sd->mPBit = 4;\r
break;\r
- case 2 :\r
+ case 2:\r
Sd->mPBit = 5;\r
break;\r
default:\r
ASSERT (FALSE);\r
}\r
- Sd->mSrcBase = (UINT8 *)Src;\r
- Sd->mDstBase = Dst;\r
+\r
+ Sd->mSrcBase = (UINT8 *)Src;\r
+ Sd->mDstBase = Dst;\r
//\r
// CompSize and OrigSize are calculated in bytes\r
//\r
//\r
// Decompression algorithm begins here\r
//\r
-#define BITBUFSIZ 32\r
-#define MAXMATCH 256\r
-#define THRESHOLD 3\r
-#define CODE_BIT 16\r
-#define BAD_TABLE - 1\r
+#define BITBUFSIZ 32\r
+#define MAXMATCH 256\r
+#define THRESHOLD 3\r
+#define CODE_BIT 16\r
+#define BAD_TABLE - 1\r
\r
//\r
// C: Char&Len Set; P: Position Set; T: exTra Set\r
//\r
-#define NC (0xff + MAXMATCH + 2 - THRESHOLD)\r
-#define CBIT 9\r
-#define MAXPBIT 5\r
-#define TBIT 5\r
-#define MAXNP ((1U << MAXPBIT) - 1)\r
-#define NT (CODE_BIT + 3)\r
+#define NC (0xff + MAXMATCH + 2 - THRESHOLD)\r
+#define CBIT 9\r
+#define MAXPBIT 5\r
+#define TBIT 5\r
+#define MAXNP ((1U << MAXPBIT) - 1)\r
+#define NT (CODE_BIT + 3)\r
#if NT > MAXNP\r
-#define NPT NT\r
+#define NPT NT\r
#else\r
-#define NPT MAXNP\r
+#define NPT MAXNP\r
#endif\r
\r
typedef struct {\r
- UINT8 *mSrcBase; // The starting address of compressed data\r
- UINT8 *mDstBase; // The starting address of decompressed data\r
- UINT32 mOutBuf;\r
- UINT32 mInBuf;\r
-\r
- UINT16 mBitCount;\r
- UINT32 mBitBuf;\r
- UINT32 mSubBitBuf;\r
- UINT16 mBlockSize;\r
- UINT32 mCompSize;\r
- UINT32 mOrigSize;\r
-\r
- UINT16 mBadTableFlag;\r
-\r
- UINT16 mLeft[2 * NC - 1];\r
- UINT16 mRight[2 * NC - 1];\r
- UINT8 mCLen[NC];\r
- UINT8 mPTLen[NPT];\r
- UINT16 mCTable[4096];\r
- UINT16 mPTTable[256];\r
+ UINT8 *mSrcBase; // The starting address of compressed data\r
+ UINT8 *mDstBase; // The starting address of decompressed data\r
+ UINT32 mOutBuf;\r
+ UINT32 mInBuf;\r
+\r
+ UINT16 mBitCount;\r
+ UINT32 mBitBuf;\r
+ UINT32 mSubBitBuf;\r
+ UINT16 mBlockSize;\r
+ UINT32 mCompSize;\r
+ UINT32 mOrigSize;\r
+\r
+ UINT16 mBadTableFlag;\r
+\r
+ UINT16 mLeft[2 * NC - 1];\r
+ UINT16 mRight[2 * NC - 1];\r
+ UINT8 mCLen[NC];\r
+ UINT8 mPTLen[NPT];\r
+ UINT16 mCTable[4096];\r
+ UINT16 mPTTable[256];\r
\r
///\r
/// The length of the field 'Position Set Code Length Array Size' in Block Header.\r
/// For UEFI 2.0 de/compression algorithm, mPBit = 4.\r
/// For Tiano de/compression algorithm, mPBit = 5.\r
///\r
- UINT8 mPBit;\r
+ UINT8 mPBit;\r
} SCRATCH_DATA;\r
\r
/**\r
IN OUT VOID *Scratch,\r
IN UINT32 Version\r
);\r
+\r
#endif\r
\r
if (IS_SECTION2 (InputSection)) {\r
if (!CompareGuid (\r
- &gTianoCustomDecompressGuid,\r
- &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid))) {\r
+ &gTianoCustomDecompressGuid,\r
+ &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid)\r
+ ))\r
+ {\r
return RETURN_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Get guid attribute of guid section.\r
//\r
- *SectionAttribute = ((EFI_GUID_DEFINED_SECTION2 *) InputSection)->Attributes;\r
+ *SectionAttribute = ((EFI_GUID_DEFINED_SECTION2 *)InputSection)->Attributes;\r
\r
//\r
// Call Tiano GetInfo to get the required size info.\r
//\r
return UefiDecompressGetInfo (\r
- (UINT8 *) InputSection + ((EFI_GUID_DEFINED_SECTION2 *) InputSection)->DataOffset,\r
- SECTION2_SIZE (InputSection) - ((EFI_GUID_DEFINED_SECTION2 *) InputSection)->DataOffset,\r
+ (UINT8 *)InputSection + ((EFI_GUID_DEFINED_SECTION2 *)InputSection)->DataOffset,\r
+ SECTION2_SIZE (InputSection) - ((EFI_GUID_DEFINED_SECTION2 *)InputSection)->DataOffset,\r
OutputBufferSize,\r
ScratchBufferSize\r
);\r
} else {\r
if (!CompareGuid (\r
- &gTianoCustomDecompressGuid,\r
- &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid))) {\r
+ &gTianoCustomDecompressGuid,\r
+ &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid)\r
+ ))\r
+ {\r
return RETURN_INVALID_PARAMETER;\r
}\r
+\r
//\r
// Get guid attribute of guid section.\r
//\r
- *SectionAttribute = ((EFI_GUID_DEFINED_SECTION *) InputSection)->Attributes;\r
+ *SectionAttribute = ((EFI_GUID_DEFINED_SECTION *)InputSection)->Attributes;\r
\r
//\r
// Call Tiano GetInfo to get the required size info.\r
//\r
return UefiDecompressGetInfo (\r
- (UINT8 *) InputSection + ((EFI_GUID_DEFINED_SECTION *) InputSection)->DataOffset,\r
- SECTION_SIZE (InputSection) - ((EFI_GUID_DEFINED_SECTION *) InputSection)->DataOffset,\r
+ (UINT8 *)InputSection + ((EFI_GUID_DEFINED_SECTION *)InputSection)->DataOffset,\r
+ SECTION_SIZE (InputSection) - ((EFI_GUID_DEFINED_SECTION *)InputSection)->DataOffset,\r
OutputBufferSize,\r
ScratchBufferSize\r
);\r
\r
if (IS_SECTION2 (InputSection)) {\r
if (!CompareGuid (\r
- &gTianoCustomDecompressGuid,\r
- &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid))) {\r
+ &gTianoCustomDecompressGuid,\r
+ &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid)\r
+ ))\r
+ {\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
// Call Tiano Decompress to get the raw data\r
//\r
return UefiTianoDecompress (\r
- (UINT8 *) InputSection + ((EFI_GUID_DEFINED_SECTION2 *) InputSection)->DataOffset,\r
+ (UINT8 *)InputSection + ((EFI_GUID_DEFINED_SECTION2 *)InputSection)->DataOffset,\r
*OutputBuffer,\r
ScratchBuffer,\r
2\r
- );\r
+ );\r
} else {\r
if (!CompareGuid (\r
- &gTianoCustomDecompressGuid,\r
- &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid))) {\r
+ &gTianoCustomDecompressGuid,\r
+ &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid)\r
+ ))\r
+ {\r
return RETURN_INVALID_PARAMETER;\r
}\r
\r
// Call Tiano Decompress to get the raw data\r
//\r
return UefiTianoDecompress (\r
- (UINT8 *) InputSection + ((EFI_GUID_DEFINED_SECTION *) InputSection)->DataOffset,\r
+ (UINT8 *)InputSection + ((EFI_GUID_DEFINED_SECTION *)InputSection)->DataOffset,\r
*OutputBuffer,\r
ScratchBuffer,\r
2\r
- );\r
+ );\r
}\r
}\r
\r
EFIAPI\r
TianoDecompressLibConstructor (\r
VOID\r
-)\r
+ )\r
{\r
return ExtractGuidedSectionRegisterHandlers (\r
- &gTianoCustomDecompressGuid,\r
- TianoDecompressGetInfo,\r
- TianoDecompress\r
- );\r
+ &gTianoCustomDecompressGuid,\r
+ TianoDecompressGetInfo,\r
+ TianoDecompress\r
+ );\r
}\r
\r
**/\r
\r
-\r
#include <PiDxe.h>\r
\r
-\r
#include <Library/DxeCoreEntryPoint.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseLib.h>\r
//\r
// Cache copy of HobList pointer.\r
//\r
-VOID *gHobList = NULL;\r
+VOID *gHobList = NULL;\r
\r
/**\r
The entry point of PE/COFF Image for the DXE Core.\r
//\r
// Should never return\r
//\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
VOID *\r
EFIAPI\r
GetNextHob (\r
- IN UINT16 Type,\r
- IN CONST VOID *HobStart\r
+ IN UINT16 Type,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS Hob;\r
\r
ASSERT (HobStart != NULL);\r
\r
- Hob.Raw = (UINT8 *) HobStart;\r
+ Hob.Raw = (UINT8 *)HobStart;\r
//\r
// Parse the HOB list until end of list or matching type is found.\r
//\r
if (Hob.Header->HobType == Type) {\r
return Hob.Raw;\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
}\r
+\r
return NULL;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstHob (\r
- IN UINT16 Type\r
+ IN UINT16 Type\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextHob (Type, HobList);\r
VOID *\r
EFIAPI\r
GetNextGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN CONST VOID *HobStart\r
+ IN CONST EFI_GUID *Guid,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS GuidHob;\r
\r
- GuidHob.Raw = (UINT8 *) HobStart;\r
+ GuidHob.Raw = (UINT8 *)HobStart;\r
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {\r
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {\r
break;\r
}\r
+\r
GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
}\r
+\r
return GuidHob.Raw;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstGuidHob (\r
- IN CONST EFI_GUID *Guid\r
+ IN CONST EFI_GUID *Guid\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextGuidHob (Guid, HobList);\r
VOID\r
)\r
{\r
- EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
\r
- HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();\r
+ HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *)GetHobList ();\r
\r
- return HandOffHob->BootMode;\r
+ return HandOffHob->BootMode;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
BuildModuleHob (\r
- IN CONST EFI_GUID *ModuleName,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
- IN UINT64 ModuleLength,\r
- IN EFI_PHYSICAL_ADDRESS EntryPoint\r
+ IN CONST EFI_GUID *ModuleName,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
+ IN UINT64 ModuleLength,\r
+ IN EFI_PHYSICAL_ADDRESS EntryPoint\r
)\r
{\r
//\r
VOID *\r
EFIAPI\r
BuildGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN DataLength\r
)\r
{\r
//\r
VOID *\r
EFIAPI\r
BuildGuidDataHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN VOID *Data,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN VOID *Data,\r
+ IN UINTN DataLength\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildFvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildFv2Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN CONST EFI_GUID *FvName,\r
- IN CONST EFI_GUID *FileName\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GUID *FvName,\r
+ IN CONST EFI_GUID *FileName\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
BuildFv3Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT32 AuthenticationStatus,\r
- IN BOOLEAN ExtractedFv,\r
- IN CONST EFI_GUID *FvName OPTIONAL,\r
- IN CONST EFI_GUID *FileName OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT32 AuthenticationStatus,\r
+ IN BOOLEAN ExtractedFv,\r
+ IN CONST EFI_GUID *FvName OPTIONAL,\r
+ IN CONST EFI_GUID *FileName OPTIONAL\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
BuildCvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildCpuHob (\r
- IN UINT8 SizeOfMemorySpace,\r
- IN UINT8 SizeOfIoSpace\r
+ IN UINT8 SizeOfMemorySpace,\r
+ IN UINT8 SizeOfIoSpace\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildStackHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildBspStoreHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildMemoryAllocationHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
//\r
#include <Library/ExtractGuidedSectionLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
-#define EXTRACT_HANDLER_TABLE_SIZE 0x10\r
+#define EXTRACT_HANDLER_TABLE_SIZE 0x10\r
\r
-UINT32 mNumberOfExtractHandler = 0;\r
-UINT32 mMaxNumberOfExtractHandler = 0;\r
+UINT32 mNumberOfExtractHandler = 0;\r
+UINT32 mMaxNumberOfExtractHandler = 0;\r
\r
-GUID *mExtractHandlerGuidTable = NULL;\r
-EXTRACT_GUIDED_SECTION_DECODE_HANDLER *mExtractDecodeHandlerTable = NULL;\r
-EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *mExtractGetInfoHandlerTable = NULL;\r
+GUID *mExtractHandlerGuidTable = NULL;\r
+EXTRACT_GUIDED_SECTION_DECODE_HANDLER *mExtractDecodeHandlerTable = NULL;\r
+EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *mExtractGetInfoHandlerTable = NULL;\r
\r
/**\r
Reallocates more global memory to store the registered guid and Handler list.\r
mMaxNumberOfExtractHandler * sizeof (GUID),\r
(mMaxNumberOfExtractHandler + EXTRACT_HANDLER_TABLE_SIZE) * sizeof (GUID),\r
mExtractHandlerGuidTable\r
- );\r
+ );\r
\r
if (mExtractHandlerGuidTable == NULL) {\r
goto Done;\r
// Reallocate memory for Decode handler Table\r
//\r
mExtractDecodeHandlerTable = ReallocatePool (\r
- mMaxNumberOfExtractHandler * sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER),\r
- (mMaxNumberOfExtractHandler + EXTRACT_HANDLER_TABLE_SIZE) * sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER),\r
- mExtractDecodeHandlerTable\r
- );\r
+ mMaxNumberOfExtractHandler * sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER),\r
+ (mMaxNumberOfExtractHandler + EXTRACT_HANDLER_TABLE_SIZE) * sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER),\r
+ mExtractDecodeHandlerTable\r
+ );\r
\r
if (mExtractDecodeHandlerTable == NULL) {\r
goto Done;\r
// Reallocate memory for GetInfo handler Table\r
//\r
mExtractGetInfoHandlerTable = ReallocatePool (\r
- mMaxNumberOfExtractHandler * sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER),\r
- (mMaxNumberOfExtractHandler + EXTRACT_HANDLER_TABLE_SIZE) * sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER),\r
- mExtractGetInfoHandlerTable\r
- );\r
+ mMaxNumberOfExtractHandler * sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER),\r
+ (mMaxNumberOfExtractHandler + EXTRACT_HANDLER_TABLE_SIZE) * sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER),\r
+ mExtractGetInfoHandlerTable\r
+ );\r
\r
if (mExtractGetInfoHandlerTable == NULL) {\r
goto Done;\r
if (mExtractHandlerGuidTable != NULL) {\r
FreePool (mExtractHandlerGuidTable);\r
}\r
+\r
if (mExtractDecodeHandlerTable != NULL) {\r
FreePool (mExtractDecodeHandlerTable);\r
}\r
+\r
if (mExtractGetInfoHandlerTable != NULL) {\r
FreePool (mExtractGetInfoHandlerTable);\r
}\r
\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
+\r
/**\r
Constructor allocates the global memory to store the registered guid and Handler list.\r
\r
IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler\r
)\r
{\r
- UINT32 Index;\r
- VOID *GuidData;\r
+ UINT32 Index;\r
+ VOID *GuidData;\r
\r
//\r
// Check input parameter.\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
- for (Index = 0; Index < mNumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < mNumberOfExtractHandler; Index++) {\r
if (CompareGuid (&mExtractHandlerGuidTable[Index], SectionGuid)) {\r
//\r
// If the guided handler has been registered before, only update its handler.\r
//\r
- mExtractDecodeHandlerTable [Index] = DecodeHandler;\r
- mExtractGetInfoHandlerTable [Index] = GetInfoHandler;\r
+ mExtractDecodeHandlerTable[Index] = DecodeHandler;\r
+ mExtractGetInfoHandlerTable[Index] = GetInfoHandler;\r
return RETURN_SUCCESS;\r
}\r
}\r
//\r
// Register new Handler and guid value.\r
//\r
- CopyGuid (&mExtractHandlerGuidTable [mNumberOfExtractHandler], SectionGuid);\r
- mExtractDecodeHandlerTable [mNumberOfExtractHandler] = DecodeHandler;\r
- mExtractGetInfoHandlerTable [mNumberOfExtractHandler++] = GetInfoHandler;\r
+ CopyGuid (&mExtractHandlerGuidTable[mNumberOfExtractHandler], SectionGuid);\r
+ mExtractDecodeHandlerTable[mNumberOfExtractHandler] = DecodeHandler;\r
+ mExtractGetInfoHandlerTable[mNumberOfExtractHandler++] = GetInfoHandler;\r
\r
//\r
// Install the Guided Section GUID configuration table to record the GUID itself.\r
// Then the content of the configuration table buffer will be the same as the GUID value itself.\r
//\r
- GuidData = AllocateCopyPool (sizeof (GUID), (VOID *) SectionGuid);\r
+ GuidData = AllocateCopyPool (sizeof (GUID), (VOID *)SectionGuid);\r
if (GuidData != NULL) {\r
- gBS->InstallConfigurationTable ((EFI_GUID *) SectionGuid, GuidData);\r
+ gBS->InstallConfigurationTable ((EFI_GUID *)SectionGuid, GuidData);\r
}\r
\r
return RETURN_SUCCESS;\r
OUT UINT16 *SectionAttribute\r
)\r
{\r
- UINT32 Index;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
ASSERT (InputSection != NULL);\r
ASSERT (OutputBufferSize != NULL);\r
ASSERT (SectionAttribute != NULL);\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
- for (Index = 0; Index < mNumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < mNumberOfExtractHandler; Index++) {\r
if (CompareGuid (&mExtractHandlerGuidTable[Index], SectionDefinitionGuid)) {\r
//\r
// Call the match handler to getinfo for the input section data.\r
//\r
- return mExtractGetInfoHandlerTable [Index] (\r
- InputSection,\r
- OutputBufferSize,\r
- ScratchBufferSize,\r
- SectionAttribute\r
- );\r
+ return mExtractGetInfoHandlerTable[Index](\r
+ InputSection,\r
+ OutputBufferSize,\r
+ ScratchBufferSize,\r
+ SectionAttribute\r
+ );\r
}\r
}\r
\r
OUT UINT32 *AuthenticationStatus\r
)\r
{\r
- UINT32 Index;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
//\r
// Check the input parameters\r
ASSERT (AuthenticationStatus != NULL);\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered extract handler for the input guided section.\r
//\r
- for (Index = 0; Index < mNumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < mNumberOfExtractHandler; Index++) {\r
if (CompareGuid (&mExtractHandlerGuidTable[Index], SectionDefinitionGuid)) {\r
//\r
// Call the match handler to extract raw data for the input section data.\r
//\r
- return mExtractDecodeHandlerTable [Index] (\r
- InputSection,\r
- OutputBuffer,\r
- ScratchBuffer,\r
- AuthenticationStatus\r
- );\r
+ return mExtractDecodeHandlerTable[Index](\r
+ InputSection,\r
+ OutputBuffer,\r
+ ScratchBuffer,\r
+ AuthenticationStatus\r
+ );\r
}\r
}\r
\r
OUT EXTRACT_GUIDED_SECTION_DECODE_HANDLER *DecodeHandler OPTIONAL\r
)\r
{\r
- UINT32 Index;\r
+ UINT32 Index;\r
\r
//\r
// Check input parameter.\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
- for (Index = 0; Index < mNumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < mNumberOfExtractHandler; Index++) {\r
if (CompareGuid (&mExtractHandlerGuidTable[Index], SectionGuid)) {\r
-\r
//\r
// If the guided handler has been registered before, then return the registered handlers.\r
//\r
if (GetInfoHandler != NULL) {\r
*GetInfoHandler = mExtractGetInfoHandlerTable[Index];\r
}\r
+\r
if (DecodeHandler != NULL) {\r
*DecodeHandler = mExtractDecodeHandlerTable[Index];\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
}\r
+\r
return RETURN_NOT_FOUND;\r
}\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mHobList != NULL);\r
}\r
+\r
return mHobList;\r
}\r
\r
VOID *\r
EFIAPI\r
GetNextHob (\r
- IN UINT16 Type,\r
- IN CONST VOID *HobStart\r
+ IN UINT16 Type,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS Hob;\r
\r
ASSERT (HobStart != NULL);\r
\r
- Hob.Raw = (UINT8 *) HobStart;\r
+ Hob.Raw = (UINT8 *)HobStart;\r
//\r
// Parse the HOB list until end of list or matching type is found.\r
//\r
if (Hob.Header->HobType == Type) {\r
return Hob.Raw;\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
}\r
+\r
return NULL;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstHob (\r
- IN UINT16 Type\r
+ IN UINT16 Type\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextHob (Type, HobList);\r
VOID *\r
EFIAPI\r
GetNextGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN CONST VOID *HobStart\r
+ IN CONST EFI_GUID *Guid,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS GuidHob;\r
\r
- GuidHob.Raw = (UINT8 *) HobStart;\r
+ GuidHob.Raw = (UINT8 *)HobStart;\r
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {\r
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {\r
break;\r
}\r
+\r
GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
}\r
+\r
return GuidHob.Raw;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstGuidHob (\r
- IN CONST EFI_GUID *Guid\r
+ IN CONST EFI_GUID *Guid\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextGuidHob (Guid, HobList);\r
VOID\r
)\r
{\r
- EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
+ EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;\r
\r
- HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();\r
+ HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *)GetHobList ();\r
\r
- return HandOffHob->BootMode;\r
+ return HandOffHob->BootMode;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
BuildModuleHob (\r
- IN CONST EFI_GUID *ModuleName,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
- IN UINT64 ModuleLength,\r
- IN EFI_PHYSICAL_ADDRESS EntryPoint\r
+ IN CONST EFI_GUID *ModuleName,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
+ IN UINT64 ModuleLength,\r
+ IN EFI_PHYSICAL_ADDRESS EntryPoint\r
)\r
{\r
//\r
VOID *\r
EFIAPI\r
BuildGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN DataLength\r
)\r
{\r
//\r
VOID *\r
EFIAPI\r
BuildGuidDataHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN VOID *Data,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN VOID *Data,\r
+ IN UINTN DataLength\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildFvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildFv2Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN CONST EFI_GUID *FvName,\r
- IN CONST EFI_GUID *FileName\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GUID *FvName,\r
+ IN CONST EFI_GUID *FileName\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
BuildFv3Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT32 AuthenticationStatus,\r
- IN BOOLEAN ExtractedFv,\r
- IN CONST EFI_GUID *FvName OPTIONAL,\r
- IN CONST EFI_GUID *FileName OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT32 AuthenticationStatus,\r
+ IN BOOLEAN ExtractedFv,\r
+ IN CONST EFI_GUID *FvName OPTIONAL,\r
+ IN CONST EFI_GUID *FileName OPTIONAL\r
)\r
{\r
ASSERT (FALSE);\r
VOID\r
EFIAPI\r
BuildCvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildCpuHob (\r
- IN UINT8 SizeOfMemorySpace,\r
- IN UINT8 SizeOfIoSpace\r
+ IN UINT8 SizeOfMemorySpace,\r
+ IN UINT8 SizeOfIoSpace\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildStackHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildBspStoreHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
BuildMemoryAllocationHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
//\r
if ((This == NULL) || (InformationBlock == NULL) || (InformationBlockSize == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
if (!CompareGuid (InformationType, &gAdapterInfoPlatformSecurityGuid)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- HstiAip = HSTI_AIP_PRIVATE_DATA_FROM_THIS(This);\r
+ HstiAip = HSTI_AIP_PRIVATE_DATA_FROM_THIS (This);\r
\r
*InformationBlock = AllocateCopyPool (HstiAip->HstiSize, HstiAip->Hsti);\r
if (*InformationBlock == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
*InformationBlockSize = HstiAip->HstiSize;\r
return EFI_SUCCESS;\r
}\r
if ((This == NULL) || (InformationBlock == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
if (!CompareGuid (InformationType, &gAdapterInfoPlatformSecurityGuid)) {\r
return EFI_UNSUPPORTED;\r
}\r
return EFI_VOLUME_CORRUPTED;\r
}\r
\r
- HstiAip = HSTI_AIP_PRIVATE_DATA_FROM_THIS(This);\r
+ HstiAip = HSTI_AIP_PRIVATE_DATA_FROM_THIS (This);\r
\r
if (InformationBlockSize > HstiAip->HstiMaxSize) {\r
NewHsti = AllocateZeroPool (InformationBlockSize);\r
if (NewHsti == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
FreePool (HstiAip->Hsti);\r
- HstiAip->Hsti = NewHsti;\r
- HstiAip->HstiSize = 0;\r
+ HstiAip->Hsti = NewHsti;\r
+ HstiAip->HstiSize = 0;\r
HstiAip->HstiMaxSize = InformationBlockSize;\r
}\r
\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- *InfoTypesBuffer = AllocateCopyPool (sizeof(gAdapterInfoPlatformSecurityGuid), &gAdapterInfoPlatformSecurityGuid);\r
+ *InfoTypesBuffer = AllocateCopyPool (sizeof (gAdapterInfoPlatformSecurityGuid), &gAdapterInfoPlatformSecurityGuid);\r
if (*InfoTypesBuffer == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
*InfoTypesBufferCount = 1;\r
\r
return EFI_SUCCESS;\r
}\r
\r
-EFI_ADAPTER_INFORMATION_PROTOCOL mAdapterInformationProtocol = {\r
+EFI_ADAPTER_INFORMATION_PROTOCOL mAdapterInformationProtocol = {\r
HstiAipGetInfo,\r
HstiAipSetInfo,\r
HstiAipGetSupportedTypes,\r
**/\r
VOID *\r
InternalHstiFindAip (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- OUT VOID **HstiData OPTIONAL,\r
- OUT UINTN *HstiSize OPTIONAL\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ OUT VOID **HstiData OPTIONAL,\r
+ OUT UINTN *HstiSize OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
return NULL;\r
}\r
\r
- Hsti = NULL;\r
- Aip = NULL;\r
- InformationBlock = NULL;\r
+ Hsti = NULL;\r
+ Aip = NULL;\r
+ InformationBlock = NULL;\r
InformationBlockSize = 0;\r
for (Index = 0; Index < NoHandles; Index++) {\r
Status = gBS->HandleProtocol (\r
break;\r
}\r
}\r
+\r
FreePool (InfoTypesBuffer);\r
\r
if (AipCandidate == NULL) {\r
//\r
// Check HSTI Role\r
//\r
- Aip = AipCandidate;\r
+ Aip = AipCandidate;\r
Status = Aip->GetInformation (\r
Aip,\r
&gAdapterInfoPlatformSecurityGuid,\r
\r
Hsti = InformationBlock;\r
if ((Hsti->Role == Role) &&\r
- ((ImplementationID == NULL) || (StrCmp (ImplementationID, Hsti->ImplementationID) == 0))) {\r
+ ((ImplementationID == NULL) || (StrCmp (ImplementationID, Hsti->ImplementationID) == 0)))\r
+ {\r
break;\r
} else {\r
Hsti = NULL;\r
continue;\r
}\r
}\r
+\r
FreePool (Handles);\r
\r
if (Hsti == NULL) {\r
if (HstiData != NULL) {\r
*HstiData = InformationBlock;\r
}\r
+\r
if (HstiSize != NULL) {\r
*HstiSize = InformationBlockSize;\r
}\r
+\r
return Aip;\r
}\r
\r
**/\r
BOOLEAN\r
InternalHstiIsValidTable (\r
- IN VOID *HstiData,\r
- IN UINTN HstiSize\r
+ IN VOID *HstiData,\r
+ IN UINTN HstiSize\r
)\r
{\r
ADAPTER_INFO_PLATFORM_SECURITY *Hsti;\r
DEBUG ((DEBUG_ERROR, "HstiData == NULL\n"));\r
return FALSE;\r
}\r
- if (HstiSize < sizeof(ADAPTER_INFO_PLATFORM_SECURITY)) {\r
+\r
+ if (HstiSize < sizeof (ADAPTER_INFO_PLATFORM_SECURITY)) {\r
DEBUG ((DEBUG_ERROR, "HstiSize < sizeof(ADAPTER_INFO_PLATFORM_SECURITY)\n"));\r
return FALSE;\r
}\r
- if (((HstiSize - sizeof(ADAPTER_INFO_PLATFORM_SECURITY)) / 3) < Hsti->SecurityFeaturesSize) {\r
+\r
+ if (((HstiSize - sizeof (ADAPTER_INFO_PLATFORM_SECURITY)) / 3) < Hsti->SecurityFeaturesSize) {\r
DEBUG ((DEBUG_ERROR, "((HstiSize - sizeof(ADAPTER_INFO_PLATFORM_SECURITY)) / 3) < SecurityFeaturesSize\n"));\r
return FALSE;\r
}\r
// Check Role\r
//\r
if ((Hsti->Role < PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE) ||\r
- (Hsti->Role > PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM)) {\r
+ (Hsti->Role > PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM))\r
+ {\r
DEBUG ((DEBUG_ERROR, "Role < PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE ||\n"));\r
DEBUG ((DEBUG_ERROR, "Role > PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM\n"));\r
return FALSE;\r
//\r
// Check ImplementationID\r
//\r
- for (Index = 0; Index < sizeof(Hsti->ImplementationID)/sizeof(Hsti->ImplementationID[0]); Index++) {\r
+ for (Index = 0; Index < sizeof (Hsti->ImplementationID)/sizeof (Hsti->ImplementationID[0]); Index++) {\r
if (Hsti->ImplementationID[Index] == 0) {\r
break;\r
}\r
}\r
- if (Index == sizeof(Hsti->ImplementationID)/sizeof(Hsti->ImplementationID[0])) {\r
+\r
+ if (Index == sizeof (Hsti->ImplementationID)/sizeof (Hsti->ImplementationID[0])) {\r
DEBUG ((DEBUG_ERROR, "ImplementationID has no NUL CHAR\n"));\r
return FALSE;\r
}\r
\r
- ErrorStringSize = HstiSize - sizeof(ADAPTER_INFO_PLATFORM_SECURITY) - Hsti->SecurityFeaturesSize * 3;\r
- ErrorString = (CHAR16 *)((UINTN)Hsti + sizeof(ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 3);\r
+ ErrorStringSize = HstiSize - sizeof (ADAPTER_INFO_PLATFORM_SECURITY) - Hsti->SecurityFeaturesSize * 3;\r
+ ErrorString = (CHAR16 *)((UINTN)Hsti + sizeof (ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 3);\r
\r
//\r
// basic check for ErrorString\r
DEBUG ((DEBUG_ERROR, "ErrorStringSize == 0\n"));\r
return FALSE;\r
}\r
+\r
if ((ErrorStringSize & BIT0) != 0) {\r
DEBUG ((DEBUG_ERROR, "(ErrorStringSize & BIT0) != 0\n"));\r
return FALSE;\r
//\r
// ErrorString might not be CHAR16 aligned.\r
//\r
- CopyMem (&ErrorChar, ErrorString, sizeof(ErrorChar));\r
+ CopyMem (&ErrorChar, ErrorString, sizeof (ErrorChar));\r
for (ErrorStringLength = 0; (ErrorChar != 0) && (ErrorStringLength < (ErrorStringSize/2)); ErrorStringLength++) {\r
ErrorString++;\r
- CopyMem (&ErrorChar, ErrorString, sizeof(ErrorChar));\r
+ CopyMem (&ErrorChar, ErrorString, sizeof (ErrorChar));\r
}\r
\r
//\r
DEBUG ((DEBUG_ERROR, "ErrorString has no NUL CHAR\n"));\r
return FALSE;\r
}\r
+\r
if (ErrorStringLength == (ErrorStringSize/2)) {\r
DEBUG ((DEBUG_ERROR, "ErrorString Length incorrect\n"));\r
return FALSE;\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetTable (\r
- IN VOID *Hsti,\r
- IN UINTN HstiSize\r
+ IN VOID *Hsti,\r
+ IN UINTN HstiSize\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE Handle;\r
- HSTI_AIP_PRIVATE_DATA *HstiAip;\r
- EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
- UINT32 Role;\r
- CHAR16 *ImplementationID;\r
- UINT32 SecurityFeaturesSize;\r
- UINT8 *SecurityFeaturesRequired;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+ HSTI_AIP_PRIVATE_DATA *HstiAip;\r
+ EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
+ UINT32 Role;\r
+ CHAR16 *ImplementationID;\r
+ UINT32 SecurityFeaturesSize;\r
+ UINT8 *SecurityFeaturesRequired;\r
\r
if (!InternalHstiIsValidTable (Hsti, HstiSize)) {\r
return EFI_VOLUME_CORRUPTED;\r
}\r
\r
- Role = ((ADAPTER_INFO_PLATFORM_SECURITY *)Hsti)->Role;\r
+ Role = ((ADAPTER_INFO_PLATFORM_SECURITY *)Hsti)->Role;\r
ImplementationID = ((ADAPTER_INFO_PLATFORM_SECURITY *)Hsti)->ImplementationID;\r
- Aip = InternalHstiFindAip (Role, ImplementationID, NULL, NULL);\r
+ Aip = InternalHstiFindAip (Role, ImplementationID, NULL, NULL);\r
if (Aip != NULL) {\r
return EFI_ALREADY_STARTED;\r
}\r
\r
- HstiAip = AllocateZeroPool (sizeof(HSTI_AIP_PRIVATE_DATA));\r
+ HstiAip = AllocateZeroPool (sizeof (HSTI_AIP_PRIVATE_DATA));\r
if (HstiAip == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
HstiAip->Hsti = AllocateCopyPool (HstiSize, Hsti);\r
if (HstiAip->Hsti == NULL) {\r
FreePool (HstiAip);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
if (Role != PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE) {\r
- SecurityFeaturesRequired = (UINT8 *)HstiAip->Hsti + sizeof(ADAPTER_INFO_PLATFORM_SECURITY);\r
- SecurityFeaturesSize = ((ADAPTER_INFO_PLATFORM_SECURITY *)Hsti)->SecurityFeaturesSize;\r
+ SecurityFeaturesRequired = (UINT8 *)HstiAip->Hsti + sizeof (ADAPTER_INFO_PLATFORM_SECURITY);\r
+ SecurityFeaturesSize = ((ADAPTER_INFO_PLATFORM_SECURITY *)Hsti)->SecurityFeaturesSize;\r
ZeroMem (SecurityFeaturesRequired, SecurityFeaturesSize);\r
}\r
\r
HstiAip->Signature = HSTI_AIP_PRIVATE_SIGNATURE;\r
- CopyMem (&HstiAip->Aip, &mAdapterInformationProtocol, sizeof(EFI_ADAPTER_INFORMATION_PROTOCOL));\r
- HstiAip->HstiSize = HstiSize;\r
+ CopyMem (&HstiAip->Aip, &mAdapterInformationProtocol, sizeof (EFI_ADAPTER_INFORMATION_PROTOCOL));\r
+ HstiAip->HstiSize = HstiSize;\r
HstiAip->HstiMaxSize = HstiSize;\r
\r
Handle = NULL;\r
EFI_STATUS\r
EFIAPI\r
HstiLibGetTable (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- OUT VOID **Hsti,\r
- OUT UINTN *HstiSize\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ OUT VOID **Hsti,\r
+ OUT UINTN *HstiSize\r
)\r
{\r
- EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
+ EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
\r
Aip = InternalHstiFindAip (Role, ImplementationID, Hsti, HstiSize);\r
if (Aip == NULL) {\r
return EFI_NOT_FOUND;\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
**/\r
EFI_STATUS\r
InternalHstiRecordFeaturesVerified (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN UINT32 ByteIndex,\r
- IN UINT8 Bit,\r
- IN BOOLEAN Set\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN UINT32 ByteIndex,\r
+ IN UINT8 Bit,\r
+ IN BOOLEAN Set\r
)\r
{\r
- EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
- ADAPTER_INFO_PLATFORM_SECURITY *Hsti;\r
- UINTN HstiSize;\r
- UINT8 *SecurityFeaturesVerified;\r
- EFI_STATUS Status;\r
+ EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
+ ADAPTER_INFO_PLATFORM_SECURITY *Hsti;\r
+ UINTN HstiSize;\r
+ UINT8 *SecurityFeaturesVerified;\r
+ EFI_STATUS Status;\r
\r
Aip = InternalHstiFindAip (Role, ImplementationID, (VOID **)&Hsti, &HstiSize);\r
if (Aip == NULL) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- SecurityFeaturesVerified = (UINT8 *)((UINTN)Hsti + sizeof(ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 2);\r
+ SecurityFeaturesVerified = (UINT8 *)((UINTN)Hsti + sizeof (ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 2);\r
\r
if (Set) {\r
SecurityFeaturesVerified[ByteIndex] = (UINT8)(SecurityFeaturesVerified[ByteIndex] | (Bit));\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetFeaturesVerified (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN UINT32 ByteIndex,\r
- IN UINT8 BitMask\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN UINT32 ByteIndex,\r
+ IN UINT8 BitMask\r
)\r
{\r
return InternalHstiRecordFeaturesVerified (\r
EFI_STATUS\r
EFIAPI\r
HstiLibClearFeaturesVerified (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN UINT32 ByteIndex,\r
- IN UINT8 BitMask\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN UINT32 ByteIndex,\r
+ IN UINT8 BitMask\r
)\r
{\r
return InternalHstiRecordFeaturesVerified (\r
**/\r
EFI_STATUS\r
InternalHstiRecordErrorString (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN CHAR16 *ErrorString,\r
- IN BOOLEAN Append\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN CHAR16 *ErrorString,\r
+ IN BOOLEAN Append\r
)\r
{\r
- EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
- ADAPTER_INFO_PLATFORM_SECURITY *Hsti;\r
- UINTN HstiSize;\r
- UINTN StringSize;\r
- VOID *NewHsti;\r
- UINTN NewHstiSize;\r
- UINTN Offset;\r
- EFI_STATUS Status;\r
+ EFI_ADAPTER_INFORMATION_PROTOCOL *Aip;\r
+ ADAPTER_INFO_PLATFORM_SECURITY *Hsti;\r
+ UINTN HstiSize;\r
+ UINTN StringSize;\r
+ VOID *NewHsti;\r
+ UINTN NewHstiSize;\r
+ UINTN Offset;\r
+ EFI_STATUS Status;\r
\r
Aip = InternalHstiFindAip (Role, ImplementationID, (VOID **)&Hsti, &HstiSize);\r
if (Aip == NULL) {\r
}\r
\r
if (Append) {\r
- Offset = HstiSize - sizeof(CHAR16);\r
+ Offset = HstiSize - sizeof (CHAR16);\r
} else {\r
- Offset = sizeof(ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 3;\r
+ Offset = sizeof (ADAPTER_INFO_PLATFORM_SECURITY) + Hsti->SecurityFeaturesSize * 3;\r
}\r
+\r
StringSize = StrSize (ErrorString);\r
\r
NewHstiSize = Offset + StringSize;\r
- NewHsti = AllocatePool (NewHstiSize);\r
+ NewHsti = AllocatePool (NewHstiSize);\r
if (NewHsti == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
EFI_STATUS\r
EFIAPI\r
HstiLibAppendErrorString (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN CHAR16 *ErrorString\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN CHAR16 *ErrorString\r
)\r
{\r
return InternalHstiRecordErrorString (\r
EFI_STATUS\r
EFIAPI\r
HstiLibSetErrorString (\r
- IN UINT32 Role,\r
- IN CHAR16 *ImplementationID OPTIONAL,\r
- IN CHAR16 *ErrorString\r
+ IN UINT32 Role,\r
+ IN CHAR16 *ImplementationID OPTIONAL,\r
+ IN CHAR16 *ErrorString\r
)\r
{\r
return InternalHstiRecordErrorString (\r
#define HSTI_AIP_PRIVATE_SIGNATURE SIGNATURE_32('H', 'S', 'T', 'I')\r
\r
typedef struct {\r
- UINT32 Signature;\r
- LIST_ENTRY Link;\r
- EFI_ADAPTER_INFORMATION_PROTOCOL Aip;\r
- VOID *Hsti;\r
- UINTN HstiSize;\r
- UINTN HstiMaxSize;\r
+ UINT32 Signature;\r
+ LIST_ENTRY Link;\r
+ EFI_ADAPTER_INFORMATION_PROTOCOL Aip;\r
+ VOID *Hsti;\r
+ UINTN HstiSize;\r
+ UINTN HstiMaxSize;\r
} HSTI_AIP_PRIVATE_DATA;\r
\r
#define HSTI_AIP_PRIVATE_DATA_FROM_THIS(a) \\r
\r
#define HSTI_DEFAULT_ERROR_STRING_LEN 255\r
\r
-extern EFI_ADAPTER_INFORMATION_PROTOCOL mAdapterInformationProtocol;\r
+extern EFI_ADAPTER_INFORMATION_PROTOCOL mAdapterInformationProtocol;\r
\r
/**\r
Return if input HSTI data follows HSTI specification.\r
**/\r
BOOLEAN\r
InternalHstiIsValidTable (\r
- IN VOID *HstiData,\r
- IN UINTN HstiSize\r
+ IN VOID *HstiData,\r
+ IN UINTN HstiSize\r
);\r
\r
#endif\r
#include <Library/DebugLib.h>\r
#include <Library/BaseLib.h>\r
\r
-\r
/**\r
Reads registers in the EFI CPU I/O space.\r
\r
UINT64\r
EFIAPI\r
MmioReadWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
+ IN UINTN Address,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioWriteWorker (\r
- IN UINTN Address,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Address,\r
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Data\r
);\r
\r
#endif\r
\r
**/\r
\r
-\r
#include "DxeCpuIo2LibInternal.h"\r
\r
/**\r
UINT8\r
EFIAPI\r
IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+ return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT16\r
EFIAPI\r
IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+ return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT32\r
EFIAPI\r
IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
UINT32\r
EFIAPI\r
IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
UINT32\r
EFIAPI\r
IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT64\r
EFIAPI\r
IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
UINT64\r
EFIAPI\r
IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
UINT64\r
EFIAPI\r
IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT8\r
EFIAPI\r
MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT16\r
EFIAPI\r
MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT32\r
EFIAPI\r
MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT64\r
EFIAPI\r
MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
UINT64\r
EFIAPI\r
MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
UINT64\r
EFIAPI\r
MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
EFI_STATUS\r
EFIAPI\r
IoLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
\r
- Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **) &mCpuIo);\r
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);\r
ASSERT_EFI_ERROR (Status);\r
\r
return Status;\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
//\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
//\r
UINT8 *\r
EFIAPI\r
MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ReturnBuffer = Buffer;\r
\r
UINT16 *\r
EFIAPI\r
MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead16 (StartAddress);\r
+ *(Buffer++) = MmioRead16 (StartAddress);\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
UINT32 *\r
EFIAPI\r
MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead32 (StartAddress);\r
+ *(Buffer++) = MmioRead32 (StartAddress);\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead64 (StartAddress);\r
+ *(Buffer++) = MmioRead64 (StartAddress);\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 8-bit access.\r
\r
UINT8 *\r
EFIAPI\r
MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
)\r
{\r
- VOID* ReturnBuffer;\r
+ VOID *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- ReturnBuffer = (UINT8 *) Buffer;\r
+ ReturnBuffer = (UINT8 *)Buffer;\r
\r
while (Length-- > 0) {\r
- MmioWrite8 (StartAddress++, *(Buffer++));\r
+ MmioWrite8 (StartAddress++, *(Buffer++));\r
}\r
\r
return ReturnBuffer;\r
-\r
}\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT16 *) Buffer;\r
+ ReturnBuffer = (UINT16 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite16 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 32-bit access.\r
\r
UINT32 *\r
EFIAPI\r
MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT32 *) Buffer;\r
+ ReturnBuffer = (UINT32 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite32 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT64 *) Buffer;\r
+ ReturnBuffer = (UINT64 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite64 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
-\r
\r
**/\r
\r
-\r
#include <PiDxe.h>\r
\r
#include <Protocol/Pcd.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/BaseMemoryLib.h>\r
\r
-PCD_PROTOCOL *mPcd = NULL;\r
-EFI_PCD_PROTOCOL *mPiPcd = NULL;\r
-GET_PCD_INFO_PROTOCOL *mPcdInfo = NULL;\r
-EFI_GET_PCD_INFO_PROTOCOL *mPiPcdInfo = NULL;\r
+PCD_PROTOCOL *mPcd = NULL;\r
+EFI_PCD_PROTOCOL *mPiPcd = NULL;\r
+GET_PCD_INFO_PROTOCOL *mPcdInfo = NULL;\r
+EFI_GET_PCD_INFO_PROTOCOL *mPiPcdInfo = NULL;\r
\r
/**\r
Retrieves the PI PCD protocol from the handle database.\r
// PI Pcd protocol defined in PI 1.2 vol3 should be installed before the module\r
// access DynamicEx type PCD.\r
//\r
- Status = gBS->LocateProtocol (&gEfiPcdProtocolGuid, NULL, (VOID **) &mPiPcd);\r
+ Status = gBS->LocateProtocol (&gEfiPcdProtocolGuid, NULL, (VOID **)&mPiPcd);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPiPcd != NULL);\r
}\r
+\r
return mPiPcd;\r
}\r
\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPcd != NULL);\r
}\r
+\r
return mPcd;\r
}\r
\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPiPcdInfo != NULL);\r
}\r
+\r
return mPiPcdInfo;\r
}\r
\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPcdInfo != NULL);\r
}\r
+\r
return mPcdInfo;\r
}\r
\r
UINTN\r
EFIAPI\r
LibPcdSetSku (\r
- IN UINTN SkuId\r
+ IN UINTN SkuId\r
)\r
{\r
- GetPcdProtocol()->SetSku (SkuId);\r
+ GetPcdProtocol ()->SetSku (SkuId);\r
\r
return SkuId;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGet8 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->Get8 (TokenNumber);\r
+ return GetPcdProtocol ()->Get8 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGet16 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->Get16 (TokenNumber);\r
+ return GetPcdProtocol ()->Get16 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT32\r
EFIAPI\r
LibPcdGet32 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->Get32 (TokenNumber);\r
+ return GetPcdProtocol ()->Get32 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGet64 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->Get64 (TokenNumber);\r
+ return GetPcdProtocol ()->Get64 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetPtr (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->GetPtr (TokenNumber);\r
+ return GetPcdProtocol ()->GetPtr (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetBool (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->GetBool (TokenNumber);\r
+ return GetPcdProtocol ()->GetBool (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetSize (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
- return GetPcdProtocol()->GetSize (TokenNumber);\r
+ return GetPcdProtocol ()->GetSize (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGetEx8 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Get8 (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->Get8 (Guid, TokenNumber);\r
}\r
\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGetEx16 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Get16 (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->Get16 (Guid, TokenNumber);\r
}\r
\r
-\r
/**\r
Returns the 32-bit value for the token specified by TokenNumber and Guid.\r
If Guid is NULL, then ASSERT().\r
UINT32\r
EFIAPI\r
LibPcdGetEx32 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Get32 (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->Get32 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGetEx64 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Get64 (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->Get64 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetExPtr (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->GetPtr (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->GetPtr (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetExBool (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->GetBool (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->GetBool (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetExSize (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->GetSize (Guid, TokenNumber);\r
+ return GetPiPcdProtocol ()->GetSize (Guid, TokenNumber);\r
}\r
\r
-\r
/**\r
This function provides a means by which to set a value for a given PCD token.\r
\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet8S (\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
- return GetPcdProtocol()->Set8 (TokenNumber, Value);\r
+ return GetPcdProtocol ()->Set8 (TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet16S (\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
- return GetPcdProtocol()->Set16 (TokenNumber, Value);\r
+ return GetPcdProtocol ()->Set16 (TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet32S (\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
- return GetPcdProtocol()->Set32 (TokenNumber, Value);\r
+ return GetPcdProtocol ()->Set32 (TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet64S (\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
- return GetPcdProtocol()->Set64 (TokenNumber, Value);\r
+ return GetPcdProtocol ()->Set64 (TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetPtrS (\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (SizeOfBuffer != NULL);\r
ASSERT (Buffer != NULL);\r
}\r
\r
- return GetPcdProtocol()->SetPtr (TokenNumber, SizeOfBuffer, (VOID *) Buffer);\r
+ return GetPcdProtocol ()->SetPtr (TokenNumber, SizeOfBuffer, (VOID *)Buffer);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetBoolS (\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
- return GetPcdProtocol()->SetBool (TokenNumber, Value);\r
+ return GetPcdProtocol ()->SetBool (TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx8S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Set8 (Guid, TokenNumber, Value);\r
+ return GetPiPcdProtocol ()->Set8 (Guid, TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx16S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Set16 (Guid, TokenNumber, Value);\r
+ return GetPiPcdProtocol ()->Set16 (Guid, TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx32S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Set32 (Guid, TokenNumber, Value);\r
+ return GetPiPcdProtocol ()->Set32 (Guid, TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx64S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->Set64 (Guid, TokenNumber, Value);\r
+ return GetPiPcdProtocol ()->Set64 (Guid, TokenNumber, Value);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExPtrS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN VOID *Buffer\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (Guid != NULL);\r
ASSERT (Buffer != NULL);\r
}\r
\r
- return GetPiPcdProtocol()->SetPtr (Guid, TokenNumber, SizeOfBuffer, Buffer);\r
+ return GetPiPcdProtocol ()->SetPtr (Guid, TokenNumber, SizeOfBuffer, Buffer);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExBoolS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
\r
- return GetPiPcdProtocol()->SetBool (Guid, TokenNumber, Value);\r
+ return GetPiPcdProtocol ()->SetBool (Guid, TokenNumber, Value);\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
LibPcdCallbackOnSet (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT (NotificationFunction != NULL);\r
\r
- Status = GetPiPcdProtocol()->CallbackOnSet (Guid, TokenNumber, (EFI_PCD_PROTOCOL_CALLBACK) NotificationFunction);\r
+ Status = GetPiPcdProtocol ()->CallbackOnSet (Guid, TokenNumber, (EFI_PCD_PROTOCOL_CALLBACK)NotificationFunction);\r
ASSERT_EFI_ERROR (Status);\r
\r
return;\r
}\r
\r
-\r
-\r
/**\r
Disable a notification function that was established with LibPcdCallbackonSet().\r
\r
VOID\r
EFIAPI\r
LibPcdCancelCallback (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT (NotificationFunction != NULL);\r
\r
- Status = GetPiPcdProtocol()->CancelCallback (Guid, TokenNumber, (EFI_PCD_PROTOCOL_CALLBACK) NotificationFunction);\r
+ Status = GetPiPcdProtocol ()->CancelCallback (Guid, TokenNumber, (EFI_PCD_PROTOCOL_CALLBACK)NotificationFunction);\r
ASSERT_EFI_ERROR (Status);\r
\r
return;\r
}\r
\r
-\r
-\r
/**\r
Retrieves the next token in a token space.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetNextToken (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = GetPiPcdProtocol()->GetNextToken (Guid, &TokenNumber);\r
+ Status = GetPiPcdProtocol ()->GetNextToken (Guid, &TokenNumber);\r
ASSERT (!EFI_ERROR (Status) || TokenNumber == 0);\r
\r
return TokenNumber;\r
}\r
\r
-\r
-\r
/**\r
Used to retrieve the list of available PCD token space GUIDs.\r
\r
IN CONST GUID *TokenSpaceGuid\r
)\r
{\r
- GetPiPcdProtocol()->GetNextTokenSpace (&TokenSpaceGuid);\r
+ GetPiPcdProtocol ()->GetNextTokenSpace (&TokenSpaceGuid);\r
\r
return (GUID *)TokenSpaceGuid;\r
}\r
\r
-\r
/**\r
Sets a value of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtr (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrS (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Sets a value and size of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtrAndSize (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
*SizeOfPatchVariable = *SizeOfBuffer;\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrAndSizeS (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
VOID\r
EFIAPI\r
LibPcdGetInfo (\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = GetPcdInfoProtocolPointer()->GetInfo (TokenNumber, (EFI_PCD_INFO *) PcdInfo);\r
+ Status = GetPcdInfoProtocolPointer ()->GetInfo (TokenNumber, (EFI_PCD_INFO *)PcdInfo);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
EFIAPI\r
LibPcdGetInfoEx (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = GetPiPcdInfoProtocolPointer()->GetInfo (Guid, TokenNumber, (EFI_PCD_INFO *) PcdInfo);\r
+ Status = GetPiPcdInfoProtocolPointer ()->GetInfo (Guid, TokenNumber, (EFI_PCD_INFO *)PcdInfo);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
)\r
{\r
- return GetPiPcdInfoProtocolPointer()->GetSku ();\r
+ return GetPiPcdInfoProtocolPointer ()->GetSku ();\r
}\r
RngProtocol = NULL;\r
\r
if (Buffer == NULL) {\r
- DEBUG((DEBUG_ERROR, "%a: Buffer == NULL.\n", __FUNCTION__));\r
- return EFI_INVALID_PARAMETER;\r
+ DEBUG ((DEBUG_ERROR, "%a: Buffer == NULL.\n", __FUNCTION__));\r
+ return EFI_INVALID_PARAMETER;\r
}\r
\r
Status = gBS->LocateProtocol (&gEfiRngProtocolGuid, NULL, (VOID **)&RngProtocol);\r
- if (EFI_ERROR (Status) || RngProtocol == NULL) {\r
- DEBUG((DEBUG_ERROR, "%a: Could not locate RNG prototocol, Status = %r\n", __FUNCTION__, Status));\r
- return Status;\r
+ if (EFI_ERROR (Status) || (RngProtocol == NULL)) {\r
+ DEBUG ((DEBUG_ERROR, "%a: Could not locate RNG prototocol, Status = %r\n", __FUNCTION__, Status));\r
+ return Status;\r
}\r
\r
Status = RngProtocol->GetRNG (RngProtocol, &gEfiRngAlgorithmSp80090Ctr256Guid, BufferSize, Buffer);\r
- DEBUG((DEBUG_INFO, "%a: GetRNG algorithm CTR-256 - Status = %r\n", __FUNCTION__, Status));\r
+ DEBUG ((DEBUG_INFO, "%a: GetRNG algorithm CTR-256 - Status = %r\n", __FUNCTION__, Status));\r
if (!EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
Status = RngProtocol->GetRNG (RngProtocol, &gEfiRngAlgorithmSp80090Hmac256Guid, BufferSize, Buffer);\r
- DEBUG((DEBUG_INFO, "%a: GetRNG algorithm HMAC-256 - Status = %r\n", __FUNCTION__, Status));\r
+ DEBUG ((DEBUG_INFO, "%a: GetRNG algorithm HMAC-256 - Status = %r\n", __FUNCTION__, Status));\r
if (!EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
Status = RngProtocol->GetRNG (RngProtocol, &gEfiRngAlgorithmSp80090Hash256Guid, BufferSize, Buffer);\r
- DEBUG((DEBUG_INFO, "%a: GetRNG algorithm Hash-256 - Status = %r\n", __FUNCTION__, Status));\r
+ DEBUG ((DEBUG_INFO, "%a: GetRNG algorithm Hash-256 - Status = %r\n", __FUNCTION__, Status));\r
if (!EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
// If all the other methods have failed, use the default method from the RngProtocol\r
Status = RngProtocol->GetRNG (RngProtocol, NULL, BufferSize, Buffer);\r
- DEBUG((DEBUG_INFO, "%a: GetRNG algorithm Hash-256 - Status = %r\n", __FUNCTION__, Status));\r
+ DEBUG ((DEBUG_INFO, "%a: GetRNG algorithm Hash-256 - Status = %r\n", __FUNCTION__, Status));\r
if (!EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
// If we get to this point, we have failed\r
- DEBUG((DEBUG_ERROR, "%a: GetRNG() failed, staus = %r\n", __FUNCTION__, Status));\r
+ DEBUG ((DEBUG_ERROR, "%a: GetRNG() failed, staus = %r\n", __FUNCTION__, Status));\r
\r
return Status;\r
}// GenerateRandomNumberViaNist800Algorithm()\r
\r
-\r
/**\r
Generates a 16-bit random number.\r
\r
OUT UINT16 *Rand\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- if (Rand == NULL)\r
- {\r
+ if (Rand == NULL) {\r
return FALSE;\r
}\r
\r
- Status = GenerateRandomNumberViaNist800Algorithm ((UINT8 *)Rand, sizeof(UINT16));\r
+ Status = GenerateRandomNumberViaNist800Algorithm ((UINT8 *)Rand, sizeof (UINT16));\r
if (EFI_ERROR (Status)) {\r
return FALSE;\r
}\r
+\r
return TRUE;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber32 (\r
- OUT UINT32 *Rand\r
+ OUT UINT32 *Rand\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (Rand == NULL) {\r
return FALSE;\r
}\r
\r
- Status = GenerateRandomNumberViaNist800Algorithm ((UINT8*)Rand, sizeof(UINT32));\r
+ Status = GenerateRandomNumberViaNist800Algorithm ((UINT8 *)Rand, sizeof (UINT32));\r
if (EFI_ERROR (Status)) {\r
return FALSE;\r
}\r
+\r
return TRUE;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber64 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (Rand == NULL) {\r
return FALSE;\r
}\r
\r
- Status = GenerateRandomNumberViaNist800Algorithm ((UINT8*)Rand, sizeof(UINT64));\r
+ Status = GenerateRandomNumberViaNist800Algorithm ((UINT8 *)Rand, sizeof (UINT64));\r
if (EFI_ERROR (Status)) {\r
return FALSE;\r
}\r
+\r
return TRUE;\r
}\r
\r
BOOLEAN\r
EFIAPI\r
GetRandomNumber128 (\r
- OUT UINT64 *Rand\r
+ OUT UINT64 *Rand\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (Rand == NULL) {\r
return FALSE;\r
}\r
\r
- Status = GenerateRandomNumberViaNist800Algorithm ((UINT8*)Rand, 2 * sizeof(UINT64));\r
+ Status = GenerateRandomNumberViaNist800Algorithm ((UINT8 *)Rand, 2 * sizeof (UINT64));\r
if (EFI_ERROR (Status)) {\r
return FALSE;\r
}\r
+\r
return TRUE;\r
}\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/SerialPortLib.h>\r
\r
-STATIC EFI_EVENT mEfiExitBootServicesEvent;\r
-STATIC BOOLEAN mEfiAtRuntime = FALSE;\r
+STATIC EFI_EVENT mEfiExitBootServicesEvent;\r
+STATIC BOOLEAN mEfiAtRuntime = FALSE;\r
\r
//\r
// Define the maximum debug and assert message length that this library supports\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
/**\r
Set AtRuntime flag as TRUE after ExitBootServices.\r
VOID\r
EFIAPI\r
ExitBootServicesEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
mEfiAtRuntime = TRUE;\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = SerialPortInitialize ();\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- return SystemTable->BootServices->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
- TPL_NOTIFY, ExitBootServicesEvent, NULL,\r
- &mEfiExitBootServicesEvent);\r
+ return SystemTable->BootServices->CreateEvent (\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ ExitBootServicesEvent,\r
+ NULL,\r
+ &mEfiExitBootServicesEvent\r
+ );\r
}\r
\r
/**\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
VA_START (Marker, Format);\r
DebugVPrint (ErrorLevel, Format, Marker);\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
if (mEfiAtRuntime) {\r
return;\r
SerialPortWrite ((UINT8 *)Buffer, AsciiStrLen (Buffer));\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
//\r
// Generate the ASSERT() message in Ascii format\r
//\r
- AsciiSPrint (Buffer, sizeof (Buffer), "ASSERT [%a] %a(%d): %a\n",\r
- gEfiCallerBaseName, FileName, LineNumber, Description);\r
+ AsciiSPrint (\r
+ Buffer,\r
+ sizeof (Buffer),\r
+ "ASSERT [%a] %a(%d): %a\n",\r
+ gEfiCallerBaseName,\r
+ FileName,\r
+ LineNumber,\r
+ Description\r
+ );\r
\r
if (!mEfiAtRuntime) {\r
//\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
//\r
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
\r
**/\r
\r
-\r
#include <PiDxe.h>\r
\r
#include <Guid/EventGroup.h>\r
/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime\r
///\r
typedef struct {\r
- UINTN PhysicalAddress;\r
- UINTN VirtualAddress;\r
+ UINTN PhysicalAddress;\r
+ UINTN VirtualAddress;\r
} PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;\r
\r
///\r
/// Set Virtual Address Map Event\r
///\r
-EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
+EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
\r
///\r
/// Module global that contains the base physical address and size of the PCI Express MMIO range.\r
///\r
-UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
-UINTN mDxeRuntimePciExpressLibPciExpressBaseSize = 0;\r
+UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
+UINTN mDxeRuntimePciExpressLibPciExpressBaseSize = 0;\r
\r
///\r
/// The number of PCI devices that have been registered for runtime access.\r
///\r
-UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
+UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
\r
///\r
/// The table of PCI devices that have been registered for runtime access.\r
///\r
/// The table index of the most recent virtual address lookup.\r
///\r
-UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
-\r
+UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
\r
/**\r
Convert the physical PCI Express MMIO addresses for all registered PCI devices\r
// virtual addresses.\r
//\r
for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
- EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r
+ EfiConvertPointer (0, (VOID **)&(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r
}\r
\r
//\r
// Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r
//\r
- EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);\r
+ EfiConvertPointer (0, (VOID **)&mDxeRuntimePciExpressLibRegistrationTable);\r
}\r
\r
/**\r
//\r
// Cache the physical address of the PCI Express MMIO range into a module global variable\r
//\r
- mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
- mDxeRuntimePciExpressLibPciExpressBaseSize = (UINTN) PcdGet64 (PcdPciExpressBaseSize);\r
+ mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN)PcdGet64 (PcdPciExpressBaseAddress);\r
+ mDxeRuntimePciExpressLibPciExpressBaseSize = (UINTN)PcdGet64 (PcdPciExpressBaseSize);\r
\r
//\r
// Register SetVirtualAddressMap () notify function\r
// Make sure the Address is in MMCONF address space\r
//\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
+ return (UINTN)-1;\r
}\r
\r
//\r
//\r
// No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.\r
//\r
- CpuBreakpoint();\r
+ CpuBreakpoint ();\r
\r
//\r
// Return the physical address\r
//\r
// Make sure Address is valid\r
//\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
\r
//\r
// Make sure the Address is in MMCONF address space\r
if (NewTable == NULL) {\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
- mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r
+\r
+ mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r
mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r
mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress = Address;\r
mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Reads an 8-bit PCI configuration register.\r
\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address);\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioRead8 (GetPciExpressAddress (Address));\r
}\r
\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioWrite8 (GetPciExpressAddress (Address), Value);\r
}\r
\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioOr8 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioAndThenOr8 (\r
GetPciExpressAddress (Address),\r
AndData,\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldRead8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldWrite8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldOr8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldAnd8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
+ return (UINT8)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr8 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioRead16 (GetPciExpressAddress (Address));\r
}\r
\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioWrite16 (GetPciExpressAddress (Address), Value);\r
}\r
\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioOr16 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioAndThenOr16 (\r
GetPciExpressAddress (Address),\r
AndData,\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldRead16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldWrite16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldOr16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldAnd16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
+ return (UINT16)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr16 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioRead32 (GetPciExpressAddress (Address));\r
}\r
\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioWrite32 (GetPciExpressAddress (Address), Value);\r
}\r
\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioOr32 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioAndThenOr32 (\r
GetPciExpressAddress (Address),\r
AndData,\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldRead32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldWrite32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldOr32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldAnd32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
+ return (UINT32)-1;\r
}\r
+\r
return MmioBitFieldAndThenOr32 (\r
GetPciExpressAddress (Address),\r
StartBit,\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
//\r
// Make sure Address is valid\r
// Make sure the Address is in MMCONF address space\r
//\r
if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
+ return (UINTN)-1;\r
}\r
\r
if (Size == 0) {\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Read as many double words as possible\r
//\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r
\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Read the last remaining word if exist\r
//\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
//\r
// Make sure Address is valid\r
// Make sure the Address is in MMCONF address space\r
//\r
if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
+ return (UINTN)-1;\r
}\r
\r
if (Size == 0) {\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
// Write as many double words as possible\r
//\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
// Write the last remaining word if exist\r
//\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
IN UINTN Pages\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PHYSICAL_ADDRESS Memory;\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS Memory;\r
\r
if (Pages == 0) {\r
return NULL;\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
+\r
return (VOID *)(UINTN)Memory;\r
}\r
**/\r
EFI_HANDLE\r
InternalImageHandleToFvHandle (\r
- EFI_HANDLE ImageHandle\r
+ EFI_HANDLE ImageHandle\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ EFI_STATUS Status;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
\r
ASSERT (ImageHandle != NULL);\r
\r
Status = gBS->HandleProtocol (\r
- ImageHandle,\r
- &gEfiLoadedImageProtocolGuid,\r
- (VOID **) &LoadedImage\r
- );\r
+ ImageHandle,\r
+ &gEfiLoadedImageProtocolGuid,\r
+ (VOID **)&LoadedImage\r
+ );\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
// protocol is installed.\r
//\r
return LoadedImage->DeviceHandle;\r
-\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
InternalGetSectionFromFv (\r
- IN EFI_HANDLE FvHandle,\r
- IN CONST EFI_GUID *NameGuid,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN EFI_HANDLE FvHandle,\r
+ IN CONST EFI_GUID *NameGuid,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
- UINT32 AuthenticationStatus;\r
+ EFI_STATUS Status;\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+ UINT32 AuthenticationStatus;\r
\r
ASSERT (NameGuid != NULL);\r
ASSERT (Buffer != NULL);\r
Status = gBS->HandleProtocol (\r
FvHandle,\r
&gEfiFirmwareVolume2ProtocolGuid,\r
- (VOID **) &Fv\r
+ (VOID **)&Fv\r
);\r
if (EFI_ERROR (Status)) {\r
return EFI_NOT_FOUND;\r
//\r
// Read desired section content in NameGuid file\r
//\r
- *Buffer = NULL;\r
- *Size = 0;\r
- Status = Fv->ReadSection (\r
- Fv,\r
- NameGuid,\r
- SectionType,\r
- SectionInstance,\r
- Buffer,\r
- Size,\r
- &AuthenticationStatus\r
- );\r
+ *Buffer = NULL;\r
+ *Size = 0;\r
+ Status = Fv->ReadSection (\r
+ Fv,\r
+ NameGuid,\r
+ SectionType,\r
+ SectionInstance,\r
+ Buffer,\r
+ Size,\r
+ &AuthenticationStatus\r
+ );\r
\r
if (EFI_ERROR (Status) && (SectionType == EFI_SECTION_TE)) {\r
//\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromAnyFvByFileType (\r
- IN EFI_FV_FILETYPE FileType,\r
- IN UINTN FileInstance,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN EFI_FV_FILETYPE FileType,\r
+ IN UINTN FileInstance,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN HandleCount;\r
- UINTN IndexFv;\r
- UINTN IndexFile;\r
- UINTN Key;\r
- EFI_GUID NameGuid;\r
- EFI_FV_FILE_ATTRIBUTES Attributes;\r
- EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN HandleCount;\r
+ UINTN IndexFv;\r
+ UINTN IndexFile;\r
+ UINTN Key;\r
+ EFI_GUID NameGuid;\r
+ EFI_FV_FILE_ATTRIBUTES Attributes;\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
\r
ASSERT (Buffer != NULL);\r
ASSERT (Size != NULL);\r
// Locate all available FVs.\r
//\r
HandleBuffer = NULL;\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiFirmwareVolume2ProtocolGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer\r
- );\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiFirmwareVolume2ProtocolGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
// Use Firmware Volume 2 Protocol to search for a file of type FileType in all FVs.\r
//\r
IndexFile = FileInstance + 1;\r
- Key = 0;\r
+ Key = 0;\r
do {\r
Status = Fv->GetNextFile (Fv, &Key, &FileType, &NameGuid, &Attributes, Size);\r
if (EFI_ERROR (Status)) {\r
break;\r
}\r
- IndexFile --;\r
+\r
+ IndexFile--;\r
} while (IndexFile > 0);\r
\r
//\r
\r
Done:\r
if (HandleBuffer != NULL) {\r
- FreePool(HandleBuffer);\r
+ FreePool (HandleBuffer);\r
}\r
\r
return Status;\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromAnyFv (\r
- IN CONST EFI_GUID *NameGuid,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
+ IN CONST EFI_GUID *NameGuid,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN HandleCount;\r
- UINTN Index;\r
- EFI_HANDLE FvHandle;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN HandleCount;\r
+ UINTN Index;\r
+ EFI_HANDLE FvHandle;\r
\r
//\r
// Search the FV that contain the caller's FFS first.\r
// will locate the FFS faster.\r
//\r
FvHandle = InternalImageHandleToFvHandle (gImageHandle);\r
- Status = InternalGetSectionFromFv (\r
- FvHandle,\r
- NameGuid,\r
- SectionType,\r
- SectionInstance,\r
- Buffer,\r
- Size\r
- );\r
+ Status = InternalGetSectionFromFv (\r
+ FvHandle,\r
+ NameGuid,\r
+ SectionType,\r
+ SectionInstance,\r
+ Buffer,\r
+ Size\r
+ );\r
if (!EFI_ERROR (Status)) {\r
return EFI_SUCCESS;\r
}\r
\r
HandleBuffer = NULL;\r
- Status = gBS->LocateHandleBuffer (\r
- ByProtocol,\r
- &gEfiFirmwareVolume2ProtocolGuid,\r
- NULL,\r
- &HandleCount,\r
- &HandleBuffer\r
- );\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiFirmwareVolume2ProtocolGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto Done;\r
}\r
goto Done;\r
}\r
}\r
-\r
}\r
\r
if (Index == HandleCount) {\r
Done:\r
\r
if (HandleBuffer != NULL) {\r
- FreePool(HandleBuffer);\r
+ FreePool (HandleBuffer);\r
}\r
- return Status;\r
\r
+ return Status;\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromFv (\r
- IN CONST EFI_GUID *NameGuid,\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
- )\r
+ IN CONST EFI_GUID *NameGuid,\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
+ )\r
{\r
return InternalGetSectionFromFv (\r
- InternalImageHandleToFvHandle(gImageHandle),\r
+ InternalImageHandleToFvHandle (gImageHandle),\r
NameGuid,\r
SectionType,\r
SectionInstance,\r
);\r
}\r
\r
-\r
/**\r
Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section.\r
\r
EFI_STATUS\r
EFIAPI\r
GetSectionFromFfs (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- OUT VOID **Buffer,\r
- OUT UINTN *Size\r
- )\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ OUT VOID **Buffer,\r
+ OUT UINTN *Size\r
+ )\r
{\r
- return InternalGetSectionFromFv(\r
- InternalImageHandleToFvHandle(gImageHandle),\r
+ return InternalGetSectionFromFv (\r
+ InternalImageHandleToFvHandle (gImageHandle),\r
&gEfiCallerIdGuid,\r
SectionType,\r
SectionInstance,\r
);\r
}\r
\r
-\r
/**\r
Get the image file buffer data and buffer size by its device path.\r
\r
VOID *\r
EFIAPI\r
GetFileBufferByFilePath (\r
- IN BOOLEAN BootPolicy,\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath,\r
- OUT UINTN *FileSize,\r
- OUT UINT32 *AuthenticationStatus\r
+ IN BOOLEAN BootPolicy,\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *FilePath,\r
+ OUT UINTN *FileSize,\r
+ OUT UINT32 *AuthenticationStatus\r
)\r
{\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePathNode;\r
- EFI_DEVICE_PATH_PROTOCOL *OrigDevicePathNode;\r
- EFI_DEVICE_PATH_PROTOCOL *TempDevicePathNode;\r
- EFI_HANDLE Handle;\r
- EFI_GUID *FvNameGuid;\r
- EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;\r
- EFI_SECTION_TYPE SectionType;\r
- UINT8 *ImageBuffer;\r
- UINTN ImageBufferSize;\r
- EFI_FV_FILETYPE Type;\r
- EFI_FV_FILE_ATTRIBUTES Attrib;\r
- EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *Volume;\r
- EFI_FILE_HANDLE FileHandle;\r
- EFI_FILE_HANDLE LastHandle;\r
- EFI_FILE_INFO *FileInfo;\r
- UINTN FileInfoSize;\r
- EFI_LOAD_FILE_PROTOCOL *LoadFile;\r
- EFI_LOAD_FILE2_PROTOCOL *LoadFile2;\r
- EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathNode;\r
+ EFI_DEVICE_PATH_PROTOCOL *OrigDevicePathNode;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePathNode;\r
+ EFI_HANDLE Handle;\r
+ EFI_GUID *FvNameGuid;\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;\r
+ EFI_SECTION_TYPE SectionType;\r
+ UINT8 *ImageBuffer;\r
+ UINTN ImageBufferSize;\r
+ EFI_FV_FILETYPE Type;\r
+ EFI_FV_FILE_ATTRIBUTES Attrib;\r
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *Volume;\r
+ EFI_FILE_HANDLE FileHandle;\r
+ EFI_FILE_HANDLE LastHandle;\r
+ EFI_FILE_INFO *FileInfo;\r
+ UINTN FileInfoSize;\r
+ EFI_LOAD_FILE_PROTOCOL *LoadFile;\r
+ EFI_LOAD_FILE2_PROTOCOL *LoadFile2;\r
+ EFI_STATUS Status;\r
\r
//\r
// Check input File device path.\r
//\r
- if (FilePath == NULL || FileSize == NULL || AuthenticationStatus == NULL) {\r
+ if ((FilePath == NULL) || (FileSize == NULL) || (AuthenticationStatus == NULL)) {\r
return NULL;\r
}\r
\r
//\r
// Init local variable\r
//\r
- TempDevicePathNode = NULL;\r
- FvNameGuid = NULL;\r
- FileInfo = NULL;\r
- FileHandle = NULL;\r
- ImageBuffer = NULL;\r
- ImageBufferSize = 0;\r
+ TempDevicePathNode = NULL;\r
+ FvNameGuid = NULL;\r
+ FileInfo = NULL;\r
+ FileHandle = NULL;\r
+ ImageBuffer = NULL;\r
+ ImageBufferSize = 0;\r
*AuthenticationStatus = 0;\r
\r
//\r
// Is so, this device path may contain a Image.\r
//\r
DevicePathNode = OrigDevicePathNode;\r
- Status = gBS->LocateDevicePath (&gEfiFirmwareVolume2ProtocolGuid, &DevicePathNode, &Handle);\r
+ Status = gBS->LocateDevicePath (&gEfiFirmwareVolume2ProtocolGuid, &DevicePathNode, &Handle);\r
if (!EFI_ERROR (Status)) {\r
//\r
// For FwVol File system there is only a single file name that is a GUID.\r
//\r
- FvNameGuid = EfiGetNameGuidFromFwVolDevicePathNode ((CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) DevicePathNode);\r
+ FvNameGuid = EfiGetNameGuidFromFwVolDevicePathNode ((CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)DevicePathNode);\r
if (FvNameGuid == NULL) {\r
Status = EFI_INVALID_PARAMETER;\r
} else {\r
//\r
// Read image from the firmware file\r
//\r
- Status = gBS->HandleProtocol (Handle, &gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol);\r
+ Status = gBS->HandleProtocol (Handle, &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&FwVol);\r
if (!EFI_ERROR (Status)) {\r
SectionType = EFI_SECTION_PE32;\r
ImageBuffer = NULL;\r
- Status = FwVol->ReadSection (\r
- FwVol,\r
- FvNameGuid,\r
- SectionType,\r
- 0,\r
- (VOID **)&ImageBuffer,\r
- &ImageBufferSize,\r
- AuthenticationStatus\r
- );\r
+ Status = FwVol->ReadSection (\r
+ FwVol,\r
+ FvNameGuid,\r
+ SectionType,\r
+ 0,\r
+ (VOID **)&ImageBuffer,\r
+ &ImageBufferSize,\r
+ AuthenticationStatus\r
+ );\r
if (EFI_ERROR (Status)) {\r
//\r
// Try a raw file, since a PE32 SECTION does not exist\r
FreePool (ImageBuffer);\r
*AuthenticationStatus = 0;\r
}\r
+\r
ImageBuffer = NULL;\r
- Status = FwVol->ReadFile (\r
- FwVol,\r
- FvNameGuid,\r
- (VOID **)&ImageBuffer,\r
- &ImageBufferSize,\r
- &Type,\r
- &Attrib,\r
- AuthenticationStatus\r
- );\r
+ Status = FwVol->ReadFile (\r
+ FwVol,\r
+ FvNameGuid,\r
+ (VOID **)&ImageBuffer,\r
+ &ImageBufferSize,\r
+ &Type,\r
+ &Attrib,\r
+ AuthenticationStatus\r
+ );\r
}\r
}\r
}\r
+\r
if (!EFI_ERROR (Status)) {\r
goto Finish;\r
}\r
// Attempt to access the file via a file system interface\r
//\r
DevicePathNode = OrigDevicePathNode;\r
- Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid, &DevicePathNode, &Handle);\r
+ Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid, &DevicePathNode, &Handle);\r
if (!EFI_ERROR (Status)) {\r
- Status = gBS->HandleProtocol (Handle, &gEfiSimpleFileSystemProtocolGuid, (VOID**)&Volume);\r
+ Status = gBS->HandleProtocol (Handle, &gEfiSimpleFileSystemProtocolGuid, (VOID **)&Volume);\r
if (!EFI_ERROR (Status)) {\r
//\r
// Open the Volume to get the File System handle\r
//\r
Status = EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// Parse each MEDIA_FILEPATH_DP node. There may be more than one, since the\r
// directory information and filename can be separate. The goal is to inch\r
//\r
DevicePathNode = TempDevicePathNode;\r
while (!EFI_ERROR (Status) && !IsDevicePathEnd (DevicePathNode)) {\r
- if (DevicePathType (DevicePathNode) != MEDIA_DEVICE_PATH ||\r
- DevicePathSubType (DevicePathNode) != MEDIA_FILEPATH_DP) {\r
+ if ((DevicePathType (DevicePathNode) != MEDIA_DEVICE_PATH) ||\r
+ (DevicePathSubType (DevicePathNode) != MEDIA_FILEPATH_DP))\r
+ {\r
Status = EFI_UNSUPPORTED;\r
break;\r
}\r
FileHandle = NULL;\r
\r
Status = LastHandle->Open (\r
- LastHandle,\r
- &FileHandle,\r
- ((FILEPATH_DEVICE_PATH *) DevicePathNode)->PathName,\r
- EFI_FILE_MODE_READ,\r
- 0\r
- );\r
+ LastHandle,\r
+ &FileHandle,\r
+ ((FILEPATH_DEVICE_PATH *)DevicePathNode)->PathName,\r
+ EFI_FILE_MODE_READ,\r
+ 0\r
+ );\r
\r
//\r
// Close the previous node\r
// We have found the file. Now we need to read it. Before we can read the file we need to\r
// figure out how big the file is.\r
//\r
- FileInfo = NULL;\r
+ FileInfo = NULL;\r
FileInfoSize = 0;\r
- Status = FileHandle->GetInfo (\r
- FileHandle,\r
- &gEfiFileInfoGuid,\r
- &FileInfoSize,\r
- FileInfo\r
- );\r
+ Status = FileHandle->GetInfo (\r
+ FileHandle,\r
+ &gEfiFileInfoGuid,\r
+ &FileInfoSize,\r
+ FileInfo\r
+ );\r
\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
FileInfo = AllocatePool (FileInfoSize);\r
Status = EFI_OUT_OF_RESOURCES;\r
} else {\r
Status = FileHandle->GetInfo (\r
- FileHandle,\r
- &gEfiFileInfoGuid,\r
- &FileInfoSize,\r
- FileInfo\r
- );\r
+ FileHandle,\r
+ &gEfiFileInfoGuid,\r
+ &FileInfoSize,\r
+ FileInfo\r
+ );\r
}\r
}\r
\r
}\r
}\r
}\r
+\r
//\r
// Close the file and Free FileInfo and TempDevicePathNode since we are done\r
//\r
if (FileInfo != NULL) {\r
FreePool (FileInfo);\r
}\r
+\r
if (FileHandle != NULL) {\r
FileHandle->Close (FileHandle);\r
}\r
+\r
if (TempDevicePathNode != NULL) {\r
FreePool (TempDevicePathNode);\r
}\r
}\r
}\r
+\r
if (!EFI_ERROR (Status)) {\r
goto Finish;\r
}\r
//\r
if (!BootPolicy) {\r
DevicePathNode = OrigDevicePathNode;\r
- Status = gBS->LocateDevicePath (&gEfiLoadFile2ProtocolGuid, &DevicePathNode, &Handle);\r
+ Status = gBS->LocateDevicePath (&gEfiLoadFile2ProtocolGuid, &DevicePathNode, &Handle);\r
if (!EFI_ERROR (Status)) {\r
- Status = gBS->HandleProtocol (Handle, &gEfiLoadFile2ProtocolGuid, (VOID**)&LoadFile2);\r
+ Status = gBS->HandleProtocol (Handle, &gEfiLoadFile2ProtocolGuid, (VOID **)&LoadFile2);\r
if (!EFI_ERROR (Status)) {\r
//\r
// Call LoadFile2 with the correct buffer size\r
//\r
ImageBufferSize = 0;\r
ImageBuffer = NULL;\r
- Status = LoadFile2->LoadFile (\r
- LoadFile2,\r
- DevicePathNode,\r
- FALSE,\r
- &ImageBufferSize,\r
- ImageBuffer\r
- );\r
+ Status = LoadFile2->LoadFile (\r
+ LoadFile2,\r
+ DevicePathNode,\r
+ FALSE,\r
+ &ImageBufferSize,\r
+ ImageBuffer\r
+ );\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
ImageBuffer = AllocatePool (ImageBufferSize);\r
if (ImageBuffer == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
} else {\r
Status = LoadFile2->LoadFile (\r
- LoadFile2,\r
- DevicePathNode,\r
- FALSE,\r
- &ImageBufferSize,\r
- ImageBuffer\r
- );\r
+ LoadFile2,\r
+ DevicePathNode,\r
+ FALSE,\r
+ &ImageBufferSize,\r
+ ImageBuffer\r
+ );\r
}\r
}\r
}\r
+\r
if (!EFI_ERROR (Status)) {\r
goto Finish;\r
}\r
// Attempt to access the file via LoadFile interface\r
//\r
DevicePathNode = OrigDevicePathNode;\r
- Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid, &DevicePathNode, &Handle);\r
+ Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid, &DevicePathNode, &Handle);\r
if (!EFI_ERROR (Status)) {\r
- Status = gBS->HandleProtocol (Handle, &gEfiLoadFileProtocolGuid, (VOID**)&LoadFile);\r
+ Status = gBS->HandleProtocol (Handle, &gEfiLoadFileProtocolGuid, (VOID **)&LoadFile);\r
if (!EFI_ERROR (Status)) {\r
//\r
// Call LoadFile with the correct buffer size\r
//\r
ImageBufferSize = 0;\r
ImageBuffer = NULL;\r
- Status = LoadFile->LoadFile (\r
- LoadFile,\r
- DevicePathNode,\r
- BootPolicy,\r
- &ImageBufferSize,\r
- ImageBuffer\r
- );\r
+ Status = LoadFile->LoadFile (\r
+ LoadFile,\r
+ DevicePathNode,\r
+ BootPolicy,\r
+ &ImageBufferSize,\r
+ ImageBuffer\r
+ );\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
ImageBuffer = AllocatePool (ImageBufferSize);\r
if (ImageBuffer == NULL) {\r
FreePool (ImageBuffer);\r
ImageBuffer = NULL;\r
}\r
+\r
*FileSize = 0;\r
} else {\r
*FileSize = ImageBufferSize;\r
OUT EFI_DEVICE_PATH_PROTOCOL **FvFileDevicePath\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE *HandleBuffer;\r
- UINTN HandleCount;\r
- UINTN Index;\r
- EFI_HANDLE FvHandle;\r
- EFI_DEVICE_PATH_PROTOCOL *FvDevicePath;\r
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *TempFvFileDevicePath;\r
- VOID *Buffer;\r
- UINTN Size;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN HandleCount;\r
+ UINTN Index;\r
+ EFI_HANDLE FvHandle;\r
+ EFI_DEVICE_PATH_PROTOCOL *FvDevicePath;\r
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *TempFvFileDevicePath;\r
+ VOID *Buffer;\r
+ UINTN Size;\r
\r
if (FvFileDevicePath == NULL) {\r
return EFI_INVALID_PARAMETER;\r
// will locate the FFS faster.\r
//\r
FvHandle = InternalImageHandleToFvHandle (gImageHandle);\r
- Status = InternalGetSectionFromFv (\r
- FvHandle,\r
- NameGuid,\r
- SectionType,\r
- SectionInstance,\r
- &Buffer,\r
- &Size\r
- );\r
+ Status = InternalGetSectionFromFv (\r
+ FvHandle,\r
+ NameGuid,\r
+ SectionType,\r
+ SectionInstance,\r
+ &Buffer,\r
+ &Size\r
+ );\r
if (!EFI_ERROR (Status)) {\r
goto Done;\r
}\r
*FvFileDevicePath = NULL;\r
return EFI_OUT_OF_RESOURCES;\r
}\r
- EfiInitializeFwVolDevicepathNode ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH*)TempFvFileDevicePath, NameGuid);\r
+\r
+ EfiInitializeFwVolDevicepathNode ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)TempFvFileDevicePath, NameGuid);\r
SetDevicePathEndNode (NextDevicePathNode (TempFvFileDevicePath));\r
*FvFileDevicePath = AppendDevicePath (\r
FvDevicePath,\r
PhitHob = (EFI_HOB_HANDOFF_INFO_TABLE *)GetHobList ();\r
if (PhitHob->EfiFreeMemoryTop <= MAX_UINT32) {\r
AllocType = AllocateMaxAddress;\r
- Memory = MAX_UINT32;\r
+ Memory = MAX_UINT32;\r
}\r
\r
Status = gBS->AllocatePages (AllocType, MemoryType, Pages, &Memory);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
+\r
return (VOID *)(UINTN)Memory;\r
}\r
//\r
// Cache copy of the DXE Services Table\r
//\r
-EFI_DXE_SERVICES *gDS = NULL;\r
+EFI_DXE_SERVICES *gDS = NULL;\r
\r
/**\r
The constructor function caches the pointer of DXE Services Table.\r
//\r
// Cache copy of the DXE Services Table\r
//\r
- Status = EfiGetSystemConfigurationTable (&gEfiDxeServicesTableGuid, (VOID **) &gDS);\r
+ Status = EfiGetSystemConfigurationTable (&gEfiDxeServicesTableGuid, (VOID **)&gDS);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (gDS != NULL);\r
\r
\r
**/\r
\r
-\r
#include "InternalSmbusLib.h"\r
\r
-\r
//\r
// Global variable to cache pointer to Smbus protocol.\r
//\r
-EFI_SMBUS_HC_PROTOCOL *mSmbus = NULL;\r
+EFI_SMBUS_HC_PROTOCOL *mSmbus = NULL;\r
\r
/**\r
The constructor function caches the pointer to Smbus protocol.\r
EFI_STATUS\r
EFIAPI\r
SmbusLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
\r
- Status = gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID**) &mSmbus);\r
+ Status = gBS->LocateProtocol (&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&mSmbus);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mSmbus != NULL);\r
\r
**/\r
UINTN\r
InternalSmBusExec (\r
- IN EFI_SMBUS_OPERATION SmbusOperation,\r
- IN UINTN SmBusAddress,\r
- IN UINTN Length,\r
- IN OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN EFI_SMBUS_OPERATION SmbusOperation,\r
+ IN UINTN SmBusAddress,\r
+ IN UINTN Length,\r
+ IN OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
RETURN_STATUS ReturnStatus;\r
#ifndef __INTERNAL_SMBUS_LIB_H_\r
#define __INTERNAL_SMBUS_LIB_H_\r
\r
-\r
#include <PiDxe.h>\r
\r
#include <Protocol/SmbusHc.h>\r
//\r
// Declaration for internal functions\r
//\r
+\r
/**\r
Executes an SMBus operation to an SMBus controller.\r
\r
**/\r
UINTN\r
InternalSmBusExec (\r
- IN EFI_SMBUS_OPERATION SmbusOperation,\r
- IN UINTN SmBusAddress,\r
- IN UINTN Length,\r
- IN OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN EFI_SMBUS_OPERATION SmbusOperation,\r
+ IN UINTN SmBusAddress,\r
+ IN UINTN Length,\r
+ IN OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmbusLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
);\r
\r
#endif\r
VOID\r
EFIAPI\r
SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
VOID\r
EFIAPI\r
SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
\r
- Byte = Value;\r
+ Byte = Value;\r
InternalSmBusExec (EfiSmbusSendByte, SmBusAddress, 1, &Byte, Status);\r
\r
return Value;\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
ASSERT (WriteBuffer != NULL);\r
ASSERT (ReadBuffer != NULL);\r
#include <Library/MmServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
\r
-EFI_MM_SYSTEM_TABLE *gMmst = NULL;\r
+EFI_MM_SYSTEM_TABLE *gMmst = NULL;\r
\r
/**\r
The constructor function caches the pointer of the MM Services Table.\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_MM_BASE_PROTOCOL *InternalMmBase;\r
+ EFI_STATUS Status;\r
+ EFI_MM_BASE_PROTOCOL *InternalMmBase;\r
\r
InternalMmBase = NULL;\r
//\r
RETURN_STATUS\r
EFIAPI\r
MmUnblockMemoryRequest (\r
- IN PHYSICAL_ADDRESS UnblockAddress,\r
- IN UINT64 NumberOfPages\r
+ IN PHYSICAL_ADDRESS UnblockAddress,\r
+ IN UINT64 NumberOfPages\r
)\r
{\r
return RETURN_UNSUPPORTED;\r
**/\r
UINTN\r
PciSegmentLibVirtualAddress (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return Address;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count);\r
- );\r
+ );\r
return RETURN_SUCCESS;\r
}\r
/// Define table for mapping PCI Segment MMIO physical addresses to virtual addresses at OS runtime\r
///\r
typedef struct {\r
- UINTN PhysicalAddress;\r
- UINTN VirtualAddress;\r
+ UINTN PhysicalAddress;\r
+ UINTN VirtualAddress;\r
} PCI_SEGMENT_RUNTIME_REGISTRATION_TABLE;\r
\r
///\r
/// Set Virtual Address Map Event\r
///\r
-EFI_EVENT mDxeRuntimePciSegmentLibVirtualNotifyEvent = NULL;\r
+EFI_EVENT mDxeRuntimePciSegmentLibVirtualNotifyEvent = NULL;\r
\r
///\r
/// The number of PCI devices that have been registered for runtime access.\r
///\r
-UINTN mDxeRuntimePciSegmentLibNumberOfRuntimeRanges = 0;\r
+UINTN mDxeRuntimePciSegmentLibNumberOfRuntimeRanges = 0;\r
\r
///\r
/// The table of PCI devices that have been registered for runtime access.\r
///\r
/// The table index of the most recent virtual address lookup.\r
///\r
-UINTN mDxeRuntimePciSegmentLibLastRuntimeRange = 0;\r
+UINTN mDxeRuntimePciSegmentLibLastRuntimeRange = 0;\r
\r
/**\r
Convert the physical PCI Express MMIO addresses for all registered PCI devices\r
IN VOID *Context\r
)\r
{\r
- UINTN Index;\r
- EFI_STATUS Status;\r
+ UINTN Index;\r
+ EFI_STATUS Status;\r
\r
//\r
// If there have been no runtime registrations, then just return\r
// virtual addresses.\r
//\r
for (Index = 0; Index < mDxeRuntimePciSegmentLibNumberOfRuntimeRanges; Index++) {\r
- Status = EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciSegmentLibRegistrationTable[Index].VirtualAddress));\r
+ Status = EfiConvertPointer (0, (VOID **)&(mDxeRuntimePciSegmentLibRegistrationTable[Index].VirtualAddress));\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
//\r
// Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r
//\r
- Status = EfiConvertPointer (0, (VOID **) &mDxeRuntimePciSegmentLibRegistrationTable);\r
+ Status = EfiConvertPointer (0, (VOID **)&mDxeRuntimePciSegmentLibRegistrationTable);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
// Convert Address to a ECAM address at the beginning of the PCI Configuration\r
// header for the specified PCI Bus/Dev/Func\r
//\r
- Address &= ~(UINTN)EFI_PAGE_MASK;\r
+ Address &= ~(UINTN)EFI_PAGE_MASK;\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
EcamAddress = PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count);\r
\r
if (EfiAtRuntime ()) {\r
return RETURN_UNSUPPORTED;\r
}\r
+\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
ASSERT (EcamAddress < BASE_4GB);\r
}\r
+\r
Address = (UINTN)EcamAddress;\r
\r
//\r
if (NewTable == NULL) {\r
return RETURN_OUT_OF_RESOURCES;\r
}\r
- mDxeRuntimePciSegmentLibRegistrationTable = NewTable;\r
+\r
+ mDxeRuntimePciSegmentLibRegistrationTable = NewTable;\r
mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r
mDxeRuntimePciSegmentLibRegistrationTable[mDxeRuntimePciSegmentLibNumberOfRuntimeRanges].VirtualAddress = Address;\r
mDxeRuntimePciSegmentLibNumberOfRuntimeRanges++;\r
**/\r
UINTN\r
PciSegmentLibVirtualAddress (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
+\r
//\r
// If SetVirtualAddressMap() has not been called, then just return the physical address\r
//\r
#include "PciSegmentLibCommon.h"\r
\r
typedef struct {\r
- UINT32 Register : 12;\r
- UINT32 Function : 3;\r
- UINT32 Device : 5;\r
- UINT32 Bus : 8;\r
- UINT32 Reserved1 : 4;\r
- UINT32 Segment : 16;\r
- UINT32 Reserved2 : 16;\r
+ UINT32 Register : 12;\r
+ UINT32 Function : 3;\r
+ UINT32 Device : 5;\r
+ UINT32 Bus : 8;\r
+ UINT32 Reserved1 : 4;\r
+ UINT32 Segment : 16;\r
+ UINT32 Reserved2 : 16;\r
} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;\r
\r
/**\r
**/\r
UINTN\r
PciSegmentLibGetEcamAddress (\r
- IN UINT64 Address,\r
- IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r
- IN UINTN Count\r
+ IN UINT64 Address,\r
+ IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r
+ IN UINTN Count\r
)\r
{\r
while (Count != 0) {\r
if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {\r
break;\r
}\r
+\r
SegmentInfo++;\r
Count--;\r
}\r
+\r
ASSERT (Count != 0);\r
ASSERT (\r
(((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&\r
(((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)\r
- );\r
+ );\r
ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);\r
ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);\r
\r
Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (\r
- ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,\r
- ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,\r
- ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,\r
- ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register);\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register\r
+ );\r
\r
if (sizeof (UINTN) == sizeof (UINT32)) {\r
ASSERT (Address < BASE_4GB);\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
}\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
return MmioBitFieldAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
}\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
- UINTN Address;\r
+ UINTN ReturnValue;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Address;\r
\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
- Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
\r
if (Size == 0) {\r
return 0;\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = MmioRead8 (Address);\r
- Address += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Address += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((Address & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, MmioRead16 (Address));\r
Address += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, MmioRead32 (Address));\r
Address += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, MmioRead16 (Address));\r
Address += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
- UINTN Count;\r
- PCI_SEGMENT_INFO *SegmentInfo;\r
- UINTN Address;\r
+ UINTN ReturnValue;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Address;\r
\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
SegmentInfo = GetPciSegmentInfo (&Count);\r
- Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
\r
if (Size == 0) {\r
return 0;\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- MmioWrite8 (Address, *(UINT8*)Buffer);\r
+ MmioWrite8 (Address, *(UINT8 *)Buffer);\r
Address += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((Address & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r
Address += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
MmioWrite32 (Address, ReadUnaligned32 (Buffer));\r
Address += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r
Address += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- MmioWrite8 (Address, *(UINT8*)Buffer);\r
+ MmioWrite8 (Address, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
**/\r
UINTN\r
PciSegmentLibVirtualAddress (\r
- IN UINTN Address\r
+ IN UINTN Address\r
);\r
\r
/**\r
**/\r
UINTN\r
PciSegmentLibGetEcamAddress (\r
- IN UINT64 Address,\r
- IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r
- IN UINTN Count\r
+ IN UINT64 Address,\r
+ IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r
+ IN UINTN Count\r
);\r
\r
#endif\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
//\r
**/\r
VOID\r
EFIAPI\r
-_ModuleEntryPoint(\r
+_ModuleEntryPoint (\r
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
-)\r
+ )\r
{\r
ProcessModuleEntryPointList (SecCoreData, PpiList, NULL);\r
\r
//\r
// Should never return\r
//\r
- ASSERT(FALSE);\r
+ ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Library/PostCodeLib.h>\r
return Value;\r
}\r
\r
-\r
/**\r
Sends an 32-bit value to a POST and associated ASCII string.\r
\r
return Value;\r
}\r
\r
-\r
/**\r
Returns TRUE if POST Codes are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if POST code descriptions are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdPostCodePropertyMask) & POST_CODE_PROPERTY_POST_CODE_DESCRIPTION_ENABLED) != 0);\r
}\r
-\r
#include <Library/HobLib.h>\r
#include <Library/ExtractGuidedSectionLib.h>\r
\r
-#define PEI_EXTRACT_HANDLER_INFO_SIGNATURE SIGNATURE_32 ('P', 'E', 'H', 'I')\r
+#define PEI_EXTRACT_HANDLER_INFO_SIGNATURE SIGNATURE_32 ('P', 'E', 'H', 'I')\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT32 NumberOfExtractHandler;\r
- GUID *ExtractHandlerGuidTable;\r
- EXTRACT_GUIDED_SECTION_DECODE_HANDLER *ExtractDecodeHandlerTable;\r
- EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *ExtractGetInfoHandlerTable;\r
+ UINT32 Signature;\r
+ UINT32 NumberOfExtractHandler;\r
+ GUID *ExtractHandlerGuidTable;\r
+ EXTRACT_GUIDED_SECTION_DECODE_HANDLER *ExtractDecodeHandlerTable;\r
+ EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *ExtractGetInfoHandlerTable;\r
} PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO;\r
\r
/**\r
**/\r
RETURN_STATUS\r
PeiGetExtractGuidedSectionHandlerInfo (\r
- IN OUT PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO **InfoPointer\r
+ IN OUT PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO **InfoPointer\r
)\r
{\r
- PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
- EFI_PEI_HOB_POINTERS Hob;\r
+ PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
\r
//\r
// First try to get handler information from guid hob specified by CallerId.\r
Hob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GetHobList ());\r
while (Hob.Raw != NULL) {\r
if (CompareGuid (&(Hob.Guid->Name), &gEfiCallerIdGuid)) {\r
- HandlerInfo = (PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *) GET_GUID_HOB_DATA (Hob.Guid);\r
+ HandlerInfo = (PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *)GET_GUID_HOB_DATA (Hob.Guid);\r
if (HandlerInfo->Signature == PEI_EXTRACT_HANDLER_INFO_SIGNATURE) {\r
//\r
// Update Table Pointer when hob start address is changed.\r
//\r
- if (HandlerInfo->ExtractHandlerGuidTable != (GUID *) (HandlerInfo + 1)) {\r
- HandlerInfo->ExtractHandlerGuidTable = (GUID *) (HandlerInfo + 1);\r
- HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
- );\r
- HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
- sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
- );\r
+ if (HandlerInfo->ExtractHandlerGuidTable != (GUID *)(HandlerInfo + 1)) {\r
+ HandlerInfo->ExtractHandlerGuidTable = (GUID *)(HandlerInfo + 1);\r
+ HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
+ );\r
+ HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
+ sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
+ );\r
}\r
+\r
//\r
// Return HandlerInfo pointer.\r
//\r
return EFI_SUCCESS;\r
}\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
Hob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, Hob.Raw);\r
}\r
// If Guid Hob is not found, Build CallerId Guid hob to store Handler Info\r
//\r
HandlerInfo = BuildGuidHob (\r
- &gEfiCallerIdGuid,\r
- sizeof (PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO) +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
- (sizeof (GUID) + sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER) + sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER))\r
- );\r
+ &gEfiCallerIdGuid,\r
+ sizeof (PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO) +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
+ (sizeof (GUID) + sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER) + sizeof (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER))\r
+ );\r
if (HandlerInfo == NULL) {\r
//\r
// No enough resource to build guid hob.\r
*InfoPointer = NULL;\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
//\r
// Init HandlerInfo structure\r
//\r
- HandlerInfo->Signature = PEI_EXTRACT_HANDLER_INFO_SIGNATURE;\r
- HandlerInfo->NumberOfExtractHandler = 0;\r
- HandlerInfo->ExtractHandlerGuidTable = (GUID *) (HandlerInfo + 1);\r
- HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
- );\r
- HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *) (\r
- (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
- PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
- sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
- );\r
+ HandlerInfo->Signature = PEI_EXTRACT_HANDLER_INFO_SIGNATURE;\r
+ HandlerInfo->NumberOfExtractHandler = 0;\r
+ HandlerInfo->ExtractHandlerGuidTable = (GUID *)(HandlerInfo + 1);\r
+ HandlerInfo->ExtractDecodeHandlerTable = (EXTRACT_GUIDED_SECTION_DECODE_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractHandlerGuidTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) * sizeof (GUID)\r
+ );\r
+ HandlerInfo->ExtractGetInfoHandlerTable = (EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER *)(\r
+ (UINT8 *)HandlerInfo->ExtractDecodeHandlerTable +\r
+ PcdGet32 (PcdMaximumGuidedExtractHandler) *\r
+ sizeof (EXTRACT_GUIDED_SECTION_DECODE_HANDLER)\r
+ );\r
//\r
// return the created HandlerInfo.\r
//\r
OUT GUID **ExtractHandlerGuidTable\r
)\r
{\r
- EFI_STATUS Status;\r
- PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_STATUS Status;\r
+ PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
ASSERT (ExtractHandlerGuidTable != NULL);\r
\r
IN EXTRACT_GUIDED_SECTION_DECODE_HANDLER DecodeHandler\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 Index;\r
- PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_STATUS Status;\r
+ UINT32 Index;\r
+ PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
\r
//\r
// Check input parameter\r
ASSERT (GetInfoHandler != NULL);\r
ASSERT (DecodeHandler != NULL);\r
\r
-\r
-\r
//\r
// Get the registered handler information\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {\r
//\r
// If the guided handler has been registered before, only update its handler.\r
//\r
- HandlerInfo->ExtractDecodeHandlerTable [Index] = DecodeHandler;\r
- HandlerInfo->ExtractGetInfoHandlerTable [Index] = GetInfoHandler;\r
+ HandlerInfo->ExtractDecodeHandlerTable[Index] = DecodeHandler;\r
+ HandlerInfo->ExtractGetInfoHandlerTable[Index] = GetInfoHandler;\r
return RETURN_SUCCESS;\r
}\r
}\r
// Register new Handler and guid value.\r
//\r
CopyGuid (HandlerInfo->ExtractHandlerGuidTable + HandlerInfo->NumberOfExtractHandler, SectionGuid);\r
- HandlerInfo->ExtractDecodeHandlerTable [HandlerInfo->NumberOfExtractHandler] = DecodeHandler;\r
- HandlerInfo->ExtractGetInfoHandlerTable [HandlerInfo->NumberOfExtractHandler++] = GetInfoHandler;\r
+ HandlerInfo->ExtractDecodeHandlerTable[HandlerInfo->NumberOfExtractHandler] = DecodeHandler;\r
+ HandlerInfo->ExtractGetInfoHandlerTable[HandlerInfo->NumberOfExtractHandler++] = GetInfoHandler;\r
\r
//\r
// Build the Guided Section GUID HOB to record the GUID itself.\r
// Then the content of the GUIDed HOB will be the same as the GUID value itself.\r
//\r
BuildGuidDataHob (\r
- (EFI_GUID *) SectionGuid,\r
- (VOID *) SectionGuid,\r
+ (EFI_GUID *)SectionGuid,\r
+ (VOID *)SectionGuid,\r
sizeof (GUID)\r
);\r
\r
OUT UINT16 *SectionAttribute\r
)\r
{\r
- UINT32 Index;\r
- EFI_STATUS Status;\r
- PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ EFI_STATUS Status;\r
+ PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
//\r
// Check input parameter\r
}\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {\r
//\r
// Call the match handler to get information for the input section data.\r
//\r
- return HandlerInfo->ExtractGetInfoHandlerTable [Index] (\r
- InputSection,\r
- OutputBufferSize,\r
- ScratchBufferSize,\r
- SectionAttribute\r
- );\r
+ return HandlerInfo->ExtractGetInfoHandlerTable[Index](\r
+ InputSection,\r
+ OutputBufferSize,\r
+ ScratchBufferSize,\r
+ SectionAttribute\r
+ );\r
}\r
}\r
\r
OUT UINT32 *AuthenticationStatus\r
)\r
{\r
- UINT32 Index;\r
- EFI_STATUS Status;\r
- PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
- EFI_GUID *SectionDefinitionGuid;\r
+ UINT32 Index;\r
+ EFI_STATUS Status;\r
+ PEI_EXTRACT_GUIDED_SECTION_HANDLER_INFO *HandlerInfo;\r
+ EFI_GUID *SectionDefinitionGuid;\r
\r
//\r
// Check input parameter\r
}\r
\r
if (IS_SECTION2 (InputSection)) {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION2 *)InputSection)->SectionDefinitionGuid);\r
} else {\r
- SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *) InputSection)->SectionDefinitionGuid);\r
+ SectionDefinitionGuid = &(((EFI_GUID_DEFINED_SECTION *)InputSection)->SectionDefinitionGuid);\r
}\r
\r
//\r
// Search the match registered Extract handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionDefinitionGuid)) {\r
//\r
// Call the match handler to extract raw data for the input guided section.\r
//\r
- return HandlerInfo->ExtractDecodeHandlerTable [Index] (\r
- InputSection,\r
- OutputBuffer,\r
- ScratchBuffer,\r
- AuthenticationStatus\r
- );\r
+ return HandlerInfo->ExtractDecodeHandlerTable[Index](\r
+ InputSection,\r
+ OutputBuffer,\r
+ ScratchBuffer,\r
+ AuthenticationStatus\r
+ );\r
}\r
}\r
\r
// Search the match registered GetInfo handler for the input guided section.\r
//\r
ASSERT (HandlerInfo != NULL);\r
- for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index ++) {\r
+ for (Index = 0; Index < HandlerInfo->NumberOfExtractHandler; Index++) {\r
if (CompareGuid (HandlerInfo->ExtractHandlerGuidTable + Index, SectionGuid)) {\r
-\r
//\r
// If the guided handler has been registered before, then return the registered handlers.\r
//\r
if (GetInfoHandler != NULL) {\r
*GetInfoHandler = HandlerInfo->ExtractGetInfoHandlerTable[Index];\r
}\r
+\r
if (DecodeHandler != NULL) {\r
*DecodeHandler = HandlerInfo->ExtractDecodeHandlerTable[Index];\r
}\r
+\r
return RETURN_SUCCESS;\r
}\r
}\r
+\r
return RETURN_NOT_FOUND;\r
}\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *HobList;\r
+ EFI_STATUS Status;\r
+ VOID *HobList;\r
\r
Status = PeiServicesGetHobList (&HobList);\r
ASSERT_EFI_ERROR (Status);\r
VOID *\r
EFIAPI\r
GetNextHob (\r
- IN UINT16 Type,\r
- IN CONST VOID *HobStart\r
+ IN UINT16 Type,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS Hob;\r
\r
ASSERT (HobStart != NULL);\r
\r
- Hob.Raw = (UINT8 *) HobStart;\r
+ Hob.Raw = (UINT8 *)HobStart;\r
//\r
// Parse the HOB list until end of list or matching type is found.\r
//\r
if (Hob.Header->HobType == Type) {\r
return Hob.Raw;\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
}\r
+\r
return NULL;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstHob (\r
- IN UINT16 Type\r
+ IN UINT16 Type\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextHob (Type, HobList);\r
VOID *\r
EFIAPI\r
GetNextGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN CONST VOID *HobStart\r
+ IN CONST EFI_GUID *Guid,\r
+ IN CONST VOID *HobStart\r
)\r
{\r
EFI_PEI_HOB_POINTERS GuidHob;\r
\r
- GuidHob.Raw = (UINT8 *) HobStart;\r
+ GuidHob.Raw = (UINT8 *)HobStart;\r
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {\r
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {\r
break;\r
}\r
+\r
GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
}\r
+\r
return GuidHob.Raw;\r
}\r
\r
VOID *\r
EFIAPI\r
GetFirstGuidHob (\r
- IN CONST EFI_GUID *Guid\r
+ IN CONST EFI_GUID *Guid\r
)\r
{\r
- VOID *HobList;\r
+ VOID *HobList;\r
\r
HobList = GetHobList ();\r
return GetNextGuidHob (Guid, HobList);\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_BOOT_MODE BootMode;\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE BootMode;\r
\r
Status = PeiServicesGetBootMode (&BootMode);\r
ASSERT_EFI_ERROR (Status);\r
VOID *\r
EFIAPI\r
InternalPeiCreateHob (\r
- IN UINT16 Type,\r
- IN UINT16 Length\r
+ IN UINT16 Type,\r
+ IN UINT16 Length\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *Hob;\r
+ EFI_STATUS Status;\r
+ VOID *Hob;\r
\r
Status = PeiServicesCreateHob (Type, Length, &Hob);\r
if (EFI_ERROR (Status)) {\r
Hob = NULL;\r
}\r
+\r
//\r
// Assume the process of HOB building is always successful.\r
//\r
VOID\r
EFIAPI\r
BuildModuleHob (\r
- IN CONST EFI_GUID *ModuleName,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
- IN UINT64 ModuleLength,\r
- IN EFI_PHYSICAL_ADDRESS EntryPoint\r
+ IN CONST EFI_GUID *ModuleName,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,\r
+ IN UINT64 ModuleLength,\r
+ IN EFI_PHYSICAL_ADDRESS EntryPoint\r
)\r
{\r
EFI_HOB_MEMORY_ALLOCATION_MODULE *Hob;\r
\r
- ASSERT (((MemoryAllocationModule & (EFI_PAGE_SIZE - 1)) == 0) &&\r
- ((ModuleLength & (EFI_PAGE_SIZE - 1)) == 0));\r
+ ASSERT (\r
+ ((MemoryAllocationModule & (EFI_PAGE_SIZE - 1)) == 0) &&\r
+ ((ModuleLength & (EFI_PAGE_SIZE - 1)) == 0)\r
+ );\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16) sizeof (EFI_HOB_MEMORY_ALLOCATION_MODULE));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16)sizeof (EFI_HOB_MEMORY_ALLOCATION_MODULE));\r
if (Hob == NULL) {\r
return;\r
}\r
{\r
EFI_HOB_RESOURCE_DESCRIPTOR *Hob;\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (UINT16) sizeof (EFI_HOB_RESOURCE_DESCRIPTOR));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (UINT16)sizeof (EFI_HOB_RESOURCE_DESCRIPTOR));\r
if (Hob == NULL) {\r
return;\r
}\r
{\r
EFI_HOB_RESOURCE_DESCRIPTOR *Hob;\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (UINT16) sizeof (EFI_HOB_RESOURCE_DESCRIPTOR));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (UINT16)sizeof (EFI_HOB_RESOURCE_DESCRIPTOR));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID *\r
EFIAPI\r
BuildGuidHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN DataLength\r
)\r
{\r
- EFI_HOB_GUID_TYPE *Hob;\r
+ EFI_HOB_GUID_TYPE *Hob;\r
\r
//\r
// Make sure Guid is valid\r
//\r
ASSERT (DataLength <= (0xFFF8 - sizeof (EFI_HOB_GUID_TYPE)));\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, (UINT16) (sizeof (EFI_HOB_GUID_TYPE) + DataLength));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, (UINT16)(sizeof (EFI_HOB_GUID_TYPE) + DataLength));\r
if (Hob == NULL) {\r
return Hob;\r
}\r
+\r
CopyGuid (&Hob->Name, Guid);\r
return Hob + 1;\r
}\r
VOID *\r
EFIAPI\r
BuildGuidDataHob (\r
- IN CONST EFI_GUID *Guid,\r
- IN VOID *Data,\r
- IN UINTN DataLength\r
+ IN CONST EFI_GUID *Guid,\r
+ IN VOID *Data,\r
+ IN UINTN DataLength\r
)\r
{\r
VOID *HobData;\r
**/\r
BOOLEAN\r
InternalCheckFvAlignment (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
- EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
- UINT32 FvAlignment;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
+ UINT32 FvAlignment;\r
\r
FvAlignment = 0;\r
- FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress;\r
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)BaseAddress;\r
\r
//\r
// If EFI_FVB2_WEAK_ALIGNMENT is set in the volume header then the first byte of the volume\r
if (FvAlignment < 8) {\r
FvAlignment = 8;\r
}\r
+\r
if ((UINTN)BaseAddress % FvAlignment != 0) {\r
//\r
// FvImage buffer is not at its required alignment.\r
VOID\r
EFIAPI\r
BuildFvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
EFI_HOB_FIRMWARE_VOLUME *Hob;\r
return;\r
}\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV, (UINT16) sizeof (EFI_HOB_FIRMWARE_VOLUME));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV, (UINT16)sizeof (EFI_HOB_FIRMWARE_VOLUME));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildFv2Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN CONST EFI_GUID *FvName,\r
- IN CONST EFI_GUID *FileName\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN CONST EFI_GUID *FvName,\r
+ IN CONST EFI_GUID *FileName\r
)\r
{\r
EFI_HOB_FIRMWARE_VOLUME2 *Hob;\r
return;\r
}\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV2, (UINT16) sizeof (EFI_HOB_FIRMWARE_VOLUME2));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV2, (UINT16)sizeof (EFI_HOB_FIRMWARE_VOLUME2));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildFv3Hob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT32 AuthenticationStatus,\r
- IN BOOLEAN ExtractedFv,\r
- IN CONST EFI_GUID *FvName OPTIONAL,\r
- IN CONST EFI_GUID *FileName OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT32 AuthenticationStatus,\r
+ IN BOOLEAN ExtractedFv,\r
+ IN CONST EFI_GUID *FvName OPTIONAL,\r
+ IN CONST EFI_GUID *FileName OPTIONAL\r
)\r
{\r
EFI_HOB_FIRMWARE_VOLUME3 *Hob;\r
return;\r
}\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV3, (UINT16) sizeof (EFI_HOB_FIRMWARE_VOLUME3));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_FV3, (UINT16)sizeof (EFI_HOB_FIRMWARE_VOLUME3));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildCvHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
EFI_HOB_UEFI_CAPSULE *Hob;\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_UEFI_CAPSULE, (UINT16) sizeof (EFI_HOB_UEFI_CAPSULE));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_UEFI_CAPSULE, (UINT16)sizeof (EFI_HOB_UEFI_CAPSULE));\r
if (Hob == NULL) {\r
return;\r
}\r
\r
- Hob->BaseAddress = BaseAddress;\r
- Hob->Length = Length;\r
+ Hob->BaseAddress = BaseAddress;\r
+ Hob->Length = Length;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
BuildCpuHob (\r
- IN UINT8 SizeOfMemorySpace,\r
- IN UINT8 SizeOfIoSpace\r
+ IN UINT8 SizeOfMemorySpace,\r
+ IN UINT8 SizeOfIoSpace\r
)\r
{\r
EFI_HOB_CPU *Hob;\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_CPU, (UINT16) sizeof (EFI_HOB_CPU));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_CPU, (UINT16)sizeof (EFI_HOB_CPU));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildStackHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
)\r
{\r
EFI_HOB_MEMORY_ALLOCATION_STACK *Hob;\r
\r
- ASSERT (((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
- ((Length & (EFI_PAGE_SIZE - 1)) == 0));\r
+ ASSERT (\r
+ ((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
+ ((Length & (EFI_PAGE_SIZE - 1)) == 0)\r
+ );\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16) sizeof (EFI_HOB_MEMORY_ALLOCATION_STACK));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16)sizeof (EFI_HOB_MEMORY_ALLOCATION_STACK));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildBspStoreHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *Hob;\r
\r
- ASSERT (((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
- ((Length & (EFI_PAGE_SIZE - 1)) == 0));\r
+ ASSERT (\r
+ ((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
+ ((Length & (EFI_PAGE_SIZE - 1)) == 0)\r
+ );\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16) sizeof (EFI_HOB_MEMORY_ALLOCATION_BSP_STORE));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16)sizeof (EFI_HOB_MEMORY_ALLOCATION_BSP_STORE));\r
if (Hob == NULL) {\r
return;\r
}\r
VOID\r
EFIAPI\r
BuildMemoryAllocationHob (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN EFI_MEMORY_TYPE MemoryType\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN EFI_MEMORY_TYPE MemoryType\r
)\r
{\r
EFI_HOB_MEMORY_ALLOCATION *Hob;\r
\r
- ASSERT (((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
- ((Length & (EFI_PAGE_SIZE - 1)) == 0));\r
+ ASSERT (\r
+ ((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&\r
+ ((Length & (EFI_PAGE_SIZE - 1)) == 0)\r
+ );\r
\r
- Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16) sizeof (EFI_HOB_MEMORY_ALLOCATION));\r
+ Hob = InternalPeiCreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, (UINT16)sizeof (EFI_HOB_MEMORY_ALLOCATION));\r
if (Hob == NULL) {\r
return;\r
}\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Library/IoLib.h>\r
UINT8\r
EFIAPI\r
IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+ return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT16\r
EFIAPI\r
IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+ return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT32\r
EFIAPI\r
IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
UINT32\r
EFIAPI\r
IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
UINT32\r
EFIAPI\r
IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT64\r
EFIAPI\r
IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
UINT64\r
EFIAPI\r
IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
UINT64\r
EFIAPI\r
IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT8\r
EFIAPI\r
MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT16\r
EFIAPI\r
MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT32\r
EFIAPI\r
MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT64\r
EFIAPI\r
MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
UINT64\r
EFIAPI\r
MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
UINT64\r
EFIAPI\r
MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Library/IoLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/PeiServicesTablePointerLib.h>\r
\r
-\r
/**\r
Reads registers in the EFI CPU I/O space.\r
\r
IN VOID *Buffer\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
- EFI_STATUS Status;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ EFI_STATUS Status;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
IN VOID *Buffer\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
- EFI_STATUS Status;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ EFI_STATUS Status;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
ASSERT (CpuIo != NULL);\r
\r
- return CpuIo->IoRead8 (PeiServices, CpuIo, (UINT64) Port);\r
+ return CpuIo->IoRead8 (PeiServices, CpuIo, (UINT64)Port);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
ASSERT (CpuIo != NULL);\r
\r
- CpuIo->IoWrite8 (PeiServices, CpuIo, (UINT64) Port, Value);\r
+ CpuIo->IoWrite8 (PeiServices, CpuIo, (UINT64)Port, Value);\r
return Value;\r
}\r
\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 16-bit boundary.\r
//\r
ASSERT ((Port & 1) == 0);\r
- return CpuIo->IoRead16 (PeiServices, CpuIo, (UINT64) Port);\r
+ return CpuIo->IoRead16 (PeiServices, CpuIo, (UINT64)Port);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 16-bit boundary.\r
//\r
ASSERT ((Port & 1) == 0);\r
- CpuIo->IoWrite16 (PeiServices, CpuIo, (UINT64) Port, Value);\r
+ CpuIo->IoWrite16 (PeiServices, CpuIo, (UINT64)Port, Value);\r
return Value;\r
}\r
\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 32-bit boundary.\r
//\r
ASSERT ((Port & 3) == 0);\r
- return CpuIo->IoRead32 (PeiServices, CpuIo, (UINT64) Port);\r
+ return CpuIo->IoRead32 (PeiServices, CpuIo, (UINT64)Port);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 32-bit boundary.\r
//\r
ASSERT ((Port & 3) == 0);\r
- CpuIo->IoWrite32 (PeiServices, CpuIo, (UINT64) Port, Value);\r
+ CpuIo->IoWrite32 (PeiServices, CpuIo, (UINT64)Port, Value);\r
return Value;\r
}\r
\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 64-bit boundary.\r
//\r
ASSERT ((Port & 7) == 0);\r
- return CpuIo->IoRead64 (PeiServices, CpuIo, (UINT64) Port);\r
+ return CpuIo->IoRead64 (PeiServices, CpuIo, (UINT64)Port);\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Port is aligned on a 64-bit boundary.\r
//\r
ASSERT ((Port & 7) == 0);\r
- CpuIo->IoWrite64 (PeiServices, CpuIo, (UINT64) Port, Value);\r
- return Value;;\r
+ CpuIo->IoWrite64 (PeiServices, CpuIo, (UINT64)Port, Value);\r
+ return Value;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
IoReadFifoWorker (Port, EfiPeiCpuIoWidthFifoUint8, Count, Buffer);\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
IoWriteFifoWorker (Port, EfiPeiCpuIoWidthFifoUint8, Count, Buffer);\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
//\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
ASSERT (CpuIo != NULL);\r
\r
- return CpuIo->MemRead8 (PeiServices, CpuIo, (UINT64) Address);\r
+ return CpuIo->MemRead8 (PeiServices, CpuIo, (UINT64)Address);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
ASSERT (CpuIo != NULL);\r
\r
- CpuIo->MemWrite8 (PeiServices, CpuIo, (UINT64) Address, Value);\r
+ CpuIo->MemWrite8 (PeiServices, CpuIo, (UINT64)Address, Value);\r
return Value;\r
}\r
\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 16-bit boundary.\r
//\r
ASSERT ((Address & 1) == 0);\r
- return CpuIo->MemRead16 (PeiServices, CpuIo, (UINT64) Address);\r
-\r
+ return CpuIo->MemRead16 (PeiServices, CpuIo, (UINT64)Address);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 16-bit boundary.\r
//\r
ASSERT ((Address & 1) == 0);\r
- CpuIo->MemWrite16 (PeiServices, CpuIo, (UINT64) Address, Value);\r
+ CpuIo->MemWrite16 (PeiServices, CpuIo, (UINT64)Address, Value);\r
return Value;\r
}\r
\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 32-bit boundary.\r
//\r
ASSERT ((Address & 3) == 0);\r
- return CpuIo->MemRead32 (PeiServices, CpuIo, (UINT64) Address);\r
-\r
+ return CpuIo->MemRead32 (PeiServices, CpuIo, (UINT64)Address);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 32-bit boundary.\r
//\r
ASSERT ((Address & 3) == 0);\r
- CpuIo->MemWrite32 (PeiServices, CpuIo, (UINT64) Address, Value);\r
+ CpuIo->MemWrite32 (PeiServices, CpuIo, (UINT64)Address, Value);\r
return Value;\r
}\r
\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 64-bit boundary.\r
//\r
ASSERT ((Address & (sizeof (UINT64) - 1)) == 0);\r
- return CpuIo->MemRead64 (PeiServices, CpuIo, (UINT64) Address);\r
-\r
+ return CpuIo->MemRead64 (PeiServices, CpuIo, (UINT64)Address);\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
- EFI_PEI_CPU_IO_PPI *CpuIo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+ EFI_PEI_CPU_IO_PPI *CpuIo;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
CpuIo = (*PeiServices)->CpuIo;\r
// Make sure Address is aligned on a 64-bit boundary.\r
//\r
ASSERT ((Address & 7) == 0);\r
- CpuIo->MemWrite64 (PeiServices, CpuIo, (UINT64) Address, Value);\r
+ CpuIo->MemWrite64 (PeiServices, CpuIo, (UINT64)Address, Value);\r
return Value;\r
}\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Library/IoLib.h>\r
UINT8 *\r
EFIAPI\r
MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ReturnBuffer = Buffer;\r
\r
UINT16 *\r
EFIAPI\r
MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead16 (StartAddress);\r
+ *(Buffer++) = MmioRead16 (StartAddress);\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
UINT32 *\r
EFIAPI\r
MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead32 (StartAddress);\r
+ *(Buffer++) = MmioRead32 (StartAddress);\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length != 0) {\r
- *(Buffer++) = MmioRead64 (StartAddress);\r
+ *(Buffer++) = MmioRead64 (StartAddress);\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 8-bit access.\r
\r
UINT8 *\r
EFIAPI\r
MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
)\r
{\r
- VOID* ReturnBuffer;\r
+ VOID *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- ReturnBuffer = (UINT8 *) Buffer;\r
+ ReturnBuffer = (UINT8 *)Buffer;\r
\r
while (Length-- != 0) {\r
- MmioWrite8 (StartAddress++, *(Buffer++));\r
+ MmioWrite8 (StartAddress++, *(Buffer++));\r
}\r
\r
return ReturnBuffer;\r
-\r
}\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT16 *) Buffer;\r
+ ReturnBuffer = (UINT16 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite16 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 32-bit access.\r
\r
UINT32 *\r
EFIAPI\r
MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT32 *) Buffer;\r
+ ReturnBuffer = (UINT32 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite32 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT64 *) Buffer;\r
+ ReturnBuffer = (UINT64 *)Buffer;\r
\r
while (Length != 0) {\r
MmioWrite64 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
-\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
-\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
\r
-\r
/**\r
Allocates one or more 4KB pages of a certain memory type.\r
\r
return NULL;\r
}\r
\r
- return (VOID *) (UINTN) Memory;\r
+ return (VOID *)(UINTN)Memory;\r
}\r
\r
/**\r
EFI_STATUS Status;\r
\r
ASSERT (Pages != 0);\r
- Status = PeiServicesFreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = PeiServicesFreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
if (Pages == 0) {\r
return NULL;\r
}\r
+\r
if (Alignment > EFI_PAGE_SIZE) {\r
//\r
// Calculate the total number of pages since alignment is larger than page size.\r
//\r
- AlignmentMask = Alignment - 1;\r
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
+ AlignmentMask = Alignment - 1;\r
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
//\r
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r
//\r
ASSERT (RealPages > Pages);\r
\r
- Status = PeiServicesAllocatePages (MemoryType, RealPages, &Memory);\r
+ Status = PeiServicesAllocatePages (MemoryType, RealPages, &Memory);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;\r
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);\r
+\r
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r
if (UnalignedPages > 0) {\r
//\r
// Free first unaligned page(s).\r
Status = PeiServicesFreePages (Memory, UnalignedPages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
+\r
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
UnalignedPages = RealPages - Pages - UnalignedPages;\r
if (UnalignedPages > 0) {\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = (UINTN) Memory;\r
+\r
+ AlignedMemory = (UINTN)Memory;\r
}\r
- return (VOID *) AlignedMemory;\r
+\r
+ return (VOID *)AlignedMemory;\r
}\r
\r
/**\r
EFI_STATUS Status;\r
\r
ASSERT (Pages != 0);\r
- Status = PeiServicesFreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = PeiServicesFreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
IN UINTN AllocationSize\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *Buffer;\r
+ EFI_STATUS Status;\r
+ VOID *Buffer;\r
\r
Status = PeiServicesAllocatePool (AllocationSize, &Buffer);\r
if (EFI_ERROR (Status)) {\r
Buffer = NULL;\r
}\r
+\r
return Buffer;\r
}\r
\r
if (Memory != NULL) {\r
Memory = ZeroMem (Memory, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
if (Memory != NULL) {\r
Memory = ZeroMem (Memory, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *Memory;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));\r
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
\r
Memory = InternalAllocatePool (PoolType, AllocationSize);\r
if (Memory != NULL) {\r
- Memory = CopyMem (Memory, Buffer, AllocationSize);\r
+ Memory = CopyMem (Memory, Buffer, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *Memory;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));\r
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
\r
Memory = AllocatePool (AllocationSize);\r
if (Memory != NULL) {\r
- Memory = CopyMem (Memory, Buffer, AllocationSize);\r
+ Memory = CopyMem (Memory, Buffer, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *NewBuffer;\r
\r
NewBuffer = InternalAllocateZeroPool (PoolType, NewSize);\r
- if (NewBuffer != NULL && OldBuffer != NULL) {\r
+ if ((NewBuffer != NULL) && (OldBuffer != NULL)) {\r
CopyMem (NewBuffer, OldBuffer, MIN (OldSize, NewSize));\r
FreePool (OldBuffer);\r
}\r
+\r
return NewBuffer;\r
}\r
\r
VOID\r
EFIAPI\r
FreePool (\r
- IN VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
//\r
// PEI phase does not support to free pool, so leave it as NOP.\r
//\r
}\r
-\r
-\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *Destination,\r
- IN CONST VOID *Source,\r
- IN UINTN Length\r
+ OUT VOID *Destination,\r
+ IN CONST VOID *Source,\r
+ IN UINTN Length\r
)\r
{\r
(*GetPeiServicesTablePointer ())->CopyMem (\r
Destination,\r
- (VOID*)Source,\r
+ (VOID *)Source,\r
Length\r
);\r
return Destination;\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Size,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Size,\r
+ IN UINT8 Value\r
)\r
{\r
(*GetPeiServicesTablePointer ())->SetMem (\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT16*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT16 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT32*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT32 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT64*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT64 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
return InternalMemSetMem (Buffer, Length, 0);\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
)\r
{\r
while ((--Length != 0) &&\r
- (*(INT8*)DestinationBuffer == *(INT8*)SourceBuffer)) {\r
- DestinationBuffer = (INT8*)DestinationBuffer + 1;\r
- SourceBuffer = (INT8*)SourceBuffer + 1;\r
+ (*(INT8 *)DestinationBuffer == *(INT8 *)SourceBuffer))\r
+ {\r
+ DestinationBuffer = (INT8 *)DestinationBuffer + 1;\r
+ SourceBuffer = (INT8 *)SourceBuffer + 1;\r
}\r
- return (INTN)*(UINT8*)DestinationBuffer - (INTN)*(UINT8*)SourceBuffer;\r
+\r
+ return (INTN)*(UINT8 *)DestinationBuffer - (INTN)*(UINT8 *)SourceBuffer;\r
}\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
)\r
{\r
- CONST UINT8 *Pointer;\r
+ CONST UINT8 *Pointer;\r
\r
- Pointer = (CONST UINT8*)Buffer;\r
+ Pointer = (CONST UINT8 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST UINT16 *Pointer;\r
+ CONST UINT16 *Pointer;\r
\r
- Pointer = (CONST UINT16*)Buffer;\r
+ Pointer = (CONST UINT16 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST UINT32 *Pointer;\r
+ CONST UINT32 *Pointer;\r
\r
- Pointer = (CONST UINT32*)Buffer;\r
+ Pointer = (CONST UINT32 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST UINT64 *Pointer;\r
+ CONST UINT64 *Pointer;\r
\r
- Pointer = (CONST UINT64*)Buffer;\r
+ Pointer = (CONST UINT64 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
IN UINTN Length\r
)\r
{\r
- CONST UINT8 *BufferData;\r
- UINTN Index;\r
+ CONST UINT8 *BufferData;\r
+ UINTN Index;\r
\r
BufferData = Buffer;\r
for (Index = 0; Index < Length; Index++) {\r
return FALSE;\r
}\r
}\r
+\r
return TRUE;\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *Destination,\r
- IN CONST VOID *Source,\r
- IN UINTN Length\r
+ OUT VOID *Destination,\r
+ IN CONST VOID *Source,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Size,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Size,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
\r
**/\r
\r
-\r
-\r
-\r
#include <PiPei.h>\r
\r
#include <Ppi/Pcd.h>\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- PCD_PPI *PcdPpi;\r
+ EFI_STATUS Status;\r
+ PCD_PPI *PcdPpi;\r
\r
Status = PeiServicesLocatePpi (&gPcdPpiGuid, 0, NULL, (VOID **)&PcdPpi);\r
ASSERT_EFI_ERROR (Status);\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PEI_PCD_PPI *PiPcdPpi;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_PCD_PPI *PiPcdPpi;\r
\r
Status = PeiServicesLocatePpi (&gEfiPeiPcdPpiGuid, 0, NULL, (VOID **)&PiPcdPpi);\r
ASSERT_EFI_ERROR (Status);\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- GET_PCD_INFO_PPI *PcdInfoPpi;\r
+ EFI_STATUS Status;\r
+ GET_PCD_INFO_PPI *PcdInfoPpi;\r
\r
Status = PeiServicesLocatePpi (&gGetPcdInfoPpiGuid, 0, NULL, (VOID **)&PcdInfoPpi);\r
ASSERT_EFI_ERROR (Status);\r
UINTN\r
EFIAPI\r
LibPcdSetSku (\r
- IN UINTN SkuId\r
+ IN UINTN SkuId\r
)\r
{\r
- GetPiPcdPpiPointer()->SetSku (SkuId);\r
+ GetPiPcdPpiPointer ()->SetSku (SkuId);\r
\r
return SkuId;\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGet8 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->Get8 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGet16 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->Get16 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT32\r
EFIAPI\r
LibPcdGet32 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->Get32 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGet64 (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->Get64 (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetPtr (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->GetPtr (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetBool (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->GetBool (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetSize (\r
- IN UINTN TokenNumber\r
+ IN UINTN TokenNumber\r
)\r
{\r
return (GetPcdPpiPointer ())->GetSize (TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT8\r
EFIAPI\r
LibPcdGetEx8 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->Get8 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT16\r
EFIAPI\r
LibPcdGetEx16 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
-\r
ASSERT (Guid != NULL);\r
\r
return (GetPiPcdPpiPointer ())->Get16 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
Returns the 32-bit value for the token specified by TokenNumber and Guid.\r
If Guid is NULL, then ASSERT().\r
UINT32\r
EFIAPI\r
LibPcdGetEx32 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->Get32 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
UINT64\r
EFIAPI\r
LibPcdGetEx64 (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->Get64 (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
VOID *\r
EFIAPI\r
LibPcdGetExPtr (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->GetPtr (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve a value for a given PCD token.\r
\r
BOOLEAN\r
EFIAPI\r
LibPcdGetExBool (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->GetBool (Guid, TokenNumber);\r
}\r
\r
-\r
-\r
/**\r
This function provides a means by which to retrieve the size of a given PCD token.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetExSize (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber\r
)\r
{\r
ASSERT (Guid != NULL);\r
return (GetPiPcdPpiPointer ())->GetSize (Guid, TokenNumber);\r
}\r
\r
-\r
/**\r
This function provides a means by which to set a value for a given PCD token.\r
\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet8S (\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
return (GetPcdPpiPointer ())->Set8 (TokenNumber, Value);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet16S (\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
return (GetPcdPpiPointer ())->Set16 (TokenNumber, Value);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet32S (\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
return (GetPcdPpiPointer ())->Set32 (TokenNumber, Value);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSet64S (\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
return (GetPcdPpiPointer ())->Set64 (TokenNumber, Value);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetPtrS (\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (SizeOfBuffer != NULL);\r
ASSERT (Buffer != NULL);\r
}\r
\r
- return (GetPcdPpiPointer ())->SetPtr (TokenNumber, SizeOfBuffer, (VOID *) Buffer);\r
+ return (GetPcdPpiPointer ())->SetPtr (TokenNumber, SizeOfBuffer, (VOID *)Buffer);\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetBoolS (\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
return (GetPcdPpiPointer ())->SetBool (TokenNumber, Value);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx8S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT8 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx16S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT16 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx32S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT32 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetEx64S (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN UINT64 Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN UINT64 Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExPtrS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN VOID *Buffer\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN VOID *Buffer\r
)\r
{\r
ASSERT (Guid != NULL);\r
RETURN_STATUS\r
EFIAPI\r
LibPcdSetExBoolS (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- IN BOOLEAN Value\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ IN BOOLEAN Value\r
)\r
{\r
ASSERT (Guid != NULL);\r
VOID\r
EFIAPI\r
LibPcdCallbackOnSet (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT (NotificationFunction != NULL);\r
\r
- Status = (GetPiPcdPpiPointer ())->CallbackOnSet (Guid, TokenNumber, (EFI_PEI_PCD_PPI_CALLBACK) NotificationFunction);\r
+ Status = (GetPiPcdPpiPointer ())->CallbackOnSet (Guid, TokenNumber, (EFI_PEI_PCD_PPI_CALLBACK)NotificationFunction);\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
return;\r
}\r
\r
-\r
-\r
/**\r
Disable a notification function that was established with LibPcdCallbackonSet().\r
\r
VOID\r
EFIAPI\r
LibPcdCancelCallback (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber,\r
- IN PCD_CALLBACK NotificationFunction\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber,\r
+ IN PCD_CALLBACK NotificationFunction\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT (NotificationFunction != NULL);\r
\r
- Status = (GetPiPcdPpiPointer ())->CancelCallback (Guid, TokenNumber, (EFI_PEI_PCD_PPI_CALLBACK) NotificationFunction);\r
+ Status = (GetPiPcdPpiPointer ())->CancelCallback (Guid, TokenNumber, (EFI_PEI_PCD_PPI_CALLBACK)NotificationFunction);\r
\r
ASSERT_EFI_ERROR (Status);\r
\r
return;\r
}\r
\r
-\r
-\r
/**\r
Retrieves the next token in a token space.\r
\r
UINTN\r
EFIAPI\r
LibPcdGetNextToken (\r
- IN CONST GUID *Guid OPTIONAL,\r
- IN UINTN TokenNumber\r
+ IN CONST GUID *Guid OPTIONAL,\r
+ IN UINTN TokenNumber\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = (GetPiPcdPpiPointer ())->GetNextToken (Guid, &TokenNumber);\r
ASSERT (!EFI_ERROR (Status) || TokenNumber == 0);\r
return TokenNumber;\r
}\r
\r
-\r
/**\r
Used to retrieve the list of available PCD token space GUIDs.\r
\r
{\r
(GetPiPcdPpiPointer ())->GetNextTokenSpace (&TokenSpaceGuid);\r
\r
- return (GUID *) TokenSpaceGuid;\r
+ return (GUID *)TokenSpaceGuid;\r
}\r
\r
-\r
-\r
/**\r
Sets a value of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtr (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrS (\r
- OUT VOID *PatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
return RETURN_SUCCESS;\r
}\r
\r
-\r
/**\r
Sets a value and size of a patchable PCD entry that is type pointer.\r
\r
VOID *\r
EFIAPI\r
LibPatchPcdSetPtrAndSize (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return NULL;\r
}\r
CopyMem (PatchVariable, Buffer, *SizeOfBuffer);\r
*SizeOfPatchVariable = *SizeOfBuffer;\r
\r
- return (VOID *) Buffer;\r
+ return (VOID *)Buffer;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
LibPatchPcdSetPtrAndSizeS (\r
- OUT VOID *PatchVariable,\r
- OUT UINTN *SizeOfPatchVariable,\r
- IN UINTN MaximumDatumSize,\r
- IN OUT UINTN *SizeOfBuffer,\r
- IN CONST VOID *Buffer\r
+ OUT VOID *PatchVariable,\r
+ OUT UINTN *SizeOfPatchVariable,\r
+ IN UINTN MaximumDatumSize,\r
+ IN OUT UINTN *SizeOfBuffer,\r
+ IN CONST VOID *Buffer\r
)\r
{\r
ASSERT (PatchVariable != NULL);\r
}\r
\r
if ((*SizeOfBuffer > MaximumDatumSize) ||\r
- (*SizeOfBuffer == MAX_ADDRESS)) {\r
+ (*SizeOfBuffer == MAX_ADDRESS))\r
+ {\r
*SizeOfBuffer = MaximumDatumSize;\r
return RETURN_INVALID_PARAMETER;\r
}\r
VOID\r
EFIAPI\r
LibPcdGetInfo (\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = GetPcdInfoPpiPointer()->GetInfo (TokenNumber, (EFI_PCD_INFO *) PcdInfo);\r
+ Status = GetPcdInfoPpiPointer ()->GetInfo (TokenNumber, (EFI_PCD_INFO *)PcdInfo);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
EFIAPI\r
LibPcdGetInfoEx (\r
- IN CONST GUID *Guid,\r
- IN UINTN TokenNumber,\r
- OUT PCD_INFO *PcdInfo\r
+ IN CONST GUID *Guid,\r
+ IN UINTN TokenNumber,\r
+ OUT PCD_INFO *PcdInfo\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = GetPiPcdInfoPpiPointer()->GetInfo (Guid, TokenNumber, (EFI_PCD_INFO *) PcdInfo);\r
+ Status = GetPiPcdInfoPpiPointer ()->GetInfo (Guid, TokenNumber, (EFI_PCD_INFO *)PcdInfo);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
)\r
{\r
- return GetPiPcdInfoPpiPointer()->GetSku ();\r
+ return GetPiPcdInfoPpiPointer ()->GetSku ();\r
}\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r
ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
\r
/**\r
**/\r
UINT32\r
PeiPciLibPciCfg2ReadWorker (\r
- IN UINTN Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
+ IN UINTN Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 Data;\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ EFI_STATUS Status;\r
+ UINT32 Data;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r
+ Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **)&PciCfg2Ppi);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (PciCfg2Ppi != NULL);\r
\r
**/\r
UINT32\r
PeiPciLibPciCfg2WriteWorker (\r
- IN UINTN Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
- IN UINT32 Data\r
+ IN UINTN Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT32 Data\r
)\r
{\r
- EFI_STATUS Status;\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ EFI_STATUS Status;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r
+ Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **)&PciCfg2Ppi);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (PciCfg2Ppi != NULL);\r
\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
+ return (UINT8)PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
+ return (UINT8)PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+ return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
+ return (UINT16)PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
+ return (UINT16)PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+ return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \\r
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
\r
/**\r
**/\r
EFI_PEI_PCI_CFG2_PPI *\r
InternalGetPciCfg2Ppi (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Instance;\r
- EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 SegmentNumber;\r
+ EFI_STATUS Status;\r
+ UINTN Instance;\r
+ EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 SegmentNumber;\r
\r
Instance = 0;\r
PciCfg2Ppi = NULL;\r
// Loop through all instances of the PPI and match segment number\r
//\r
do {\r
- Status = PeiServicesLocatePpi(\r
+ Status = PeiServicesLocatePpi (\r
&gEfiPciCfg2PpiGuid,\r
Instance,\r
NULL,\r
- (VOID**) &PciCfg2Ppi\r
+ (VOID **)&PciCfg2Ppi\r
);\r
ASSERT_EFI_ERROR (Status);\r
Instance++;\r
**/\r
UINT32\r
PeiPciSegmentLibPciCfg2ReadWorker (\r
- IN UINT64 Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
+ IN UINT64 Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r
)\r
{\r
- UINT32 Data;\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ UINT32 Data;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
+ PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
PciCfg2Ppi->Read (\r
GetPeiServicesTablePointer (),\r
**/\r
UINT32\r
PeiPciSegmentLibPciCfg2WriteWorker (\r
- IN UINT64 Address,\r
- IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
- IN UINT32 Data\r
+ IN UINT64 Address,\r
+ IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r
+ IN UINT32 Data\r
)\r
{\r
- CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
- UINT64 PciCfg2Address;\r
+ CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r
+ UINT64 PciCfg2Address;\r
\r
- PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
+ PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r
PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r
PciCfg2Ppi->Write (\r
GetPeiServicesTablePointer (),\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
+ return (UINT8)PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
+ return (UINT8)PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
+ return (UINT16)PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
+ return (UINT16)PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
return ReturnValue;\r
}\r
\r
-\r
/**\r
Copies the data in a caller supplied buffer to a specified range of PCI\r
configuration space.\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
\r
**/\r
\r
-\r
-\r
#include <PiPei.h>\r
\r
-\r
#include <Library/ResourcePublicationLib.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/DebugLib.h>\r
\r
-\r
/**\r
Declares the presence of permanent system memory in the platform.\r
\r
RETURN_STATUS\r
EFIAPI\r
PublishSystemMemory (\r
- IN PHYSICAL_ADDRESS MemoryBegin,\r
- IN UINT64 MemoryLength\r
+ IN PHYSICAL_ADDRESS MemoryBegin,\r
+ IN UINT64 MemoryLength\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT (MemoryLength > 0);\r
ASSERT (MemoryLength <= (MAX_ADDRESS - MemoryBegin + 1));\r
\r
- Status = PeiServicesInstallPeiMemory (MemoryBegin, MemoryLength);\r
+ Status = PeiServicesInstallPeiMemory (MemoryBegin, MemoryLength);\r
\r
- return (RETURN_STATUS) Status;\r
+ return (RETURN_STATUS)Status;\r
}\r
-\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Ppi/FirmwareVolumeInfo.h>\r
EFI_STATUS\r
EFIAPI\r
PeiServicesInstallPpi (\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList\r
)\r
{\r
CONST EFI_PEI_SERVICES **PeiServices;\r
EFI_STATUS\r
EFIAPI\r
PeiServicesReInstallPpi (\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,\r
- IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *OldPpi,\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *NewPpi\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->ReInstallPpi (PeiServices, OldPpi, NewPpi);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesLocatePpi (\r
- IN CONST EFI_GUID *Guid,\r
- IN UINTN Instance,\r
- IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,\r
- IN OUT VOID **Ppi\r
+ IN CONST EFI_GUID *Guid,\r
+ IN UINTN Instance,\r
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor OPTIONAL,\r
+ IN OUT VOID **Ppi\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->LocatePpi (PeiServices, Guid, Instance, PpiDescriptor, Ppi);\r
IN CONST EFI_PEI_NOTIFY_DESCRIPTOR *NotifyList\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->NotifyPpi (PeiServices, NotifyList);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesGetBootMode (\r
- OUT EFI_BOOT_MODE *BootMode\r
+ OUT EFI_BOOT_MODE *BootMode\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->GetBootMode (PeiServices, BootMode);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesSetBootMode (\r
- IN EFI_BOOT_MODE BootMode\r
+ IN EFI_BOOT_MODE BootMode\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->SetBootMode (PeiServices, BootMode);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesGetHobList (\r
- OUT VOID **HobList\r
+ OUT VOID **HobList\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->GetHobList (PeiServices, HobList);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesCreateHob (\r
- IN UINT16 Type,\r
- IN UINT16 Length,\r
- OUT VOID **Hob\r
+ IN UINT16 Type,\r
+ IN UINT16 Length,\r
+ OUT VOID **Hob\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->CreateHob (PeiServices, Type, Length, Hob);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindNextVolume (\r
- IN UINTN Instance,\r
- IN OUT EFI_PEI_FV_HANDLE *VolumeHandle\r
+ IN UINTN Instance,\r
+ IN OUT EFI_PEI_FV_HANDLE *VolumeHandle\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->FfsFindNextVolume (PeiServices, Instance, VolumeHandle);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindNextFile (\r
- IN EFI_FV_FILETYPE SearchType,\r
- IN EFI_PEI_FV_HANDLE VolumeHandle,\r
- IN OUT EFI_PEI_FILE_HANDLE *FileHandle\r
+ IN EFI_FV_FILETYPE SearchType,\r
+ IN EFI_PEI_FV_HANDLE VolumeHandle,\r
+ IN OUT EFI_PEI_FILE_HANDLE *FileHandle\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->FfsFindNextFile (PeiServices, SearchType, VolumeHandle, FileHandle);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindSectionData (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT VOID **SectionData\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT VOID **SectionData\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->FfsFindSectionData (PeiServices, SectionType, FileHandle, SectionData);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindSectionData3 (\r
- IN EFI_SECTION_TYPE SectionType,\r
- IN UINTN SectionInstance,\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT VOID **SectionData,\r
- OUT UINT32 *AuthenticationStatus\r
+ IN EFI_SECTION_TYPE SectionType,\r
+ IN UINTN SectionInstance,\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT VOID **SectionData,\r
+ OUT UINT32 *AuthenticationStatus\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->FindSectionData3 (PeiServices, SectionType, SectionInstance, FileHandle, SectionData, AuthenticationStatus);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesInstallPeiMemory (\r
- IN EFI_PHYSICAL_ADDRESS MemoryBegin,\r
- IN UINT64 MemoryLength\r
+ IN EFI_PHYSICAL_ADDRESS MemoryBegin,\r
+ IN UINT64 MemoryLength\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->InstallPeiMemory (PeiServices, MemoryBegin, MemoryLength);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesAllocatePages (\r
- IN EFI_MEMORY_TYPE MemoryType,\r
- IN UINTN Pages,\r
- OUT EFI_PHYSICAL_ADDRESS *Memory\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT EFI_PHYSICAL_ADDRESS *Memory\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->AllocatePages (PeiServices, MemoryType, Pages, Memory);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFreePages (\r
- IN EFI_PHYSICAL_ADDRESS Memory,\r
- IN UINTN Pages\r
+ IN EFI_PHYSICAL_ADDRESS Memory,\r
+ IN UINTN Pages\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->FreePages (PeiServices, Memory, Pages);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesAllocatePool (\r
- IN UINTN Size,\r
- OUT VOID **Buffer\r
+ IN UINTN Size,\r
+ OUT VOID **Buffer\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->AllocatePool (PeiServices, Size, Buffer);\r
VOID\r
)\r
{\r
- CONST EFI_PEI_SERVICES **PeiServices;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
\r
PeiServices = GetPeiServicesTablePointer ();\r
return (*PeiServices)->ResetSystem (PeiServices);\r
EFI_STATUS\r
EFIAPI\r
PeiServicesRegisterForShadow (\r
- IN EFI_PEI_FILE_HANDLE FileHandle\r
+ IN EFI_PEI_FILE_HANDLE FileHandle\r
)\r
{\r
- return (*GetPeiServicesTablePointer())->RegisterForShadow (FileHandle);\r
+ return (*GetPeiServicesTablePointer ())->RegisterForShadow (FileHandle);\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetFileInfo (\r
- IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT EFI_FV_FILE_INFO *FileInfo\r
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT EFI_FV_FILE_INFO *FileInfo\r
)\r
{\r
- return (*GetPeiServicesTablePointer())->FfsGetFileInfo (FileHandle, FileInfo);\r
+ return (*GetPeiServicesTablePointer ())->FfsGetFileInfo (FileHandle, FileInfo);\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetFileInfo2 (\r
- IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
- OUT EFI_FV_FILE_INFO2 *FileInfo\r
+ IN CONST EFI_PEI_FILE_HANDLE FileHandle,\r
+ OUT EFI_FV_FILE_INFO2 *FileInfo\r
)\r
{\r
- return (*GetPeiServicesTablePointer())->FfsGetFileInfo2 (FileHandle, FileInfo);\r
+ return (*GetPeiServicesTablePointer ())->FfsGetFileInfo2 (FileHandle, FileInfo);\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsFindFileByName (\r
- IN CONST EFI_GUID *FileName,\r
- IN CONST EFI_PEI_FV_HANDLE VolumeHandle,\r
- OUT EFI_PEI_FILE_HANDLE *FileHandle\r
+ IN CONST EFI_GUID *FileName,\r
+ IN CONST EFI_PEI_FV_HANDLE VolumeHandle,\r
+ OUT EFI_PEI_FILE_HANDLE *FileHandle\r
)\r
{\r
- return (*GetPeiServicesTablePointer())->FfsFindFileByName (FileName, VolumeHandle, FileHandle);\r
+ return (*GetPeiServicesTablePointer ())->FfsFindFileByName (FileName, VolumeHandle, FileHandle);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the PEI Service FfsGetVolumeInfo(), except the pointer to the PEI Services\r
Table has been removed. See the Platform Initialization Pre-EFI Initialization Core Interface\r
EFI_STATUS\r
EFIAPI\r
PeiServicesFfsGetVolumeInfo (\r
- IN EFI_PEI_FV_HANDLE VolumeHandle,\r
- OUT EFI_FV_INFO *VolumeInfo\r
+ IN EFI_PEI_FV_HANDLE VolumeHandle,\r
+ OUT EFI_FV_INFO *VolumeInfo\r
)\r
{\r
- return (*GetPeiServicesTablePointer())->FfsGetVolumeInfo (VolumeHandle, VolumeInfo);\r
+ return (*GetPeiServicesTablePointer ())->FfsGetVolumeInfo (VolumeHandle, VolumeInfo);\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
InternalPeiServicesInstallFvInfoPpi (\r
- IN BOOLEAN InstallFvInfoPpi,\r
- IN CONST EFI_GUID *FvFormat OPTIONAL,\r
- IN CONST VOID *FvInfo,\r
- IN UINT32 FvInfoSize,\r
- IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
- IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
- IN UINT32 AuthenticationStatus\r
+ IN BOOLEAN InstallFvInfoPpi,\r
+ IN CONST EFI_GUID *FvFormat OPTIONAL,\r
+ IN CONST VOID *FvInfo,\r
+ IN UINT32 FvInfoSize,\r
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
+ IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
+ IN UINT32 AuthenticationStatus\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *FvInfoPpi;\r
- EFI_PEI_PPI_DESCRIPTOR *FvInfoPpiDescriptor;\r
- EFI_GUID *ParentFvNameValue;\r
- EFI_GUID *ParentFileNameValue;\r
- EFI_GUID *PpiGuid;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *FvInfoPpi;\r
+ EFI_PEI_PPI_DESCRIPTOR *FvInfoPpiDescriptor;\r
+ EFI_GUID *ParentFvNameValue;\r
+ EFI_GUID *ParentFileNameValue;\r
+ EFI_GUID *PpiGuid;\r
\r
ParentFvNameValue = NULL;\r
ParentFileNameValue = NULL;\r
//\r
FvInfoPpi = AllocateZeroPool (sizeof (EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI));\r
ASSERT (FvInfoPpi != NULL);\r
- ((EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *) FvInfoPpi)->AuthenticationStatus = AuthenticationStatus;\r
- PpiGuid = &gEfiPeiFirmwareVolumeInfo2PpiGuid;\r
+ ((EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *)FvInfoPpi)->AuthenticationStatus = AuthenticationStatus;\r
+ PpiGuid = &gEfiPeiFirmwareVolumeInfo2PpiGuid;\r
}\r
\r
if (FvFormat != NULL) {\r
// ((EFI_FIRMWARE_VOLUME_HEADER *) FvInfo)->FileSystemGuid can be just used for both\r
// firmware file system 2 and 3 format.\r
//\r
- ASSERT (CompareGuid (&(((EFI_FIRMWARE_VOLUME_HEADER *) FvInfo)->FileSystemGuid), &gEfiFirmwareFileSystem2Guid));\r
+ ASSERT (CompareGuid (&(((EFI_FIRMWARE_VOLUME_HEADER *)FvInfo)->FileSystemGuid), &gEfiFirmwareFileSystem2Guid));\r
}\r
- FvInfoPpi->FvInfo = (VOID *) FvInfo;\r
+\r
+ FvInfoPpi->FvInfo = (VOID *)FvInfo;\r
FvInfoPpi->FvInfoSize = FvInfoSize;\r
if (ParentFvName != NULL) {\r
ParentFvNameValue = AllocateCopyPool (sizeof (EFI_GUID), ParentFvName);\r
ASSERT (ParentFvNameValue != NULL);\r
FvInfoPpi->ParentFvName = ParentFvNameValue;\r
}\r
+\r
if (ParentFileName != NULL) {\r
ParentFileNameValue = AllocateCopyPool (sizeof (EFI_GUID), ParentFileName);\r
ASSERT (ParentFileNameValue != NULL);\r
\r
FvInfoPpiDescriptor->Guid = PpiGuid;\r
FvInfoPpiDescriptor->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
- FvInfoPpiDescriptor->Ppi = (VOID *) FvInfoPpi;\r
- Status = PeiServicesInstallPpi (FvInfoPpiDescriptor);\r
+ FvInfoPpiDescriptor->Ppi = (VOID *)FvInfoPpi;\r
+ Status = PeiServicesInstallPpi (FvInfoPpiDescriptor);\r
ASSERT_EFI_ERROR (Status);\r
-\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
PeiServicesInstallFvInfoPpi (\r
- IN CONST EFI_GUID *FvFormat OPTIONAL,\r
- IN CONST VOID *FvInfo,\r
- IN UINT32 FvInfoSize,\r
- IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
- IN CONST EFI_GUID *ParentFileName OPTIONAL\r
+ IN CONST EFI_GUID *FvFormat OPTIONAL,\r
+ IN CONST VOID *FvInfo,\r
+ IN UINT32 FvInfoSize,\r
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
+ IN CONST EFI_GUID *ParentFileName OPTIONAL\r
)\r
{\r
InternalPeiServicesInstallFvInfoPpi (TRUE, FvFormat, FvInfo, FvInfoSize, ParentFvName, ParentFileName, 0);\r
VOID\r
EFIAPI\r
PeiServicesInstallFvInfo2Ppi (\r
- IN CONST EFI_GUID *FvFormat OPTIONAL,\r
- IN CONST VOID *FvInfo,\r
- IN UINT32 FvInfoSize,\r
- IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
- IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
- IN UINT32 AuthenticationStatus\r
+ IN CONST EFI_GUID *FvFormat OPTIONAL,\r
+ IN CONST VOID *FvInfo,\r
+ IN UINT32 FvInfoSize,\r
+ IN CONST EFI_GUID *ParentFvName OPTIONAL,\r
+ IN CONST EFI_GUID *ParentFileName OPTIONAL,\r
+ IN UINT32 AuthenticationStatus\r
)\r
{\r
InternalPeiServicesInstallFvInfoPpi (FALSE, FvFormat, FvInfo, FvInfoSize, ParentFvName, ParentFileName, AuthenticationStatus);\r
VOID\r
EFIAPI\r
PeiServicesResetSystem2 (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN VOID *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData OPTIONAL\r
)\r
{\r
- (*GetPeiServicesTablePointer())->ResetSystem2 (ResetType, ResetStatus, DataSize, ResetData);\r
+ (*GetPeiServicesTablePointer ())->ResetSystem2 (ResetType, ResetStatus, DataSize, ResetData);\r
}\r
VOID\r
EFIAPI\r
SetPeiServicesTablePointer (\r
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer\r
)\r
{\r
ASSERT (PeiServicesTablePointer != NULL);\r
return gPeiServices;\r
}\r
\r
-\r
/**\r
The constructor function caches the pointer to PEI services.\r
\r
EFI_STATUS\r
EFIAPI\r
PeiServicesTablePointerLibConstructor (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
gPeiServices = PeiServices;\r
)\r
{\r
CONST EFI_PEI_SERVICES **PeiServices;\r
- IA32_DESCRIPTOR Idtr;\r
+ IA32_DESCRIPTOR Idtr;\r
\r
AsmReadIdtr (&Idtr);\r
- PeiServices = (CONST EFI_PEI_SERVICES **) (*(UINTN*)(Idtr.Base - sizeof (UINTN)));\r
+ PeiServices = (CONST EFI_PEI_SERVICES **)(*(UINTN *)(Idtr.Base - sizeof (UINTN)));\r
ASSERT (PeiServices != NULL);\r
return PeiServices;\r
}\r
VOID\r
EFIAPI\r
SetPeiServicesTablePointer (\r
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer\r
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer\r
)\r
{\r
- IA32_DESCRIPTOR Idtr;\r
+ IA32_DESCRIPTOR Idtr;\r
\r
ASSERT (PeiServicesTablePointer != NULL);\r
AsmReadIdtr (&Idtr);\r
- (*(UINTN*)(Idtr.Base - sizeof (UINTN))) = (UINTN)PeiServicesTablePointer;\r
+ (*(UINTN *)(Idtr.Base - sizeof (UINTN))) = (UINTN)PeiServicesTablePointer;\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- IA32_DESCRIPTOR Idtr;\r
- EFI_PHYSICAL_ADDRESS IdtBase;\r
+ EFI_STATUS Status;\r
+ IA32_DESCRIPTOR Idtr;\r
+ EFI_PHYSICAL_ADDRESS IdtBase;\r
CONST EFI_PEI_SERVICES **PeiServices;\r
\r
//\r
// Get PEI Services Table pointer\r
//\r
AsmReadIdtr (&Idtr);\r
- PeiServices = (CONST EFI_PEI_SERVICES **) (*(UINTN*)(Idtr.Base - sizeof (UINTN)));\r
+ PeiServices = (CONST EFI_PEI_SERVICES **)(*(UINTN *)(Idtr.Base - sizeof (UINTN)));\r
ASSERT (PeiServices != NULL);\r
//\r
// Allocate the permanent memory.\r
//\r
Status = (*PeiServices)->AllocatePages (\r
- PeiServices,\r
- EfiBootServicesCode,\r
- EFI_SIZE_TO_PAGES(Idtr.Limit + 1 + sizeof (UINTN)),\r
- &IdtBase\r
- );\r
+ PeiServices,\r
+ EfiBootServicesCode,\r
+ EFI_SIZE_TO_PAGES (Idtr.Limit + 1 + sizeof (UINTN)),\r
+ &IdtBase\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
//\r
// Idt table needs to be migrated into memory.\r
//\r
- CopyMem ((VOID *) (UINTN) IdtBase, (VOID *) (Idtr.Base - sizeof (UINTN)), Idtr.Limit + 1 + sizeof (UINTN));\r
- Idtr.Base = (UINTN) IdtBase + sizeof (UINTN);\r
+ CopyMem ((VOID *)(UINTN)IdtBase, (VOID *)(Idtr.Base - sizeof (UINTN)), Idtr.Limit + 1 + sizeof (UINTN));\r
+ Idtr.Base = (UINTN)IdtBase + sizeof (UINTN);\r
AsmWriteIdtr (&Idtr);\r
\r
return;\r
}\r
-\r
-\r
#ifndef __INTERNAL_SMBUS_LIB_H_\r
#define __INTERNAL_SMBUS_LIB_H_\r
\r
-\r
#include <PiPei.h>\r
\r
#include <Ppi/Smbus2.h>\r
**/\r
UINTN\r
InternalSmBusExec (\r
- IN EFI_SMBUS_OPERATION SmbusOperation,\r
- IN UINTN SmBusAddress,\r
- IN UINTN Length,\r
- IN OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN EFI_SMBUS_OPERATION SmbusOperation,\r
+ IN UINTN SmBusAddress,\r
+ IN UINTN Length,\r
+ IN OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
);\r
\r
#endif\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_PEI_SMBUS2_PPI *SmbusPpi;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_SMBUS2_PPI *SmbusPpi;\r
\r
- Status = PeiServicesLocatePpi (&gEfiPeiSmbus2PpiGuid, 0, NULL, (VOID **) &SmbusPpi);\r
+ Status = PeiServicesLocatePpi (&gEfiPeiSmbus2PpiGuid, 0, NULL, (VOID **)&SmbusPpi);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (SmbusPpi != NULL);\r
\r
**/\r
UINTN\r
InternalSmBusExec (\r
- IN EFI_SMBUS_OPERATION SmbusOperation,\r
- IN UINTN SmBusAddress,\r
- IN UINTN Length,\r
- IN OUT VOID *Buffer,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN EFI_SMBUS_OPERATION SmbusOperation,\r
+ IN UINTN SmBusAddress,\r
+ IN UINTN Length,\r
+ IN OUT VOID *Buffer,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
EFI_PEI_SMBUS2_PPI *SmbusPpi;\r
RETURN_STATUS ReturnStatus;\r
EFI_SMBUS_DEVICE_ADDRESS SmbusDeviceAddress;\r
\r
- SmbusPpi = InternalGetSmbusPpi ();\r
+ SmbusPpi = InternalGetSmbusPpi ();\r
SmbusDeviceAddress.SmbusDeviceAddress = SMBUS_LIB_SLAVE_ADDRESS (SmBusAddress);\r
\r
ReturnStatus = SmbusPpi->Execute (\r
VOID\r
EFIAPI\r
SmBusQuickRead (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
VOID\r
EFIAPI\r
SmBusQuickWrite (\r
- IN UINTN SmBusAddress,\r
- OUT RETURN_STATUS *Status OPTIONAL\r
+ IN UINTN SmBusAddress,\r
+ OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
\r
- Byte = Value;\r
+ Byte = Value;\r
InternalSmBusExec (EfiSmbusSendByte, SmBusAddress, 1, &Byte, Status);\r
\r
return Value;\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINT8 Byte;\r
+ UINT8 Byte;\r
\r
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
OUT RETURN_STATUS *Status OPTIONAL\r
)\r
{\r
- UINTN Length;\r
+ UINTN Length;\r
\r
ASSERT (WriteBuffer != NULL);\r
ASSERT (ReadBuffer != NULL);\r
\r
**/\r
\r
-\r
#include <PiPei.h>\r
\r
-\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/DebugLib.h>\r
\r
EFI_STATUS\r
EFIAPI\r
_ModuleEntryPoint (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
if (_gPeimRevision != 0) {\r
return ProcessModuleEntryPointList (FileHandle, PeiServices);\r
}\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiMain (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
return _ModuleEntryPoint (FileHandle, PeiServices);\r
return TRUE;\r
}\r
\r
- /**\r
- Trace IO Write operation after wirte IO port.\r
- It is used to trace IO operation.\r
+/**\r
+Trace IO Write operation after wirte IO port.\r
+It is used to trace IO operation.\r
\r
- @param[in] Width Signifies the width of the I/O operation.\r
- @param[in] Address The base address of the I/O operation.\r
- @param[in] Buffer The source buffer from which to Write data.\r
+@param[in] Width Signifies the width of the I/O operation.\r
+@param[in] Address The base address of the I/O operation.\r
+@param[in] Buffer The source buffer from which to Write data.\r
\r
**/\r
VOID\r
BOOLEAN\r
EFIAPI\r
FilterBeforeMsrRead (\r
- IN UINT32 Index,\r
- IN OUT UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN OUT UINT64 *Value\r
)\r
{\r
return TRUE;\r
VOID\r
EFIAPI\r
FilterAfterMsrRead (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
)\r
{\r
return;\r
BOOLEAN\r
EFIAPI\r
FilterBeforeMsrWrite (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
)\r
{\r
return TRUE;\r
VOID\r
EFIAPI\r
FilterAfterMsrWrite (\r
- IN UINT32 Index,\r
- IN UINT64 *Value\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
)\r
{\r
return;\r
}\r
-\r
#include <Library/PcdLib.h>\r
#include <Library/DebugLib.h>\r
\r
-#define APIC_SVR 0x0f0\r
-#define APIC_LVTERR 0x370\r
-#define APIC_TMICT 0x380\r
-#define APIC_TMCCT 0x390\r
-#define APIC_TDCR 0x3e0\r
+#define APIC_SVR 0x0f0\r
+#define APIC_LVTERR 0x370\r
+#define APIC_TMICT 0x380\r
+#define APIC_TMCCT 0x390\r
+#define APIC_TDCR 0x3e0\r
\r
//\r
// The following array is used in calculating the frequency of local APIC\r
// timer. Refer to IA-32 developers' manual for more details.\r
//\r
GLOBAL_REMOVE_IF_UNREFERENCED\r
-CONST UINT8 mTimerLibLocalApicDivisor[] = {\r
+CONST UINT8 mTimerLibLocalApicDivisor[] = {\r
0x02, 0x04, 0x08, 0x10,\r
0x02, 0x04, 0x08, 0x10,\r
0x20, 0x40, 0x80, 0x01,\r
VOID\r
)\r
{\r
- UINTN MsrValue;\r
- UINTN ApicBase;\r
+ UINTN MsrValue;\r
+ UINTN ApicBase;\r
\r
- MsrValue = (UINTN) AsmReadMsr64 (27);\r
+ MsrValue = (UINTN)AsmReadMsr64 (27);\r
ApicBase = MsrValue & 0xffffff000ULL;\r
\r
//\r
UINT32\r
EFIAPI\r
InternalX86GetTimerFrequency (\r
- IN UINTN ApicBase\r
+ IN UINTN ApicBase\r
)\r
{\r
return\r
- PcdGet32(PcdFSBClock) /\r
+ PcdGet32 (PcdFSBClock) /\r
mTimerLibLocalApicDivisor[MmioBitFieldRead32 (ApicBase + APIC_TDCR, 0, 3)];\r
}\r
\r
INT32\r
EFIAPI\r
InternalX86GetTimerTick (\r
- IN UINTN ApicBase\r
+ IN UINTN ApicBase\r
)\r
{\r
return MmioRead32 (ApicBase + APIC_TMCCT);\r
**/\r
UINT32\r
InternalX86GetInitTimerCount (\r
- IN UINTN ApicBase\r
+ IN UINTN ApicBase\r
)\r
{\r
return MmioRead32 (ApicBase + APIC_TMICT);\r
VOID\r
EFIAPI\r
InternalX86Delay (\r
- IN UINTN ApicBase,\r
- IN UINT32 Delay\r
+ IN UINTN ApicBase,\r
+ IN UINT32 Delay\r
)\r
{\r
- INT32 Ticks;\r
- UINT32 Times;\r
- UINT32 InitCount;\r
- UINT32 StartTick;\r
+ INT32 Ticks;\r
+ UINT32 Times;\r
+ UINT32 InitCount;\r
+ UINT32 StartTick;\r
\r
//\r
// In case Delay is too larger, separate it into several small delay slot.\r
//\r
InitCount = InternalX86GetInitTimerCount (ApicBase);\r
ASSERT (InitCount != 0);\r
- Times = Delay / (InitCount / 2);\r
- Delay = Delay % (InitCount / 2);\r
+ Times = Delay / (InitCount / 2);\r
+ Delay = Delay % (InitCount / 2);\r
\r
//\r
// Get Start Tick and do delay\r
//\r
- StartTick = InternalX86GetTimerTick (ApicBase);\r
+ StartTick = InternalX86GetTimerTick (ApicBase);\r
do {\r
//\r
// Wait until time out by Delay value\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r
- IN UINTN MicroSeconds\r
+ IN UINTN MicroSeconds\r
)\r
{\r
- UINTN ApicBase;\r
+ UINTN ApicBase;\r
\r
ApicBase = InternalX86GetApicBase ();\r
InternalX86Delay (\r
UINTN\r
EFIAPI\r
NanoSecondDelay (\r
- IN UINTN NanoSeconds\r
+ IN UINTN NanoSeconds\r
)\r
{\r
- UINTN ApicBase;\r
+ UINTN ApicBase;\r
\r
ApicBase = InternalX86GetApicBase ();\r
InternalX86Delay (\r
UINT64\r
EFIAPI\r
GetPerformanceCounterProperties (\r
- OUT UINT64 *StartValue OPTIONAL,\r
- OUT UINT64 *EndValue OPTIONAL\r
+ OUT UINT64 *StartValue OPTIONAL,\r
+ OUT UINT64 *EndValue OPTIONAL\r
)\r
{\r
- UINTN ApicBase;\r
+ UINTN ApicBase;\r
\r
ApicBase = InternalX86GetApicBase ();\r
\r
*EndValue = 0;\r
}\r
\r
- return (UINT64) InternalX86GetTimerFrequency (ApicBase);\r
+ return (UINT64)InternalX86GetTimerFrequency (ApicBase);\r
}\r
\r
/**\r
UINT64\r
EFIAPI\r
GetTimeInNanoSecond (\r
- IN UINT64 Ticks\r
+ IN UINT64 Ticks\r
)\r
{\r
UINT64 Frequency;\r
// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
// i.e. highest bit set in Remainder should <= 33.\r
//\r
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
+ Remainder = RShiftU64 (Remainder, (UINTN)Shift);\r
+ Frequency = RShiftU64 (Frequency, (UINTN)Shift);\r
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
\r
return NanoSeconds;\r
EFI_STATUS\r
EFIAPI\r
SmiHandlerProfileRegisterHandler (\r
- IN EFI_GUID *HandlerGuid,\r
- IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
- IN PHYSICAL_ADDRESS CallerAddress,\r
- IN VOID *Context OPTIONAL,\r
- IN UINTN ContextSize OPTIONAL\r
+ IN EFI_GUID *HandlerGuid,\r
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
+ IN PHYSICAL_ADDRESS CallerAddress,\r
+ IN VOID *Context OPTIONAL,\r
+ IN UINTN ContextSize OPTIONAL\r
)\r
{\r
return EFI_UNSUPPORTED;\r
EFI_STATUS\r
EFIAPI\r
SmiHandlerProfileUnregisterHandler (\r
- IN EFI_GUID *HandlerGuid,\r
- IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
- IN VOID *Context OPTIONAL,\r
- IN UINTN ContextSize OPTIONAL\r
+ IN EFI_GUID *HandlerGuid,\r
+ IN EFI_SMM_HANDLER_ENTRY_POINT2 Handler,\r
+ IN VOID *Context OPTIONAL,\r
+ IN UINTN ContextSize OPTIONAL\r
)\r
{\r
return EFI_UNSUPPORTED;\r
\r
**/\r
\r
-\r
#include <PiSmm.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Protocol/SmmReadyToLock.h>\r
#include <Protocol/SmmEndOfDxe.h>\r
\r
-EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mSmmIoLibGcdMemSpace = NULL;\r
-UINTN mSmmIoLibGcdMemNumberOfDesc = 0;\r
+EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mSmmIoLibGcdMemSpace = NULL;\r
+UINTN mSmmIoLibGcdMemNumberOfDesc = 0;\r
\r
EFI_PHYSICAL_ADDRESS mSmmIoLibInternalMaximumSupportMemAddress = 0;\r
\r
-VOID *mSmmIoLibRegistrationEndOfDxe;\r
-VOID *mSmmIoLibRegistrationReadyToLock;\r
+VOID *mSmmIoLibRegistrationEndOfDxe;\r
+VOID *mSmmIoLibRegistrationReadyToLock;\r
\r
-BOOLEAN mSmmIoLibReadyToLock = FALSE;\r
+BOOLEAN mSmmIoLibReadyToLock = FALSE;\r
\r
/**\r
Calculate and save the maximum support address.\r
VOID\r
)\r
{\r
- VOID *Hob;\r
- UINT32 RegEax;\r
- UINT8 MemPhysicalAddressBits;\r
+ VOID *Hob;\r
+ UINT32 RegEax;\r
+ UINT8 MemPhysicalAddressBits;\r
\r
//\r
// Get physical address bits supported.\r
//\r
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
if (Hob != NULL) {\r
- MemPhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+ MemPhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;\r
} else {\r
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
if (RegEax >= 0x80000008) {\r
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
- MemPhysicalAddressBits = (UINT8) RegEax;\r
+ MemPhysicalAddressBits = (UINT8)RegEax;\r
} else {\r
MemPhysicalAddressBits = 36;\r
}\r
}\r
+\r
//\r
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
//\r
IN EFI_GUID *Owner OPTIONAL\r
)\r
{\r
- UINTN Index;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;\r
- BOOLEAN InValidRegion;\r
+ UINTN Index;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;\r
+ BOOLEAN InValidRegion;\r
\r
//\r
// Check override.\r
//\r
if ((Length > mSmmIoLibInternalMaximumSupportMemAddress) ||\r
(BaseAddress > mSmmIoLibInternalMaximumSupportMemAddress) ||\r
- ((Length != 0) && (BaseAddress > (mSmmIoLibInternalMaximumSupportMemAddress - (Length - 1)))) ) {\r
+ ((Length != 0) && (BaseAddress > (mSmmIoLibInternalMaximumSupportMemAddress - (Length - 1)))))\r
+ {\r
//\r
// Overflow happen\r
//\r
//\r
if (mSmmIoLibReadyToLock) {\r
InValidRegion = FALSE;\r
- for (Index = 0; Index < mSmmIoLibGcdMemNumberOfDesc; Index ++) {\r
+ for (Index = 0; Index < mSmmIoLibGcdMemNumberOfDesc; Index++) {\r
Desc = &mSmmIoLibGcdMemSpace[Index];\r
if ((Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&\r
(BaseAddress >= Desc->BaseAddress) &&\r
- ((BaseAddress + Length) <= (Desc->BaseAddress + Desc->Length))) {\r
+ ((BaseAddress + Length) <= (Desc->BaseAddress + Desc->Length)))\r
+ {\r
InValidRegion = TRUE;\r
}\r
}\r
return FALSE;\r
}\r
}\r
+\r
return TRUE;\r
}\r
\r
IN OUT UINTN *NumberOfDescriptors\r
)\r
{\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMapEntry;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMapEnd;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *NewGcdMemoryMapEntry;\r
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *NextGcdMemoryMapEntry;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMapEntry;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *GcdMemoryMapEnd;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *NewGcdMemoryMapEntry;\r
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *NextGcdMemoryMapEntry;\r
\r
- GcdMemoryMapEntry = GcdMemoryMap;\r
+ GcdMemoryMapEntry = GcdMemoryMap;\r
NewGcdMemoryMapEntry = GcdMemoryMap;\r
- GcdMemoryMapEnd = (EFI_GCD_MEMORY_SPACE_DESCRIPTOR *) ((UINT8 *) GcdMemoryMap + (*NumberOfDescriptors) * sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR));\r
+ GcdMemoryMapEnd = (EFI_GCD_MEMORY_SPACE_DESCRIPTOR *)((UINT8 *)GcdMemoryMap + (*NumberOfDescriptors) * sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR));\r
while ((UINTN)GcdMemoryMapEntry < (UINTN)GcdMemoryMapEnd) {\r
- CopyMem (NewGcdMemoryMapEntry, GcdMemoryMapEntry, sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR));\r
+ CopyMem (NewGcdMemoryMapEntry, GcdMemoryMapEntry, sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR));\r
NextGcdMemoryMapEntry = GcdMemoryMapEntry + 1;\r
\r
do {\r
if (((UINTN)NextGcdMemoryMapEntry < (UINTN)GcdMemoryMapEnd) &&\r
(GcdMemoryMapEntry->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) && (NextGcdMemoryMapEntry->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&\r
- ((GcdMemoryMapEntry->BaseAddress + GcdMemoryMapEntry->Length) == NextGcdMemoryMapEntry->BaseAddress)) {\r
+ ((GcdMemoryMapEntry->BaseAddress + GcdMemoryMapEntry->Length) == NextGcdMemoryMapEntry->BaseAddress))\r
+ {\r
GcdMemoryMapEntry->Length += NextGcdMemoryMapEntry->Length;\r
if (NewGcdMemoryMapEntry != GcdMemoryMapEntry) {\r
NewGcdMemoryMapEntry->Length += NextGcdMemoryMapEntry->Length;\r
}\r
} while (TRUE);\r
\r
- GcdMemoryMapEntry = GcdMemoryMapEntry + 1;\r
+ GcdMemoryMapEntry = GcdMemoryMapEntry + 1;\r
NewGcdMemoryMapEntry = NewGcdMemoryMapEntry + 1;\r
}\r
\r
- *NumberOfDescriptors = ((UINTN)NewGcdMemoryMapEntry - (UINTN)GcdMemoryMap) / sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR);\r
+ *NumberOfDescriptors = ((UINTN)NewGcdMemoryMapEntry - (UINTN)GcdMemoryMap) / sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR);\r
\r
- return ;\r
+ return;\r
}\r
\r
/**\r
\r
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap);\r
if (!EFI_ERROR (Status)) {\r
-\r
MergeGcdMmioEntry (MemSpaceMap, &NumberOfDescriptors);\r
\r
mSmmIoLibGcdMemSpace = AllocateCopyPool (NumberOfDescriptors * sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR), MemSpaceMap);\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
//\r
// Calculate and save maximum support address\r
UINT8\r
EFIAPI\r
IoOr8 (\r
- IN UINTN Port,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) | OrData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAnd8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) (IoRead8 (Port) & AndData));\r
+ return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return IoWrite8 (Port, (UINT8) ((IoRead8 (Port) & AndData) | OrData));\r
+ return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
IoBitFieldRead8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
IoBitFieldWrite8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAnd8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return IoWrite8 (\r
UINT8\r
EFIAPI\r
IoBitFieldAndThenOr8 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return IoWrite8 (\r
UINT16\r
EFIAPI\r
IoOr16 (\r
- IN UINTN Port,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) | OrData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAnd16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) (IoRead16 (Port) & AndData));\r
+ return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return IoWrite16 (Port, (UINT16) ((IoRead16 (Port) & AndData) | OrData));\r
+ return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
IoBitFieldRead16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
IoBitFieldWrite16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAnd16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return IoWrite16 (\r
UINT16\r
EFIAPI\r
IoBitFieldAndThenOr16 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return IoWrite16 (\r
UINT32\r
EFIAPI\r
IoOr32 (\r
- IN UINTN Port,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) | OrData);\r
UINT32\r
EFIAPI\r
IoAnd32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (Port, IoRead32 (Port) & AndData);\r
UINT32\r
EFIAPI\r
IoAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
IoBitFieldRead32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
IoBitFieldWrite32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAnd32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return IoWrite32 (\r
UINT32\r
EFIAPI\r
IoBitFieldAndThenOr32 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return IoWrite32 (\r
UINT64\r
EFIAPI\r
IoOr64 (\r
- IN UINTN Port,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) | OrData);\r
UINT64\r
EFIAPI\r
IoAnd64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (Port, IoRead64 (Port) & AndData);\r
UINT64\r
EFIAPI\r
IoAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
IoBitFieldRead64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
IoBitFieldWrite64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAnd64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return IoWrite64 (\r
UINT64\r
EFIAPI\r
IoBitFieldAndThenOr64 (\r
- IN UINTN Port,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Port,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return IoWrite64 (\r
UINT8\r
EFIAPI\r
MmioOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) (MmioRead8 (Address) & AndData));\r
+ return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return MmioWrite8 (Address, (UINT8) ((MmioRead8 (Address) & AndData) | OrData));\r
+ return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
MmioBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
MmioBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return MmioWrite8 (\r
UINT8\r
EFIAPI\r
MmioBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return MmioWrite8 (\r
UINT16\r
EFIAPI\r
MmioOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) (MmioRead16 (Address) & AndData));\r
+ return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return MmioWrite16 (Address, (UINT16) ((MmioRead16 (Address) & AndData) | OrData));\r
+ return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
MmioBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
MmioBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return MmioWrite16 (\r
UINT16\r
EFIAPI\r
MmioBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return MmioWrite16 (\r
UINT32\r
EFIAPI\r
MmioOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
MmioAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (Address, MmioRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
MmioAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
MmioBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
MmioBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return MmioWrite32 (\r
UINT32\r
EFIAPI\r
MmioBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return MmioWrite32 (\r
UINT64\r
EFIAPI\r
MmioOr64 (\r
- IN UINTN Address,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) | OrData);\r
UINT64\r
EFIAPI\r
MmioAnd64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (Address, MmioRead64 (Address) & AndData);\r
UINT64\r
EFIAPI\r
MmioAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);\r
UINT64\r
EFIAPI\r
MmioBitFieldRead64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);\r
UINT64\r
EFIAPI\r
MmioBitFieldWrite64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 Value\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAnd64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
MmioBitFieldAndThenOr64 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT64 AndData,\r
- IN UINT64 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT64 AndData,\r
+ IN UINT64 OrData\r
)\r
{\r
return MmioWrite64 (\r
UINT64\r
EFIAPI\r
IoReadWorker (\r
- IN UINTN Port,\r
- IN EFI_SMM_IO_WIDTH Width\r
+ IN UINTN Port,\r
+ IN EFI_SMM_IO_WIDTH Width\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Data;\r
+ EFI_STATUS Status;\r
+ UINT64 Data;\r
\r
Status = gSmst->SmmIo.Io.Read (&gSmst->SmmIo, Width, Port, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
UINT64\r
EFIAPI\r
IoWriteWorker (\r
- IN UINTN Port,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Port,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Data\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gSmst->SmmIo.Io.Write (&gSmst->SmmIo, Width, Port, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
UINT64\r
EFIAPI\r
MmioReadWorker (\r
- IN UINTN Address,\r
- IN EFI_SMM_IO_WIDTH Width\r
+ IN UINTN Address,\r
+ IN EFI_SMM_IO_WIDTH Width\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT64 Data;\r
+ EFI_STATUS Status;\r
+ UINT64 Data;\r
\r
Status = gSmst->SmmIo.Mem.Read (&gSmst->SmmIo, Width, Address, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
UINT64\r
EFIAPI\r
MmioWriteWorker (\r
- IN UINTN Address,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Address,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Data\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gSmst->SmmIo.Mem.Write (&gSmst->SmmIo, Width, Address, 1, &Data);\r
ASSERT_EFI_ERROR (Status);\r
UINT8\r
EFIAPI\r
IoRead8 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
return (UINT8)IoReadWorker (Port, SMM_IO_UINT8);\r
UINT8\r
EFIAPI\r
IoWrite8 (\r
- IN UINTN Port,\r
- IN UINT8 Value\r
+ IN UINTN Port,\r
+ IN UINT8 Value\r
)\r
{\r
return (UINT8)IoWriteWorker (Port, SMM_IO_UINT8, Value);\r
UINT16\r
EFIAPI\r
IoRead16 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT16\r
EFIAPI\r
IoWrite16 (\r
- IN UINTN Port,\r
- IN UINT16 Value\r
+ IN UINTN Port,\r
+ IN UINT16 Value\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
IoRead32 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
IoWrite32 (\r
- IN UINTN Port,\r
- IN UINT32 Value\r
+ IN UINTN Port,\r
+ IN UINT32 Value\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
IoRead64 (\r
- IN UINTN Port\r
+ IN UINTN Port\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
IoWrite64 (\r
- IN UINTN Port,\r
- IN UINT64 Value\r
+ IN UINTN Port,\r
+ IN UINT64 Value\r
)\r
{\r
//\r
VOID\r
EFIAPI\r
IoReadFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINT8 *Buffer8;\r
+ UINT8 *Buffer8;\r
\r
Buffer8 = (UINT8 *)Buffer;\r
while (Count-- > 0) {\r
VOID\r
EFIAPI\r
IoWriteFifo8 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINT8 *Buffer8;\r
+ UINT8 *Buffer8;\r
\r
Buffer8 = (UINT8 *)Buffer;\r
while (Count-- > 0) {\r
VOID\r
EFIAPI\r
IoReadFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINT16 *Buffer16;\r
+ UINT16 *Buffer16;\r
\r
//\r
// Make sure Port is aligned on a 16-bit boundary.\r
VOID\r
EFIAPI\r
IoWriteFifo16 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINT16 *Buffer16;\r
+ UINT16 *Buffer16;\r
\r
//\r
// Make sure Port is aligned on a 16-bit boundary.\r
VOID\r
EFIAPI\r
IoReadFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINT32 *Buffer32;\r
+ UINT32 *Buffer32;\r
\r
//\r
// Make sure Port is aligned on a 32-bit boundary.\r
VOID\r
EFIAPI\r
IoWriteFifo32 (\r
- IN UINTN Port,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
+ IN UINTN Port,\r
+ IN UINTN Count,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINT32 *Buffer32;\r
+ UINT32 *Buffer32;\r
\r
//\r
// Make sure Port is aligned on a 32-bit boundary.\r
UINT8\r
EFIAPI\r
MmioRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
return (UINT8)MmioReadWorker (Address, SMM_IO_UINT8);\r
UINT8\r
EFIAPI\r
MmioWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
return (UINT8)MmioWriteWorker (Address, SMM_IO_UINT8, Value);\r
UINT16\r
EFIAPI\r
MmioRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT16\r
EFIAPI\r
MmioWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
MmioRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT32\r
EFIAPI\r
MmioWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
MmioRead64 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
//\r
UINT64\r
EFIAPI\r
MmioWrite64 (\r
- IN UINTN Address,\r
- IN UINT64 Value\r
+ IN UINTN Address,\r
+ IN UINT64 Value\r
)\r
{\r
//\r
UINT8 *\r
EFIAPI\r
MmioReadBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT8 *Buffer\r
)\r
{\r
- UINT8 *ReturnBuffer;\r
+ UINT8 *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ReturnBuffer = Buffer;\r
\r
UINT16 *\r
EFIAPI\r
MmioReadBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead16 (StartAddress);\r
+ *(Buffer++) = MmioRead16 (StartAddress);\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
UINT32 *\r
EFIAPI\r
MmioReadBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead32 (StartAddress);\r
+ *(Buffer++) = MmioRead32 (StartAddress);\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioReadBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- OUT UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ OUT UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
ReturnBuffer = Buffer;\r
\r
while (Length > 0) {\r
- *(Buffer++) = MmioRead64 (StartAddress);\r
+ *(Buffer++) = MmioRead64 (StartAddress);\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 8-bit access.\r
\r
UINT8 *\r
EFIAPI\r
MmioWriteBuffer8 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT8 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT8 *Buffer\r
)\r
{\r
- VOID* ReturnBuffer;\r
+ VOID *ReturnBuffer;\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- ReturnBuffer = (UINT8 *) Buffer;\r
+ ReturnBuffer = (UINT8 *)Buffer;\r
\r
while (Length-- > 0) {\r
- MmioWrite8 (StartAddress++, *(Buffer++));\r
+ MmioWrite8 (StartAddress++, *(Buffer++));\r
}\r
\r
return ReturnBuffer;\r
-\r
}\r
\r
/**\r
UINT16 *\r
EFIAPI\r
MmioWriteBuffer16 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT16 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT16 *Buffer\r
)\r
{\r
- UINT16 *ReturnBuffer;\r
+ UINT16 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT16) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT16 *) Buffer;\r
+ ReturnBuffer = (UINT16 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite16 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT16);\r
- Length -= sizeof (UINT16);\r
+ Length -= sizeof (UINT16);\r
}\r
\r
return ReturnBuffer;\r
}\r
\r
-\r
/**\r
Copy data from system memory to MMIO region by using 32-bit access.\r
\r
UINT32 *\r
EFIAPI\r
MmioWriteBuffer32 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT32 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT32 *Buffer\r
)\r
{\r
- UINT32 *ReturnBuffer;\r
+ UINT32 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT32) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT32 *) Buffer;\r
+ ReturnBuffer = (UINT32 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite32 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT32);\r
- Length -= sizeof (UINT32);\r
+ Length -= sizeof (UINT32);\r
}\r
\r
return ReturnBuffer;\r
UINT64 *\r
EFIAPI\r
MmioWriteBuffer64 (\r
- IN UINTN StartAddress,\r
- IN UINTN Length,\r
- IN CONST UINT64 *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Length,\r
+ IN CONST UINT64 *Buffer\r
)\r
{\r
- UINT64 *ReturnBuffer;\r
+ UINT64 *ReturnBuffer;\r
\r
ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);\r
\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));\r
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));\r
+ ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);\r
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);\r
+ ASSERT (((UINTN)Buffer & (sizeof (UINT64) - 1)) == 0);\r
\r
- ReturnBuffer = (UINT64 *) Buffer;\r
+ ReturnBuffer = (UINT64 *)Buffer;\r
\r
while (Length > 0) {\r
MmioWrite64 (StartAddress, *(Buffer++));\r
\r
StartAddress += sizeof (UINT64);\r
- Length -= sizeof (UINT64);\r
+ Length -= sizeof (UINT64);\r
}\r
\r
return ReturnBuffer;\r
}\r
-\r
#include <Library/BaseLib.h>\r
#include <Library/SmmServicesTableLib.h>\r
\r
-\r
/**\r
Reads registers in the EFI CPU I/O space.\r
\r
UINT64\r
EFIAPI\r
IoReadWorker (\r
- IN UINTN Port,\r
- IN EFI_SMM_IO_WIDTH Width\r
+ IN UINTN Port,\r
+ IN EFI_SMM_IO_WIDTH Width\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
IoWriteWorker (\r
- IN UINTN Port,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Port,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Data\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioReadWorker (\r
- IN UINTN Address,\r
- IN EFI_SMM_IO_WIDTH Width\r
+ IN UINTN Address,\r
+ IN EFI_SMM_IO_WIDTH Width\r
);\r
\r
/**\r
UINT64\r
EFIAPI\r
MmioWriteWorker (\r
- IN UINTN Address,\r
- IN EFI_SMM_IO_WIDTH Width,\r
- IN UINT64 Data\r
+ IN UINTN Address,\r
+ IN EFI_SMM_IO_WIDTH Width,\r
+ IN UINT64 Data\r
);\r
\r
#endif\r
return;\r
}\r
\r
-\r
/**\r
Triggers an SMI at run time.\r
\r
return;\r
}\r
\r
-\r
-\r
/**\r
Test if a boot time software SMI happened.\r
\r
return FALSE;\r
}\r
\r
-\r
/**\r
Test if a run time software SMI happened.\r
\r
\r
**/\r
\r
-\r
#include <PiSmm.h>\r
\r
#include <Library/BaseLib.h>\r
#define EFI_MEMORY_INITIALIZED 0x0200000000000000ULL\r
#define EFI_MEMORY_TESTED 0x0400000000000000ULL\r
\r
-EFI_SMRAM_DESCRIPTOR *mSmmMemLibInternalSmramRanges;\r
-UINTN mSmmMemLibInternalSmramCount;\r
+EFI_SMRAM_DESCRIPTOR *mSmmMemLibInternalSmramRanges;\r
+UINTN mSmmMemLibInternalSmramCount;\r
\r
//\r
// Maximum support address used to check input buffer\r
//\r
EFI_PHYSICAL_ADDRESS mSmmMemLibInternalMaximumSupportAddress = 0;\r
\r
-UINTN mMemoryMapEntryCount;\r
-EFI_MEMORY_DESCRIPTOR *mMemoryMap;\r
-UINTN mDescriptorSize;\r
+UINTN mMemoryMapEntryCount;\r
+EFI_MEMORY_DESCRIPTOR *mMemoryMap;\r
+UINTN mDescriptorSize;\r
\r
-EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mSmmMemLibGcdMemSpace = NULL;\r
-UINTN mSmmMemLibGcdMemNumberOfDesc = 0;\r
+EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mSmmMemLibGcdMemSpace = NULL;\r
+UINTN mSmmMemLibGcdMemNumberOfDesc = 0;\r
\r
EFI_MEMORY_ATTRIBUTES_TABLE *mSmmMemLibMemoryAttributesTable = NULL;\r
\r
-VOID *mRegistrationEndOfDxe;\r
-VOID *mRegistrationReadyToLock;\r
+VOID *mRegistrationEndOfDxe;\r
+VOID *mRegistrationReadyToLock;\r
\r
-BOOLEAN mSmmMemLibSmmReadyToLock = FALSE;\r
+BOOLEAN mSmmMemLibSmmReadyToLock = FALSE;\r
\r
/**\r
Calculate and save the maximum support address.\r
VOID\r
)\r
{\r
- VOID *Hob;\r
- UINT32 RegEax;\r
- UINT8 PhysicalAddressBits;\r
+ VOID *Hob;\r
+ UINT32 RegEax;\r
+ UINT8 PhysicalAddressBits;\r
\r
//\r
// Get physical address bits supported.\r
//\r
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
if (Hob != NULL) {\r
- PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+ PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;\r
} else {\r
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
if (RegEax >= 0x80000008) {\r
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
- PhysicalAddressBits = (UINT8) RegEax;\r
+ PhysicalAddressBits = (UINT8)RegEax;\r
} else {\r
PhysicalAddressBits = 36;\r
}\r
}\r
+\r
//\r
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
//\r
//\r
if ((Length > mSmmMemLibInternalMaximumSupportAddress) ||\r
(Buffer > mSmmMemLibInternalMaximumSupportAddress) ||\r
- ((Length != 0) && (Buffer > (mSmmMemLibInternalMaximumSupportAddress - (Length - 1)))) ) {\r
+ ((Length != 0) && (Buffer > (mSmmMemLibInternalMaximumSupportAddress - (Length - 1)))))\r
+ {\r
//\r
// Overflow happen\r
//\r
return FALSE;\r
}\r
\r
- for (Index = 0; Index < mSmmMemLibInternalSmramCount; Index ++) {\r
+ for (Index = 0; Index < mSmmMemLibInternalSmramCount; Index++) {\r
if (((Buffer >= mSmmMemLibInternalSmramRanges[Index].CpuStart) && (Buffer < mSmmMemLibInternalSmramRanges[Index].CpuStart + mSmmMemLibInternalSmramRanges[Index].PhysicalSize)) ||\r
- ((mSmmMemLibInternalSmramRanges[Index].CpuStart >= Buffer) && (mSmmMemLibInternalSmramRanges[Index].CpuStart < Buffer + Length))) {\r
+ ((mSmmMemLibInternalSmramRanges[Index].CpuStart >= Buffer) && (mSmmMemLibInternalSmramRanges[Index].CpuStart < Buffer + Length)))\r
+ {\r
DEBUG ((\r
DEBUG_ERROR,\r
"SmmIsBufferOutsideSmmValid: Overlap: Buffer (0x%lx) - Length (0x%lx), ",\r
// Check override for Valid Communication Region\r
//\r
if (mSmmMemLibSmmReadyToLock) {\r
- EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
- BOOLEAN InValidCommunicationRegion;\r
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
+ BOOLEAN InValidCommunicationRegion;\r
\r
InValidCommunicationRegion = FALSE;\r
- MemoryMap = mMemoryMap;\r
+ MemoryMap = mMemoryMap;\r
for (Index = 0; Index < mMemoryMapEntryCount; Index++) {\r
if ((Buffer >= MemoryMap->PhysicalStart) &&\r
- (Buffer + Length <= MemoryMap->PhysicalStart + LShiftU64 (MemoryMap->NumberOfPages, EFI_PAGE_SHIFT))) {\r
+ (Buffer + Length <= MemoryMap->PhysicalStart + LShiftU64 (MemoryMap->NumberOfPages, EFI_PAGE_SHIFT)))\r
+ {\r
InValidCommunicationRegion = TRUE;\r
}\r
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mDescriptorSize);\r
+\r
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mDescriptorSize);\r
}\r
\r
if (!InValidCommunicationRegion) {\r
//\r
for (Index = 0; Index < mSmmMemLibGcdMemNumberOfDesc; Index++) {\r
if (((Buffer >= mSmmMemLibGcdMemSpace[Index].BaseAddress) && (Buffer < mSmmMemLibGcdMemSpace[Index].BaseAddress + mSmmMemLibGcdMemSpace[Index].Length)) ||\r
- ((mSmmMemLibGcdMemSpace[Index].BaseAddress >= Buffer) && (mSmmMemLibGcdMemSpace[Index].BaseAddress < Buffer + Length))) {\r
+ ((mSmmMemLibGcdMemSpace[Index].BaseAddress >= Buffer) && (mSmmMemLibGcdMemSpace[Index].BaseAddress < Buffer + Length)))\r
+ {\r
DEBUG ((\r
DEBUG_ERROR,\r
"SmmIsBufferOutsideSmmValid: In Untested Memory Region: Buffer (0x%lx) - Length (0x%lx)\n",\r
// Check UEFI runtime memory with EFI_MEMORY_RO as invalid communication buffer.\r
//\r
if (mSmmMemLibMemoryAttributesTable != NULL) {\r
- EFI_MEMORY_DESCRIPTOR *Entry;\r
+ EFI_MEMORY_DESCRIPTOR *Entry;\r
\r
Entry = (EFI_MEMORY_DESCRIPTOR *)(mSmmMemLibMemoryAttributesTable + 1);\r
for (Index = 0; Index < mSmmMemLibMemoryAttributesTable->NumberOfEntries; Index++) {\r
- if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {\r
+ if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {\r
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {\r
if (((Buffer >= Entry->PhysicalStart) && (Buffer < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) ||\r
- ((Entry->PhysicalStart >= Buffer) && (Entry->PhysicalStart < Buffer + Length))) {\r
+ ((Entry->PhysicalStart >= Buffer) && (Entry->PhysicalStart < Buffer + Length)))\r
+ {\r
DEBUG ((\r
DEBUG_ERROR,\r
"SmmIsBufferOutsideSmmValid: In RuntimeCode Region: Buffer (0x%lx) - Length (0x%lx)\n",\r
}\r
}\r
}\r
+\r
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mSmmMemLibMemoryAttributesTable->DescriptorSize);\r
}\r
}\r
}\r
+\r
return TRUE;\r
}\r
\r
DEBUG ((DEBUG_ERROR, "SmmCopyMemToSmram: Security Violation: Source (0x%x), Length (0x%x)\n", SourceBuffer, Length));\r
return EFI_SECURITY_VIOLATION;\r
}\r
+\r
CopyMem (DestinationBuffer, SourceBuffer, Length);\r
return EFI_SUCCESS;\r
}\r
DEBUG ((DEBUG_ERROR, "SmmCopyMemFromSmram: Security Violation: Destination (0x%x), Length (0x%x)\n", DestinationBuffer, Length));\r
return EFI_SECURITY_VIOLATION;\r
}\r
+\r
CopyMem (DestinationBuffer, SourceBuffer, Length);\r
return EFI_SUCCESS;\r
}\r
DEBUG ((DEBUG_ERROR, "SmmCopyMem: Security Violation: Destination (0x%x), Length (0x%x)\n", DestinationBuffer, Length));\r
return EFI_SECURITY_VIOLATION;\r
}\r
+\r
if (!SmmIsBufferOutsideSmmValid ((EFI_PHYSICAL_ADDRESS)(UINTN)SourceBuffer, Length)) {\r
DEBUG ((DEBUG_ERROR, "SmmCopyMem: Security Violation: Source (0x%x), Length (0x%x)\n", SourceBuffer, Length));\r
return EFI_SECURITY_VIOLATION;\r
}\r
+\r
CopyMem (DestinationBuffer, SourceBuffer, Length);\r
return EFI_SUCCESS;\r
}\r
DEBUG ((DEBUG_ERROR, "SmmSetMem: Security Violation: Source (0x%x), Length (0x%x)\n", Buffer, Length));\r
return EFI_SECURITY_VIOLATION;\r
}\r
+\r
SetMem (Buffer, Length, Value);\r
return EFI_SUCCESS;\r
}\r
\r
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap);\r
if (EFI_ERROR (Status)) {\r
- return ;\r
+ return;\r
}\r
\r
mSmmMemLibGcdMemNumberOfDesc = 0;\r
for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
- if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&\r
- (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
- (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)\r
- ) {\r
+ if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&\r
+ ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
+ (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))\r
+ )\r
+ {\r
mSmmMemLibGcdMemNumberOfDesc++;\r
}\r
}\r
if (mSmmMemLibGcdMemSpace == NULL) {\r
mSmmMemLibGcdMemNumberOfDesc = 0;\r
gBS->FreePool (MemSpaceMap);\r
- return ;\r
+ return;\r
}\r
\r
mSmmMemLibGcdMemNumberOfDesc = 0;\r
for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
- if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&\r
- (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
- (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)\r
- ) {\r
+ if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&\r
+ ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
+ (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))\r
+ )\r
+ {\r
CopyMem (\r
&mSmmMemLibGcdMemSpace[mSmmMemLibGcdMemNumberOfDesc],\r
&MemSpaceMap[Index],\r
- sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR)\r
+ sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR)\r
);\r
mSmmMemLibGcdMemNumberOfDesc++;\r
}\r
\r
Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);\r
if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) {\r
- MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;\r
+ MemoryAttributesTableSize = sizeof (EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;\r
mSmmMemLibMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable);\r
ASSERT (mSmmMemLibMemoryAttributesTable != NULL);\r
}\r
IN EFI_HANDLE Handle\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN MapKey;\r
- UINTN MemoryMapSize;\r
- EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
- EFI_MEMORY_DESCRIPTOR *MemoryMapStart;\r
- EFI_MEMORY_DESCRIPTOR *SmmMemoryMapStart;\r
- UINTN MemoryMapEntryCount;\r
- UINTN DescriptorSize;\r
- UINT32 DescriptorVersion;\r
- UINTN Index;\r
+ EFI_STATUS Status;\r
+ UINTN MapKey;\r
+ UINTN MemoryMapSize;\r
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
+ EFI_MEMORY_DESCRIPTOR *MemoryMapStart;\r
+ EFI_MEMORY_DESCRIPTOR *SmmMemoryMapStart;\r
+ UINTN MemoryMapEntryCount;\r
+ UINTN DescriptorSize;\r
+ UINT32 DescriptorVersion;\r
+ UINTN Index;\r
\r
MemoryMapSize = 0;\r
- MemoryMap = NULL;\r
- Status = gBS->GetMemoryMap (\r
- &MemoryMapSize,\r
- MemoryMap,\r
- &MapKey,\r
- &DescriptorSize,\r
- &DescriptorVersion\r
- );\r
+ MemoryMap = NULL;\r
+ Status = gBS->GetMemoryMap (\r
+ &MemoryMapSize,\r
+ MemoryMap,\r
+ &MapKey,\r
+ &DescriptorSize,\r
+ &DescriptorVersion\r
+ );\r
ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
do {\r
ASSERT (MemoryMap != NULL);\r
\r
Status = gBS->GetMemoryMap (\r
- &MemoryMapSize,\r
- MemoryMap,\r
- &MapKey,\r
- &DescriptorSize,\r
- &DescriptorVersion\r
- );\r
+ &MemoryMapSize,\r
+ MemoryMap,\r
+ &MapKey,\r
+ &DescriptorSize,\r
+ &DescriptorVersion\r
+ );\r
if (EFI_ERROR (Status)) {\r
gBS->FreePool (MemoryMap);\r
}\r
//\r
// Get Count\r
//\r
- mDescriptorSize = DescriptorSize;\r
- MemoryMapEntryCount = MemoryMapSize/DescriptorSize;\r
- MemoryMapStart = MemoryMap;\r
+ mDescriptorSize = DescriptorSize;\r
+ MemoryMapEntryCount = MemoryMapSize/DescriptorSize;\r
+ MemoryMapStart = MemoryMap;\r
mMemoryMapEntryCount = 0;\r
for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
switch (MemoryMap->Type) {\r
- case EfiReservedMemoryType:\r
- case EfiRuntimeServicesCode:\r
- case EfiRuntimeServicesData:\r
- case EfiACPIMemoryNVS:\r
- mMemoryMapEntryCount++;\r
- break;\r
+ case EfiReservedMemoryType:\r
+ case EfiRuntimeServicesCode:\r
+ case EfiRuntimeServicesData:\r
+ case EfiACPIMemoryNVS:\r
+ mMemoryMapEntryCount++;\r
+ break;\r
}\r
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);\r
+\r
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);\r
}\r
+\r
MemoryMap = MemoryMapStart;\r
\r
//\r
SmmMemoryMapStart = mMemoryMap;\r
for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
switch (MemoryMap->Type) {\r
- case EfiReservedMemoryType:\r
- case EfiRuntimeServicesCode:\r
- case EfiRuntimeServicesData:\r
- case EfiACPIMemoryNVS:\r
- CopyMem (mMemoryMap, MemoryMap, DescriptorSize);\r
- mMemoryMap = NEXT_MEMORY_DESCRIPTOR(mMemoryMap, DescriptorSize);\r
- break;\r
+ case EfiReservedMemoryType:\r
+ case EfiRuntimeServicesCode:\r
+ case EfiRuntimeServicesData:\r
+ case EfiACPIMemoryNVS:\r
+ CopyMem (mMemoryMap, MemoryMap, DescriptorSize);\r
+ mMemoryMap = NEXT_MEMORY_DESCRIPTOR (mMemoryMap, DescriptorSize);\r
+ break;\r
}\r
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);\r
+\r
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);\r
}\r
+\r
mMemoryMap = SmmMemoryMapStart;\r
- MemoryMap = MemoryMapStart;\r
+ MemoryMap = MemoryMapStart;\r
\r
gBS->FreePool (MemoryMap);\r
\r
mSmmMemLibSmmReadyToLock = TRUE;\r
return EFI_SUCCESS;\r
}\r
+\r
/**\r
The constructor function initializes the Smm Mem library\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r
- UINTN Size;\r
+ EFI_STATUS Status;\r
+ EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r
+ UINTN Size;\r
\r
//\r
// Get SMRAM information\r
Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);\r
ASSERT_EFI_ERROR (Status);\r
\r
- Size = 0;\r
+ Size = 0;\r
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
//\r
// Get SMRAM range information\r
//\r
- Size = 0;\r
+ Size = 0;\r
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
\r
- mSmramRanges = (EFI_SMRAM_DESCRIPTOR *) AllocatePool (Size);\r
+ mSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r
ASSERT (mSmramRanges != NULL);\r
\r
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmramRanges);\r
BOOLEAN\r
EFIAPI\r
BufferInSmram (\r
- IN VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
UINTN Index;\r
\r
- for (Index = 0; Index < mSmramRangeCount; Index ++) {\r
- if (((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer >= mSmramRanges[Index].CpuStart) &&\r
- ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer < (mSmramRanges[Index].CpuStart + mSmramRanges[Index].PhysicalSize))) {\r
+ for (Index = 0; Index < mSmramRangeCount; Index++) {\r
+ if (((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer >= mSmramRanges[Index].CpuStart) &&\r
+ ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer < (mSmramRanges[Index].CpuStart + mSmramRanges[Index].PhysicalSize)))\r
+ {\r
return TRUE;\r
}\r
}\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- return (VOID *) (UINTN) Memory;\r
+\r
+ return (VOID *)(UINTN)Memory;\r
}\r
\r
/**\r
// When Buffer is in SMRAM range, it should be allocated by gSmst->SmmAllocatePages() service.\r
// So, gSmst->SmmFreePages() service is used to free it.\r
//\r
- Status = gSmst->SmmFreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gSmst->SmmFreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
} else {\r
//\r
// When Buffer is out of SMRAM range, it should be allocated by gBS->AllocatePages() service.\r
// So, gBS->FreePages() service is used to free it.\r
//\r
- Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
}\r
+\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
if (Pages == 0) {\r
return NULL;\r
}\r
+\r
if (Alignment > EFI_PAGE_SIZE) {\r
//\r
// Calculate the total number of pages since alignment is larger than page size.\r
//\r
- AlignmentMask = Alignment - 1;\r
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
+ AlignmentMask = Alignment - 1;\r
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
//\r
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r
//\r
ASSERT (RealPages > Pages);\r
\r
- Status = gSmst->SmmAllocatePages (AllocateAnyPages, MemoryType, RealPages, &Memory);\r
+ Status = gSmst->SmmAllocatePages (AllocateAnyPages, MemoryType, RealPages, &Memory);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;\r
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);\r
+\r
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r
if (UnalignedPages > 0) {\r
//\r
// Free first unaligned page(s).\r
Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
+\r
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
UnalignedPages = RealPages - Pages - UnalignedPages;\r
if (UnalignedPages > 0) {\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = (UINTN) Memory;\r
+\r
+ AlignedMemory = (UINTN)Memory;\r
}\r
- return (VOID *) AlignedMemory;\r
+\r
+ return (VOID *)AlignedMemory;\r
}\r
\r
/**\r
// When Buffer is in SMRAM range, it should be allocated by gSmst->SmmAllocatePages() service.\r
// So, gSmst->SmmFreePages() service is used to free it.\r
//\r
- Status = gSmst->SmmFreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gSmst->SmmFreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
} else {\r
//\r
// When Buffer is out of SMRAM range, it should be allocated by gBS->AllocatePages() service.\r
// So, gBS->FreePages() service is used to free it.\r
//\r
- Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
}\r
+\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
if (EFI_ERROR (Status)) {\r
Memory = NULL;\r
}\r
+\r
return Memory;\r
}\r
\r
if (Memory != NULL) {\r
Memory = ZeroMem (Memory, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *Memory;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));\r
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
\r
Memory = InternalAllocatePool (PoolType, AllocationSize);\r
if (Memory != NULL) {\r
- Memory = CopyMem (Memory, Buffer, AllocationSize);\r
+ Memory = CopyMem (Memory, Buffer, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *NewBuffer;\r
\r
NewBuffer = InternalAllocateZeroPool (PoolType, NewSize);\r
- if (NewBuffer != NULL && OldBuffer != NULL) {\r
+ if ((NewBuffer != NULL) && (OldBuffer != NULL)) {\r
CopyMem (NewBuffer, OldBuffer, MIN (OldSize, NewSize));\r
FreePool (OldBuffer);\r
}\r
+\r
return NewBuffer;\r
}\r
\r
VOID\r
EFIAPI\r
FreePool (\r
- IN VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (BufferInSmram (Buffer)) {\r
//\r
//\r
Status = gBS->FreePool (Buffer);\r
}\r
+\r
ASSERT_EFI_ERROR (Status);\r
}\r
///\r
/// Module global that contains the base physical address and size of the PCI Express MMIO range.\r
///\r
-UINTN mSmmPciExpressLibPciExpressBaseAddress = 0;\r
-UINTN mSmmPciExpressLibPciExpressBaseSize = 0;\r
+UINTN mSmmPciExpressLibPciExpressBaseAddress = 0;\r
+UINTN mSmmPciExpressLibPciExpressBaseSize = 0;\r
\r
/**\r
The constructor function caches the PCI Express Base Address\r
EFI_STATUS\r
EFIAPI\r
SmmPciExpressLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
- )\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
{\r
- //\r
- // Cache the physical address and size of the PCI Express MMIO range into a module global variable\r
- //\r
- mSmmPciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
- mSmmPciExpressLibPciExpressBaseSize = (UINTN) PcdGet64 (PcdPciExpressBaseSize);\r
+ //\r
+ // Cache the physical address and size of the PCI Express MMIO range into a module global variable\r
+ //\r
+ mSmmPciExpressLibPciExpressBaseAddress = (UINTN)PcdGet64 (PcdPciExpressBaseAddress);\r
+ mSmmPciExpressLibPciExpressBaseSize = (UINTN)PcdGet64 (PcdPciExpressBaseSize);\r
\r
- return EFI_SUCCESS;\r
+ return EFI_SUCCESS;\r
}\r
\r
/**\r
RETURN_STATUS\r
EFIAPI\r
PciExpressRegisterForRuntimeAccess (\r
- IN UINTN Address\r
- )\r
+ IN UINTN Address\r
+ )\r
{\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- return RETURN_UNSUPPORTED;\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ return RETURN_UNSUPPORTED;\r
}\r
\r
/**\r
**/\r
UINTN\r
GetPciExpressAddress (\r
- IN UINTN Address\r
- )\r
+ IN UINTN Address\r
+ )\r
{\r
- //\r
- // Make sure Address is valid\r
- //\r
- ASSERT_INVALID_PCI_ADDRESS (Address);\r
- //\r
- // Make sure the Address is in MMCONF address space\r
- //\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
- }\r
- return mSmmPciExpressLibPciExpressBaseAddress + Address;\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT_INVALID_PCI_ADDRESS (Address);\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
+ return mSmmPciExpressLibPciExpressBaseAddress + Address;\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
- IN UINTN Address\r
- )\r
+ IN UINTN Address\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioRead8 (GetPciExpressAddress (Address));\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioRead8 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioWrite8 (GetPciExpressAddress (Address), Value);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioWrite8 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioOr8 (GetPciExpressAddress (Address), OrData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioOr8 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioAndThenOr8 (\r
- GetPciExpressAddress (Address),\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioAndThenOr8 (\r
+ GetPciExpressAddress (Address),\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioBitFieldRead8 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioBitFieldRead8 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit\r
+ );\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioBitFieldWrite8 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioBitFieldWrite8 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioBitFieldOr8 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioBitFieldOr8 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioBitFieldAnd8 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioBitFieldAnd8 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT8) -1;\r
- }\r
- return MmioBitFieldAndThenOr8 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT8)-1;\r
+ }\r
+\r
+ return MmioBitFieldAndThenOr8 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
- IN UINTN Address\r
- )\r
+ IN UINTN Address\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioRead16 (GetPciExpressAddress (Address));\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioRead16 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioWrite16 (GetPciExpressAddress (Address), Value);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioWrite16 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioOr16 (GetPciExpressAddress (Address), OrData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioOr16 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioAndThenOr16 (\r
- GetPciExpressAddress (Address),\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioAndThenOr16 (\r
+ GetPciExpressAddress (Address),\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioBitFieldRead16 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioBitFieldRead16 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioBitFieldWrite16 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioBitFieldWrite16 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioBitFieldOr16 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioBitFieldOr16 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioBitFieldAnd16 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioBitFieldAnd16 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT16) -1;\r
- }\r
- return MmioBitFieldAndThenOr16 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT16)-1;\r
+ }\r
+\r
+ return MmioBitFieldAndThenOr16 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
- IN UINTN Address\r
- )\r
+ IN UINTN Address\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioRead32 (GetPciExpressAddress (Address));\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioRead32 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioWrite32 (GetPciExpressAddress (Address), Value);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioWrite32 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioOr32 (GetPciExpressAddress (Address), OrData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioOr32 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioAndThenOr32 (\r
- GetPciExpressAddress (Address),\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioAndThenOr32 (\r
+ GetPciExpressAddress (Address),\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioBitFieldRead32 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioBitFieldRead32 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioBitFieldWrite32 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- Value\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioBitFieldWrite32 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ Value\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioBitFieldOr32 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioBitFieldOr32 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioBitFieldAnd32 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioBitFieldAnd32 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData\r
+ );\r
}\r
\r
/**\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
- )\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
{\r
- if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINT32) -1;\r
- }\r
- return MmioBitFieldAndThenOr32 (\r
- GetPciExpressAddress (Address),\r
- StartBit,\r
- EndBit,\r
- AndData,\r
- OrData\r
- );\r
+ if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINT32)-1;\r
+ }\r
+\r
+ return MmioBitFieldAndThenOr32 (\r
+ GetPciExpressAddress (Address),\r
+ StartBit,\r
+ EndBit,\r
+ AndData,\r
+ OrData\r
+ );\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
- )\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
+ )\r
{\r
- UINTN ReturnValue;\r
-\r
- //\r
- // Make sure Address is valid\r
- //\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- //\r
- // Make sure the Address is in MMCONF address space\r
- //\r
- if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
- }\r
-\r
- if (Size == 0) {\r
- return Size;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Read a byte if StartAddress is byte aligned\r
- //\r
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Read a word if StartAddress is word aligned\r
- //\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
-\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Read as many double words as possible\r
- //\r
- WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
-\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Read the last remaining word if exist\r
- //\r
- WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Read the last remaining byte if exist\r
- //\r
- *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
- }\r
-\r
- return ReturnValue;\r
+ UINTN ReturnValue;\r
+\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
+ if (Size == 0) {\r
+ return Size;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((StartAddress & 1) != 0) {\r
+ //\r
+ // Read a byte if StartAddress is byte aligned\r
+ //\r
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
+ }\r
+\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
+ //\r
+ // Read a word if StartAddress is word aligned\r
+ //\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
+\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Read as many double words as possible\r
+ //\r
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r
+\r
+ StartAddress += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Read the last remaining word if exist\r
+ //\r
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Read the last remaining byte if exist\r
+ //\r
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
+ }\r
+\r
+ return ReturnValue;\r
}\r
\r
/**\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
- )\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
{\r
- UINTN ReturnValue;\r
-\r
- //\r
- // Make sure Address is valid\r
- //\r
- ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
-\r
- //\r
- // Make sure the Address is in MMCONF address space\r
- //\r
- if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r
- return (UINTN) -1;\r
- }\r
-\r
-\r
- if (Size == 0) {\r
- return 0;\r
- }\r
-\r
- ASSERT (Buffer != NULL);\r
-\r
- //\r
- // Save Size for return\r
- //\r
- ReturnValue = Size;\r
-\r
- if ((StartAddress & 1) != 0) {\r
- //\r
- // Write a byte if StartAddress is byte aligned\r
- //\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
- //\r
- // Write a word if StartAddress is word aligned\r
- //\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- while (Size >= sizeof (UINT32)) {\r
- //\r
- // Write as many double words as possible\r
- //\r
- PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
- StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT16)) {\r
- //\r
- // Write the last remaining word if exist\r
- //\r
- PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
- StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
- }\r
-\r
- if (Size >= sizeof (UINT8)) {\r
- //\r
- // Write the last remaining byte if exist\r
- //\r
- PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
- }\r
-\r
- return ReturnValue;\r
+ UINTN ReturnValue;\r
+\r
+ //\r
+ // Make sure Address is valid\r
+ //\r
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ //\r
+ // Make sure the Address is in MMCONF address space\r
+ //\r
+ if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r
+ return (UINTN)-1;\r
+ }\r
+\r
+ if (Size == 0) {\r
+ return 0;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((StartAddress & 1) != 0) {\r
+ //\r
+ // Write a byte if StartAddress is byte aligned\r
+ //\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
+ }\r
+\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r
+ //\r
+ // Write a word if StartAddress is word aligned\r
+ //\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Write as many double words as possible\r
+ //\r
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r
+ StartAddress += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Write the last remaining word if exist\r
+ //\r
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r
+ StartAddress += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Write the last remaining byte if exist\r
+ //\r
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r
+ }\r
+\r
+ return ReturnValue;\r
}\r
#include <Library/BaseLib.h>\r
#include <Library/SmmServicesTableLib.h>\r
\r
-\r
/**\r
Assert the validity of a PCI address. A valid PCI address should contain 1's\r
only in the low 28 bits.\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r
ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
\r
/**\r
//\r
// Global variable to cache pointer to PCI Root Bridge I/O protocol.\r
//\r
-EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL *mSmmPciRootBridgeIo = NULL;\r
+EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL *mSmmPciRootBridgeIo = NULL;\r
\r
/**\r
The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r
EFI_STATUS\r
EFIAPI\r
PciLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
\r
- Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mSmmPciRootBridgeIo);\r
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmPciRootBridgeIoProtocolGuid, NULL, (VOID **)&mSmmPciRootBridgeIo);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mSmmPciRootBridgeIo != NULL);\r
\r
UINT32 Data;\r
\r
mSmmPciRootBridgeIo->Pci.Read (\r
- mSmmPciRootBridgeIo,\r
- Width,\r
- PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
- 1,\r
- &Data\r
- );\r
+ mSmmPciRootBridgeIo,\r
+ Width,\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+ 1,\r
+ &Data\r
+ );\r
\r
return Data;\r
}\r
)\r
{\r
mSmmPciRootBridgeIo->Pci.Write (\r
- mSmmPciRootBridgeIo,\r
- Width,\r
- PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
- 1,\r
- &Data\r
- );\r
+ mSmmPciRootBridgeIo,\r
+ Width,\r
+ PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r
+ 1,\r
+ &Data\r
+ );\r
return Data;\r
}\r
\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+ return (UINT8)SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+ return (UINT8)SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+ return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+ return (UINT16)SmmPciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+ return (UINT16)SmmPciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+ return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
///\r
/// Signature value that must be set to PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT_SIGNATURE\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// The link entry to be inserted to the list of periodic SMI handlers.\r
///\r
- LIST_ENTRY Link;\r
+ LIST_ENTRY Link;\r
///\r
/// The dispatch function to called to invoke an enabled periodic SMI handler.\r
///\r
- PERIODIC_SMI_LIBRARY_HANDLER DispatchFunction;\r
+ PERIODIC_SMI_LIBRARY_HANDLER DispatchFunction;\r
///\r
/// The context to pass into DispatchFunction\r
///\r
- VOID *Context;\r
+ VOID *Context;\r
///\r
/// The tick period in 100 ns units that DispatchFunction should be called.\r
///\r
- UINT64 TickPeriod;\r
+ UINT64 TickPeriod;\r
///\r
/// The Cpu number that is required to execute DispatchFunction. If Cpu is\r
/// set to PERIODIC_SMI_LIBRARY_ANY_CPU, then DispatchFunction may be executed\r
/// on any CPU.\r
///\r
- UINTN Cpu;\r
+ UINTN Cpu;\r
///\r
/// The size, in bytes, of the stack allocated for a periodic SMI handler.\r
/// This value must be a multiple of EFI_PAGE_SIZE.\r
///\r
- UINTN StackSize;\r
+ UINTN StackSize;\r
///\r
/// A pointer to the stack allocated using AllocatePages(). This field will\r
/// be NULL if StackSize is 0.\r
///\r
- VOID *Stack;\r
+ VOID *Stack;\r
///\r
/// Spin lock used to wait for an AP to complete the execution of a periodic SMI handler\r
///\r
- SPIN_LOCK DispatchLock;\r
+ SPIN_LOCK DispatchLock;\r
///\r
/// The rate in Hz of the performance counter that is used to measure the\r
/// amount of time that a periodic SMI handler executes.\r
///\r
- UINT64 PerfomanceCounterRate;\r
+ UINT64 PerfomanceCounterRate;\r
///\r
/// The start count value of the performance counter that is used to measure\r
/// the amount of time that a periodic SMI handler executes.\r
///\r
- UINT64 PerfomanceCounterStartValue;\r
+ UINT64 PerfomanceCounterStartValue;\r
///\r
/// The end count value of the performance counter that is used to measure\r
/// the amount of time that a periodic SMI handler executes.\r
///\r
- UINT64 PerfomanceCounterEndValue;\r
+ UINT64 PerfomanceCounterEndValue;\r
///\r
/// The context record passed into the Register() function of the SMM Periodic\r
/// Timer Dispatch Protocol when a periodic SMI handler is enabled.\r
///\r
- EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT RegisterContext;\r
+ EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT RegisterContext;\r
///\r
/// The handle returned from the Register() function of the SMM Periodic\r
/// Timer Dispatch Protocol when a periodic SMI handler is enabled.\r
///\r
- EFI_HANDLE DispatchHandle;\r
+ EFI_HANDLE DispatchHandle;\r
///\r
/// The total number of performance counter ticks that the periodic SMI handler\r
/// has been executing in its current invocation.\r
///\r
- UINT64 DispatchTotalTime;\r
+ UINT64 DispatchTotalTime;\r
///\r
/// The performance counter value that was captured the last time that the\r
/// periodic SMI handler called PeriodicSmiExecutionTime(). This allows the\r
/// time value returned by PeriodicSmiExecutionTime() to be accurate even when\r
/// the performance counter rolls over.\r
///\r
- UINT64 DispatchCheckPointTime;\r
+ UINT64 DispatchCheckPointTime;\r
///\r
/// Buffer used to save the context when control is transfer from this library\r
/// to an enabled periodic SMI handler. This saved context is used when the\r
/// periodic SMI handler exits or yields.\r
///\r
- BASE_LIBRARY_JUMP_BUFFER DispatchJumpBuffer;\r
+ BASE_LIBRARY_JUMP_BUFFER DispatchJumpBuffer;\r
///\r
/// Flag that is set to TRUE when a periodic SMI handler requests to yield\r
/// using PeriodicSmiYield(). When this flag IS TRUE, YieldJumpBuffer is\r
/// valid. When this flag is FALSE, YieldJumpBuffer is not valid.\r
///\r
- BOOLEAN YieldFlag;\r
+ BOOLEAN YieldFlag;\r
///\r
/// Buffer used to save the context when a periodic SMI handler requests to\r
/// yield using PeriodicSmiYield(). This context is used to resume the\r
/// execution of a periodic SMI handler the next time control is transferred\r
/// to the periodic SMI handler that yielded.\r
///\r
- BASE_LIBRARY_JUMP_BUFFER YieldJumpBuffer;\r
+ BASE_LIBRARY_JUMP_BUFFER YieldJumpBuffer;\r
///\r
/// The amount of time, in 100 ns units, that have elapsed since the last\r
/// time the periodic SMI handler was invoked.\r
///\r
- UINT64 ElapsedTime;\r
+ UINT64 ElapsedTime;\r
} PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT;\r
\r
/**\r
///\r
/// Pointer to the SMM Periodic Timer Dispatch Protocol that was located in the constructor.\r
///\r
-EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *gSmmPeriodicTimerDispatch2 = NULL;\r
+EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *gSmmPeriodicTimerDispatch2 = NULL;\r
\r
///\r
/// Pointer to a table of supported periodic SMI tick periods in 100 ns units\r
/// in based on the values returned from the SMM Periodic Timer Dispatch 2 Protocol\r
/// function GetNextShorterInterval().\r
///\r
-UINT64 *gSmiTickPeriodTable = NULL;\r
+UINT64 *gSmiTickPeriodTable = NULL;\r
\r
///\r
/// Linked list of free periodic SMI handlers that this library can use.\r
///\r
-LIST_ENTRY gFreePeriodicSmiLibraryHandlers =\r
- INITIALIZE_LIST_HEAD_VARIABLE (gFreePeriodicSmiLibraryHandlers);\r
+LIST_ENTRY gFreePeriodicSmiLibraryHandlers =\r
+ INITIALIZE_LIST_HEAD_VARIABLE (gFreePeriodicSmiLibraryHandlers);\r
\r
///\r
/// Linked list of periodic SMI handlers that this library is currently managing.\r
///\r
-LIST_ENTRY gPeriodicSmiLibraryHandlers =\r
- INITIALIZE_LIST_HEAD_VARIABLE (gPeriodicSmiLibraryHandlers);\r
+LIST_ENTRY gPeriodicSmiLibraryHandlers =\r
+ INITIALIZE_LIST_HEAD_VARIABLE (gPeriodicSmiLibraryHandlers);\r
\r
///\r
/// Pointer to the periodic SMI handler that is currently being executed.\r
/// Is set to NULL if no periodic SMI handler is currently being executed.\r
///\r
-PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *gActivePeriodicSmiLibraryHandler = NULL;\r
+PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *gActivePeriodicSmiLibraryHandler = NULL;\r
\r
/**\r
Internal worker function that returns a pointer to the\r
**/\r
PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *\r
LookupPeriodicSmiLibraryHandler (\r
- IN EFI_HANDLE DispatchHandle OPTIONAL\r
+ IN EFI_HANDLE DispatchHandle OPTIONAL\r
)\r
{\r
LIST_ENTRY *Link;\r
// Search the periodic SMI handler entries for a a matching DispatchHandle\r
//\r
for ( Link = GetFirstNode (&gPeriodicSmiLibraryHandlers)\r
- ; !IsNull (&gPeriodicSmiLibraryHandlers, Link)\r
- ; Link = GetNextNode (&gPeriodicSmiLibraryHandlers, Link)\r
- ) {\r
+ ; !IsNull (&gPeriodicSmiLibraryHandlers, Link)\r
+ ; Link = GetNextNode (&gPeriodicSmiLibraryHandlers, Link)\r
+ )\r
+ {\r
PeriodicSmiLibraryHandler = PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT_FROM_LINK (Link);\r
\r
if (PeriodicSmiLibraryHandler->DispatchHandle == DispatchHandle) {\r
**/\r
PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *\r
SetActivePeriodicSmiLibraryHandler (\r
- IN EFI_HANDLE DispatchHandle OPTIONAL\r
+ IN EFI_HANDLE DispatchHandle OPTIONAL\r
)\r
{\r
if (DispatchHandle == NULL) {\r
} else {\r
gActivePeriodicSmiLibraryHandler = LookupPeriodicSmiLibraryHandler (DispatchHandle);\r
}\r
+\r
return gActivePeriodicSmiLibraryHandler;\r
}\r
\r
**/\r
VOID\r
ReclaimPeriodicSmiLibraryHandler (\r
- PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *PeriodicSmiLibraryHandler\r
+ PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT *PeriodicSmiLibraryHandler\r
)\r
{\r
ASSERT (PeriodicSmiLibraryHandler->DispatchHandle == NULL);\r
);\r
PeriodicSmiLibraryHandler->Stack = NULL;\r
}\r
+\r
RemoveEntryList (&PeriodicSmiLibraryHandler->Link);\r
InsertHeadList (&gFreePeriodicSmiLibraryHandlers, &PeriodicSmiLibraryHandler->Link);\r
}\r
if (PeriodicSmiLibraryHandler == NULL) {\r
break;\r
}\r
+\r
PeriodicSmiLibraryHandler->Signature = PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT_SIGNATURE;\r
InsertHeadList (&gFreePeriodicSmiLibraryHandlers, &PeriodicSmiLibraryHandler->Link);\r
}\r
\r
- return (BOOLEAN) (Index > 0);\r
+ return (BOOLEAN)(Index > 0);\r
}\r
\r
/**\r
// Must never return\r
//\r
ASSERT (FALSE);\r
- CpuDeadLoop();\r
+ CpuDeadLoop ();\r
}\r
\r
/**\r
// periodic SMI handler was dispatched.\r
//\r
PeriodicSmiLibraryHandler->DispatchFunction (\r
- PeriodicSmiLibraryHandler->Context,\r
- PeriodicSmiLibraryHandler->ElapsedTime\r
- );\r
+ PeriodicSmiLibraryHandler->Context,\r
+ PeriodicSmiLibraryHandler->ElapsedTime\r
+ );\r
\r
//\r
// If this DispatchFunction() returns, then unconditionally call PeriodicSmiExit()\r
// calculated.\r
//\r
PeriodicSmiLibraryHandler->DispatchTotalTime = 0;\r
- PeriodicSmiLibraryHandler->DispatchCheckPointTime = GetPerformanceCounter();\r
+ PeriodicSmiLibraryHandler->DispatchCheckPointTime = GetPerformanceCounter ();\r
\r
if (PeriodicSmiLibraryHandler->YieldFlag) {\r
//\r
// elapsed since the previous time this periodic SMI handler was dispatched.\r
//\r
PeriodicSmiLibraryHandler->DispatchFunction (\r
- PeriodicSmiLibraryHandler->Context,\r
- PeriodicSmiLibraryHandler->ElapsedTime\r
- );\r
+ PeriodicSmiLibraryHandler->Context,\r
+ PeriodicSmiLibraryHandler->ElapsedTime\r
+ );\r
\r
//\r
// If this DispatchFunction() returns, then unconditionally call PeriodicSmiExit()\r
// Must never return\r
//\r
ASSERT (FALSE);\r
- CpuDeadLoop();\r
+ CpuDeadLoop ();\r
}\r
\r
/**\r
//\r
PeriodicSmiLibraryHandler->ElapsedTime = 0;\r
if (CommBuffer != NULL) {\r
- TimerContext = (EFI_SMM_PERIODIC_TIMER_CONTEXT *)CommBuffer;\r
+ TimerContext = (EFI_SMM_PERIODIC_TIMER_CONTEXT *)CommBuffer;\r
PeriodicSmiLibraryHandler->ElapsedTime = TimerContext->ElapsedTime;\r
}\r
\r
// Dispatch the periodic SMI handler\r
//\r
if ((PeriodicSmiLibraryHandler->Cpu == PERIODIC_SMI_LIBRARY_ANY_CPU) ||\r
- (PeriodicSmiLibraryHandler->Cpu == gSmst->CurrentlyExecutingCpu) ) {\r
+ (PeriodicSmiLibraryHandler->Cpu == gSmst->CurrentlyExecutingCpu))\r
+ {\r
//\r
// Dispatch on the currently execution CPU if the CPU specified in PeriodicSmiEnable()\r
// was PERIODIC_SMI_LIBRARY_ANY_CPU or the currently executing CPU matches the CPU\r
break;\r
}\r
}\r
+\r
if (gSmiTickPeriodTable[Index] == 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
- if (Cpu != PERIODIC_SMI_LIBRARY_ANY_CPU && Cpu >= gSmst->NumberOfCpus) {\r
+ if ((Cpu != PERIODIC_SMI_LIBRARY_ANY_CPU) && (Cpu >= gSmst->NumberOfCpus)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Find a free periodic SMI handler entry\r
//\r
- PeriodicSmiLibraryHandler = FindFreePeriodicSmiLibraryHandler();\r
+ PeriodicSmiLibraryHandler = FindFreePeriodicSmiLibraryHandler ();\r
if (PeriodicSmiLibraryHandler == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
if (PeriodicSmiLibraryHandler->Stack == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
ZeroMem (PeriodicSmiLibraryHandler->Stack, PeriodicSmiLibraryHandler->StackSize);\r
} else {\r
PeriodicSmiLibraryHandler->Stack = NULL;\r
}\r
+\r
InitializeSpinLock (&PeriodicSmiLibraryHandler->DispatchLock);\r
PeriodicSmiLibraryHandler->PerfomanceCounterRate = GetPerformanceCounterProperties (\r
&PeriodicSmiLibraryHandler->PerfomanceCounterStartValue,\r
);\r
PeriodicSmiLibraryHandler->RegisterContext.Period = TickPeriod;\r
PeriodicSmiLibraryHandler->RegisterContext.SmiTickInterval = TickPeriod;\r
- Status = gSmmPeriodicTimerDispatch2->Register (\r
- gSmmPeriodicTimerDispatch2,\r
- PeriodicSmiDispatchFunction,\r
- &PeriodicSmiLibraryHandler->RegisterContext,\r
- &PeriodicSmiLibraryHandler->DispatchHandle\r
- );\r
+ Status = gSmmPeriodicTimerDispatch2->Register (\r
+ gSmmPeriodicTimerDispatch2,\r
+ PeriodicSmiDispatchFunction,\r
+ &PeriodicSmiLibraryHandler->RegisterContext,\r
+ &PeriodicSmiLibraryHandler->DispatchHandle\r
+ );\r
if (EFI_ERROR (Status)) {\r
PeriodicSmiLibraryHandler->DispatchHandle = NULL;\r
ReclaimPeriodicSmiLibraryHandler (PeriodicSmiLibraryHandler);\r
if (DispatchHandle != NULL) {\r
*DispatchHandle = PeriodicSmiLibraryHandler->DispatchHandle;\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
// Dispatch 2 Protocol supports.\r
//\r
SmiTickInterval = NULL;\r
- Count = 0;\r
+ Count = 0;\r
do {\r
Status = gSmmPeriodicTimerDispatch2->GetNextShorterInterval (\r
gSmmPeriodicTimerDispatch2,\r
// Fill in the table of supported periodic SMI tick periods.\r
//\r
SmiTickInterval = NULL;\r
- Count = 0;\r
+ Count = 0;\r
do {\r
gSmiTickPeriodTable[Count] = 0;\r
- Status = gSmmPeriodicTimerDispatch2->GetNextShorterInterval (\r
- gSmmPeriodicTimerDispatch2,\r
- &SmiTickInterval\r
- );\r
+ Status = gSmmPeriodicTimerDispatch2->GetNextShorterInterval (\r
+ gSmmPeriodicTimerDispatch2,\r
+ &SmiTickInterval\r
+ );\r
if (SmiTickInterval != NULL) {\r
gSmiTickPeriodTable[Count] = *SmiTickInterval;\r
}\r
+\r
Count++;\r
} while (SmiTickInterval != NULL);\r
\r
//\r
for (Link = GetFirstNode (&gPeriodicSmiLibraryHandlers); !IsNull (&gPeriodicSmiLibraryHandlers, Link);) {\r
PeriodicSmiLibraryHandler = PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT_FROM_LINK (Link);\r
- Link = GetNextNode (&gPeriodicSmiLibraryHandlers, Link);\r
+ Link = GetNextNode (&gPeriodicSmiLibraryHandlers, Link);\r
PeriodicSmiDisable (PeriodicSmiLibraryHandler->DispatchHandle);\r
}\r
\r
//\r
for (Link = GetFirstNode (&gFreePeriodicSmiLibraryHandlers); !IsNull (&gFreePeriodicSmiLibraryHandlers, Link);) {\r
PeriodicSmiLibraryHandler = PERIODIC_SMI_LIBRARY_HANDLER_CONTEXT_FROM_LINK (Link);\r
- Link = RemoveEntryList (Link);\r
+ Link = RemoveEntryList (Link);\r
FreePool (PeriodicSmiLibraryHandler);\r
}\r
\r
#include <Library/SmmServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
\r
-EFI_SMM_SYSTEM_TABLE2 *gSmst = NULL;\r
+EFI_SMM_SYSTEM_TABLE2 *gSmst = NULL;\r
\r
/**\r
The constructor function caches the pointer of SMM Services Table.\r
EFI_STATUS\r
EFIAPI\r
_DriverUnloadHandler (\r
- EFI_HANDLE ImageHandle\r
+ EFI_HANDLE ImageHandle\r
)\r
{\r
EFI_STATUS Status;\r
EFI_STATUS\r
EFIAPI\r
_ModuleEntryPoint (\r
- IN EFI_HANDLE ImageHandle,\r
- IN IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN IN EFI_MM_SYSTEM_TABLE *MmSystemTable\r
)\r
{\r
EFI_STATUS Status;\r
#include <Library/MmServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
\r
-EFI_MM_SYSTEM_TABLE *gMmst = NULL;\r
+EFI_MM_SYSTEM_TABLE *gMmst = NULL;\r
\r
/**\r
The constructor function caches the pointer of the MM Services Table.\r
#include <Library/DebugLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
-\r
/**\r
Entry point to UEFI Application.\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (_gUefiDriverRevision != 0) {\r
//\r
return Status;\r
}\r
\r
-\r
/**\r
Invokes the library destructors for all dependent libraries and terminates\r
the UEFI Application.\r
gBS->Exit (gImageHandle, Status, 0, NULL);\r
}\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
\r
#include <Library/UefiBootServicesTableLib.h>\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
-extern BOOLEAN mPostEBS;\r
-extern EFI_SYSTEM_TABLE *mDebugST;\r
+extern BOOLEAN mPostEBS;\r
+extern EFI_SYSTEM_TABLE *mDebugST;\r
\r
/**\r
Prints a debug message to the debug output device if the specified error level is enabled.\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR16 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR16 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
if (!mPostEBS) {\r
//\r
UnicodeBSPrintAsciiFormat (Buffer, sizeof (Buffer), Format, BaseListMarker);\r
}\r
\r
-\r
//\r
// Send the print string to the Console Output device\r
//\r
}\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
//\r
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
//\r
// BOOLEAN value to indicate if it is at the post ExitBootServices pahse\r
//\r
-BOOLEAN mPostEBS = FALSE;\r
+BOOLEAN mPostEBS = FALSE;\r
\r
-static EFI_EVENT mExitBootServicesEvent;\r
+static EFI_EVENT mExitBootServicesEvent;\r
\r
//\r
// Pointer to SystemTable\r
// This library instance may have a cycle consume with UefiBootServicesTableLib\r
// because of the constructors.\r
//\r
-EFI_SYSTEM_TABLE *mDebugST;\r
+EFI_SYSTEM_TABLE *mDebugST;\r
\r
/**\r
This routine sets the mPostEBS for exit boot servies true\r
VOID\r
EFIAPI\r
ExitBootServicesCallback (\r
- EFI_EVENT Event,\r
- VOID* Context\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
)\r
{\r
mPostEBS = TRUE;\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibConstructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibConstructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
mDebugST = SystemTable;\r
\r
SystemTable->BootServices->CreateEvent (\r
- EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
- TPL_NOTIFY,\r
- ExitBootServicesCallback,\r
- NULL,\r
- &mExitBootServicesEvent\r
- );\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ ExitBootServicesCallback,\r
+ NULL,\r
+ &mExitBootServicesEvent\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibDestructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibDestructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
if (mExitBootServicesEvent != NULL) {\r
//\r
// Define the timeout for EFI_DEBUGPORT_PROTOCOL.Write\r
//\r
-#define WRITE_TIMEOUT 1000\r
+#define WRITE_TIMEOUT 1000\r
\r
-\r
-EFI_DEBUGPORT_PROTOCOL *mDebugPort = NULL;\r
+EFI_DEBUGPORT_PROTOCOL *mDebugPort = NULL;\r
\r
//\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
-extern BOOLEAN mPostEBS;\r
-extern EFI_BOOT_SERVICES *mDebugBS;\r
+extern BOOLEAN mPostEBS;\r
+extern EFI_BOOT_SERVICES *mDebugBS;\r
\r
/**\r
Send message to DebugPort Protocol.\r
IN UINTN BufferLength\r
)\r
{\r
- UINTN Length;\r
- EFI_STATUS Status;\r
+ UINTN Length;\r
+ EFI_STATUS Status;\r
\r
if (!mPostEBS) {\r
//\r
// If mDebugPort is NULL, initialize first.\r
//\r
if (mDebugPort == NULL) {\r
- Status = mDebugBS->LocateProtocol (&gEfiDebugPortProtocolGuid, NULL, (VOID **)&mDebugPort);\r
- if (EFI_ERROR (Status)) {\r
- return;\r
- }\r
+ Status = mDebugBS->LocateProtocol (&gEfiDebugPortProtocolGuid, NULL, (VOID **)&mDebugPort);\r
+ if (EFI_ERROR (Status)) {\r
+ return;\r
+ }\r
\r
- mDebugPort->Reset (mDebugPort);\r
+ mDebugPort->Reset (mDebugPort);\r
}\r
\r
//\r
while (BufferLength > 0) {\r
Length = BufferLength;\r
\r
- Status = mDebugPort->Write (mDebugPort, WRITE_TIMEOUT, &Length, (VOID *) Buffer);\r
- if (EFI_ERROR (Status) || BufferLength < Length) {\r
+ Status = mDebugPort->Write (mDebugPort, WRITE_TIMEOUT, &Length, (VOID *)Buffer);\r
+ if (EFI_ERROR (Status) || (BufferLength < Length)) {\r
break;\r
}\r
\r
- Buffer += Length;\r
+ Buffer += Length;\r
BufferLength -= Length;\r
}\r
}\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
VA_START (Marker, Format);\r
DebugVPrint (ErrorLevel, Format, Marker);\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
if (!mPostEBS) {\r
//\r
}\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
//\r
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
-\r
//\r
// BOOLEAN value to indicate if it is at the post ExitBootServices pahse\r
//\r
-BOOLEAN mPostEBS = FALSE;\r
+BOOLEAN mPostEBS = FALSE;\r
\r
-static EFI_EVENT mExitBootServicesEvent;\r
+static EFI_EVENT mExitBootServicesEvent;\r
\r
//\r
// Pointer to SystemTable\r
// This library instance may have a cycle consume with UefiBootServicesTableLib\r
// because of the constructors.\r
//\r
-EFI_BOOT_SERVICES *mDebugBS;\r
+EFI_BOOT_SERVICES *mDebugBS;\r
\r
/**\r
This routine sets the mPostEBS for exit boot servies true\r
VOID\r
EFIAPI\r
ExitBootServicesCallback (\r
- EFI_EVENT Event,\r
- VOID* Context\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
)\r
{\r
mPostEBS = TRUE;\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibConstructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibConstructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
mDebugBS = SystemTable->BootServices;\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibDestructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibDestructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
if (mExitBootServicesEvent != NULL) {\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
\r
#include <Library/DebugLib.h>\r
//\r
#define MAX_DEBUG_MESSAGE_LENGTH 0x100\r
\r
-\r
//\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
-extern BOOLEAN mPostEBS;\r
-extern EFI_SYSTEM_TABLE *mDebugST;\r
+extern BOOLEAN mPostEBS;\r
+extern EFI_SYSTEM_TABLE *mDebugST;\r
\r
/**\r
Prints a debug message to the debug output device if the specified error level is enabled.\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
VA_START (Marker, Format);\r
DebugVPrint (ErrorLevel, Format, Marker);\r
VA_END (Marker);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled base on Null-terminated format string and a\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR16 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR16 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
if (!mPostEBS) {\r
//\r
}\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
}\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified\r
error level is enabled.\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
}\r
\r
-\r
/**\r
Prints an assert message containing a filename, line number, and description.\r
This may be followed by a breakpoint or a dead loop.\r
//\r
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings\r
//\r
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {\r
CpuBreakpoint ();\r
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {\r
CpuDeadLoop ();\r
}\r
}\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
//\r
// SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
//\r
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CODE() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
//\r
// BOOLEAN value to indicate if it is at the post ExitBootServices pahse\r
//\r
-BOOLEAN mPostEBS = FALSE;\r
+BOOLEAN mPostEBS = FALSE;\r
\r
-static EFI_EVENT mExitBootServicesEvent;\r
+static EFI_EVENT mExitBootServicesEvent;\r
\r
//\r
// Pointer to SystemTable\r
// This library instance may have a cycle consume with UefiBootServicesTableLib\r
// because of the constructors.\r
//\r
-EFI_SYSTEM_TABLE *mDebugST;\r
+EFI_SYSTEM_TABLE *mDebugST;\r
\r
/**\r
This routine sets the mPostEBS for exit boot servies true\r
VOID\r
EFIAPI\r
ExitBootServicesCallback (\r
- EFI_EVENT Event,\r
- VOID* Context\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
)\r
{\r
mPostEBS = TRUE;\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibConstructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibConstructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
mDebugST = SystemTable;\r
\r
SystemTable->BootServices->CreateEvent (\r
- EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
- TPL_NOTIFY,\r
- ExitBootServicesCallback,\r
- NULL,\r
- &mExitBootServicesEvent\r
- );\r
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,\r
+ TPL_NOTIFY,\r
+ ExitBootServicesCallback,\r
+ NULL,\r
+ &mExitBootServicesEvent\r
+ );\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-DxeDebugLibDestructor(\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+DxeDebugLibDestructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
if (mExitBootServicesEvent != NULL) {\r
**/\r
CHAR16 *\r
GetParamByNodeName (\r
- IN CHAR16 *Str,\r
- IN CHAR16 *NodeName\r
+ IN CHAR16 *Str,\r
+ IN CHAR16 *NodeName\r
)\r
{\r
CHAR16 *ParamStr;\r
//\r
ParamStr++;\r
ParameterLength = 0;\r
- StrPointer = ParamStr;\r
+ StrPointer = ParamStr;\r
while (!IS_NULL (*StrPointer)) {\r
if (IS_RIGHT_PARENTH (*StrPointer)) {\r
break;\r
}\r
+\r
StrPointer++;\r
ParameterLength++;\r
}\r
+\r
if (IS_NULL (*StrPointer)) {\r
//\r
// ')' not found\r
if (ParamStr == NULL) {\r
return NULL;\r
}\r
+\r
//\r
// Terminate the parameter string\r
//\r
**/\r
CHAR16 *\r
SplitStr (\r
- IN OUT CHAR16 **List,\r
- IN CHAR16 Separator\r
+ IN OUT CHAR16 **List,\r
+ IN CHAR16 Separator\r
)\r
{\r
CHAR16 *Str;\r
CHAR16 *ReturnStr;\r
\r
- Str = *List;\r
+ Str = *List;\r
ReturnStr = Str;\r
\r
if (IS_NULL (*Str)) {\r
if (*Str == Separator) {\r
break;\r
}\r
+\r
Str++;\r
}\r
\r
**/\r
CHAR16 *\r
GetNextParamStr (\r
- IN OUT CHAR16 **List\r
+ IN OUT CHAR16 **List\r
)\r
{\r
//\r
if (!IS_SLASH (*Str) &&\r
!IS_COMMA (*Str) &&\r
!IS_LEFT_PARENTH (*Str) &&\r
- !IS_RIGHT_PARENTH (*Str)) {\r
+ !IS_RIGHT_PARENTH (*Str))\r
+ {\r
break;\r
}\r
+\r
Str++;\r
}\r
\r
\r
if (IS_COMMA (*Str)) {\r
*IsInstanceEnd = TRUE;\r
- *Str = L'\0';\r
+ *Str = L'\0';\r
Str++;\r
} else {\r
*IsInstanceEnd = FALSE;\r
return ReturnStr;\r
}\r
\r
-\r
/**\r
Return whether the integer string is a hex string.\r
\r
**/\r
BOOLEAN\r
IsHexStr (\r
- IN CHAR16 *Str\r
+ IN CHAR16 *Str\r
)\r
{\r
//\r
// skip preceeding white space\r
//\r
while ((*Str != 0) && *Str == L' ') {\r
- Str ++;\r
+ Str++;\r
}\r
+\r
//\r
// skip preceeding zeros\r
//\r
while ((*Str != 0) && *Str == L'0') {\r
- Str ++;\r
+ Str++;\r
}\r
\r
- return (BOOLEAN) (*Str == L'x' || *Str == L'X');\r
+ return (BOOLEAN)(*Str == L'x' || *Str == L'X');\r
}\r
\r
/**\r
**/\r
VOID\r
StrToAscii (\r
- IN CHAR16 *Str,\r
- IN OUT CHAR8 **AsciiStr\r
+ IN CHAR16 *Str,\r
+ IN OUT CHAR8 **AsciiStr\r
)\r
{\r
- CHAR8 *Dest;\r
+ CHAR8 *Dest;\r
\r
Dest = *AsciiStr;\r
while (!IS_NULL (*Str)) {\r
- *(Dest++) = (CHAR8) *(Str++);\r
+ *(Dest++) = (CHAR8)*(Str++);\r
}\r
+\r
*Dest = 0;\r
\r
//\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextGenericPath (\r
- IN UINT8 Type,\r
- IN CHAR16 *TextDeviceNode\r
+ IN UINT8 Type,\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- EFI_DEVICE_PATH_PROTOCOL *Node;\r
- CHAR16 *SubtypeStr;\r
- CHAR16 *DataStr;\r
- UINTN DataLength;\r
+ EFI_DEVICE_PATH_PROTOCOL *Node;\r
+ CHAR16 *SubtypeStr;\r
+ CHAR16 *DataStr;\r
+ UINTN DataLength;\r
\r
SubtypeStr = GetNextParamStr (&TextDeviceNode);\r
DataStr = GetNextParamStr (&TextDeviceNode);\r
} else {\r
DataLength = StrLen (DataStr) / 2;\r
}\r
+\r
Node = CreateDeviceNode (\r
Type,\r
- (UINT8) Strtoi (SubtypeStr),\r
- (UINT16) (sizeof (EFI_DEVICE_PATH_PROTOCOL) + DataLength)\r
+ (UINT8)Strtoi (SubtypeStr),\r
+ (UINT16)(sizeof (EFI_DEVICE_PATH_PROTOCOL) + DataLength)\r
);\r
\r
- StrHexToBytes (DataStr, DataLength * 2, (UINT8 *) (Node + 1), DataLength);\r
+ StrHexToBytes (DataStr, DataLength * 2, (UINT8 *)(Node + 1), DataLength);\r
return Node;\r
}\r
\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *TypeStr;\r
+ CHAR16 *TypeStr;\r
\r
- TypeStr = GetNextParamStr (&TextDeviceNode);\r
+ TypeStr = GetNextParamStr (&TextDeviceNode);\r
\r
- return DevPathFromTextGenericPath ((UINT8) Strtoi (TypeStr), TextDeviceNode);\r
+ return DevPathFromTextGenericPath ((UINT8)Strtoi (TypeStr), TextDeviceNode);\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextHardwarePath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return DevPathFromTextGenericPath (HARDWARE_DEVICE_PATH, TextDeviceNode);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPci (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *FunctionStr;\r
- CHAR16 *DeviceStr;\r
- PCI_DEVICE_PATH *Pci;\r
+ CHAR16 *FunctionStr;\r
+ CHAR16 *DeviceStr;\r
+ PCI_DEVICE_PATH *Pci;\r
\r
DeviceStr = GetNextParamStr (&TextDeviceNode);\r
FunctionStr = GetNextParamStr (&TextDeviceNode);\r
- Pci = (PCI_DEVICE_PATH *) CreateDeviceNode (\r
- HARDWARE_DEVICE_PATH,\r
- HW_PCI_DP,\r
- (UINT16) sizeof (PCI_DEVICE_PATH)\r
- );\r
+ Pci = (PCI_DEVICE_PATH *)CreateDeviceNode (\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_PCI_DP,\r
+ (UINT16)sizeof (PCI_DEVICE_PATH)\r
+ );\r
\r
- Pci->Function = (UINT8) Strtoi (FunctionStr);\r
- Pci->Device = (UINT8) Strtoi (DeviceStr);\r
+ Pci->Function = (UINT8)Strtoi (FunctionStr);\r
+ Pci->Device = (UINT8)Strtoi (DeviceStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Pci;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Pci;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPcCard (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *FunctionNumberStr;\r
PCCARD_DEVICE_PATH *Pccard;\r
\r
FunctionNumberStr = GetNextParamStr (&TextDeviceNode);\r
- Pccard = (PCCARD_DEVICE_PATH *) CreateDeviceNode (\r
- HARDWARE_DEVICE_PATH,\r
- HW_PCCARD_DP,\r
- (UINT16) sizeof (PCCARD_DEVICE_PATH)\r
- );\r
+ Pccard = (PCCARD_DEVICE_PATH *)CreateDeviceNode (\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_PCCARD_DP,\r
+ (UINT16)sizeof (PCCARD_DEVICE_PATH)\r
+ );\r
\r
- Pccard->FunctionNumber = (UINT8) Strtoi (FunctionNumberStr);\r
+ Pccard->FunctionNumber = (UINT8)Strtoi (FunctionNumberStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Pccard;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Pccard;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextMemoryMapped (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *MemoryTypeStr;\r
MemoryTypeStr = GetNextParamStr (&TextDeviceNode);\r
StartingAddressStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddressStr = GetNextParamStr (&TextDeviceNode);\r
- MemMap = (MEMMAP_DEVICE_PATH *) CreateDeviceNode (\r
+ MemMap = (MEMMAP_DEVICE_PATH *)CreateDeviceNode (\r
HARDWARE_DEVICE_PATH,\r
HW_MEMMAP_DP,\r
- (UINT16) sizeof (MEMMAP_DEVICE_PATH)\r
+ (UINT16)sizeof (MEMMAP_DEVICE_PATH)\r
);\r
\r
- MemMap->MemoryType = (UINT32) Strtoi (MemoryTypeStr);\r
+ MemMap->MemoryType = (UINT32)Strtoi (MemoryTypeStr);\r
Strtoi64 (StartingAddressStr, &MemMap->StartingAddress);\r
Strtoi64 (EndingAddressStr, &MemMap->EndingAddress);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) MemMap;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)MemMap;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
ConvertFromTextVendor (\r
- IN CHAR16 *TextDeviceNode,\r
- IN UINT8 Type,\r
- IN UINT8 SubType\r
+ IN CHAR16 *TextDeviceNode,\r
+ IN UINT8 Type,\r
+ IN UINT8 SubType\r
)\r
{\r
CHAR16 *GuidStr;\r
//\r
// Two hex characters make up 1 buffer byte\r
//\r
- Length = (Length + 1) / 2;\r
+ Length = (Length + 1) / 2;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- Type,\r
- SubType,\r
- (UINT16) (sizeof (VENDOR_DEVICE_PATH) + Length)\r
- );\r
+ Vendor = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ Type,\r
+ SubType,\r
+ (UINT16)(sizeof (VENDOR_DEVICE_PATH) + Length)\r
+ );\r
\r
StrToGuid (GuidStr, &Vendor->Guid);\r
- StrHexToBytes (DataStr, Length * 2, (UINT8 *) (Vendor + 1), Length);\r
+ StrHexToBytes (DataStr, Length * 2, (UINT8 *)(Vendor + 1), Length);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vendor;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vendor;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenHw (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextVendor (\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextCtrl (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *ControllerStr;\r
CONTROLLER_DEVICE_PATH *Controller;\r
\r
ControllerStr = GetNextParamStr (&TextDeviceNode);\r
- Controller = (CONTROLLER_DEVICE_PATH *) CreateDeviceNode (\r
- HARDWARE_DEVICE_PATH,\r
- HW_CONTROLLER_DP,\r
- (UINT16) sizeof (CONTROLLER_DEVICE_PATH)\r
- );\r
- Controller->ControllerNumber = (UINT32) Strtoi (ControllerStr);\r
+ Controller = (CONTROLLER_DEVICE_PATH *)CreateDeviceNode (\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_CONTROLLER_DP,\r
+ (UINT16)sizeof (CONTROLLER_DEVICE_PATH)\r
+ );\r
+ Controller->ControllerNumber = (UINT32)Strtoi (ControllerStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Controller;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Controller;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextBmc (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *InterfaceTypeStr;\r
- CHAR16 *BaseAddressStr;\r
- BMC_DEVICE_PATH *BmcDp;\r
+ CHAR16 *InterfaceTypeStr;\r
+ CHAR16 *BaseAddressStr;\r
+ BMC_DEVICE_PATH *BmcDp;\r
\r
InterfaceTypeStr = GetNextParamStr (&TextDeviceNode);\r
BaseAddressStr = GetNextParamStr (&TextDeviceNode);\r
- BmcDp = (BMC_DEVICE_PATH *) CreateDeviceNode (\r
- HARDWARE_DEVICE_PATH,\r
- HW_BMC_DP,\r
- (UINT16) sizeof (BMC_DEVICE_PATH)\r
- );\r
+ BmcDp = (BMC_DEVICE_PATH *)CreateDeviceNode (\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_BMC_DP,\r
+ (UINT16)sizeof (BMC_DEVICE_PATH)\r
+ );\r
\r
- BmcDp->InterfaceType = (UINT8) Strtoi (InterfaceTypeStr);\r
+ BmcDp->InterfaceType = (UINT8)Strtoi (InterfaceTypeStr);\r
WriteUnaligned64 (\r
- (UINT64 *) (&BmcDp->BaseAddress),\r
+ (UINT64 *)(&BmcDp->BaseAddress),\r
StrHexToUint64 (BaseAddressStr)\r
);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) BmcDp;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)BmcDp;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAcpiPath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return DevPathFromTextGenericPath (ACPI_DEVICE_PATH, TextDeviceNode);\r
**/\r
UINT32\r
EisaIdFromText (\r
- IN CHAR16 *Text\r
+ IN CHAR16 *Text\r
)\r
{\r
return (((Text[0] - 'A' + 1) & 0x1f) << 10)\r
- + (((Text[1] - 'A' + 1) & 0x1f) << 5)\r
- + (((Text[2] - 'A' + 1) & 0x1f) << 0)\r
- + (UINT32) (StrHexToUintn (&Text[3]) << 16)\r
- ;\r
+ + (((Text[1] - 'A' + 1) & 0x1f) << 5)\r
+ + (((Text[2] - 'A' + 1) & 0x1f) << 0)\r
+ + (UINT32)(StrHexToUintn (&Text[3]) << 16)\r
+ ;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAcpi (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *HIDStr;\r
\r
HIDStr = GetNextParamStr (&TextDeviceNode);\r
UIDStr = GetNextParamStr (&TextDeviceNode);\r
- Acpi = (ACPI_HID_DEVICE_PATH *) CreateDeviceNode (\r
- ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- (UINT16) sizeof (ACPI_HID_DEVICE_PATH)\r
- );\r
+ Acpi = (ACPI_HID_DEVICE_PATH *)CreateDeviceNode (\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ (UINT16)sizeof (ACPI_HID_DEVICE_PATH)\r
+ );\r
\r
Acpi->HID = EisaIdFromText (HIDStr);\r
- Acpi->UID = (UINT32) Strtoi (UIDStr);\r
+ Acpi->UID = (UINT32)Strtoi (UIDStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Acpi;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Acpi;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
ConvertFromTextAcpi (\r
- IN CHAR16 *TextDeviceNode,\r
+ IN CHAR16 *TextDeviceNode,\r
IN UINT32 PnPId\r
)\r
{\r
ACPI_HID_DEVICE_PATH *Acpi;\r
\r
UIDStr = GetNextParamStr (&TextDeviceNode);\r
- Acpi = (ACPI_HID_DEVICE_PATH *) CreateDeviceNode (\r
- ACPI_DEVICE_PATH,\r
- ACPI_DP,\r
- (UINT16) sizeof (ACPI_HID_DEVICE_PATH)\r
- );\r
+ Acpi = (ACPI_HID_DEVICE_PATH *)CreateDeviceNode (\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ (UINT16)sizeof (ACPI_HID_DEVICE_PATH)\r
+ );\r
\r
Acpi->HID = EFI_PNP_ID (PnPId);\r
- Acpi->UID = (UINT32) Strtoi (UIDStr);\r
+ Acpi->UID = (UINT32)Strtoi (UIDStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Acpi;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Acpi;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPciRoot (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0a03);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPcieRoot (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0a08);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFloppy (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0604);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextKeyboard (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0301);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextSerial (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0501);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextParallelPort (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextAcpi (TextDeviceNode, 0x0401);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAcpiEx (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *HIDStr;\r
CIDSTRStr = GetNextParamStr (&TextDeviceNode);\r
UIDSTRStr = GetNextParamStr (&TextDeviceNode);\r
\r
- Length = (UINT16) (sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + StrLen (HIDSTRStr) + 1);\r
- Length = (UINT16) (Length + StrLen (UIDSTRStr) + 1);\r
- Length = (UINT16) (Length + StrLen (CIDSTRStr) + 1);\r
- AcpiEx = (ACPI_EXTENDED_HID_DEVICE_PATH *) CreateDeviceNode (\r
- ACPI_DEVICE_PATH,\r
- ACPI_EXTENDED_DP,\r
- Length\r
- );\r
+ Length = (UINT16)(sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + StrLen (HIDSTRStr) + 1);\r
+ Length = (UINT16)(Length + StrLen (UIDSTRStr) + 1);\r
+ Length = (UINT16)(Length + StrLen (CIDSTRStr) + 1);\r
+ AcpiEx = (ACPI_EXTENDED_HID_DEVICE_PATH *)CreateDeviceNode (\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_EXTENDED_DP,\r
+ Length\r
+ );\r
\r
AcpiEx->HID = EisaIdFromText (HIDStr);\r
AcpiEx->CID = EisaIdFromText (CIDStr);\r
- AcpiEx->UID = (UINT32) Strtoi (UIDStr);\r
+ AcpiEx->UID = (UINT32)Strtoi (UIDStr);\r
\r
- AsciiStr = (CHAR8 *) ((UINT8 *)AcpiEx + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
+ AsciiStr = (CHAR8 *)((UINT8 *)AcpiEx + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
StrToAscii (HIDSTRStr, &AsciiStr);\r
StrToAscii (UIDSTRStr, &AsciiStr);\r
StrToAscii (CIDSTRStr, &AsciiStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) AcpiEx;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)AcpiEx;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAcpiExp (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *HIDStr;\r
HIDStr = GetNextParamStr (&TextDeviceNode);\r
CIDStr = GetNextParamStr (&TextDeviceNode);\r
UIDSTRStr = GetNextParamStr (&TextDeviceNode);\r
- Length = (UINT16) (sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + StrLen (UIDSTRStr) + 3);\r
- AcpiEx = (ACPI_EXTENDED_HID_DEVICE_PATH *) CreateDeviceNode (\r
- ACPI_DEVICE_PATH,\r
- ACPI_EXTENDED_DP,\r
- Length\r
- );\r
+ Length = (UINT16)(sizeof (ACPI_EXTENDED_HID_DEVICE_PATH) + StrLen (UIDSTRStr) + 3);\r
+ AcpiEx = (ACPI_EXTENDED_HID_DEVICE_PATH *)CreateDeviceNode (\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_EXTENDED_DP,\r
+ Length\r
+ );\r
\r
AcpiEx->HID = EisaIdFromText (HIDStr);\r
//\r
// So when the CID parametr is not specified or specified as 0 in the text device node.\r
// Set the CID to 0 in the ACPI extension device path structure.\r
//\r
- if (*CIDStr == L'\0' || *CIDStr == L'0') {\r
+ if ((*CIDStr == L'\0') || (*CIDStr == L'0')) {\r
AcpiEx->CID = 0;\r
} else {\r
AcpiEx->CID = EisaIdFromText (CIDStr);\r
}\r
+\r
AcpiEx->UID = 0;\r
\r
- AsciiStr = (CHAR8 *) ((UINT8 *)AcpiEx + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
+ AsciiStr = (CHAR8 *)((UINT8 *)AcpiEx + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
//\r
// HID string is NULL\r
//\r
//\r
*AsciiStr = '\0';\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) AcpiEx;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)AcpiEx;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAcpiAdr (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *DisplayDeviceStr;\r
UINTN Index;\r
UINTN Length;\r
\r
- AcpiAdr = (ACPI_ADR_DEVICE_PATH *) CreateDeviceNode (\r
- ACPI_DEVICE_PATH,\r
- ACPI_ADR_DP,\r
- (UINT16) sizeof (ACPI_ADR_DEVICE_PATH)\r
- );\r
+ AcpiAdr = (ACPI_ADR_DEVICE_PATH *)CreateDeviceNode (\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_ADR_DP,\r
+ (UINT16)sizeof (ACPI_ADR_DEVICE_PATH)\r
+ );\r
ASSERT (AcpiAdr != NULL);\r
\r
for (Index = 0; ; Index++) {\r
if (IS_NULL (*DisplayDeviceStr)) {\r
break;\r
}\r
+\r
if (Index > 0) {\r
Length = DevicePathNodeLength (AcpiAdr);\r
AcpiAdr = ReallocatePool (\r
SetDevicePathNodeLength (AcpiAdr, Length + sizeof (UINT32));\r
}\r
\r
- (&AcpiAdr->ADR)[Index] = (UINT32) Strtoi (DisplayDeviceStr);\r
+ (&AcpiAdr->ADR)[Index] = (UINT32)Strtoi (DisplayDeviceStr);\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) AcpiAdr;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)AcpiAdr;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextMsg (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return DevPathFromTextGenericPath (MESSAGING_DEVICE_PATH, TextDeviceNode);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextAta (\r
-IN CHAR16 *TextDeviceNode\r
-)\r
+ IN CHAR16 *TextDeviceNode\r
+ )\r
{\r
- CHAR16 *PrimarySecondaryStr;\r
- CHAR16 *SlaveMasterStr;\r
- CHAR16 *LunStr;\r
- ATAPI_DEVICE_PATH *Atapi;\r
+ CHAR16 *PrimarySecondaryStr;\r
+ CHAR16 *SlaveMasterStr;\r
+ CHAR16 *LunStr;\r
+ ATAPI_DEVICE_PATH *Atapi;\r
\r
- Atapi = (ATAPI_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_ATAPI_DP,\r
- (UINT16) sizeof (ATAPI_DEVICE_PATH)\r
- );\r
+ Atapi = (ATAPI_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_ATAPI_DP,\r
+ (UINT16)sizeof (ATAPI_DEVICE_PATH)\r
+ );\r
\r
PrimarySecondaryStr = GetNextParamStr (&TextDeviceNode);\r
SlaveMasterStr = GetNextParamStr (&TextDeviceNode);\r
} else if (StrCmp (PrimarySecondaryStr, L"Secondary") == 0) {\r
Atapi->PrimarySecondary = 1;\r
} else {\r
- Atapi->PrimarySecondary = (UINT8) Strtoi (PrimarySecondaryStr);\r
+ Atapi->PrimarySecondary = (UINT8)Strtoi (PrimarySecondaryStr);\r
}\r
+\r
if (StrCmp (SlaveMasterStr, L"Master") == 0) {\r
- Atapi->SlaveMaster = 0;\r
+ Atapi->SlaveMaster = 0;\r
} else if (StrCmp (SlaveMasterStr, L"Slave") == 0) {\r
- Atapi->SlaveMaster = 1;\r
+ Atapi->SlaveMaster = 1;\r
} else {\r
- Atapi->SlaveMaster = (UINT8) Strtoi (SlaveMasterStr);\r
+ Atapi->SlaveMaster = (UINT8)Strtoi (SlaveMasterStr);\r
}\r
\r
- Atapi->Lun = (UINT16) Strtoi (LunStr);\r
+ Atapi->Lun = (UINT16)Strtoi (LunStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Atapi;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Atapi;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextScsi (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *PunStr;\r
\r
PunStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
- Scsi = (SCSI_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_SCSI_DP,\r
- (UINT16) sizeof (SCSI_DEVICE_PATH)\r
- );\r
+ Scsi = (SCSI_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_SCSI_DP,\r
+ (UINT16)sizeof (SCSI_DEVICE_PATH)\r
+ );\r
\r
- Scsi->Pun = (UINT16) Strtoi (PunStr);\r
- Scsi->Lun = (UINT16) Strtoi (LunStr);\r
+ Scsi->Pun = (UINT16)Strtoi (PunStr);\r
+ Scsi->Lun = (UINT16)Strtoi (LunStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Scsi;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Scsi;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFibre (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *WWNStr;\r
\r
WWNStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
- Fibre = (FIBRECHANNEL_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_FIBRECHANNEL_DP,\r
- (UINT16) sizeof (FIBRECHANNEL_DEVICE_PATH)\r
- );\r
+ Fibre = (FIBRECHANNEL_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_FIBRECHANNEL_DP,\r
+ (UINT16)sizeof (FIBRECHANNEL_DEVICE_PATH)\r
+ );\r
\r
Fibre->Reserved = 0;\r
Strtoi64 (WWNStr, &Fibre->WWN);\r
Strtoi64 (LunStr, &Fibre->Lun);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Fibre;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Fibre;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFibreEx (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *WWNStr;\r
\r
WWNStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
- FibreEx = (FIBRECHANNELEX_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_FIBRECHANNELEX_DP,\r
- (UINT16) sizeof (FIBRECHANNELEX_DEVICE_PATH)\r
- );\r
+ FibreEx = (FIBRECHANNELEX_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_FIBRECHANNELEX_DP,\r
+ (UINT16)sizeof (FIBRECHANNELEX_DEVICE_PATH)\r
+ );\r
\r
FibreEx->Reserved = 0;\r
- Strtoi64 (WWNStr, (UINT64 *) (&FibreEx->WWN));\r
- Strtoi64 (LunStr, (UINT64 *) (&FibreEx->Lun));\r
+ Strtoi64 (WWNStr, (UINT64 *)(&FibreEx->WWN));\r
+ Strtoi64 (LunStr, (UINT64 *)(&FibreEx->Lun));\r
\r
- *(UINT64 *) (&FibreEx->WWN) = SwapBytes64 (*(UINT64 *) (&FibreEx->WWN));\r
- *(UINT64 *) (&FibreEx->Lun) = SwapBytes64 (*(UINT64 *) (&FibreEx->Lun));\r
+ *(UINT64 *)(&FibreEx->WWN) = SwapBytes64 (*(UINT64 *)(&FibreEx->WWN));\r
+ *(UINT64 *)(&FibreEx->Lun) = SwapBytes64 (*(UINT64 *)(&FibreEx->Lun));\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) FibreEx;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)FibreEx;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromText1394 (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *GuidStr;\r
- F1394_DEVICE_PATH *F1394DevPath;\r
+ CHAR16 *GuidStr;\r
+ F1394_DEVICE_PATH *F1394DevPath;\r
\r
- GuidStr = GetNextParamStr (&TextDeviceNode);\r
- F1394DevPath = (F1394_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_1394_DP,\r
- (UINT16) sizeof (F1394_DEVICE_PATH)\r
- );\r
+ GuidStr = GetNextParamStr (&TextDeviceNode);\r
+ F1394DevPath = (F1394_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_1394_DP,\r
+ (UINT16)sizeof (F1394_DEVICE_PATH)\r
+ );\r
\r
F1394DevPath->Reserved = 0;\r
F1394DevPath->Guid = StrHexToUint64 (GuidStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) F1394DevPath;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)F1394DevPath;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsb (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *PortStr;\r
- CHAR16 *InterfaceStr;\r
- USB_DEVICE_PATH *Usb;\r
+ CHAR16 *PortStr;\r
+ CHAR16 *InterfaceStr;\r
+ USB_DEVICE_PATH *Usb;\r
\r
- PortStr = GetNextParamStr (&TextDeviceNode);\r
- InterfaceStr = GetNextParamStr (&TextDeviceNode);\r
- Usb = (USB_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_USB_DP,\r
- (UINT16) sizeof (USB_DEVICE_PATH)\r
- );\r
+ PortStr = GetNextParamStr (&TextDeviceNode);\r
+ InterfaceStr = GetNextParamStr (&TextDeviceNode);\r
+ Usb = (USB_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_USB_DP,\r
+ (UINT16)sizeof (USB_DEVICE_PATH)\r
+ );\r
\r
- Usb->ParentPortNumber = (UINT8) Strtoi (PortStr);\r
- Usb->InterfaceNumber = (UINT8) Strtoi (InterfaceStr);\r
+ Usb->ParentPortNumber = (UINT8)Strtoi (PortStr);\r
+ Usb->InterfaceNumber = (UINT8)Strtoi (InterfaceStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Usb;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Usb;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextI2O (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *TIDStr;\r
- I2O_DEVICE_PATH *I2ODevPath;\r
+ CHAR16 *TIDStr;\r
+ I2O_DEVICE_PATH *I2ODevPath;\r
\r
TIDStr = GetNextParamStr (&TextDeviceNode);\r
- I2ODevPath = (I2O_DEVICE_PATH *) CreateDeviceNode (\r
+ I2ODevPath = (I2O_DEVICE_PATH *)CreateDeviceNode (\r
MESSAGING_DEVICE_PATH,\r
MSG_I2O_DP,\r
- (UINT16) sizeof (I2O_DEVICE_PATH)\r
+ (UINT16)sizeof (I2O_DEVICE_PATH)\r
);\r
\r
- I2ODevPath->Tid = (UINT32) Strtoi (TIDStr);\r
+ I2ODevPath->Tid = (UINT32)Strtoi (TIDStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) I2ODevPath;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)I2ODevPath;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextInfiniband (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *FlagsStr;\r
SidStr = GetNextParamStr (&TextDeviceNode);\r
TidStr = GetNextParamStr (&TextDeviceNode);\r
DidStr = GetNextParamStr (&TextDeviceNode);\r
- InfiniBand = (INFINIBAND_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_INFINIBAND_DP,\r
- (UINT16) sizeof (INFINIBAND_DEVICE_PATH)\r
- );\r
+ InfiniBand = (INFINIBAND_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_INFINIBAND_DP,\r
+ (UINT16)sizeof (INFINIBAND_DEVICE_PATH)\r
+ );\r
\r
- InfiniBand->ResourceFlags = (UINT32) Strtoi (FlagsStr);\r
- StrToGuid (GuidStr, (EFI_GUID *) InfiniBand->PortGid);\r
+ InfiniBand->ResourceFlags = (UINT32)Strtoi (FlagsStr);\r
+ StrToGuid (GuidStr, (EFI_GUID *)InfiniBand->PortGid);\r
Strtoi64 (SidStr, &InfiniBand->ServiceId);\r
Strtoi64 (TidStr, &InfiniBand->TargetPortId);\r
Strtoi64 (DidStr, &InfiniBand->DeviceId);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) InfiniBand;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)InfiniBand;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenMsg (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextVendor (\r
- TextDeviceNode,\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP\r
- );\r
+ TextDeviceNode,\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP\r
+ );\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenPcAnsi (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
VENDOR_DEVICE_PATH *Vendor;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (VENDOR_DEVICE_PATH));\r
+ Vendor = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (VENDOR_DEVICE_PATH)\r
+ );\r
CopyGuid (&Vendor->Guid, &gEfiPcAnsiGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vendor;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vendor;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenVt100 (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
VENDOR_DEVICE_PATH *Vendor;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (VENDOR_DEVICE_PATH));\r
+ Vendor = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (VENDOR_DEVICE_PATH)\r
+ );\r
CopyGuid (&Vendor->Guid, &gEfiVT100Guid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vendor;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vendor;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenVt100Plus (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
VENDOR_DEVICE_PATH *Vendor;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (VENDOR_DEVICE_PATH));\r
+ Vendor = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (VENDOR_DEVICE_PATH)\r
+ );\r
CopyGuid (&Vendor->Guid, &gEfiVT100PlusGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vendor;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vendor;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenUtf8 (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
VENDOR_DEVICE_PATH *Vendor;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (VENDOR_DEVICE_PATH));\r
+ Vendor = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (VENDOR_DEVICE_PATH)\r
+ );\r
CopyGuid (&Vendor->Guid, &gEfiVTUTF8Guid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vendor;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vendor;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUartFlowCtrl (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *ValueStr;\r
- UART_FLOW_CONTROL_DEVICE_PATH *UartFlowControl;\r
+ CHAR16 *ValueStr;\r
+ UART_FLOW_CONTROL_DEVICE_PATH *UartFlowControl;\r
\r
ValueStr = GetNextParamStr (&TextDeviceNode);\r
- UartFlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (UART_FLOW_CONTROL_DEVICE_PATH)\r
- );\r
+ UartFlowControl = (UART_FLOW_CONTROL_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (UART_FLOW_CONTROL_DEVICE_PATH)\r
+ );\r
\r
CopyGuid (&UartFlowControl->Guid, &gEfiUartDevicePathGuid);\r
if (StrCmp (ValueStr, L"XonXoff") == 0) {\r
UartFlowControl->FlowControlMap = 0;\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) UartFlowControl;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)UartFlowControl;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextSAS (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *AddressStr;\r
- CHAR16 *LunStr;\r
- CHAR16 *RTPStr;\r
- CHAR16 *SASSATAStr;\r
- CHAR16 *LocationStr;\r
- CHAR16 *ConnectStr;\r
- CHAR16 *DriveBayStr;\r
- CHAR16 *ReservedStr;\r
- UINT16 Info;\r
- UINT16 Uint16;\r
- SAS_DEVICE_PATH *Sas;\r
+ CHAR16 *AddressStr;\r
+ CHAR16 *LunStr;\r
+ CHAR16 *RTPStr;\r
+ CHAR16 *SASSATAStr;\r
+ CHAR16 *LocationStr;\r
+ CHAR16 *ConnectStr;\r
+ CHAR16 *DriveBayStr;\r
+ CHAR16 *ReservedStr;\r
+ UINT16 Info;\r
+ UINT16 Uint16;\r
+ SAS_DEVICE_PATH *Sas;\r
\r
AddressStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
ConnectStr = GetNextParamStr (&TextDeviceNode);\r
DriveBayStr = GetNextParamStr (&TextDeviceNode);\r
ReservedStr = GetNextParamStr (&TextDeviceNode);\r
- Sas = (SAS_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (SAS_DEVICE_PATH)\r
- );\r
+ Sas = (SAS_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (SAS_DEVICE_PATH)\r
+ );\r
\r
CopyGuid (&Sas->Guid, &gEfiSasDevicePathGuid);\r
Strtoi64 (AddressStr, &Sas->SasAddress);\r
Strtoi64 (LunStr, &Sas->Lun);\r
- Sas->RelativeTargetPort = (UINT16) Strtoi (RTPStr);\r
+ Sas->RelativeTargetPort = (UINT16)Strtoi (RTPStr);\r
\r
if (StrCmp (SASSATAStr, L"NoTopology") == 0) {\r
Info = 0x0;\r
-\r
} else if ((StrCmp (SASSATAStr, L"SATA") == 0) || (StrCmp (SASSATAStr, L"SAS") == 0)) {\r
-\r
- Uint16 = (UINT16) Strtoi (DriveBayStr);\r
+ Uint16 = (UINT16)Strtoi (DriveBayStr);\r
if (Uint16 == 0) {\r
Info = 0x1;\r
} else {\r
- Info = (UINT16) (0x2 | ((Uint16 - 1) << 8));\r
+ Info = (UINT16)(0x2 | ((Uint16 - 1) << 8));\r
}\r
\r
if (StrCmp (SASSATAStr, L"SATA") == 0) {\r
} else if (StrCmp (LocationStr, L"Internal") == 0) {\r
Uint16 = 0;\r
} else {\r
- Uint16 = ((UINT16) Strtoi (LocationStr) & BIT0);\r
+ Uint16 = ((UINT16)Strtoi (LocationStr) & BIT0);\r
}\r
+\r
Info |= (Uint16 << 5);\r
\r
//\r
} else if (StrCmp (ConnectStr, L"Direct") == 0) {\r
Uint16 = 0;\r
} else {\r
- Uint16 = ((UINT16) Strtoi (ConnectStr) & (BIT0 | BIT1));\r
+ Uint16 = ((UINT16)Strtoi (ConnectStr) & (BIT0 | BIT1));\r
}\r
- Info |= (Uint16 << 6);\r
\r
+ Info |= (Uint16 << 6);\r
} else {\r
- Info = (UINT16) Strtoi (SASSATAStr);\r
+ Info = (UINT16)Strtoi (SASSATAStr);\r
}\r
\r
Sas->DeviceTopology = Info;\r
- Sas->Reserved = (UINT32) Strtoi (ReservedStr);\r
+ Sas->Reserved = (UINT32)Strtoi (ReservedStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Sas;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Sas;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextSasEx (\r
- IN CHAR16 *TextDeviceNode\r
- )\r
-{\r
- CHAR16 *AddressStr;\r
- CHAR16 *LunStr;\r
- CHAR16 *RTPStr;\r
- CHAR16 *SASSATAStr;\r
- CHAR16 *LocationStr;\r
- CHAR16 *ConnectStr;\r
- CHAR16 *DriveBayStr;\r
- UINT16 Info;\r
- UINT16 Uint16;\r
- UINT64 SasAddress;\r
- UINT64 Lun;\r
- SASEX_DEVICE_PATH *SasEx;\r
+ IN CHAR16 *TextDeviceNode\r
+ )\r
+{\r
+ CHAR16 *AddressStr;\r
+ CHAR16 *LunStr;\r
+ CHAR16 *RTPStr;\r
+ CHAR16 *SASSATAStr;\r
+ CHAR16 *LocationStr;\r
+ CHAR16 *ConnectStr;\r
+ CHAR16 *DriveBayStr;\r
+ UINT16 Info;\r
+ UINT16 Uint16;\r
+ UINT64 SasAddress;\r
+ UINT64 Lun;\r
+ SASEX_DEVICE_PATH *SasEx;\r
\r
AddressStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
LocationStr = GetNextParamStr (&TextDeviceNode);\r
ConnectStr = GetNextParamStr (&TextDeviceNode);\r
DriveBayStr = GetNextParamStr (&TextDeviceNode);\r
- SasEx = (SASEX_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_SASEX_DP,\r
- (UINT16) sizeof (SASEX_DEVICE_PATH)\r
- );\r
+ SasEx = (SASEX_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_SASEX_DP,\r
+ (UINT16)sizeof (SASEX_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (AddressStr, &SasAddress);\r
- Strtoi64 (LunStr, &Lun);\r
- WriteUnaligned64 ((UINT64 *) &SasEx->SasAddress, SwapBytes64 (SasAddress));\r
- WriteUnaligned64 ((UINT64 *) &SasEx->Lun, SwapBytes64 (Lun));\r
- SasEx->RelativeTargetPort = (UINT16) Strtoi (RTPStr);\r
+ Strtoi64 (LunStr, &Lun);\r
+ WriteUnaligned64 ((UINT64 *)&SasEx->SasAddress, SwapBytes64 (SasAddress));\r
+ WriteUnaligned64 ((UINT64 *)&SasEx->Lun, SwapBytes64 (Lun));\r
+ SasEx->RelativeTargetPort = (UINT16)Strtoi (RTPStr);\r
\r
if (StrCmp (SASSATAStr, L"NoTopology") == 0) {\r
Info = 0x0;\r
-\r
} else if ((StrCmp (SASSATAStr, L"SATA") == 0) || (StrCmp (SASSATAStr, L"SAS") == 0)) {\r
-\r
- Uint16 = (UINT16) Strtoi (DriveBayStr);\r
+ Uint16 = (UINT16)Strtoi (DriveBayStr);\r
if (Uint16 == 0) {\r
Info = 0x1;\r
} else {\r
- Info = (UINT16) (0x2 | ((Uint16 - 1) << 8));\r
+ Info = (UINT16)(0x2 | ((Uint16 - 1) << 8));\r
}\r
\r
if (StrCmp (SASSATAStr, L"SATA") == 0) {\r
} else if (StrCmp (LocationStr, L"Internal") == 0) {\r
Uint16 = 0;\r
} else {\r
- Uint16 = ((UINT16) Strtoi (LocationStr) & BIT0);\r
+ Uint16 = ((UINT16)Strtoi (LocationStr) & BIT0);\r
}\r
+\r
Info |= (Uint16 << 5);\r
\r
//\r
} else if (StrCmp (ConnectStr, L"Direct") == 0) {\r
Uint16 = 0;\r
} else {\r
- Uint16 = ((UINT16) Strtoi (ConnectStr) & (BIT0 | BIT1));\r
+ Uint16 = ((UINT16)Strtoi (ConnectStr) & (BIT0 | BIT1));\r
}\r
- Info |= (Uint16 << 6);\r
\r
+ Info |= (Uint16 << 6);\r
} else {\r
- Info = (UINT16) Strtoi (SASSATAStr);\r
+ Info = (UINT16)Strtoi (SASSATAStr);\r
}\r
\r
SasEx->DeviceTopology = Info;\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) SasEx;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)SasEx;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextNVMe (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *NamespaceIdStr;\r
- CHAR16 *NamespaceUuidStr;\r
- NVME_NAMESPACE_DEVICE_PATH *Nvme;\r
- UINT8 *Uuid;\r
- UINTN Index;\r
+ CHAR16 *NamespaceIdStr;\r
+ CHAR16 *NamespaceUuidStr;\r
+ NVME_NAMESPACE_DEVICE_PATH *Nvme;\r
+ UINT8 *Uuid;\r
+ UINTN Index;\r
\r
NamespaceIdStr = GetNextParamStr (&TextDeviceNode);\r
NamespaceUuidStr = GetNextParamStr (&TextDeviceNode);\r
- Nvme = (NVME_NAMESPACE_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_NVME_NAMESPACE_DP,\r
- (UINT16) sizeof (NVME_NAMESPACE_DEVICE_PATH)\r
- );\r
+ Nvme = (NVME_NAMESPACE_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_NVME_NAMESPACE_DP,\r
+ (UINT16)sizeof (NVME_NAMESPACE_DEVICE_PATH)\r
+ );\r
\r
- Nvme->NamespaceId = (UINT32) Strtoi (NamespaceIdStr);\r
- Uuid = (UINT8 *) &Nvme->NamespaceUuid;\r
+ Nvme->NamespaceId = (UINT32)Strtoi (NamespaceIdStr);\r
+ Uuid = (UINT8 *)&Nvme->NamespaceUuid;\r
\r
Index = sizeof (Nvme->NamespaceUuid) / sizeof (UINT8);\r
while (Index-- != 0) {\r
- Uuid[Index] = (UINT8) StrHexToUintn (SplitStr (&NamespaceUuidStr, L'-'));\r
+ Uuid[Index] = (UINT8)StrHexToUintn (SplitStr (&NamespaceUuidStr, L'-'));\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Nvme;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Nvme;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUfs (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *PunStr;\r
- CHAR16 *LunStr;\r
- UFS_DEVICE_PATH *Ufs;\r
+ CHAR16 *PunStr;\r
+ CHAR16 *LunStr;\r
+ UFS_DEVICE_PATH *Ufs;\r
\r
PunStr = GetNextParamStr (&TextDeviceNode);\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
- Ufs = (UFS_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_UFS_DP,\r
- (UINT16) sizeof (UFS_DEVICE_PATH)\r
- );\r
+ Ufs = (UFS_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_UFS_DP,\r
+ (UINT16)sizeof (UFS_DEVICE_PATH)\r
+ );\r
\r
- Ufs->Pun = (UINT8) Strtoi (PunStr);\r
- Ufs->Lun = (UINT8) Strtoi (LunStr);\r
+ Ufs->Pun = (UINT8)Strtoi (PunStr);\r
+ Ufs->Lun = (UINT8)Strtoi (LunStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Ufs;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Ufs;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextSd (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *SlotNumberStr;\r
- SD_DEVICE_PATH *Sd;\r
+ CHAR16 *SlotNumberStr;\r
+ SD_DEVICE_PATH *Sd;\r
\r
SlotNumberStr = GetNextParamStr (&TextDeviceNode);\r
- Sd = (SD_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_SD_DP,\r
- (UINT16) sizeof (SD_DEVICE_PATH)\r
- );\r
+ Sd = (SD_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_SD_DP,\r
+ (UINT16)sizeof (SD_DEVICE_PATH)\r
+ );\r
\r
- Sd->SlotNumber = (UINT8) Strtoi (SlotNumberStr);\r
+ Sd->SlotNumber = (UINT8)Strtoi (SlotNumberStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Sd;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Sd;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextEmmc (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *SlotNumberStr;\r
EMMC_DEVICE_PATH *Emmc;\r
\r
SlotNumberStr = GetNextParamStr (&TextDeviceNode);\r
- Emmc = (EMMC_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_EMMC_DP,\r
- (UINT16) sizeof (EMMC_DEVICE_PATH)\r
- );\r
+ Emmc = (EMMC_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_EMMC_DP,\r
+ (UINT16)sizeof (EMMC_DEVICE_PATH)\r
+ );\r
\r
- Emmc->SlotNumber = (UINT8) Strtoi (SlotNumberStr);\r
+ Emmc->SlotNumber = (UINT8)Strtoi (SlotNumberStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Emmc;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Emmc;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextDebugPort (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
VENDOR_DEVICE_PATH *Vend;\r
\r
- Vend = (VENDOR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VENDOR_DP,\r
- (UINT16) sizeof (VENDOR_DEVICE_PATH)\r
- );\r
+ Vend = (VENDOR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ (UINT16)sizeof (VENDOR_DEVICE_PATH)\r
+ );\r
\r
CopyGuid (&Vend->Guid, &gEfiDebugPortProtocolGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vend;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vend;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextMAC (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *AddressStr;\r
UINTN Length;\r
MAC_ADDR_DEVICE_PATH *MACDevPath;\r
\r
- AddressStr = GetNextParamStr (&TextDeviceNode);\r
- IfTypeStr = GetNextParamStr (&TextDeviceNode);\r
- MACDevPath = (MAC_ADDR_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_MAC_ADDR_DP,\r
- (UINT16) sizeof (MAC_ADDR_DEVICE_PATH)\r
- );\r
+ AddressStr = GetNextParamStr (&TextDeviceNode);\r
+ IfTypeStr = GetNextParamStr (&TextDeviceNode);\r
+ MACDevPath = (MAC_ADDR_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_MAC_ADDR_DP,\r
+ (UINT16)sizeof (MAC_ADDR_DEVICE_PATH)\r
+ );\r
\r
- MACDevPath->IfType = (UINT8) Strtoi (IfTypeStr);\r
+ MACDevPath->IfType = (UINT8)Strtoi (IfTypeStr);\r
\r
Length = sizeof (EFI_MAC_ADDRESS);\r
- if (MACDevPath->IfType == 0x01 || MACDevPath->IfType == 0x00) {\r
+ if ((MACDevPath->IfType == 0x01) || (MACDevPath->IfType == 0x00)) {\r
Length = 6;\r
}\r
\r
StrHexToBytes (AddressStr, Length * 2, MACDevPath->MacAddress.Addr, Length);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) MACDevPath;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)MACDevPath;\r
}\r
\r
-\r
/**\r
Converts a text format to the network protocol ID.\r
\r
**/\r
UINTN\r
NetworkProtocolFromText (\r
- IN CHAR16 *Text\r
+ IN CHAR16 *Text\r
)\r
{\r
if (StrCmp (Text, L"UDP") == 0) {\r
return Strtoi (Text);\r
}\r
\r
-\r
/**\r
Converts a text device path node to IPV4 device path structure.\r
\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextIPv4 (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *RemoteIPStr;\r
CHAR16 *SubnetMaskStr;\r
IPv4_DEVICE_PATH *IPv4;\r
\r
- RemoteIPStr = GetNextParamStr (&TextDeviceNode);\r
- ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
- TypeStr = GetNextParamStr (&TextDeviceNode);\r
- LocalIPStr = GetNextParamStr (&TextDeviceNode);\r
- GatewayIPStr = GetNextParamStr (&TextDeviceNode);\r
- SubnetMaskStr = GetNextParamStr (&TextDeviceNode);\r
- IPv4 = (IPv4_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_IPv4_DP,\r
- (UINT16) sizeof (IPv4_DEVICE_PATH)\r
- );\r
+ RemoteIPStr = GetNextParamStr (&TextDeviceNode);\r
+ ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
+ TypeStr = GetNextParamStr (&TextDeviceNode);\r
+ LocalIPStr = GetNextParamStr (&TextDeviceNode);\r
+ GatewayIPStr = GetNextParamStr (&TextDeviceNode);\r
+ SubnetMaskStr = GetNextParamStr (&TextDeviceNode);\r
+ IPv4 = (IPv4_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_IPv4_DP,\r
+ (UINT16)sizeof (IPv4_DEVICE_PATH)\r
+ );\r
\r
StrToIpv4Address (RemoteIPStr, NULL, &IPv4->RemoteIpAddress, NULL);\r
- IPv4->Protocol = (UINT16) NetworkProtocolFromText (ProtocolStr);\r
+ IPv4->Protocol = (UINT16)NetworkProtocolFromText (ProtocolStr);\r
if (StrCmp (TypeStr, L"Static") == 0) {\r
IPv4->StaticIpAddress = TRUE;\r
} else {\r
\r
StrToIpv4Address (LocalIPStr, NULL, &IPv4->LocalIpAddress, NULL);\r
if (!IS_NULL (*GatewayIPStr) && !IS_NULL (*SubnetMaskStr)) {\r
- StrToIpv4Address (GatewayIPStr, NULL, &IPv4->GatewayIpAddress, NULL);\r
- StrToIpv4Address (SubnetMaskStr, NULL, &IPv4->SubnetMask, NULL);\r
+ StrToIpv4Address (GatewayIPStr, NULL, &IPv4->GatewayIpAddress, NULL);\r
+ StrToIpv4Address (SubnetMaskStr, NULL, &IPv4->SubnetMask, NULL);\r
} else {\r
ZeroMem (&IPv4->GatewayIpAddress, sizeof (IPv4->GatewayIpAddress));\r
- ZeroMem (&IPv4->SubnetMask, sizeof (IPv4->SubnetMask));\r
+ ZeroMem (&IPv4->SubnetMask, sizeof (IPv4->SubnetMask));\r
}\r
\r
- IPv4->LocalPort = 0;\r
- IPv4->RemotePort = 0;\r
+ IPv4->LocalPort = 0;\r
+ IPv4->RemotePort = 0;\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) IPv4;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)IPv4;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextIPv6 (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *RemoteIPStr;\r
CHAR16 *PrefixLengthStr;\r
IPv6_DEVICE_PATH *IPv6;\r
\r
- RemoteIPStr = GetNextParamStr (&TextDeviceNode);\r
- ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
- TypeStr = GetNextParamStr (&TextDeviceNode);\r
- LocalIPStr = GetNextParamStr (&TextDeviceNode);\r
- PrefixLengthStr = GetNextParamStr (&TextDeviceNode);\r
- GatewayIPStr = GetNextParamStr (&TextDeviceNode);\r
- IPv6 = (IPv6_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_IPv6_DP,\r
- (UINT16) sizeof (IPv6_DEVICE_PATH)\r
- );\r
+ RemoteIPStr = GetNextParamStr (&TextDeviceNode);\r
+ ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
+ TypeStr = GetNextParamStr (&TextDeviceNode);\r
+ LocalIPStr = GetNextParamStr (&TextDeviceNode);\r
+ PrefixLengthStr = GetNextParamStr (&TextDeviceNode);\r
+ GatewayIPStr = GetNextParamStr (&TextDeviceNode);\r
+ IPv6 = (IPv6_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_IPv6_DP,\r
+ (UINT16)sizeof (IPv6_DEVICE_PATH)\r
+ );\r
\r
StrToIpv6Address (RemoteIPStr, NULL, &IPv6->RemoteIpAddress, NULL);\r
- IPv6->Protocol = (UINT16) NetworkProtocolFromText (ProtocolStr);\r
+ IPv6->Protocol = (UINT16)NetworkProtocolFromText (ProtocolStr);\r
if (StrCmp (TypeStr, L"Static") == 0) {\r
IPv6->IpAddressOrigin = 0;\r
} else if (StrCmp (TypeStr, L"StatelessAutoConfigure") == 0) {\r
StrToIpv6Address (LocalIPStr, NULL, &IPv6->LocalIpAddress, NULL);\r
if (!IS_NULL (*GatewayIPStr) && !IS_NULL (*PrefixLengthStr)) {\r
StrToIpv6Address (GatewayIPStr, NULL, &IPv6->GatewayIpAddress, NULL);\r
- IPv6->PrefixLength = (UINT8) Strtoi (PrefixLengthStr);\r
+ IPv6->PrefixLength = (UINT8)Strtoi (PrefixLengthStr);\r
} else {\r
ZeroMem (&IPv6->GatewayIpAddress, sizeof (IPv6->GatewayIpAddress));\r
IPv6->PrefixLength = 0;\r
}\r
\r
- IPv6->LocalPort = 0;\r
- IPv6->RemotePort = 0;\r
+ IPv6->LocalPort = 0;\r
+ IPv6->RemotePort = 0;\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) IPv6;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)IPv6;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUart (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *BaudStr;\r
CHAR16 *StopBitsStr;\r
UART_DEVICE_PATH *Uart;\r
\r
- BaudStr = GetNextParamStr (&TextDeviceNode);\r
- DataBitsStr = GetNextParamStr (&TextDeviceNode);\r
- ParityStr = GetNextParamStr (&TextDeviceNode);\r
- StopBitsStr = GetNextParamStr (&TextDeviceNode);\r
- Uart = (UART_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_UART_DP,\r
- (UINT16) sizeof (UART_DEVICE_PATH)\r
- );\r
+ BaudStr = GetNextParamStr (&TextDeviceNode);\r
+ DataBitsStr = GetNextParamStr (&TextDeviceNode);\r
+ ParityStr = GetNextParamStr (&TextDeviceNode);\r
+ StopBitsStr = GetNextParamStr (&TextDeviceNode);\r
+ Uart = (UART_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_UART_DP,\r
+ (UINT16)sizeof (UART_DEVICE_PATH)\r
+ );\r
\r
if (StrCmp (BaudStr, L"DEFAULT") == 0) {\r
Uart->BaudRate = 115200;\r
} else {\r
Strtoi64 (BaudStr, &Uart->BaudRate);\r
}\r
- Uart->DataBits = (UINT8) ((StrCmp (DataBitsStr, L"DEFAULT") == 0) ? 8 : Strtoi (DataBitsStr));\r
+\r
+ Uart->DataBits = (UINT8)((StrCmp (DataBitsStr, L"DEFAULT") == 0) ? 8 : Strtoi (DataBitsStr));\r
switch (*ParityStr) {\r
- case L'D':\r
- Uart->Parity = 0;\r
- break;\r
+ case L'D':\r
+ Uart->Parity = 0;\r
+ break;\r
\r
- case L'N':\r
- Uart->Parity = 1;\r
- break;\r
+ case L'N':\r
+ Uart->Parity = 1;\r
+ break;\r
\r
- case L'E':\r
- Uart->Parity = 2;\r
- break;\r
+ case L'E':\r
+ Uart->Parity = 2;\r
+ break;\r
\r
- case L'O':\r
- Uart->Parity = 3;\r
- break;\r
+ case L'O':\r
+ Uart->Parity = 3;\r
+ break;\r
\r
- case L'M':\r
- Uart->Parity = 4;\r
- break;\r
+ case L'M':\r
+ Uart->Parity = 4;\r
+ break;\r
\r
- case L'S':\r
- Uart->Parity = 5;\r
- break;\r
+ case L'S':\r
+ Uart->Parity = 5;\r
+ break;\r
\r
- default:\r
- Uart->Parity = (UINT8) Strtoi (ParityStr);\r
- break;\r
+ default:\r
+ Uart->Parity = (UINT8)Strtoi (ParityStr);\r
+ break;\r
}\r
\r
if (StrCmp (StopBitsStr, L"D") == 0) {\r
- Uart->StopBits = (UINT8) 0;\r
+ Uart->StopBits = (UINT8)0;\r
} else if (StrCmp (StopBitsStr, L"1") == 0) {\r
- Uart->StopBits = (UINT8) 1;\r
+ Uart->StopBits = (UINT8)1;\r
} else if (StrCmp (StopBitsStr, L"1.5") == 0) {\r
- Uart->StopBits = (UINT8) 2;\r
+ Uart->StopBits = (UINT8)2;\r
} else if (StrCmp (StopBitsStr, L"2") == 0) {\r
- Uart->StopBits = (UINT8) 3;\r
+ Uart->StopBits = (UINT8)3;\r
} else {\r
- Uart->StopBits = (UINT8) Strtoi (StopBitsStr);\r
+ Uart->StopBits = (UINT8)Strtoi (StopBitsStr);\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Uart;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Uart;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
ConvertFromTextUsbClass (\r
- IN CHAR16 *TextDeviceNode,\r
- IN USB_CLASS_TEXT *UsbClassText\r
+ IN CHAR16 *TextDeviceNode,\r
+ IN USB_CLASS_TEXT *UsbClassText\r
)\r
{\r
- CHAR16 *VIDStr;\r
- CHAR16 *PIDStr;\r
- CHAR16 *ClassStr;\r
- CHAR16 *SubClassStr;\r
- CHAR16 *ProtocolStr;\r
- USB_CLASS_DEVICE_PATH *UsbClass;\r
+ CHAR16 *VIDStr;\r
+ CHAR16 *PIDStr;\r
+ CHAR16 *ClassStr;\r
+ CHAR16 *SubClassStr;\r
+ CHAR16 *ProtocolStr;\r
+ USB_CLASS_DEVICE_PATH *UsbClass;\r
\r
- UsbClass = (USB_CLASS_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_USB_CLASS_DP,\r
- (UINT16) sizeof (USB_CLASS_DEVICE_PATH)\r
- );\r
+ UsbClass = (USB_CLASS_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_USB_CLASS_DP,\r
+ (UINT16)sizeof (USB_CLASS_DEVICE_PATH)\r
+ );\r
\r
- VIDStr = GetNextParamStr (&TextDeviceNode);\r
- PIDStr = GetNextParamStr (&TextDeviceNode);\r
+ VIDStr = GetNextParamStr (&TextDeviceNode);\r
+ PIDStr = GetNextParamStr (&TextDeviceNode);\r
if (UsbClassText->ClassExist) {\r
ClassStr = GetNextParamStr (&TextDeviceNode);\r
if (*ClassStr == L'\0') {\r
UsbClass->DeviceClass = 0xFF;\r
} else {\r
- UsbClass->DeviceClass = (UINT8) Strtoi (ClassStr);\r
+ UsbClass->DeviceClass = (UINT8)Strtoi (ClassStr);\r
}\r
} else {\r
UsbClass->DeviceClass = UsbClassText->Class;\r
}\r
+\r
if (UsbClassText->SubClassExist) {\r
SubClassStr = GetNextParamStr (&TextDeviceNode);\r
if (*SubClassStr == L'\0') {\r
UsbClass->DeviceSubClass = 0xFF;\r
} else {\r
- UsbClass->DeviceSubClass = (UINT8) Strtoi (SubClassStr);\r
+ UsbClass->DeviceSubClass = (UINT8)Strtoi (SubClassStr);\r
}\r
} else {\r
UsbClass->DeviceSubClass = UsbClassText->SubClass;\r
ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
\r
if (*VIDStr == L'\0') {\r
- UsbClass->VendorId = 0xFFFF;\r
+ UsbClass->VendorId = 0xFFFF;\r
} else {\r
- UsbClass->VendorId = (UINT16) Strtoi (VIDStr);\r
+ UsbClass->VendorId = (UINT16)Strtoi (VIDStr);\r
}\r
+\r
if (*PIDStr == L'\0') {\r
- UsbClass->ProductId = 0xFFFF;\r
+ UsbClass->ProductId = 0xFFFF;\r
} else {\r
- UsbClass->ProductId = (UINT16) Strtoi (PIDStr);\r
+ UsbClass->ProductId = (UINT16)Strtoi (PIDStr);\r
}\r
+\r
if (*ProtocolStr == L'\0') {\r
- UsbClass->DeviceProtocol = 0xFF;\r
+ UsbClass->DeviceProtocol = 0xFF;\r
} else {\r
- UsbClass->DeviceProtocol = (UINT8) Strtoi (ProtocolStr);\r
+ UsbClass->DeviceProtocol = (UINT8)Strtoi (ProtocolStr);\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) UsbClass;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)UsbClass;\r
}\r
\r
-\r
/**\r
Converts a text device path node to USB class device path structure.\r
\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbClass (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbAudio (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbCDCControl (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbHID (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbImage (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbPrinter (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbMassStorage (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbHub (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbCDCData (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbSmartCard (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbVideo (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbDiagnostic (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbWireless (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbDeviceFirmwareUpdate (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbIrdaBridge (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbTestAndMeasurement (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
USB_CLASS_TEXT UsbClassText;\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUsbWwid (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *VIDStr;\r
USB_WWID_DEVICE_PATH *UsbWwid;\r
UINTN SerialNumberStrLen;\r
\r
- VIDStr = GetNextParamStr (&TextDeviceNode);\r
- PIDStr = GetNextParamStr (&TextDeviceNode);\r
- InterfaceNumStr = GetNextParamStr (&TextDeviceNode);\r
- SerialNumberStr = GetNextParamStr (&TextDeviceNode);\r
- SerialNumberStrLen = StrLen (SerialNumberStr);\r
- if (SerialNumberStrLen >= 2 &&\r
- SerialNumberStr[0] == L'\"' &&\r
- SerialNumberStr[SerialNumberStrLen - 1] == L'\"'\r
- ) {\r
+ VIDStr = GetNextParamStr (&TextDeviceNode);\r
+ PIDStr = GetNextParamStr (&TextDeviceNode);\r
+ InterfaceNumStr = GetNextParamStr (&TextDeviceNode);\r
+ SerialNumberStr = GetNextParamStr (&TextDeviceNode);\r
+ SerialNumberStrLen = StrLen (SerialNumberStr);\r
+ if ((SerialNumberStrLen >= 2) &&\r
+ (SerialNumberStr[0] == L'\"') &&\r
+ (SerialNumberStr[SerialNumberStrLen - 1] == L'\"')\r
+ )\r
+ {\r
SerialNumberStr[SerialNumberStrLen - 1] = L'\0';\r
SerialNumberStr++;\r
SerialNumberStrLen -= 2;\r
}\r
- UsbWwid = (USB_WWID_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_USB_WWID_DP,\r
- (UINT16) (sizeof (USB_WWID_DEVICE_PATH) + SerialNumberStrLen * sizeof (CHAR16))\r
- );\r
- UsbWwid->VendorId = (UINT16) Strtoi (VIDStr);\r
- UsbWwid->ProductId = (UINT16) Strtoi (PIDStr);\r
- UsbWwid->InterfaceNumber = (UINT16) Strtoi (InterfaceNumStr);\r
+\r
+ UsbWwid = (USB_WWID_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_USB_WWID_DP,\r
+ (UINT16)(sizeof (USB_WWID_DEVICE_PATH) + SerialNumberStrLen * sizeof (CHAR16))\r
+ );\r
+ UsbWwid->VendorId = (UINT16)Strtoi (VIDStr);\r
+ UsbWwid->ProductId = (UINT16)Strtoi (PIDStr);\r
+ UsbWwid->InterfaceNumber = (UINT16)Strtoi (InterfaceNumStr);\r
\r
//\r
// There is no memory allocated in UsbWwid for the '\0' in SerialNumberStr.\r
// Therefore, the '\0' will not be copied.\r
//\r
CopyMem (\r
- (UINT8 *) UsbWwid + sizeof (USB_WWID_DEVICE_PATH),\r
+ (UINT8 *)UsbWwid + sizeof (USB_WWID_DEVICE_PATH),\r
SerialNumberStr,\r
SerialNumberStrLen * sizeof (CHAR16)\r
);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) UsbWwid;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)UsbWwid;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUnit (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *LunStr;\r
- DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicalUnit;\r
+ CHAR16 *LunStr;\r
+ DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicalUnit;\r
\r
LunStr = GetNextParamStr (&TextDeviceNode);\r
- LogicalUnit = (DEVICE_LOGICAL_UNIT_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_DEVICE_LOGICAL_UNIT_DP,\r
- (UINT16) sizeof (DEVICE_LOGICAL_UNIT_DEVICE_PATH)\r
- );\r
+ LogicalUnit = (DEVICE_LOGICAL_UNIT_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_DEVICE_LOGICAL_UNIT_DP,\r
+ (UINT16)sizeof (DEVICE_LOGICAL_UNIT_DEVICE_PATH)\r
+ );\r
\r
- LogicalUnit->Lun = (UINT8) Strtoi (LunStr);\r
+ LogicalUnit->Lun = (UINT8)Strtoi (LunStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) LogicalUnit;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)LogicalUnit;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextiSCSI (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- UINT16 Options;\r
- CHAR16 *NameStr;\r
- CHAR16 *PortalGroupStr;\r
- CHAR16 *LunStr;\r
- CHAR16 *HeaderDigestStr;\r
- CHAR16 *DataDigestStr;\r
- CHAR16 *AuthenticationStr;\r
- CHAR16 *ProtocolStr;\r
- CHAR8 *AsciiStr;\r
- ISCSI_DEVICE_PATH_WITH_NAME *ISCSIDevPath;\r
- UINT64 Lun;\r
+ UINT16 Options;\r
+ CHAR16 *NameStr;\r
+ CHAR16 *PortalGroupStr;\r
+ CHAR16 *LunStr;\r
+ CHAR16 *HeaderDigestStr;\r
+ CHAR16 *DataDigestStr;\r
+ CHAR16 *AuthenticationStr;\r
+ CHAR16 *ProtocolStr;\r
+ CHAR8 *AsciiStr;\r
+ ISCSI_DEVICE_PATH_WITH_NAME *ISCSIDevPath;\r
+ UINT64 Lun;\r
\r
NameStr = GetNextParamStr (&TextDeviceNode);\r
PortalGroupStr = GetNextParamStr (&TextDeviceNode);\r
DataDigestStr = GetNextParamStr (&TextDeviceNode);\r
AuthenticationStr = GetNextParamStr (&TextDeviceNode);\r
ProtocolStr = GetNextParamStr (&TextDeviceNode);\r
- ISCSIDevPath = (ISCSI_DEVICE_PATH_WITH_NAME *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_ISCSI_DP,\r
- (UINT16) (sizeof (ISCSI_DEVICE_PATH_WITH_NAME) + StrLen (NameStr))\r
- );\r
+ ISCSIDevPath = (ISCSI_DEVICE_PATH_WITH_NAME *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_ISCSI_DP,\r
+ (UINT16)(sizeof (ISCSI_DEVICE_PATH_WITH_NAME) + StrLen (NameStr))\r
+ );\r
\r
AsciiStr = ISCSIDevPath->TargetName;\r
StrToAscii (NameStr, &AsciiStr);\r
\r
- ISCSIDevPath->TargetPortalGroupTag = (UINT16) Strtoi (PortalGroupStr);\r
+ ISCSIDevPath->TargetPortalGroupTag = (UINT16)Strtoi (PortalGroupStr);\r
Strtoi64 (LunStr, &Lun);\r
- WriteUnaligned64 ((UINT64 *) &ISCSIDevPath->Lun, SwapBytes64 (Lun));\r
+ WriteUnaligned64 ((UINT64 *)&ISCSIDevPath->Lun, SwapBytes64 (Lun));\r
\r
Options = 0x0000;\r
if (StrCmp (HeaderDigestStr, L"CRC32C") == 0) {\r
Options |= 0x1000;\r
}\r
\r
- ISCSIDevPath->LoginOption = (UINT16) Options;\r
+ ISCSIDevPath->LoginOption = (UINT16)Options;\r
\r
if (IS_NULL (*ProtocolStr) || (StrCmp (ProtocolStr, L"TCP") == 0)) {\r
ISCSIDevPath->NetworkProtocol = 0;\r
ISCSIDevPath->NetworkProtocol = 1;\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) ISCSIDevPath;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)ISCSIDevPath;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVlan (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *VlanStr;\r
VLAN_DEVICE_PATH *Vlan;\r
\r
VlanStr = GetNextParamStr (&TextDeviceNode);\r
- Vlan = (VLAN_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_VLAN_DP,\r
- (UINT16) sizeof (VLAN_DEVICE_PATH)\r
- );\r
+ Vlan = (VLAN_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VLAN_DP,\r
+ (UINT16)sizeof (VLAN_DEVICE_PATH)\r
+ );\r
\r
- Vlan->VlanId = (UINT16) Strtoi (VlanStr);\r
+ Vlan->VlanId = (UINT16)Strtoi (VlanStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Vlan;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Vlan;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextBluetooth (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *BluetoothStr;\r
- BLUETOOTH_DEVICE_PATH *BluetoothDp;\r
+ CHAR16 *BluetoothStr;\r
+ BLUETOOTH_DEVICE_PATH *BluetoothDp;\r
\r
BluetoothStr = GetNextParamStr (&TextDeviceNode);\r
- BluetoothDp = (BLUETOOTH_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_BLUETOOTH_DP,\r
- (UINT16) sizeof (BLUETOOTH_DEVICE_PATH)\r
- );\r
+ BluetoothDp = (BLUETOOTH_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_BLUETOOTH_DP,\r
+ (UINT16)sizeof (BLUETOOTH_DEVICE_PATH)\r
+ );\r
StrHexToBytes (\r
BluetoothStr,\r
sizeof (BLUETOOTH_ADDRESS) * 2,\r
BluetoothDp->BD_ADDR.Address,\r
sizeof (BLUETOOTH_ADDRESS)\r
);\r
- return (EFI_DEVICE_PATH_PROTOCOL *) BluetoothDp;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)BluetoothDp;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextWiFi (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *SSIdStr;\r
- CHAR8 AsciiStr[33];\r
- UINTN DataLen;\r
- WIFI_DEVICE_PATH *WiFiDp;\r
+ CHAR16 *SSIdStr;\r
+ CHAR8 AsciiStr[33];\r
+ UINTN DataLen;\r
+ WIFI_DEVICE_PATH *WiFiDp;\r
\r
SSIdStr = GetNextParamStr (&TextDeviceNode);\r
- WiFiDp = (WIFI_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_WIFI_DP,\r
- (UINT16) sizeof (WIFI_DEVICE_PATH)\r
- );\r
+ WiFiDp = (WIFI_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_WIFI_DP,\r
+ (UINT16)sizeof (WIFI_DEVICE_PATH)\r
+ );\r
\r
if (NULL != SSIdStr) {\r
DataLen = StrLen (SSIdStr);\r
CopyMem (WiFiDp->SSId, AsciiStr, DataLen);\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) WiFiDp;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)WiFiDp;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextBluetoothLE (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *BluetoothLeAddrStr;\r
- CHAR16 *BluetoothLeAddrTypeStr;\r
- BLUETOOTH_LE_DEVICE_PATH *BluetoothLeDp;\r
+ CHAR16 *BluetoothLeAddrStr;\r
+ CHAR16 *BluetoothLeAddrTypeStr;\r
+ BLUETOOTH_LE_DEVICE_PATH *BluetoothLeDp;\r
\r
BluetoothLeAddrStr = GetNextParamStr (&TextDeviceNode);\r
BluetoothLeAddrTypeStr = GetNextParamStr (&TextDeviceNode);\r
- BluetoothLeDp = (BLUETOOTH_LE_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_BLUETOOTH_LE_DP,\r
- (UINT16) sizeof (BLUETOOTH_LE_DEVICE_PATH)\r
- );\r
+ BluetoothLeDp = (BLUETOOTH_LE_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_BLUETOOTH_LE_DP,\r
+ (UINT16)sizeof (BLUETOOTH_LE_DEVICE_PATH)\r
+ );\r
\r
- BluetoothLeDp->Address.Type = (UINT8) Strtoi (BluetoothLeAddrTypeStr);\r
+ BluetoothLeDp->Address.Type = (UINT8)Strtoi (BluetoothLeAddrTypeStr);\r
StrHexToBytes (\r
- BluetoothLeAddrStr, sizeof (BluetoothLeDp->Address.Address) * 2,\r
- BluetoothLeDp->Address.Address, sizeof (BluetoothLeDp->Address.Address)\r
+ BluetoothLeAddrStr,\r
+ sizeof (BluetoothLeDp->Address.Address) * 2,\r
+ BluetoothLeDp->Address.Address,\r
+ sizeof (BluetoothLeDp->Address.Address)\r
);\r
- return (EFI_DEVICE_PATH_PROTOCOL *) BluetoothLeDp;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)BluetoothLeDp;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextDns (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *DeviceNodeStr;\r
- CHAR16 *DeviceNodeStrPtr;\r
- UINT32 DnsServerIpCount;\r
- UINT16 DnsDeviceNodeLength;\r
- DNS_DEVICE_PATH *DnsDeviceNode;\r
- UINT32 DnsServerIpIndex;\r
- CHAR16 *DnsServerIp;\r
-\r
+ CHAR16 *DeviceNodeStr;\r
+ CHAR16 *DeviceNodeStrPtr;\r
+ UINT32 DnsServerIpCount;\r
+ UINT16 DnsDeviceNodeLength;\r
+ DNS_DEVICE_PATH *DnsDeviceNode;\r
+ UINT32 DnsServerIpIndex;\r
+ CHAR16 *DnsServerIp;\r
\r
//\r
// Count the DNS server address number.\r
DnsServerIpCount = 0;\r
while (DeviceNodeStrPtr != NULL && *DeviceNodeStrPtr != L'\0') {\r
GetNextParamStr (&DeviceNodeStrPtr);\r
- DnsServerIpCount ++;\r
+ DnsServerIpCount++;\r
}\r
\r
FreePool (DeviceNodeStr);\r
//\r
// Create the DNS DeviceNode.\r
//\r
- DnsDeviceNodeLength = (UINT16) (sizeof (EFI_DEVICE_PATH_PROTOCOL) + sizeof (UINT8) + DnsServerIpCount * sizeof (EFI_IP_ADDRESS));\r
- DnsDeviceNode = (DNS_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_DNS_DP,\r
- DnsDeviceNodeLength\r
- );\r
+ DnsDeviceNodeLength = (UINT16)(sizeof (EFI_DEVICE_PATH_PROTOCOL) + sizeof (UINT8) + DnsServerIpCount * sizeof (EFI_IP_ADDRESS));\r
+ DnsDeviceNode = (DNS_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_DNS_DP,\r
+ DnsDeviceNodeLength\r
+ );\r
if (DnsDeviceNode == NULL) {\r
return NULL;\r
}\r
for (DnsServerIpIndex = 0; DnsServerIpIndex < DnsServerIpCount; DnsServerIpIndex++) {\r
DnsServerIp = GetNextParamStr (&TextDeviceNode);\r
if (DnsDeviceNode->IsIPv6 == 0x00) {\r
- StrToIpv4Address (DnsServerIp, NULL, &(DnsDeviceNode->DnsServerIp[DnsServerIpIndex].v4), NULL);\r
+ StrToIpv4Address (DnsServerIp, NULL, &(DnsDeviceNode->DnsServerIp[DnsServerIpIndex].v4), NULL);\r
} else {\r
StrToIpv6Address (DnsServerIp, NULL, &(DnsDeviceNode->DnsServerIp[DnsServerIpIndex].v6), NULL);\r
}\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) DnsDeviceNode;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)DnsDeviceNode;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextUri (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *UriStr;\r
UINTN UriLength;\r
URI_DEVICE_PATH *Uri;\r
\r
- UriStr = GetNextParamStr (&TextDeviceNode);\r
+ UriStr = GetNextParamStr (&TextDeviceNode);\r
UriLength = StrnLenS (UriStr, MAX_UINT16 - sizeof (URI_DEVICE_PATH));\r
- Uri = (URI_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_URI_DP,\r
- (UINT16) (sizeof (URI_DEVICE_PATH) + UriLength)\r
- );\r
+ Uri = (URI_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_URI_DP,\r
+ (UINT16)(sizeof (URI_DEVICE_PATH) + UriLength)\r
+ );\r
\r
while (UriLength-- != 0) {\r
- Uri->Uri[UriLength] = (CHAR8) UriStr[UriLength];\r
+ Uri->Uri[UriLength] = (CHAR8)UriStr[UriLength];\r
}\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Uri;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Uri;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextMediaPath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return DevPathFromTextGenericPath (MEDIA_DEVICE_PATH, TextDeviceNode);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextHD (\r
- IN CHAR16 *TextDeviceNode\r
- )\r
-{\r
- CHAR16 *PartitionStr;\r
- CHAR16 *TypeStr;\r
- CHAR16 *SignatureStr;\r
- CHAR16 *StartStr;\r
- CHAR16 *SizeStr;\r
- UINT32 Signature32;\r
- HARDDRIVE_DEVICE_PATH *Hd;\r
-\r
- PartitionStr = GetNextParamStr (&TextDeviceNode);\r
- TypeStr = GetNextParamStr (&TextDeviceNode);\r
- SignatureStr = GetNextParamStr (&TextDeviceNode);\r
- StartStr = GetNextParamStr (&TextDeviceNode);\r
- SizeStr = GetNextParamStr (&TextDeviceNode);\r
- Hd = (HARDDRIVE_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_HARDDRIVE_DP,\r
- (UINT16) sizeof (HARDDRIVE_DEVICE_PATH)\r
- );\r
+ IN CHAR16 *TextDeviceNode\r
+ )\r
+{\r
+ CHAR16 *PartitionStr;\r
+ CHAR16 *TypeStr;\r
+ CHAR16 *SignatureStr;\r
+ CHAR16 *StartStr;\r
+ CHAR16 *SizeStr;\r
+ UINT32 Signature32;\r
+ HARDDRIVE_DEVICE_PATH *Hd;\r
+\r
+ PartitionStr = GetNextParamStr (&TextDeviceNode);\r
+ TypeStr = GetNextParamStr (&TextDeviceNode);\r
+ SignatureStr = GetNextParamStr (&TextDeviceNode);\r
+ StartStr = GetNextParamStr (&TextDeviceNode);\r
+ SizeStr = GetNextParamStr (&TextDeviceNode);\r
+ Hd = (HARDDRIVE_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_HARDDRIVE_DP,\r
+ (UINT16)sizeof (HARDDRIVE_DEVICE_PATH)\r
+ );\r
\r
- Hd->PartitionNumber = (UINT32) Strtoi (PartitionStr);\r
+ Hd->PartitionNumber = (UINT32)Strtoi (PartitionStr);\r
\r
ZeroMem (Hd->Signature, 16);\r
- Hd->MBRType = (UINT8) 0;\r
+ Hd->MBRType = (UINT8)0;\r
\r
if (StrCmp (TypeStr, L"MBR") == 0) {\r
Hd->SignatureType = SIGNATURE_TYPE_MBR;\r
Hd->MBRType = 0x01;\r
\r
- Signature32 = (UINT32) Strtoi (SignatureStr);\r
+ Signature32 = (UINT32)Strtoi (SignatureStr);\r
CopyMem (Hd->Signature, &Signature32, sizeof (UINT32));\r
} else if (StrCmp (TypeStr, L"GPT") == 0) {\r
Hd->SignatureType = SIGNATURE_TYPE_GUID;\r
Hd->MBRType = 0x02;\r
\r
- StrToGuid (SignatureStr, (EFI_GUID *) Hd->Signature);\r
+ StrToGuid (SignatureStr, (EFI_GUID *)Hd->Signature);\r
} else {\r
- Hd->SignatureType = (UINT8) Strtoi (TypeStr);\r
+ Hd->SignatureType = (UINT8)Strtoi (TypeStr);\r
}\r
\r
Strtoi64 (StartStr, &Hd->PartitionStart);\r
Strtoi64 (SizeStr, &Hd->PartitionSize);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Hd;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Hd;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextCDROM (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *EntryStr;\r
- CHAR16 *StartStr;\r
- CHAR16 *SizeStr;\r
- CDROM_DEVICE_PATH *CDROMDevPath;\r
+ CHAR16 *EntryStr;\r
+ CHAR16 *StartStr;\r
+ CHAR16 *SizeStr;\r
+ CDROM_DEVICE_PATH *CDROMDevPath;\r
\r
- EntryStr = GetNextParamStr (&TextDeviceNode);\r
- StartStr = GetNextParamStr (&TextDeviceNode);\r
- SizeStr = GetNextParamStr (&TextDeviceNode);\r
- CDROMDevPath = (CDROM_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_CDROM_DP,\r
- (UINT16) sizeof (CDROM_DEVICE_PATH)\r
- );\r
+ EntryStr = GetNextParamStr (&TextDeviceNode);\r
+ StartStr = GetNextParamStr (&TextDeviceNode);\r
+ SizeStr = GetNextParamStr (&TextDeviceNode);\r
+ CDROMDevPath = (CDROM_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_CDROM_DP,\r
+ (UINT16)sizeof (CDROM_DEVICE_PATH)\r
+ );\r
\r
- CDROMDevPath->BootEntry = (UINT32) Strtoi (EntryStr);\r
+ CDROMDevPath->BootEntry = (UINT32)Strtoi (EntryStr);\r
Strtoi64 (StartStr, &CDROMDevPath->PartitionStart);\r
Strtoi64 (SizeStr, &CDROMDevPath->PartitionSize);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) CDROMDevPath;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)CDROMDevPath;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVenMedia (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return ConvertFromTextVendor (\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFilePath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
FILEPATH_DEVICE_PATH *File;\r
\r
- File = (FILEPATH_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_FILEPATH_DP,\r
- (UINT16) (sizeof (FILEPATH_DEVICE_PATH) + StrLen (TextDeviceNode) * 2)\r
- );\r
+ File = (FILEPATH_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_FILEPATH_DP,\r
+ (UINT16)(sizeof (FILEPATH_DEVICE_PATH) + StrLen (TextDeviceNode) * 2)\r
+ );\r
\r
StrCpyS (File->PathName, StrLen (TextDeviceNode) + 1, TextDeviceNode);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) File;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)File;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextMedia (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *GuidStr;\r
MEDIA_PROTOCOL_DEVICE_PATH *Media;\r
\r
GuidStr = GetNextParamStr (&TextDeviceNode);\r
- Media = (MEDIA_PROTOCOL_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_PROTOCOL_DP,\r
- (UINT16) sizeof (MEDIA_PROTOCOL_DEVICE_PATH)\r
- );\r
+ Media = (MEDIA_PROTOCOL_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_PROTOCOL_DP,\r
+ (UINT16)sizeof (MEDIA_PROTOCOL_DEVICE_PATH)\r
+ );\r
\r
StrToGuid (GuidStr, &Media->Protocol);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Media;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Media;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFv (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *GuidStr;\r
MEDIA_FW_VOL_DEVICE_PATH *Fv;\r
\r
GuidStr = GetNextParamStr (&TextDeviceNode);\r
- Fv = (MEDIA_FW_VOL_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_PIWG_FW_VOL_DP,\r
- (UINT16) sizeof (MEDIA_FW_VOL_DEVICE_PATH)\r
- );\r
+ Fv = (MEDIA_FW_VOL_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_PIWG_FW_VOL_DP,\r
+ (UINT16)sizeof (MEDIA_FW_VOL_DEVICE_PATH)\r
+ );\r
\r
StrToGuid (GuidStr, &Fv->FvName);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Fv;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Fv;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextFvFile (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
CHAR16 *GuidStr;\r
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFile;\r
\r
GuidStr = GetNextParamStr (&TextDeviceNode);\r
- FvFile = (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_PIWG_FW_FILE_DP,\r
- (UINT16) sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH)\r
- );\r
+ FvFile = (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_PIWG_FW_FILE_DP,\r
+ (UINT16)sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH)\r
+ );\r
\r
StrToGuid (GuidStr, &FvFile->FvFileName);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) FvFile;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)FvFile;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextRelativeOffsetRange (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingOffsetStr;\r
- CHAR16 *EndingOffsetStr;\r
- MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset;\r
+ CHAR16 *StartingOffsetStr;\r
+ CHAR16 *EndingOffsetStr;\r
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset;\r
\r
StartingOffsetStr = GetNextParamStr (&TextDeviceNode);\r
EndingOffsetStr = GetNextParamStr (&TextDeviceNode);\r
- Offset = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RELATIVE_OFFSET_RANGE_DP,\r
- (UINT16) sizeof (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH)\r
- );\r
+ Offset = (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RELATIVE_OFFSET_RANGE_DP,\r
+ (UINT16)sizeof (MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingOffsetStr, &Offset->StartingOffset);\r
Strtoi64 (EndingOffsetStr, &Offset->EndingOffset);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Offset;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Offset;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextRamDisk (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingAddrStr;\r
- CHAR16 *EndingAddrStr;\r
- CHAR16 *TypeGuidStr;\r
- CHAR16 *InstanceStr;\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
- UINT64 StartingAddr;\r
- UINT64 EndingAddr;\r
+ CHAR16 *StartingAddrStr;\r
+ CHAR16 *EndingAddrStr;\r
+ CHAR16 *TypeGuidStr;\r
+ CHAR16 *InstanceStr;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ UINT64 StartingAddr;\r
+ UINT64 EndingAddr;\r
\r
StartingAddrStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddrStr = GetNextParamStr (&TextDeviceNode);\r
InstanceStr = GetNextParamStr (&TextDeviceNode);\r
TypeGuidStr = GetNextParamStr (&TextDeviceNode);\r
- RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RAM_DISK_DP,\r
- (UINT16) sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
- );\r
+ RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RAM_DISK_DP,\r
+ (UINT16)sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingAddrStr, &StartingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->StartingAddr[0]), StartingAddr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->StartingAddr[0]), StartingAddr);\r
Strtoi64 (EndingAddrStr, &EndingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->EndingAddr[0]), EndingAddr);\r
- RamDisk->Instance = (UINT16) Strtoi (InstanceStr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->EndingAddr[0]), EndingAddr);\r
+ RamDisk->Instance = (UINT16)Strtoi (InstanceStr);\r
StrToGuid (TypeGuidStr, &RamDisk->TypeGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) RamDisk;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)RamDisk;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVirtualDisk (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingAddrStr;\r
- CHAR16 *EndingAddrStr;\r
- CHAR16 *InstanceStr;\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
- UINT64 StartingAddr;\r
- UINT64 EndingAddr;\r
+ CHAR16 *StartingAddrStr;\r
+ CHAR16 *EndingAddrStr;\r
+ CHAR16 *InstanceStr;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ UINT64 StartingAddr;\r
+ UINT64 EndingAddr;\r
\r
StartingAddrStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddrStr = GetNextParamStr (&TextDeviceNode);\r
InstanceStr = GetNextParamStr (&TextDeviceNode);\r
\r
- RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RAM_DISK_DP,\r
- (UINT16) sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
- );\r
+ RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RAM_DISK_DP,\r
+ (UINT16)sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingAddrStr, &StartingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->StartingAddr[0]), StartingAddr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->StartingAddr[0]), StartingAddr);\r
Strtoi64 (EndingAddrStr, &EndingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->EndingAddr[0]), EndingAddr);\r
- RamDisk->Instance = (UINT16) Strtoi (InstanceStr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->EndingAddr[0]), EndingAddr);\r
+ RamDisk->Instance = (UINT16)Strtoi (InstanceStr);\r
CopyGuid (&RamDisk->TypeGuid, &gEfiVirtualDiskGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) RamDisk;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)RamDisk;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextVirtualCd (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingAddrStr;\r
- CHAR16 *EndingAddrStr;\r
- CHAR16 *InstanceStr;\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
- UINT64 StartingAddr;\r
- UINT64 EndingAddr;\r
+ CHAR16 *StartingAddrStr;\r
+ CHAR16 *EndingAddrStr;\r
+ CHAR16 *InstanceStr;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ UINT64 StartingAddr;\r
+ UINT64 EndingAddr;\r
\r
StartingAddrStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddrStr = GetNextParamStr (&TextDeviceNode);\r
InstanceStr = GetNextParamStr (&TextDeviceNode);\r
\r
- RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RAM_DISK_DP,\r
- (UINT16) sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
- );\r
+ RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RAM_DISK_DP,\r
+ (UINT16)sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingAddrStr, &StartingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->StartingAddr[0]), StartingAddr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->StartingAddr[0]), StartingAddr);\r
Strtoi64 (EndingAddrStr, &EndingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->EndingAddr[0]), EndingAddr);\r
- RamDisk->Instance = (UINT16) Strtoi (InstanceStr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->EndingAddr[0]), EndingAddr);\r
+ RamDisk->Instance = (UINT16)Strtoi (InstanceStr);\r
CopyGuid (&RamDisk->TypeGuid, &gEfiVirtualCdGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) RamDisk;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)RamDisk;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPersistentVirtualDisk (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingAddrStr;\r
- CHAR16 *EndingAddrStr;\r
- CHAR16 *InstanceStr;\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
- UINT64 StartingAddr;\r
- UINT64 EndingAddr;\r
+ CHAR16 *StartingAddrStr;\r
+ CHAR16 *EndingAddrStr;\r
+ CHAR16 *InstanceStr;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ UINT64 StartingAddr;\r
+ UINT64 EndingAddr;\r
\r
StartingAddrStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddrStr = GetNextParamStr (&TextDeviceNode);\r
InstanceStr = GetNextParamStr (&TextDeviceNode);\r
\r
- RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RAM_DISK_DP,\r
- (UINT16) sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
- );\r
+ RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RAM_DISK_DP,\r
+ (UINT16)sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingAddrStr, &StartingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->StartingAddr[0]), StartingAddr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->StartingAddr[0]), StartingAddr);\r
Strtoi64 (EndingAddrStr, &EndingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->EndingAddr[0]), EndingAddr);\r
- RamDisk->Instance = (UINT16) Strtoi (InstanceStr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->EndingAddr[0]), EndingAddr);\r
+ RamDisk->Instance = (UINT16)Strtoi (InstanceStr);\r
CopyGuid (&RamDisk->TypeGuid, &gEfiPersistentVirtualDiskGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) RamDisk;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)RamDisk;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextPersistentVirtualCd (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- CHAR16 *StartingAddrStr;\r
- CHAR16 *EndingAddrStr;\r
- CHAR16 *InstanceStr;\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
- UINT64 StartingAddr;\r
- UINT64 EndingAddr;\r
+ CHAR16 *StartingAddrStr;\r
+ CHAR16 *EndingAddrStr;\r
+ CHAR16 *InstanceStr;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ UINT64 StartingAddr;\r
+ UINT64 EndingAddr;\r
\r
StartingAddrStr = GetNextParamStr (&TextDeviceNode);\r
EndingAddrStr = GetNextParamStr (&TextDeviceNode);\r
InstanceStr = GetNextParamStr (&TextDeviceNode);\r
\r
- RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *) CreateDeviceNode (\r
- MEDIA_DEVICE_PATH,\r
- MEDIA_RAM_DISK_DP,\r
- (UINT16) sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
- );\r
+ RamDisk = (MEDIA_RAM_DISK_DEVICE_PATH *)CreateDeviceNode (\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_RAM_DISK_DP,\r
+ (UINT16)sizeof (MEDIA_RAM_DISK_DEVICE_PATH)\r
+ );\r
\r
Strtoi64 (StartingAddrStr, &StartingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->StartingAddr[0]), StartingAddr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->StartingAddr[0]), StartingAddr);\r
Strtoi64 (EndingAddrStr, &EndingAddr);\r
- WriteUnaligned64 ((UINT64 *) &(RamDisk->EndingAddr[0]), EndingAddr);\r
- RamDisk->Instance = (UINT16) Strtoi (InstanceStr);\r
+ WriteUnaligned64 ((UINT64 *)&(RamDisk->EndingAddr[0]), EndingAddr);\r
+ RamDisk->Instance = (UINT16)Strtoi (InstanceStr);\r
CopyGuid (&RamDisk->TypeGuid, &gEfiPersistentVirtualCdGuid);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) RamDisk;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)RamDisk;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextBbsPath (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
return DevPathFromTextGenericPath (BBS_DEVICE_PATH, TextDeviceNode);\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextBBS (\r
- IN CHAR16 *TextDeviceNode\r
- )\r
-{\r
- CHAR16 *TypeStr;\r
- CHAR16 *IdStr;\r
- CHAR16 *FlagsStr;\r
- CHAR8 *AsciiStr;\r
- BBS_BBS_DEVICE_PATH *Bbs;\r
-\r
- TypeStr = GetNextParamStr (&TextDeviceNode);\r
- IdStr = GetNextParamStr (&TextDeviceNode);\r
- FlagsStr = GetNextParamStr (&TextDeviceNode);\r
- Bbs = (BBS_BBS_DEVICE_PATH *) CreateDeviceNode (\r
- BBS_DEVICE_PATH,\r
- BBS_BBS_DP,\r
- (UINT16) (sizeof (BBS_BBS_DEVICE_PATH) + StrLen (IdStr))\r
- );\r
+ IN CHAR16 *TextDeviceNode\r
+ )\r
+{\r
+ CHAR16 *TypeStr;\r
+ CHAR16 *IdStr;\r
+ CHAR16 *FlagsStr;\r
+ CHAR8 *AsciiStr;\r
+ BBS_BBS_DEVICE_PATH *Bbs;\r
+\r
+ TypeStr = GetNextParamStr (&TextDeviceNode);\r
+ IdStr = GetNextParamStr (&TextDeviceNode);\r
+ FlagsStr = GetNextParamStr (&TextDeviceNode);\r
+ Bbs = (BBS_BBS_DEVICE_PATH *)CreateDeviceNode (\r
+ BBS_DEVICE_PATH,\r
+ BBS_BBS_DP,\r
+ (UINT16)(sizeof (BBS_BBS_DEVICE_PATH) + StrLen (IdStr))\r
+ );\r
\r
if (StrCmp (TypeStr, L"Floppy") == 0) {\r
Bbs->DeviceType = BBS_TYPE_FLOPPY;\r
} else if (StrCmp (TypeStr, L"Network") == 0) {\r
Bbs->DeviceType = BBS_TYPE_EMBEDDED_NETWORK;\r
} else {\r
- Bbs->DeviceType = (UINT16) Strtoi (TypeStr);\r
+ Bbs->DeviceType = (UINT16)Strtoi (TypeStr);\r
}\r
\r
AsciiStr = Bbs->String;\r
StrToAscii (IdStr, &AsciiStr);\r
\r
- Bbs->StatusFlag = (UINT16) Strtoi (FlagsStr);\r
+ Bbs->StatusFlag = (UINT16)Strtoi (FlagsStr);\r
\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Bbs;\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Bbs;\r
}\r
\r
/**\r
**/\r
EFI_DEVICE_PATH_PROTOCOL *\r
DevPathFromTextSata (\r
- IN CHAR16 *TextDeviceNode\r
+ IN CHAR16 *TextDeviceNode\r
)\r
{\r
- SATA_DEVICE_PATH *Sata;\r
- CHAR16 *Param1;\r
- CHAR16 *Param2;\r
- CHAR16 *Param3;\r
+ SATA_DEVICE_PATH *Sata;\r
+ CHAR16 *Param1;\r
+ CHAR16 *Param2;\r
+ CHAR16 *Param3;\r
\r
Param1 = GetNextParamStr (&TextDeviceNode);\r
Param2 = GetNextParamStr (&TextDeviceNode);\r
Param3 = GetNextParamStr (&TextDeviceNode);\r
\r
- Sata = (SATA_DEVICE_PATH *) CreateDeviceNode (\r
- MESSAGING_DEVICE_PATH,\r
- MSG_SATA_DP,\r
- (UINT16) sizeof (SATA_DEVICE_PATH)\r
- );\r
- Sata->HBAPortNumber = (UINT16) Strtoi (Param1);\r
+ Sata = (SATA_DEVICE_PATH *)CreateDeviceNode (\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_SATA_DP,\r
+ (UINT16)sizeof (SATA_DEVICE_PATH)\r
+ );\r
+ Sata->HBAPortNumber = (UINT16)Strtoi (Param1);\r
\r
//\r
// According to UEFI spec, if PMPN is not provided, the default is 0xFFFF\r
if (*Param2 == L'\0' ) {\r
Sata->PortMultiplierPortNumber = 0xFFFF;\r
} else {\r
- Sata->PortMultiplierPortNumber = (UINT16) Strtoi (Param2);\r
- }\r
- Sata->Lun = (UINT16) Strtoi (Param3);\r
-\r
- return (EFI_DEVICE_PATH_PROTOCOL *) Sata;\r
-}\r
-\r
-GLOBAL_REMOVE_IF_UNREFERENCED DEVICE_PATH_FROM_TEXT_TABLE mUefiDevicePathLibDevPathFromTextTable[] = {\r
- {L"Path", DevPathFromTextPath },\r
-\r
- {L"HardwarePath", DevPathFromTextHardwarePath },\r
- {L"Pci", DevPathFromTextPci },\r
- {L"PcCard", DevPathFromTextPcCard },\r
- {L"MemoryMapped", DevPathFromTextMemoryMapped },\r
- {L"VenHw", DevPathFromTextVenHw },\r
- {L"Ctrl", DevPathFromTextCtrl },\r
- {L"BMC", DevPathFromTextBmc },\r
-\r
- {L"AcpiPath", DevPathFromTextAcpiPath },\r
- {L"Acpi", DevPathFromTextAcpi },\r
- {L"PciRoot", DevPathFromTextPciRoot },\r
- {L"PcieRoot", DevPathFromTextPcieRoot },\r
- {L"Floppy", DevPathFromTextFloppy },\r
- {L"Keyboard", DevPathFromTextKeyboard },\r
- {L"Serial", DevPathFromTextSerial },\r
- {L"ParallelPort", DevPathFromTextParallelPort },\r
- {L"AcpiEx", DevPathFromTextAcpiEx },\r
- {L"AcpiExp", DevPathFromTextAcpiExp },\r
- {L"AcpiAdr", DevPathFromTextAcpiAdr },\r
-\r
- {L"Msg", DevPathFromTextMsg },\r
- {L"Ata", DevPathFromTextAta },\r
- {L"Scsi", DevPathFromTextScsi },\r
- {L"Fibre", DevPathFromTextFibre },\r
- {L"FibreEx", DevPathFromTextFibreEx },\r
- {L"I1394", DevPathFromText1394 },\r
- {L"USB", DevPathFromTextUsb },\r
- {L"I2O", DevPathFromTextI2O },\r
- {L"Infiniband", DevPathFromTextInfiniband },\r
- {L"VenMsg", DevPathFromTextVenMsg },\r
- {L"VenPcAnsi", DevPathFromTextVenPcAnsi },\r
- {L"VenVt100", DevPathFromTextVenVt100 },\r
- {L"VenVt100Plus", DevPathFromTextVenVt100Plus },\r
- {L"VenUtf8", DevPathFromTextVenUtf8 },\r
- {L"UartFlowCtrl", DevPathFromTextUartFlowCtrl },\r
- {L"SAS", DevPathFromTextSAS },\r
- {L"SasEx", DevPathFromTextSasEx },\r
- {L"NVMe", DevPathFromTextNVMe },\r
- {L"UFS", DevPathFromTextUfs },\r
- {L"SD", DevPathFromTextSd },\r
- {L"eMMC", DevPathFromTextEmmc },\r
- {L"DebugPort", DevPathFromTextDebugPort },\r
- {L"MAC", DevPathFromTextMAC },\r
- {L"IPv4", DevPathFromTextIPv4 },\r
- {L"IPv6", DevPathFromTextIPv6 },\r
- {L"Uart", DevPathFromTextUart },\r
- {L"UsbClass", DevPathFromTextUsbClass },\r
- {L"UsbAudio", DevPathFromTextUsbAudio },\r
- {L"UsbCDCControl", DevPathFromTextUsbCDCControl },\r
- {L"UsbHID", DevPathFromTextUsbHID },\r
- {L"UsbImage", DevPathFromTextUsbImage },\r
- {L"UsbPrinter", DevPathFromTextUsbPrinter },\r
- {L"UsbMassStorage", DevPathFromTextUsbMassStorage },\r
- {L"UsbHub", DevPathFromTextUsbHub },\r
- {L"UsbCDCData", DevPathFromTextUsbCDCData },\r
- {L"UsbSmartCard", DevPathFromTextUsbSmartCard },\r
- {L"UsbVideo", DevPathFromTextUsbVideo },\r
- {L"UsbDiagnostic", DevPathFromTextUsbDiagnostic },\r
- {L"UsbWireless", DevPathFromTextUsbWireless },\r
- {L"UsbDeviceFirmwareUpdate", DevPathFromTextUsbDeviceFirmwareUpdate },\r
- {L"UsbIrdaBridge", DevPathFromTextUsbIrdaBridge },\r
- {L"UsbTestAndMeasurement", DevPathFromTextUsbTestAndMeasurement },\r
- {L"UsbWwid", DevPathFromTextUsbWwid },\r
- {L"Unit", DevPathFromTextUnit },\r
- {L"iSCSI", DevPathFromTextiSCSI },\r
- {L"Vlan", DevPathFromTextVlan },\r
- {L"Dns", DevPathFromTextDns },\r
- {L"Uri", DevPathFromTextUri },\r
- {L"Bluetooth", DevPathFromTextBluetooth },\r
- {L"Wi-Fi", DevPathFromTextWiFi },\r
- {L"BluetoothLE", DevPathFromTextBluetoothLE },\r
- {L"MediaPath", DevPathFromTextMediaPath },\r
- {L"HD", DevPathFromTextHD },\r
- {L"CDROM", DevPathFromTextCDROM },\r
- {L"VenMedia", DevPathFromTextVenMedia },\r
- {L"Media", DevPathFromTextMedia },\r
- {L"Fv", DevPathFromTextFv },\r
- {L"FvFile", DevPathFromTextFvFile },\r
- {L"Offset", DevPathFromTextRelativeOffsetRange },\r
- {L"RamDisk", DevPathFromTextRamDisk },\r
- {L"VirtualDisk", DevPathFromTextVirtualDisk },\r
- {L"VirtualCD", DevPathFromTextVirtualCd },\r
- {L"PersistentVirtualDisk", DevPathFromTextPersistentVirtualDisk },\r
- {L"PersistentVirtualCD", DevPathFromTextPersistentVirtualCd },\r
-\r
- {L"BbsPath", DevPathFromTextBbsPath },\r
- {L"BBS", DevPathFromTextBBS },\r
- {L"Sata", DevPathFromTextSata },\r
- {NULL, NULL}\r
+ Sata->PortMultiplierPortNumber = (UINT16)Strtoi (Param2);\r
+ }\r
+\r
+ Sata->Lun = (UINT16)Strtoi (Param3);\r
+\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)Sata;\r
+}\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED DEVICE_PATH_FROM_TEXT_TABLE mUefiDevicePathLibDevPathFromTextTable[] = {\r
+ { L"Path", DevPathFromTextPath },\r
+\r
+ { L"HardwarePath", DevPathFromTextHardwarePath },\r
+ { L"Pci", DevPathFromTextPci },\r
+ { L"PcCard", DevPathFromTextPcCard },\r
+ { L"MemoryMapped", DevPathFromTextMemoryMapped },\r
+ { L"VenHw", DevPathFromTextVenHw },\r
+ { L"Ctrl", DevPathFromTextCtrl },\r
+ { L"BMC", DevPathFromTextBmc },\r
+\r
+ { L"AcpiPath", DevPathFromTextAcpiPath },\r
+ { L"Acpi", DevPathFromTextAcpi },\r
+ { L"PciRoot", DevPathFromTextPciRoot },\r
+ { L"PcieRoot", DevPathFromTextPcieRoot },\r
+ { L"Floppy", DevPathFromTextFloppy },\r
+ { L"Keyboard", DevPathFromTextKeyboard },\r
+ { L"Serial", DevPathFromTextSerial },\r
+ { L"ParallelPort", DevPathFromTextParallelPort },\r
+ { L"AcpiEx", DevPathFromTextAcpiEx },\r
+ { L"AcpiExp", DevPathFromTextAcpiExp },\r
+ { L"AcpiAdr", DevPathFromTextAcpiAdr },\r
+\r
+ { L"Msg", DevPathFromTextMsg },\r
+ { L"Ata", DevPathFromTextAta },\r
+ { L"Scsi", DevPathFromTextScsi },\r
+ { L"Fibre", DevPathFromTextFibre },\r
+ { L"FibreEx", DevPathFromTextFibreEx },\r
+ { L"I1394", DevPathFromText1394 },\r
+ { L"USB", DevPathFromTextUsb },\r
+ { L"I2O", DevPathFromTextI2O },\r
+ { L"Infiniband", DevPathFromTextInfiniband },\r
+ { L"VenMsg", DevPathFromTextVenMsg },\r
+ { L"VenPcAnsi", DevPathFromTextVenPcAnsi },\r
+ { L"VenVt100", DevPathFromTextVenVt100 },\r
+ { L"VenVt100Plus", DevPathFromTextVenVt100Plus },\r
+ { L"VenUtf8", DevPathFromTextVenUtf8 },\r
+ { L"UartFlowCtrl", DevPathFromTextUartFlowCtrl },\r
+ { L"SAS", DevPathFromTextSAS },\r
+ { L"SasEx", DevPathFromTextSasEx },\r
+ { L"NVMe", DevPathFromTextNVMe },\r
+ { L"UFS", DevPathFromTextUfs },\r
+ { L"SD", DevPathFromTextSd },\r
+ { L"eMMC", DevPathFromTextEmmc },\r
+ { L"DebugPort", DevPathFromTextDebugPort },\r
+ { L"MAC", DevPathFromTextMAC },\r
+ { L"IPv4", DevPathFromTextIPv4 },\r
+ { L"IPv6", DevPathFromTextIPv6 },\r
+ { L"Uart", DevPathFromTextUart },\r
+ { L"UsbClass", DevPathFromTextUsbClass },\r
+ { L"UsbAudio", DevPathFromTextUsbAudio },\r
+ { L"UsbCDCControl", DevPathFromTextUsbCDCControl },\r
+ { L"UsbHID", DevPathFromTextUsbHID },\r
+ { L"UsbImage", DevPathFromTextUsbImage },\r
+ { L"UsbPrinter", DevPathFromTextUsbPrinter },\r
+ { L"UsbMassStorage", DevPathFromTextUsbMassStorage },\r
+ { L"UsbHub", DevPathFromTextUsbHub },\r
+ { L"UsbCDCData", DevPathFromTextUsbCDCData },\r
+ { L"UsbSmartCard", DevPathFromTextUsbSmartCard },\r
+ { L"UsbVideo", DevPathFromTextUsbVideo },\r
+ { L"UsbDiagnostic", DevPathFromTextUsbDiagnostic },\r
+ { L"UsbWireless", DevPathFromTextUsbWireless },\r
+ { L"UsbDeviceFirmwareUpdate", DevPathFromTextUsbDeviceFirmwareUpdate },\r
+ { L"UsbIrdaBridge", DevPathFromTextUsbIrdaBridge },\r
+ { L"UsbTestAndMeasurement", DevPathFromTextUsbTestAndMeasurement },\r
+ { L"UsbWwid", DevPathFromTextUsbWwid },\r
+ { L"Unit", DevPathFromTextUnit },\r
+ { L"iSCSI", DevPathFromTextiSCSI },\r
+ { L"Vlan", DevPathFromTextVlan },\r
+ { L"Dns", DevPathFromTextDns },\r
+ { L"Uri", DevPathFromTextUri },\r
+ { L"Bluetooth", DevPathFromTextBluetooth },\r
+ { L"Wi-Fi", DevPathFromTextWiFi },\r
+ { L"BluetoothLE", DevPathFromTextBluetoothLE },\r
+ { L"MediaPath", DevPathFromTextMediaPath },\r
+ { L"HD", DevPathFromTextHD },\r
+ { L"CDROM", DevPathFromTextCDROM },\r
+ { L"VenMedia", DevPathFromTextVenMedia },\r
+ { L"Media", DevPathFromTextMedia },\r
+ { L"Fv", DevPathFromTextFv },\r
+ { L"FvFile", DevPathFromTextFvFile },\r
+ { L"Offset", DevPathFromTextRelativeOffsetRange },\r
+ { L"RamDisk", DevPathFromTextRamDisk },\r
+ { L"VirtualDisk", DevPathFromTextVirtualDisk },\r
+ { L"VirtualCD", DevPathFromTextVirtualCd },\r
+ { L"PersistentVirtualDisk", DevPathFromTextPersistentVirtualDisk },\r
+ { L"PersistentVirtualCD", DevPathFromTextPersistentVirtualCd },\r
+\r
+ { L"BbsPath", DevPathFromTextBbsPath },\r
+ { L"BBS", DevPathFromTextBBS },\r
+ { L"Sata", DevPathFromTextSata },\r
+ { NULL, NULL }\r
};\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
)\r
{\r
- DEVICE_PATH_FROM_TEXT FromText;\r
- CHAR16 *ParamStr;\r
- EFI_DEVICE_PATH_PROTOCOL *DeviceNode;\r
- CHAR16 *DeviceNodeStr;\r
- UINTN Index;\r
+ DEVICE_PATH_FROM_TEXT FromText;\r
+ CHAR16 *ParamStr;\r
+ EFI_DEVICE_PATH_PROTOCOL *DeviceNode;\r
+ CHAR16 *DeviceNodeStr;\r
+ UINTN Index;\r
\r
if ((TextDeviceNode == NULL) || (IS_NULL (*TextDeviceNode))) {\r
return NULL;\r
//\r
// A file path\r
//\r
- FromText = DevPathFromTextFilePath;\r
+ FromText = DevPathFromTextFilePath;\r
DeviceNode = FromText (DeviceNodeStr);\r
} else {\r
DeviceNode = FromText (ParamStr);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
)\r
{\r
- EFI_DEVICE_PATH_PROTOCOL *DeviceNode;\r
- EFI_DEVICE_PATH_PROTOCOL *NewDevicePath;\r
- CHAR16 *DevicePathStr;\r
- CHAR16 *Str;\r
- CHAR16 *DeviceNodeStr;\r
- BOOLEAN IsInstanceEnd;\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *DeviceNode;\r
+ EFI_DEVICE_PATH_PROTOCOL *NewDevicePath;\r
+ CHAR16 *DevicePathStr;\r
+ CHAR16 *Str;\r
+ CHAR16 *DeviceNodeStr;\r
+ BOOLEAN IsInstanceEnd;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
\r
if ((TextDevicePath == NULL) || (IS_NULL (*TextDevicePath))) {\r
return NULL;\r
}\r
\r
- DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocatePool (END_DEVICE_PATH_LENGTH);\r
+ DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)AllocatePool (END_DEVICE_PATH_LENGTH);\r
ASSERT (DevicePath != NULL);\r
SetDevicePathEndNode (DevicePath);\r
\r
DevicePathStr = UefiDevicePathLibStrDuplicate (TextDevicePath);\r
\r
- Str = DevicePathStr;\r
+ Str = DevicePathStr;\r
while ((DeviceNodeStr = GetNextDeviceNodeStr (&Str, &IsInstanceEnd)) != NULL) {\r
DeviceNode = UefiDevicePathLibConvertTextToDeviceNode (DeviceNodeStr);\r
\r
DevicePath = NewDevicePath;\r
\r
if (IsInstanceEnd) {\r
- DeviceNode = (EFI_DEVICE_PATH_PROTOCOL *) AllocatePool (END_DEVICE_PATH_LENGTH);\r
+ DeviceNode = (EFI_DEVICE_PATH_PROTOCOL *)AllocatePool (END_DEVICE_PATH_LENGTH);\r
ASSERT (DeviceNode != NULL);\r
SetDevicePathEndNode (DeviceNode);\r
DeviceNode->SubType = END_INSTANCE_DEVICE_PATH_SUBTYPE;\r
CHAR16 *\r
EFIAPI\r
UefiDevicePathLibCatPrint (\r
- IN OUT POOL_PRINT *Str,\r
- IN CHAR16 *Fmt,\r
+ IN OUT POOL_PRINT *Str,\r
+ IN CHAR16 *Fmt,\r
...\r
)\r
{\r
- UINTN Count;\r
- VA_LIST Args;\r
+ UINTN Count;\r
+ VA_LIST Args;\r
\r
VA_START (Args, Fmt);\r
Count = SPrintLength (Fmt, Args);\r
- VA_END(Args);\r
+ VA_END (Args);\r
\r
if ((Str->Count + (Count + 1)) * sizeof (CHAR16) > Str->Capacity) {\r
Str->Capacity = (Str->Count + (Count + 1) * 2) * sizeof (CHAR16);\r
- Str->Str = ReallocatePool (\r
- Str->Count * sizeof (CHAR16),\r
- Str->Capacity,\r
- Str->Str\r
- );\r
+ Str->Str = ReallocatePool (\r
+ Str->Count * sizeof (CHAR16),\r
+ Str->Capacity,\r
+ Str->Str\r
+ );\r
ASSERT (Str->Str != NULL);\r
}\r
+\r
VA_START (Args, Fmt);\r
UnicodeVSPrint (&Str->Str[Str->Count], Str->Capacity - Str->Count * sizeof (CHAR16), Fmt, Args);\r
Str->Count += Count;\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- PCI_DEVICE_PATH *Pci;\r
+ PCI_DEVICE_PATH *Pci;\r
\r
Pci = DevPath;\r
UefiDevicePathLibCatPrint (Str, L"Pci(0x%x,0x%x)", Pci->Device, Pci->Function);\r
UINT32 FlowControlMap;\r
UINT16 Info;\r
\r
- Vendor = (VENDOR_DEVICE_PATH *) DevPath;\r
+ Vendor = (VENDOR_DEVICE_PATH *)DevPath;\r
switch (DevicePathType (&Vendor->Header)) {\r
- case HARDWARE_DEVICE_PATH:\r
- Type = L"Hw";\r
- break;\r
-\r
- case MESSAGING_DEVICE_PATH:\r
- Type = L"Msg";\r
- if (AllowShortcuts) {\r
- if (CompareGuid (&Vendor->Guid, &gEfiPcAnsiGuid)) {\r
- UefiDevicePathLibCatPrint (Str, L"VenPcAnsi()");\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiVT100Guid)) {\r
- UefiDevicePathLibCatPrint (Str, L"VenVt100()");\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiVT100PlusGuid)) {\r
- UefiDevicePathLibCatPrint (Str, L"VenVt100Plus()");\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiVTUTF8Guid)) {\r
- UefiDevicePathLibCatPrint (Str, L"VenUtf8()");\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiUartDevicePathGuid)) {\r
- FlowControlMap = (((UART_FLOW_CONTROL_DEVICE_PATH *) Vendor)->FlowControlMap);\r
- switch (FlowControlMap & 0x00000003) {\r
- case 0:\r
- UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"None");\r
- break;\r
-\r
- case 1:\r
- UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"Hardware");\r
- break;\r
-\r
- case 2:\r
- UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"XonXoff");\r
- break;\r
-\r
- default:\r
- break;\r
- }\r
+ case HARDWARE_DEVICE_PATH:\r
+ Type = L"Hw";\r
+ break;\r
\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiSasDevicePathGuid)) {\r
- UefiDevicePathLibCatPrint (\r
- Str,\r
- L"SAS(0x%lx,0x%lx,0x%x,",\r
- ((SAS_DEVICE_PATH *) Vendor)->SasAddress,\r
- ((SAS_DEVICE_PATH *) Vendor)->Lun,\r
- ((SAS_DEVICE_PATH *) Vendor)->RelativeTargetPort\r
- );\r
- Info = (((SAS_DEVICE_PATH *) Vendor)->DeviceTopology);\r
- if (((Info & 0x0f) == 0) && ((Info & BIT7) == 0)) {\r
- UefiDevicePathLibCatPrint (Str, L"NoTopology,0,0,0,");\r
- } else if (((Info & 0x0f) <= 2) && ((Info & BIT7) == 0)) {\r
+ case MESSAGING_DEVICE_PATH:\r
+ Type = L"Msg";\r
+ if (AllowShortcuts) {\r
+ if (CompareGuid (&Vendor->Guid, &gEfiPcAnsiGuid)) {\r
+ UefiDevicePathLibCatPrint (Str, L"VenPcAnsi()");\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiVT100Guid)) {\r
+ UefiDevicePathLibCatPrint (Str, L"VenVt100()");\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiVT100PlusGuid)) {\r
+ UefiDevicePathLibCatPrint (Str, L"VenVt100Plus()");\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiVTUTF8Guid)) {\r
+ UefiDevicePathLibCatPrint (Str, L"VenUtf8()");\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiUartDevicePathGuid)) {\r
+ FlowControlMap = (((UART_FLOW_CONTROL_DEVICE_PATH *)Vendor)->FlowControlMap);\r
+ switch (FlowControlMap & 0x00000003) {\r
+ case 0:\r
+ UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"None");\r
+ break;\r
+\r
+ case 1:\r
+ UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"Hardware");\r
+ break;\r
+\r
+ case 2:\r
+ UefiDevicePathLibCatPrint (Str, L"UartFlowCtrl(%s)", L"XonXoff");\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiSasDevicePathGuid)) {\r
UefiDevicePathLibCatPrint (\r
Str,\r
- L"%s,%s,%s,",\r
- ((Info & BIT4) != 0) ? L"SATA" : L"SAS",\r
- ((Info & BIT5) != 0) ? L"External" : L"Internal",\r
- ((Info & BIT6) != 0) ? L"Expanded" : L"Direct"\r
+ L"SAS(0x%lx,0x%lx,0x%x,",\r
+ ((SAS_DEVICE_PATH *)Vendor)->SasAddress,\r
+ ((SAS_DEVICE_PATH *)Vendor)->Lun,\r
+ ((SAS_DEVICE_PATH *)Vendor)->RelativeTargetPort\r
);\r
- if ((Info & 0x0f) == 1) {\r
- UefiDevicePathLibCatPrint (Str, L"0,");\r
+ Info = (((SAS_DEVICE_PATH *)Vendor)->DeviceTopology);\r
+ if (((Info & 0x0f) == 0) && ((Info & BIT7) == 0)) {\r
+ UefiDevicePathLibCatPrint (Str, L"NoTopology,0,0,0,");\r
+ } else if (((Info & 0x0f) <= 2) && ((Info & BIT7) == 0)) {\r
+ UefiDevicePathLibCatPrint (\r
+ Str,\r
+ L"%s,%s,%s,",\r
+ ((Info & BIT4) != 0) ? L"SATA" : L"SAS",\r
+ ((Info & BIT5) != 0) ? L"External" : L"Internal",\r
+ ((Info & BIT6) != 0) ? L"Expanded" : L"Direct"\r
+ );\r
+ if ((Info & 0x0f) == 1) {\r
+ UefiDevicePathLibCatPrint (Str, L"0,");\r
+ } else {\r
+ //\r
+ // Value 0x0 thru 0xFF -> Drive 1 thru Drive 256\r
+ //\r
+ UefiDevicePathLibCatPrint (Str, L"0x%x,", ((Info >> 8) & 0xff) + 1);\r
+ }\r
} else {\r
- //\r
- // Value 0x0 thru 0xFF -> Drive 1 thru Drive 256\r
- //\r
- UefiDevicePathLibCatPrint (Str, L"0x%x,", ((Info >> 8) & 0xff) + 1);\r
+ UefiDevicePathLibCatPrint (Str, L"0x%x,0,0,0,", Info);\r
}\r
- } else {\r
- UefiDevicePathLibCatPrint (Str, L"0x%x,0,0,0,", Info);\r
- }\r
\r
- UefiDevicePathLibCatPrint (Str, L"0x%x)", ((SAS_DEVICE_PATH *) Vendor)->Reserved);\r
- return ;\r
- } else if (CompareGuid (&Vendor->Guid, &gEfiDebugPortProtocolGuid)) {\r
- UefiDevicePathLibCatPrint (Str, L"DebugPort()");\r
- return ;\r
+ UefiDevicePathLibCatPrint (Str, L"0x%x)", ((SAS_DEVICE_PATH *)Vendor)->Reserved);\r
+ return;\r
+ } else if (CompareGuid (&Vendor->Guid, &gEfiDebugPortProtocolGuid)) {\r
+ UefiDevicePathLibCatPrint (Str, L"DebugPort()");\r
+ return;\r
+ }\r
}\r
- }\r
- break;\r
\r
- case MEDIA_DEVICE_PATH:\r
- Type = L"Media";\r
- break;\r
+ break;\r
+\r
+ case MEDIA_DEVICE_PATH:\r
+ Type = L"Media";\r
+ break;\r
\r
- default:\r
- Type = L"?";\r
- break;\r
+ default:\r
+ Type = L"?";\r
+ break;\r
}\r
\r
DataLength = DevicePathNodeLength (&Vendor->Header) - sizeof (VENDOR_DEVICE_PATH);\r
if (DataLength != 0) {\r
UefiDevicePathLibCatPrint (Str, L",");\r
for (Index = 0; Index < DataLength; Index++) {\r
- UefiDevicePathLibCatPrint (Str, L"%02x", ((VENDOR_DEVICE_PATH_WITH_DATA *) Vendor)->VendorDefinedData[Index]);\r
+ UefiDevicePathLibCatPrint (Str, L"%02x", ((VENDOR_DEVICE_PATH_WITH_DATA *)Vendor)->VendorDefinedData[Index]);\r
}\r
}\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- BMC_DEVICE_PATH *Bmc;\r
+ BMC_DEVICE_PATH *Bmc;\r
\r
Bmc = DevPath;\r
UefiDevicePathLibCatPrint (\r
Str,\r
L"BMC(0x%x,0x%lx)",\r
Bmc->InterfaceType,\r
- ReadUnaligned64 ((UINT64 *) (&Bmc->BaseAddress))\r
+ ReadUnaligned64 ((UINT64 *)(&Bmc->BaseAddress))\r
);\r
}\r
\r
Acpi = DevPath;\r
if ((Acpi->HID & PNP_EISA_ID_MASK) == PNP_EISA_ID_CONST) {\r
switch (EISA_ID_TO_NUM (Acpi->HID)) {\r
- case 0x0a03:\r
- UefiDevicePathLibCatPrint (Str, L"PciRoot(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0a03:\r
+ UefiDevicePathLibCatPrint (Str, L"PciRoot(0x%x)", Acpi->UID);\r
+ break;\r
\r
- case 0x0a08:\r
- UefiDevicePathLibCatPrint (Str, L"PcieRoot(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0a08:\r
+ UefiDevicePathLibCatPrint (Str, L"PcieRoot(0x%x)", Acpi->UID);\r
+ break;\r
\r
- case 0x0604:\r
- UefiDevicePathLibCatPrint (Str, L"Floppy(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0604:\r
+ UefiDevicePathLibCatPrint (Str, L"Floppy(0x%x)", Acpi->UID);\r
+ break;\r
\r
- case 0x0301:\r
- UefiDevicePathLibCatPrint (Str, L"Keyboard(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0301:\r
+ UefiDevicePathLibCatPrint (Str, L"Keyboard(0x%x)", Acpi->UID);\r
+ break;\r
\r
- case 0x0501:\r
- UefiDevicePathLibCatPrint (Str, L"Serial(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0501:\r
+ UefiDevicePathLibCatPrint (Str, L"Serial(0x%x)", Acpi->UID);\r
+ break;\r
\r
- case 0x0401:\r
- UefiDevicePathLibCatPrint (Str, L"ParallelPort(0x%x)", Acpi->UID);\r
- break;\r
+ case 0x0401:\r
+ UefiDevicePathLibCatPrint (Str, L"ParallelPort(0x%x)", Acpi->UID);\r
+ break;\r
\r
- default:\r
- UefiDevicePathLibCatPrint (Str, L"Acpi(PNP%04x,0x%x)", EISA_ID_TO_NUM (Acpi->HID), Acpi->UID);\r
- break;\r
+ default:\r
+ UefiDevicePathLibCatPrint (Str, L"Acpi(PNP%04x,0x%x)", EISA_ID_TO_NUM (Acpi->HID), Acpi->UID);\r
+ break;\r
}\r
} else {\r
UefiDevicePathLibCatPrint (Str, L"Acpi(0x%08x,0x%x)", Acpi->HID, Acpi->UID);\r
CHAR16 CIDText[11];\r
\r
AcpiEx = DevPath;\r
- HIDStr = (CHAR8 *) (((UINT8 *) AcpiEx) + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
+ HIDStr = (CHAR8 *)(((UINT8 *)AcpiEx) + sizeof (ACPI_EXTENDED_HID_DEVICE_PATH));\r
UIDStr = HIDStr + AsciiStrLen (HIDStr) + 1;\r
CIDStr = UIDStr + AsciiStrLen (UIDStr) + 1;\r
\r
if (DisplayOnly) {\r
if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A03) ||\r
- (EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A03 && EISA_ID_TO_NUM (AcpiEx->HID) != 0x0A08)) {\r
+ ((EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A03) && (EISA_ID_TO_NUM (AcpiEx->HID) != 0x0A08)))\r
+ {\r
if (AcpiEx->UID == 0) {\r
UefiDevicePathLibCatPrint (Str, L"PciRoot(%a)", UIDStr);\r
} else {\r
UefiDevicePathLibCatPrint (Str, L"PciRoot(0x%x)", AcpiEx->UID);\r
}\r
+\r
return;\r
}\r
\r
- if (EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A08 || EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A08) {\r
+ if ((EISA_ID_TO_NUM (AcpiEx->HID) == 0x0A08) || (EISA_ID_TO_NUM (AcpiEx->CID) == 0x0A08)) {\r
if (AcpiEx->UID == 0) {\r
UefiDevicePathLibCatPrint (Str, L"PcieRoot(%a)", UIDStr);\r
} else {\r
UefiDevicePathLibCatPrint (Str, L"PcieRoot(0x%x)", AcpiEx->UID);\r
}\r
+\r
return;\r
}\r
}\r
L"AcpiExp(%s,0,%a)",\r
HIDText,\r
UIDStr\r
- );\r
+ );\r
} else {\r
UefiDevicePathLibCatPrint (\r
Str,\r
HIDText,\r
CIDText,\r
UIDStr\r
- );\r
+ );\r
}\r
} else {\r
if (DisplayOnly) {\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- ACPI_ADR_DEVICE_PATH *AcpiAdr;\r
- UINT16 Index;\r
- UINT16 Length;\r
- UINT16 AdditionalAdrCount;\r
+ ACPI_ADR_DEVICE_PATH *AcpiAdr;\r
+ UINT16 Index;\r
+ UINT16 Length;\r
+ UINT16 AdditionalAdrCount;\r
\r
AcpiAdr = DevPath;\r
- Length = (UINT16) DevicePathNodeLength ((EFI_DEVICE_PATH_PROTOCOL *) AcpiAdr);\r
- AdditionalAdrCount = (UINT16) ((Length - 8) / 4);\r
+ Length = (UINT16)DevicePathNodeLength ((EFI_DEVICE_PATH_PROTOCOL *)AcpiAdr);\r
+ AdditionalAdrCount = (UINT16)((Length - 8) / 4);\r
\r
UefiDevicePathLibCatPrint (Str, L"AcpiAdr(0x%x", AcpiAdr->ADR);\r
for (Index = 0; Index < AdditionalAdrCount; Index++) {\r
- UefiDevicePathLibCatPrint (Str, L",0x%x", *(UINT32 *) ((UINT8 *) AcpiAdr + 8 + Index * 4));\r
+ UefiDevicePathLibCatPrint (Str, L",0x%x", *(UINT32 *)((UINT8 *)AcpiAdr + 8 + Index * 4));\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L")");\r
}\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- ATAPI_DEVICE_PATH *Atapi;\r
+ ATAPI_DEVICE_PATH *Atapi;\r
\r
Atapi = DevPath;\r
\r
for (Index = 0; Index < sizeof (FibreEx->WWN) / sizeof (FibreEx->WWN[0]); Index++) {\r
UefiDevicePathLibCatPrint (Str, L"%02x", FibreEx->WWN[Index]);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L",0x");\r
for (Index = 0; Index < sizeof (FibreEx->Lun) / sizeof (FibreEx->Lun[0]); Index++) {\r
UefiDevicePathLibCatPrint (Str, L"%02x", FibreEx->Lun[Index]);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L")");\r
}\r
\r
for (Index = 0; Index < sizeof (SasEx->SasAddress) / sizeof (SasEx->SasAddress[0]); Index++) {\r
UefiDevicePathLibCatPrint (Str, L"%02x", SasEx->SasAddress[Index]);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L",0x");\r
for (Index = 0; Index < sizeof (SasEx->Lun) / sizeof (SasEx->Lun[0]); Index++) {\r
UefiDevicePathLibCatPrint (Str, L"%02x", SasEx->Lun[Index]);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L",0x%x,", SasEx->RelativeTargetPort);\r
\r
if (((SasEx->DeviceTopology & 0x0f) == 0) && ((SasEx->DeviceTopology & BIT7) == 0)) {\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L")");\r
- return ;\r
-\r
+ return;\r
}\r
\r
/**\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- NVME_NAMESPACE_DEVICE_PATH *Nvme;\r
- UINT8 *Uuid;\r
+ NVME_NAMESPACE_DEVICE_PATH *Nvme;\r
+ UINT8 *Uuid;\r
\r
Nvme = DevPath;\r
- Uuid = (UINT8 *) &Nvme->NamespaceUuid;\r
+ Uuid = (UINT8 *)&Nvme->NamespaceUuid;\r
UefiDevicePathLibCatPrint (\r
Str,\r
L"NVMe(0x%x,%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x)",\r
Nvme->NamespaceId,\r
- Uuid[7], Uuid[6], Uuid[5], Uuid[4],\r
- Uuid[3], Uuid[2], Uuid[1], Uuid[0]\r
+ Uuid[7],\r
+ Uuid[6],\r
+ Uuid[5],\r
+ Uuid[4],\r
+ Uuid[3],\r
+ Uuid[2],\r
+ Uuid[1],\r
+ Uuid[0]\r
);\r
}\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- SD_DEVICE_PATH *Sd;\r
+ SD_DEVICE_PATH *Sd;\r
\r
Sd = DevPath;\r
UefiDevicePathLibCatPrint (\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- EMMC_DEVICE_PATH *Emmc;\r
+ EMMC_DEVICE_PATH *Emmc;\r
\r
Emmc = DevPath;\r
UefiDevicePathLibCatPrint (\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- F1394_DEVICE_PATH *F1394DevPath;\r
+ F1394_DEVICE_PATH *F1394DevPath;\r
\r
F1394DevPath = DevPath;\r
//\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- USB_DEVICE_PATH *Usb;\r
+ USB_DEVICE_PATH *Usb;\r
\r
Usb = DevPath;\r
UefiDevicePathLibCatPrint (Str, L"USB(0x%x,0x%x)", Usb->ParentPortNumber, Usb->InterfaceNumber);\r
\r
UsbWWId = DevPath;\r
\r
- SerialNumberStr = (CHAR16 *) ((UINT8 *) UsbWWId + sizeof (USB_WWID_DEVICE_PATH));\r
- Length = (UINT16) ((DevicePathNodeLength ((EFI_DEVICE_PATH_PROTOCOL *) UsbWWId) - sizeof (USB_WWID_DEVICE_PATH)) / sizeof (CHAR16));\r
- if (Length >= 1 && SerialNumberStr [Length - 1] != 0) {\r
+ SerialNumberStr = (CHAR16 *)((UINT8 *)UsbWWId + sizeof (USB_WWID_DEVICE_PATH));\r
+ Length = (UINT16)((DevicePathNodeLength ((EFI_DEVICE_PATH_PROTOCOL *)UsbWWId) - sizeof (USB_WWID_DEVICE_PATH)) / sizeof (CHAR16));\r
+ if ((Length >= 1) && (SerialNumberStr[Length - 1] != 0)) {\r
//\r
// In case no NULL terminator in SerialNumber, create a new one with NULL terminator\r
//\r
NewStr = AllocateCopyPool ((Length + 1) * sizeof (CHAR16), SerialNumberStr);\r
ASSERT (NewStr != NULL);\r
- NewStr [Length] = 0;\r
+ NewStr[Length] = 0;\r
SerialNumberStr = NewStr;\r
}\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicalUnit;\r
+ DEVICE_LOGICAL_UNIT_DEVICE_PATH *LogicalUnit;\r
\r
LogicalUnit = DevPath;\r
UefiDevicePathLibCatPrint (Str, L"Unit(0x%x)", LogicalUnit->Lun);\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- USB_CLASS_DEVICE_PATH *UsbClass;\r
- BOOLEAN IsKnownSubClass;\r
-\r
+ USB_CLASS_DEVICE_PATH *UsbClass;\r
+ BOOLEAN IsKnownSubClass;\r
\r
UsbClass = DevPath;\r
\r
IsKnownSubClass = TRUE;\r
switch (UsbClass->DeviceClass) {\r
- case USB_CLASS_AUDIO:\r
- UefiDevicePathLibCatPrint (Str, L"UsbAudio");\r
- break;\r
+ case USB_CLASS_AUDIO:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbAudio");\r
+ break;\r
\r
- case USB_CLASS_CDCCONTROL:\r
- UefiDevicePathLibCatPrint (Str, L"UsbCDCControl");\r
- break;\r
+ case USB_CLASS_CDCCONTROL:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbCDCControl");\r
+ break;\r
\r
- case USB_CLASS_HID:\r
- UefiDevicePathLibCatPrint (Str, L"UsbHID");\r
- break;\r
+ case USB_CLASS_HID:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbHID");\r
+ break;\r
\r
- case USB_CLASS_IMAGE:\r
- UefiDevicePathLibCatPrint (Str, L"UsbImage");\r
- break;\r
+ case USB_CLASS_IMAGE:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbImage");\r
+ break;\r
\r
- case USB_CLASS_PRINTER:\r
- UefiDevicePathLibCatPrint (Str, L"UsbPrinter");\r
- break;\r
+ case USB_CLASS_PRINTER:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbPrinter");\r
+ break;\r
\r
- case USB_CLASS_MASS_STORAGE:\r
- UefiDevicePathLibCatPrint (Str, L"UsbMassStorage");\r
- break;\r
+ case USB_CLASS_MASS_STORAGE:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbMassStorage");\r
+ break;\r
\r
- case USB_CLASS_HUB:\r
- UefiDevicePathLibCatPrint (Str, L"UsbHub");\r
- break;\r
+ case USB_CLASS_HUB:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbHub");\r
+ break;\r
\r
- case USB_CLASS_CDCDATA:\r
- UefiDevicePathLibCatPrint (Str, L"UsbCDCData");\r
- break;\r
+ case USB_CLASS_CDCDATA:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbCDCData");\r
+ break;\r
\r
- case USB_CLASS_SMART_CARD:\r
- UefiDevicePathLibCatPrint (Str, L"UsbSmartCard");\r
- break;\r
+ case USB_CLASS_SMART_CARD:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbSmartCard");\r
+ break;\r
\r
- case USB_CLASS_VIDEO:\r
- UefiDevicePathLibCatPrint (Str, L"UsbVideo");\r
- break;\r
+ case USB_CLASS_VIDEO:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbVideo");\r
+ break;\r
\r
- case USB_CLASS_DIAGNOSTIC:\r
- UefiDevicePathLibCatPrint (Str, L"UsbDiagnostic");\r
- break;\r
+ case USB_CLASS_DIAGNOSTIC:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbDiagnostic");\r
+ break;\r
\r
- case USB_CLASS_WIRELESS:\r
- UefiDevicePathLibCatPrint (Str, L"UsbWireless");\r
- break;\r
+ case USB_CLASS_WIRELESS:\r
+ UefiDevicePathLibCatPrint (Str, L"UsbWireless");\r
+ break;\r
\r
- default:\r
- IsKnownSubClass = FALSE;\r
- break;\r
+ default:\r
+ IsKnownSubClass = FALSE;\r
+ break;\r
}\r
\r
if (IsKnownSubClass) {\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- SATA_DEVICE_PATH *Sata;\r
+ SATA_DEVICE_PATH *Sata;\r
\r
Sata = DevPath;\r
UefiDevicePathLibCatPrint (\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- I2O_DEVICE_PATH *I2ODevPath;\r
+ I2O_DEVICE_PATH *I2ODevPath;\r
\r
I2ODevPath = DevPath;\r
UefiDevicePathLibCatPrint (Str, L"I2O(0x%x)", I2ODevPath->Tid);\r
MacDevPath = DevPath;\r
\r
HwAddressSize = sizeof (EFI_MAC_ADDRESS);\r
- if (MacDevPath->IfType == 0x01 || MacDevPath->IfType == 0x00) {\r
+ if ((MacDevPath->IfType == 0x01) || (MacDevPath->IfType == 0x00)) {\r
HwAddressSize = 6;\r
}\r
\r
**/\r
VOID\r
CatIPv4Address (\r
- IN OUT POOL_PRINT *Str,\r
- IN EFI_IPv4_ADDRESS *Address\r
+ IN OUT POOL_PRINT *Str,\r
+ IN EFI_IPv4_ADDRESS *Address\r
)\r
{\r
UefiDevicePathLibCatPrint (Str, L"%d.%d.%d.%d", Address->Addr[0], Address->Addr[1], Address->Addr[2], Address->Addr[3]);\r
**/\r
VOID\r
CatIPv6Address (\r
- IN OUT POOL_PRINT *Str,\r
- IN EFI_IPv6_ADDRESS *Address\r
+ IN OUT POOL_PRINT *Str,\r
+ IN EFI_IPv6_ADDRESS *Address\r
)\r
{\r
UefiDevicePathLibCatPrint (\r
- Str, L"%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x",\r
- Address->Addr[0], Address->Addr[1],\r
- Address->Addr[2], Address->Addr[3],\r
- Address->Addr[4], Address->Addr[5],\r
- Address->Addr[6], Address->Addr[7],\r
- Address->Addr[8], Address->Addr[9],\r
- Address->Addr[10], Address->Addr[11],\r
- Address->Addr[12], Address->Addr[13],\r
- Address->Addr[14], Address->Addr[15]\r
- );\r
+ Str,\r
+ L"%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x",\r
+ Address->Addr[0],\r
+ Address->Addr[1],\r
+ Address->Addr[2],\r
+ Address->Addr[3],\r
+ Address->Addr[4],\r
+ Address->Addr[5],\r
+ Address->Addr[6],\r
+ Address->Addr[7],\r
+ Address->Addr[8],\r
+ Address->Addr[9],\r
+ Address->Addr[10],\r
+ Address->Addr[11],\r
+ Address->Addr[12],\r
+ Address->Addr[13],\r
+ Address->Addr[14],\r
+ Address->Addr[15]\r
+ );\r
}\r
\r
/**\r
\r
if (DisplayOnly) {\r
UefiDevicePathLibCatPrint (Str, L")");\r
- return ;\r
+ return;\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L",");\r
UefiDevicePathLibCatPrint (Str, L",");\r
CatIPv4Address (Str, &IPDevPath->SubnetMask);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L")");\r
}\r
\r
CatIPv6Address (Str, &IPDevPath->RemoteIpAddress);\r
if (DisplayOnly) {\r
UefiDevicePathLibCatPrint (Str, L")");\r
- return ;\r
+ return;\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L",");\r
UefiDevicePathLibCatPrint (Str, L",0x%x,", IPDevPath->PrefixLength);\r
CatIPv6Address (Str, &IPDevPath->GatewayIpAddress);\r
}\r
+\r
UefiDevicePathLibCatPrint (Str, L")");\r
}\r
\r
\r
Uart = DevPath;\r
switch (Uart->Parity) {\r
- case 0:\r
- Parity = 'D';\r
- break;\r
+ case 0:\r
+ Parity = 'D';\r
+ break;\r
\r
- case 1:\r
- Parity = 'N';\r
- break;\r
+ case 1:\r
+ Parity = 'N';\r
+ break;\r
\r
- case 2:\r
- Parity = 'E';\r
- break;\r
+ case 2:\r
+ Parity = 'E';\r
+ break;\r
\r
- case 3:\r
- Parity = 'O';\r
- break;\r
+ case 3:\r
+ Parity = 'O';\r
+ break;\r
\r
- case 4:\r
- Parity = 'M';\r
- break;\r
+ case 4:\r
+ Parity = 'M';\r
+ break;\r
\r
- case 5:\r
- Parity = 'S';\r
- break;\r
+ case 5:\r
+ Parity = 'S';\r
+ break;\r
\r
- default:\r
- Parity = 'x';\r
- break;\r
+ default:\r
+ Parity = 'x';\r
+ break;\r
}\r
\r
if (Uart->BaudRate == 0) {\r
UefiDevicePathLibCatPrint (Str, L"%c,", Parity);\r
\r
switch (Uart->StopBits) {\r
- case 0:\r
- UefiDevicePathLibCatPrint (Str, L"D)");\r
- break;\r
+ case 0:\r
+ UefiDevicePathLibCatPrint (Str, L"D)");\r
+ break;\r
\r
- case 1:\r
- UefiDevicePathLibCatPrint (Str, L"1)");\r
- break;\r
+ case 1:\r
+ UefiDevicePathLibCatPrint (Str, L"1)");\r
+ break;\r
\r
- case 2:\r
- UefiDevicePathLibCatPrint (Str, L"1.5)");\r
- break;\r
+ case 2:\r
+ UefiDevicePathLibCatPrint (Str, L"1.5)");\r
+ break;\r
\r
- case 3:\r
- UefiDevicePathLibCatPrint (Str, L"2)");\r
- break;\r
+ case 3:\r
+ UefiDevicePathLibCatPrint (Str, L"2)");\r
+ break;\r
\r
- default:\r
- UefiDevicePathLibCatPrint (Str, L"x)");\r
- break;\r
+ default:\r
+ UefiDevicePathLibCatPrint (Str, L"x)");\r
+ break;\r
}\r
}\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- ISCSI_DEVICE_PATH_WITH_NAME *ISCSIDevPath;\r
- UINT16 Options;\r
- UINTN Index;\r
+ ISCSI_DEVICE_PATH_WITH_NAME *ISCSIDevPath;\r
+ UINT16 Options;\r
+ UINTN Index;\r
\r
ISCSIDevPath = DevPath;\r
UefiDevicePathLibCatPrint (\r
for (Index = 0; Index < sizeof (ISCSIDevPath->Lun) / sizeof (UINT8); Index++) {\r
UefiDevicePathLibCatPrint (Str, L"%02x", ((UINT8 *)&ISCSIDevPath->Lun)[Index]);\r
}\r
+\r
Options = ISCSIDevPath->LoginOption;\r
UefiDevicePathLibCatPrint (Str, L",%s,", (((Options >> 1) & 0x0001) != 0) ? L"CRC32C" : L"None");\r
UefiDevicePathLibCatPrint (Str, L"%s,", (((Options >> 3) & 0x0001) != 0) ? L"CRC32C" : L"None");\r
UefiDevicePathLibCatPrint (Str, L"%s,", L"CHAP_UNI");\r
} else {\r
UefiDevicePathLibCatPrint (Str, L"%s,", L"CHAP_BI");\r
-\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L"%s)", (ISCSIDevPath->NetworkProtocol == 0) ? L"TCP" : L"reserved");\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- WIFI_DEVICE_PATH *WiFi;\r
- UINT8 SSId[33];\r
+ WIFI_DEVICE_PATH *WiFi;\r
+ UINT8 SSId[33];\r
\r
WiFi = DevPath;\r
\r
UINT32 DnsServerIpCount;\r
UINT32 DnsServerIpIndex;\r
\r
- DnsDevPath = DevPath;\r
- DnsServerIpCount = (UINT32) (DevicePathNodeLength(DnsDevPath) - sizeof (EFI_DEVICE_PATH_PROTOCOL) - sizeof (DnsDevPath->IsIPv6)) / sizeof (EFI_IP_ADDRESS);\r
+ DnsDevPath = DevPath;\r
+ DnsServerIpCount = (UINT32)(DevicePathNodeLength (DnsDevPath) - sizeof (EFI_DEVICE_PATH_PROTOCOL) - sizeof (DnsDevPath->IsIPv6)) / sizeof (EFI_IP_ADDRESS);\r
\r
UefiDevicePathLibCatPrint (Str, L"Dns(");\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- URI_DEVICE_PATH *Uri;\r
- UINTN UriLength;\r
- CHAR8 *UriStr;\r
+ URI_DEVICE_PATH *Uri;\r
+ UINTN UriLength;\r
+ CHAR8 *UriStr;\r
\r
//\r
// Uri in the device path may not be null terminated.\r
//\r
Uri = DevPath;\r
UriLength = DevicePathNodeLength (Uri) - sizeof (URI_DEVICE_PATH);\r
- UriStr = AllocatePool (UriLength + 1);\r
+ UriStr = AllocatePool (UriLength + 1);\r
ASSERT (UriStr != NULL);\r
\r
CopyMem (UriStr, Uri->Uri, UriLength);\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- HARDDRIVE_DEVICE_PATH *Hd;\r
+ HARDDRIVE_DEVICE_PATH *Hd;\r
\r
Hd = DevPath;\r
switch (Hd->SignatureType) {\r
- case SIGNATURE_TYPE_MBR:\r
- UefiDevicePathLibCatPrint (\r
- Str,\r
- L"HD(%d,%s,0x%08x,",\r
- Hd->PartitionNumber,\r
- L"MBR",\r
- *((UINT32 *) (&(Hd->Signature[0])))\r
- );\r
- break;\r
+ case SIGNATURE_TYPE_MBR:\r
+ UefiDevicePathLibCatPrint (\r
+ Str,\r
+ L"HD(%d,%s,0x%08x,",\r
+ Hd->PartitionNumber,\r
+ L"MBR",\r
+ *((UINT32 *)(&(Hd->Signature[0])))\r
+ );\r
+ break;\r
\r
- case SIGNATURE_TYPE_GUID:\r
- UefiDevicePathLibCatPrint (\r
- Str,\r
- L"HD(%d,%s,%g,",\r
- Hd->PartitionNumber,\r
- L"GPT",\r
- (EFI_GUID *) &(Hd->Signature[0])\r
- );\r
- break;\r
+ case SIGNATURE_TYPE_GUID:\r
+ UefiDevicePathLibCatPrint (\r
+ Str,\r
+ L"HD(%d,%s,%g,",\r
+ Hd->PartitionNumber,\r
+ L"GPT",\r
+ (EFI_GUID *)&(Hd->Signature[0])\r
+ );\r
+ break;\r
\r
- default:\r
- UefiDevicePathLibCatPrint (\r
- Str,\r
- L"HD(%d,%d,0,",\r
- Hd->PartitionNumber,\r
- Hd->SignatureType\r
- );\r
- break;\r
+ default:\r
+ UefiDevicePathLibCatPrint (\r
+ Str,\r
+ L"HD(%d,%d,0,",\r
+ Hd->PartitionNumber,\r
+ Hd->SignatureType\r
+ );\r
+ break;\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L"0x%lx,0x%lx)", Hd->PartitionStart, Hd->PartitionSize);\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- CDROM_DEVICE_PATH *Cd;\r
+ CDROM_DEVICE_PATH *Cd;\r
\r
Cd = DevPath;\r
if (DisplayOnly) {\r
UefiDevicePathLibCatPrint (Str, L"CDROM(0x%x)", Cd->BootEntry);\r
- return ;\r
+ return;\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L"CDROM(0x%x,0x%lx,0x%lx)", Cd->BootEntry, Cd->PartitionStart, Cd->PartitionSize);\r
**/\r
VOID\r
DevPathRelativeOffsetRange (\r
- IN OUT POOL_PRINT *Str,\r
- IN VOID *DevPath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN OUT POOL_PRINT *Str,\r
+ IN VOID *DevPath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
- MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset;\r
+ MEDIA_RELATIVE_OFFSET_RANGE_DEVICE_PATH *Offset;\r
\r
Offset = DevPath;\r
UefiDevicePathLibCatPrint (\r
**/\r
VOID\r
DevPathToTextRamDisk (\r
- IN OUT POOL_PRINT *Str,\r
- IN VOID *DevPath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN OUT POOL_PRINT *Str,\r
+ IN VOID *DevPath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
- MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
+ MEDIA_RAM_DISK_DEVICE_PATH *RamDisk;\r
\r
RamDisk = DevPath;\r
\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- BBS_BBS_DEVICE_PATH *Bbs;\r
- CHAR16 *Type;\r
+ BBS_BBS_DEVICE_PATH *Bbs;\r
+ CHAR16 *Type;\r
\r
Bbs = DevPath;\r
switch (Bbs->DeviceType) {\r
- case BBS_TYPE_FLOPPY:\r
- Type = L"Floppy";\r
- break;\r
+ case BBS_TYPE_FLOPPY:\r
+ Type = L"Floppy";\r
+ break;\r
\r
- case BBS_TYPE_HARDDRIVE:\r
- Type = L"HD";\r
- break;\r
+ case BBS_TYPE_HARDDRIVE:\r
+ Type = L"HD";\r
+ break;\r
\r
- case BBS_TYPE_CDROM:\r
- Type = L"CDROM";\r
- break;\r
+ case BBS_TYPE_CDROM:\r
+ Type = L"CDROM";\r
+ break;\r
\r
- case BBS_TYPE_PCMCIA:\r
- Type = L"PCMCIA";\r
- break;\r
+ case BBS_TYPE_PCMCIA:\r
+ Type = L"PCMCIA";\r
+ break;\r
\r
- case BBS_TYPE_USB:\r
- Type = L"USB";\r
- break;\r
+ case BBS_TYPE_USB:\r
+ Type = L"USB";\r
+ break;\r
\r
- case BBS_TYPE_EMBEDDED_NETWORK:\r
- Type = L"Network";\r
- break;\r
+ case BBS_TYPE_EMBEDDED_NETWORK:\r
+ Type = L"Network";\r
+ break;\r
\r
- default:\r
- Type = NULL;\r
- break;\r
+ default:\r
+ Type = NULL;\r
+ break;\r
}\r
\r
if (Type != NULL) {\r
\r
if (DisplayOnly) {\r
UefiDevicePathLibCatPrint (Str, L")");\r
- return ;\r
+ return;\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L",0x%x)", Bbs->StatusFlag);\r
UefiDevicePathLibCatPrint (Str, L",");\r
}\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED const DEVICE_PATH_TO_TEXT_GENERIC_TABLE mUefiDevicePathLibToTextTableGeneric[] = {\r
- {HARDWARE_DEVICE_PATH, L"HardwarePath" },\r
- {ACPI_DEVICE_PATH, L"AcpiPath" },\r
- {MESSAGING_DEVICE_PATH, L"Msg" },\r
- {MEDIA_DEVICE_PATH, L"MediaPath" },\r
- {BBS_DEVICE_PATH, L"BbsPath" },\r
- {0, NULL}\r
+GLOBAL_REMOVE_IF_UNREFERENCED const DEVICE_PATH_TO_TEXT_GENERIC_TABLE mUefiDevicePathLibToTextTableGeneric[] = {\r
+ { HARDWARE_DEVICE_PATH, L"HardwarePath" },\r
+ { ACPI_DEVICE_PATH, L"AcpiPath" },\r
+ { MESSAGING_DEVICE_PATH, L"Msg" },\r
+ { MEDIA_DEVICE_PATH, L"MediaPath" },\r
+ { BBS_DEVICE_PATH, L"BbsPath" },\r
+ { 0, NULL }\r
};\r
\r
/**\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- EFI_DEVICE_PATH_PROTOCOL *Node;\r
- UINTN Index;\r
+ EFI_DEVICE_PATH_PROTOCOL *Node;\r
+ UINTN Index;\r
\r
Node = DevPath;\r
\r
Index = sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
if (Index < DevicePathNodeLength (Node)) {\r
UefiDevicePathLibCatPrint (Str, L",");\r
- for (; Index < DevicePathNodeLength (Node); Index++) {\r
- UefiDevicePathLibCatPrint (Str, L"%02x", ((UINT8 *) Node)[Index]);\r
+ for ( ; Index < DevicePathNodeLength (Node); Index++) {\r
+ UefiDevicePathLibCatPrint (Str, L"%02x", ((UINT8 *)Node)[Index]);\r
}\r
}\r
\r
UefiDevicePathLibCatPrint (Str, L")");\r
}\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED const DEVICE_PATH_TO_TEXT_TABLE mUefiDevicePathLibToTextTable[] = {\r
- {HARDWARE_DEVICE_PATH, HW_PCI_DP, DevPathToTextPci },\r
- {HARDWARE_DEVICE_PATH, HW_PCCARD_DP, DevPathToTextPccard },\r
- {HARDWARE_DEVICE_PATH, HW_MEMMAP_DP, DevPathToTextMemMap },\r
- {HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DevPathToTextVendor },\r
- {HARDWARE_DEVICE_PATH, HW_CONTROLLER_DP, DevPathToTextController },\r
- {HARDWARE_DEVICE_PATH, HW_BMC_DP, DevPathToTextBmc },\r
- {ACPI_DEVICE_PATH, ACPI_DP, DevPathToTextAcpi },\r
- {ACPI_DEVICE_PATH, ACPI_EXTENDED_DP, DevPathToTextAcpiEx },\r
- {ACPI_DEVICE_PATH, ACPI_ADR_DP, DevPathToTextAcpiAdr },\r
- {MESSAGING_DEVICE_PATH, MSG_ATAPI_DP, DevPathToTextAtapi },\r
- {MESSAGING_DEVICE_PATH, MSG_SCSI_DP, DevPathToTextScsi },\r
- {MESSAGING_DEVICE_PATH, MSG_FIBRECHANNEL_DP, DevPathToTextFibre },\r
- {MESSAGING_DEVICE_PATH, MSG_FIBRECHANNELEX_DP, DevPathToTextFibreEx },\r
- {MESSAGING_DEVICE_PATH, MSG_SASEX_DP, DevPathToTextSasEx },\r
- {MESSAGING_DEVICE_PATH, MSG_NVME_NAMESPACE_DP, DevPathToTextNVMe },\r
- {MESSAGING_DEVICE_PATH, MSG_UFS_DP, DevPathToTextUfs },\r
- {MESSAGING_DEVICE_PATH, MSG_SD_DP, DevPathToTextSd },\r
- {MESSAGING_DEVICE_PATH, MSG_EMMC_DP, DevPathToTextEmmc },\r
- {MESSAGING_DEVICE_PATH, MSG_1394_DP, DevPathToText1394 },\r
- {MESSAGING_DEVICE_PATH, MSG_USB_DP, DevPathToTextUsb },\r
- {MESSAGING_DEVICE_PATH, MSG_USB_WWID_DP, DevPathToTextUsbWWID },\r
- {MESSAGING_DEVICE_PATH, MSG_DEVICE_LOGICAL_UNIT_DP, DevPathToTextLogicalUnit },\r
- {MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, DevPathToTextUsbClass },\r
- {MESSAGING_DEVICE_PATH, MSG_SATA_DP, DevPathToTextSata },\r
- {MESSAGING_DEVICE_PATH, MSG_I2O_DP, DevPathToTextI2O },\r
- {MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP, DevPathToTextMacAddr },\r
- {MESSAGING_DEVICE_PATH, MSG_IPv4_DP, DevPathToTextIPv4 },\r
- {MESSAGING_DEVICE_PATH, MSG_IPv6_DP, DevPathToTextIPv6 },\r
- {MESSAGING_DEVICE_PATH, MSG_INFINIBAND_DP, DevPathToTextInfiniBand },\r
- {MESSAGING_DEVICE_PATH, MSG_UART_DP, DevPathToTextUart },\r
- {MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, DevPathToTextVendor },\r
- {MESSAGING_DEVICE_PATH, MSG_ISCSI_DP, DevPathToTextiSCSI },\r
- {MESSAGING_DEVICE_PATH, MSG_VLAN_DP, DevPathToTextVlan },\r
- {MESSAGING_DEVICE_PATH, MSG_DNS_DP, DevPathToTextDns },\r
- {MESSAGING_DEVICE_PATH, MSG_URI_DP, DevPathToTextUri },\r
- {MESSAGING_DEVICE_PATH, MSG_BLUETOOTH_DP, DevPathToTextBluetooth },\r
- {MESSAGING_DEVICE_PATH, MSG_WIFI_DP, DevPathToTextWiFi },\r
- {MESSAGING_DEVICE_PATH, MSG_BLUETOOTH_LE_DP, DevPathToTextBluetoothLE },\r
- {MEDIA_DEVICE_PATH, MEDIA_HARDDRIVE_DP, DevPathToTextHardDrive },\r
- {MEDIA_DEVICE_PATH, MEDIA_CDROM_DP, DevPathToTextCDROM },\r
- {MEDIA_DEVICE_PATH, MEDIA_VENDOR_DP, DevPathToTextVendor },\r
- {MEDIA_DEVICE_PATH, MEDIA_PROTOCOL_DP, DevPathToTextMediaProtocol },\r
- {MEDIA_DEVICE_PATH, MEDIA_FILEPATH_DP, DevPathToTextFilePath },\r
- {MEDIA_DEVICE_PATH, MEDIA_PIWG_FW_VOL_DP, DevPathToTextFv },\r
- {MEDIA_DEVICE_PATH, MEDIA_PIWG_FW_FILE_DP, DevPathToTextFvFile },\r
- {MEDIA_DEVICE_PATH, MEDIA_RELATIVE_OFFSET_RANGE_DP, DevPathRelativeOffsetRange },\r
- {MEDIA_DEVICE_PATH, MEDIA_RAM_DISK_DP, DevPathToTextRamDisk },\r
- {BBS_DEVICE_PATH, BBS_BBS_DP, DevPathToTextBBS },\r
- {END_DEVICE_PATH_TYPE, END_INSTANCE_DEVICE_PATH_SUBTYPE, DevPathToTextEndInstance },\r
- {0, 0, NULL}\r
+GLOBAL_REMOVE_IF_UNREFERENCED const DEVICE_PATH_TO_TEXT_TABLE mUefiDevicePathLibToTextTable[] = {\r
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, DevPathToTextPci },\r
+ { HARDWARE_DEVICE_PATH, HW_PCCARD_DP, DevPathToTextPccard },\r
+ { HARDWARE_DEVICE_PATH, HW_MEMMAP_DP, DevPathToTextMemMap },\r
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DevPathToTextVendor },\r
+ { HARDWARE_DEVICE_PATH, HW_CONTROLLER_DP, DevPathToTextController },\r
+ { HARDWARE_DEVICE_PATH, HW_BMC_DP, DevPathToTextBmc },\r
+ { ACPI_DEVICE_PATH, ACPI_DP, DevPathToTextAcpi },\r
+ { ACPI_DEVICE_PATH, ACPI_EXTENDED_DP, DevPathToTextAcpiEx },\r
+ { ACPI_DEVICE_PATH, ACPI_ADR_DP, DevPathToTextAcpiAdr },\r
+ { MESSAGING_DEVICE_PATH, MSG_ATAPI_DP, DevPathToTextAtapi },\r
+ { MESSAGING_DEVICE_PATH, MSG_SCSI_DP, DevPathToTextScsi },\r
+ { MESSAGING_DEVICE_PATH, MSG_FIBRECHANNEL_DP, DevPathToTextFibre },\r
+ { MESSAGING_DEVICE_PATH, MSG_FIBRECHANNELEX_DP, DevPathToTextFibreEx },\r
+ { MESSAGING_DEVICE_PATH, MSG_SASEX_DP, DevPathToTextSasEx },\r
+ { MESSAGING_DEVICE_PATH, MSG_NVME_NAMESPACE_DP, DevPathToTextNVMe },\r
+ { MESSAGING_DEVICE_PATH, MSG_UFS_DP, DevPathToTextUfs },\r
+ { MESSAGING_DEVICE_PATH, MSG_SD_DP, DevPathToTextSd },\r
+ { MESSAGING_DEVICE_PATH, MSG_EMMC_DP, DevPathToTextEmmc },\r
+ { MESSAGING_DEVICE_PATH, MSG_1394_DP, DevPathToText1394 },\r
+ { MESSAGING_DEVICE_PATH, MSG_USB_DP, DevPathToTextUsb },\r
+ { MESSAGING_DEVICE_PATH, MSG_USB_WWID_DP, DevPathToTextUsbWWID },\r
+ { MESSAGING_DEVICE_PATH, MSG_DEVICE_LOGICAL_UNIT_DP, DevPathToTextLogicalUnit },\r
+ { MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, DevPathToTextUsbClass },\r
+ { MESSAGING_DEVICE_PATH, MSG_SATA_DP, DevPathToTextSata },\r
+ { MESSAGING_DEVICE_PATH, MSG_I2O_DP, DevPathToTextI2O },\r
+ { MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP, DevPathToTextMacAddr },\r
+ { MESSAGING_DEVICE_PATH, MSG_IPv4_DP, DevPathToTextIPv4 },\r
+ { MESSAGING_DEVICE_PATH, MSG_IPv6_DP, DevPathToTextIPv6 },\r
+ { MESSAGING_DEVICE_PATH, MSG_INFINIBAND_DP, DevPathToTextInfiniBand },\r
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DevPathToTextUart },\r
+ { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, DevPathToTextVendor },\r
+ { MESSAGING_DEVICE_PATH, MSG_ISCSI_DP, DevPathToTextiSCSI },\r
+ { MESSAGING_DEVICE_PATH, MSG_VLAN_DP, DevPathToTextVlan },\r
+ { MESSAGING_DEVICE_PATH, MSG_DNS_DP, DevPathToTextDns },\r
+ { MESSAGING_DEVICE_PATH, MSG_URI_DP, DevPathToTextUri },\r
+ { MESSAGING_DEVICE_PATH, MSG_BLUETOOTH_DP, DevPathToTextBluetooth },\r
+ { MESSAGING_DEVICE_PATH, MSG_WIFI_DP, DevPathToTextWiFi },\r
+ { MESSAGING_DEVICE_PATH, MSG_BLUETOOTH_LE_DP, DevPathToTextBluetoothLE },\r
+ { MEDIA_DEVICE_PATH, MEDIA_HARDDRIVE_DP, DevPathToTextHardDrive },\r
+ { MEDIA_DEVICE_PATH, MEDIA_CDROM_DP, DevPathToTextCDROM },\r
+ { MEDIA_DEVICE_PATH, MEDIA_VENDOR_DP, DevPathToTextVendor },\r
+ { MEDIA_DEVICE_PATH, MEDIA_PROTOCOL_DP, DevPathToTextMediaProtocol },\r
+ { MEDIA_DEVICE_PATH, MEDIA_FILEPATH_DP, DevPathToTextFilePath },\r
+ { MEDIA_DEVICE_PATH, MEDIA_PIWG_FW_VOL_DP, DevPathToTextFv },\r
+ { MEDIA_DEVICE_PATH, MEDIA_PIWG_FW_FILE_DP, DevPathToTextFvFile },\r
+ { MEDIA_DEVICE_PATH, MEDIA_RELATIVE_OFFSET_RANGE_DP, DevPathRelativeOffsetRange },\r
+ { MEDIA_DEVICE_PATH, MEDIA_RAM_DISK_DP, DevPathToTextRamDisk },\r
+ { BBS_DEVICE_PATH, BBS_BBS_DP, DevPathToTextBBS },\r
+ { END_DEVICE_PATH_TYPE, END_INSTANCE_DEVICE_PATH_SUBTYPE, DevPathToTextEndInstance },\r
+ { 0, 0, NULL }\r
};\r
\r
/**\r
IN BOOLEAN AllowShortcuts\r
)\r
{\r
- POOL_PRINT Str;\r
- UINTN Index;\r
- DEVICE_PATH_TO_TEXT ToText;\r
+ POOL_PRINT Str;\r
+ UINTN Index;\r
+ DEVICE_PATH_TO_TEXT ToText;\r
\r
if (DeviceNode == NULL) {\r
return NULL;\r
//\r
ToText = DevPathToTextNodeGeneric;\r
for (Index = 0; mUefiDevicePathLibToTextTable[Index].Function != NULL; Index++) {\r
- if (DevicePathType (DeviceNode) == mUefiDevicePathLibToTextTable[Index].Type &&\r
- DevicePathSubType (DeviceNode) == mUefiDevicePathLibToTextTable[Index].SubType\r
- ) {\r
+ if ((DevicePathType (DeviceNode) == mUefiDevicePathLibToTextTable[Index].Type) &&\r
+ (DevicePathSubType (DeviceNode) == mUefiDevicePathLibToTextTable[Index].SubType)\r
+ )\r
+ {\r
ToText = mUefiDevicePathLibToTextTable[Index].Function;\r
break;\r
}\r
//\r
// Print this node\r
//\r
- ToText (&Str, (VOID *) DeviceNode, DisplayOnly, AllowShortcuts);\r
+ ToText (&Str, (VOID *)DeviceNode, DisplayOnly, AllowShortcuts);\r
\r
ASSERT (Str.Str != NULL);\r
return Str.Str;\r
CHAR16 *\r
EFIAPI\r
UefiDevicePathLibConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
- POOL_PRINT Str;\r
- EFI_DEVICE_PATH_PROTOCOL *Node;\r
- EFI_DEVICE_PATH_PROTOCOL *AlignedNode;\r
- UINTN Index;\r
- DEVICE_PATH_TO_TEXT ToText;\r
+ POOL_PRINT Str;\r
+ EFI_DEVICE_PATH_PROTOCOL *Node;\r
+ EFI_DEVICE_PATH_PROTOCOL *AlignedNode;\r
+ UINTN Index;\r
+ DEVICE_PATH_TO_TEXT ToText;\r
\r
if (DevicePath == NULL) {\r
return NULL;\r
//\r
// Process each device path node\r
//\r
- Node = (EFI_DEVICE_PATH_PROTOCOL *) DevicePath;\r
+ Node = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;\r
while (!IsDevicePathEnd (Node)) {\r
//\r
// Find the handler to dump this device path node\r
//\r
ToText = DevPathToTextNodeGeneric;\r
for (Index = 0; mUefiDevicePathLibToTextTable[Index].Function != NULL; Index += 1) {\r
-\r
- if (DevicePathType (Node) == mUefiDevicePathLibToTextTable[Index].Type &&\r
- DevicePathSubType (Node) == mUefiDevicePathLibToTextTable[Index].SubType\r
- ) {\r
+ if ((DevicePathType (Node) == mUefiDevicePathLibToTextTable[Index].Type) &&\r
+ (DevicePathSubType (Node) == mUefiDevicePathLibToTextTable[Index].SubType)\r
+ )\r
+ {\r
ToText = mUefiDevicePathLibToTextTable[Index].Function;\r
break;\r
}\r
}\r
+\r
//\r
// Put a path separator in if needed\r
//\r
BOOLEAN\r
EFIAPI\r
IsDevicePathValid (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN UINTN MaxSize\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINTN MaxSize\r
)\r
{\r
- UINTN Count;\r
- UINTN Size;\r
- UINTN NodeLength;\r
+ UINTN Count;\r
+ UINTN Size;\r
+ UINTN NodeLength;\r
\r
//\r
- //Validate the input whether exists and its size big enough to touch the first node\r
+ // Validate the input whether exists and its size big enough to touch the first node\r
//\r
- if (DevicePath == NULL || (MaxSize > 0 && MaxSize < END_DEVICE_PATH_LENGTH)) {\r
+ if ((DevicePath == NULL) || ((MaxSize > 0) && (MaxSize < END_DEVICE_PATH_LENGTH))) {\r
return FALSE;\r
}\r
\r
if (NodeLength > MAX_UINTN - Size) {\r
return FALSE;\r
}\r
+\r
Size += NodeLength;\r
\r
//\r
//\r
// FilePath must be a NULL-terminated string.\r
//\r
- if (DevicePathType (DevicePath) == MEDIA_DEVICE_PATH &&\r
- DevicePathSubType (DevicePath) == MEDIA_FILEPATH_DP &&\r
- *(CHAR16 *)((UINT8 *)DevicePath + NodeLength - 2) != 0) {\r
+ if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&\r
+ (DevicePathSubType (DevicePath) == MEDIA_FILEPATH_DP) &&\r
+ (*(CHAR16 *)((UINT8 *)DevicePath + NodeLength - 2) != 0))\r
+ {\r
return FALSE;\r
}\r
}\r
//\r
// Only return TRUE when the End Device Path node is valid.\r
//\r
- return (BOOLEAN) (DevicePathNodeLength (DevicePath) == END_DEVICE_PATH_LENGTH);\r
+ return (BOOLEAN)(DevicePathNodeLength (DevicePath) == END_DEVICE_PATH_LENGTH);\r
}\r
\r
-\r
/**\r
Returns the Type field of a device path node.\r
\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength(Node));\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength (Node));\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (DevicePathType (Node) == END_DEVICE_PATH_TYPE);\r
+ return (BOOLEAN)(DevicePathType (Node) == END_DEVICE_PATH_TYPE);\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (IsDevicePathEndType (Node) && DevicePathSubType(Node) == END_ENTIRE_DEVICE_PATH_SUBTYPE);\r
+ return (BOOLEAN)(IsDevicePathEndType (Node) && DevicePathSubType (Node) == END_ENTIRE_DEVICE_PATH_SUBTYPE);\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (IsDevicePathEndType (Node) && DevicePathSubType(Node) == END_INSTANCE_DEVICE_PATH_SUBTYPE);\r
+ return (BOOLEAN)(IsDevicePathEndType (Node) && DevicePathSubType (Node) == END_INSTANCE_DEVICE_PATH_SUBTYPE);\r
}\r
\r
/**\r
//\r
// Compute the size and add back in the size of the end device path structure\r
//\r
- return ((UINTN) DevicePath - (UINTN) Start) + DevicePathNodeLength (DevicePath);\r
+ return ((UINTN)DevicePath - (UINTN)Start) + DevicePathNodeLength (DevicePath);\r
}\r
\r
/**\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
)\r
{\r
- UINTN Size;\r
+ UINTN Size;\r
\r
//\r
// Compute the size\r
// Allocate space for the combined device path. It only has one end node of\r
// length EFI_DEVICE_PATH_PROTOCOL.\r
//\r
- Size1 = GetDevicePathSize (FirstDevicePath);\r
- Size2 = GetDevicePathSize (SecondDevicePath);\r
- Size = Size1 + Size2 - END_DEVICE_PATH_LENGTH;\r
+ Size1 = GetDevicePathSize (FirstDevicePath);\r
+ Size2 = GetDevicePathSize (SecondDevicePath);\r
+ Size = Size1 + Size2 - END_DEVICE_PATH_LENGTH;\r
\r
NewDevicePath = AllocatePool (Size);\r
\r
//\r
// Over write FirstDevicePath EndNode and do the copy\r
//\r
- DevicePath2 = (EFI_DEVICE_PATH_PROTOCOL *) ((CHAR8 *) NewDevicePath +\r
- (Size1 - END_DEVICE_PATH_LENGTH));\r
+ DevicePath2 = (EFI_DEVICE_PATH_PROTOCOL *)((CHAR8 *)NewDevicePath +\r
+ (Size1 - END_DEVICE_PATH_LENGTH));\r
CopyMem (DevicePath2, SecondDevicePath, Size2);\r
}\r
\r
if (DevicePathNode == NULL) {\r
return DuplicateDevicePath ((DevicePath != NULL) ? DevicePath : &mUefiDevicePathLibEndDevicePath);\r
}\r
+\r
//\r
// Build a Node that has a terminator on it\r
//\r
if (TempDevicePath == NULL) {\r
return NULL;\r
}\r
+\r
TempDevicePath = CopyMem (TempDevicePath, DevicePathNode, NodeLength);\r
//\r
// Add and end device path node to convert Node to device path\r
return NULL;\r
}\r
\r
- SrcSize = GetDevicePathSize (DevicePath);\r
- InstanceSize = GetDevicePathSize (DevicePathInstance);\r
+ SrcSize = GetDevicePathSize (DevicePath);\r
+ InstanceSize = GetDevicePathSize (DevicePathInstance);\r
\r
NewDevicePath = AllocatePool (SrcSize + InstanceSize);\r
if (NewDevicePath != NULL) {\r
-\r
- TempDevicePath = CopyMem (NewDevicePath, DevicePath, SrcSize);;\r
+ TempDevicePath = CopyMem (NewDevicePath, DevicePath, SrcSize);\r
\r
while (!IsDevicePathEnd (TempDevicePath)) {\r
TempDevicePath = NextDevicePathNode (TempDevicePath);\r
}\r
\r
- TempDevicePath->SubType = END_INSTANCE_DEVICE_PATH_SUBTYPE;\r
- TempDevicePath = NextDevicePathNode (TempDevicePath);\r
+ TempDevicePath->SubType = END_INSTANCE_DEVICE_PATH_SUBTYPE;\r
+ TempDevicePath = NextDevicePathNode (TempDevicePath);\r
CopyMem (TempDevicePath, DevicePathInstance, InstanceSize);\r
}\r
\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibGetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
)\r
{\r
EFI_DEVICE_PATH_PROTOCOL *DevPath;\r
\r
ASSERT (Size != NULL);\r
\r
- if (DevicePath == NULL || *DevicePath == NULL) {\r
+ if ((DevicePath == NULL) || (*DevicePath == NULL)) {\r
*Size = 0;\r
return NULL;\r
}\r
//\r
// Compute the size of the device path instance\r
//\r
- *Size = ((UINTN) DevPath - (UINTN) (*DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
+ *Size = ((UINTN)DevPath - (UINTN)(*DevicePath)) + sizeof (EFI_DEVICE_PATH_PROTOCOL);\r
\r
//\r
// Make a copy and return the device path instance\r
//\r
- Temp = DevPath->SubType;\r
- DevPath->SubType = END_ENTIRE_DEVICE_PATH_SUBTYPE;\r
- ReturnValue = DuplicateDevicePath (*DevicePath);\r
- DevPath->SubType = Temp;\r
+ Temp = DevPath->SubType;\r
+ DevPath->SubType = END_ENTIRE_DEVICE_PATH_SUBTYPE;\r
+ ReturnValue = DuplicateDevicePath (*DevicePath);\r
+ DevPath->SubType = Temp;\r
\r
//\r
// If DevPath is the end of an entire device path, then another instance\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibCreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
)\r
{\r
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
\r
if (NodeLength < sizeof (EFI_DEVICE_PATH_PROTOCOL)) {\r
//\r
\r
DevicePath = AllocateZeroPool (NodeLength);\r
if (DevicePath != NULL) {\r
- DevicePath->Type = NodeType;\r
- DevicePath->SubType = NodeSubType;\r
- SetDevicePathNodeLength (DevicePath, NodeLength);\r
+ DevicePath->Type = NodeType;\r
+ DevicePath->SubType = NodeSubType;\r
+ SetDevicePathNodeLength (DevicePath, NodeLength);\r
}\r
\r
return DevicePath;\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
)\r
{\r
- CONST EFI_DEVICE_PATH_PROTOCOL *Node;\r
+ CONST EFI_DEVICE_PATH_PROTOCOL *Node;\r
\r
if (DevicePath == NULL) {\r
return FALSE;\r
return FALSE;\r
}\r
\r
-\r
/**\r
Allocates a device path for a file and appends it to an existing device path.\r
\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
FileDevicePath (\r
- IN EFI_HANDLE Device OPTIONAL,\r
- IN CONST CHAR16 *FileName\r
+ IN EFI_HANDLE Device OPTIONAL,\r
+ IN CONST CHAR16 *FileName\r
)\r
{\r
UINTN Size;\r
\r
DevicePath = NULL;\r
\r
- Size = StrSize (FileName);\r
+ Size = StrSize (FileName);\r
FileDevicePath = AllocatePool (Size + SIZE_OF_FILEPATH_DEVICE_PATH + END_DEVICE_PATH_LENGTH);\r
if (FileDevicePath != NULL) {\r
- FilePath = (FILEPATH_DEVICE_PATH *) FileDevicePath;\r
+ FilePath = (FILEPATH_DEVICE_PATH *)FileDevicePath;\r
FilePath->Header.Type = MEDIA_DEVICE_PATH;\r
FilePath->Header.SubType = MEDIA_FILEPATH_DP;\r
CopyMem (&FilePath->PathName, FileName, Size);\r
\r
#include "UefiDevicePathLib.h"\r
\r
-\r
/**\r
Retrieves the device path protocol from a handle.\r
\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
DevicePathFromHandle (\r
- IN EFI_HANDLE Handle\r
+ IN EFI_HANDLE Handle\r
)\r
{\r
EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
Status = gBS->HandleProtocol (\r
Handle,\r
&gEfiDevicePathProtocolGuid,\r
- (VOID *) &DevicePath\r
+ (VOID *)&DevicePath\r
);\r
if (EFI_ERROR (Status)) {\r
DevicePath = NULL;\r
}\r
+\r
return DevicePath;\r
}\r
\r
#include "UefiDevicePathLib.h"\r
\r
-\r
/**\r
Retrieves the device path protocol from a handle.\r
\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
DevicePathFromHandle (\r
- IN EFI_HANDLE Handle\r
+ IN EFI_HANDLE Handle\r
)\r
{\r
return NULL;\r
\r
**/\r
\r
-\r
#include "UefiDevicePathLib.h"\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
GetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
)\r
{\r
return UefiDevicePathLibGetNextDevicePathInstance (DevicePath, Size);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
CreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
)\r
{\r
return UefiDevicePathLibCreateDeviceNode (NodeType, NodeSubType, NodeLength);\r
CHAR16 *\r
EFIAPI\r
ConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
return UefiDevicePathLibConvertDevicePathToText (DevicePath, DisplayOnly, AllowShortcuts);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
)\r
{\r
return UefiDevicePathLibConvertTextToDeviceNode (TextDeviceNode);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
)\r
{\r
return UefiDevicePathLibConvertTextToDevicePath (TextDevicePath);\r
#include <Library/PcdLib.h>\r
#include <IndustryStandard/Bluetooth.h>\r
\r
-#define IS_COMMA(a) ((a) == L',')\r
-#define IS_HYPHEN(a) ((a) == L'-')\r
-#define IS_DOT(a) ((a) == L'.')\r
-#define IS_LEFT_PARENTH(a) ((a) == L'(')\r
-#define IS_RIGHT_PARENTH(a) ((a) == L')')\r
-#define IS_SLASH(a) ((a) == L'/')\r
-#define IS_NULL(a) ((a) == L'\0')\r
-\r
+#define IS_COMMA(a) ((a) == L',')\r
+#define IS_HYPHEN(a) ((a) == L'-')\r
+#define IS_DOT(a) ((a) == L'.')\r
+#define IS_LEFT_PARENTH(a) ((a) == L'(')\r
+#define IS_RIGHT_PARENTH(a) ((a) == L')')\r
+#define IS_SLASH(a) ((a) == L'/')\r
+#define IS_NULL(a) ((a) == L'\0')\r
\r
//\r
// Private Data structure\r
//\r
typedef struct {\r
- CHAR16 *Str;\r
- UINTN Count;\r
- UINTN Capacity;\r
+ CHAR16 *Str;\r
+ UINTN Count;\r
+ UINTN Capacity;\r
} POOL_PRINT;\r
\r
typedef\r
EFI_DEVICE_PATH_PROTOCOL *\r
(*DEVICE_PATH_FROM_TEXT) (\r
- IN CHAR16 *Str\r
+ IN CHAR16 *Str\r
);\r
\r
typedef\r
);\r
\r
typedef struct {\r
- UINT8 Type;\r
- UINT8 SubType;\r
- DEVICE_PATH_TO_TEXT Function;\r
+ UINT8 Type;\r
+ UINT8 SubType;\r
+ DEVICE_PATH_TO_TEXT Function;\r
} DEVICE_PATH_TO_TEXT_TABLE;\r
\r
typedef struct {\r
- UINT8 Type;\r
- CHAR16 *Text;\r
+ UINT8 Type;\r
+ CHAR16 *Text;\r
} DEVICE_PATH_TO_TEXT_GENERIC_TABLE;\r
\r
typedef struct {\r
- CHAR16 *DevicePathNodeText;\r
- DEVICE_PATH_FROM_TEXT Function;\r
+ CHAR16 *DevicePathNodeText;\r
+ DEVICE_PATH_FROM_TEXT Function;\r
} DEVICE_PATH_FROM_TEXT_TABLE;\r
\r
typedef struct {\r
- BOOLEAN ClassExist;\r
- UINT8 Class;\r
- BOOLEAN SubClassExist;\r
- UINT8 SubClass;\r
+ BOOLEAN ClassExist;\r
+ UINT8 Class;\r
+ BOOLEAN SubClassExist;\r
+ UINT8 SubClass;\r
} USB_CLASS_TEXT;\r
\r
-#define USB_CLASS_AUDIO 1\r
-#define USB_CLASS_CDCCONTROL 2\r
-#define USB_CLASS_HID 3\r
-#define USB_CLASS_IMAGE 6\r
-#define USB_CLASS_PRINTER 7\r
-#define USB_CLASS_MASS_STORAGE 8\r
-#define USB_CLASS_HUB 9\r
-#define USB_CLASS_CDCDATA 10\r
-#define USB_CLASS_SMART_CARD 11\r
-#define USB_CLASS_VIDEO 14\r
-#define USB_CLASS_DIAGNOSTIC 220\r
-#define USB_CLASS_WIRELESS 224\r
-\r
-#define USB_CLASS_RESERVE 254\r
-#define USB_SUBCLASS_FW_UPDATE 1\r
-#define USB_SUBCLASS_IRDA_BRIDGE 2\r
-#define USB_SUBCLASS_TEST 3\r
-\r
-#define RFC_1700_UDP_PROTOCOL 17\r
-#define RFC_1700_TCP_PROTOCOL 6\r
+#define USB_CLASS_AUDIO 1\r
+#define USB_CLASS_CDCCONTROL 2\r
+#define USB_CLASS_HID 3\r
+#define USB_CLASS_IMAGE 6\r
+#define USB_CLASS_PRINTER 7\r
+#define USB_CLASS_MASS_STORAGE 8\r
+#define USB_CLASS_HUB 9\r
+#define USB_CLASS_CDCDATA 10\r
+#define USB_CLASS_SMART_CARD 11\r
+#define USB_CLASS_VIDEO 14\r
+#define USB_CLASS_DIAGNOSTIC 220\r
+#define USB_CLASS_WIRELESS 224\r
+\r
+#define USB_CLASS_RESERVE 254\r
+#define USB_SUBCLASS_FW_UPDATE 1\r
+#define USB_SUBCLASS_IRDA_BRIDGE 2\r
+#define USB_SUBCLASS_TEST 3\r
+\r
+#define RFC_1700_UDP_PROTOCOL 17\r
+#define RFC_1700_TCP_PROTOCOL 6\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- EFI_GUID Guid;\r
- UINT8 VendorDefinedData[1];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_GUID Guid;\r
+ UINT8 VendorDefinedData[1];\r
} VENDOR_DEFINED_HARDWARE_DEVICE_PATH;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- EFI_GUID Guid;\r
- UINT8 VendorDefinedData[1];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_GUID Guid;\r
+ UINT8 VendorDefinedData[1];\r
} VENDOR_DEFINED_MESSAGING_DEVICE_PATH;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- EFI_GUID Guid;\r
- UINT8 VendorDefinedData[1];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_GUID Guid;\r
+ UINT8 VendorDefinedData[1];\r
} VENDOR_DEFINED_MEDIA_DEVICE_PATH;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT32 Hid;\r
- UINT32 Uid;\r
- UINT32 Cid;\r
- CHAR8 HidUidCidStr[3];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT32 Hid;\r
+ UINT32 Uid;\r
+ UINT32 Cid;\r
+ CHAR8 HidUidCidStr[3];\r
} ACPI_EXTENDED_HID_DEVICE_PATH_WITH_STR;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- UINT16 NetworkProtocol;\r
- UINT16 LoginOption;\r
- UINT64 Lun;\r
- UINT16 TargetPortalGroupTag;\r
- CHAR8 TargetName[1];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ UINT16 NetworkProtocol;\r
+ UINT16 LoginOption;\r
+ UINT64 Lun;\r
+ UINT16 TargetPortalGroupTag;\r
+ CHAR8 TargetName[1];\r
} ISCSI_DEVICE_PATH_WITH_NAME;\r
\r
typedef struct {\r
- EFI_DEVICE_PATH_PROTOCOL Header;\r
- EFI_GUID Guid;\r
- UINT8 VendorDefinedData[1];\r
+ EFI_DEVICE_PATH_PROTOCOL Header;\r
+ EFI_GUID Guid;\r
+ UINT8 VendorDefinedData[1];\r
} VENDOR_DEVICE_PATH_WITH_DATA;\r
\r
#pragma pack()\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibGetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibCreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
);\r
\r
/**\r
IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath\r
);\r
\r
-\r
/**\r
Converts a device path to its text representation.\r
\r
CHAR16 *\r
EFIAPI\r
UefiDevicePathLibConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
);\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
UefiDevicePathLibConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
);\r
\r
#endif\r
\r
**/\r
\r
-\r
#include "UefiDevicePathLib.h"\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_UTILITIES_PROTOCOL *mDevicePathLibDevicePathUtilities = NULL;\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *mDevicePathLibDevicePathToText = NULL;\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *mDevicePathLibDevicePathFromText = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_UTILITIES_PROTOCOL *mDevicePathLibDevicePathUtilities = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *mDevicePathLibDevicePathToText = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *mDevicePathLibDevicePathFromText = NULL;\r
\r
/**\r
The constructor function caches the pointer to DevicePathUtilites protocol,\r
EFI_STATUS\r
EFIAPI\r
UefiDevicePathLibOptionalDevicePathProtocolConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->LocateProtocol (\r
&gEfiDevicePathUtilitiesProtocolGuid,\r
NULL,\r
- (VOID**) &mDevicePathLibDevicePathUtilities\r
+ (VOID **)&mDevicePathLibDevicePathUtilities\r
);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mDevicePathLibDevicePathUtilities != NULL);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
GetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
)\r
{\r
if (mDevicePathLibDevicePathUtilities != NULL) {\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
CreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
)\r
{\r
if (mDevicePathLibDevicePathUtilities != NULL) {\r
**/\r
VOID *\r
UefiDevicePathLibLocateProtocol (\r
- EFI_GUID *ProtocolGuid\r
+ EFI_GUID *ProtocolGuid\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *Protocol;\r
+ EFI_STATUS Status;\r
+ VOID *Protocol;\r
+\r
Status = gBS->LocateProtocol (\r
ProtocolGuid,\r
NULL,\r
- (VOID**) &Protocol\r
+ (VOID **)&Protocol\r
);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
if (mDevicePathLibDevicePathToText == NULL) {\r
mDevicePathLibDevicePathToText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathToTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathToText != NULL) {\r
return mDevicePathLibDevicePathToText->ConvertDeviceNodeToText (DeviceNode, DisplayOnly, AllowShortcuts);\r
}\r
CHAR16 *\r
EFIAPI\r
ConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
if (mDevicePathLibDevicePathToText == NULL) {\r
mDevicePathLibDevicePathToText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathToTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathToText != NULL) {\r
return mDevicePathLibDevicePathToText->ConvertDevicePathToText (DevicePath, DisplayOnly, AllowShortcuts);\r
}\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
)\r
{\r
if (mDevicePathLibDevicePathFromText == NULL) {\r
mDevicePathLibDevicePathFromText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathFromTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathFromText != NULL) {\r
return mDevicePathLibDevicePathFromText->ConvertTextToDeviceNode (TextDeviceNode);\r
}\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
)\r
{\r
if (mDevicePathLibDevicePathFromText == NULL) {\r
mDevicePathLibDevicePathFromText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathFromTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathFromText != NULL) {\r
return mDevicePathLibDevicePathFromText->ConvertTextToDevicePath (TextDevicePath);\r
}\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
\r
#include <Protocol/DevicePathUtilities.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/PcdLib.h>\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_UTILITIES_PROTOCOL *mDevicePathLibDevicePathUtilities = NULL;\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *mDevicePathLibDevicePathToText = NULL;\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *mDevicePathLibDevicePathFromText = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_UTILITIES_PROTOCOL *mDevicePathLibDevicePathUtilities = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *mDevicePathLibDevicePathToText = NULL;\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *mDevicePathLibDevicePathFromText = NULL;\r
\r
//\r
// Template for an end-of-device path node.\r
EFI_STATUS\r
EFIAPI\r
DevicePathLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->LocateProtocol (\r
&gEfiDevicePathUtilitiesProtocolGuid,\r
NULL,\r
- (VOID**) &mDevicePathLibDevicePathUtilities\r
+ (VOID **)&mDevicePathLibDevicePathUtilities\r
);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mDevicePathLibDevicePathUtilities != NULL);\r
BOOLEAN\r
EFIAPI\r
IsDevicePathValid (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN UINTN MaxSize\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN UINTN MaxSize\r
)\r
{\r
- UINTN Count;\r
- UINTN Size;\r
- UINTN NodeLength;\r
+ UINTN Count;\r
+ UINTN Size;\r
+ UINTN NodeLength;\r
\r
ASSERT (DevicePath != NULL);\r
\r
if (NodeLength > MAX_UINTN - Size) {\r
return FALSE;\r
}\r
+\r
Size += NodeLength;\r
\r
//\r
//\r
// FilePath must be a NULL-terminated string.\r
//\r
- if (DevicePathType (DevicePath) == MEDIA_DEVICE_PATH &&\r
- DevicePathSubType (DevicePath) == MEDIA_FILEPATH_DP &&\r
- *(CHAR16 *)((UINT8 *)DevicePath + NodeLength - 2) != 0) {\r
+ if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&\r
+ (DevicePathSubType (DevicePath) == MEDIA_FILEPATH_DP) &&\r
+ (*(CHAR16 *)((UINT8 *)DevicePath + NodeLength - 2) != 0))\r
+ {\r
return FALSE;\r
}\r
}\r
//\r
// Only return TRUE when the End Device Path node is valid.\r
//\r
- return (BOOLEAN) (DevicePathNodeLength (DevicePath) == END_DEVICE_PATH_LENGTH);\r
+ return (BOOLEAN)(DevicePathNodeLength (DevicePath) == END_DEVICE_PATH_LENGTH);\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength(Node));\r
+ return (EFI_DEVICE_PATH_PROTOCOL *)((UINT8 *)(Node) + DevicePathNodeLength (Node));\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (DevicePathType (Node) == END_DEVICE_PATH_TYPE);\r
+ return (BOOLEAN)(DevicePathType (Node) == END_DEVICE_PATH_TYPE);\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (IsDevicePathEndType (Node) && DevicePathSubType(Node) == END_ENTIRE_DEVICE_PATH_SUBTYPE);\r
+ return (BOOLEAN)(IsDevicePathEndType (Node) && DevicePathSubType (Node) == END_ENTIRE_DEVICE_PATH_SUBTYPE);\r
}\r
\r
/**\r
)\r
{\r
ASSERT (Node != NULL);\r
- return (BOOLEAN) (IsDevicePathEndType (Node) && DevicePathSubType(Node) == END_INSTANCE_DEVICE_PATH_SUBTYPE);\r
+ return (BOOLEAN)(IsDevicePathEndType (Node) && DevicePathSubType (Node) == END_INSTANCE_DEVICE_PATH_SUBTYPE);\r
}\r
\r
/**\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
GetNextDevicePathInstance (\r
- IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
- OUT UINTN *Size\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath,\r
+ OUT UINTN *Size\r
)\r
{\r
ASSERT (Size != NULL);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
CreateDeviceNode (\r
- IN UINT8 NodeType,\r
- IN UINT8 NodeSubType,\r
- IN UINT16 NodeLength\r
+ IN UINT8 NodeType,\r
+ IN UINT8 NodeSubType,\r
+ IN UINT16 NodeLength\r
)\r
{\r
return mDevicePathLibDevicePathUtilities->CreateDeviceNode (NodeType, NodeSubType, NodeLength);\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
DevicePathFromHandle (\r
- IN EFI_HANDLE Handle\r
+ IN EFI_HANDLE Handle\r
)\r
{\r
EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
Status = gBS->HandleProtocol (\r
Handle,\r
&gEfiDevicePathProtocolGuid,\r
- (VOID *) &DevicePath\r
+ (VOID *)&DevicePath\r
);\r
if (EFI_ERROR (Status)) {\r
DevicePath = NULL;\r
}\r
+\r
return DevicePath;\r
}\r
\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
FileDevicePath (\r
- IN EFI_HANDLE Device OPTIONAL,\r
- IN CONST CHAR16 *FileName\r
+ IN EFI_HANDLE Device OPTIONAL,\r
+ IN CONST CHAR16 *FileName\r
)\r
{\r
UINTN Size;\r
\r
DevicePath = NULL;\r
\r
- Size = StrSize (FileName);\r
+ Size = StrSize (FileName);\r
FileDevicePath = AllocatePool (Size + SIZE_OF_FILEPATH_DEVICE_PATH + END_DEVICE_PATH_LENGTH);\r
if (FileDevicePath != NULL) {\r
- FilePath = (FILEPATH_DEVICE_PATH *) FileDevicePath;\r
+ FilePath = (FILEPATH_DEVICE_PATH *)FileDevicePath;\r
FilePath->Header.Type = MEDIA_DEVICE_PATH;\r
FilePath->Header.SubType = MEDIA_FILEPATH_DP;\r
CopyMem (&FilePath->PathName, FileName, Size);\r
**/\r
VOID *\r
UefiDevicePathLibLocateProtocol (\r
- EFI_GUID *ProtocolGuid\r
+ EFI_GUID *ProtocolGuid\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *Protocol;\r
+ EFI_STATUS Status;\r
+ VOID *Protocol;\r
+\r
Status = gBS->LocateProtocol (\r
ProtocolGuid,\r
NULL,\r
- (VOID**) &Protocol\r
+ (VOID **)&Protocol\r
);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
if (mDevicePathLibDevicePathToText == NULL) {\r
mDevicePathLibDevicePathToText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathToTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathToText != NULL) {\r
return mDevicePathLibDevicePathToText->ConvertDeviceNodeToText (DeviceNode, DisplayOnly, AllowShortcuts);\r
} else {\r
CHAR16 *\r
EFIAPI\r
ConvertDevicePathToText (\r
- IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
- IN BOOLEAN DisplayOnly,\r
- IN BOOLEAN AllowShortcuts\r
+ IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r
+ IN BOOLEAN DisplayOnly,\r
+ IN BOOLEAN AllowShortcuts\r
)\r
{\r
if (mDevicePathLibDevicePathToText == NULL) {\r
mDevicePathLibDevicePathToText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathToTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathToText != NULL) {\r
return mDevicePathLibDevicePathToText->ConvertDevicePathToText (DevicePath, DisplayOnly, AllowShortcuts);\r
} else {\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDeviceNode (\r
- IN CONST CHAR16 *TextDeviceNode\r
+ IN CONST CHAR16 *TextDeviceNode\r
)\r
{\r
if (mDevicePathLibDevicePathFromText == NULL) {\r
mDevicePathLibDevicePathFromText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathFromTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathFromText != NULL) {\r
return mDevicePathLibDevicePathFromText->ConvertTextToDeviceNode (TextDeviceNode);\r
} else {\r
EFI_DEVICE_PATH_PROTOCOL *\r
EFIAPI\r
ConvertTextToDevicePath (\r
- IN CONST CHAR16 *TextDevicePath\r
+ IN CONST CHAR16 *TextDevicePath\r
)\r
{\r
if (mDevicePathLibDevicePathFromText == NULL) {\r
mDevicePathLibDevicePathFromText = UefiDevicePathLibLocateProtocol (&gEfiDevicePathFromTextProtocolGuid);\r
}\r
+\r
if (mDevicePathLibDevicePathFromText != NULL) {\r
return mDevicePathLibDevicePathFromText->ConvertTextToDevicePath (TextDevicePath);\r
} else {\r
\r
**/\r
\r
-\r
-\r
#include <Uefi.h>\r
\r
#include <Protocol/LoadedImage.h>\r
#include <Library/DebugLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
-\r
/**\r
Unloads an image from memory.\r
\r
EFI_STATUS\r
EFIAPI\r
_DriverUnloadHandler (\r
- EFI_HANDLE ImageHandle\r
+ EFI_HANDLE ImageHandle\r
)\r
{\r
EFI_STATUS Status;\r
return Status;\r
}\r
\r
-\r
/**\r
The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM\r
Driver, or UEFI Driver.\r
return Status;\r
}\r
\r
-\r
/**\r
Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().\r
\r
#include <Library/PcdLib.h>\r
#include <Library/PrintLib.h>\r
\r
-CONST UINT16 gUnicodeFileTag = EFI_UNICODE_BYTE_ORDER_MARK;\r
+CONST UINT16 gUnicodeFileTag = EFI_UNICODE_BYTE_ORDER_MARK;\r
\r
-#define MAX_FILE_NAME_LEN 522 // (20 * (6+5+2))+1) unicode characters from EFI FAT spec (doubled for bytes)\r
-#define FIND_XXXXX_FILE_BUFFER_SIZE (SIZE_OF_EFI_FILE_INFO + MAX_FILE_NAME_LEN)\r
+#define MAX_FILE_NAME_LEN 522// (20 * (6+5+2))+1) unicode characters from EFI FAT spec (doubled for bytes)\r
+#define FIND_XXXXX_FILE_BUFFER_SIZE (SIZE_OF_EFI_FILE_INFO + MAX_FILE_NAME_LEN)\r
\r
/**\r
This function will retrieve the information about the file for the handle\r
\r
@return the information about the file\r
**/\r
-EFI_FILE_INFO*\r
+EFI_FILE_INFO *\r
EFIAPI\r
FileHandleGetInfo (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
)\r
{\r
- EFI_FILE_INFO *FileInfo;\r
- UINTN FileInfoSize;\r
- EFI_STATUS Status;\r
+ EFI_FILE_INFO *FileInfo;\r
+ UINTN FileInfoSize;\r
+ EFI_STATUS Status;\r
\r
if (FileHandle == NULL) {\r
return (NULL);\r
// Get the required size to allocate\r
//\r
FileInfoSize = 0;\r
- FileInfo = NULL;\r
- Status = FileHandle->GetInfo(FileHandle,\r
+ FileInfo = NULL;\r
+ Status = FileHandle->GetInfo (\r
+ FileHandle,\r
&gEfiFileInfoGuid,\r
&FileInfoSize,\r
- NULL);\r
- if (Status == EFI_BUFFER_TOO_SMALL){\r
+ NULL\r
+ );\r
+ if (Status == EFI_BUFFER_TOO_SMALL) {\r
//\r
// error is expected. getting size to allocate\r
//\r
- FileInfo = AllocateZeroPool(FileInfoSize);\r
+ FileInfo = AllocateZeroPool (FileInfoSize);\r
if (FileInfo != NULL) {\r
//\r
// now get the information\r
//\r
- Status = FileHandle->GetInfo(FileHandle,\r
- &gEfiFileInfoGuid,\r
- &FileInfoSize,\r
- FileInfo);\r
+ Status = FileHandle->GetInfo (\r
+ FileHandle,\r
+ &gEfiFileInfoGuid,\r
+ &FileInfoSize,\r
+ FileInfo\r
+ );\r
//\r
// if we got an error free the memory and return NULL\r
//\r
- if (EFI_ERROR(Status)) {\r
- FreePool(FileInfo);\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool (FileInfo);\r
FileInfo = NULL;\r
}\r
}\r
}\r
+\r
return (FileInfo);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetInfo (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_FILE_INFO *FileInfo\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_FILE_INFO *FileInfo\r
)\r
{\r
-\r
- if (FileHandle == NULL || FileInfo == NULL) {\r
+ if ((FileHandle == NULL) || (FileInfo == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
//\r
// Set the info\r
//\r
- return (FileHandle->SetInfo(FileHandle,\r
- &gEfiFileInfoGuid,\r
- (UINTN)FileInfo->Size,\r
- (EFI_FILE_INFO*)FileInfo));\r
+ return (FileHandle->SetInfo (\r
+ FileHandle,\r
+ &gEfiFileInfoGuid,\r
+ (UINTN)FileInfo->Size,\r
+ (EFI_FILE_INFO *)FileInfo\r
+ ));\r
}\r
\r
/**\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleRead(\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN OUT UINTN *BufferSize,\r
- OUT VOID *Buffer\r
+FileHandleRead (\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN OUT UINTN *BufferSize,\r
+ OUT VOID *Buffer\r
)\r
{\r
if (FileHandle == NULL) {\r
//\r
// Perform the read based on EFI_FILE_PROTOCOL\r
//\r
- return (FileHandle->Read(FileHandle, BufferSize, Buffer));\r
+ return (FileHandle->Read (FileHandle, BufferSize, Buffer));\r
}\r
\r
-\r
/**\r
Write data to a file.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleWrite(\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN OUT UINTN *BufferSize,\r
- IN VOID *Buffer\r
+FileHandleWrite (\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN OUT UINTN *BufferSize,\r
+ IN VOID *Buffer\r
)\r
{\r
if (FileHandle == NULL) {\r
//\r
// Perform the write based on EFI_FILE_PROTOCOL\r
//\r
- return (FileHandle->Write(FileHandle, BufferSize, Buffer));\r
+ return (FileHandle->Write (FileHandle, BufferSize, Buffer));\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleClose (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (FileHandle == NULL) {\r
return (EFI_INVALID_PARAMETER);\r
//\r
// Perform the Close based on EFI_FILE_PROTOCOL\r
//\r
- Status = FileHandle->Close(FileHandle);\r
+ Status = FileHandle->Close (FileHandle);\r
return Status;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleDelete (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
if (FileHandle == NULL) {\r
return (EFI_INVALID_PARAMETER);\r
//\r
// Perform the Delete based on EFI_FILE_PROTOCOL\r
//\r
- Status = FileHandle->Delete(FileHandle);\r
+ Status = FileHandle->Delete (FileHandle);\r
return Status;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetPosition (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN UINT64 Position\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN UINT64 Position\r
)\r
{\r
if (FileHandle == NULL) {\r
//\r
// Perform the SetPosition based on EFI_FILE_PROTOCOL\r
//\r
- return (FileHandle->SetPosition(FileHandle, Position));\r
+ return (FileHandle->SetPosition (FileHandle, Position));\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetPosition (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- OUT UINT64 *Position\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ OUT UINT64 *Position\r
)\r
{\r
- if (Position == NULL || FileHandle == NULL) {\r
+ if ((Position == NULL) || (FileHandle == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
//\r
// Perform the GetPosition based on EFI_FILE_PROTOCOL\r
//\r
- return (FileHandle->GetPosition(FileHandle, Position));\r
+ return (FileHandle->GetPosition (FileHandle, Position));\r
}\r
+\r
/**\r
Flushes data on a file\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleFlush (\r
- IN EFI_FILE_HANDLE FileHandle\r
+ IN EFI_FILE_HANDLE FileHandle\r
)\r
{\r
if (FileHandle == NULL) {\r
//\r
// Perform the Flush based on EFI_FILE_PROTOCOL\r
//\r
- return (FileHandle->Flush(FileHandle));\r
+ return (FileHandle->Flush (FileHandle));\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FileHandleIsDirectory (\r
- IN EFI_FILE_HANDLE DirHandle\r
+ IN EFI_FILE_HANDLE DirHandle\r
)\r
{\r
- EFI_FILE_INFO *DirInfo;\r
+ EFI_FILE_INFO *DirInfo;\r
\r
if (DirHandle == NULL) {\r
return (EFI_INVALID_PARAMETER);\r
//\r
return (EFI_INVALID_PARAMETER);\r
}\r
+\r
if ((DirInfo->Attribute & EFI_FILE_DIRECTORY) == 0) {\r
//\r
// Attributes say this is not a directory\r
FreePool (DirInfo);\r
return (EFI_NOT_FOUND);\r
}\r
+\r
//\r
// all good...\r
//\r
EFI_STATUS\r
EFIAPI\r
FileHandleFindFirstFile (\r
- IN EFI_FILE_HANDLE DirHandle,\r
- OUT EFI_FILE_INFO **Buffer\r
+ IN EFI_FILE_HANDLE DirHandle,\r
+ OUT EFI_FILE_INFO **Buffer\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN BufferSize;\r
+ EFI_STATUS Status;\r
+ UINTN BufferSize;\r
\r
- if (Buffer == NULL || DirHandle == NULL) {\r
+ if ((Buffer == NULL) || (DirHandle == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
//\r
// verify that DirHandle is a directory\r
//\r
- Status = FileHandleIsDirectory(DirHandle);\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleIsDirectory (DirHandle);\r
+ if (EFI_ERROR (Status)) {\r
return (Status);\r
}\r
\r
// Allocate a buffer sized to struct size + enough for the string at the end\r
//\r
BufferSize = FIND_XXXXX_FILE_BUFFER_SIZE;\r
- *Buffer = AllocateZeroPool(BufferSize);\r
- if (*Buffer == NULL){\r
+ *Buffer = AllocateZeroPool (BufferSize);\r
+ if (*Buffer == NULL) {\r
return (EFI_OUT_OF_RESOURCES);\r
}\r
\r
//\r
// reset to the beginning of the directory\r
//\r
- Status = FileHandleSetPosition(DirHandle, 0);\r
- if (EFI_ERROR(Status)) {\r
- FreePool(*Buffer);\r
+ Status = FileHandleSetPosition (DirHandle, 0);\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool (*Buffer);\r
*Buffer = NULL;\r
return (Status);\r
}\r
// read in the info about the first file\r
//\r
Status = FileHandleRead (DirHandle, &BufferSize, *Buffer);\r
- ASSERT(Status != EFI_BUFFER_TOO_SMALL);\r
- if (EFI_ERROR(Status) || BufferSize == 0) {\r
- FreePool(*Buffer);\r
+ ASSERT (Status != EFI_BUFFER_TOO_SMALL);\r
+ if (EFI_ERROR (Status) || (BufferSize == 0)) {\r
+ FreePool (*Buffer);\r
*Buffer = NULL;\r
if (BufferSize == 0) {\r
return (EFI_NOT_FOUND);\r
}\r
+\r
return (Status);\r
}\r
+\r
return (EFI_SUCCESS);\r
}\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleFindNextFile(\r
- IN EFI_FILE_HANDLE DirHandle,\r
- OUT EFI_FILE_INFO *Buffer,\r
- OUT BOOLEAN *NoFile\r
+FileHandleFindNextFile (\r
+ IN EFI_FILE_HANDLE DirHandle,\r
+ OUT EFI_FILE_INFO *Buffer,\r
+ OUT BOOLEAN *NoFile\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN BufferSize;\r
+ EFI_STATUS Status;\r
+ UINTN BufferSize;\r
\r
- if (DirHandle == NULL || Buffer == NULL || NoFile == NULL) {\r
+ if ((DirHandle == NULL) || (Buffer == NULL) || (NoFile == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
// read in the info about the next file\r
//\r
Status = FileHandleRead (DirHandle, &BufferSize, Buffer);\r
- ASSERT(Status != EFI_BUFFER_TOO_SMALL);\r
- if (EFI_ERROR(Status)) {\r
+ ASSERT (Status != EFI_BUFFER_TOO_SMALL);\r
+ if (EFI_ERROR (Status)) {\r
return (Status);\r
}\r
\r
// If we read 0 bytes (but did not have erros) we already read in the last file.\r
//\r
if (BufferSize == 0) {\r
- FreePool(Buffer);\r
+ FreePool (Buffer);\r
*NoFile = TRUE;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetSize (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- OUT UINT64 *Size\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ OUT UINT64 *Size\r
)\r
{\r
- EFI_FILE_INFO *FileInfo;\r
+ EFI_FILE_INFO *FileInfo;\r
\r
- if (FileHandle == NULL || Size == NULL) {\r
+ if ((FileHandle == NULL) || (Size == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
//\r
// get the FileInfo structure\r
//\r
- FileInfo = FileHandleGetInfo(FileHandle);\r
+ FileInfo = FileHandleGetInfo (FileHandle);\r
if (FileInfo == NULL) {\r
return (EFI_DEVICE_ERROR);\r
}\r
//\r
// free the FileInfo memory\r
//\r
- FreePool(FileInfo);\r
+ FreePool (FileInfo);\r
\r
return (EFI_SUCCESS);\r
}\r
EFI_STATUS\r
EFIAPI\r
FileHandleSetSize (\r
- IN EFI_FILE_HANDLE FileHandle,\r
- IN UINT64 Size\r
+ IN EFI_FILE_HANDLE FileHandle,\r
+ IN UINT64 Size\r
)\r
{\r
- EFI_FILE_INFO *FileInfo;\r
- EFI_STATUS Status;\r
+ EFI_FILE_INFO *FileInfo;\r
+ EFI_STATUS Status;\r
\r
if (FileHandle == NULL) {\r
return (EFI_INVALID_PARAMETER);\r
//\r
// get the FileInfo structure\r
//\r
- FileInfo = FileHandleGetInfo(FileHandle);\r
+ FileInfo = FileHandleGetInfo (FileHandle);\r
if (FileInfo == NULL) {\r
return (EFI_DEVICE_ERROR);\r
}\r
//\r
FileInfo->FileSize = Size;\r
\r
- Status = FileHandleSetInfo(FileHandle, FileInfo);\r
+ Status = FileHandleSetInfo (FileHandle, FileInfo);\r
//\r
// free the FileInfo memory\r
//\r
- FreePool(FileInfo);\r
+ FreePool (FileInfo);\r
\r
return (Status);\r
}\r
\r
@return Destination return the resultant string.\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
StrnCatGrowLeft (\r
- IN OUT CHAR16 **Destination,\r
- IN OUT UINTN *CurrentSize,\r
- IN CONST CHAR16 *Source,\r
- IN UINTN Count\r
+ IN OUT CHAR16 **Destination,\r
+ IN OUT UINTN *CurrentSize,\r
+ IN CONST CHAR16 *Source,\r
+ IN UINTN Count\r
)\r
{\r
- UINTN DestinationStartSize;\r
- UINTN NewSize;\r
- UINTN CopySize;\r
+ UINTN DestinationStartSize;\r
+ UINTN NewSize;\r
+ UINTN CopySize;\r
\r
if (Destination == NULL) {\r
return (NULL);\r
// allow for NULL pointers address as Destination\r
//\r
if (*Destination != NULL) {\r
- ASSERT(CurrentSize != 0);\r
- DestinationStartSize = StrSize(*Destination);\r
- ASSERT(DestinationStartSize <= *CurrentSize);\r
+ ASSERT (CurrentSize != 0);\r
+ DestinationStartSize = StrSize (*Destination);\r
+ ASSERT (DestinationStartSize <= *CurrentSize);\r
} else {\r
DestinationStartSize = 0;\r
-// ASSERT(*CurrentSize == 0);\r
+ // ASSERT(*CurrentSize == 0);\r
}\r
\r
//\r
// Append all of Source?\r
//\r
if (Count == 0) {\r
- Count = StrSize(Source);\r
+ Count = StrSize (Source);\r
}\r
\r
//\r
while (NewSize < (DestinationStartSize + Count)) {\r
NewSize += 2 * Count;\r
}\r
- *Destination = ReallocatePool(*CurrentSize, NewSize, *Destination);\r
+\r
+ *Destination = ReallocatePool (*CurrentSize, NewSize, *Destination);\r
*CurrentSize = NewSize;\r
} else {\r
- *Destination = AllocateZeroPool(Count+sizeof(CHAR16));\r
+ *Destination = AllocateZeroPool (Count+sizeof (CHAR16));\r
}\r
+\r
if (*Destination == NULL) {\r
return NULL;\r
}\r
\r
- CopySize = StrSize(*Destination);\r
- CopyMem((*Destination)+((Count-2)/sizeof(CHAR16)), *Destination, CopySize);\r
- CopyMem(*Destination, Source, Count-2);\r
+ CopySize = StrSize (*Destination);\r
+ CopyMem ((*Destination)+((Count-2)/sizeof (CHAR16)), *Destination, CopySize);\r
+ CopyMem (*Destination, Source, Count-2);\r
return (*Destination);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
FileHandleGetFileName (\r
- IN CONST EFI_FILE_HANDLE Handle,\r
- OUT CHAR16 **FullFileName\r
+ IN CONST EFI_FILE_HANDLE Handle,\r
+ OUT CHAR16 **FullFileName\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Size;\r
- EFI_FILE_HANDLE CurrentHandle;\r
- EFI_FILE_HANDLE NextHigherHandle;\r
- EFI_FILE_INFO *FileInfo;\r
+ EFI_STATUS Status;\r
+ UINTN Size;\r
+ EFI_FILE_HANDLE CurrentHandle;\r
+ EFI_FILE_HANDLE NextHigherHandle;\r
+ EFI_FILE_INFO *FileInfo;\r
\r
Size = 0;\r
\r
//\r
// Check our parameters\r
//\r
- if (FullFileName == NULL || Handle == NULL) {\r
+ if ((FullFileName == NULL) || (Handle == NULL)) {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
*FullFileName = NULL;\r
CurrentHandle = NULL;\r
\r
- Status = Handle->Open(Handle, &CurrentHandle, L".", EFI_FILE_MODE_READ, 0);\r
- if (!EFI_ERROR(Status)) {\r
+ Status = Handle->Open (Handle, &CurrentHandle, L".", EFI_FILE_MODE_READ, 0);\r
+ if (!EFI_ERROR (Status)) {\r
//\r
// Reverse out the current directory on the device\r
//\r
- for (;;) {\r
- FileInfo = FileHandleGetInfo(CurrentHandle);\r
+ for ( ; ;) {\r
+ FileInfo = FileHandleGetInfo (CurrentHandle);\r
if (FileInfo == NULL) {\r
Status = EFI_OUT_OF_RESOURCES;\r
break;\r
//\r
Status = EFI_SUCCESS;\r
if (*FullFileName == NULL) {\r
- ASSERT((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
- *FullFileName = StrnCatGrowLeft(FullFileName, &Size, L"\\", 0);\r
+ ASSERT ((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
+ *FullFileName = StrnCatGrowLeft (FullFileName, &Size, L"\\", 0);\r
}\r
- FreePool(FileInfo);\r
+\r
+ FreePool (FileInfo);\r
break;\r
} else {\r
if (*FullFileName == NULL) {\r
- ASSERT((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
- *FullFileName = StrnCatGrowLeft(FullFileName, &Size, L"\\", 0);\r
+ ASSERT ((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
+ *FullFileName = StrnCatGrowLeft (FullFileName, &Size, L"\\", 0);\r
}\r
- ASSERT((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
- *FullFileName = StrnCatGrowLeft(FullFileName, &Size, FileInfo->FileName, 0);\r
- *FullFileName = StrnCatGrowLeft(FullFileName, &Size, L"\\", 0);\r
- FreePool(FileInfo);\r
+\r
+ ASSERT ((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
+ *FullFileName = StrnCatGrowLeft (FullFileName, &Size, FileInfo->FileName, 0);\r
+ *FullFileName = StrnCatGrowLeft (FullFileName, &Size, L"\\", 0);\r
+ FreePool (FileInfo);\r
}\r
}\r
\r
- FileHandleClose(CurrentHandle);\r
+ FileHandleClose (CurrentHandle);\r
//\r
// Move to the parent directory\r
//\r
}\r
} else if (Status == EFI_NOT_FOUND) {\r
Status = EFI_SUCCESS;\r
- ASSERT((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
- *FullFileName = StrnCatGrowLeft(FullFileName, &Size, L"\\", 0);\r
+ ASSERT ((*FullFileName == NULL && Size == 0) || (*FullFileName != NULL));\r
+ *FullFileName = StrnCatGrowLeft (FullFileName, &Size, L"\\", 0);\r
}\r
\r
- if (*FullFileName != NULL &&\r
- (*FullFileName)[StrLen(*FullFileName) - 1] == L'\\' &&\r
- StrLen(*FullFileName) > 1 &&\r
- FileHandleIsDirectory(Handle) == EFI_NOT_FOUND\r
- ) {\r
- (*FullFileName)[StrLen(*FullFileName) - 1] = CHAR_NULL;\r
+ if ((*FullFileName != NULL) &&\r
+ ((*FullFileName)[StrLen (*FullFileName) - 1] == L'\\') &&\r
+ (StrLen (*FullFileName) > 1) &&\r
+ (FileHandleIsDirectory (Handle) == EFI_NOT_FOUND)\r
+ )\r
+ {\r
+ (*FullFileName)[StrLen (*FullFileName) - 1] = CHAR_NULL;\r
}\r
\r
if (CurrentHandle != NULL) {\r
CurrentHandle->Close (CurrentHandle);\r
}\r
\r
- if (EFI_ERROR(Status) && *FullFileName != NULL) {\r
- FreePool(*FullFileName);\r
+ if (EFI_ERROR (Status) && (*FullFileName != NULL)) {\r
+ FreePool (*FullFileName);\r
}\r
\r
return (Status);\r
\r
@sa FileHandleReadLine\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
-FileHandleReturnLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN OUT BOOLEAN *Ascii\r
+FileHandleReturnLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN OUT BOOLEAN *Ascii\r
)\r
{\r
- CHAR16 *RetVal;\r
- UINTN Size;\r
- EFI_STATUS Status;\r
+ CHAR16 *RetVal;\r
+ UINTN Size;\r
+ EFI_STATUS Status;\r
\r
- Size = 0;\r
+ Size = 0;\r
RetVal = NULL;\r
\r
- Status = FileHandleReadLine(Handle, RetVal, &Size, FALSE, Ascii);\r
+ Status = FileHandleReadLine (Handle, RetVal, &Size, FALSE, Ascii);\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
- RetVal = AllocateZeroPool(Size);\r
- Status = FileHandleReadLine(Handle, RetVal, &Size, FALSE, Ascii);\r
+ RetVal = AllocateZeroPool (Size);\r
+ Status = FileHandleReadLine (Handle, RetVal, &Size, FALSE, Ascii);\r
}\r
- ASSERT_EFI_ERROR(Status);\r
- if (EFI_ERROR(Status) && (RetVal != NULL)) {\r
- FreePool(RetVal);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (EFI_ERROR (Status) && (RetVal != NULL)) {\r
+ FreePool (RetVal);\r
RetVal = NULL;\r
}\r
+\r
return (RetVal);\r
}\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleReadLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN OUT CHAR16 *Buffer,\r
- IN OUT UINTN *Size,\r
- IN BOOLEAN Truncate,\r
- IN OUT BOOLEAN *Ascii\r
+FileHandleReadLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN OUT CHAR16 *Buffer,\r
+ IN OUT UINTN *Size,\r
+ IN BOOLEAN Truncate,\r
+ IN OUT BOOLEAN *Ascii\r
)\r
{\r
EFI_STATUS Status;\r
UINTN OldSize;\r
UINT64 OriginalFilePosition;\r
\r
- if (Handle == NULL\r
- ||Size == NULL\r
- ||(Buffer==NULL&&*Size!=0)\r
- ){\r
+ if ( (Handle == NULL)\r
+ || (Size == NULL)\r
+ || ((Buffer == NULL) && (*Size != 0))\r
+ )\r
+ {\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
- if (Buffer != NULL && *Size != 0) {\r
+ if ((Buffer != NULL) && (*Size != 0)) {\r
*Buffer = CHAR_NULL;\r
}\r
\r
return EFI_SUCCESS;\r
}\r
\r
- FileHandleGetPosition(Handle, &OriginalFilePosition);\r
+ FileHandleGetPosition (Handle, &OriginalFilePosition);\r
if (OriginalFilePosition == 0) {\r
- CharSize = sizeof(CHAR16);\r
- Status = FileHandleRead(Handle, &CharSize, &CharBuffer);\r
- ASSERT_EFI_ERROR(Status);\r
+ CharSize = sizeof (CHAR16);\r
+ Status = FileHandleRead (Handle, &CharSize, &CharBuffer);\r
+ ASSERT_EFI_ERROR (Status);\r
if (CharBuffer == gUnicodeFileTag) {\r
*Ascii = FALSE;\r
} else {\r
*Ascii = TRUE;\r
- FileHandleSetPosition(Handle, OriginalFilePosition);\r
+ FileHandleSetPosition (Handle, OriginalFilePosition);\r
}\r
}\r
\r
CrCount = 0;\r
- for (CountSoFar = 0;;CountSoFar++){\r
+ for (CountSoFar = 0; ; CountSoFar++) {\r
CharBuffer = 0;\r
if (*Ascii) {\r
- CharSize = sizeof(CHAR8);\r
+ CharSize = sizeof (CHAR8);\r
} else {\r
- CharSize = sizeof(CHAR16);\r
+ CharSize = sizeof (CHAR16);\r
}\r
- Status = FileHandleRead(Handle, &CharSize, &CharBuffer);\r
- if ( EFI_ERROR(Status)\r
- || CharSize == 0\r
- || (CharBuffer == L'\n' && !(*Ascii))\r
- || (CharBuffer == '\n' && *Ascii)\r
- ){\r
+\r
+ Status = FileHandleRead (Handle, &CharSize, &CharBuffer);\r
+ if ( EFI_ERROR (Status)\r
+ || (CharSize == 0)\r
+ || ((CharBuffer == L'\n') && !(*Ascii))\r
+ || ((CharBuffer == '\n') && *Ascii)\r
+ )\r
+ {\r
break;\r
} else if (\r
- (CharBuffer == L'\r' && !(*Ascii)) ||\r
- (CharBuffer == '\r' && *Ascii)\r
- ) {\r
+ ((CharBuffer == L'\r') && !(*Ascii)) ||\r
+ ((CharBuffer == '\r') && *Ascii)\r
+ )\r
+ {\r
CrCount++;\r
continue;\r
}\r
+\r
//\r
// if we have space save it...\r
//\r
- if ((CountSoFar+1-CrCount)*sizeof(CHAR16) < *Size){\r
- ASSERT(Buffer != NULL);\r
- ((CHAR16*)Buffer)[CountSoFar-CrCount] = CharBuffer;\r
- ((CHAR16*)Buffer)[CountSoFar+1-CrCount] = CHAR_NULL;\r
+ if ((CountSoFar+1-CrCount)*sizeof (CHAR16) < *Size) {\r
+ ASSERT (Buffer != NULL);\r
+ ((CHAR16 *)Buffer)[CountSoFar-CrCount] = CharBuffer;\r
+ ((CHAR16 *)Buffer)[CountSoFar+1-CrCount] = CHAR_NULL;\r
}\r
}\r
\r
//\r
// if we ran out of space tell when...\r
//\r
- if ((CountSoFar+1-CrCount)*sizeof(CHAR16) > *Size){\r
+ if ((CountSoFar+1-CrCount)*sizeof (CHAR16) > *Size) {\r
OldSize = *Size;\r
- *Size = (CountSoFar+1-CrCount)*sizeof(CHAR16);\r
+ *Size = (CountSoFar+1-CrCount)*sizeof (CHAR16);\r
if (!Truncate) {\r
- if (Buffer != NULL && OldSize != 0) {\r
- ZeroMem(Buffer, OldSize);\r
+ if ((Buffer != NULL) && (OldSize != 0)) {\r
+ ZeroMem (Buffer, OldSize);\r
}\r
- FileHandleSetPosition(Handle, OriginalFilePosition);\r
+\r
+ FileHandleSetPosition (Handle, OriginalFilePosition);\r
return (EFI_BUFFER_TOO_SMALL);\r
} else {\r
- DEBUG((DEBUG_WARN, "The line was truncated in FileHandleReadLine"));\r
+ DEBUG ((DEBUG_WARN, "The line was truncated in FileHandleReadLine"));\r
return (EFI_SUCCESS);\r
}\r
}\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandleWriteLine(\r
- IN EFI_FILE_HANDLE Handle,\r
- IN CHAR16 *Buffer\r
+FileHandleWriteLine (\r
+ IN EFI_FILE_HANDLE Handle,\r
+ IN CHAR16 *Buffer\r
)\r
{\r
EFI_STATUS Status;\r
return (EFI_INVALID_PARAMETER);\r
}\r
\r
- Ascii = FALSE;\r
+ Ascii = FALSE;\r
AsciiBuffer = NULL;\r
\r
- Status = FileHandleGetPosition(Handle, &OriginalFilePosition);\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleGetPosition (Handle, &OriginalFilePosition);\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- Status = FileHandleSetPosition(Handle, 0);\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleSetPosition (Handle, 0);\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
- Status = FileHandleGetSize(Handle, &FileSize);\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleGetSize (Handle, &FileSize);\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
Ascii = TRUE;\r
} else {\r
CharSize = sizeof (CHAR16);\r
- Status = FileHandleRead (Handle, &CharSize, &CharBuffer);\r
+ Status = FileHandleRead (Handle, &CharSize, &CharBuffer);\r
ASSERT_EFI_ERROR (Status);\r
if (CharBuffer == gUnicodeFileTag) {\r
Ascii = FALSE;\r
}\r
}\r
\r
- Status = FileHandleSetPosition(Handle, OriginalFilePosition);\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleSetPosition (Handle, OriginalFilePosition);\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
\r
if (Ascii) {\r
- Size = ( StrSize(Buffer) / sizeof(CHAR16) ) * sizeof(CHAR8);\r
- AsciiBuffer = (CHAR8 *)AllocateZeroPool(Size);\r
+ Size = (StrSize (Buffer) / sizeof (CHAR16)) * sizeof (CHAR8);\r
+ AsciiBuffer = (CHAR8 *)AllocateZeroPool (Size);\r
if (AsciiBuffer == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
UnicodeStrToAsciiStrS (Buffer, AsciiBuffer, Size);\r
for (Index = 0; Index < Size; Index++) {\r
if ((AsciiBuffer[Index] & BIT7) != 0) {\r
- FreePool(AsciiBuffer);\r
+ FreePool (AsciiBuffer);\r
return EFI_INVALID_PARAMETER;\r
}\r
}\r
\r
- Size = AsciiStrSize(AsciiBuffer) - sizeof(CHAR8);\r
- Status = FileHandleWrite(Handle, &Size, AsciiBuffer);\r
- if (EFI_ERROR(Status)) {\r
+ Size = AsciiStrSize (AsciiBuffer) - sizeof (CHAR8);\r
+ Status = FileHandleWrite (Handle, &Size, AsciiBuffer);\r
+ if (EFI_ERROR (Status)) {\r
FreePool (AsciiBuffer);\r
return (Status);\r
}\r
- Size = AsciiStrSize("\r\n") - sizeof(CHAR8);\r
- Status = FileHandleWrite(Handle, &Size, "\r\n");\r
+\r
+ Size = AsciiStrSize ("\r\n") - sizeof (CHAR8);\r
+ Status = FileHandleWrite (Handle, &Size, "\r\n");\r
} else {\r
if (OriginalFilePosition == 0) {\r
- Status = FileHandleSetPosition (Handle, sizeof(CHAR16));\r
- if (EFI_ERROR(Status)) {\r
+ Status = FileHandleSetPosition (Handle, sizeof (CHAR16));\r
+ if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
}\r
- Size = StrSize(Buffer) - sizeof(CHAR16);\r
- Status = FileHandleWrite(Handle, &Size, Buffer);\r
- if (EFI_ERROR(Status)) {\r
+\r
+ Size = StrSize (Buffer) - sizeof (CHAR16);\r
+ Status = FileHandleWrite (Handle, &Size, Buffer);\r
+ if (EFI_ERROR (Status)) {\r
return (Status);\r
}\r
- Size = StrSize(L"\r\n") - sizeof(CHAR16);\r
- Status = FileHandleWrite(Handle, &Size, L"\r\n");\r
+\r
+ Size = StrSize (L"\r\n") - sizeof (CHAR16);\r
+ Status = FileHandleWrite (Handle, &Size, L"\r\n");\r
}\r
\r
if (AsciiBuffer != NULL) {\r
FreePool (AsciiBuffer);\r
}\r
+\r
return Status;\r
}\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-FileHandlePrintLine(\r
+FileHandlePrintLine (\r
IN EFI_FILE_HANDLE Handle,\r
IN CONST CHAR16 *Format,\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- CHAR16 *Buffer;\r
- EFI_STATUS Status;\r
+ VA_LIST Marker;\r
+ CHAR16 *Buffer;\r
+ EFI_STATUS Status;\r
\r
//\r
// Get a buffer to print into\r
//\r
// Print buffer into file\r
//\r
- Status = FileHandleWriteLine(Handle, Buffer);\r
+ Status = FileHandleWriteLine (Handle, Buffer);\r
\r
//\r
// Cleanup and return\r
//\r
- FreePool(Buffer);\r
+ FreePool (Buffer);\r
return (Status);\r
}\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
-FileHandleEof(\r
- IN EFI_FILE_HANDLE Handle\r
+FileHandleEof (\r
+ IN EFI_FILE_HANDLE Handle\r
)\r
{\r
- EFI_FILE_INFO *Info;\r
- UINT64 Pos;\r
- BOOLEAN RetVal;\r
+ EFI_FILE_INFO *Info;\r
+ UINT64 Pos;\r
+ BOOLEAN RetVal;\r
\r
if (Handle == NULL) {\r
return (FALSE);\r
}\r
\r
- FileHandleGetPosition(Handle, &Pos);\r
+ FileHandleGetPosition (Handle, &Pos);\r
Info = FileHandleGetInfo (Handle);\r
\r
if (Info == NULL) {\r
return (FALSE);\r
}\r
\r
- FileHandleSetPosition(Handle, Pos);\r
+ FileHandleSetPosition (Handle, Pos);\r
\r
if (Pos == Info->FileSize) {\r
RetVal = TRUE;\r
**/\r
EFI_ACPI_COMMON_HEADER *\r
ScanTableInSDT (\r
- IN EFI_ACPI_DESCRIPTION_HEADER *Sdt,\r
- IN UINTN TablePointerSize,\r
- IN UINT32 Signature,\r
- IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL,\r
- OUT BOOLEAN *PreviousTableLocated OPTIONAL\r
+ IN EFI_ACPI_DESCRIPTION_HEADER *Sdt,\r
+ IN UINTN TablePointerSize,\r
+ IN UINT32 Signature,\r
+ IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL,\r
+ OUT BOOLEAN *PreviousTableLocated OPTIONAL\r
)\r
{\r
- UINTN Index;\r
- UINTN EntryCount;\r
- UINT64 EntryPtr;\r
- UINTN BasePtr;\r
- EFI_ACPI_COMMON_HEADER *Table;\r
+ UINTN Index;\r
+ UINTN EntryCount;\r
+ UINT64 EntryPtr;\r
+ UINTN BasePtr;\r
+ EFI_ACPI_COMMON_HEADER *Table;\r
\r
if (PreviousTableLocated != NULL) {\r
ASSERT (PreviousTable != NULL);\r
EntryCount = (Sdt->Length - sizeof (EFI_ACPI_DESCRIPTION_HEADER)) / TablePointerSize;\r
\r
BasePtr = (UINTN)(Sdt + 1);\r
- for (Index = 0; Index < EntryCount; Index ++) {\r
+ for (Index = 0; Index < EntryCount; Index++) {\r
EntryPtr = 0;\r
CopyMem (&EntryPtr, (VOID *)(BasePtr + Index * TablePointerSize), TablePointerSize);\r
Table = (EFI_ACPI_COMMON_HEADER *)((UINTN)(EntryPtr));\r
//\r
return Table;\r
}\r
-\r
}\r
}\r
\r
IN EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt\r
)\r
{\r
- EFI_ACPI_COMMON_HEADER *Facs;\r
- UINT64 Data64;\r
+ EFI_ACPI_COMMON_HEADER *Facs;\r
+ UINT64 Data64;\r
\r
if (Fadt == NULL) {\r
return NULL;\r
if (Fadt->Header.Revision < EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
Facs = (EFI_ACPI_COMMON_HEADER *)(UINTN)Fadt->FirmwareCtrl;\r
} else {\r
- CopyMem (&Data64, &Fadt->XFirmwareCtrl, sizeof(UINT64));\r
+ CopyMem (&Data64, &Fadt->XFirmwareCtrl, sizeof (UINT64));\r
if (Data64 != 0) {\r
Facs = (EFI_ACPI_COMMON_HEADER *)(UINTN)Data64;\r
} else {\r
Facs = (EFI_ACPI_COMMON_HEADER *)(UINTN)Fadt->FirmwareCtrl;\r
}\r
}\r
+\r
return Facs;\r
}\r
\r
IN EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt\r
)\r
{\r
- EFI_ACPI_COMMON_HEADER *Dsdt;\r
- UINT64 Data64;\r
+ EFI_ACPI_COMMON_HEADER *Dsdt;\r
+ UINT64 Data64;\r
\r
if (Fadt == NULL) {\r
return NULL;\r
if (Fadt->Header.Revision < EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
Dsdt = (EFI_ACPI_COMMON_HEADER *)(UINTN)Fadt->Dsdt;\r
} else {\r
- CopyMem (&Data64, &Fadt->XDsdt, sizeof(UINT64));\r
+ CopyMem (&Data64, &Fadt->XDsdt, sizeof (UINT64));\r
if (Data64 != 0) {\r
Dsdt = (EFI_ACPI_COMMON_HEADER *)(UINTN)Data64;\r
} else {\r
Dsdt = (EFI_ACPI_COMMON_HEADER *)(UINTN)Fadt->Dsdt;\r
}\r
}\r
+\r
return Dsdt;\r
}\r
\r
**/\r
EFI_ACPI_COMMON_HEADER *\r
LocateAcpiTableInAcpiConfigurationTable (\r
- IN EFI_GUID *AcpiGuid,\r
- IN UINT32 Signature,\r
- IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL,\r
- OUT BOOLEAN *PreviousTableLocated OPTIONAL\r
+ IN EFI_GUID *AcpiGuid,\r
+ IN UINT32 Signature,\r
+ IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL,\r
+ OUT BOOLEAN *PreviousTableLocated OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// Get ACPI ConfigurationTable (RSD_PTR)\r
//\r
- Status = EfiGetSystemConfigurationTable(AcpiGuid, (VOID **)&Rsdp);\r
+ Status = EfiGetSystemConfigurationTable (AcpiGuid, (VOID **)&Rsdp);\r
if (EFI_ERROR (Status) || (Rsdp == NULL)) {\r
return NULL;\r
}\r
// Search XSDT\r
//\r
if (Rsdp->Revision >= EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION) {\r
- Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN) Rsdp->XsdtAddress;\r
+ Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)Rsdp->XsdtAddress;\r
if (Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {\r
ASSERT (PreviousTable == NULL);\r
//\r
// It is to locate DSDT,\r
// need to locate FADT first.\r
//\r
- Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) ScanTableInSDT (\r
- Xsdt,\r
- sizeof (UINT64),\r
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- NULL,\r
- NULL\r
- );\r
+ Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)ScanTableInSDT (\r
+ Xsdt,\r
+ sizeof (UINT64),\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ NULL,\r
+ NULL\r
+ );\r
Table = LocateAcpiDsdtFromFadt (Fadt);\r
} else if (Signature == EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {\r
ASSERT (PreviousTable == NULL);\r
// It is to locate FACS,\r
// need to locate FADT first.\r
//\r
- Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) ScanTableInSDT (\r
- Xsdt,\r
- sizeof (UINT64),\r
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- NULL,\r
- NULL\r
- );\r
+ Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)ScanTableInSDT (\r
+ Xsdt,\r
+ sizeof (UINT64),\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ NULL,\r
+ NULL\r
+ );\r
Table = LocateAcpiFacsFromFadt (Fadt);\r
} else {\r
Table = ScanTableInSDT (\r
if (Table != NULL) {\r
return Table;\r
} else if ((PreviousTableLocated != NULL) &&\r
- *PreviousTableLocated) {\r
+ *PreviousTableLocated)\r
+ {\r
//\r
// PreviousTable could be located in XSDT,\r
// but next table could not be located in XSDT.\r
//\r
// Search RSDT\r
//\r
- Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN) Rsdp->RsdtAddress;\r
+ Rsdt = (EFI_ACPI_DESCRIPTION_HEADER *)(UINTN)Rsdp->RsdtAddress;\r
if (Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {\r
ASSERT (PreviousTable == NULL);\r
//\r
// It is to locate DSDT,\r
// need to locate FADT first.\r
//\r
- Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) ScanTableInSDT (\r
- Rsdt,\r
- sizeof (UINT32),\r
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- NULL,\r
- NULL\r
- );\r
+ Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)ScanTableInSDT (\r
+ Rsdt,\r
+ sizeof (UINT32),\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ NULL,\r
+ NULL\r
+ );\r
Table = LocateAcpiDsdtFromFadt (Fadt);\r
} else if (Signature == EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {\r
ASSERT (PreviousTable == NULL);\r
// It is to locate FACS,\r
// need to locate FADT first.\r
//\r
- Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) ScanTableInSDT (\r
- Rsdt,\r
- sizeof (UINT32),\r
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
- NULL,\r
- NULL\r
- );\r
+ Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)ScanTableInSDT (\r
+ Rsdt,\r
+ sizeof (UINT32),\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ NULL,\r
+ NULL\r
+ );\r
Table = LocateAcpiFacsFromFadt (Fadt);\r
} else {\r
Table = ScanTableInSDT (\r
EFI_ACPI_COMMON_HEADER *\r
EFIAPI\r
EfiLocateNextAcpiTable (\r
- IN UINT32 Signature,\r
- IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL\r
+ IN UINT32 Signature,\r
+ IN EFI_ACPI_COMMON_HEADER *PreviousTable OPTIONAL\r
)\r
{\r
- EFI_ACPI_COMMON_HEADER *Table;\r
- BOOLEAN TempPreviousTableLocated;\r
- BOOLEAN *PreviousTableLocated;\r
+ EFI_ACPI_COMMON_HEADER *Table;\r
+ BOOLEAN TempPreviousTableLocated;\r
+ BOOLEAN *PreviousTableLocated;\r
\r
if (PreviousTable != NULL) {\r
if (PreviousTable->Signature != Signature) {\r
return NULL;\r
} else if ((Signature == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE) ||\r
(Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) ||\r
- (Signature == EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE)) {\r
+ (Signature == EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE))\r
+ {\r
//\r
// There is only one FADT/DSDT/FACS table,\r
// so don't try to locate next one.\r
return NULL;\r
}\r
\r
- PreviousTableLocated = &TempPreviousTableLocated;\r
+ PreviousTableLocated = &TempPreviousTableLocated;\r
*PreviousTableLocated = FALSE;\r
} else {\r
PreviousTableLocated = NULL;\r
if (Table != NULL) {\r
return Table;\r
} else if ((PreviousTableLocated != NULL) &&\r
- *PreviousTableLocated) {\r
+ *PreviousTableLocated)\r
+ {\r
//\r
// PreviousTable could be located in gEfiAcpi20TableGuid system\r
// configuration table, but next table could not be located in\r
EFI_ACPI_COMMON_HEADER *\r
EFIAPI\r
EfiLocateFirstAcpiTable (\r
- IN UINT32 Signature\r
+ IN UINT32 Signature\r
)\r
{\r
return EfiLocateNextAcpiTable (Signature, NULL);\r
\r
**/\r
\r
-\r
-\r
-\r
#include "UefiLibInternal.h"\r
\r
typedef struct {\r
- CHAR16 WChar;\r
- UINT32 Width;\r
+ CHAR16 WChar;\r
+ UINT32 Width;\r
} UNICODE_WIDTH_ENTRY;\r
\r
-#define NARROW_CHAR 0xFFF0\r
-#define WIDE_CHAR 0xFFF1\r
+#define NARROW_CHAR 0xFFF0\r
+#define WIDE_CHAR 0xFFF1\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST UNICODE_WIDTH_ENTRY mUnicodeWidthTable[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST UNICODE_WIDTH_ENTRY mUnicodeWidthTable[] = {\r
//\r
// General script area\r
//\r
- {(CHAR16)0x1FFF, 1},\r
+ { (CHAR16)0x1FFF, 1 },\r
+\r
/*\r
* Merge the blocks and replace them with the above entry as they fall to\r
* the same category and they are all narrow glyph. This will reduce search\r
//\r
// Symbol area\r
//\r
- {(CHAR16)0x2FFF, 1},\r
+ { (CHAR16)0x2FFF, 1 },\r
+\r
/*\r
* Merge the blocks and replace them with the above entry as they fall to\r
* the same category and they are all narrow glyph. This will reduce search\r
//\r
// CJK phonetics and symbol area\r
//\r
- {(CHAR16)0x33FF, 2},\r
+ { (CHAR16)0x33FF, 2 },\r
+\r
/*\r
* Merge the blocks and replace them with the above entry as they fall to\r
* the same category and they are all wide glyph. This will reduce search\r
//\r
// CJK ideograph area\r
//\r
- {(CHAR16)0x9FFF, 2},\r
+ { (CHAR16)0x9FFF, 2 },\r
+\r
/*\r
* Merge the blocks and replace them with the above entry as they fall to\r
* the same category and they are all wide glyph. This will reduce search\r
//\r
// Reserved\r
//\r
- {(CHAR16)0xABFF, 0}, // Reserved. 0xA000-0xA490 as Yi syllables. 0xA490-0xA4D0\r
+ { (CHAR16)0xABFF, 0 }, // Reserved. 0xA000-0xA490 as Yi syllables. 0xA490-0xA4D0\r
// as Yi radicals in ver3.0. 0xA000-0xABFF\r
//\r
// Hangul syllables\r
//\r
- {(CHAR16)0xD7FF, 2},\r
+ { (CHAR16)0xD7FF, 2 },\r
+\r
/*\r
* Merge the blocks and replace them with the above entry as they fall to\r
* the same category and they are all wide glyph. This will reduce search\r
//\r
// Surrogates area\r
//\r
- {(CHAR16)0xDFFF, 0}, // Surrogates, not used now. 0xD800-0xDFFF\r
+ { (CHAR16)0xDFFF, 0 }, // Surrogates, not used now. 0xD800-0xDFFF\r
\r
//\r
// Private use area\r
//\r
- {(CHAR16)0xF8FF, 0}, // Private use area. 0xE000-0xF8FF\r
+ { (CHAR16)0xF8FF, 0 }, // Private use area. 0xE000-0xF8FF\r
\r
//\r
// Compatibility area and specials\r
//\r
- {(CHAR16)0xFAFF, 2}, // CJK compatibility ideographs. 0xF900-0xFAFF\r
- {(CHAR16)0xFB4F, 1}, // Alphabetic presentation forms. 0xFB00-0xFB4F\r
- {(CHAR16)0xFDFF, 1}, // Arabic presentation forms-A. 0xFB50-0xFDFF\r
- {(CHAR16)0xFE1F, 0}, // Reserved. As variation selectors in ver3.0. 0xFE00-0xFE1F\r
- {(CHAR16)0xFE2F, 1}, // Combining half marks. 0xFE20-0xFE2F\r
- {(CHAR16)0xFE4F, 2}, // CJK compatibility forms. 0xFE30-0xFE4F\r
- {(CHAR16)0xFE6F, 1}, // Small Form Variants. 0xFE50-0xFE6F\r
- {(CHAR16)0xFEFF, 1}, // Arabic presentation forms-B. 0xFE70-0xFEFF\r
- {(CHAR16)0xFFEF, 1}, // Half width and full width forms. 0xFF00-0xFFEF\r
- {(CHAR16)0xFFFF, 0}, // Speicials. 0xFFF0-0xFFFF\r
+ { (CHAR16)0xFAFF, 2 }, // CJK compatibility ideographs. 0xF900-0xFAFF\r
+ { (CHAR16)0xFB4F, 1 }, // Alphabetic presentation forms. 0xFB00-0xFB4F\r
+ { (CHAR16)0xFDFF, 1 }, // Arabic presentation forms-A. 0xFB50-0xFDFF\r
+ { (CHAR16)0xFE1F, 0 }, // Reserved. As variation selectors in ver3.0. 0xFE00-0xFE1F\r
+ { (CHAR16)0xFE2F, 1 }, // Combining half marks. 0xFE20-0xFE2F\r
+ { (CHAR16)0xFE4F, 2 }, // CJK compatibility forms. 0xFE30-0xFE4F\r
+ { (CHAR16)0xFE6F, 1 }, // Small Form Variants. 0xFE50-0xFE6F\r
+ { (CHAR16)0xFEFF, 1 }, // Arabic presentation forms-B. 0xFE70-0xFEFF\r
+ { (CHAR16)0xFFEF, 1 }, // Half width and full width forms. 0xFF00-0xFFEF\r
+ { (CHAR16)0xFFFF, 0 }, // Speicials. 0xFFF0-0xFFFF\r
};\r
\r
/**\r
IN CHAR16 UnicodeChar\r
)\r
{\r
- UINTN Index;\r
- UINTN Low;\r
- UINTN High;\r
- CONST UNICODE_WIDTH_ENTRY *Item;\r
-\r
- Item = NULL;\r
- Low = 0;\r
- High = (sizeof (mUnicodeWidthTable)) / (sizeof (UNICODE_WIDTH_ENTRY)) - 1;\r
+ UINTN Index;\r
+ UINTN Low;\r
+ UINTN High;\r
+ CONST UNICODE_WIDTH_ENTRY *Item;\r
+\r
+ Item = NULL;\r
+ Low = 0;\r
+ High = (sizeof (mUnicodeWidthTable)) / (sizeof (UNICODE_WIDTH_ENTRY)) - 1;\r
while (Low <= High) {\r
Index = (Low + High) >> 1;\r
Item = &(mUnicodeWidthTable[Index]);\r
IN CONST CHAR16 *String\r
)\r
{\r
- UINTN Length;\r
- UINTN Width;\r
+ UINTN Length;\r
+ UINTN Width;\r
\r
if (String == NULL) {\r
return 0;\r
**/\r
UINTN\r
UefiLibGetStringWidth (\r
- IN CHAR16 *String,\r
- IN BOOLEAN LimitLen,\r
- IN UINTN MaxWidth,\r
- OUT UINTN *Offset\r
+ IN CHAR16 *String,\r
+ IN BOOLEAN LimitLen,\r
+ IN UINTN MaxWidth,\r
+ OUT UINTN *Offset\r
)\r
{\r
- UINTN Index;\r
- UINTN Count;\r
- UINTN IncrementValue;\r
+ UINTN Index;\r
+ UINTN Count;\r
+ UINTN IncrementValue;\r
\r
if (String == NULL) {\r
return 0;\r
}\r
\r
- Index = 0;\r
- Count = 0;\r
- IncrementValue = 1;\r
+ Index = 0;\r
+ Count = 0;\r
+ IncrementValue = 1;\r
\r
do {\r
//\r
// Advance to the null-terminator or to the first width directive\r
//\r
- for (;(String[Index] != NARROW_CHAR) && (String[Index] != WIDE_CHAR) && (String[Index] != 0); Index++) {\r
+ for ( ; (String[Index] != NARROW_CHAR) && (String[Index] != WIDE_CHAR) && (String[Index] != 0); Index++) {\r
Count = Count + IncrementValue;\r
\r
- if (LimitLen && Count > MaxWidth) {\r
+ if (LimitLen && (Count > MaxWidth)) {\r
break;\r
}\r
}\r
break;\r
}\r
\r
- if (LimitLen && Count > MaxWidth) {\r
+ if (LimitLen && (Count > MaxWidth)) {\r
*Offset = Index;\r
break;\r
}\r
// number of lines in the popup\r
//\r
VA_START (Args, Key);\r
- MaxLength = 0;\r
+ MaxLength = 0;\r
NumberOfLines = 0;\r
while ((String = VA_ARG (Args, CHAR16 *)) != NULL) {\r
MaxLength = MAX (MaxLength, UefiLibGetStringWidth (String, FALSE, 0, NULL) / 2);\r
NumberOfLines++;\r
}\r
+\r
VA_END (Args);\r
\r
//\r
ConOut->OutputString (ConOut, TmpString);\r
FreePool (TmpString);\r
}\r
+\r
NumberOfLines--;\r
}\r
+\r
VA_END (Args);\r
\r
//\r
//\r
// Restore the cursor visibility, position, and attributes\r
//\r
- ConOut->EnableCursor (ConOut, SavedConsoleMode.CursorVisible);\r
+ ConOut->EnableCursor (ConOut, SavedConsoleMode.CursorVisible);\r
ConOut->SetCursorPosition (ConOut, SavedConsoleMode.CursorColumn, SavedConsoleMode.CursorRow);\r
- ConOut->SetAttribute (ConOut, SavedConsoleMode.Attribute);\r
+ ConOut->SetAttribute (ConOut, SavedConsoleMode.Attribute);\r
\r
//\r
// Wait for a keystroke\r
if (Status != EFI_NOT_READY) {\r
continue;\r
}\r
+\r
gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &EventIndex);\r
}\r
}\r
\r
**/\r
\r
-\r
#include "UefiLibInternal.h"\r
\r
/**\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
//\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Uninstalls a Driver Binding Protocol instance.\r
\r
\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
//\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Installs and completes the initialization of a Driver Binding Protocol instance and\r
optionally installs the Component Name, Driver Configuration and Driver Diagnostics Protocols.\r
DriverBinding->ImageHandle = ImageHandle;\r
DriverBinding->DriverBindingHandle = DriverBindingHandle;\r
\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
if (DriverConfiguration == NULL) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
}\r
} else {\r
if (DriverConfiguration == NULL) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Uninstalls a Driver Binding Protocol instance and optionally uninstalls the\r
Component Name, Driver Configuration and Driver Diagnostics Protocols.\r
\r
ASSERT (DriverBinding != NULL);\r
\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
if (DriverConfiguration == NULL) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
}\r
} else {\r
if (DriverConfiguration == NULL) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Installs Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiLibInstallDriverBindingComponentName2 (\r
- IN CONST EFI_HANDLE ImageHandle,\r
- IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
+ IN CONST EFI_HANDLE ImageHandle,\r
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
DriverBinding->ImageHandle = ImageHandle;\r
DriverBinding->DriverBindingHandle = DriverBindingHandle;\r
\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
- } else {\r
+ } else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
- }\r
+ }\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- NULL\r
- );\r
- } else {\r
- Status = gBS->InstallMultipleProtocolInterfaces (\r
- &DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- NULL\r
- );\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ NULL\r
+ );\r
+ } else {\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ NULL\r
+ );\r
}\r
}\r
\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Uninstalls Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiLibUninstallDriverBindingComponentName2 (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
\r
ASSERT (DriverBinding != NULL);\r
\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
- } else {\r
+ } else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
- }\r
+ }\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
- Status = gBS->UninstallMultipleProtocolInterfaces (\r
- DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- NULL\r
- );\r
- } else {\r
- Status = gBS->UninstallMultipleProtocolInterfaces (\r
- DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- NULL\r
- );\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ NULL\r
+ );\r
+ } else {\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ NULL\r
+ );\r
}\r
}\r
\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Installs Driver Binding Protocol with optional Component Name, Component Name 2, Driver\r
Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.\r
EFI_STATUS\r
EFIAPI\r
EfiLibInstallAllDriverProtocols2 (\r
- IN CONST EFI_HANDLE ImageHandle,\r
- IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
+ IN CONST EFI_HANDLE ImageHandle,\r
+ IN CONST EFI_SYSTEM_TABLE *SystemTable,\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
\r
if (DriverConfiguration2 == NULL) {\r
if (DriverConfiguration == NULL) {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
} else {\r
if (DriverConfiguration == NULL) {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
return Status;\r
}\r
\r
-\r
-\r
/**\r
Uninstalls Driver Binding Protocol with optional Component Name, Component Name 2, Driver\r
Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.\r
EFI_STATUS\r
EFIAPI\r
EfiLibUninstallAllDriverProtocols2 (\r
- IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
- IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
- IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
- IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
- IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,\r
+ IN CONST EFI_COMPONENT_NAME_PROTOCOL *ComponentName OPTIONAL,\r
+ IN CONST EFI_COMPONENT_NAME2_PROTOCOL *ComponentName2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL *DriverConfiguration OPTIONAL,\r
+ IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2 OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL *DriverDiagnostics OPTIONAL,\r
+ IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL *DriverDiagnostics2 OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
\r
if (DriverConfiguration2 == NULL) {\r
if (DriverConfiguration == NULL) {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
} else {\r
if (DriverConfiguration == NULL) {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics == NULL || FeaturePcdGet(PcdDriverDiagnosticsDisable)) {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics == NULL) || FeaturePcdGet (PcdDriverDiagnosticsDisable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
}\r
}\r
} else {\r
- if (DriverDiagnostics2 == NULL || FeaturePcdGet(PcdDriverDiagnostics2Disable)) {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((DriverDiagnostics2 == NULL) || FeaturePcdGet (PcdDriverDiagnostics2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
NULL\r
);\r
}\r
}\r
} else {\r
- if (ComponentName == NULL || FeaturePcdGet(PcdComponentNameDisable)) {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
+ if ((ComponentName == NULL) || FeaturePcdGet (PcdComponentNameDisable)) {\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
} else {\r
Status = gBS->UninstallMultipleProtocolInterfaces (\r
DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
} else {\r
- if (ComponentName2 == NULL || FeaturePcdGet(PcdComponentName2Disable)) {\r
- Status = gBS->UninstallMultipleProtocolInterfaces (\r
- DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
- NULL\r
- );\r
- } else {\r
- Status = gBS->UninstallMultipleProtocolInterfaces (\r
- DriverBinding->DriverBindingHandle,\r
- &gEfiDriverBindingProtocolGuid, DriverBinding,\r
- &gEfiComponentNameProtocolGuid, ComponentName,\r
- &gEfiComponentName2ProtocolGuid, ComponentName2,\r
- &gEfiDriverConfigurationProtocolGuid, DriverConfiguration,\r
- &gEfiDriverConfiguration2ProtocolGuid, DriverConfiguration2,\r
- &gEfiDriverDiagnosticsProtocolGuid, DriverDiagnostics,\r
- &gEfiDriverDiagnostics2ProtocolGuid, DriverDiagnostics2,\r
+ if ((ComponentName2 == NULL) || FeaturePcdGet (PcdComponentName2Disable)) {\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
+ NULL\r
+ );\r
+ } else {\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ DriverBinding->DriverBindingHandle,\r
+ &gEfiDriverBindingProtocolGuid,\r
+ DriverBinding,\r
+ &gEfiComponentNameProtocolGuid,\r
+ ComponentName,\r
+ &gEfiComponentName2ProtocolGuid,\r
+ ComponentName2,\r
+ &gEfiDriverConfigurationProtocolGuid,\r
+ DriverConfiguration,\r
+ &gEfiDriverConfiguration2ProtocolGuid,\r
+ DriverConfiguration2,\r
+ &gEfiDriverDiagnosticsProtocolGuid,\r
+ DriverDiagnostics,\r
+ &gEfiDriverDiagnostics2ProtocolGuid,\r
+ DriverDiagnostics2,\r
NULL\r
);\r
}\r
\r
**/\r
\r
-\r
#include "UefiLibInternal.h"\r
\r
/**\r
UINT32 Name1;\r
UINT32 Name2;\r
\r
- Name1 = ReadUnaligned24 ((CONST UINT32 *) Language1);\r
- Name2 = ReadUnaligned24 ((CONST UINT32 *) Language2);\r
+ Name1 = ReadUnaligned24 ((CONST UINT32 *)Language1);\r
+ Name2 = ReadUnaligned24 ((CONST UINT32 *)Language2);\r
\r
- return (BOOLEAN) (Name1 == Name2);\r
+ return (BOOLEAN)(Name1 == Name2);\r
}\r
\r
/**\r
ASSERT (Table != NULL);\r
\r
SystemTable = gST;\r
- *Table = NULL;\r
+ *Table = NULL;\r
for (Index = 0; Index < SystemTable->NumberOfTableEntries; Index++) {\r
if (CompareGuid (TableGuid, &(SystemTable->ConfigurationTable[Index].VendorGuid))) {\r
*Table = SystemTable->ConfigurationTable[Index].VendorTable;\r
**/\r
EFI_EVENT\r
EFIAPI\r
-EfiCreateProtocolNotifyEvent(\r
+EfiCreateProtocolNotifyEvent (\r
IN EFI_GUID *ProtocolGuid,\r
IN EFI_TPL NotifyTpl,\r
IN EFI_EVENT_NOTIFY NotifyFunction,\r
EVT_NOTIFY_SIGNAL,\r
NotifyTpl,\r
NotifyFunction,\r
- (VOID *) NotifyContext,\r
+ (VOID *)NotifyContext,\r
&Event\r
);\r
ASSERT_EFI_ERROR (Status);\r
//\r
\r
Status = gBS->RegisterProtocolNotify (\r
- (EFI_GUID *) Name,\r
+ (EFI_GUID *)Name,\r
Event,\r
RegistrationLocal\r
);\r
EFI_STATUS Status;\r
EFI_HANDLE Handle;\r
\r
- ASSERT(Name != NULL);\r
+ ASSERT (Name != NULL);\r
\r
Handle = NULL;\r
Status = gBS->InstallProtocolInterface (\r
&Handle,\r
- (EFI_GUID *) Name,\r
+ (EFI_GUID *)Name,\r
EFI_NATIVE_INTERFACE,\r
NULL\r
);\r
\r
Status = gBS->UninstallProtocolInterface (\r
Handle,\r
- (EFI_GUID *) Name,\r
+ (EFI_GUID *)Name,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r
EFI_STATUS\r
EFIAPI\r
EfiEventGroupSignal (\r
- IN CONST EFI_GUID *EventGroup\r
+ IN CONST EFI_GUID *EventGroup\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_EVENT Event;\r
+ EFI_STATUS Status;\r
+ EFI_EVENT Event;\r
\r
if (EventGroup == NULL) {\r
return EFI_INVALID_PARAMETER;\r
VOID\r
EFIAPI\r
EfiEventEmptyFunction (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
}\r
VOID\r
)\r
{\r
- EFI_TPL Tpl;\r
+ EFI_TPL Tpl;\r
\r
Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r
gBS->RestoreTPL (Tpl);\r
return Tpl;\r
}\r
\r
-\r
/**\r
Initializes a basic mutual exclusion lock.\r
\r
EFIAPI\r
EfiInitializeLock (\r
IN OUT EFI_LOCK *Lock,\r
- IN EFI_TPL Priority\r
+ IN EFI_TPL Priority\r
)\r
{\r
ASSERT (Lock != NULL);\r
ASSERT (Priority <= TPL_HIGH_LEVEL);\r
\r
- Lock->Tpl = Priority;\r
- Lock->OwnerTpl = TPL_APPLICATION;\r
- Lock->Lock = EfiLockReleased ;\r
+ Lock->Tpl = Priority;\r
+ Lock->OwnerTpl = TPL_APPLICATION;\r
+ Lock->Lock = EfiLockReleased;\r
return Lock;\r
}\r
\r
IN EFI_LOCK *Lock\r
)\r
{\r
-\r
ASSERT (Lock != NULL);\r
ASSERT (Lock->Lock != EfiLockUninitialized);\r
\r
IN EFI_LOCK *Lock\r
)\r
{\r
- EFI_TPL Tpl;\r
+ EFI_TPL Tpl;\r
\r
ASSERT (Lock != NULL);\r
ASSERT (Lock->Lock == EfiLockAcquired);\r
EFI_STATUS\r
EFIAPI\r
EfiTestManagedDevice (\r
- IN CONST EFI_HANDLE ControllerHandle,\r
- IN CONST EFI_HANDLE DriverBindingHandle,\r
- IN CONST EFI_GUID *ProtocolGuid\r
+ IN CONST EFI_HANDLE ControllerHandle,\r
+ IN CONST EFI_HANDLE DriverBindingHandle,\r
+ IN CONST EFI_GUID *ProtocolGuid\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *ManagedInterface;\r
+ EFI_STATUS Status;\r
+ VOID *ManagedInterface;\r
\r
ASSERT (ProtocolGuid != NULL);\r
\r
Status = gBS->OpenProtocol (\r
ControllerHandle,\r
- (EFI_GUID *) ProtocolGuid,\r
+ (EFI_GUID *)ProtocolGuid,\r
&ManagedInterface,\r
DriverBindingHandle,\r
ControllerHandle,\r
if (!EFI_ERROR (Status)) {\r
gBS->CloseProtocol (\r
ControllerHandle,\r
- (EFI_GUID *) ProtocolGuid,\r
+ (EFI_GUID *)ProtocolGuid,\r
DriverBindingHandle,\r
ControllerHandle\r
);\r
EFI_STATUS\r
EFIAPI\r
EfiTestChildHandle (\r
- IN CONST EFI_HANDLE ControllerHandle,\r
- IN CONST EFI_HANDLE ChildHandle,\r
- IN CONST EFI_GUID *ProtocolGuid\r
+ IN CONST EFI_HANDLE ControllerHandle,\r
+ IN CONST EFI_HANDLE ChildHandle,\r
+ IN CONST EFI_GUID *ProtocolGuid\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;\r
- UINTN EntryCount;\r
- UINTN Index;\r
+ EFI_STATUS Status;\r
+ EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;\r
+ UINTN EntryCount;\r
+ UINTN Index;\r
\r
ASSERT (ProtocolGuid != NULL);\r
\r
//\r
Status = gBS->OpenProtocolInformation (\r
ControllerHandle,\r
- (EFI_GUID *) ProtocolGuid,\r
+ (EFI_GUID *)ProtocolGuid,\r
&OpenInfoBuffer,\r
&EntryCount\r
);\r
Status = EFI_UNSUPPORTED;\r
for (Index = 0; Index < EntryCount; Index++) {\r
if ((OpenInfoBuffer[Index].ControllerHandle == ChildHandle) &&\r
- (OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) != 0) {\r
+ ((OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) != 0))\r
+ {\r
Status = EFI_SUCCESS;\r
break;\r
}\r
EFI_STATUS\r
EFIAPI\r
IsLanguageSupported (\r
- IN CONST CHAR8 *SupportedLanguages,\r
- IN CONST CHAR8 *TargetLanguage\r
+ IN CONST CHAR8 *SupportedLanguages,\r
+ IN CONST CHAR8 *TargetLanguage\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
+\r
while (*SupportedLanguages != 0) {\r
- for (Index = 0; SupportedLanguages[Index] != 0 && SupportedLanguages[Index] != ';'; Index++);\r
- if ((AsciiStrnCmp(SupportedLanguages, TargetLanguage, Index) == 0) && (TargetLanguage[Index] == 0)) {\r
+ for (Index = 0; SupportedLanguages[Index] != 0 && SupportedLanguages[Index] != ';'; Index++) {\r
+ }\r
+\r
+ if ((AsciiStrnCmp (SupportedLanguages, TargetLanguage, Index) == 0) && (TargetLanguage[Index] == 0)) {\r
return EFI_SUCCESS;\r
}\r
+\r
SupportedLanguages += Index;\r
- for (; *SupportedLanguages != 0 && *SupportedLanguages == ';'; SupportedLanguages++);\r
+ for ( ; *SupportedLanguages != 0 && *SupportedLanguages == ';'; SupportedLanguages++) {\r
+ }\r
}\r
\r
return EFI_UNSUPPORTED;\r
//\r
// Make sure the parameters are valid\r
//\r
- if (Language == NULL || UnicodeString == NULL) {\r
+ if ((Language == NULL) || (UnicodeString == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// If there are no supported languages, or the Unicode String Table is empty, then the\r
// Unicode String specified by Language is not supported by this Unicode String Table\r
//\r
- if (SupportedLanguages == NULL || UnicodeStringTable == NULL) {\r
+ if ((SupportedLanguages == NULL) || (UnicodeStringTable == NULL)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
//\r
while (*SupportedLanguages != 0) {\r
if (CompareIso639LanguageCode (Language, SupportedLanguages)) {\r
-\r
//\r
// Search the Unicode String Table for the matching Language specifier\r
//\r
while (UnicodeStringTable->Language != NULL) {\r
if (CompareIso639LanguageCode (Language, UnicodeStringTable->Language)) {\r
-\r
//\r
// A matching string was found, so return it\r
//\r
return EFI_UNSUPPORTED;\r
}\r
\r
-\r
-\r
/**\r
This function looks up a Unicode string in UnicodeStringTable.\r
\r
IN BOOLEAN Iso639Language\r
)\r
{\r
- BOOLEAN Found;\r
- UINTN Index;\r
- CHAR8 *LanguageString;\r
+ BOOLEAN Found;\r
+ UINTN Index;\r
+ CHAR8 *LanguageString;\r
\r
//\r
// Make sure the parameters are valid\r
//\r
- if (Language == NULL || UnicodeString == NULL) {\r
+ if ((Language == NULL) || (UnicodeString == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// If there are no supported languages, or the Unicode String Table is empty, then the\r
// Unicode String specified by Language is not supported by this Unicode String Table\r
//\r
- if (SupportedLanguages == NULL || UnicodeStringTable == NULL) {\r
+ if ((SupportedLanguages == NULL) || (UnicodeStringTable == NULL)) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
Found = TRUE;\r
break;\r
}\r
+\r
SupportedLanguages += 3;\r
}\r
} else {\r
- Found = !IsLanguageSupported(SupportedLanguages, Language);\r
+ Found = !IsLanguageSupported (SupportedLanguages, Language);\r
}\r
\r
-\r
//\r
// If Language is not a member of SupportedLanguages, then return EFI_UNSUPPORTED\r
//\r
while (UnicodeStringTable->Language != NULL) {\r
LanguageString = UnicodeStringTable->Language;\r
while (0 != *LanguageString) {\r
- for (Index = 0 ;LanguageString[Index] != 0 && LanguageString[Index] != ';'; Index++);\r
- if (AsciiStrnCmp(LanguageString, Language, Index) == 0) {\r
+ for (Index = 0; LanguageString[Index] != 0 && LanguageString[Index] != ';'; Index++) {\r
+ }\r
+\r
+ if (AsciiStrnCmp (LanguageString, Language, Index) == 0) {\r
*UnicodeString = UnicodeStringTable->UnicodeString;\r
return EFI_SUCCESS;\r
}\r
+\r
LanguageString += Index;\r
- for (Index = 0 ;LanguageString[Index] != 0 && LanguageString[Index] == ';'; Index++);\r
+ for (Index = 0; LanguageString[Index] != 0 && LanguageString[Index] == ';'; Index++) {\r
+ }\r
}\r
+\r
UnicodeStringTable++;\r
}\r
\r
return EFI_UNSUPPORTED;\r
}\r
\r
-\r
/**\r
This function adds a Unicode string to UnicodeStringTable.\r
\r
//\r
// Make sure the parameter are valid\r
//\r
- if (Language == NULL || UnicodeString == NULL || UnicodeStringTable == NULL) {\r
+ if ((Language == NULL) || (UnicodeString == NULL) || (UnicodeStringTable == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
while (*SupportedLanguages != 0) {\r
if (CompareIso639LanguageCode (Language, SupportedLanguages)) {\r
-\r
//\r
// Determine the size of the Unicode String Table by looking for a NULL Language entry\r
//\r
//\r
if (*UnicodeStringTable != NULL) {\r
CopyMem (\r
- NewUnicodeStringTable,\r
- *UnicodeStringTable,\r
- NumberOfEntries * sizeof (EFI_UNICODE_STRING_TABLE)\r
- );\r
+ NewUnicodeStringTable,\r
+ *UnicodeStringTable,\r
+ NumberOfEntries * sizeof (EFI_UNICODE_STRING_TABLE)\r
+ );\r
}\r
\r
//\r
//\r
// Compute the length of the Unicode String\r
//\r
- for (UnicodeStringLength = 0; UnicodeString[UnicodeStringLength] != 0; UnicodeStringLength++)\r
- ;\r
+ for (UnicodeStringLength = 0; UnicodeString[UnicodeStringLength] != 0; UnicodeStringLength++) {\r
+ }\r
\r
//\r
// Allocate space for a copy of the Unicode String\r
//\r
NewUnicodeStringTable[NumberOfEntries].UnicodeString = AllocateCopyPool (\r
- (UnicodeStringLength + 1) * sizeof (CHAR16),\r
- UnicodeString\r
- );\r
+ (UnicodeStringLength + 1) * sizeof (CHAR16),\r
+ UnicodeString\r
+ );\r
if (NewUnicodeStringTable[NumberOfEntries].UnicodeString == NULL) {\r
FreePool (NewUnicodeStringTable[NumberOfEntries].Language);\r
FreePool (NewUnicodeStringTable);\r
//\r
// Mark the end of the Unicode String Table\r
//\r
- NewUnicodeStringTable[NumberOfEntries + 1].Language = NULL;\r
- NewUnicodeStringTable[NumberOfEntries + 1].UnicodeString = NULL;\r
+ NewUnicodeStringTable[NumberOfEntries + 1].Language = NULL;\r
+ NewUnicodeStringTable[NumberOfEntries + 1].UnicodeString = NULL;\r
\r
//\r
// Free the old Unicode String Table\r
return EFI_UNSUPPORTED;\r
}\r
\r
-\r
/**\r
This function adds the Null-terminated Unicode string specified by UnicodeString\r
to UnicodeStringTable.\r
//\r
// Make sure the parameter are valid\r
//\r
- if (Language == NULL || UnicodeString == NULL || UnicodeStringTable == NULL) {\r
+ if ((Language == NULL) || (UnicodeString == NULL) || (UnicodeStringTable == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
Found = TRUE;\r
break;\r
}\r
+\r
SupportedLanguages += 3;\r
}\r
} else {\r
- Found = !IsLanguageSupported(SupportedLanguages, Language);\r
+ Found = !IsLanguageSupported (SupportedLanguages, Language);\r
}\r
+\r
//\r
// If Language is not a member of SupportedLanguages, then return EFI_UNSUPPORTED\r
//\r
LanguageString = OldUnicodeStringTable->Language;\r
\r
while (*LanguageString != 0) {\r
- for (Index = 0; LanguageString[Index] != 0 && LanguageString[Index] != ';'; Index++);\r
+ for (Index = 0; LanguageString[Index] != 0 && LanguageString[Index] != ';'; Index++) {\r
+ }\r
\r
if (AsciiStrnCmp (Language, LanguageString, Index) == 0) {\r
return EFI_ALREADY_STARTED;\r
}\r
+\r
LanguageString += Index;\r
- for (; *LanguageString != 0 && *LanguageString == ';'; LanguageString++);\r
+ for ( ; *LanguageString != 0 && *LanguageString == ';'; LanguageString++) {\r
+ }\r
}\r
+\r
OldUnicodeStringTable++;\r
NumberOfEntries++;\r
}\r
//\r
// Allocate space for a copy of the Language specifier\r
//\r
- NewUnicodeStringTable[NumberOfEntries].Language = AllocateCopyPool (AsciiStrSize(Language), Language);\r
+ NewUnicodeStringTable[NumberOfEntries].Language = AllocateCopyPool (AsciiStrSize (Language), Language);\r
if (NewUnicodeStringTable[NumberOfEntries].Language == NULL) {\r
FreePool (NewUnicodeStringTable);\r
return EFI_OUT_OF_RESOURCES;\r
//\r
// Compute the length of the Unicode String\r
//\r
- for (UnicodeStringLength = 0; UnicodeString[UnicodeStringLength] != 0; UnicodeStringLength++);\r
+ for (UnicodeStringLength = 0; UnicodeString[UnicodeStringLength] != 0; UnicodeStringLength++) {\r
+ }\r
\r
//\r
// Allocate space for a copy of the Unicode String\r
//\r
// Mark the end of the Unicode String Table\r
//\r
- NewUnicodeStringTable[NumberOfEntries + 1].Language = NULL;\r
- NewUnicodeStringTable[NumberOfEntries + 1].UnicodeString = NULL;\r
+ NewUnicodeStringTable[NumberOfEntries + 1].Language = NULL;\r
+ NewUnicodeStringTable[NumberOfEntries + 1].UnicodeString = NULL;\r
\r
//\r
// Free the old Unicode String Table\r
IN EFI_UNICODE_STRING_TABLE *UnicodeStringTable\r
)\r
{\r
- UINTN Index;\r
+ UINTN Index;\r
\r
//\r
// If the Unicode String Table is NULL, then it is already freed\r
// Loop through the Unicode String Table until we reach the end of table marker\r
//\r
for (Index = 0; UnicodeStringTable[Index].Language != NULL; Index++) {\r
-\r
//\r
// Free the Language string from the Unicode String Table\r
//\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
Returns the status whether get the variable success. The function retrieves\r
variable through the UEFI Runtime Service GetVariable(). The\r
BufferSize = 0;\r
*Value = NULL;\r
if (Size != NULL) {\r
- *Size = 0;\r
+ *Size = 0;\r
}\r
\r
- Status = gRT->GetVariable ((CHAR16 *) Name, (EFI_GUID *) Guid, NULL, &BufferSize, *Value);\r
+ Status = gRT->GetVariable ((CHAR16 *)Name, (EFI_GUID *)Guid, NULL, &BufferSize, *Value);\r
if (Status != EFI_BUFFER_TOO_SMALL) {\r
return Status;\r
}\r
//\r
// Get the variable data.\r
//\r
- Status = gRT->GetVariable ((CHAR16 *) Name, (EFI_GUID *) Guid, NULL, &BufferSize, *Value);\r
+ Status = gRT->GetVariable ((CHAR16 *)Name, (EFI_GUID *)Guid, NULL, &BufferSize, *Value);\r
if (EFI_ERROR (Status)) {\r
- FreePool(*Value);\r
+ FreePool (*Value);\r
*Value = NULL;\r
}\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
-GetVariable3(\r
- IN CONST CHAR16 *Name,\r
- IN CONST EFI_GUID *Guid,\r
- OUT VOID **Value,\r
- OUT UINTN *Size OPTIONAL,\r
- OUT UINT32 *Attr OPTIONAL\r
+GetVariable3 (\r
+ IN CONST CHAR16 *Name,\r
+ IN CONST EFI_GUID *Guid,\r
+ OUT VOID **Value,\r
+ OUT UINTN *Size OPTIONAL,\r
+ OUT UINT32 *Attr OPTIONAL\r
)\r
{\r
EFI_STATUS Status;\r
UINTN BufferSize;\r
\r
- ASSERT(Name != NULL && Guid != NULL && Value != NULL);\r
+ ASSERT (Name != NULL && Guid != NULL && Value != NULL);\r
\r
//\r
// Try to get the variable size.\r
//\r
BufferSize = 0;\r
- *Value = NULL;\r
+ *Value = NULL;\r
if (Size != NULL) {\r
*Size = 0;\r
}\r
*Attr = 0;\r
}\r
\r
- Status = gRT->GetVariable((CHAR16 *)Name, (EFI_GUID *)Guid, Attr, &BufferSize, *Value);\r
+ Status = gRT->GetVariable ((CHAR16 *)Name, (EFI_GUID *)Guid, Attr, &BufferSize, *Value);\r
if (Status != EFI_BUFFER_TOO_SMALL) {\r
return Status;\r
}\r
//\r
// Allocate buffer to get the variable.\r
//\r
- *Value = AllocatePool(BufferSize);\r
- ASSERT(*Value != NULL);\r
+ *Value = AllocatePool (BufferSize);\r
+ ASSERT (*Value != NULL);\r
if (*Value == NULL) {\r
return EFI_OUT_OF_RESOURCES;\r
}\r
//\r
// Get the variable data.\r
//\r
- Status = gRT->GetVariable((CHAR16 *)Name, (EFI_GUID *)Guid, Attr, &BufferSize, *Value);\r
- if (EFI_ERROR(Status)) {\r
- FreePool(*Value);\r
+ Status = gRT->GetVariable ((CHAR16 *)Name, (EFI_GUID *)Guid, Attr, &BufferSize, *Value);\r
+ if (EFI_ERROR (Status)) {\r
+ FreePool (*Value);\r
*Value = NULL;\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
GetEfiGlobalVariable2 (\r
- IN CONST CHAR16 *Name,\r
- OUT VOID **Value,\r
- OUT UINTN *Size OPTIONAL\r
+ IN CONST CHAR16 *Name,\r
+ OUT VOID **Value,\r
+ OUT UINTN *Size OPTIONAL\r
)\r
{\r
return GetVariable2 (Name, &gEfiGlobalVariableGuid, Value, Size);\r
// If in RFC 4646 mode, then determine the length of the first RFC 4646 language code in Language\r
//\r
if (Iso639Language == 0) {\r
- for (LanguageLength = 0; Language[LanguageLength] != 0 && Language[LanguageLength] != ';'; LanguageLength++);\r
+ for (LanguageLength = 0; Language[LanguageLength] != 0 && Language[LanguageLength] != ';'; LanguageLength++) {\r
+ }\r
}\r
\r
//\r
//\r
// Skip ';' characters in Supported\r
//\r
- for (; *Supported != '\0' && *Supported == ';'; Supported++);\r
+ for ( ; *Supported != '\0' && *Supported == ';'; Supported++) {\r
+ }\r
+\r
//\r
// Determine the length of the next language code in Supported\r
//\r
- for (CompareLength = 0; Supported[CompareLength] != 0 && Supported[CompareLength] != ';'; CompareLength++);\r
+ for (CompareLength = 0; Supported[CompareLength] != 0 && Supported[CompareLength] != ';'; CompareLength++) {\r
+ }\r
+\r
//\r
// If Language is longer than the Supported, then skip to the next language\r
//\r
continue;\r
}\r
}\r
+\r
//\r
// See if the first LanguageLength characters in Supported match Language\r
//\r
if (BestLanguage == NULL) {\r
return NULL;\r
}\r
+\r
return CopyMem (BestLanguage, Supported, CompareLength);\r
}\r
}\r
//\r
// If RFC 4646 mode, then trim Language from the right to the next '-' character\r
//\r
- for (LanguageLength--; LanguageLength > 0 && Language[LanguageLength] != '-'; LanguageLength--);\r
+ for (LanguageLength--; LanguageLength > 0 && Language[LanguageLength] != '-'; LanguageLength--) {\r
+ }\r
}\r
}\r
}\r
+\r
VA_END (Args);\r
\r
//\r
//\r
// Check input parameters\r
//\r
- if (Protocol == NULL || NoProtocols == NULL || Buffer == NULL) {\r
+ if ((Protocol == NULL) || (NoProtocols == NULL) || (Buffer == NULL)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
// Initialze output parameters\r
//\r
*NoProtocols = 0;\r
- *Buffer = NULL;\r
+ *Buffer = NULL;\r
\r
//\r
// Retrieve the array of handles that support Protocol\r
gBS->FreePool (HandleBuffer);\r
return EFI_OUT_OF_RESOURCES;\r
}\r
+\r
ZeroMem (*Buffer, NoHandles * sizeof (VOID *));\r
\r
//\r
IN UINT64 Attributes\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_HANDLE FileSystemHandle;\r
- EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FileSystem;\r
- EFI_FILE_PROTOCOL *LastFile;\r
- FILEPATH_DEVICE_PATH *FilePathNode;\r
- CHAR16 *AlignedPathName;\r
- CHAR16 *PathName;\r
- EFI_FILE_PROTOCOL *NextFile;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE FileSystemHandle;\r
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FileSystem;\r
+ EFI_FILE_PROTOCOL *LastFile;\r
+ FILEPATH_DEVICE_PATH *FilePathNode;\r
+ CHAR16 *AlignedPathName;\r
+ CHAR16 *PathName;\r
+ EFI_FILE_PROTOCOL *NextFile;\r
\r
if (File == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
+\r
*File = NULL;\r
\r
if (FilePath == NULL) {\r
if (EFI_ERROR (Status)) {\r
return Status;\r
}\r
+\r
Status = gBS->OpenProtocol (\r
FileSystemHandle,\r
&gEfiSimpleFileSystemProtocolGuid,\r
// Traverse the device path nodes relative to the filesystem.\r
//\r
while (!IsDevicePathEnd (*FilePath)) {\r
- if (DevicePathType (*FilePath) != MEDIA_DEVICE_PATH ||\r
- DevicePathSubType (*FilePath) != MEDIA_FILEPATH_DP) {\r
+ if ((DevicePathType (*FilePath) != MEDIA_DEVICE_PATH) ||\r
+ (DevicePathSubType (*FilePath) != MEDIA_FILEPATH_DP))\r
+ {\r
Status = EFI_INVALID_PARAMETER;\r
goto CloseLastFile;\r
}\r
+\r
FilePathNode = (FILEPATH_DEVICE_PATH *)*FilePath;\r
\r
//\r
//\r
if ((UINTN)FilePathNode->PathName % sizeof *FilePathNode->PathName == 0) {\r
AlignedPathName = NULL;\r
- PathName = FilePathNode->PathName;\r
+ PathName = FilePathNode->PathName;\r
} else {\r
AlignedPathName = AllocateCopyPool (\r
(DevicePathNodeLength (FilePathNode) -\r
Status = EFI_OUT_OF_RESOURCES;\r
goto CloseLastFile;\r
}\r
+\r
PathName = AlignedPathName;\r
}\r
\r
if (AlignedPathName != NULL) {\r
FreePool (AlignedPathName);\r
}\r
+\r
if (EFI_ERROR (Status)) {\r
goto CloseLastFile;\r
}\r
// Advance to the next device path node.\r
//\r
LastFile->Close (LastFile);\r
- LastFile = NextFile;\r
+ LastFile = NextFile;\r
*FilePath = NextDevicePathNode (FilePathNode);\r
}\r
\r
#ifndef __UEFI_LIB_INTERNAL_H_\r
#define __UEFI_LIB_INTERNAL_H_\r
\r
-\r
#include <Uefi.h>\r
#include <Protocol/DriverBinding.h>\r
#include <Protocol/ComponentName.h>\r
\r
#include "UefiLibInternal.h"\r
\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_GRAPHICS_OUTPUT_BLT_PIXEL mEfiColors[16] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GRAPHICS_OUTPUT_BLT_PIXEL mEfiColors[16] = {\r
{ 0x00, 0x00, 0x00, 0x00 },\r
{ 0x98, 0x00, 0x00, 0x00 },\r
{ 0x00, 0x98, 0x00, 0x00 },\r
UINTN BufferSize;\r
\r
ASSERT (Format != NULL);\r
- ASSERT (((UINTN) Format & BIT0) == 0);\r
+ ASSERT (((UINTN)Format & BIT0) == 0);\r
ASSERT (Console != NULL);\r
\r
BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);\r
\r
- Buffer = (CHAR16 *) AllocatePool(BufferSize);\r
+ Buffer = (CHAR16 *)AllocatePool (BufferSize);\r
ASSERT (Buffer != NULL);\r
\r
Return = UnicodeVSPrint (Buffer, BufferSize, Format, Marker);\r
\r
- if (Console != NULL && Return > 0) {\r
+ if ((Console != NULL) && (Return > 0)) {\r
//\r
// To be extra safe make sure Console has been initialized\r
//\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN Return;\r
+ VA_LIST Marker;\r
+ UINTN Return;\r
\r
VA_START (Marker, Format);\r
\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN Return;\r
+ VA_LIST Marker;\r
+ UINTN Return;\r
\r
VA_START (Marker, Format);\r
\r
- Return = InternalPrint( Format, gST->StdErr, Marker);\r
+ Return = InternalPrint (Format, gST->StdErr, Marker);\r
\r
VA_END (Marker);\r
\r
return Return;\r
}\r
\r
-\r
/**\r
Internal function which prints a formatted ASCII string to the console output device\r
specified by Console\r
\r
BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);\r
\r
- Buffer = (CHAR16 *) AllocatePool(BufferSize);\r
+ Buffer = (CHAR16 *)AllocatePool (BufferSize);\r
ASSERT (Buffer != NULL);\r
\r
Return = UnicodeVSPrintAsciiFormat (Buffer, BufferSize, Format, Marker);\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN Return;\r
+ VA_LIST Marker;\r
+ UINTN Return;\r
+\r
ASSERT (Format != NULL);\r
\r
VA_START (Marker, Format);\r
\r
- Return = AsciiInternalPrint( Format, gST->ConOut, Marker);\r
+ Return = AsciiInternalPrint (Format, gST->ConOut, Marker);\r
\r
VA_END (Marker);\r
\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- UINTN Return;\r
+ VA_LIST Marker;\r
+ UINTN Return;\r
\r
ASSERT (Format != NULL);\r
\r
VA_START (Marker, Format);\r
\r
- Return = AsciiInternalPrint( Format, gST->StdErr, Marker);\r
+ Return = AsciiInternalPrint (Format, gST->StdErr, Marker);\r
\r
VA_END (Marker);\r
\r
**/\r
UINTN\r
InternalPrintGraphic (\r
- IN UINTN PointX,\r
- IN UINTN PointY,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Foreground,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Background,\r
- IN CHAR16 *Buffer,\r
- IN UINTN PrintNum\r
+ IN UINTN PointX,\r
+ IN UINTN PointY,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Foreground,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Background,\r
+ IN CHAR16 *Buffer,\r
+ IN UINTN PrintNum\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 HorizontalResolution;\r
- UINT32 VerticalResolution;\r
- UINT32 ColorDepth;\r
- UINT32 RefreshRate;\r
- EFI_HII_FONT_PROTOCOL *HiiFont;\r
- EFI_IMAGE_OUTPUT *Blt;\r
- EFI_FONT_DISPLAY_INFO FontInfo;\r
- EFI_HII_ROW_INFO *RowInfoArray;\r
- UINTN RowInfoArraySize;\r
- EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;\r
- EFI_UGA_DRAW_PROTOCOL *UgaDraw;\r
- EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *Sto;\r
- EFI_HANDLE ConsoleHandle;\r
- UINTN Width;\r
- UINTN Height;\r
- UINTN Delta;\r
-\r
- HorizontalResolution = 0;\r
- VerticalResolution = 0;\r
- Blt = NULL;\r
- RowInfoArray = NULL;\r
+ EFI_STATUS Status;\r
+ UINT32 HorizontalResolution;\r
+ UINT32 VerticalResolution;\r
+ UINT32 ColorDepth;\r
+ UINT32 RefreshRate;\r
+ EFI_HII_FONT_PROTOCOL *HiiFont;\r
+ EFI_IMAGE_OUTPUT *Blt;\r
+ EFI_FONT_DISPLAY_INFO FontInfo;\r
+ EFI_HII_ROW_INFO *RowInfoArray;\r
+ UINTN RowInfoArraySize;\r
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;\r
+ EFI_UGA_DRAW_PROTOCOL *UgaDraw;\r
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *Sto;\r
+ EFI_HANDLE ConsoleHandle;\r
+ UINTN Width;\r
+ UINTN Height;\r
+ UINTN Delta;\r
+\r
+ HorizontalResolution = 0;\r
+ VerticalResolution = 0;\r
+ Blt = NULL;\r
+ RowInfoArray = NULL;\r
\r
ConsoleHandle = gST->ConsoleOutHandle;\r
\r
- ASSERT( ConsoleHandle != NULL);\r
+ ASSERT (ConsoleHandle != NULL);\r
\r
Status = gBS->HandleProtocol (\r
ConsoleHandle,\r
&gEfiGraphicsOutputProtocolGuid,\r
- (VOID **) &GraphicsOutput\r
+ (VOID **)&GraphicsOutput\r
);\r
\r
UgaDraw = NULL;\r
Status = gBS->HandleProtocol (\r
ConsoleHandle,\r
&gEfiUgaDrawProtocolGuid,\r
- (VOID **) &UgaDraw\r
+ (VOID **)&UgaDraw\r
);\r
}\r
+\r
if (EFI_ERROR (Status)) {\r
goto Error;\r
}\r
Status = gBS->HandleProtocol (\r
ConsoleHandle,\r
&gEfiSimpleTextOutProtocolGuid,\r
- (VOID **) &Sto\r
+ (VOID **)&Sto\r
);\r
\r
if (EFI_ERROR (Status)) {\r
\r
if (GraphicsOutput != NULL) {\r
HorizontalResolution = GraphicsOutput->Mode->Info->HorizontalResolution;\r
- VerticalResolution = GraphicsOutput->Mode->Info->VerticalResolution;\r
- } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+ VerticalResolution = GraphicsOutput->Mode->Info->VerticalResolution;\r
+ } else if ((UgaDraw != NULL) && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
UgaDraw->GetMode (UgaDraw, &HorizontalResolution, &VerticalResolution, &ColorDepth, &RefreshRate);\r
} else {\r
goto Error;\r
}\r
\r
- ASSERT ((HorizontalResolution != 0) && (VerticalResolution !=0));\r
+ ASSERT ((HorizontalResolution != 0) && (VerticalResolution != 0));\r
\r
- Status = gBS->LocateProtocol (&gEfiHiiFontProtocolGuid, NULL, (VOID **) &HiiFont);\r
+ Status = gBS->LocateProtocol (&gEfiHiiFontProtocolGuid, NULL, (VOID **)&HiiFont);\r
if (EFI_ERROR (Status)) {\r
goto Error;\r
}\r
\r
- Blt = (EFI_IMAGE_OUTPUT *) AllocateZeroPool (sizeof (EFI_IMAGE_OUTPUT));\r
+ Blt = (EFI_IMAGE_OUTPUT *)AllocateZeroPool (sizeof (EFI_IMAGE_OUTPUT));\r
ASSERT (Blt != NULL);\r
\r
- Blt->Width = (UINT16) (HorizontalResolution);\r
- Blt->Height = (UINT16) (VerticalResolution);\r
+ Blt->Width = (UINT16)(HorizontalResolution);\r
+ Blt->Height = (UINT16)(VerticalResolution);\r
\r
ZeroMem (&FontInfo, sizeof (EFI_FONT_DISPLAY_INFO));\r
\r
sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)\r
);\r
}\r
+\r
if (Background != NULL) {\r
CopyMem (&FontInfo.BackgroundColor, Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));\r
} else {\r
Blt->Image.Screen = GraphicsOutput;\r
\r
Status = HiiFont->StringToImage (\r
- HiiFont,\r
- EFI_HII_IGNORE_IF_NO_GLYPH | EFI_HII_OUT_FLAG_CLIP |\r
- EFI_HII_OUT_FLAG_CLIP_CLEAN_X | EFI_HII_OUT_FLAG_CLIP_CLEAN_Y |\r
- EFI_HII_IGNORE_LINE_BREAK | EFI_HII_DIRECT_TO_SCREEN,\r
- Buffer,\r
- &FontInfo,\r
- &Blt,\r
- PointX,\r
- PointY,\r
- &RowInfoArray,\r
- &RowInfoArraySize,\r
- NULL\r
- );\r
+ HiiFont,\r
+ EFI_HII_IGNORE_IF_NO_GLYPH | EFI_HII_OUT_FLAG_CLIP |\r
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_X | EFI_HII_OUT_FLAG_CLIP_CLEAN_Y |\r
+ EFI_HII_IGNORE_LINE_BREAK | EFI_HII_DIRECT_TO_SCREEN,\r
+ Buffer,\r
+ &FontInfo,\r
+ &Blt,\r
+ PointX,\r
+ PointY,\r
+ &RowInfoArray,\r
+ &RowInfoArraySize,\r
+ NULL\r
+ );\r
if (EFI_ERROR (Status)) {\r
goto Error;\r
}\r
-\r
} else if (FeaturePcdGet (PcdUgaConsumeSupport)) {\r
- ASSERT (UgaDraw!= NULL);\r
+ ASSERT (UgaDraw != NULL);\r
\r
//\r
// Ensure Width * Height * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow.\r
goto Error;\r
}\r
\r
- Blt->Image.Bitmap = AllocateZeroPool ((UINT32) Blt->Width * Blt->Height * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));\r
+ Blt->Image.Bitmap = AllocateZeroPool ((UINT32)Blt->Width * Blt->Height * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));\r
ASSERT (Blt->Image.Bitmap != NULL);\r
\r
//\r
// we ask StringToImage to print the string to blt buffer, then blt to device using UgaDraw.\r
//\r
Status = HiiFont->StringToImage (\r
- HiiFont,\r
- EFI_HII_IGNORE_IF_NO_GLYPH | EFI_HII_OUT_FLAG_CLIP |\r
- EFI_HII_OUT_FLAG_CLIP_CLEAN_X | EFI_HII_OUT_FLAG_CLIP_CLEAN_Y |\r
- EFI_HII_IGNORE_LINE_BREAK,\r
- Buffer,\r
- &FontInfo,\r
- &Blt,\r
- PointX,\r
- PointY,\r
- &RowInfoArray,\r
- &RowInfoArraySize,\r
- NULL\r
- );\r
+ HiiFont,\r
+ EFI_HII_IGNORE_IF_NO_GLYPH | EFI_HII_OUT_FLAG_CLIP |\r
+ EFI_HII_OUT_FLAG_CLIP_CLEAN_X | EFI_HII_OUT_FLAG_CLIP_CLEAN_Y |\r
+ EFI_HII_IGNORE_LINE_BREAK,\r
+ Buffer,\r
+ &FontInfo,\r
+ &Blt,\r
+ PointX,\r
+ PointY,\r
+ &RowInfoArray,\r
+ &RowInfoArraySize,\r
+ NULL\r
+ );\r
\r
if (!EFI_ERROR (Status)) {\r
ASSERT (RowInfoArray != NULL);\r
Height = 0;\r
Delta = 0;\r
}\r
+\r
Status = UgaDraw->Blt (\r
UgaDraw,\r
- (EFI_UGA_PIXEL *) Blt->Image.Bitmap,\r
+ (EFI_UGA_PIXEL *)Blt->Image.Bitmap,\r
EfiUgaBltBufferToVideo,\r
PointX,\r
PointY,\r
} else {\r
goto Error;\r
}\r
+\r
FreePool (Blt->Image.Bitmap);\r
} else {\r
goto Error;\r
}\r
+\r
//\r
// Calculate the number of actual printed characters\r
//\r
if (Blt != NULL) {\r
FreePool (Blt);\r
}\r
+\r
return 0;\r
}\r
\r
UINTN\r
EFIAPI\r
PrintXY (\r
- IN UINTN PointX,\r
- IN UINTN PointY,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
- IN CONST CHAR16 *Format,\r
+ IN UINTN PointX,\r
+ IN UINTN PointY,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
+ IN CONST CHAR16 *Format,\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- CHAR16 *Buffer;\r
- UINTN BufferSize;\r
- UINTN PrintNum;\r
- UINTN ReturnNum;\r
+ VA_LIST Marker;\r
+ CHAR16 *Buffer;\r
+ UINTN BufferSize;\r
+ UINTN PrintNum;\r
+ UINTN ReturnNum;\r
\r
ASSERT (Format != NULL);\r
- ASSERT (((UINTN) Format & BIT0) == 0);\r
+ ASSERT (((UINTN)Format & BIT0) == 0);\r
\r
VA_START (Marker, Format);\r
\r
BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);\r
\r
- Buffer = (CHAR16 *) AllocatePool (BufferSize);\r
+ Buffer = (CHAR16 *)AllocatePool (BufferSize);\r
ASSERT (Buffer != NULL);\r
\r
PrintNum = UnicodeVSPrint (Buffer, BufferSize, Format, Marker);\r
UINTN\r
EFIAPI\r
AsciiPrintXY (\r
- IN UINTN PointX,\r
- IN UINTN PointY,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
- IN CONST CHAR8 *Format,\r
+ IN UINTN PointX,\r
+ IN UINTN PointY,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *ForeGround OPTIONAL,\r
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BackGround OPTIONAL,\r
+ IN CONST CHAR8 *Format,\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- CHAR16 *Buffer;\r
- UINTN BufferSize;\r
- UINTN PrintNum;\r
- UINTN ReturnNum;\r
+ VA_LIST Marker;\r
+ CHAR16 *Buffer;\r
+ UINTN BufferSize;\r
+ UINTN PrintNum;\r
+ UINTN ReturnNum;\r
\r
ASSERT (Format != NULL);\r
\r
\r
BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);\r
\r
- Buffer = (CHAR16 *) AllocatePool (BufferSize);\r
+ Buffer = (CHAR16 *)AllocatePool (BufferSize);\r
ASSERT (Buffer != NULL);\r
\r
PrintNum = UnicodeSPrintAsciiFormat (Buffer, BufferSize, Format, Marker);\r
@return Null-terminated Unicode string is that is the formatted\r
string appended to String.\r
**/\r
-CHAR16*\r
+CHAR16 *\r
EFIAPI\r
CatVSPrint (\r
- IN CHAR16 *String OPTIONAL,\r
+ IN CHAR16 *String OPTIONAL,\r
IN CONST CHAR16 *FormatString,\r
IN VA_LIST Marker\r
)\r
{\r
- UINTN CharactersRequired;\r
- UINTN SizeRequired;\r
- CHAR16 *BufferToReturn;\r
- VA_LIST ExtraMarker;\r
+ UINTN CharactersRequired;\r
+ UINTN SizeRequired;\r
+ CHAR16 *BufferToReturn;\r
+ VA_LIST ExtraMarker;\r
\r
VA_COPY (ExtraMarker, Marker);\r
- CharactersRequired = SPrintLength(FormatString, ExtraMarker);\r
+ CharactersRequired = SPrintLength (FormatString, ExtraMarker);\r
VA_END (ExtraMarker);\r
\r
if (String != NULL) {\r
- SizeRequired = StrSize(String) + (CharactersRequired * sizeof(CHAR16));\r
+ SizeRequired = StrSize (String) + (CharactersRequired * sizeof (CHAR16));\r
} else {\r
- SizeRequired = sizeof(CHAR16) + (CharactersRequired * sizeof(CHAR16));\r
+ SizeRequired = sizeof (CHAR16) + (CharactersRequired * sizeof (CHAR16));\r
}\r
\r
- BufferToReturn = AllocatePool(SizeRequired);\r
+ BufferToReturn = AllocatePool (SizeRequired);\r
\r
if (BufferToReturn == NULL) {\r
return NULL;\r
}\r
\r
if (String != NULL) {\r
- StrCpyS(BufferToReturn, SizeRequired / sizeof(CHAR16), String);\r
+ StrCpyS (BufferToReturn, SizeRequired / sizeof (CHAR16), String);\r
}\r
\r
- UnicodeVSPrint(BufferToReturn + StrLen(BufferToReturn), (CharactersRequired+1) * sizeof(CHAR16), FormatString, Marker);\r
+ UnicodeVSPrint (BufferToReturn + StrLen (BufferToReturn), (CharactersRequired+1) * sizeof (CHAR16), FormatString, Marker);\r
\r
- ASSERT(StrSize(BufferToReturn)==SizeRequired);\r
+ ASSERT (StrSize (BufferToReturn) == SizeRequired);\r
\r
return (BufferToReturn);\r
}\r
CHAR16 *\r
EFIAPI\r
CatSPrint (\r
- IN CHAR16 *String OPTIONAL,\r
+ IN CHAR16 *String OPTIONAL,\r
IN CONST CHAR16 *FormatString,\r
...\r
)\r
{\r
- VA_LIST Marker;\r
- CHAR16 *NewString;\r
+ VA_LIST Marker;\r
+ CHAR16 *NewString;\r
\r
VA_START (Marker, FormatString);\r
- NewString = CatVSPrint(String, FormatString, Marker);\r
+ NewString = CatVSPrint (String, FormatString, Marker);\r
VA_END (Marker);\r
return NewString;\r
}\r
\r
**/\r
\r
-\r
-\r
#include "UefiLibInternal.h"\r
\r
/**\r
} else {\r
WorkerNotifyFunction = NotifyFunction;\r
}\r
+\r
Status = gBS->CreateEventEx (\r
EVT_NOTIFY_SIGNAL,\r
NotifyTpl,\r
} else {\r
WorkerNotifyFunction = NotifyFunction;\r
}\r
+\r
Status = gBS->CreateEventEx (\r
EVT_NOTIFY_SIGNAL,\r
NotifyTpl,\r
return Status;\r
}\r
\r
-\r
/**\r
Create, Signal, and Close the Ready to Boot event using EfiSignalEventReadyToBoot().\r
\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_EVENT ReadyToBootEvent;\r
+ EFI_STATUS Status;\r
+ EFI_EVENT ReadyToBootEvent;\r
\r
Status = EfiCreateEventReadyToBoot (&ReadyToBootEvent);\r
if (!EFI_ERROR (Status)) {\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_EVENT LegacyBootEvent;\r
+ EFI_STATUS Status;\r
+ EFI_EVENT LegacyBootEvent;\r
\r
Status = EfiCreateEventLegacyBoot (&LegacyBootEvent);\r
if (!EFI_ERROR (Status)) {\r
}\r
}\r
\r
-\r
/**\r
Check to see if the Firmware Volume (FV) Media Device Path is valid\r
\r
{\r
ASSERT (FvDevicePathNode != NULL);\r
\r
- if (DevicePathType (&FvDevicePathNode->Header) == MEDIA_DEVICE_PATH &&\r
- DevicePathSubType (&FvDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP) {\r
- return (EFI_GUID *) &FvDevicePathNode->FvFileName;\r
+ if ((DevicePathType (&FvDevicePathNode->Header) == MEDIA_DEVICE_PATH) &&\r
+ (DevicePathSubType (&FvDevicePathNode->Header) == MEDIA_PIWG_FW_FILE_DP))\r
+ {\r
+ return (EFI_GUID *)&FvDevicePathNode->FvFileName;\r
}\r
\r
return NULL;\r
}\r
\r
-\r
/**\r
Initialize a Firmware Volume (FV) Media Device Path node.\r
\r
//\r
// Use the new Device path that does not conflict with the UEFI\r
//\r
- FvDevicePathNode->Header.Type = MEDIA_DEVICE_PATH;\r
- FvDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP;\r
+ FvDevicePathNode->Header.Type = MEDIA_DEVICE_PATH;\r
+ FvDevicePathNode->Header.SubType = MEDIA_PIWG_FW_FILE_DP;\r
SetDevicePathNodeLength (&FvDevicePathNode->Header, sizeof (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH));\r
\r
CopyGuid (&FvDevicePathNode->FvFileName, NameGuid);\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
\r
-\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/BaseMemoryLib.h>\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- return (VOID *) (UINTN) Memory;\r
+\r
+ return (VOID *)(UINTN)Memory;\r
}\r
\r
/**\r
EFI_STATUS Status;\r
\r
ASSERT (Pages != 0);\r
- Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
if (Pages == 0) {\r
return NULL;\r
}\r
+\r
if (Alignment > EFI_PAGE_SIZE) {\r
//\r
// Calculate the total number of pages since alignment is larger than page size.\r
//\r
- AlignmentMask = Alignment - 1;\r
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
+ AlignmentMask = Alignment - 1;\r
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
//\r
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r
//\r
ASSERT (RealPages > Pages);\r
\r
- Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, RealPages, &Memory);\r
+ Status = gBS->AllocatePages (AllocateAnyPages, MemoryType, RealPages, &Memory);\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;\r
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);\r
+\r
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r
if (UnalignedPages > 0) {\r
//\r
// Free first unaligned page(s).\r
Status = gBS->FreePages (Memory, UnalignedPages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
+\r
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
UnalignedPages = RealPages - Pages - UnalignedPages;\r
if (UnalignedPages > 0) {\r
if (EFI_ERROR (Status)) {\r
return NULL;\r
}\r
- AlignedMemory = (UINTN) Memory;\r
+\r
+ AlignedMemory = (UINTN)Memory;\r
}\r
- return (VOID *) AlignedMemory;\r
+\r
+ return (VOID *)AlignedMemory;\r
}\r
\r
/**\r
EFI_STATUS Status;\r
\r
ASSERT (Pages != 0);\r
- Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);\r
+ Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, Pages);\r
ASSERT_EFI_ERROR (Status);\r
}\r
\r
if (EFI_ERROR (Status)) {\r
Memory = NULL;\r
}\r
+\r
return Memory;\r
}\r
\r
if (Memory != NULL) {\r
Memory = ZeroMem (Memory, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *Memory;\r
\r
ASSERT (Buffer != NULL);\r
- ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN) Buffer + 1));\r
+ ASSERT (AllocationSize <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
\r
Memory = InternalAllocatePool (PoolType, AllocationSize);\r
if (Memory != NULL) {\r
- Memory = CopyMem (Memory, Buffer, AllocationSize);\r
+ Memory = CopyMem (Memory, Buffer, AllocationSize);\r
}\r
+\r
return Memory;\r
}\r
\r
VOID *NewBuffer;\r
\r
NewBuffer = InternalAllocateZeroPool (PoolType, NewSize);\r
- if (NewBuffer != NULL && OldBuffer != NULL) {\r
+ if ((NewBuffer != NULL) && (OldBuffer != NULL)) {\r
CopyMem (NewBuffer, OldBuffer, MIN (OldSize, NewSize));\r
FreePool (OldBuffer);\r
}\r
+\r
return NewBuffer;\r
}\r
\r
VOID\r
EFIAPI\r
FreePool (\r
- IN VOID *Buffer\r
+ IN VOID *Buffer\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
Status = gBS->FreePool (Buffer);\r
ASSERT_EFI_ERROR (Status);\r
}\r
-\r
IN UINTN Length\r
)\r
{\r
- if (Length == 0 || DestinationBuffer == SourceBuffer) {\r
+ if ((Length == 0) || (DestinationBuffer == SourceBuffer)) {\r
return 0;\r
}\r
+\r
ASSERT (DestinationBuffer != NULL);\r
ASSERT (SourceBuffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
if (Length == 0) {\r
return DestinationBuffer;\r
}\r
+\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)DestinationBuffer));\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)SourceBuffer));\r
\r
if (DestinationBuffer == SourceBuffer) {\r
return DestinationBuffer;\r
}\r
+\r
return InternalMemCopyMem (DestinationBuffer, SourceBuffer, Length);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *Destination,\r
- IN CONST VOID *Source,\r
- IN UINTN Length\r
+ OUT VOID *Destination,\r
+ IN CONST VOID *Source,\r
+ IN UINTN Length\r
)\r
{\r
- gBS->CopyMem (Destination, (VOID*)Source, Length);\r
+ gBS->CopyMem (Destination, (VOID *)Source, Length);\r
return Destination;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Size,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Size,\r
+ IN UINT8 Value\r
)\r
{\r
gBS->SetMem (Buffer, Size, Value);\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT16*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT16 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT32*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT32 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- for (; Length != 0; Length--) {\r
- ((UINT64*)Buffer)[Length - 1] = Value;\r
+ for ( ; Length != 0; Length--) {\r
+ ((UINT64 *)Buffer)[Length - 1] = Value;\r
}\r
+\r
return Buffer;\r
}\r
\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
)\r
{\r
return InternalMemSetMem (Buffer, Length, 0);\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
)\r
{\r
while ((--Length != 0) &&\r
- (*(INT8*)DestinationBuffer == *(INT8*)SourceBuffer)) {\r
- DestinationBuffer = (INT8*)DestinationBuffer + 1;\r
- SourceBuffer = (INT8*)SourceBuffer + 1;\r
+ (*(INT8 *)DestinationBuffer == *(INT8 *)SourceBuffer))\r
+ {\r
+ DestinationBuffer = (INT8 *)DestinationBuffer + 1;\r
+ SourceBuffer = (INT8 *)SourceBuffer + 1;\r
}\r
- return (INTN)*(UINT8*)DestinationBuffer - (INTN)*(UINT8*)SourceBuffer;\r
+\r
+ return (INTN)*(UINT8 *)DestinationBuffer - (INTN)*(UINT8 *)SourceBuffer;\r
}\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
)\r
{\r
- CONST UINT8 *Pointer;\r
+ CONST UINT8 *Pointer;\r
\r
- Pointer = (CONST UINT8*)Buffer;\r
+ Pointer = (CONST UINT8 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
)\r
{\r
- CONST UINT16 *Pointer;\r
+ CONST UINT16 *Pointer;\r
\r
- Pointer = (CONST UINT16*)Buffer;\r
+ Pointer = (CONST UINT16 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
)\r
{\r
- CONST UINT32 *Pointer;\r
+ CONST UINT32 *Pointer;\r
\r
- Pointer = (CONST UINT32*)Buffer;\r
+ Pointer = (CONST UINT32 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
)\r
{\r
- CONST UINT64 *Pointer;\r
+ CONST UINT64 *Pointer;\r
\r
- Pointer = (CONST UINT64*)Buffer;\r
+ Pointer = (CONST UINT64 *)Buffer;\r
do {\r
if (*(Pointer++) == Value) {\r
return --Pointer;\r
}\r
} while (--Length != 0);\r
+\r
return NULL;\r
}\r
\r
IN UINTN Length\r
)\r
{\r
- CONST UINT8 *BufferData;\r
- UINTN Index;\r
+ CONST UINT8 *BufferData;\r
+ UINTN Index;\r
\r
BufferData = Buffer;\r
for (Index = 0; Index < Length; Index++) {\r
return FALSE;\r
}\r
}\r
+\r
return TRUE;\r
}\r
)\r
{\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid)\r
+ (UINT64 *)DestinationGuid,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid)\r
);\r
WriteUnaligned64 (\r
- (UINT64*)DestinationGuid + 1,\r
- ReadUnaligned64 ((CONST UINT64*)SourceGuid + 1)\r
+ (UINT64 *)DestinationGuid + 1,\r
+ ReadUnaligned64 ((CONST UINT64 *)SourceGuid + 1)\r
);\r
return DestinationGuid;\r
}\r
UINT64 HighPartOfGuid1;\r
UINT64 HighPartOfGuid2;\r
\r
- LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1);\r
- LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2);\r
- HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64*) Guid1 + 1);\r
- HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64*) Guid2 + 1);\r
+ LowPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1);\r
+ LowPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2);\r
+ HighPartOfGuid1 = ReadUnaligned64 ((CONST UINT64 *)Guid1 + 1);\r
+ HighPartOfGuid2 = ReadUnaligned64 ((CONST UINT64 *)Guid2 + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
+ return (BOOLEAN)(LowPartOfGuid1 == LowPartOfGuid2 && HighPartOfGuid1 == HighPartOfGuid2);\r
}\r
\r
/**\r
IN CONST GUID *Guid\r
)\r
{\r
- CONST GUID *GuidPtr;\r
+ CONST GUID *GuidPtr;\r
\r
ASSERT (((UINTN)Buffer & (sizeof (Guid->Data1) - 1)) == 0);\r
ASSERT (Length <= (MAX_ADDRESS - (UINTN)Buffer + 1));\r
ASSERT ((Length & (sizeof (*GuidPtr) - 1)) == 0);\r
\r
- GuidPtr = (GUID*)Buffer;\r
+ GuidPtr = (GUID *)Buffer;\r
Buffer = GuidPtr + Length / sizeof (*GuidPtr);\r
- while (GuidPtr < (CONST GUID*)Buffer) {\r
+ while (GuidPtr < (CONST GUID *)Buffer) {\r
if (CompareGuid (GuidPtr, Guid)) {\r
- return (VOID*)GuidPtr;\r
+ return (VOID *)GuidPtr;\r
}\r
+\r
GuidPtr++;\r
}\r
+\r
return NULL;\r
}\r
\r
UINT64 LowPartOfGuid;\r
UINT64 HighPartOfGuid;\r
\r
- LowPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid);\r
- HighPartOfGuid = ReadUnaligned64 ((CONST UINT64*) Guid + 1);\r
+ LowPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid);\r
+ HighPartOfGuid = ReadUnaligned64 ((CONST UINT64 *)Guid + 1);\r
\r
- return (BOOLEAN) (LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
+ return (BOOLEAN)(LowPartOfGuid == 0 && HighPartOfGuid == 0);\r
}\r
VOID *\r
EFIAPI\r
InternalMemCopyMem (\r
- OUT VOID *Destination,\r
- IN CONST VOID *Source,\r
- IN UINTN Length\r
+ OUT VOID *Destination,\r
+ IN CONST VOID *Source,\r
+ IN UINTN Length\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Size,\r
- IN UINT8 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Size,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem16 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem32 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemSetMem64 (\r
- OUT VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
VOID *\r
EFIAPI\r
InternalMemZeroMem (\r
- OUT VOID *Buffer,\r
- IN UINTN Length\r
+ OUT VOID *Buffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
INTN\r
EFIAPI\r
InternalMemCompareMem (\r
- IN CONST VOID *DestinationBuffer,\r
- IN CONST VOID *SourceBuffer,\r
- IN UINTN Length\r
+ IN CONST VOID *DestinationBuffer,\r
+ IN CONST VOID *SourceBuffer,\r
+ IN UINTN Length\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem8 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT8 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT8 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem16 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT16 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT16 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem32 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT32 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT32 Value\r
);\r
\r
/**\r
CONST VOID *\r
EFIAPI\r
InternalMemScanMem64 (\r
- IN CONST VOID *Buffer,\r
- IN UINTN Length,\r
- IN UINT64 Value\r
+ IN CONST VOID *Buffer,\r
+ IN UINTN Length,\r
+ IN UINT64 Value\r
);\r
\r
/**\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem16 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem32 (Buffer, Length / sizeof (Value), Value);\r
}\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
ASSERT ((Length & (sizeof (Value) - 1)) == 0);\r
\r
- return (VOID*)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
+ return (VOID *)InternalMemScanMem64 (Buffer, Length / sizeof (Value), Value);\r
}\r
if (Length == 0) {\r
return NULL;\r
}\r
+\r
ASSERT (Buffer != NULL);\r
ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Buffer));\r
\r
- return (VOID*)InternalMemScanMem8 (Buffer, Length, Value);\r
+ return (VOID *)InternalMemScanMem8 (Buffer, Length, Value);\r
}\r
\r
/**\r
return ScanMem32 (Buffer, Length, (UINT32)Value);\r
}\r
}\r
-\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_ADDRESS(A, M) \\r
ASSERT (((A) & (~0xfffffff | (M))) == 0)\r
\r
/**\r
//\r
// Global varible to cache pointer to PCI Root Bridge I/O protocol.\r
//\r
-EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL;\r
\r
/**\r
The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r
EFI_STATUS\r
EFIAPI\r
PciLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
\r
- Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mPciRootBridgeIo);\r
+ Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID **)&mPciRootBridgeIo);\r
ASSERT_EFI_ERROR (Status);\r
ASSERT (mPciRootBridgeIo != NULL);\r
\r
UINT8\r
EFIAPI\r
PciRead8 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+ return (UINT8)DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciWrite8 (\r
- IN UINTN Address,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+ return (UINT8)DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciOr8 (\r
- IN UINTN Address,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAnd8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r
+ return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r
+ return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciBitFieldRead8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciBitFieldWrite8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAnd8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciWrite8 (\r
UINT8\r
EFIAPI\r
PciBitFieldAndThenOr8 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciWrite8 (\r
UINT16\r
EFIAPI\r
PciRead16 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+ return (UINT16)DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciWrite16 (\r
- IN UINTN Address,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+ return (UINT16)DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciOr16 (\r
- IN UINTN Address,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAnd16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r
+ return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r
+ return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciBitFieldRead16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciBitFieldWrite16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAnd16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciWrite16 (\r
UINT16\r
EFIAPI\r
PciBitFieldAndThenOr16 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciWrite16 (\r
UINT32\r
EFIAPI\r
PciRead32 (\r
- IN UINTN Address\r
+ IN UINTN Address\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciWrite32 (\r
- IN UINTN Address,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciOr32 (\r
- IN UINTN Address,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciAnd32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (Address, PciRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciBitFieldRead32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciBitFieldWrite32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAnd32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciWrite32 (\r
UINT32\r
EFIAPI\r
PciBitFieldAndThenOr32 (\r
- IN UINTN Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINTN Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciWrite32 (\r
UINTN\r
EFIAPI\r
PciReadBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciWriteBuffer (\r
- IN UINTN StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINTN StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
//\r
// Global variable to record data of PCI Root Bridge I/O Protocol instances\r
//\r
-PCI_ROOT_BRIDGE_DATA *mPciRootBridgeData = NULL;\r
-UINTN mNumberOfPciRootBridges = 0;\r
+PCI_ROOT_BRIDGE_DATA *mPciRootBridgeData = NULL;\r
+UINTN mNumberOfPciRootBridges = 0;\r
\r
/**\r
The constructor function caches data of PCI Root Bridge I/O Protocol instances.\r
EFI_STATUS\r
EFIAPI\r
PciSegmentLibConstructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
- UINTN Index;\r
- UINTN HandleCount;\r
- EFI_HANDLE *HandleBuffer;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
\r
HandleCount = 0;\r
HandleBuffer = NULL;\r
Status = gBS->HandleProtocol (\r
HandleBuffer[Index],\r
&gEfiPciRootBridgeIoProtocolGuid,\r
- (VOID **) &PciRootBridgeIo\r
+ (VOID **)&PciRootBridgeIo\r
);\r
ASSERT_EFI_ERROR (Status);\r
\r
mPciRootBridgeData[Index].PciRootBridgeIo = PciRootBridgeIo;\r
mPciRootBridgeData[Index].SegmentNumber = PciRootBridgeIo->SegmentNumber;\r
\r
- Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r
+ Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **)&Descriptors);\r
ASSERT_EFI_ERROR (Status);\r
\r
while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {\r
mPciRootBridgeData[Index].MaxBusNumber = Descriptors->AddrRangeMax;\r
break;\r
}\r
+\r
Descriptors++;\r
}\r
+\r
ASSERT (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR);\r
}\r
\r
- FreePool(HandleBuffer);\r
+ FreePool (HandleBuffer);\r
\r
return EFI_SUCCESS;\r
}\r
EFI_STATUS\r
EFIAPI\r
PciSegmentLibDestructor (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
FreePool (mPciRootBridgeData);\r
**/\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *\r
PciSegmentLibSearchForRootBridge (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
- UINTN Index;\r
- UINT64 SegmentNumber;\r
- UINT64 BusNumber;\r
+ UINTN Index;\r
+ UINT64 SegmentNumber;\r
+ UINT64 BusNumber;\r
\r
for (Index = 0; Index < mNumberOfPciRootBridges; Index++) {\r
//\r
// Matches the bus number of address with bus number range of protocol instance.\r
//\r
BusNumber = BitFieldRead64 (Address, 20, 27);\r
- if (BusNumber >= mPciRootBridgeData[Index].MinBusNumber && BusNumber <= mPciRootBridgeData[Index].MaxBusNumber) {\r
+ if ((BusNumber >= mPciRootBridgeData[Index].MinBusNumber) && (BusNumber <= mPciRootBridgeData[Index].MaxBusNumber)) {\r
return mPciRootBridgeData[Index].PciRootBridgeIo;\r
}\r
}\r
}\r
+\r
return NULL;\r
}\r
\r
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width\r
)\r
{\r
- UINT32 Data;\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ UINT32 Data;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
\r
PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r
ASSERT (PciRootBridgeIo != NULL);\r
IN UINT32 Data\r
)\r
{\r
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
\r
PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r
ASSERT (PciRootBridgeIo != NULL);\r
UINT8\r
EFIAPI\r
PciSegmentRead8 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
+ return (UINT8)DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentWrite8 (\r
- IN UINT64 Address,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r
\r
- return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
+ return (UINT8)DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAnd8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r
+ return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldRead8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldWrite8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAnd8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT8\r
EFIAPI\r
PciSegmentBitFieldAndThenOr8 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT8 AndData,\r
- IN UINT8 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
)\r
{\r
return PciSegmentWrite8 (\r
UINT16\r
EFIAPI\r
PciSegmentRead16 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
+ return (UINT16)DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentWrite16 (\r
- IN UINT64 Address,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r
\r
- return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
+ return (UINT16)DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAnd16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));\r
}\r
\r
/**\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldRead16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldWrite16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAnd16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT16\r
EFIAPI\r
PciSegmentBitFieldAndThenOr16 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT16 AndData,\r
- IN UINT16 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
)\r
{\r
return PciSegmentWrite16 (\r
UINT32\r
EFIAPI\r
PciSegmentRead32 (\r
- IN UINT64 Address\r
+ IN UINT64 Address\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentWrite32 (\r
- IN UINT64 Address,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
)\r
{\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r
UINT32\r
EFIAPI\r
PciSegmentOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentAnd32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r
UINT32\r
EFIAPI\r
PciSegmentAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldRead32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
)\r
{\r
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldWrite32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 Value\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAnd32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINT32\r
EFIAPI\r
PciSegmentBitFieldAndThenOr32 (\r
- IN UINT64 Address,\r
- IN UINTN StartBit,\r
- IN UINTN EndBit,\r
- IN UINT32 AndData,\r
- IN UINT32 OrData\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
)\r
{\r
return PciSegmentWrite32 (\r
UINTN\r
EFIAPI\r
PciSegmentReadBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- OUT VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
// Read a byte if StartAddress is byte aligned\r
//\r
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r
- StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ StartAddress += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Read a word if StartAddress is word aligned\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
UINTN\r
EFIAPI\r
PciSegmentWriteBuffer (\r
- IN UINT64 StartAddress,\r
- IN UINTN Size,\r
- IN VOID *Buffer\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
)\r
{\r
- UINTN ReturnValue;\r
+ UINTN ReturnValue;\r
\r
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
//\r
// Write a byte if StartAddress is byte aligned\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
StartAddress += sizeof (UINT8);\r
- Size -= sizeof (UINT8);\r
- Buffer = (UINT8*)Buffer + 1;\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8 *)Buffer + 1;\r
}\r
\r
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r
//\r
// Write a word if StartAddress is word aligned\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
while (Size >= sizeof (UINT32)) {\r
//\r
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r
StartAddress += sizeof (UINT32);\r
- Size -= sizeof (UINT32);\r
- Buffer = (UINT32*)Buffer + 1;\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT16)) {\r
//\r
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r
StartAddress += sizeof (UINT16);\r
- Size -= sizeof (UINT16);\r
- Buffer = (UINT16*)Buffer + 1;\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16 *)Buffer + 1;\r
}\r
\r
if (Size >= sizeof (UINT8)) {\r
//\r
// Write the last remaining byte if exist\r
//\r
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r
}\r
\r
return ReturnValue;\r
#ifndef __DXE_PCI_SEGMENT_LIB__\r
#define __DXE_PCI_SEGMENT_LIB__\r
\r
-\r
#include <Protocol/PciRootBridgeIo.h>\r
\r
#include <Library/PciSegmentLib.h>\r
@param M Additional bits to assert to be zero.\r
\r
**/\r
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \\r
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r
\r
/**\r
///\r
/// Driver Lib Module Globals\r
///\r
-EFI_EVENT mEfiVirtualNotifyEvent;\r
-EFI_EVENT mEfiExitBootServicesEvent;\r
-BOOLEAN mEfiGoneVirtual = FALSE;\r
-BOOLEAN mEfiAtRuntime = FALSE;\r
-EFI_RUNTIME_SERVICES *mInternalRT;\r
+EFI_EVENT mEfiVirtualNotifyEvent;\r
+EFI_EVENT mEfiExitBootServicesEvent;\r
+BOOLEAN mEfiGoneVirtual = FALSE;\r
+BOOLEAN mEfiAtRuntime = FALSE;\r
+EFI_RUNTIME_SERVICES *mInternalRT;\r
\r
/**\r
Set AtRuntime flag as TRUE after ExitBootServices.\r
VOID\r
EFIAPI\r
RuntimeLibExitBootServicesEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
mEfiAtRuntime = TRUE;\r
VOID\r
EFIAPI\r
RuntimeLibVirtualNotifyEvent (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
//\r
// Update global for Runtime Services Table and IO\r
//\r
- EfiConvertPointer (0, (VOID **) &mInternalRT);\r
+ EfiConvertPointer (0, (VOID **)&mInternalRT);\r
\r
mEfiGoneVirtual = TRUE;\r
}\r
EFI_STATUS\r
EFIAPI\r
RuntimeDriverLibConstruct (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
return mEfiGoneVirtual;\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service ResetSystem().\r
\r
VOID\r
EFIAPI\r
EfiResetSystem (\r
- IN EFI_RESET_TYPE ResetType,\r
- IN EFI_STATUS ResetStatus,\r
- IN UINTN DataSize,\r
- IN VOID *ResetData OPTIONAL\r
+ IN EFI_RESET_TYPE ResetType,\r
+ IN EFI_STATUS ResetStatus,\r
+ IN UINTN DataSize,\r
+ IN VOID *ResetData OPTIONAL\r
)\r
{\r
mInternalRT->ResetSystem (ResetType, ResetStatus, DataSize, ResetData);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetTime().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiGetTime (\r
- OUT EFI_TIME *Time,\r
- OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL\r
+ OUT EFI_TIME *Time,\r
+ OUT EFI_TIME_CAPABILITIES *Capabilities OPTIONAL\r
)\r
{\r
return mInternalRT->GetTime (Time, Capabilities);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service SetTime().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiSetTime (\r
- IN EFI_TIME *Time\r
+ IN EFI_TIME *Time\r
)\r
{\r
return mInternalRT->SetTime (Time);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetWakeupTime().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiGetWakeupTime (\r
- OUT BOOLEAN *Enabled,\r
- OUT BOOLEAN *Pending,\r
- OUT EFI_TIME *Time\r
+ OUT BOOLEAN *Enabled,\r
+ OUT BOOLEAN *Pending,\r
+ OUT EFI_TIME *Time\r
)\r
{\r
return mInternalRT->GetWakeupTime (Enabled, Pending, Time);\r
}\r
\r
-\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service SetWakeupTime()\r
\r
EFI_STATUS\r
EFIAPI\r
EfiSetWakeupTime (\r
- IN BOOLEAN Enable,\r
- IN EFI_TIME *Time OPTIONAL\r
+ IN BOOLEAN Enable,\r
+ IN EFI_TIME *Time OPTIONAL\r
)\r
{\r
return mInternalRT->SetWakeupTime (Enable, Time);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetVariable().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiGetVariable (\r
- IN CHAR16 *VariableName,\r
- IN EFI_GUID *VendorGuid,\r
- OUT UINT32 *Attributes OPTIONAL,\r
- IN OUT UINTN *DataSize,\r
- OUT VOID *Data\r
+ IN CHAR16 *VariableName,\r
+ IN EFI_GUID *VendorGuid,\r
+ OUT UINT32 *Attributes OPTIONAL,\r
+ IN OUT UINTN *DataSize,\r
+ OUT VOID *Data\r
)\r
{\r
return mInternalRT->GetVariable (VariableName, VendorGuid, Attributes, DataSize, Data);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetNextVariableName().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiGetNextVariableName (\r
- IN OUT UINTN *VariableNameSize,\r
- IN OUT CHAR16 *VariableName,\r
- IN OUT EFI_GUID *VendorGuid\r
+ IN OUT UINTN *VariableNameSize,\r
+ IN OUT CHAR16 *VariableName,\r
+ IN OUT EFI_GUID *VendorGuid\r
)\r
{\r
return mInternalRT->GetNextVariableName (VariableNameSize, VariableName, VendorGuid);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetNextVariableName()\r
\r
EFI_STATUS\r
EFIAPI\r
EfiSetVariable (\r
- IN CHAR16 *VariableName,\r
- IN EFI_GUID *VendorGuid,\r
- IN UINT32 Attributes,\r
- IN UINTN DataSize,\r
- IN VOID *Data\r
+ IN CHAR16 *VariableName,\r
+ IN EFI_GUID *VendorGuid,\r
+ IN UINT32 Attributes,\r
+ IN UINTN DataSize,\r
+ IN VOID *Data\r
)\r
{\r
return mInternalRT->SetVariable (VariableName, VendorGuid, Attributes, DataSize, Data);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service GetNextHighMonotonicCount().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiGetNextHighMonotonicCount (\r
- OUT UINT32 *HighCount\r
+ OUT UINT32 *HighCount\r
)\r
{\r
return mInternalRT->GetNextHighMonotonicCount (HighCount);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service ConvertPointer().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiConvertPointer (\r
- IN UINTN DebugDisposition,\r
- IN OUT VOID **Address\r
+ IN UINTN DebugDisposition,\r
+ IN OUT VOID **Address\r
)\r
{\r
return gRT->ConvertPointer (DebugDisposition, Address);\r
}\r
\r
-\r
/**\r
Determines the new virtual address that is to be used on subsequent memory accesses.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiConvertFunctionPointer (\r
- IN UINTN DebugDisposition,\r
- IN OUT VOID **Address\r
+ IN UINTN DebugDisposition,\r
+ IN OUT VOID **Address\r
)\r
{\r
return EfiConvertPointer (DebugDisposition, Address);\r
}\r
\r
-\r
/**\r
Convert the standard Lib double linked list to a virtual mapping.\r
\r
EFI_STATUS\r
EFIAPI\r
EfiConvertList (\r
- IN UINTN DebugDisposition,\r
- IN OUT LIST_ENTRY *ListHead\r
+ IN UINTN DebugDisposition,\r
+ IN OUT LIST_ENTRY *ListHead\r
)\r
{\r
LIST_ENTRY *Link;\r
\r
EfiConvertPointer (\r
Link->ForwardLink == ListHead ? DebugDisposition : 0,\r
- (VOID **) &Link->ForwardLink\r
+ (VOID **)&Link->ForwardLink\r
);\r
\r
EfiConvertPointer (\r
Link->BackLink == ListHead ? DebugDisposition : 0,\r
- (VOID **) &Link->BackLink\r
+ (VOID **)&Link->BackLink\r
);\r
\r
Link = NextLink;\r
} while (Link != ListHead);\r
+\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service SetVirtualAddressMap().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiSetVirtualAddressMap (\r
- IN UINTN MemoryMapSize,\r
- IN UINTN DescriptorSize,\r
- IN UINT32 DescriptorVersion,\r
- IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap\r
+ IN UINTN MemoryMapSize,\r
+ IN UINTN DescriptorSize,\r
+ IN UINT32 DescriptorVersion,\r
+ IN CONST EFI_MEMORY_DESCRIPTOR *VirtualMap\r
)\r
{\r
return mInternalRT->SetVirtualAddressMap (\r
MemoryMapSize,\r
DescriptorSize,\r
DescriptorVersion,\r
- (EFI_MEMORY_DESCRIPTOR *) VirtualMap\r
+ (EFI_MEMORY_DESCRIPTOR *)VirtualMap\r
);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service UpdateCapsule().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiUpdateCapsule (\r
- IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
- IN UINTN CapsuleCount,\r
- IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL\r
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
+ IN UINTN CapsuleCount,\r
+ IN EFI_PHYSICAL_ADDRESS ScatterGatherList OPTIONAL\r
)\r
{\r
return mInternalRT->UpdateCapsule (\r
);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service QueryCapsuleCapabilities().\r
\r
EFI_STATUS\r
EFIAPI\r
EfiQueryCapsuleCapabilities (\r
- IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
- IN UINTN CapsuleCount,\r
- OUT UINT64 *MaximumCapsuleSize,\r
- OUT EFI_RESET_TYPE *ResetType\r
+ IN EFI_CAPSULE_HEADER **CapsuleHeaderArray,\r
+ IN UINTN CapsuleCount,\r
+ OUT UINT64 *MaximumCapsuleSize,\r
+ OUT EFI_RESET_TYPE *ResetType\r
)\r
{\r
return mInternalRT->QueryCapsuleCapabilities (\r
);\r
}\r
\r
-\r
/**\r
This service is a wrapper for the UEFI Runtime Service QueryVariableInfo().\r
\r
\r
**/\r
\r
-\r
#include <Uefi.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
\r
#include <IndustryStandard/Scsi.h>\r
\r
-\r
- //\r
- // Scsi Command Length\r
- //\r
+//\r
+// Scsi Command Length\r
+//\r
#define EFI_SCSI_OP_LENGTH_SIX 0x6\r
#define EFI_SCSI_OP_LENGTH_TEN 0xa\r
#define EFI_SCSI_OP_LENGTH_TWELVE 0xc\r
/// The SCSI request packet to send to the SCSI controller specified by\r
/// the device handle.\r
///\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
///\r
/// The length of the output sense data.\r
///\r
- UINT8 *SenseDataLength;\r
+ UINT8 *SenseDataLength;\r
///\r
/// The status of the SCSI host adapter.\r
///\r
- UINT8 *HostAdapterStatus;\r
+ UINT8 *HostAdapterStatus;\r
///\r
/// The status of the target SCSI device.\r
///\r
- UINT8 *TargetStatus;\r
+ UINT8 *TargetStatus;\r
///\r
/// The length of the data buffer for the SCSI read/write command.\r
///\r
- UINT32 *DataLength;\r
+ UINT32 *DataLength;\r
///\r
/// The caller event to be signaled when the SCSI read/write command\r
/// completes.\r
///\r
- EFI_EVENT CallerEvent;\r
+ EFI_EVENT CallerEvent;\r
} EFI_SCSI_LIB_ASYNC_CONTEXT;\r
\r
-\r
-\r
/**\r
Execute Test Unit Ready SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_SIX);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = NULL;\r
- CommandPacket.InTransferLength= 0;\r
- CommandPacket.OutDataBuffer = NULL;\r
- CommandPacket.OutTransferLength= 0;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = NULL;\r
+ CommandPacket.InTransferLength = 0;\r
+ CommandPacket.OutDataBuffer = NULL;\r
+ CommandPacket.OutTransferLength = 0;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Test Unit Ready Command\r
//\r
Cdb[0] = EFI_SCSI_OP_TEST_UNIT_READY;\r
- CommandPacket.CdbLength = (UINT8) EFI_SCSI_OP_LENGTH_SIX;\r
+ CommandPacket.CdbLength = (UINT8)EFI_SCSI_OP_LENGTH_SIX;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Inquiry SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *InquiryDataBuffer OPTIONAL,\r
IN OUT UINT32 *InquiryDataLength,\r
IN BOOLEAN EnableVitalProductData,\r
IN UINT8 PageCode\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_SIX);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = InquiryDataBuffer;\r
- CommandPacket.InTransferLength= *InquiryDataLength;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.SenseDataLength = *SenseDataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = InquiryDataBuffer;\r
+ CommandPacket.InTransferLength = *InquiryDataLength;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.SenseDataLength = *SenseDataLength;\r
+ CommandPacket.Cdb = Cdb;\r
\r
- Cdb[0] = EFI_SCSI_OP_INQUIRY;\r
+ Cdb[0] = EFI_SCSI_OP_INQUIRY;\r
if (EnableVitalProductData) {\r
Cdb[1] |= 0x01;\r
Cdb[2] = PageCode;\r
*InquiryDataLength = 0xff;\r
}\r
\r
- Cdb[4] = (UINT8) (*InquiryDataLength);\r
- CommandPacket.CdbLength = (UINT8) EFI_SCSI_OP_LENGTH_SIX;\r
+ Cdb[4] = (UINT8)(*InquiryDataLength);\r
+ CommandPacket.CdbLength = (UINT8)EFI_SCSI_OP_LENGTH_SIX;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *InquiryDataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *InquiryDataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Inquiry SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *InquiryDataBuffer OPTIONAL,\r
IN OUT UINT32 *InquiryDataLength,\r
IN BOOLEAN EnableVitalProductData\r
EFI_STATUS\r
EFIAPI\r
ScsiModeSense10Command (\r
- IN EFI_SCSI_IO_PROTOCOL *ScsiIo,\r
- IN UINT64 Timeout,\r
- IN OUT VOID *SenseData OPTIONAL,\r
- IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
- IN OUT VOID *DataBuffer OPTIONAL,\r
- IN OUT UINT32 *DataLength,\r
- IN UINT8 DBDField OPTIONAL,\r
- IN UINT8 PageControl,\r
- IN UINT8 PageCode\r
+ IN EFI_SCSI_IO_PROTOCOL *ScsiIo,\r
+ IN UINT64 Timeout,\r
+ IN OUT VOID *SenseData OPTIONAL,\r
+ IN OUT UINT8 *SenseDataLength,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
+ IN OUT VOID *DataBuffer OPTIONAL,\r
+ IN OUT UINT32 *DataLength,\r
+ IN UINT8 DBDField OPTIONAL,\r
+ IN UINT8 PageControl,\r
+ IN UINT8 PageCode\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_TEN);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = DataBuffer;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.InTransferLength= *DataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = DataBuffer;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.InTransferLength = *DataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Mode Sense (10) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_MODE_SEN10;\r
+ Cdb[0] = EFI_SCSI_OP_MODE_SEN10;\r
//\r
// DBDField is in Cdb[1] bit3 of (bit7..0)\r
//\r
- Cdb[1] = (UINT8) ((DBDField << 3) & 0x08);\r
+ Cdb[1] = (UINT8)((DBDField << 3) & 0x08);\r
//\r
// PageControl is in Cdb[2] bit7..6, PageCode is in Cdb[2] bit5..0\r
//\r
- Cdb[2] = (UINT8) (((PageControl << 6) & 0xc0) | (PageCode & 0x3f));\r
- Cdb[7] = (UINT8) (*DataLength >> 8);\r
- Cdb[8] = (UINT8) (*DataLength);\r
+ Cdb[2] = (UINT8)(((PageControl << 6) & 0xc0) | (PageCode & 0x3f));\r
+ Cdb[7] = (UINT8)(*DataLength >> 8);\r
+ Cdb[8] = (UINT8)(*DataLength);\r
\r
CommandPacket.CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Request Sense SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIX];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_SIX);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = SenseData;\r
- CommandPacket.SenseData = NULL;\r
- CommandPacket.InTransferLength= *SenseDataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = SenseData;\r
+ CommandPacket.SenseData = NULL;\r
+ CommandPacket.InTransferLength = *SenseDataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Request Sense Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_REQUEST_SENSE;\r
- Cdb[4] = (UINT8) (*SenseDataLength);\r
+ Cdb[0] = EFI_SCSI_OP_REQUEST_SENSE;\r
+ Cdb[4] = (UINT8)(*SenseDataLength);\r
\r
- CommandPacket.CdbLength = (UINT8) EFI_SCSI_OP_LENGTH_SIX;\r
+ CommandPacket.CdbLength = (UINT8)EFI_SCSI_OP_LENGTH_SIX;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = 0;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = (UINT8) CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = (UINT8)CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Read Capacity SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN BOOLEAN Pmi\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_TEN);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = DataBuffer;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.InTransferLength= *DataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = DataBuffer;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.InTransferLength = *DataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Read Capacity Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ_CAPACITY;\r
+ Cdb[0] = EFI_SCSI_OP_READ_CAPACITY;\r
if (!Pmi) {\r
//\r
// Partial medium indicator,if Pmi is FALSE, the Cdb.2 ~ Cdb.5 MUST BE ZERO.\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Read Capacity SCSI 16 command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN BOOLEAN Pmi\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[16];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[16];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, 16);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = DataBuffer;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.InTransferLength= *DataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = DataBuffer;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.InTransferLength = *DataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Read Capacity Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ_CAPACITY16;\r
- Cdb[1] = 0x10;\r
+ Cdb[0] = EFI_SCSI_OP_READ_CAPACITY16;\r
+ Cdb[1] = 0x10;\r
if (!Pmi) {\r
//\r
// Partial medium indicator,if Pmi is FALSE, the Cdb.2 ~ Cdb.9 MUST BE ZERO.\r
Cdb[14] |= 0x01;\r
}\r
\r
- Cdb[13] = 0x20;\r
+ Cdb[13] = 0x20;\r
CommandPacket.CdbLength = 16;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Read(10) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN UINT32 SectorSize\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_TEN);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = DataBuffer;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.InTransferLength= *DataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = DataBuffer;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.InTransferLength = *DataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Read (10) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ10;\r
+ Cdb[0] = EFI_SCSI_OP_READ10;\r
WriteUnaligned32 ((UINT32 *)&Cdb[2], SwapBytes32 (StartLba));\r
- WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16) SectorSize));\r
+ WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16)SectorSize));\r
\r
CommandPacket.CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Write(10) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN UINT32 SectorSize\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
//\r
// Fill Cdb for Write (10) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_WRITE10;\r
- Cdb[1] = EFI_SCSI_BLOCK_FUA;\r
+ Cdb[0] = EFI_SCSI_OP_WRITE10;\r
+ Cdb[1] = EFI_SCSI_BLOCK_FUA;\r
WriteUnaligned32 ((UINT32 *)&Cdb[2], SwapBytes32 (StartLba));\r
- WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16) SectorSize));\r
+ WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16)SectorSize));\r
\r
CommandPacket.CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_OUT;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.OutTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.OutTransferLength;\r
\r
return Status;\r
}\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN UINT32 SectorSize\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIXTEEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIXTEEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
//\r
// Fill Cdb for Read (16) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ16;\r
+ Cdb[0] = EFI_SCSI_OP_READ16;\r
WriteUnaligned64 ((UINT64 *)&Cdb[2], SwapBytes64 (StartLba));\r
WriteUnaligned32 ((UINT32 *)&Cdb[10], SwapBytes32 (SectorSize));\r
\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Write(16) SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN UINT32 SectorSize\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIXTEEN];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_SIXTEEN];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
//\r
// Fill Cdb for Write (16) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_WRITE16;\r
- Cdb[1] = EFI_SCSI_BLOCK_FUA;\r
+ Cdb[0] = EFI_SCSI_OP_WRITE16;\r
+ Cdb[1] = EFI_SCSI_BLOCK_FUA;\r
WriteUnaligned64 ((UINT64 *)&Cdb[2], SwapBytes64 (StartLba));\r
WriteUnaligned32 ((UINT32 *)&Cdb[10], SwapBytes32 (SectorSize));\r
\r
CommandPacket.DataDirection = EFI_SCSI_DATA_OUT;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *DataLength = CommandPacket.OutTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *DataLength = CommandPacket.OutTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Security Protocol In SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN UINT8 SecurityProtocol,\r
IN UINT16 SecurityProtocolSpecific,\r
IN BOOLEAN Inc512,\r
IN UINTN DataLength,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
- OUT UINTN *TransferLength\r
+ OUT UINTN *TransferLength\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TWELVE];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TWELVE];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
ZeroMem (&CommandPacket, sizeof (EFI_SCSI_IO_SCSI_REQUEST_PACKET));\r
ZeroMem (Cdb, EFI_SCSI_OP_LENGTH_TWELVE);\r
\r
- CommandPacket.Timeout = Timeout;\r
- CommandPacket.InDataBuffer = DataBuffer;\r
- CommandPacket.SenseData = SenseData;\r
- CommandPacket.InTransferLength = (UINT32) DataLength;\r
- CommandPacket.Cdb = Cdb;\r
+ CommandPacket.Timeout = Timeout;\r
+ CommandPacket.InDataBuffer = DataBuffer;\r
+ CommandPacket.SenseData = SenseData;\r
+ CommandPacket.InTransferLength = (UINT32)DataLength;\r
+ CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Security Protocol In Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_SECURITY_PROTOCOL_IN;\r
- Cdb[1] = SecurityProtocol;\r
+ Cdb[0] = EFI_SCSI_OP_SECURITY_PROTOCOL_IN;\r
+ Cdb[1] = SecurityProtocol;\r
WriteUnaligned16 ((UINT16 *)&Cdb[2], SwapBytes16 (SecurityProtocolSpecific));\r
\r
if (Inc512) {\r
if (DataLength % 512 != 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- Cdb[4] = BIT7;\r
- WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32) DataLength / 512));\r
+\r
+ Cdb[4] = BIT7;\r
+ WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32)DataLength / 512));\r
} else {\r
- WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32) DataLength));\r
+ WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32)DataLength));\r
}\r
\r
CommandPacket.CdbLength = EFI_SCSI_OP_LENGTH_TWELVE;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_IN;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
- *TransferLength = (UINTN) CommandPacket.InTransferLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *TransferLength = (UINTN)CommandPacket.InTransferLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Execute Security Protocol Out SCSI command on a specific SCSI target.\r
\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN UINT8 SecurityProtocol,\r
IN UINT16 SecurityProtocolSpecific,\r
IN BOOLEAN Inc512,\r
IN OUT VOID *DataBuffer OPTIONAL\r
)\r
{\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 Cdb[EFI_SCSI_OP_LENGTH_TWELVE];\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 Cdb[EFI_SCSI_OP_LENGTH_TWELVE];\r
\r
ASSERT (SenseDataLength != NULL);\r
ASSERT (HostAdapterStatus != NULL);\r
CommandPacket.Timeout = Timeout;\r
CommandPacket.OutDataBuffer = DataBuffer;\r
CommandPacket.SenseData = SenseData;\r
- CommandPacket.OutTransferLength = (UINT32) DataLength;\r
+ CommandPacket.OutTransferLength = (UINT32)DataLength;\r
CommandPacket.Cdb = Cdb;\r
//\r
// Fill Cdb for Security Protocol Out Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_SECURITY_PROTOCOL_OUT;\r
- Cdb[1] = SecurityProtocol;\r
+ Cdb[0] = EFI_SCSI_OP_SECURITY_PROTOCOL_OUT;\r
+ Cdb[1] = SecurityProtocol;\r
WriteUnaligned16 ((UINT16 *)&Cdb[2], SwapBytes16 (SecurityProtocolSpecific));\r
\r
if (Inc512) {\r
if (DataLength % 512 != 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
- Cdb[4] = BIT7;\r
- WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32) DataLength / 512));\r
+\r
+ Cdb[4] = BIT7;\r
+ WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32)DataLength / 512));\r
} else {\r
- WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32) DataLength));\r
+ WriteUnaligned32 ((UINT32 *)&Cdb[6], SwapBytes32 ((UINT32)DataLength));\r
}\r
\r
CommandPacket.CdbLength = EFI_SCSI_OP_LENGTH_TWELVE;\r
CommandPacket.DataDirection = EFI_SCSI_DATA_OUT;\r
CommandPacket.SenseDataLength = *SenseDataLength;\r
\r
- Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
+ Status = ScsiIo->ExecuteScsiCommand (ScsiIo, &CommandPacket, NULL);\r
\r
- *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
- *TargetStatus = CommandPacket.TargetStatus;\r
- *SenseDataLength = CommandPacket.SenseDataLength;\r
+ *HostAdapterStatus = CommandPacket.HostAdapterStatus;\r
+ *TargetStatus = CommandPacket.TargetStatus;\r
+ *SenseDataLength = CommandPacket.SenseDataLength;\r
\r
return Status;\r
}\r
\r
-\r
/**\r
Internal helper notify function in which update the result of the\r
non-blocking SCSI Read/Write commands and signal caller event.\r
IN VOID *Context\r
)\r
{\r
- EFI_SCSI_LIB_ASYNC_CONTEXT *LibContext;\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
- EFI_EVENT CallerEvent;\r
+ EFI_SCSI_LIB_ASYNC_CONTEXT *LibContext;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
+ EFI_EVENT CallerEvent;\r
\r
- LibContext = (EFI_SCSI_LIB_ASYNC_CONTEXT *) Context;\r
+ LibContext = (EFI_SCSI_LIB_ASYNC_CONTEXT *)Context;\r
CommandPacket = &LibContext->CommandPacket;\r
- CallerEvent = LibContext->CallerEvent;\r
+ CallerEvent = LibContext->CallerEvent;\r
\r
//\r
// Update SCSI Read/Write operation results\r
//\r
- *LibContext->SenseDataLength = CommandPacket->SenseDataLength;\r
- *LibContext->HostAdapterStatus = CommandPacket->HostAdapterStatus;\r
- *LibContext->TargetStatus = CommandPacket->TargetStatus;\r
+ *LibContext->SenseDataLength = CommandPacket->SenseDataLength;\r
+ *LibContext->HostAdapterStatus = CommandPacket->HostAdapterStatus;\r
+ *LibContext->TargetStatus = CommandPacket->TargetStatus;\r
if (CommandPacket->InDataBuffer != NULL) {\r
- *LibContext->DataLength = CommandPacket->InTransferLength;\r
+ *LibContext->DataLength = CommandPacket->InTransferLength;\r
} else {\r
- *LibContext->DataLength = CommandPacket->OutTransferLength;\r
+ *LibContext->DataLength = CommandPacket->OutTransferLength;\r
}\r
\r
if (CommandPacket->Cdb != NULL) {\r
FreePool (CommandPacket->Cdb);\r
}\r
+\r
FreePool (Context);\r
\r
gBS->CloseEvent (Event);\r
gBS->SignalEvent (CallerEvent);\r
}\r
\r
-\r
/**\r
Execute blocking/non-blocking Read(10) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
)\r
{\r
- EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 *Cdb;\r
- EFI_EVENT SelfEvent;\r
+ EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 *Cdb;\r
+ EFI_EVENT SelfEvent;\r
\r
if (Event == NULL) {\r
return ScsiRead10Command (\r
goto ErrorExit;\r
}\r
\r
- Context->SenseDataLength = SenseDataLength;\r
- Context->HostAdapterStatus = HostAdapterStatus;\r
- Context->TargetStatus = TargetStatus;\r
- Context->CallerEvent = Event;\r
+ Context->SenseDataLength = SenseDataLength;\r
+ Context->HostAdapterStatus = HostAdapterStatus;\r
+ Context->TargetStatus = TargetStatus;\r
+ Context->CallerEvent = Event;\r
\r
CommandPacket = &Context->CommandPacket;\r
CommandPacket->Timeout = Timeout;\r
//\r
// Fill Cdb for Read (10) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ10;\r
+ Cdb[0] = EFI_SCSI_OP_READ10;\r
WriteUnaligned32 ((UINT32 *)&Cdb[2], SwapBytes32 (StartLba));\r
- WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16) SectorSize));\r
+ WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16)SectorSize));\r
\r
- CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
- CommandPacket->DataDirection = EFI_SCSI_DATA_IN;\r
- CommandPacket->SenseDataLength = *SenseDataLength;\r
+ CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
+ CommandPacket->DataDirection = EFI_SCSI_DATA_IN;\r
+ CommandPacket->SenseDataLength = *SenseDataLength;\r
\r
//\r
// Create Event\r
Context,\r
&SelfEvent\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
\r
Status = ScsiIo->ExecuteScsiCommand (ScsiIo, CommandPacket, SelfEvent);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
//\r
// Since ScsiLibNotify() will not be signaled if ExecuteScsiCommand()\r
// returns with error, close the event here.\r
return Status;\r
}\r
\r
-\r
/**\r
Execute blocking/non-blocking Write(10) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT32 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
)\r
{\r
- EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 *Cdb;\r
- EFI_EVENT SelfEvent;\r
+ EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 *Cdb;\r
+ EFI_EVENT SelfEvent;\r
\r
if (Event == NULL) {\r
return ScsiWrite10Command (\r
goto ErrorExit;\r
}\r
\r
- Context->SenseDataLength = SenseDataLength;\r
- Context->HostAdapterStatus = HostAdapterStatus;\r
- Context->TargetStatus = TargetStatus;\r
- Context->CallerEvent = Event;\r
+ Context->SenseDataLength = SenseDataLength;\r
+ Context->HostAdapterStatus = HostAdapterStatus;\r
+ Context->TargetStatus = TargetStatus;\r
+ Context->CallerEvent = Event;\r
\r
CommandPacket = &Context->CommandPacket;\r
CommandPacket->Timeout = Timeout;\r
//\r
// Fill Cdb for Write (10) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_WRITE10;\r
+ Cdb[0] = EFI_SCSI_OP_WRITE10;\r
WriteUnaligned32 ((UINT32 *)&Cdb[2], SwapBytes32 (StartLba));\r
- WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16) SectorSize));\r
+ WriteUnaligned16 ((UINT16 *)&Cdb[7], SwapBytes16 ((UINT16)SectorSize));\r
\r
- CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
- CommandPacket->DataDirection = EFI_SCSI_DATA_OUT;\r
- CommandPacket->SenseDataLength = *SenseDataLength;\r
+ CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_TEN;\r
+ CommandPacket->DataDirection = EFI_SCSI_DATA_OUT;\r
+ CommandPacket->SenseDataLength = *SenseDataLength;\r
\r
//\r
// Create Event\r
Context,\r
&SelfEvent\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
\r
Status = ScsiIo->ExecuteScsiCommand (ScsiIo, CommandPacket, SelfEvent);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
//\r
// Since ScsiLibNotify() will not be signaled if ExecuteScsiCommand()\r
// returns with error, close the event here.\r
return Status;\r
}\r
\r
-\r
/**\r
Execute blocking/non-blocking Read(16) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
)\r
{\r
- EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 *Cdb;\r
- EFI_EVENT SelfEvent;\r
+ EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 *Cdb;\r
+ EFI_EVENT SelfEvent;\r
\r
if (Event == NULL) {\r
return ScsiRead16Command (\r
goto ErrorExit;\r
}\r
\r
- Context->SenseDataLength = SenseDataLength;\r
- Context->HostAdapterStatus = HostAdapterStatus;\r
- Context->TargetStatus = TargetStatus;\r
- Context->CallerEvent = Event;\r
+ Context->SenseDataLength = SenseDataLength;\r
+ Context->HostAdapterStatus = HostAdapterStatus;\r
+ Context->TargetStatus = TargetStatus;\r
+ Context->CallerEvent = Event;\r
\r
CommandPacket = &Context->CommandPacket;\r
CommandPacket->Timeout = Timeout;\r
//\r
// Fill Cdb for Read (16) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_READ16;\r
+ Cdb[0] = EFI_SCSI_OP_READ16;\r
WriteUnaligned64 ((UINT64 *)&Cdb[2], SwapBytes64 (StartLba));\r
WriteUnaligned32 ((UINT32 *)&Cdb[10], SwapBytes32 (SectorSize));\r
\r
- CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_SIXTEEN;\r
- CommandPacket->DataDirection = EFI_SCSI_DATA_IN;\r
- CommandPacket->SenseDataLength = *SenseDataLength;\r
+ CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_SIXTEEN;\r
+ CommandPacket->DataDirection = EFI_SCSI_DATA_IN;\r
+ CommandPacket->SenseDataLength = *SenseDataLength;\r
\r
//\r
// Create Event\r
Context,\r
&SelfEvent\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
\r
Status = ScsiIo->ExecuteScsiCommand (ScsiIo, CommandPacket, SelfEvent);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
//\r
// Since ScsiLibNotify() will not be signaled if ExecuteScsiCommand()\r
// returns with error, close the event here.\r
return Status;\r
}\r
\r
-\r
/**\r
Execute blocking/non-blocking Write(16) SCSI command on a specific SCSI\r
target.\r
IN UINT64 Timeout,\r
IN OUT VOID *SenseData OPTIONAL,\r
IN OUT UINT8 *SenseDataLength,\r
- OUT UINT8 *HostAdapterStatus,\r
- OUT UINT8 *TargetStatus,\r
+ OUT UINT8 *HostAdapterStatus,\r
+ OUT UINT8 *TargetStatus,\r
IN OUT VOID *DataBuffer OPTIONAL,\r
IN OUT UINT32 *DataLength,\r
IN UINT64 StartLba,\r
IN EFI_EVENT Event OPTIONAL\r
)\r
{\r
- EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
- EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
- EFI_STATUS Status;\r
- UINT8 *Cdb;\r
- EFI_EVENT SelfEvent;\r
+ EFI_SCSI_LIB_ASYNC_CONTEXT *Context;\r
+ EFI_SCSI_IO_SCSI_REQUEST_PACKET *CommandPacket;\r
+ EFI_STATUS Status;\r
+ UINT8 *Cdb;\r
+ EFI_EVENT SelfEvent;\r
\r
if (Event == NULL) {\r
return ScsiWrite16Command (\r
goto ErrorExit;\r
}\r
\r
- Context->SenseDataLength = SenseDataLength;\r
- Context->HostAdapterStatus = HostAdapterStatus;\r
- Context->TargetStatus = TargetStatus;\r
- Context->CallerEvent = Event;\r
+ Context->SenseDataLength = SenseDataLength;\r
+ Context->HostAdapterStatus = HostAdapterStatus;\r
+ Context->TargetStatus = TargetStatus;\r
+ Context->CallerEvent = Event;\r
\r
CommandPacket = &Context->CommandPacket;\r
CommandPacket->Timeout = Timeout;\r
//\r
// Fill Cdb for Write (16) Command\r
//\r
- Cdb[0] = EFI_SCSI_OP_WRITE16;\r
+ Cdb[0] = EFI_SCSI_OP_WRITE16;\r
WriteUnaligned64 ((UINT64 *)&Cdb[2], SwapBytes64 (StartLba));\r
WriteUnaligned32 ((UINT32 *)&Cdb[10], SwapBytes32 (SectorSize));\r
\r
- CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_SIXTEEN;\r
- CommandPacket->DataDirection = EFI_SCSI_DATA_OUT;\r
- CommandPacket->SenseDataLength = *SenseDataLength;\r
+ CommandPacket->CdbLength = EFI_SCSI_OP_LENGTH_SIXTEEN;\r
+ CommandPacket->DataDirection = EFI_SCSI_DATA_OUT;\r
+ CommandPacket->SenseDataLength = *SenseDataLength;\r
\r
//\r
// Create Event\r
Context,\r
&SelfEvent\r
);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
goto ErrorExit;\r
}\r
\r
Status = ScsiIo->ExecuteScsiCommand (ScsiIo, CommandPacket, SelfEvent);\r
- if (EFI_ERROR(Status)) {\r
+ if (EFI_ERROR (Status)) {\r
//\r
// Since ScsiLibNotify() will not be signaled if ExecuteScsiCommand()\r
// returns with error, close the event here.\r
EFI_STATUS\r
EFIAPI\r
UsbGetHidDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ OUT EFI_USB_HID_DESCRIPTOR *HidDescriptor\r
)\r
{\r
UINT32 Status;\r
EFI_STATUS Result;\r
EFI_USB_DEVICE_REQUEST Request;\r
\r
- ASSERT(UsbIo != NULL);\r
- ASSERT(HidDescriptor != NULL);\r
+ ASSERT (UsbIo != NULL);\r
+ ASSERT (HidDescriptor != NULL);\r
\r
Request.RequestType = USB_HID_GET_DESCRIPTOR_REQ_TYPE;\r
Request.Request = USB_REQ_GET_DESCRIPTOR;\r
- Request.Value = (UINT16) (USB_DESC_TYPE_HID << 8);\r
+ Request.Value = (UINT16)(USB_DESC_TYPE_HID << 8);\r
Request.Index = Interface;\r
- Request.Length = (UINT16) sizeof (EFI_USB_HID_DESCRIPTOR);\r
+ Request.Length = (UINT16)sizeof (EFI_USB_HID_DESCRIPTOR);\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
\r
return Result;\r
-\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetReportDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT16 DescriptorLength,\r
- OUT UINT8 *DescriptorBuffer\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT16 DescriptorLength,\r
+ OUT UINT8 *DescriptorBuffer\r
)\r
{\r
UINT32 Status;\r
//\r
Request.RequestType = USB_HID_GET_DESCRIPTOR_REQ_TYPE;\r
Request.Request = USB_REQ_GET_DESCRIPTOR;\r
- Request.Value = (UINT16) (USB_DESC_TYPE_REPORT << 8);\r
+ Request.Value = (UINT16)(USB_DESC_TYPE_REPORT << 8);\r
Request.Index = Interface;\r
Request.Length = DescriptorLength;\r
\r
);\r
\r
return Result;\r
-\r
}\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
UsbGetProtocolRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- OUT UINT8 *Protocol\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ OUT UINT8 *Protocol\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_GET_REQ_TYPE;\r
- Request.Request = EFI_USB_GET_PROTOCOL_REQUEST;\r
- Request.Value = 0;\r
- Request.Index = Interface;\r
- Request.Length = 1;\r
+ Request.Request = EFI_USB_GET_PROTOCOL_REQUEST;\r
+ Request.Value = 0;\r
+ Request.Index = Interface;\r
+ Request.Length = 1;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
return Result;\r
}\r
\r
-\r
-\r
/**\r
Set the HID protocol of the specified USB HID interface.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetProtocolRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 Protocol\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 Protocol\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_SET_REQ_TYPE;\r
- Request.Request = EFI_USB_SET_PROTOCOL_REQUEST;\r
- Request.Value = Protocol;\r
- Request.Index = Interface;\r
- Request.Length = 0;\r
+ Request.Request = EFI_USB_SET_PROTOCOL_REQUEST;\r
+ Request.Value = Protocol;\r
+ Request.Index = Interface;\r
+ Request.Length = 0;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
return Result;\r
}\r
\r
-\r
/**\r
Set the idle rate of the specified USB HID report.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetIdleRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 Duration\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 Duration\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_SET_REQ_TYPE;\r
- Request.Request = EFI_USB_SET_IDLE_REQUEST;\r
- Request.Value = (UINT16) ((Duration << 8) | ReportId);\r
- Request.Index = Interface;\r
- Request.Length = 0;\r
+ Request.Request = EFI_USB_SET_IDLE_REQUEST;\r
+ Request.Value = (UINT16)((Duration << 8) | ReportId);\r
+ Request.Index = Interface;\r
+ Request.Length = 0;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
return Result;\r
}\r
\r
-\r
/**\r
Get the idle rate of the specified USB HID report.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetIdleRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- OUT UINT8 *Duration\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ OUT UINT8 *Duration\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_GET_REQ_TYPE;\r
- Request.Request = EFI_USB_GET_IDLE_REQUEST;\r
- Request.Value = ReportId;\r
- Request.Index = Interface;\r
- Request.Length = 1;\r
+ Request.Request = EFI_USB_GET_IDLE_REQUEST;\r
+ Request.Value = ReportId;\r
+ Request.Index = Interface;\r
+ Request.Length = 1;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
return Result;\r
}\r
\r
-\r
-\r
/**\r
Set the report descriptor of the specified USB HID interface.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetReportRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 ReportType,\r
- IN UINT16 ReportLen,\r
- IN UINT8 *Report\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 ReportType,\r
+ IN UINT16 ReportLen,\r
+ IN UINT8 *Report\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_SET_REQ_TYPE;\r
- Request.Request = EFI_USB_SET_REPORT_REQUEST;\r
- Request.Value = (UINT16) ((ReportType << 8) | ReportId);\r
- Request.Index = Interface;\r
- Request.Length = ReportLen;\r
+ Request.Request = EFI_USB_SET_REPORT_REQUEST;\r
+ Request.Value = (UINT16)((ReportType << 8) | ReportId);\r
+ Request.Index = Interface;\r
+ Request.Length = ReportLen;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
return Result;\r
}\r
\r
-\r
/**\r
Get the report descriptor of the specified USB HID interface.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetReportRequest (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Interface,\r
- IN UINT8 ReportId,\r
- IN UINT8 ReportType,\r
- IN UINT16 ReportLen,\r
- OUT UINT8 *Report\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Interface,\r
+ IN UINT8 ReportId,\r
+ IN UINT8 ReportType,\r
+ IN UINT16 ReportLen,\r
+ OUT UINT8 *Report\r
)\r
{\r
UINT32 Status;\r
// Fill Device request packet\r
//\r
Request.RequestType = USB_HID_CLASS_GET_REQ_TYPE;\r
- Request.Request = EFI_USB_GET_REPORT_REQUEST;\r
- Request.Value = (UINT16) ((ReportType << 8) | ReportId);\r
- Request.Index = Interface;\r
- Request.Length = ReportLen;\r
+ Request.Request = EFI_USB_GET_REPORT_REQUEST;\r
+ Request.Value = (UINT16)((ReportType << 8) | ReportId);\r
+ Request.Index = Interface;\r
+ Request.Length = ReportLen;\r
\r
Result = UsbIo->UsbControlTransfer (\r
UsbIo,\r
\r
#include <IndustryStandard/Usb.h>\r
\r
-\r
#endif\r
\r
#include "UefiUsbLibInternal.h"\r
\r
-\r
/**\r
Get the descriptor of the specified USB device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Value,\r
- IN UINT16 Index,\r
- IN UINT16 DescriptorLength,\r
- OUT VOID *Descriptor,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Value,\r
+ IN UINT16 Index,\r
+ IN UINT16 DescriptorLength,\r
+ OUT VOID *Descriptor,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_GET_DESCRIPTOR_REQ_TYPE;\r
- DevReq.Request = USB_REQ_GET_DESCRIPTOR;\r
- DevReq.Value = Value;\r
- DevReq.Index = Index;\r
- DevReq.Length = DescriptorLength;\r
+ DevReq.RequestType = USB_DEV_GET_DESCRIPTOR_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_GET_DESCRIPTOR;\r
+ DevReq.Value = Value;\r
+ DevReq.Index = Index;\r
+ DevReq.Length = DescriptorLength;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Set the descriptor of the specified USB device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetDescriptor (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Value,\r
- IN UINT16 Index,\r
- IN UINT16 DescriptorLength,\r
- IN VOID *Descriptor,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Value,\r
+ IN UINT16 Index,\r
+ IN UINT16 DescriptorLength,\r
+ IN VOID *Descriptor,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_SET_DESCRIPTOR_REQ_TYPE;\r
- DevReq.Request = USB_REQ_SET_DESCRIPTOR;\r
- DevReq.Value = Value;\r
- DevReq.Index = Index;\r
- DevReq.Length = DescriptorLength;\r
+ DevReq.RequestType = USB_DEV_SET_DESCRIPTOR_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_SET_DESCRIPTOR;\r
+ DevReq.Value = Value;\r
+ DevReq.Index = Index;\r
+ DevReq.Length = DescriptorLength;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Get the interface setting of the specified USB device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetInterface (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Interface,\r
- OUT UINT16 *AlternateSetting,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Interface,\r
+ OUT UINT16 *AlternateSetting,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_GET_INTERFACE_REQ_TYPE;\r
- DevReq.Request = USB_REQ_GET_INTERFACE;\r
- DevReq.Index = Interface;\r
- DevReq.Length = 1;\r
+ DevReq.RequestType = USB_DEV_GET_INTERFACE_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_GET_INTERFACE;\r
+ DevReq.Index = Interface;\r
+ DevReq.Length = 1;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Set the interface setting of the specified USB device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetInterface (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 Interface,\r
- IN UINT16 AlternateSetting,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 Interface,\r
+ IN UINT16 AlternateSetting,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_SET_INTERFACE_REQ_TYPE;\r
- DevReq.Request = USB_REQ_SET_INTERFACE;\r
- DevReq.Value = AlternateSetting;\r
- DevReq.Index = Interface;\r
+ DevReq.RequestType = USB_DEV_SET_INTERFACE_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_SET_INTERFACE;\r
+ DevReq.Value = AlternateSetting;\r
+ DevReq.Index = Interface;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Get the device configuration.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetConfiguration (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- OUT UINT16 *ConfigurationValue,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ OUT UINT16 *ConfigurationValue,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_GET_CONFIGURATION_REQ_TYPE;\r
- DevReq.Request = USB_REQ_GET_CONFIG;\r
- DevReq.Length = 1;\r
+ DevReq.RequestType = USB_DEV_GET_CONFIGURATION_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_GET_CONFIG;\r
+ DevReq.Length = 1;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Set the device configuration.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetConfiguration (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT16 ConfigurationValue,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT16 ConfigurationValue,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
- DevReq.RequestType = USB_DEV_SET_CONFIGURATION_REQ_TYPE;\r
- DevReq.Request = USB_REQ_SET_CONFIG;\r
- DevReq.Value = ConfigurationValue;\r
+ DevReq.RequestType = USB_DEV_SET_CONFIGURATION_REQ_TYPE;\r
+ DevReq.Request = USB_REQ_SET_CONFIG;\r
+ DevReq.Value = ConfigurationValue;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Set the specified feature of the specified device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbSetFeature (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Value,\r
- IN UINT16 Target,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Value,\r
+ IN UINT16 Target,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
switch (Recipient) {\r
+ case USB_TARGET_DEVICE:\r
+ DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_D;\r
+ break;\r
\r
- case USB_TARGET_DEVICE:\r
- DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_D;\r
- break;\r
-\r
- case USB_TARGET_INTERFACE:\r
- DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_I;\r
- break;\r
+ case USB_TARGET_INTERFACE:\r
+ DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_I;\r
+ break;\r
\r
- case USB_TARGET_ENDPOINT:\r
- DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_E;\r
- break;\r
+ case USB_TARGET_ENDPOINT:\r
+ DevReq.RequestType = USB_DEV_SET_FEATURE_REQ_TYPE_E;\r
+ break;\r
\r
- default:\r
- break;\r
+ default:\r
+ break;\r
}\r
+\r
//\r
// Fill device request, see USB1.1 spec\r
//\r
- DevReq.Request = USB_REQ_SET_FEATURE;\r
- DevReq.Value = Value;\r
- DevReq.Index = Target;\r
-\r
+ DevReq.Request = USB_REQ_SET_FEATURE;\r
+ DevReq.Value = Value;\r
+ DevReq.Index = Target;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Clear the specified feature of the specified device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbClearFeature (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Value,\r
- IN UINT16 Target,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Value,\r
+ IN UINT16 Target,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
ASSERT (UsbIo != NULL);\r
ASSERT (Status != NULL);\r
\r
-\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
switch (Recipient) {\r
+ case USB_TARGET_DEVICE:\r
+ DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_D;\r
+ break;\r
\r
- case USB_TARGET_DEVICE:\r
- DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_D;\r
- break;\r
-\r
- case USB_TARGET_INTERFACE:\r
- DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_I;\r
- break;\r
+ case USB_TARGET_INTERFACE:\r
+ DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_I;\r
+ break;\r
\r
- case USB_TARGET_ENDPOINT:\r
- DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_E;\r
- break;\r
+ case USB_TARGET_ENDPOINT:\r
+ DevReq.RequestType = USB_DEV_CLEAR_FEATURE_REQ_TYPE_E;\r
+ break;\r
\r
- default:\r
- break;\r
+ default:\r
+ break;\r
}\r
+\r
//\r
// Fill device request, see USB1.1 spec\r
//\r
- DevReq.Request = USB_REQ_CLEAR_FEATURE;\r
- DevReq.Value = Value;\r
- DevReq.Index = Target;\r
-\r
+ DevReq.Request = USB_REQ_CLEAR_FEATURE;\r
+ DevReq.Value = Value;\r
+ DevReq.Index = Target;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Get the status of the specified device.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbGetStatus (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN USB_TYPES_DEFINITION Recipient,\r
- IN UINT16 Target,\r
- OUT UINT16 *DeviceStatus,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN USB_TYPES_DEFINITION Recipient,\r
+ IN UINT16 Target,\r
+ OUT UINT16 *DeviceStatus,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_USB_DEVICE_REQUEST DevReq;\r
ZeroMem (&DevReq, sizeof (EFI_USB_DEVICE_REQUEST));\r
\r
switch (Recipient) {\r
+ case USB_TARGET_DEVICE:\r
+ DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_D;\r
+ break;\r
\r
- case USB_TARGET_DEVICE:\r
- DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_D;\r
- break;\r
-\r
- case USB_TARGET_INTERFACE:\r
- DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_I;\r
- break;\r
+ case USB_TARGET_INTERFACE:\r
+ DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_I;\r
+ break;\r
\r
- case USB_TARGET_ENDPOINT:\r
- DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_E;\r
- break;\r
+ case USB_TARGET_ENDPOINT:\r
+ DevReq.RequestType = USB_DEV_GET_STATUS_REQ_TYPE_E;\r
+ break;\r
\r
- default:\r
- break;\r
+ default:\r
+ break;\r
}\r
+\r
//\r
// Fill device request, see USB1.1 spec\r
//\r
- DevReq.Request = USB_REQ_GET_STATUS;\r
- DevReq.Value = 0;\r
- DevReq.Index = Target;\r
- DevReq.Length = 2;\r
+ DevReq.Request = USB_REQ_GET_STATUS;\r
+ DevReq.Value = 0;\r
+ DevReq.Index = Target;\r
+ DevReq.Length = 2;\r
\r
return UsbIo->UsbControlTransfer (\r
UsbIo,\r
);\r
}\r
\r
-\r
/**\r
Clear halt feature of the specified usb endpoint.\r
\r
EFI_STATUS\r
EFIAPI\r
UsbClearEndpointHalt (\r
- IN EFI_USB_IO_PROTOCOL *UsbIo,\r
- IN UINT8 Endpoint,\r
- OUT UINT32 *Status\r
+ IN EFI_USB_IO_PROTOCOL *UsbIo,\r
+ IN UINT8 Endpoint,\r
+ OUT UINT32 *Status\r
)\r
{\r
EFI_STATUS Result;\r
}\r
\r
Result = UsbClearFeature (\r
- UsbIo,\r
- USB_TARGET_ENDPOINT,\r
- USB_FEATURE_ENDPOINT_HALT,\r
- EndpointDescriptor.EndpointAddress,\r
- Status\r
- );\r
+ UsbIo,\r
+ USB_TARGET_ENDPOINT,\r
+ USB_FEATURE_ENDPOINT_HALT,\r
+ EndpointDescriptor.EndpointAddress,\r
+ Status\r
+ );\r
\r
return Result;\r
}\r
/// Common services\r
///\r
typedef struct {\r
- UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts;\r
- UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts;\r
- UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts;\r
- UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState;\r
} UNIT_TEST_HOST_BASE_LIB_COMMON;\r
\r
///\r
/// IA32/X64 services\r
///\r
typedef struct {\r
- UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx;\r
- UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache;\r
- UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr;\r
- UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait;\r
- UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd;\r
- UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Properties;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk16;\r
- UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr;\r
- UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence;\r
- UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Properties;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk16;\r
+ UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr;\r
+ UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence;\r
+ UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86;\r
} UNIT_TEST_HOST_BASE_LIB_X86;\r
\r
///\r
/// can be added to the end of this structure.\r
///\r
typedef struct {\r
- UNIT_TEST_HOST_BASE_LIB_COMMON *Common;\r
- UNIT_TEST_HOST_BASE_LIB_X86 *X86;\r
+ UNIT_TEST_HOST_BASE_LIB_COMMON *Common;\r
+ UNIT_TEST_HOST_BASE_LIB_X86 *X86;\r
} UNIT_TEST_HOST_BASE_LIB;\r
\r
extern UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib;\r
*/\r
\r
typedef struct {\r
- CHAR8 *TestInput;\r
- CHAR8 *TestOutput;\r
- EFI_STATUS ExpectedStatus;\r
- VOID *BufferToFree;\r
- UINTN ExpectedSize;\r
+ CHAR8 *TestInput;\r
+ CHAR8 *TestOutput;\r
+ EFI_STATUS ExpectedStatus;\r
+ VOID *BufferToFree;\r
+ UINTN ExpectedSize;\r
} BASIC_TEST_CONTEXT;\r
\r
-#define B64_TEST_1 ""\r
-#define BIN_TEST_1 ""\r
+#define B64_TEST_1 ""\r
+#define BIN_TEST_1 ""\r
\r
-#define B64_TEST_2 "Zg=="\r
-#define BIN_TEST_2 "f"\r
+#define B64_TEST_2 "Zg=="\r
+#define BIN_TEST_2 "f"\r
\r
-#define B64_TEST_3 "Zm8="\r
-#define BIN_TEST_3 "fo"\r
+#define B64_TEST_3 "Zm8="\r
+#define BIN_TEST_3 "fo"\r
\r
-#define B64_TEST_4 "Zm9v"\r
-#define BIN_TEST_4 "foo"\r
+#define B64_TEST_4 "Zm9v"\r
+#define BIN_TEST_4 "foo"\r
\r
-#define B64_TEST_5 "Zm9vYg=="\r
-#define BIN_TEST_5 "foob"\r
+#define B64_TEST_5 "Zm9vYg=="\r
+#define BIN_TEST_5 "foob"\r
\r
-#define B64_TEST_6 "Zm9vYmE="\r
-#define BIN_TEST_6 "fooba"\r
+#define B64_TEST_6 "Zm9vYmE="\r
+#define BIN_TEST_6 "fooba"\r
\r
-#define B64_TEST_7 "Zm9vYmFy"\r
-#define BIN_TEST_7 "foobar"\r
+#define B64_TEST_7 "Zm9vYmFy"\r
+#define BIN_TEST_7 "foobar"\r
\r
// Adds all white space - also ends the last quantum with only spaces afterwards\r
-#define B64_TEST_8_IN " \t\v Zm9\r\nvYmFy \f "\r
-#define BIN_TEST_8 "foobar"\r
+#define B64_TEST_8_IN " \t\v Zm9\r\nvYmFy \f "\r
+#define BIN_TEST_8 "foobar"\r
\r
// Not a quantum multiple of 4\r
#define B64_ERROR_1 "Zm9vymFy="\r
#define B64_ERROR_2 "Zm$vymFy"\r
\r
// Too many '=' characters\r
-#define B64_ERROR_3 "Z==="\r
+#define B64_ERROR_3 "Z==="\r
\r
// Poorly placed '='\r
-#define B64_ERROR_4 "Zm=vYmFy"\r
+#define B64_ERROR_4 "Zm=vYmFy"\r
\r
-#define MAX_TEST_STRING_SIZE (200)\r
+#define MAX_TEST_STRING_SIZE (200)\r
\r
// ------------------------------------------------ Input----------Output-----------Result-------Free--Expected Output Size\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest1 = {BIN_TEST_1, B64_TEST_1, EFI_SUCCESS, NULL, sizeof(B64_TEST_1)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest2 = {BIN_TEST_2, B64_TEST_2, EFI_SUCCESS, NULL, sizeof(B64_TEST_2)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest3 = {BIN_TEST_3, B64_TEST_3, EFI_SUCCESS, NULL, sizeof(B64_TEST_3)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest4 = {BIN_TEST_4, B64_TEST_4, EFI_SUCCESS, NULL, sizeof(B64_TEST_4)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest5 = {BIN_TEST_5, B64_TEST_5, EFI_SUCCESS, NULL, sizeof(B64_TEST_5)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest6 = {BIN_TEST_6, B64_TEST_6, EFI_SUCCESS, NULL, sizeof(B64_TEST_6)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeTest7 = {BIN_TEST_7, B64_TEST_7, EFI_SUCCESS, NULL, sizeof(B64_TEST_7)};\r
-static BASIC_TEST_CONTEXT mBasicEncodeError1 = {BIN_TEST_7, B64_TEST_1, EFI_BUFFER_TOO_SMALL, NULL, sizeof(B64_TEST_7)};\r
-\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest1 = {B64_TEST_1, BIN_TEST_1, EFI_SUCCESS, NULL, sizeof(BIN_TEST_1)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest2 = {B64_TEST_2, BIN_TEST_2, EFI_SUCCESS, NULL, sizeof(BIN_TEST_2)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest3 = {B64_TEST_3, BIN_TEST_3, EFI_SUCCESS, NULL, sizeof(BIN_TEST_3)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest4 = {B64_TEST_4, BIN_TEST_4, EFI_SUCCESS, NULL, sizeof(BIN_TEST_4)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest5 = {B64_TEST_5, BIN_TEST_5, EFI_SUCCESS, NULL, sizeof(BIN_TEST_5)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest6 = {B64_TEST_6, BIN_TEST_6, EFI_SUCCESS, NULL, sizeof(BIN_TEST_6)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest7 = {B64_TEST_7, BIN_TEST_7, EFI_SUCCESS, NULL, sizeof(BIN_TEST_7)-1};\r
-static BASIC_TEST_CONTEXT mBasicDecodeTest8 = {B64_TEST_8_IN, BIN_TEST_8, EFI_SUCCESS, NULL, sizeof(BIN_TEST_8)-1};\r
-\r
-static BASIC_TEST_CONTEXT mBasicDecodeError1 = {B64_ERROR_1, B64_ERROR_1, EFI_INVALID_PARAMETER, NULL, 0};\r
-static BASIC_TEST_CONTEXT mBasicDecodeError2 = {B64_ERROR_2, B64_ERROR_2, EFI_INVALID_PARAMETER, NULL, 0};\r
-static BASIC_TEST_CONTEXT mBasicDecodeError3 = {B64_ERROR_3, B64_ERROR_3, EFI_INVALID_PARAMETER, NULL, 0};\r
-static BASIC_TEST_CONTEXT mBasicDecodeError4 = {B64_ERROR_4, B64_ERROR_4, EFI_INVALID_PARAMETER, NULL, 0};\r
-static BASIC_TEST_CONTEXT mBasicDecodeError5 = {B64_TEST_7, BIN_TEST_1, EFI_BUFFER_TOO_SMALL, NULL, sizeof(BIN_TEST_7)-1};\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest1 = { BIN_TEST_1, B64_TEST_1, EFI_SUCCESS, NULL, sizeof (B64_TEST_1) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest2 = { BIN_TEST_2, B64_TEST_2, EFI_SUCCESS, NULL, sizeof (B64_TEST_2) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest3 = { BIN_TEST_3, B64_TEST_3, EFI_SUCCESS, NULL, sizeof (B64_TEST_3) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest4 = { BIN_TEST_4, B64_TEST_4, EFI_SUCCESS, NULL, sizeof (B64_TEST_4) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest5 = { BIN_TEST_5, B64_TEST_5, EFI_SUCCESS, NULL, sizeof (B64_TEST_5) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest6 = { BIN_TEST_6, B64_TEST_6, EFI_SUCCESS, NULL, sizeof (B64_TEST_6) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeTest7 = { BIN_TEST_7, B64_TEST_7, EFI_SUCCESS, NULL, sizeof (B64_TEST_7) };\r
+static BASIC_TEST_CONTEXT mBasicEncodeError1 = { BIN_TEST_7, B64_TEST_1, EFI_BUFFER_TOO_SMALL, NULL, sizeof (B64_TEST_7) };\r
+\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest1 = { B64_TEST_1, BIN_TEST_1, EFI_SUCCESS, NULL, sizeof (BIN_TEST_1)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest2 = { B64_TEST_2, BIN_TEST_2, EFI_SUCCESS, NULL, sizeof (BIN_TEST_2)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest3 = { B64_TEST_3, BIN_TEST_3, EFI_SUCCESS, NULL, sizeof (BIN_TEST_3)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest4 = { B64_TEST_4, BIN_TEST_4, EFI_SUCCESS, NULL, sizeof (BIN_TEST_4)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest5 = { B64_TEST_5, BIN_TEST_5, EFI_SUCCESS, NULL, sizeof (BIN_TEST_5)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest6 = { B64_TEST_6, BIN_TEST_6, EFI_SUCCESS, NULL, sizeof (BIN_TEST_6)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest7 = { B64_TEST_7, BIN_TEST_7, EFI_SUCCESS, NULL, sizeof (BIN_TEST_7)-1 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeTest8 = { B64_TEST_8_IN, BIN_TEST_8, EFI_SUCCESS, NULL, sizeof (BIN_TEST_8)-1 };\r
+\r
+static BASIC_TEST_CONTEXT mBasicDecodeError1 = { B64_ERROR_1, B64_ERROR_1, EFI_INVALID_PARAMETER, NULL, 0 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeError2 = { B64_ERROR_2, B64_ERROR_2, EFI_INVALID_PARAMETER, NULL, 0 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeError3 = { B64_ERROR_3, B64_ERROR_3, EFI_INVALID_PARAMETER, NULL, 0 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeError4 = { B64_ERROR_4, B64_ERROR_4, EFI_INVALID_PARAMETER, NULL, 0 };\r
+static BASIC_TEST_CONTEXT mBasicDecodeError5 = { B64_TEST_7, BIN_TEST_1, EFI_BUFFER_TOO_SMALL, NULL, sizeof (BIN_TEST_7)-1 };\r
\r
/**\r
Simple clean up method to make sure tests clean up even if interrupted and fail\r
\r
Btc = (BASIC_TEST_CONTEXT *)Context;\r
if (Btc != NULL) {\r
- //free string if set\r
+ // free string if set\r
if (Btc->BufferToFree != NULL) {\r
FreePool (Btc->BufferToFree);\r
Btc->BufferToFree = NULL;\r
INTN CompareStatus;\r
UINTN indx;\r
\r
- Btc = (BASIC_TEST_CONTEXT *) Context;\r
+ Btc = (BASIC_TEST_CONTEXT *)Context;\r
binString = Btc->TestInput;\r
b64String = Btc->TestOutput;\r
\r
// string buffer.\r
//\r
\r
- b64StringSize = AsciiStrnSizeS(b64String, MAX_TEST_STRING_SIZE);\r
- BinSize = AsciiStrnLenS(binString, MAX_TEST_STRING_SIZE);\r
- BinData = (UINT8 *) binString;\r
+ b64StringSize = AsciiStrnSizeS (b64String, MAX_TEST_STRING_SIZE);\r
+ BinSize = AsciiStrnLenS (binString, MAX_TEST_STRING_SIZE);\r
+ BinData = (UINT8 *)binString;\r
\r
- b64WorkString = (CHAR8 *) AllocatePool(b64StringSize);\r
- UT_ASSERT_NOT_NULL(b64WorkString);\r
+ b64WorkString = (CHAR8 *)AllocatePool (b64StringSize);\r
+ UT_ASSERT_NOT_NULL (b64WorkString);\r
\r
Btc->BufferToFree = b64WorkString;\r
- ReturnSize = b64StringSize;\r
+ ReturnSize = b64StringSize;\r
\r
- Status = Base64Encode(BinData, BinSize, b64WorkString, &ReturnSize);\r
+ Status = Base64Encode (BinData, BinSize, b64WorkString, &ReturnSize);\r
\r
- UT_ASSERT_STATUS_EQUAL(Status, Btc->ExpectedStatus);\r
+ UT_ASSERT_STATUS_EQUAL (Status, Btc->ExpectedStatus);\r
\r
- UT_ASSERT_EQUAL(ReturnSize, Btc->ExpectedSize);\r
+ UT_ASSERT_EQUAL (ReturnSize, Btc->ExpectedSize);\r
\r
if (!EFI_ERROR (Btc->ExpectedStatus)) {\r
if (ReturnSize != 0) {\r
for (indx = 0; indx < ReturnSize; indx++) {\r
UT_LOG_ERROR (" %2.2x", 0xff & b64String[indx]);\r
}\r
+\r
UT_LOG_ERROR ("\n b64 work string:\n");\r
for (indx = 0; indx < ReturnSize; indx++) {\r
UT_LOG_ERROR (" %2.2x", 0xff & b64WorkString[indx]);\r
}\r
+\r
UT_LOG_ERROR ("\n");\r
}\r
+\r
UT_ASSERT_EQUAL (CompareStatus, 0);\r
}\r
}\r
STATIC\r
UNIT_TEST_STATUS\r
EFIAPI\r
-RfcDecodeTest(\r
+RfcDecodeTest (\r
IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
- BASIC_TEST_CONTEXT *Btc;\r
- CHAR8 *b64String;\r
- CHAR8 *binString;\r
+ BASIC_TEST_CONTEXT *Btc;\r
+ CHAR8 *b64String;\r
+ CHAR8 *binString;\r
EFI_STATUS Status;\r
UINTN b64StringLen;\r
UINTN ReturnSize;\r
- UINT8 *BinData;\r
+ UINT8 *BinData;\r
UINTN BinSize;\r
INTN CompareStatus;\r
UINTN indx;\r
\r
- Btc = (BASIC_TEST_CONTEXT *)Context;\r
+ Btc = (BASIC_TEST_CONTEXT *)Context;\r
b64String = Btc->TestInput;\r
binString = Btc->TestOutput;\r
\r
//\r
\r
b64StringLen = AsciiStrnLenS (b64String, MAX_TEST_STRING_SIZE);\r
- BinSize = AsciiStrnLenS (binString, MAX_TEST_STRING_SIZE);\r
+ BinSize = AsciiStrnLenS (binString, MAX_TEST_STRING_SIZE);\r
\r
BinData = AllocatePool (BinSize);\r
- UT_ASSERT_NOT_NULL(BinData);\r
+ UT_ASSERT_NOT_NULL (BinData);\r
\r
Btc->BufferToFree = BinData;\r
- ReturnSize = BinSize;\r
+ ReturnSize = BinSize;\r
\r
Status = Base64Decode (b64String, b64StringLen, BinData, &ReturnSize);\r
\r
for (indx = 0; indx < ReturnSize; indx++) {\r
UT_LOG_ERROR (" %2.2x", 0xff & binString[indx]);\r
}\r
+\r
UT_LOG_ERROR ("\nBinData:\n");\r
for (indx = 0; indx < ReturnSize; indx++) {\r
UT_LOG_ERROR (" %2.2x", 0xff & BinData[indx]);\r
}\r
+\r
UT_LOG_ERROR ("\n");\r
}\r
+\r
UT_ASSERT_EQUAL (CompareStatus, 0);\r
}\r
}\r
//\r
Status = InitUnitTestFramework (&Fw, UNIT_TEST_APP_NAME, gEfiCallerBaseName, UNIT_TEST_APP_VERSION);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));\r
- goto EXIT;\r
+ DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));\r
+ goto EXIT;\r
}\r
\r
//\r
//\r
Status = CreateUnitTestSuite (&b64DecodeTests, Fw, "b64 Decode Ascii string to binary", "BaseLib.b64Decode", NULL, NULL);\r
if (EFI_ERROR (Status)) {\r
- DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for b64Decode Tests\n"));\r
- Status = EFI_OUT_OF_RESOURCES;\r
- goto EXIT;\r
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for b64Decode Tests\n"));\r
+ Status = EFI_OUT_OF_RESOURCES;\r
+ goto EXIT;\r
}\r
\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - Empty", "Test1", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest1);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - f", "Test2", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest2);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fo", "Test3", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest3);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foo", "Test4", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest4);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foob", "Test5", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest5);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fooba", "Test6", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest6);\r
- AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foobar", "Test7", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest7);\r
- AddTestCase (b64DecodeTests, "Ignore Whitespace test", "Test8", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest8);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - Empty", "Test1", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest1);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - f", "Test2", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest2);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fo", "Test3", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest3);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foo", "Test4", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest4);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foob", "Test5", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest5);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - fooba", "Test6", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest6);\r
+ AddTestCase (b64DecodeTests, "RFC 4686 Test Vector - foobar", "Test7", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest7);\r
+ AddTestCase (b64DecodeTests, "Ignore Whitespace test", "Test8", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeTest8);\r
\r
AddTestCase (b64DecodeTests, "Not a quantum multiple of 4", "Error1", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeError1);\r
AddTestCase (b64DecodeTests, "Invalid characters in the string", "Error2", RfcDecodeTest, NULL, CleanUpB64TestContext, &mBasicDecodeError2);\r
**/\r
int\r
main (\r
- int argc,\r
- char *argv[]\r
+ int argc,\r
+ char *argv[]\r
)\r
{\r
return UnitTestingEntry ();\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt32ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INTN, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUint32ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUint32ToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// INTN is same as INT32 in IA32, so this is just a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeIntnToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeIntnToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeIntnToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// UINTN is same as UINT32 in IA32, so this is just a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUintnToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INTN, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUintnToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUintnToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToInt64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// INT64, so this is just a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUintnToInt64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToInt64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INTN and MAX_INTN2 inclusive, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt64ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt64ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-1537977259), Result);\r
+ Status = SafeInt64ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-1537977259), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINTN inclusive, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeInt64ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INTN, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUint64ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINTN, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUint64ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnAdd (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a;\r
Addend = 0x3a3a3a3a;\r
Result = 0;\r
- Status = SafeUintnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74747474, Result);\r
+ Status = SafeUintnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74747474, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xabababab;\r
Addend = 0xbcbcbcbc;\r
- Status = SafeUintnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnAdd (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a;\r
Addend = 0x3a3a3a3a;\r
Result = 0;\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74747474, Result);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74747474, Result);\r
\r
Augend = (-976894522);\r
Addend = (-976894522);\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-1953789044), Result);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-1953789044), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a5a5a5a;\r
Addend = 0x5a5a5a5a;\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-1515870810);\r
Addend = (-1515870810);\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnSub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x3b3b3b3b;\r
- Result = 0;\r
- Status = SafeUintnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f1f1f1f, Result);\r
+ Result = 0;\r
+ Status = SafeUintnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f1f1f1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x6d6d6d6d;\r
- Status = SafeUintnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnSub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INTN or\r
// underflow MIN_INTN, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x3a3a3a3a;\r
- Result = 0;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x20202020, Result);\r
+ Result = 0;\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x20202020, Result);\r
\r
- Minuend = 0x3a3a3a3a;\r
+ Minuend = 0x3a3a3a3a;\r
Subtrahend = 0x5a5a5a5a;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-538976288), Result);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-538976288), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-2054847098);\r
+ Minuend = (-2054847098);\r
Subtrahend = 2054847098;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (2054847098);\r
+ Minuend = (2054847098);\r
Subtrahend = (-2054847098);\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnMult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINTN, it will succeed\r
//\r
Multiplicand = 0xa122a;\r
- Multiplier = 0xd23;\r
- Result = 0;\r
- Status = SafeUintnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x844c9dbe, Result);\r
+ Multiplier = 0xd23;\r
+ Result = 0;\r
+ Status = SafeUintnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x844c9dbe, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0xa122a;\r
- Multiplier = 0xed23;\r
- Status = SafeUintnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xed23;\r
+ Status = SafeUintnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnMult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINTN, it will succeed\r
//\r
Multiplicand = 0x123456;\r
- Multiplier = 0x678;\r
- Result = 0;\r
- Status = SafeIntnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x75c28c50, Result);\r
+ Multiplier = 0x678;\r
+ Result = 0;\r
+ Status = SafeIntnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x75c28c50, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456;\r
- Multiplier = 0xabc;\r
- Status = SafeIntnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xabc;\r
+ Status = SafeIntnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt32ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUint32ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT32 and MAX_INT32 inclusive, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeIntnToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-1537977259), Result);\r
+ Status = SafeIntnToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-1537977259), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeIntnToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeIntnToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT32 inclusive, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeIntnToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeIntnToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeIntnToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT32, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUintnToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUintnToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INTN (0x7fff_ffff_ffff_ffff), then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeUintnToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUintnToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToInt64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT64, then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeUintnToInt64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToInt64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUintnToInt64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToInt64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// INTN is same as INT64 in x64, so this is just a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeInt64ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeInt64ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToIntn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INTN (0x7fff_ffff_ffff_ffff), then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeUint64ToIntn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToIntn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToIntn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToIntn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// UINTN is same as UINT64 in x64, so this is just a cast\r
//\r
Operand = 0xababababefefefef;\r
- Result = 0;\r
- Status = SafeUint64ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xababababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xababababefefefef, Result);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnAdd (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a12121212;\r
Addend = 0x3a3a3a3a12121212;\r
Result = 0;\r
- Status = SafeUintnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474747424242424, Result);\r
+ Status = SafeUintnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474747424242424, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xababababefefefef;\r
Addend = 0xbcbcbcbcdededede;\r
- Status = SafeUintnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnAdd (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a3a3a3a3a;\r
Addend = 0x3a3a3a3a3a3a3a3a;\r
Result = 0;\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474747474747474, Result);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474747474747474, Result);\r
\r
Augend = (-4195730024608447034);\r
Addend = (-4195730024608447034);\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-8391460049216894068), Result);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-8391460049216894068), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a5a5a5a5a5a5a5a;\r
Addend = 0x5a5a5a5a5a5a5a5a;\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-6510615555426900570);\r
Addend = (-6510615555426900570);\r
- Status = SafeIntnAdd(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnAdd (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnSub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x3b3b3b3b3b3b3b3b;\r
- Result = 0;\r
- Status = SafeUintnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f1f1f1f1f1f1f1f, Result);\r
+ Result = 0;\r
+ Status = SafeUintnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f1f1f1f1f1f1f1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x6d6d6d6d6d6d6d6d;\r
- Status = SafeUintnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnSub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INTN or\r
// underflow MIN_INTN, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x3a3a3a3a3a3a3a3a;\r
- Result = 0;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x2020202020202020, Result);\r
+ Result = 0;\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x2020202020202020, Result);\r
\r
- Minuend = 0x3a3a3a3a3a3a3a3a;\r
+ Minuend = 0x3a3a3a3a3a3a3a3a;\r
Subtrahend = 0x5a5a5a5a5a5a5a5a;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-2314885530818453536), Result);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-2314885530818453536), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-8825501086245354106);\r
+ Minuend = (-8825501086245354106);\r
Subtrahend = 8825501086245354106;\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (8825501086245354106);\r
+ Minuend = (8825501086245354106);\r
Subtrahend = (-8825501086245354106);\r
- Status = SafeIntnSub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnSub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnMult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINTN, it will succeed\r
//\r
Multiplicand = 0x123456789a;\r
- Multiplier = 0x1234567;\r
- Result = 0;\r
- Status = SafeUintnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x14b66db9745a07f6, Result);\r
+ Multiplier = 0x1234567;\r
+ Result = 0;\r
+ Status = SafeUintnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x14b66db9745a07f6, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456789a;\r
- Multiplier = 0x12345678;\r
- Status = SafeUintnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0x12345678;\r
+ Status = SafeUintnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnMult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINTN, it will succeed\r
//\r
Multiplicand = 0x123456789;\r
- Multiplier = 0x6789abcd;\r
- Result = 0;\r
- Status = SafeIntnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x75cd9045220d6bb5, Result);\r
+ Multiplier = 0x6789abcd;\r
+ Result = 0;\r
+ Status = SafeIntnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x75cd9045220d6bb5, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456789;\r
- Multiplier = 0xa789abcd;\r
- Status = SafeIntnMult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xa789abcd;\r
+ Status = SafeIntnMult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
\r
#include "TestBaseSafeIntLib.h"\r
\r
-#define UNIT_TEST_NAME "Int Safe Lib Unit Test Application"\r
-#define UNIT_TEST_VERSION "0.1"\r
+#define UNIT_TEST_NAME "Int Safe Lib Unit Test Application"\r
+#define UNIT_TEST_VERSION "0.1"\r
\r
//\r
// Conversion function tests:\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Positive UINT8 should result in just a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt8ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt8ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Negative number should result in an error status\r
//\r
Operand = (-56);\r
- Status = SafeInt8ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Positive UINT8 should result in just a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt8ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt8ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Negative number should result in an error status\r
//\r
Operand = (-56);\r
- Status = SafeInt8ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8ToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Positive UINT8 should result in just a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt8ToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt8ToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Negative number should result in an error status\r
//\r
Operand = (-56);\r
- Status = SafeInt8ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Positive UINT8 should result in just a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt8ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt8ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Negative number should result in an error status\r
//\r
Operand = (-56);\r
- Status = SafeInt8ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8ToUint64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Positive UINT8 should result in just a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt8ToUint64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt8ToUint64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Negative number should result in an error status\r
//\r
Operand = (-56);\r
- Status = SafeInt8ToUint64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8ToUint64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint8ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Operand <= 0x7F (MAX_INT8) should result in a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint8ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint8ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Operand larger than 0x7f should result in an error status\r
//\r
Operand = 0xaf;\r
- Status = SafeUint8ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint8ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint8ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// Operand <= 0x7F (MAX_INT8) should result in a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint8ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint8ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Operand larger than 0x7f should result in an error status\r
//\r
Operand = 0xaf;\r
- Status = SafeUint8ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint8ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt16ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = (-35);\r
- Status = SafeInt16ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-35), Result);\r
+ Status = SafeInt16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-35), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = 0x1234;\r
- Status = SafeInt16ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-17835);\r
- Status = SafeInt16ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = 0;\r
- Result = 0;\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0, Result);\r
\r
Operand = MAX_INT8;\r
- Result = 0;\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(MAX_INT8, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (MAX_INT8, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-35);\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = 0x1234;\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-17835);\r
- Status = SafeInt16ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt16ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = 0x1234;\r
- Status = SafeInt16ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-17835);\r
- Status = SafeInt16ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
- INT16 Operand = 0x5b5b;\r
- UINT16 Result = 0;\r
+ INT16 Operand = 0x5b5b;\r
+ UINT16 Result = 0;\r
\r
//\r
// If Operand is non-negative, then it's a cast\r
//\r
- Status = SafeInt16ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Status = SafeInt16ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-17835);\r
- Status = SafeInt16ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5b5b;\r
- Result = 0;\r
- Status = SafeInt16ToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-17835);\r
- Status = SafeInt16ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5b5b;\r
- Result = 0;\r
- Status = SafeInt16ToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-17835);\r
- Status = SafeInt16ToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16ToUint64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5b5b;\r
- Result = 0;\r
- Status = SafeInt16ToUint64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt16ToUint64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-17835);\r
- Status = SafeInt16ToUint64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16ToUint64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint16ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5b5b);\r
- Status = SafeUint16ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint16ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5b5b);\r
- Status = SafeUint16ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT8 (0xff), it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeUint16ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeUint16ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5b5b);\r
- Status = SafeUint16ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16ToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT16 (0x7fff), it's a cast\r
//\r
Operand = 0x5b5b;\r
- Result = 0;\r
- Status = SafeUint16ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint16ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabab);\r
- Status = SafeUint16ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt32ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = (-57);\r
- Status = SafeInt32ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-57), Result);\r
+ Status = SafeInt32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-57), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeInt32ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt32ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = 0;\r
- Result = 0;\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0, Result);\r
\r
Operand = MAX_INT8;\r
- Result = 0;\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(MAX_INT8, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (MAX_INT8, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-57);\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (0x5bababab);\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt32ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt32ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-57);\r
- Status = SafeInt32ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (0x5bababab);\r
- Status = SafeInt32ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast\r
//\r
Operand = 0x5b5b;\r
- Result = 0;\r
- Status = SafeInt32ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b5b, Result);\r
\r
Operand = (-17857);\r
- Status = SafeInt32ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-17857), Result);\r
+ Status = SafeInt32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-17857), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeInt32ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt32ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeInt32ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-17857);\r
- Status = SafeInt32ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (0x5bababab);\r
- Status = SafeInt32ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt32ToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32ToUint64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt32ToUint64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt32ToUint64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeInt32ToUint64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32ToUint64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint32ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeUint32ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint32ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeUint32ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT8, then it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeUint32ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUint32ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT16, then it's a cast\r
//\r
Operand = 0x5bab;\r
- Result = 0;\r
- Status = SafeUint32ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUint32ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT16, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeUint32ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUint32ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32ToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT32, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUint32ToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint32ToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUint32ToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32ToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeIntnToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = (-53);\r
- Status = SafeIntnToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-53), Result);\r
+ Status = SafeIntnToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-53), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeIntnToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = 0;\r
- Result = 0;\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0, Result);\r
\r
Operand = MAX_INT8;\r
- Result = 0;\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(MAX_INT8, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (MAX_INT8, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-53);\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (0x5bababab);\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT8 inclusive, then it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeIntnToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeIntnToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast\r
//\r
Operand = 0x5bab;\r
- Result = 0;\r
- Status = SafeIntnToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bab, Result);\r
\r
Operand = (-23467);\r
- Status = SafeIntnToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-23467), Result);\r
+ Status = SafeIntnToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-23467), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeIntnToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeIntnToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5bababab);\r
- Status = SafeIntnToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-1537977259);\r
- Status = SafeIntnToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUintn (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeIntnToUintn(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUintn (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeIntnToUintn(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUintn (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeIntnToUint64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeIntnToUint64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeIntnToUint64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-1537977259);\r
- Status = SafeIntnToUint64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeIntnToUint64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUintnToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabab);\r
- Status = SafeUintnToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUintnToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabab);\r
- Status = SafeUintnToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT8, then it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeUintnToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabab);\r
- Status = SafeUintnToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT16, then it's a cast\r
//\r
Operand = 0x5bab;\r
- Result = 0;\r
- Status = SafeUintnToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabab);\r
- Status = SafeUintnToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT16, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeUintnToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUintnToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUintnToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT32, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUintnToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUintnToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xabababab);\r
- Status = SafeUintnToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUintnToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt64ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = (-37);\r
- Status = SafeInt64ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-37), Result);\r
+ Status = SafeInt64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-37), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT8 and MAX_INT8 inclusive, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
Operand = 0;\r
- Result = 0;\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0, Result);\r
\r
Operand = MAX_INT8;\r
- Result = 0;\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(MAX_INT8, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (MAX_INT8, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-37);\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT8 inclusive, then it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeInt64ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT16 and MAX_INT16 inclusive, then it's a cast\r
//\r
Operand = 0x5bab;\r
- Result = 0;\r
- Status = SafeInt64ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bab, Result);\r
\r
Operand = (-23467);\r
- Status = SafeInt64ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-23467), Result);\r
+ Status = SafeInt64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-23467), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT16 inclusive, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeInt64ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between MIN_INT32 and MAX_INT32 inclusive, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeInt64ToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
Operand = (-1537977259);\r
- Status = SafeInt64ToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-1537977259), Result);\r
+ Status = SafeInt64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-1537977259), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is between 0 and MAX_UINT32 inclusive, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeInt64ToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0x5babababefefefef);\r
- Status = SafeInt64ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64ToUint64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is non-negative, then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeInt64ToUint64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeInt64ToUint64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (-6605562033422200815);\r
- Status = SafeInt64ToUint64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64ToUint64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToInt8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint64ToInt8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToInt8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToInt8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToChar8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT8, then it's a cast\r
//\r
Operand = 0x5b;\r
- Result = 0;\r
- Status = SafeUint64ToChar8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5b, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5b, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToChar8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToChar8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToUint8 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT8, then it's a cast\r
//\r
Operand = 0xab;\r
- Result = 0;\r
- Status = SafeUint64ToUint8(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToUint8 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToUint8(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToUint8 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToInt16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT16, then it's a cast\r
//\r
Operand = 0x5bab;\r
- Result = 0;\r
- Status = SafeUint64ToInt16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToInt16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToInt16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToUint16 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT16, then it's a cast\r
//\r
Operand = 0xabab;\r
- Result = 0;\r
- Status = SafeUint64ToUint16(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToUint16 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToUint16(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToUint16 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToInt32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT32, then it's a cast\r
//\r
Operand = 0x5bababab;\r
- Result = 0;\r
- Status = SafeUint64ToInt32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5bababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5bababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToInt32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToInt32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToUint32 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_UINT32, then it's a cast\r
//\r
Operand = 0xabababab;\r
- Result = 0;\r
- Status = SafeUint64ToUint32(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xabababab, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToUint32 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xabababab, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToUint32(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToUint32 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64ToInt64 (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If Operand is <= MAX_INT64, then it's a cast\r
//\r
Operand = 0x5babababefefefef;\r
- Result = 0;\r
- Status = SafeUint64ToInt64(Operand, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x5babababefefefef, Result);\r
+ Result = 0;\r
+ Status = SafeUint64ToInt64 (Operand, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x5babababefefefef, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Operand = (0xababababefefefef);\r
- Status = SafeUint64ToInt64(Operand, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64ToInt64 (Operand, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint8Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a;\r
Addend = 0x3a;\r
Result = 0;\r
- Status = SafeUint8Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74, Result);\r
+ Status = SafeUint8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xab;\r
Addend = 0xbc;\r
- Status = SafeUint8Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
- UINT16 Augend = 0x3a3a;\r
- UINT16 Addend = 0x3a3a;\r
- UINT16 Result = 0;\r
+ UINT16 Augend = 0x3a3a;\r
+ UINT16 Addend = 0x3a3a;\r
+ UINT16 Result = 0;\r
\r
//\r
// If the result of addition doesn't overflow MAX_UINT16, then it's addition\r
//\r
- Status = SafeUint16Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474, Result);\r
+ Status = SafeUint16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xabab;\r
Addend = 0xbcbc;\r
- Status = SafeUint16Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a;\r
Addend = 0x3a3a3a3a;\r
Result = 0;\r
- Status = SafeUint32Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74747474, Result);\r
+ Status = SafeUint32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74747474, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xabababab;\r
Addend = 0xbcbcbcbc;\r
- Status = SafeUint32Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a12121212;\r
Addend = 0x3a3a3a3a12121212;\r
Result = 0;\r
- Status = SafeUint64Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474747424242424, Result);\r
+ Status = SafeUint64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474747424242424, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0xababababefefefef;\r
Addend = 0xbcbcbcbcdededede;\r
- Status = SafeUint64Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a;\r
Addend = 0x3a;\r
Result = 0;\r
- Status = SafeInt8Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74, Result);\r
+ Status = SafeInt8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74, Result);\r
\r
Augend = (-58);\r
Addend = (-58);\r
- Status = SafeInt8Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-116), Result);\r
+ Status = SafeInt8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-116), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a;\r
Addend = 0x5a;\r
- Status = SafeInt8Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-90);\r
Addend = (-90);\r
- Status = SafeInt8Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
-\r
}\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a;\r
Addend = 0x3a3a;\r
Result = 0;\r
- Status = SafeInt16Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474, Result);\r
+ Status = SafeInt16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474, Result);\r
\r
Augend = (-14906);\r
Addend = (-14906);\r
- Status = SafeInt16Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-29812), Result);\r
+ Status = SafeInt16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-29812), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a5a;\r
Addend = 0x5a5a;\r
- Status = SafeInt16Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-23130);\r
Addend = (-23130);\r
- Status = SafeInt16Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a;\r
Addend = 0x3a3a3a3a;\r
Result = 0;\r
- Status = SafeInt32Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x74747474, Result);\r
+ Status = SafeInt32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x74747474, Result);\r
\r
Augend = (-976894522);\r
Addend = (-976894522);\r
- Status = SafeInt32Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-1953789044), Result);\r
+ Status = SafeInt32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-1953789044), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a5a5a5a;\r
Addend = 0x5a5a5a5a;\r
- Status = SafeInt32Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-1515870810);\r
Addend = (-1515870810);\r
- Status = SafeInt32Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64Add (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
Augend = 0x3a3a3a3a3a3a3a3a;\r
Addend = 0x3a3a3a3a3a3a3a3a;\r
Result = 0;\r
- Status = SafeInt64Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7474747474747474, Result);\r
+ Status = SafeInt64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7474747474747474, Result);\r
\r
Augend = (-4195730024608447034);\r
Addend = (-4195730024608447034);\r
- Status = SafeInt64Add(Augend, Addend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-8391460049216894068), Result);\r
+ Status = SafeInt64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-8391460049216894068), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Augend = 0x5a5a5a5a5a5a5a5a;\r
Addend = 0x5a5a5a5a5a5a5a5a;\r
- Status = SafeInt64Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
Augend = (-6510615555426900570);\r
Addend = (-6510615555426900570);\r
- Status = SafeInt64Add(Augend, Addend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64Add (Augend, Addend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint8Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a;\r
+ Minuend = 0x5a;\r
Subtrahend = 0x3b;\r
- Result = 0;\r
- Status = SafeUint8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f, Result);\r
+ Result = 0;\r
+ Status = SafeUint8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a;\r
+ Minuend = 0x5a;\r
Subtrahend = 0x6d;\r
- Status = SafeUint8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a5a;\r
+ Minuend = 0x5a5a;\r
Subtrahend = 0x3b3b;\r
- Result = 0;\r
- Status = SafeUint16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f1f, Result);\r
+ Result = 0;\r
+ Status = SafeUint16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a5a;\r
+ Minuend = 0x5a5a;\r
Subtrahend = 0x6d6d;\r
- Status = SafeUint16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x3b3b3b3b;\r
- Result = 0;\r
- Status = SafeUint32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f1f1f1f, Result);\r
+ Result = 0;\r
+ Status = SafeUint32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f1f1f1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x6d6d6d6d;\r
- Status = SafeUint32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
//\r
// If Minuend >= Subtrahend, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x3b3b3b3b3b3b3b3b;\r
- Result = 0;\r
- Status = SafeUint64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x1f1f1f1f1f1f1f1f, Result);\r
+ Result = 0;\r
+ Status = SafeUint64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x1f1f1f1f1f1f1f1f, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x6d6d6d6d6d6d6d6d;\r
- Status = SafeUint64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeUint64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INT8 or\r
// underflow MIN_INT8, then it's subtraction\r
//\r
- Minuend = 0x5a;\r
+ Minuend = 0x5a;\r
Subtrahend = 0x3a;\r
- Result = 0;\r
- Status = SafeInt8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x20, Result);\r
+ Result = 0;\r
+ Status = SafeInt8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x20, Result);\r
\r
- Minuend = 58;\r
+ Minuend = 58;\r
Subtrahend = 78;\r
- Status = SafeInt8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-20), Result);\r
+ Status = SafeInt8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-20), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-80);\r
+ Minuend = (-80);\r
Subtrahend = 80;\r
- Status = SafeInt8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (80);\r
+ Minuend = (80);\r
Subtrahend = (-80);\r
- Status = SafeInt8Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt8Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INT16 or\r
// underflow MIN_INT16, then it's subtraction\r
//\r
- Minuend = 0x5a5a;\r
+ Minuend = 0x5a5a;\r
Subtrahend = 0x3a3a;\r
- Result = 0;\r
- Status = SafeInt16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x2020, Result);\r
+ Result = 0;\r
+ Status = SafeInt16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x2020, Result);\r
\r
- Minuend = 0x3a3a;\r
+ Minuend = 0x3a3a;\r
Subtrahend = 0x5a5a;\r
- Status = SafeInt16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-8224), Result);\r
+ Status = SafeInt16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-8224), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-31354);\r
+ Minuend = (-31354);\r
Subtrahend = 31354;\r
- Status = SafeInt16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (31354);\r
+ Minuend = (31354);\r
Subtrahend = (-31354);\r
- Status = SafeInt16Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt16Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INT32 or\r
// underflow MIN_INT32, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a;\r
Subtrahend = 0x3a3a3a3a;\r
- Result = 0;\r
- Status = SafeInt32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x20202020, Result);\r
+ Result = 0;\r
+ Status = SafeInt32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x20202020, Result);\r
\r
- Minuend = 0x3a3a3a3a;\r
+ Minuend = 0x3a3a3a3a;\r
Subtrahend = 0x5a5a5a5a;\r
- Status = SafeInt32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-538976288), Result);\r
+ Status = SafeInt32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-538976288), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-2054847098);\r
+ Minuend = (-2054847098);\r
Subtrahend = 2054847098;\r
- Status = SafeInt32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (2054847098);\r
+ Minuend = (2054847098);\r
Subtrahend = (-2054847098);\r
- Status = SafeInt32Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt32Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64Sub (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of subtractions doesn't overflow MAX_INT64 or\r
// underflow MIN_INT64, then it's subtraction\r
//\r
- Minuend = 0x5a5a5a5a5a5a5a5a;\r
+ Minuend = 0x5a5a5a5a5a5a5a5a;\r
Subtrahend = 0x3a3a3a3a3a3a3a3a;\r
- Result = 0;\r
- Status = SafeInt64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x2020202020202020, Result);\r
+ Result = 0;\r
+ Status = SafeInt64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x2020202020202020, Result);\r
\r
- Minuend = 0x3a3a3a3a3a3a3a3a;\r
+ Minuend = 0x3a3a3a3a3a3a3a3a;\r
Subtrahend = 0x5a5a5a5a5a5a5a5a;\r
- Status = SafeInt64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL((-2314885530818453536), Result);\r
+ Status = SafeInt64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL ((-2314885530818453536), Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
- Minuend = (-8825501086245354106);\r
+ Minuend = (-8825501086245354106);\r
Subtrahend = 8825501086245354106;\r
- Status = SafeInt64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
- Minuend = (8825501086245354106);\r
+ Minuend = (8825501086245354106);\r
Subtrahend = (-8825501086245354106);\r
- Status = SafeInt64Sub(Minuend, Subtrahend, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Status = SafeInt64Sub (Minuend, Subtrahend, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint8Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINT8, it will succeed\r
//\r
Multiplicand = 0x12;\r
- Multiplier = 0xa;\r
- Result = 0;\r
- Status = SafeUint8Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xb4, Result);\r
+ Multiplier = 0xa;\r
+ Result = 0;\r
+ Status = SafeUint8Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xb4, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x12;\r
- Multiplier = 0x23;\r
- Status = SafeUint8Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0x23;\r
+ Status = SafeUint8Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint16Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINT16, it will succeed\r
//\r
Multiplicand = 0x212;\r
- Multiplier = 0x7a;\r
- Result = 0;\r
- Status = SafeUint16Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0xfc94, Result);\r
+ Multiplier = 0x7a;\r
+ Result = 0;\r
+ Status = SafeUint16Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0xfc94, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x1234;\r
- Multiplier = 0x213;\r
- Status = SafeUint16Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0x213;\r
+ Status = SafeUint16Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint32Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINT32, it will succeed\r
//\r
Multiplicand = 0xa122a;\r
- Multiplier = 0xd23;\r
- Result = 0;\r
- Status = SafeUint32Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x844c9dbe, Result);\r
+ Multiplier = 0xd23;\r
+ Result = 0;\r
+ Status = SafeUint32Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x844c9dbe, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0xa122a;\r
- Multiplier = 0xed23;\r
- Status = SafeUint32Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xed23;\r
+ Status = SafeUint32Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeUint64Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// If the result of multiplication doesn't overflow MAX_UINT64, it will succeed\r
//\r
Multiplicand = 0x123456789a;\r
- Multiplier = 0x1234567;\r
- Result = 0;\r
- Status = SafeUint64Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x14b66db9745a07f6, Result);\r
+ Multiplier = 0x1234567;\r
+ Result = 0;\r
+ Status = SafeUint64Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x14b66db9745a07f6, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456789a;\r
- Multiplier = 0x12345678;\r
- Status = SafeUint64Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0x12345678;\r
+ Status = SafeUint64Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt8Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINT8, it will succeed\r
//\r
Multiplicand = 0x12;\r
- Multiplier = 0x7;\r
- Result = 0;\r
- Status = SafeInt8Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7e, Result);\r
+ Multiplier = 0x7;\r
+ Result = 0;\r
+ Status = SafeInt8Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7e, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x12;\r
- Multiplier = 0xa;\r
- Status = SafeInt8Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xa;\r
+ Status = SafeInt8Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt16Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINT16, it will succeed\r
//\r
Multiplicand = 0x123;\r
- Multiplier = 0x67;\r
- Result = 0;\r
- Status = SafeInt16Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x7515, Result);\r
+ Multiplier = 0x67;\r
+ Result = 0;\r
+ Status = SafeInt16Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x7515, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123;\r
- Multiplier = 0xab;\r
- Status = SafeInt16Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xab;\r
+ Status = SafeInt16Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt32Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINT32, it will succeed\r
//\r
Multiplicand = 0x123456;\r
- Multiplier = 0x678;\r
- Result = 0;\r
- Status = SafeInt32Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x75c28c50, Result);\r
+ Multiplier = 0x678;\r
+ Result = 0;\r
+ Status = SafeInt32Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x75c28c50, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456;\r
- Multiplier = 0xabc;\r
- Status = SafeInt32Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xabc;\r
+ Status = SafeInt32Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_STATUS\r
EFIAPI\r
TestSafeInt64Mult (\r
- IN UNIT_TEST_CONTEXT Context\r
+ IN UNIT_TEST_CONTEXT Context\r
)\r
{\r
EFI_STATUS Status;\r
// underflow MIN_UINT64, it will succeed\r
//\r
Multiplicand = 0x123456789;\r
- Multiplier = 0x6789abcd;\r
- Result = 0;\r
- Status = SafeInt64Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_NOT_EFI_ERROR(Status);\r
- UT_ASSERT_EQUAL(0x75cd9045220d6bb5, Result);\r
+ Multiplier = 0x6789abcd;\r
+ Result = 0;\r
+ Status = SafeInt64Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_NOT_EFI_ERROR (Status);\r
+ UT_ASSERT_EQUAL (0x75cd9045220d6bb5, Result);\r
\r
//\r
// Otherwise should result in an error status\r
//\r
Multiplicand = 0x123456789;\r
- Multiplier = 0xa789abcd;\r
- Status = SafeInt64Mult(Multiplicand, Multiplier, &Result);\r
- UT_ASSERT_EQUAL(RETURN_BUFFER_TOO_SMALL, Status);\r
+ Multiplier = 0xa789abcd;\r
+ Status = SafeInt64Mult (Multiplicand, Multiplier, &Result);\r
+ UT_ASSERT_EQUAL (RETURN_BUFFER_TOO_SMALL, Status);\r
\r
return UNIT_TEST_PASSED;\r
}\r
UNIT_TEST_SUITE_HANDLE AdditionSubtractionTestSuite;\r
UNIT_TEST_SUITE_HANDLE MultiplicationTestSuite;\r
\r
- Framework = NULL;\r
- ConversionTestSuite = NULL;\r
+ Framework = NULL;\r
+ ConversionTestSuite = NULL;\r
AdditionSubtractionTestSuite = NULL;\r
- MultiplicationTestSuite = NULL;\r
+ MultiplicationTestSuite = NULL;\r
\r
- DEBUG((DEBUG_INFO, "%a v%a\n", UNIT_TEST_NAME, UNIT_TEST_VERSION));\r
+ DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_NAME, UNIT_TEST_VERSION));\r
\r
//\r
// Start setting up the test framework for running the tests.\r
//\r
Status = InitUnitTestFramework (&Framework, UNIT_TEST_NAME, gEfiCallerBaseName, UNIT_TEST_VERSION);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status = %r\n", Status));\r
goto EXIT;\r
}\r
\r
// Test the conversion functions\r
//\r
Status = CreateUnitTestSuite (&ConversionTestSuite, Framework, "Int Safe Conversions Test Suite", "Common.SafeInt.Convert", NULL, NULL);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Conversions Test Suite\n"));\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Conversions Test Suite\n"));\r
Status = EFI_OUT_OF_RESOURCES;\r
goto EXIT;\r
}\r
- AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint8", "TestSafeInt8ToUint8", TestSafeInt8ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint16", "TestSafeInt8ToUint16", TestSafeInt8ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint32", "TestSafeInt8ToUint32", TestSafeInt8ToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt8ToUintn", "TestSafeInt8ToUintn", TestSafeInt8ToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt8ToUint64", "TestSafeInt8ToUint64", TestSafeInt8ToUint64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint8ToInt8", "TestSafeUint8ToInt8", TestSafeUint8ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint8ToChar8", "TestSafeUint8ToChar8", TestSafeUint8ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToInt8", "TestSafeInt16ToInt8", TestSafeInt16ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToChar8", "TestSafeInt16ToChar8", TestSafeInt16ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint8", "TestSafeInt16ToUint8", TestSafeInt16ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint16", "TestSafeInt16ToUint16", TestSafeInt16ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint32", "TestSafeInt16ToUint32", TestSafeInt16ToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToUintn", "TestSafeInt16ToUintn", TestSafeInt16ToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt16ToUint64", "TestSafeInt16ToUint64", TestSafeInt16ToUint64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint16ToInt8", "TestSafeUint16ToInt8", TestSafeUint16ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint16ToChar8", "TestSafeUint16ToChar8", TestSafeUint16ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint16ToUint8", "TestSafeUint16ToUint8", TestSafeUint16ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint16ToInt16", "TestSafeUint16ToInt16", TestSafeUint16ToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToInt8", "TestSafeInt32ToInt8", TestSafeInt32ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToChar8", "TestSafeInt32ToChar8", TestSafeInt32ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint8", "TestSafeInt32ToUint8", TestSafeInt32ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToInt16", "TestSafeInt32ToInt16", TestSafeInt32ToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint16", "TestSafeInt32ToUint16", TestSafeInt32ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint32", "TestSafeInt32ToUint32", TestSafeInt32ToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToUintn", "TestSafeInt32ToUintn", TestSafeInt32ToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt32ToUint64", "TestSafeInt32ToUint64", TestSafeInt32ToUint64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt8", "TestSafeUint32ToInt8", TestSafeUint32ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToChar8", "TestSafeUint32ToChar8", TestSafeUint32ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToUint8", "TestSafeUint32ToUint8", TestSafeUint32ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt16", "TestSafeUint32ToInt16", TestSafeUint32ToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToUint16", "TestSafeUint32ToUint16", TestSafeUint32ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToInt32", "TestSafeUint32ToInt32", TestSafeUint32ToInt32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint32ToIntn", "TestSafeUint32ToIntn", TestSafeUint32ToIntn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToInt8", "TestSafeIntnToInt8", TestSafeIntnToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToChar8", "TestSafeIntnToChar8", TestSafeIntnToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToUint8", "TestSafeIntnToUint8", TestSafeIntnToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToInt16", "TestSafeIntnToInt16", TestSafeIntnToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToUint16", "TestSafeIntnToUint16", TestSafeIntnToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToInt32", "TestSafeIntnToInt32", TestSafeIntnToInt32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToUint32", "TestSafeIntnToUint32", TestSafeIntnToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToUintn", "TestSafeIntnToUintn", TestSafeIntnToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeIntnToUint64", "TestSafeIntnToUint64", TestSafeIntnToUint64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToInt8", "TestSafeUintnToInt8", TestSafeUintnToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToChar8", "TestSafeUintnToChar8", TestSafeUintnToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToUint8", "TestSafeUintnToUint8", TestSafeUintnToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToInt16", "TestSafeUintnToInt16", TestSafeUintnToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToUint16", "TestSafeUintnToUint16", TestSafeUintnToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToInt32", "TestSafeUintnToInt32", TestSafeUintnToInt32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToUint32", "TestSafeUintnToUint32", TestSafeUintnToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToIntn", "TestSafeUintnToIntn", TestSafeUintnToIntn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUintnToInt64", "TestSafeUintnToInt64", TestSafeUintnToInt64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt8", "TestSafeInt64ToInt8", TestSafeInt64ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToChar8", "TestSafeInt64ToChar8", TestSafeInt64ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint8", "TestSafeInt64ToUint8", TestSafeInt64ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt16", "TestSafeInt64ToInt16", TestSafeInt64ToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint16", "TestSafeInt64ToUint16", TestSafeInt64ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToInt32", "TestSafeInt64ToInt32", TestSafeInt64ToInt32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint32", "TestSafeInt64ToUint32", TestSafeInt64ToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToIntn", "TestSafeInt64ToIntn", TestSafeInt64ToIntn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToUintn", "TestSafeInt64ToUintn", TestSafeInt64ToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeInt64ToUint64", "TestSafeInt64ToUint64", TestSafeInt64ToUint64, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt8", "TestSafeUint64ToInt8", TestSafeUint64ToInt8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToChar8", "TestSafeUint64ToChar8", TestSafeUint64ToChar8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint8", "TestSafeUint64ToUint8", TestSafeUint64ToUint8, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt16", "TestSafeUint64ToInt16", TestSafeUint64ToInt16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint16", "TestSafeUint64ToUint16", TestSafeUint64ToUint16, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt32", "TestSafeUint64ToInt32", TestSafeUint64ToInt32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToUint32", "TestSafeUint64ToUint32", TestSafeUint64ToUint32, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToIntn", "TestSafeUint64ToIntn", TestSafeUint64ToIntn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToUintn", "TestSafeUint64ToUintn", TestSafeUint64ToUintn, NULL, NULL, NULL);\r
- AddTestCase(ConversionTestSuite, "Test SafeUint64ToInt64", "TestSafeUint64ToInt64", TestSafeUint64ToInt64, NULL, NULL, NULL);\r
+\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt8ToUint8", "TestSafeInt8ToUint8", TestSafeInt8ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt8ToUint16", "TestSafeInt8ToUint16", TestSafeInt8ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt8ToUint32", "TestSafeInt8ToUint32", TestSafeInt8ToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt8ToUintn", "TestSafeInt8ToUintn", TestSafeInt8ToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt8ToUint64", "TestSafeInt8ToUint64", TestSafeInt8ToUint64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint8ToInt8", "TestSafeUint8ToInt8", TestSafeUint8ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint8ToChar8", "TestSafeUint8ToChar8", TestSafeUint8ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToInt8", "TestSafeInt16ToInt8", TestSafeInt16ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToChar8", "TestSafeInt16ToChar8", TestSafeInt16ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToUint8", "TestSafeInt16ToUint8", TestSafeInt16ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToUint16", "TestSafeInt16ToUint16", TestSafeInt16ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToUint32", "TestSafeInt16ToUint32", TestSafeInt16ToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToUintn", "TestSafeInt16ToUintn", TestSafeInt16ToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt16ToUint64", "TestSafeInt16ToUint64", TestSafeInt16ToUint64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint16ToInt8", "TestSafeUint16ToInt8", TestSafeUint16ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint16ToChar8", "TestSafeUint16ToChar8", TestSafeUint16ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint16ToUint8", "TestSafeUint16ToUint8", TestSafeUint16ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint16ToInt16", "TestSafeUint16ToInt16", TestSafeUint16ToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToInt8", "TestSafeInt32ToInt8", TestSafeInt32ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToChar8", "TestSafeInt32ToChar8", TestSafeInt32ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToUint8", "TestSafeInt32ToUint8", TestSafeInt32ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToInt16", "TestSafeInt32ToInt16", TestSafeInt32ToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToUint16", "TestSafeInt32ToUint16", TestSafeInt32ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToUint32", "TestSafeInt32ToUint32", TestSafeInt32ToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToUintn", "TestSafeInt32ToUintn", TestSafeInt32ToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt32ToUint64", "TestSafeInt32ToUint64", TestSafeInt32ToUint64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToInt8", "TestSafeUint32ToInt8", TestSafeUint32ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToChar8", "TestSafeUint32ToChar8", TestSafeUint32ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToUint8", "TestSafeUint32ToUint8", TestSafeUint32ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToInt16", "TestSafeUint32ToInt16", TestSafeUint32ToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToUint16", "TestSafeUint32ToUint16", TestSafeUint32ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToInt32", "TestSafeUint32ToInt32", TestSafeUint32ToInt32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint32ToIntn", "TestSafeUint32ToIntn", TestSafeUint32ToIntn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToInt8", "TestSafeIntnToInt8", TestSafeIntnToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToChar8", "TestSafeIntnToChar8", TestSafeIntnToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToUint8", "TestSafeIntnToUint8", TestSafeIntnToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToInt16", "TestSafeIntnToInt16", TestSafeIntnToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToUint16", "TestSafeIntnToUint16", TestSafeIntnToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToInt32", "TestSafeIntnToInt32", TestSafeIntnToInt32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToUint32", "TestSafeIntnToUint32", TestSafeIntnToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToUintn", "TestSafeIntnToUintn", TestSafeIntnToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeIntnToUint64", "TestSafeIntnToUint64", TestSafeIntnToUint64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToInt8", "TestSafeUintnToInt8", TestSafeUintnToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToChar8", "TestSafeUintnToChar8", TestSafeUintnToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToUint8", "TestSafeUintnToUint8", TestSafeUintnToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToInt16", "TestSafeUintnToInt16", TestSafeUintnToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToUint16", "TestSafeUintnToUint16", TestSafeUintnToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToInt32", "TestSafeUintnToInt32", TestSafeUintnToInt32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToUint32", "TestSafeUintnToUint32", TestSafeUintnToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToIntn", "TestSafeUintnToIntn", TestSafeUintnToIntn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUintnToInt64", "TestSafeUintnToInt64", TestSafeUintnToInt64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToInt8", "TestSafeInt64ToInt8", TestSafeInt64ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToChar8", "TestSafeInt64ToChar8", TestSafeInt64ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToUint8", "TestSafeInt64ToUint8", TestSafeInt64ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToInt16", "TestSafeInt64ToInt16", TestSafeInt64ToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToUint16", "TestSafeInt64ToUint16", TestSafeInt64ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToInt32", "TestSafeInt64ToInt32", TestSafeInt64ToInt32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToUint32", "TestSafeInt64ToUint32", TestSafeInt64ToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToIntn", "TestSafeInt64ToIntn", TestSafeInt64ToIntn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToUintn", "TestSafeInt64ToUintn", TestSafeInt64ToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeInt64ToUint64", "TestSafeInt64ToUint64", TestSafeInt64ToUint64, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToInt8", "TestSafeUint64ToInt8", TestSafeUint64ToInt8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToChar8", "TestSafeUint64ToChar8", TestSafeUint64ToChar8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToUint8", "TestSafeUint64ToUint8", TestSafeUint64ToUint8, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToInt16", "TestSafeUint64ToInt16", TestSafeUint64ToInt16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToUint16", "TestSafeUint64ToUint16", TestSafeUint64ToUint16, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToInt32", "TestSafeUint64ToInt32", TestSafeUint64ToInt32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToUint32", "TestSafeUint64ToUint32", TestSafeUint64ToUint32, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToIntn", "TestSafeUint64ToIntn", TestSafeUint64ToIntn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToUintn", "TestSafeUint64ToUintn", TestSafeUint64ToUintn, NULL, NULL, NULL);\r
+ AddTestCase (ConversionTestSuite, "Test SafeUint64ToInt64", "TestSafeUint64ToInt64", TestSafeUint64ToInt64, NULL, NULL, NULL);\r
\r
//\r
// Test the addition and subtraction functions\r
//\r
- Status = CreateUnitTestSuite(&AdditionSubtractionTestSuite, Framework, "Int Safe Add/Subtract Test Suite", "Common.SafeInt.AddSubtract", NULL, NULL);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Add/Subtract Test Suite\n"));\r
+ Status = CreateUnitTestSuite (&AdditionSubtractionTestSuite, Framework, "Int Safe Add/Subtract Test Suite", "Common.SafeInt.AddSubtract", NULL, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Add/Subtract Test Suite\n"));\r
Status = EFI_OUT_OF_RESOURCES;\r
goto EXIT;\r
}\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint8Add", "TestSafeUint8Add", TestSafeUint8Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint16Add", "TestSafeUint16Add", TestSafeUint16Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint32Add", "TestSafeUint32Add", TestSafeUint32Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUintnAdd", "TestSafeUintnAdd", TestSafeUintnAdd, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint64Add", "TestSafeUint64Add", TestSafeUint64Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt8Add", "TestSafeInt8Add", TestSafeInt8Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt16Add", "TestSafeInt16Add", TestSafeInt16Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt32Add", "TestSafeInt32Add", TestSafeInt32Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeIntnAdd", "TestSafeIntnAdd", TestSafeIntnAdd, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt64Add", "TestSafeInt64Add", TestSafeInt64Add, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint8Sub", "TestSafeUint8Sub", TestSafeUint8Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint16Sub", "TestSafeUint16Sub", TestSafeUint16Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint32Sub", "TestSafeUint32Sub", TestSafeUint32Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUintnSub", "TestSafeUintnSub", TestSafeUintnSub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeUint64Sub", "TestSafeUint64Sub", TestSafeUint64Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt8Sub", "TestSafeInt8Sub", TestSafeInt8Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt16Sub", "TestSafeInt16Sub", TestSafeInt16Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt32Sub", "TestSafeInt32Sub", TestSafeInt32Sub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeIntnSub", "TestSafeIntnSub", TestSafeIntnSub, NULL, NULL, NULL);\r
- AddTestCase(AdditionSubtractionTestSuite, "Test SafeInt64Sub", "TestSafeInt64Sub", TestSafeInt64Sub, NULL, NULL, NULL);\r
+\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint8Add", "TestSafeUint8Add", TestSafeUint8Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint16Add", "TestSafeUint16Add", TestSafeUint16Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint32Add", "TestSafeUint32Add", TestSafeUint32Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUintnAdd", "TestSafeUintnAdd", TestSafeUintnAdd, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint64Add", "TestSafeUint64Add", TestSafeUint64Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt8Add", "TestSafeInt8Add", TestSafeInt8Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt16Add", "TestSafeInt16Add", TestSafeInt16Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt32Add", "TestSafeInt32Add", TestSafeInt32Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeIntnAdd", "TestSafeIntnAdd", TestSafeIntnAdd, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt64Add", "TestSafeInt64Add", TestSafeInt64Add, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint8Sub", "TestSafeUint8Sub", TestSafeUint8Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint16Sub", "TestSafeUint16Sub", TestSafeUint16Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint32Sub", "TestSafeUint32Sub", TestSafeUint32Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUintnSub", "TestSafeUintnSub", TestSafeUintnSub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeUint64Sub", "TestSafeUint64Sub", TestSafeUint64Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt8Sub", "TestSafeInt8Sub", TestSafeInt8Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt16Sub", "TestSafeInt16Sub", TestSafeInt16Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt32Sub", "TestSafeInt32Sub", TestSafeInt32Sub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeIntnSub", "TestSafeIntnSub", TestSafeIntnSub, NULL, NULL, NULL);\r
+ AddTestCase (AdditionSubtractionTestSuite, "Test SafeInt64Sub", "TestSafeInt64Sub", TestSafeInt64Sub, NULL, NULL, NULL);\r
\r
//\r
// Test the multiplication functions\r
//\r
- Status = CreateUnitTestSuite(&MultiplicationTestSuite, Framework, "Int Safe Multiply Test Suite", "Common.SafeInt.Multiply", NULL, NULL);\r
- if (EFI_ERROR(Status)) {\r
- DEBUG((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Multiply Test Suite\n"));\r
+ Status = CreateUnitTestSuite (&MultiplicationTestSuite, Framework, "Int Safe Multiply Test Suite", "Common.SafeInt.Multiply", NULL, NULL);\r
+ if (EFI_ERROR (Status)) {\r
+ DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Int Safe Multiply Test Suite\n"));\r
Status = EFI_OUT_OF_RESOURCES;\r
goto EXIT;\r
}\r
- AddTestCase(MultiplicationTestSuite, "Test SafeUint8Mult", "TestSafeUint8Mult", TestSafeUint8Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeUint16Mult", "TestSafeUint16Mult", TestSafeUint16Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeUint32Mult", "TestSafeUint32Mult", TestSafeUint32Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeUintnMult", "TestSafeUintnMult", TestSafeUintnMult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeUint64Mult", "TestSafeUint64Mult", TestSafeUint64Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeInt8Mult", "TestSafeInt8Mult", TestSafeInt8Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeInt16Mult", "TestSafeInt16Mult", TestSafeInt16Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeInt32Mult", "TestSafeInt32Mult", TestSafeInt32Mult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeIntnMult", "TestSafeIntnMult", TestSafeIntnMult, NULL, NULL, NULL);\r
- AddTestCase(MultiplicationTestSuite, "Test SafeInt64Mult", "TestSafeInt64Mult", TestSafeInt64Mult, NULL, NULL, NULL);\r
+\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeUint8Mult", "TestSafeUint8Mult", TestSafeUint8Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeUint16Mult", "TestSafeUint16Mult", TestSafeUint16Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeUint32Mult", "TestSafeUint32Mult", TestSafeUint32Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeUintnMult", "TestSafeUintnMult", TestSafeUintnMult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeUint64Mult", "TestSafeUint64Mult", TestSafeUint64Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeInt8Mult", "TestSafeInt8Mult", TestSafeInt8Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeInt16Mult", "TestSafeInt16Mult", TestSafeInt16Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeInt32Mult", "TestSafeInt32Mult", TestSafeInt32Mult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeIntnMult", "TestSafeIntnMult", TestSafeIntnMult, NULL, NULL, NULL);\r
+ AddTestCase (MultiplicationTestSuite, "Test SafeInt64Mult", "TestSafeInt64Mult", TestSafeInt64Mult, NULL, NULL, NULL);\r
\r
//\r
// Execute the tests.\r
//\r
- Status = RunAllTestSuites(Framework);\r
+ Status = RunAllTestSuites (Framework);\r
\r
EXIT:\r
if (Framework != NULL) {\r
- FreeUnitTestFramework(Framework);\r
+ FreeUnitTestFramework (Framework);\r
}\r
\r
return Status;\r
EFI_STATUS\r
EFIAPI\r
PeiEntryPoint (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
return UefiTestMain ();\r
\r
int\r
main (\r
- int argc,\r
- char *argv[]\r
+ int argc,\r
+ char *argv[]\r
)\r
{\r
return UefiTestMain ();\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeInt32ToUintn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeInt32ToUintn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUint32ToIntn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUint32ToIntn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeIntnToInt32(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeIntnToInt32 (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeIntnToUint32(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeIntnToUint32 (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnToUint32(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnToUint32 (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnToIntn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnToIntn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnToInt64(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnToInt64 (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeInt64ToIntn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeInt64ToIntn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeInt64ToUintn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeInt64ToUintn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUint64ToIntn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUint64ToIntn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUint64ToUintn(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUint64ToUintn (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnAdd(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnAdd (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeIntnAdd(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeIntnAdd (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnSub(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnSub (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeIntnSub(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeIntnSub (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeUintnMult(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeUintnMult (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
UNIT_TEST_STATUS\r
EFIAPI\r
-TestSafeIntnMult(\r
- IN UNIT_TEST_CONTEXT Context\r
+TestSafeIntnMult (\r
+ IN UNIT_TEST_CONTEXT Context\r
);\r
\r
#endif\r
projects / mirror_edk2.git / commitdiff