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hw/i386: Introduce apicid functions inside X86MachineState
[mirror_qemu.git] / target / i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
e688df6b 19
1ef26b1f 20#include "qemu/osdep.h"
6a4e0614 21#include "qemu/units.h"
f348b6d1 22#include "qemu/cutils.h"
631be321 23#include "qemu/bitops.h"
0442428a 24#include "qemu/qemu-print.h"
c6dc6f63
AP		 25
26#include "cpu.h"
63c91552 27#include "exec/exec-all.h"
9c17d615 28#include "sysemu/kvm.h"
71e8a915 29#include "sysemu/reset.h"
d6dcc558 30#include "sysemu/hvf.h"
8932cfdf 31#include "sysemu/cpus.h"
50a2c6e5 32#include "kvm_i386.h"
6cb8f2a6 33#include "sev_i386.h"
c6dc6f63 34
d49b6836 35#include "qemu/error-report.h"
0b8fa32f 36#include "qemu/module.h"
1de7afc9
PB		 37#include "qemu/option.h"
38#include "qemu/config-file.h"
e688df6b 39#include "qapi/error.h"
8ac25c84 40#include "qapi/qapi-visit-machine.h"
112ed241 41#include "qapi/qapi-visit-run-state.h"
452fcdbc 42#include "qapi/qmp/qdict.h"
7b1b5d19 43#include "qapi/qmp/qerror.h"
7b1b5d19 44#include "qapi/visitor.h"
f99fd7ca 45#include "qom/qom-qobject.h"
9c17d615 46#include "sysemu/arch_init.h"
7f7b4e7a 47#include "qapi/qapi-commands-machine-target.h"
71ad61d3 48
1814eab6 49#include "standard-headers/asm-x86/kvm_para.h"
65dee380 50
9c17d615 51#include "sysemu/sysemu.h"
14a48c1d 52#include "sysemu/tcg.h"
53a89e26 53#include "hw/qdev-properties.h"
5232d00a 54#include "hw/i386/topology.h"
bdeec802 55#ifndef CONFIG_USER_ONLY
2001d0cd 56#include "exec/address-spaces.h"
0d09e41a 57#include "hw/xen/xen.h"
0d09e41a 58#include "hw/i386/apic_internal.h"
0e11fc69 59#include "hw/boards.h"
bdeec802
IM		 60#endif
61
b666d2a4
RH		 62#include "disas/capstone.h"
63
7e3482f8
EH		 64/* Helpers for building CPUID[2] descriptors: */
65
66struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72};
5e891bf8 73
7e3482f8
EH		 74/*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
5f00335a 79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
7e3482f8 80 .associativity = 4, .line_size = 32, },
5f00335a 81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
7e3482f8 82 .associativity = 4, .line_size = 32, },
5f00335a 83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 84 .associativity = 4, .line_size = 64, },
5f00335a 85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 86 .associativity = 2, .line_size = 32, },
5f00335a 87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 88 .associativity = 4, .line_size = 32, },
5f00335a 89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 90 .associativity = 4, .line_size = 64, },
5f00335a 91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
7e3482f8 92 .associativity = 6, .line_size = 64, },
5f00335a 93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 94 .associativity = 2, .line_size = 64, },
5f00335a 95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8
EH		 96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
5f00335a 100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
5f00335a 105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 106 .associativity = 8, .line_size = 64, },
5f00335a 107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
7e3482f8 108 .associativity = 8, .line_size = 64, },
5f00335a 109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
7e3482f8 110 .associativity = 4, .line_size = 32, },
5f00335a 111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 112 .associativity = 4, .line_size = 32, },
5f00335a 113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 114 .associativity = 4, .line_size = 32, },
5f00335a 115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 116 .associativity = 4, .line_size = 32, },
5f00335a 117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 118 .associativity = 4, .line_size = 32, },
5f00335a 119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 120 .associativity = 4, .line_size = 64, },
5f00335a 121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 122 .associativity = 8, .line_size = 64, },
5f00335a 123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8
EH		 124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
5f00335a 126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 127 .associativity = 12, .line_size = 64, },
5f00335a 128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 129 .associativity = 16, .line_size = 64, },
5f00335a 130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 131 .associativity = 12, .line_size = 64, },
5f00335a 132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
7e3482f8 133 .associativity = 16, .line_size = 64, },
5f00335a 134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 135 .associativity = 24, .line_size = 64, },
5f00335a 136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 137 .associativity = 8, .line_size = 64, },
5f00335a 138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
7e3482f8 139 .associativity = 4, .line_size = 64, },
5f00335a 140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
7e3482f8 141 .associativity = 4, .line_size = 64, },
5f00335a 142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
7e3482f8 143 .associativity = 4, .line_size = 64, },
5f00335a 144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8
EH		 145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
5f00335a 149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 150 .associativity = 8, .line_size = 64, },
5f00335a 151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 152 .associativity = 2, .line_size = 64, },
5f00335a 153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 154 .associativity = 8, .line_size = 64, },
5f00335a 155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
7e3482f8 156 .associativity = 8, .line_size = 32, },
5f00335a 157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 158 .associativity = 8, .line_size = 32, },
5f00335a 159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 160 .associativity = 8, .line_size = 32, },
5f00335a 161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 162 .associativity = 8, .line_size = 32, },
5f00335a 163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 164 .associativity = 4, .line_size = 64, },
5f00335a 165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 166 .associativity = 8, .line_size = 64, },
5f00335a 167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
7e3482f8 168 .associativity = 4, .line_size = 64, },
5f00335a 169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 170 .associativity = 4, .line_size = 64, },
5f00335a 171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 172 .associativity = 4, .line_size = 64, },
5f00335a 173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
7e3482f8 174 .associativity = 8, .line_size = 64, },
5f00335a 175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 176 .associativity = 8, .line_size = 64, },
5f00335a 177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 178 .associativity = 8, .line_size = 64, },
5f00335a 179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
7e3482f8 180 .associativity = 12, .line_size = 64, },
5f00335a 181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
7e3482f8 182 .associativity = 12, .line_size = 64, },
5f00335a 183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
7e3482f8 184 .associativity = 12, .line_size = 64, },
5f00335a 185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
7e3482f8 186 .associativity = 16, .line_size = 64, },
5f00335a 187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
7e3482f8 188 .associativity = 16, .line_size = 64, },
5f00335a 189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
7e3482f8 190 .associativity = 16, .line_size = 64, },
5f00335a 191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
7e3482f8 192 .associativity = 24, .line_size = 64, },
5f00335a 193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
7e3482f8 194 .associativity = 24, .line_size = 64, },
5f00335a 195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
7e3482f8
EH		 196 .associativity = 24, .line_size = 64, },
197};
198
199/*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203#define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
5e891bf8 204
7e3482f8
EH		 205/*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210{
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
5e891bf8 225
7e3482f8
EH		 226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227}
5e891bf8
EH		 228
229/* CPUID Leaf 4 constants: */
230
231/* EAX: */
7e3482f8
EH		 232#define CACHE_TYPE_D 1
233#define CACHE_TYPE_I 2
234#define CACHE_TYPE_UNIFIED 3
5e891bf8 235
7e3482f8 236#define CACHE_LEVEL(l) (l << 5)
5e891bf8 237
7e3482f8 238#define CACHE_SELF_INIT_LEVEL (1 << 8)
5e891bf8
EH		 239
240/* EDX: */
7e3482f8
EH		 241#define CACHE_NO_INVD_SHARING (1 << 0)
242#define CACHE_INCLUSIVE (1 << 1)
243#define CACHE_COMPLEX_IDX (1 << 2)
244
245/* Encode CacheType for CPUID[4].EAX */
5f00335a
EH		 246#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
7e3482f8
EH		 250
251
252/* Encode cache info for CPUID[4] */
253static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257{
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283}
284
285/* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287{
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294}
5e891bf8
EH		 295
296#define ASSOC_FULL 0xFF
297
298/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
7e3482f8
EH		 312/*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319{
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339}
5e891bf8 340
8f4202fb 341/* Encode cache info for CPUID[8000001D] */
dd08ef03
BM		 342static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
8f4202fb
BM		 346{
347 uint32_t l3_cores;
dd08ef03
BM		 348 unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
349
8f4202fb
BM		 350 assert(cache->size == cache->line_size * cache->associativity *
351 cache->partitions * cache->sets);
352
353 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
354 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
355
356 /* L3 is shared among multiple cores */
357 if (cache->level == 3) {
dd08ef03
BM		 358 l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
359 topo_info->cores_per_die *
360 topo_info->threads_per_core),
361 nodes);
362 *eax |= (l3_cores - 1) << 14;
8f4202fb 363 } else {
dd08ef03 364 *eax |= ((topo_info->threads_per_core - 1) << 14);
8f4202fb
BM		 365 }
366
367 assert(cache->line_size > 0);
368 assert(cache->partitions > 0);
369 assert(cache->associativity > 0);
370 /* We don't implement fully-associative caches */
371 assert(cache->associativity < cache->sets);
372 *ebx = (cache->line_size - 1) |
373 ((cache->partitions - 1) << 12) |
374 ((cache->associativity - 1) << 22);
375
376 assert(cache->sets > 0);
377 *ecx = cache->sets - 1;
378
379 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
380 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
381 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
382}
383
ed78467a 384/* Encode cache info for CPUID[8000001E] */
dd08ef03 385static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
ed78467a
BM		 386 uint32_t *eax, uint32_t *ebx,
387 uint32_t *ecx, uint32_t *edx)
388{
dd08ef03
BM		 389 X86CPUTopoIDs topo_ids = {0};
390 unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
631be321 391 int shift;
ed78467a 392
dd08ef03
BM		 393 x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
394
ed78467a
BM		 395 *eax = cpu->apic_id;
396 /*
397 * CPUID_Fn8000001E_EBX
398 * 31:16 Reserved
399 * 15:8 Threads per core (The number of threads per core is
400 * Threads per core + 1)
401 * 7:0 Core id (see bit decoding below)
402 * SMT:
403 * 4:3 node id
404 * 2 Core complex id
405 * 1:0 Core id
406 * Non SMT:
407 * 5:4 node id
408 * 3 Core complex id
409 * 1:0 Core id
410 */
dd08ef03
BM		 411 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
412 (topo_ids.core_id);
ed78467a
BM		 413 /*
414 * CPUID_Fn8000001E_ECX
415 * 31:11 Reserved
416 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
417 * 7:0 Node id (see bit decoding below)
418 * 2 Socket id
419 * 1:0 Node id
420 */
dd08ef03
BM		 421 if (nodes <= 4) {
422 *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
631be321
BM		 423 } else {
424 /*
425 * Node id fix up. Actual hardware supports up to 4 nodes. But with
426 * more than 32 cores, we may end up with more than 4 nodes.
427 * Node id is a combination of socket id and node id. Only requirement
428 * here is that this number should be unique accross the system.
429 * Shift the socket id to accommodate more nodes. We dont expect both
430 * socket id and node id to be big number at the same time. This is not
431 * an ideal config but we need to to support it. Max nodes we can have
432 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
433 * 5 bits for nodes. Find the left most set bit to represent the total
434 * number of nodes. find_last_bit returns last set bit(0 based). Left
435 * shift(+1) the socket id to represent all the nodes.
436 */
dd08ef03 437 nodes -= 1;
631be321 438 shift = find_last_bit(&nodes, 8);
dd08ef03
BM		 439 *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
440 topo_ids.node_id;
631be321 441 }
ed78467a
BM		 442 *edx = 0;
443}
444
ab8f992e
BM		 445/*
446 * Definitions of the hardcoded cache entries we expose:
447 * These are legacy cache values. If there is a need to change any
448 * of these values please use builtin_x86_defs
449 */
5e891bf8
EH		 450
451/* L1 data cache: */
ab8f992e 452static CPUCacheInfo legacy_l1d_cache = {
5f00335a 453 .type = DATA_CACHE,
7e3482f8
EH		 454 .level = 1,
455 .size = 32 * KiB,
456 .self_init = 1,
457 .line_size = 64,
458 .associativity = 8,
459 .sets = 64,
460 .partitions = 1,
461 .no_invd_sharing = true,
462};
463
5e891bf8 464/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 465static CPUCacheInfo legacy_l1d_cache_amd = {
5f00335a 466 .type = DATA_CACHE,
7e3482f8
EH		 467 .level = 1,
468 .size = 64 * KiB,
469 .self_init = 1,
470 .line_size = 64,
471 .associativity = 2,
472 .sets = 512,
473 .partitions = 1,
474 .lines_per_tag = 1,
475 .no_invd_sharing = true,
476};
5e891bf8
EH		 477
478/* L1 instruction cache: */
ab8f992e 479static CPUCacheInfo legacy_l1i_cache = {
5f00335a 480 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 481 .level = 1,
482 .size = 32 * KiB,
483 .self_init = 1,
484 .line_size = 64,
485 .associativity = 8,
486 .sets = 64,
487 .partitions = 1,
488 .no_invd_sharing = true,
489};
490
5e891bf8 491/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
ab8f992e 492static CPUCacheInfo legacy_l1i_cache_amd = {
5f00335a 493 .type = INSTRUCTION_CACHE,
7e3482f8
EH		 494 .level = 1,
495 .size = 64 * KiB,
496 .self_init = 1,
497 .line_size = 64,
498 .associativity = 2,
499 .sets = 512,
500 .partitions = 1,
501 .lines_per_tag = 1,
502 .no_invd_sharing = true,
503};
5e891bf8
EH		 504
505/* Level 2 unified cache: */
ab8f992e 506static CPUCacheInfo legacy_l2_cache = {
7e3482f8
EH		 507 .type = UNIFIED_CACHE,
508 .level = 2,
509 .size = 4 * MiB,
510 .self_init = 1,
511 .line_size = 64,
512 .associativity = 16,
513 .sets = 4096,
514 .partitions = 1,
515 .no_invd_sharing = true,
516};
517
5e891bf8 518/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
ab8f992e 519static CPUCacheInfo legacy_l2_cache_cpuid2 = {
7e3482f8
EH		 520 .type = UNIFIED_CACHE,
521 .level = 2,
522 .size = 2 * MiB,
523 .line_size = 64,
524 .associativity = 8,
525};
526
527
5e891bf8 528/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
ab8f992e 529static CPUCacheInfo legacy_l2_cache_amd = {
7e3482f8
EH		 530 .type = UNIFIED_CACHE,
531 .level = 2,
532 .size = 512 * KiB,
533 .line_size = 64,
534 .lines_per_tag = 1,
535 .associativity = 16,
536 .sets = 512,
537 .partitions = 1,
538};
5e891bf8 539
14c985cf 540/* Level 3 unified cache: */
ab8f992e 541static CPUCacheInfo legacy_l3_cache = {
7e3482f8
EH		 542 .type = UNIFIED_CACHE,
543 .level = 3,
544 .size = 16 * MiB,
545 .line_size = 64,
546 .associativity = 16,
547 .sets = 16384,
548 .partitions = 1,
549 .lines_per_tag = 1,
550 .self_init = true,
551 .inclusive = true,
552 .complex_indexing = true,
553};
5e891bf8
EH		 554
555/* TLB definitions: */
556
557#define L1_DTLB_2M_ASSOC 1
558#define L1_DTLB_2M_ENTRIES 255
559#define L1_DTLB_4K_ASSOC 1
560#define L1_DTLB_4K_ENTRIES 255
561
562#define L1_ITLB_2M_ASSOC 1
563#define L1_ITLB_2M_ENTRIES 255
564#define L1_ITLB_4K_ASSOC 1
565#define L1_ITLB_4K_ENTRIES 255
566
567#define L2_DTLB_2M_ASSOC 0 /* disabled */
568#define L2_DTLB_2M_ENTRIES 0 /* disabled */
569#define L2_DTLB_4K_ASSOC 4
570#define L2_DTLB_4K_ENTRIES 512
571
572#define L2_ITLB_2M_ASSOC 0 /* disabled */
573#define L2_ITLB_2M_ENTRIES 0 /* disabled */
574#define L2_ITLB_4K_ASSOC 4
575#define L2_ITLB_4K_ENTRIES 512
576
e37a5c7f
CP		 577/* CPUID Leaf 0x14 constants: */
578#define INTEL_PT_MAX_SUBLEAF 0x1
579/*
580 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
581 * MSR can be accessed;
582 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
583 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
584 * of Intel PT MSRs across warm reset;
585 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
586 */
587#define INTEL_PT_MINIMAL_EBX 0xf
588/*
589 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
590 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
591 * accessed;
592 * bit[01]: ToPA tables can hold any number of output entries, up to the
593 * maximum allowed by the MaskOrTableOffset field of
594 * IA32_RTIT_OUTPUT_MASK_PTRS;
595 * bit[02]: Support Single-Range Output scheme;
596 */
597#define INTEL_PT_MINIMAL_ECX 0x7
c078ca96
LK		 598/* generated packets which contain IP payloads have LIP values */
599#define INTEL_PT_IP_LIP (1 << 31)
e37a5c7f
CP		 600#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
601#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
602#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
603#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
604#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
5e891bf8 605
99b88a17
IM		 606static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
607 uint32_t vendor2, uint32_t vendor3)
608{
609 int i;
610 for (i = 0; i < 4; i++) {
611 dst[i] = vendor1 >> (8 * i);
612 dst[i + 4] = vendor2 >> (8 * i);
613 dst[i + 8] = vendor3 >> (8 * i);
614 }
615 dst[CPUID_VENDOR_SZ] = '\0';
616}
617
621626ce
EH		 618#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
619#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
620 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
621#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
622 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
623 CPUID_PSE36 | CPUID_FXSR)
624#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
625#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
626 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
627 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
628 CPUID_PAE | CPUID_SEP | CPUID_APIC)
629
630#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
631 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
632 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
633 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
b6c5a6f0 634 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
621626ce
EH		 635 /* partly implemented:
636 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
637 /* missing:
638 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
639#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
19dc85db 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
369fd5ca
RH		 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
644 CPUID_EXT_RDRAND)
621626ce
EH		 645 /* missing:
646 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
647 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
648 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
19dc85db 649 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
369fd5ca 650 CPUID_EXT_F16C */
621626ce
EH		 651
652#ifdef TARGET_X86_64
653#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
654#else
655#define TCG_EXT2_X86_64_FEATURES 0
656#endif
657
658#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
659 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
660 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
661 TCG_EXT2_X86_64_FEATURES)
662#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
663 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
664#define TCG_EXT4_FEATURES 0
fe441054 665#define TCG_SVM_FEATURES CPUID_SVM_NPT
621626ce
EH		 666#define TCG_KVM_FEATURES 0
667#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
0c47242b
XG		 668 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
669 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
7eb24386
PB		 670 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
671 CPUID_7_0_EBX_ERMS)
621626ce 672 /* missing:
07929f2a 673 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
7eb24386 674 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
621626ce 675 CPUID_7_0_EBX_RDSEED */
9ccb9784
EH		 676#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
677 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
6c7c3c21 678 CPUID_7_0_ECX_LA57)
95ea69fb 679#define TCG_7_0_EDX_FEATURES 0
80db491d 680#define TCG_7_1_EAX_FEATURES 0
303752a9 681#define TCG_APM_FEATURES 0
28b8e4d0 682#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
c9cfe8f9
RH		 683#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
684 /* missing:
685 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
621626ce 686
07585923
RH		 687typedef enum FeatureWordType {
688 CPUID_FEATURE_WORD,
689 MSR_FEATURE_WORD,
690} FeatureWordType;
691
5ef57876 692typedef struct FeatureWordInfo {
07585923 693 FeatureWordType type;
2d5312da
EH		 694 /* feature flags names are taken from "Intel Processor Identification and
695 * the CPUID Instruction" and AMD's "CPUID Specification".
696 * In cases of disagreement between feature naming conventions,
697 * aliases may be added.
698 */
ede146c2 699 const char *feat_names[64];
07585923
RH		 700 union {
701 /* If type==CPUID_FEATURE_WORD */
702 struct {
703 uint32_t eax; /* Input EAX for CPUID */
704 bool needs_ecx; /* CPUID instruction uses ECX as input */
705 uint32_t ecx; /* Input ECX value for CPUID */
706 int reg; /* output register (R_* constant) */
707 } cpuid;
708 /* If type==MSR_FEATURE_WORD */
709 struct {
710 uint32_t index;
07585923
RH		 711 } msr;
712 };
ede146c2
PB		 713 uint64_t tcg_features; /* Feature flags supported by TCG */
714 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
715 uint64_t migratable_flags; /* Feature flags known to be migratable */
0d914f39 716 /* Features that shouldn't be auto-enabled by "-cpu host" */
ede146c2 717 uint64_t no_autoenable_flags;
5ef57876
EH		 718} FeatureWordInfo;
719
720static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
bffd67b0 721 [FEAT_1_EDX] = {
07585923 722 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 723 .feat_names = {
724 "fpu", "vme", "de", "pse",
725 "tsc", "msr", "pae", "mce",
726 "cx8", "apic", NULL, "sep",
727 "mtrr", "pge", "mca", "cmov",
728 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
729 NULL, "ds" /* Intel dts */, "acpi", "mmx",
730 "fxsr", "sse", "sse2", "ss",
731 "ht" /* Intel htt */, "tm", "ia64", "pbe",
732 },
07585923 733 .cpuid = {.eax = 1, .reg = R_EDX, },
37ce3522 734 .tcg_features = TCG_FEATURES,
bffd67b0
EH		 735 },
736 [FEAT_1_ECX] = {
07585923 737 .type = CPUID_FEATURE_WORD,
2d5312da 738 .feat_names = {
16d2fcaa 739 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
fc7dfd20 740 "ds-cpl", "vmx", "smx", "est",
2d5312da
EH		 741 "tm2", "ssse3", "cid", NULL,
742 "fma", "cx16", "xtpr", "pdcm",
16d2fcaa
EH		 743 NULL, "pcid", "dca", "sse4.1",
744 "sse4.2", "x2apic", "movbe", "popcnt",
f1a23522 745 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
2d5312da
EH		 746 "avx", "f16c", "rdrand", "hypervisor",
747 },
07585923 748 .cpuid = { .eax = 1, .reg = R_ECX, },
37ce3522 749 .tcg_features = TCG_EXT_FEATURES,
bffd67b0 750 },
2d5312da
EH		 751 /* Feature names that are already defined on feature_name[] but
752 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
753 * names on feat_names below. They are copied automatically
754 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
755 */
bffd67b0 756 [FEAT_8000_0001_EDX] = {
07585923 757 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 758 .feat_names = {
759 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
760 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
761 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
762 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
763 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
16d2fcaa
EH		 764 "nx", NULL, "mmxext", NULL /* mmx */,
765 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
766 NULL, "lm", "3dnowext", "3dnow",
2d5312da 767 },
07585923 768 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
37ce3522 769 .tcg_features = TCG_EXT2_FEATURES,
bffd67b0
EH		 770 },
771 [FEAT_8000_0001_ECX] = {
07585923 772 .type = CPUID_FEATURE_WORD,
2d5312da 773 .feat_names = {
fc7dfd20 774 "lahf-lm", "cmp-legacy", "svm", "extapic",
2d5312da
EH		 775 "cr8legacy", "abm", "sse4a", "misalignsse",
776 "3dnowprefetch", "osvw", "ibs", "xop",
777 "skinit", "wdt", NULL, "lwp",
fc7dfd20
EH		 778 "fma4", "tce", NULL, "nodeid-msr",
779 NULL, "tbm", "topoext", "perfctr-core",
780 "perfctr-nb", NULL, NULL, NULL,
2d5312da
EH		 781 NULL, NULL, NULL, NULL,
782 },
07585923 783 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
37ce3522 784 .tcg_features = TCG_EXT3_FEATURES,
7210a02c
EH		 785 /*
786 * TOPOEXT is always allowed but can't be enabled blindly by
787 * "-cpu host", as it requires consistent cache topology info
788 * to be provided so it doesn't confuse guests.
789 */
790 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
bffd67b0 791 },
89e49c8b 792 [FEAT_C000_0001_EDX] = {
07585923 793 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 794 .feat_names = {
795 NULL, NULL, "xstore", "xstore-en",
796 NULL, NULL, "xcrypt", "xcrypt-en",
797 "ace2", "ace2-en", "phe", "phe-en",
798 "pmm", "pmm-en", NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
803 },
07585923 804 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
37ce3522 805 .tcg_features = TCG_EXT4_FEATURES,
89e49c8b 806 },
bffd67b0 807 [FEAT_KVM] = {
07585923 808 .type = CPUID_FEATURE_WORD,
2d5312da 809 .feat_names = {
fc7dfd20
EH		 810 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
811 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
7f710c32 812 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
b896c4b5 813 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
2d5312da
EH		 814 NULL, NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 "kvmclock-stable-bit", NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 },
07585923 819 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
37ce3522 820 .tcg_features = TCG_KVM_FEATURES,
bffd67b0 821 },
be777326 822 [FEAT_KVM_HINTS] = {
07585923 823 .type = CPUID_FEATURE_WORD,
be777326
WL		 824 .feat_names = {
825 "kvm-hint-dedicated", NULL, NULL, NULL,
826 NULL, NULL, NULL, NULL,
827 NULL, NULL, NULL, NULL,
828 NULL, NULL, NULL, NULL,
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 NULL, NULL, NULL, NULL,
833 },
07585923 834 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
be777326 835 .tcg_features = TCG_KVM_FEATURES,
0d914f39
EH		 836 /*
837 * KVM hints aren't auto-enabled by -cpu host, they need to be
838 * explicitly enabled in the command-line.
839 */
840 .no_autoenable_flags = ~0U,
be777326 841 },
abd5fc4c
VK		 842 /*
843 * .feat_names are commented out for Hyper-V enlightenments because we
844 * don't want to have two different ways for enabling them on QEMU command
845 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
846 * enabling several feature bits simultaneously, exposing these bits
847 * individually may just confuse guests.
848 */
c35bd19a 849 [FEAT_HYPERV_EAX] = {
07585923 850 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 851 .feat_names = {
852 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
853 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
854 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
855 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
856 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
857 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
ba6a4fd9
VK		 858 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
859 NULL, NULL,
2d5312da
EH		 860 NULL, NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 },
07585923 865 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
c35bd19a
EY		 866 },
867 [FEAT_HYPERV_EBX] = {
07585923 868 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 869 .feat_names = {
870 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
871 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
872 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
873 NULL /* hv_create_port */, NULL /* hv_connect_port */,
874 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
875 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
876 NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
07585923 882 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
c35bd19a
EY		 883 },
884 [FEAT_HYPERV_EDX] = {
07585923 885 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 886 .feat_names = {
887 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
888 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
889 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
890 NULL, NULL,
891 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 },
07585923 898 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
c35bd19a 899 },
a2b107db
VK		 900 [FEAT_HV_RECOMM_EAX] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 NULL /* hv_recommend_pv_as_switch */,
904 NULL /* hv_recommend_pv_tlbflush_local */,
905 NULL /* hv_recommend_pv_tlbflush_remote */,
906 NULL /* hv_recommend_msr_apic_access */,
907 NULL /* hv_recommend_msr_reset */,
908 NULL /* hv_recommend_relaxed_timing */,
909 NULL /* hv_recommend_dma_remapping */,
910 NULL /* hv_recommend_int_remapping */,
911 NULL /* hv_recommend_x2apic_msrs */,
912 NULL /* hv_recommend_autoeoi_deprecation */,
913 NULL /* hv_recommend_pv_ipi */,
914 NULL /* hv_recommend_ex_hypercalls */,
915 NULL /* hv_hypervisor_is_nested */,
916 NULL /* hv_recommend_int_mbec */,
917 NULL /* hv_recommend_evmcs */,
918 NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
924 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
925 },
926 [FEAT_HV_NESTED_EAX] = {
927 .type = CPUID_FEATURE_WORD,
928 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
929 },
bffd67b0 930 [FEAT_SVM] = {
07585923 931 .type = CPUID_FEATURE_WORD,
2d5312da 932 .feat_names = {
fc7dfd20
EH		 933 "npt", "lbrv", "svm-lock", "nrip-save",
934 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
935 NULL, NULL, "pause-filter", NULL,
2d5312da
EH		 936 "pfthreshold", NULL, NULL, NULL,
937 NULL, NULL, NULL, NULL,
938 NULL, NULL, NULL, NULL,
939 NULL, NULL, NULL, NULL,
940 NULL, NULL, NULL, NULL,
941 },
07585923 942 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
37ce3522 943 .tcg_features = TCG_SVM_FEATURES,
bffd67b0
EH		 944 },
945 [FEAT_7_0_EBX] = {
07585923 946 .type = CPUID_FEATURE_WORD,
2d5312da 947 .feat_names = {
fc7dfd20 948 "fsgsbase", "tsc-adjust", NULL, "bmi1",
2d5312da
EH		 949 "hle", "avx2", NULL, "smep",
950 "bmi2", "erms", "invpcid", "rtm",
951 NULL, NULL, "mpx", NULL,
952 "avx512f", "avx512dq", "rdseed", "adx",
953 "smap", "avx512ifma", "pcommit", "clflushopt",
e37a5c7f 954 "clwb", "intel-pt", "avx512pf", "avx512er",
638cbd45 955 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
2d5312da 956 },
07585923
RH		 957 .cpuid = {
958 .eax = 7,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EBX,
961 },
37ce3522 962 .tcg_features = TCG_7_0_EBX_FEATURES,
bffd67b0 963 },
f74eefe0 964 [FEAT_7_0_ECX] = {
07585923 965 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 966 .feat_names = {
967 NULL, "avx512vbmi", "umip", "pku",
67192a29 968 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
aff9e6e4
YZ		 969 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
970 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
6c7c3c21 971 "la57", NULL, NULL, NULL,
2d5312da 972 NULL, NULL, "rdpid", NULL,
24261de4 973 NULL, "cldemote", NULL, "movdiri",
1c65775f 974 "movdir64b", NULL, NULL, NULL,
2d5312da 975 },
07585923
RH		 976 .cpuid = {
977 .eax = 7,
978 .needs_ecx = true, .ecx = 0,
979 .reg = R_ECX,
980 },
f74eefe0
HH		 981 .tcg_features = TCG_7_0_ECX_FEATURES,
982 },
95ea69fb 983 [FEAT_7_0_EDX] = {
07585923 984 .type = CPUID_FEATURE_WORD,
95ea69fb
LK		 985 .feat_names = {
986 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
987 NULL, NULL, NULL, NULL,
b2ae5210 988 NULL, NULL, "md-clear", NULL,
95ea69fb 989 NULL, NULL, NULL, NULL,
2924ab02 990 NULL, NULL, NULL /* pconfig */, NULL,
95ea69fb 991 NULL, NULL, NULL, NULL,
0e891658 992 NULL, NULL, "spec-ctrl", "stibp",
597360c0 993 NULL, "arch-capabilities", "core-capability", "ssbd",
95ea69fb 994 },
07585923
RH		 995 .cpuid = {
996 .eax = 7,
997 .needs_ecx = true, .ecx = 0,
998 .reg = R_EDX,
999 },
95ea69fb
LK		 1000 .tcg_features = TCG_7_0_EDX_FEATURES,
1001 },
80db491d
JL		 1002 [FEAT_7_1_EAX] = {
1003 .type = CPUID_FEATURE_WORD,
1004 .feat_names = {
1005 NULL, NULL, NULL, NULL,
1006 NULL, "avx512-bf16", NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 },
1014 .cpuid = {
1015 .eax = 7,
1016 .needs_ecx = true, .ecx = 1,
1017 .reg = R_EAX,
1018 },
1019 .tcg_features = TCG_7_1_EAX_FEATURES,
1020 },
303752a9 1021 [FEAT_8000_0007_EDX] = {
07585923 1022 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1023 .feat_names = {
1024 NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 "invtsc", NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 },
07585923 1033 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
303752a9
MT		 1034 .tcg_features = TCG_APM_FEATURES,
1035 .unmigratable_flags = CPUID_APM_INVTSC,
1036 },
1b3420e1 1037 [FEAT_8000_0008_EBX] = {
07585923 1038 .type = CPUID_FEATURE_WORD,
1b3420e1 1039 .feat_names = {
e900135d 1040 "clzero", NULL, "xsaveerptr", NULL,
1b3420e1 1041 NULL, NULL, NULL, NULL,
59a80a19 1042 NULL, "wbnoinvd", NULL, NULL,
143c30d4 1043 "ibpb", NULL, NULL, "amd-stibp",
1b3420e1
EH		 1044 NULL, NULL, NULL, NULL,
1045 NULL, NULL, NULL, NULL,
254790a9 1046 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1b3420e1
EH		 1047 NULL, NULL, NULL, NULL,
1048 },
07585923 1049 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1b3420e1
EH		 1050 .tcg_features = 0,
1051 .unmigratable_flags = 0,
1052 },
0bb0b2d2 1053 [FEAT_XSAVE] = {
07585923 1054 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1055 .feat_names = {
1056 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 },
07585923
RH		 1065 .cpuid = {
1066 .eax = 0xd,
1067 .needs_ecx = true, .ecx = 1,
1068 .reg = R_EAX,
1069 },
c9cfe8f9 1070 .tcg_features = TCG_XSAVE_FEATURES,
0bb0b2d2 1071 },
28b8e4d0 1072 [FEAT_6_EAX] = {
07585923 1073 .type = CPUID_FEATURE_WORD,
2d5312da
EH		 1074 .feat_names = {
1075 NULL, NULL, "arat", NULL,
1076 NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL,
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 },
07585923 1084 .cpuid = { .eax = 6, .reg = R_EAX, },
28b8e4d0
JK		 1085 .tcg_features = TCG_6_EAX_FEATURES,
1086 },
96193c22 1087 [FEAT_XSAVE_COMP_LO] = {
07585923
RH		 1088 .type = CPUID_FEATURE_WORD,
1089 .cpuid = {
1090 .eax = 0xD,
1091 .needs_ecx = true, .ecx = 0,
1092 .reg = R_EAX,
1093 },
96193c22 1094 .tcg_features = ~0U,
6fb2fff7
EH		 1095 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1096 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1097 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1098 XSTATE_PKRU_MASK,
96193c22
EH		 1099 },
1100 [FEAT_XSAVE_COMP_HI] = {
07585923
RH		 1101 .type = CPUID_FEATURE_WORD,
1102 .cpuid = {
1103 .eax = 0xD,
1104 .needs_ecx = true, .ecx = 0,
1105 .reg = R_EDX,
1106 },
96193c22
EH		 1107 .tcg_features = ~0U,
1108 },
d86f9636
RH		 1109 /*Below are MSR exposed features*/
1110 [FEAT_ARCH_CAPABILITIES] = {
1111 .type = MSR_FEATURE_WORD,
1112 .feat_names = {
1113 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
2a9758c5 1114 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
7fac3863 1115 "taa-no", NULL, NULL, NULL,
d86f9636
RH		 1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 },
1122 .msr = {
1123 .index = MSR_IA32_ARCH_CAPABILITIES,
d86f9636
RH		 1124 },
1125 },
597360c0
XL		 1126 [FEAT_CORE_CAPABILITY] = {
1127 .type = MSR_FEATURE_WORD,
1128 .feat_names = {
1129 NULL, NULL, NULL, NULL,
1130 NULL, "split-lock-detect", NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
1138 .msr = {
1139 .index = MSR_IA32_CORE_CAPABILITY,
597360c0
XL		 1140 },
1141 },
20a78b02
PB		 1142
1143 [FEAT_VMX_PROCBASED_CTLS] = {
1144 .type = MSR_FEATURE_WORD,
1145 .feat_names = {
1146 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1147 NULL, NULL, NULL, "vmx-hlt-exit",
1148 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1149 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1150 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1151 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1152 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1153 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1154 },
1155 .msr = {
1156 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1157 }
1158 },
1159
1160 [FEAT_VMX_SECONDARY_CTLS] = {
1161 .type = MSR_FEATURE_WORD,
1162 .feat_names = {
1163 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1164 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1165 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1166 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1167 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1168 "vmx-xsaves", NULL, NULL, NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 },
1172 .msr = {
1173 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1174 }
1175 },
1176
1177 [FEAT_VMX_PINBASED_CTLS] = {
1178 .type = MSR_FEATURE_WORD,
1179 .feat_names = {
1180 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1181 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1182 NULL, NULL, NULL, NULL,
1183 NULL, NULL, NULL, NULL,
1184 NULL, NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 NULL, NULL, NULL, NULL,
1187 NULL, NULL, NULL, NULL,
1188 },
1189 .msr = {
1190 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1191 }
1192 },
1193
1194 [FEAT_VMX_EXIT_CTLS] = {
1195 .type = MSR_FEATURE_WORD,
1196 /*
1197 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1198 * the LM CPUID bit.
1199 */
1200 .feat_names = {
1201 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1202 NULL, NULL, NULL, NULL,
1203 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1204 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1205 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1206 "vmx-exit-save-efer", "vmx-exit-load-efer",
1207 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1208 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 },
1211 .msr = {
1212 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1213 }
1214 },
1215
1216 [FEAT_VMX_ENTRY_CTLS] = {
1217 .type = MSR_FEATURE_WORD,
1218 .feat_names = {
1219 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1220 NULL, NULL, NULL, NULL,
1221 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1222 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1223 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1224 NULL, NULL, NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL,
1227 },
1228 .msr = {
1229 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1230 }
1231 },
1232
1233 [FEAT_VMX_MISC] = {
1234 .type = MSR_FEATURE_WORD,
1235 .feat_names = {
1236 NULL, NULL, NULL, NULL,
1237 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1238 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1239 NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL,
1242 NULL, NULL, NULL, NULL,
1243 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1244 },
1245 .msr = {
1246 .index = MSR_IA32_VMX_MISC,
1247 }
1248 },
1249
1250 [FEAT_VMX_EPT_VPID_CAPS] = {
1251 .type = MSR_FEATURE_WORD,
1252 .feat_names = {
1253 "vmx-ept-execonly", NULL, NULL, NULL,
1254 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1255 NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL, NULL,
1257 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1258 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1259 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1260 NULL, NULL, NULL, NULL,
1261 "vmx-invvpid", NULL, NULL, NULL,
1262 NULL, NULL, NULL, NULL,
1263 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1264 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1265 NULL, NULL, NULL, NULL,
1266 NULL, NULL, NULL, NULL,
1267 NULL, NULL, NULL, NULL,
1268 NULL, NULL, NULL, NULL,
1269 NULL, NULL, NULL, NULL,
1270 },
1271 .msr = {
1272 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1273 }
1274 },
1275
1276 [FEAT_VMX_BASIC] = {
1277 .type = MSR_FEATURE_WORD,
1278 .feat_names = {
1279 [54] = "vmx-ins-outs",
1280 [55] = "vmx-true-ctls",
1281 },
1282 .msr = {
1283 .index = MSR_IA32_VMX_BASIC,
1284 },
1285 /* Just to be safe - we don't support setting the MSEG version field. */
1286 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1287 },
1288
1289 [FEAT_VMX_VMFUNC] = {
1290 .type = MSR_FEATURE_WORD,
1291 .feat_names = {
1292 [0] = "vmx-eptp-switching",
1293 },
1294 .msr = {
1295 .index = MSR_IA32_VMX_VMFUNC,
1296 }
1297 },
1298
5ef57876
EH		 1299};
1300
99e24dbd
PB		 1301typedef struct FeatureMask {
1302 FeatureWord index;
ede146c2 1303 uint64_t mask;
99e24dbd
PB		 1304} FeatureMask;
1305
1306typedef struct FeatureDep {
1307 FeatureMask from, to;
1308} FeatureDep;
1309
1310static FeatureDep feature_dependencies[] = {
1311 {
1312 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
ede146c2 1313 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
99e24dbd
PB		 1314 },
1315 {
1316 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
ede146c2 1317 .to = { FEAT_CORE_CAPABILITY, ~0ull },
99e24dbd 1318 },
20a78b02
PB		 1319 {
1320 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1321 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1322 },
1323 {
1324 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1325 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1326 },
1327 {
1328 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1329 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1330 },
1331 {
1332 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1333 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1334 },
1335 {
1336 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1337 .to = { FEAT_VMX_MISC, ~0ull },
1338 },
1339 {
1340 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1341 .to = { FEAT_VMX_BASIC, ~0ull },
1342 },
1343 {
1344 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1345 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1346 },
1347 {
1348 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1349 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1350 },
1351 {
1352 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1353 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1354 },
1355 {
1356 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1357 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1358 },
1359 {
1360 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1361 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1362 },
1363 {
1364 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1365 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1366 },
1367 {
1368 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1369 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1370 },
1371 {
1372 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1373 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1374 },
1375 {
1376 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1377 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1378 },
1379 {
1380 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1381 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1382 },
1383 {
1384 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1385 .to = { FEAT_VMX_VMFUNC, ~0ull },
1386 },
99e24dbd
PB		 1387};
1388
8e8aba50
EH		 1389typedef struct X86RegisterInfo32 {
1390 /* Name of register */
1391 const char *name;
1392 /* QAPI enum value register */
1393 X86CPURegister32 qapi_enum;
1394} X86RegisterInfo32;
1395
1396#define REGISTER(reg) \
5d371f41 1397 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
a443bc34 1398static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
8e8aba50
EH		 1399 REGISTER(EAX),
1400 REGISTER(ECX),
1401 REGISTER(EDX),
1402 REGISTER(EBX),
1403 REGISTER(ESP),
1404 REGISTER(EBP),
1405 REGISTER(ESI),
1406 REGISTER(EDI),
1407};
1408#undef REGISTER
1409
3f32bd21
RH		 1410typedef struct ExtSaveArea {
1411 uint32_t feature, bits;
1412 uint32_t offset, size;
1413} ExtSaveArea;
1414
1415static const ExtSaveArea x86_ext_save_areas[] = {
e3c9022b
EH		 1416 [XSTATE_FP_BIT] = {
1417 /* x87 FP state component is always enabled if XSAVE is supported */
1418 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1419 /* x87 state is in the legacy region of the XSAVE area */
1420 .offset = 0,
1421 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1422 },
1423 [XSTATE_SSE_BIT] = {
1424 /* SSE state component is always enabled if XSAVE is supported */
1425 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1426 /* SSE state is in the legacy region of the XSAVE area */
1427 .offset = 0,
1428 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1429 },
cfc3b074
PB		 1430 [XSTATE_YMM_BIT] =
1431 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
ee1b09f6
EH		 1432 .offset = offsetof(X86XSaveArea, avx_state),
1433 .size = sizeof(XSaveAVX) },
cfc3b074
PB		 1434 [XSTATE_BNDREGS_BIT] =
1435 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1436 .offset = offsetof(X86XSaveArea, bndreg_state),
1437 .size = sizeof(XSaveBNDREG) },
cfc3b074
PB		 1438 [XSTATE_BNDCSR_BIT] =
1439 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
ee1b09f6
EH		 1440 .offset = offsetof(X86XSaveArea, bndcsr_state),
1441 .size = sizeof(XSaveBNDCSR) },
cfc3b074
PB		 1442 [XSTATE_OPMASK_BIT] =
1443 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1444 .offset = offsetof(X86XSaveArea, opmask_state),
1445 .size = sizeof(XSaveOpmask) },
cfc3b074
PB		 1446 [XSTATE_ZMM_Hi256_BIT] =
1447 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1448 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1449 .size = sizeof(XSaveZMM_Hi256) },
cfc3b074
PB		 1450 [XSTATE_Hi16_ZMM_BIT] =
1451 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
ee1b09f6
EH		 1452 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1453 .size = sizeof(XSaveHi16_ZMM) },
cfc3b074
PB		 1454 [XSTATE_PKRU_BIT] =
1455 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
ee1b09f6
EH		 1456 .offset = offsetof(X86XSaveArea, pkru_state),
1457 .size = sizeof(XSavePKRU) },
2560f19f 1458};
8e8aba50 1459
1fda6198
EH		 1460static uint32_t xsave_area_size(uint64_t mask)
1461{
1462 int i;
e3c9022b 1463 uint64_t ret = 0;
1fda6198 1464
e3c9022b 1465 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1fda6198
EH		 1466 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1467 if ((mask >> i) & 1) {
1468 ret = MAX(ret, esa->offset + esa->size);
1469 }
1470 }
1471 return ret;
1472}
1473
d6dcc558
SAGDR		 1474static inline bool accel_uses_host_cpuid(void)
1475{
1476 return kvm_enabled() || hvf_enabled();
1477}
1478
96193c22
EH		 1479static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1480{
1481 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1482 cpu->env.features[FEAT_XSAVE_COMP_LO];
1483}
1484
8b4beddc
EH		 1485const char *get_register_name_32(unsigned int reg)
1486{
31ccdde2 1487 if (reg >= CPU_NB_REGS32) {
8b4beddc
EH		 1488 return NULL;
1489 }
8e8aba50 1490 return x86_reg_info_32[reg].name;
8b4beddc
EH		 1491}
1492
84f1b92f
EH		 1493/*
1494 * Returns the set of feature flags that are supported and migratable by
1495 * QEMU, for a given FeatureWord.
1496 */
ede146c2 1497static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
84f1b92f
EH		 1498{
1499 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 1500 uint64_t r = 0;
84f1b92f
EH		 1501 int i;
1502
ede146c2
PB		 1503 for (i = 0; i < 64; i++) {
1504 uint64_t f = 1ULL << i;
6fb2fff7
EH		 1505
1506 /* If the feature name is known, it is implicitly considered migratable,
1507 * unless it is explicitly set in unmigratable_flags */
1508 if ((wi->migratable_flags & f) ||
1509 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1510 r |= f;
84f1b92f 1511 }
84f1b92f
EH		 1512 }
1513 return r;
1514}
1515
bb44e0d1
JK		 1516void host_cpuid(uint32_t function, uint32_t count,
1517 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a 1518{
a1fd24af
AL		 1519 uint32_t vec[4];
1520
1521#ifdef __x86_64__
1522 asm volatile("cpuid"
1523 : "=a"(vec[0]), "=b"(vec[1]),
1524 "=c"(vec[2]), "=d"(vec[3])
1525 : "0"(function), "c"(count) : "cc");
c1f41226 1526#elif defined(__i386__)
a1fd24af
AL		 1527 asm volatile("pusha \n\t"
1528 "cpuid \n\t"
1529 "mov %%eax, 0(%2) \n\t"
1530 "mov %%ebx, 4(%2) \n\t"
1531 "mov %%ecx, 8(%2) \n\t"
1532 "mov %%edx, 12(%2) \n\t"
1533 "popa"
1534 : : "a"(function), "c"(count), "S"(vec)
1535 : "memory", "cc");
c1f41226
EH		 1536#else
1537 abort();
a1fd24af
AL		 1538#endif
1539
bdde476a 1540 if (eax)
a1fd24af 1541 *eax = vec[0];
bdde476a 1542 if (ebx)
a1fd24af 1543 *ebx = vec[1];
bdde476a 1544 if (ecx)
a1fd24af 1545 *ecx = vec[2];
bdde476a 1546 if (edx)
a1fd24af 1547 *edx = vec[3];
bdde476a 1548}
c6dc6f63 1549
20271d48
EH		 1550void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1551{
1552 uint32_t eax, ebx, ecx, edx;
1553
1554 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1555 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1556
1557 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1558 if (family) {
1559 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1560 }
1561 if (model) {
1562 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1563 }
1564 if (stepping) {
1565 *stepping = eax & 0x0F;
1566 }
1567}
1568
d940ee9b
EH		 1569/* CPU class name definitions: */
1570
d940ee9b
EH		 1571/* Return type name for a given CPU model name
1572 * Caller is responsible for freeing the returned string.
1573 */
1574static char *x86_cpu_type_name(const char *model_name)
1575{
1576 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1577}
1578
500050d1
AF		 1579static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1580{
88703ce2
EH		 1581 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1582 return object_class_by_name(typename);
500050d1
AF		 1583}
1584
104494ea
IM		 1585static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1586{
1587 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1588 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1589 return g_strndup(class_name,
1590 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1591}
1592
dcafd1ef
EH		 1593typedef struct PropValue {
1594 const char *prop, *value;
1595} PropValue;
1596
1597typedef struct X86CPUVersionDefinition {
1598 X86CPUVersion version;
53db89d9 1599 const char *alias;
c63938df 1600 const char *note;
dcafd1ef
EH		 1601 PropValue *props;
1602} X86CPUVersionDefinition;
1603
1604/* Base definition for a CPU model */
1605typedef struct X86CPUDefinition {
c6dc6f63
AP		 1606 const char *name;
1607 uint32_t level;
90e4b0c3 1608 uint32_t xlevel;
99b88a17
IM		 1609 /* vendor is zero-terminated, 12 character ASCII string */
1610 char vendor[CPUID_VENDOR_SZ + 1];
c6dc6f63
AP		 1611 int family;
1612 int model;
1613 int stepping;
0514ef2f 1614 FeatureWordArray features;
807e9869 1615 const char *model_id;
6aaeb054 1616 CPUCaches *cache_info;
dcafd1ef
EH		 1617 /*
1618 * Definitions for alternative versions of CPU model.
1619 * List is terminated by item with version == 0.
1620 * If NULL, version 1 will be registered automatically.
1621 */
1622 const X86CPUVersionDefinition *versions;
1623} X86CPUDefinition;
1624
1625/* Reference to a specific CPU model version */
1626struct X86CPUModel {
1627 /* Base CPU definition */
1628 X86CPUDefinition *cpudef;
1629 /* CPU model version */
1630 X86CPUVersion version;
c63938df 1631 const char *note;
0788a56b
EH		 1632 /*
1633 * If true, this is an alias CPU model.
1634 * This matters only for "-cpu help" and query-cpu-definitions
1635 */
1636 bool is_alias;
d940ee9b 1637};
c6dc6f63 1638
dcafd1ef
EH		 1639/* Get full model name for CPU version */
1640static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1641 X86CPUVersion version)
1642{
1643 assert(version > 0);
1644 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1645}
1646
1647static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1648{
1649 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1650 static const X86CPUVersionDefinition default_version_list[] = {
1651 { 1 },
1652 { /* end of list */ }
1653 };
1654
1655 return def->versions ?: default_version_list;
1656}
1657
fe52acd2 1658static CPUCaches epyc_cache_info = {
a9f27ea9 1659 .l1d_cache = &(CPUCacheInfo) {
5f00335a 1660 .type = DATA_CACHE,
fe52acd2
BM		 1661 .level = 1,
1662 .size = 32 * KiB,
1663 .line_size = 64,
1664 .associativity = 8,
1665 .partitions = 1,
1666 .sets = 64,
1667 .lines_per_tag = 1,
1668 .self_init = 1,
1669 .no_invd_sharing = true,
1670 },
a9f27ea9 1671 .l1i_cache = &(CPUCacheInfo) {
5f00335a 1672 .type = INSTRUCTION_CACHE,
fe52acd2
BM		 1673 .level = 1,
1674 .size = 64 * KiB,
1675 .line_size = 64,
1676 .associativity = 4,
1677 .partitions = 1,
1678 .sets = 256,
1679 .lines_per_tag = 1,
1680 .self_init = 1,
1681 .no_invd_sharing = true,
1682 },
a9f27ea9 1683 .l2_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1684 .type = UNIFIED_CACHE,
1685 .level = 2,
1686 .size = 512 * KiB,
1687 .line_size = 64,
1688 .associativity = 8,
1689 .partitions = 1,
1690 .sets = 1024,
1691 .lines_per_tag = 1,
1692 },
a9f27ea9 1693 .l3_cache = &(CPUCacheInfo) {
fe52acd2
BM		 1694 .type = UNIFIED_CACHE,
1695 .level = 3,
1696 .size = 8 * MiB,
1697 .line_size = 64,
1698 .associativity = 16,
1699 .partitions = 1,
1700 .sets = 8192,
1701 .lines_per_tag = 1,
1702 .self_init = true,
1703 .inclusive = true,
1704 .complex_indexing = true,
1705 },
1706};
1707
143c30d4
MB		 1708static CPUCaches epyc_rome_cache_info = {
1709 .l1d_cache = &(CPUCacheInfo) {
1710 .type = DATA_CACHE,
1711 .level = 1,
1712 .size = 32 * KiB,
1713 .line_size = 64,
1714 .associativity = 8,
1715 .partitions = 1,
1716 .sets = 64,
1717 .lines_per_tag = 1,
1718 .self_init = 1,
1719 .no_invd_sharing = true,
1720 },
1721 .l1i_cache = &(CPUCacheInfo) {
1722 .type = INSTRUCTION_CACHE,
1723 .level = 1,
1724 .size = 32 * KiB,
1725 .line_size = 64,
1726 .associativity = 8,
1727 .partitions = 1,
1728 .sets = 64,
1729 .lines_per_tag = 1,
1730 .self_init = 1,
1731 .no_invd_sharing = true,
1732 },
1733 .l2_cache = &(CPUCacheInfo) {
1734 .type = UNIFIED_CACHE,
1735 .level = 2,
1736 .size = 512 * KiB,
1737 .line_size = 64,
1738 .associativity = 8,
1739 .partitions = 1,
1740 .sets = 1024,
1741 .lines_per_tag = 1,
1742 },
1743 .l3_cache = &(CPUCacheInfo) {
1744 .type = UNIFIED_CACHE,
1745 .level = 3,
1746 .size = 16 * MiB,
1747 .line_size = 64,
1748 .associativity = 16,
1749 .partitions = 1,
1750 .sets = 16384,
1751 .lines_per_tag = 1,
1752 .self_init = true,
1753 .inclusive = true,
1754 .complex_indexing = true,
1755 },
1756};
1757
0723cc8a
PB		 1758/* The following VMX features are not supported by KVM and are left out in the
1759 * CPU definitions:
1760 *
1761 * Dual-monitor support (all processors)
1762 * Entry to SMM
1763 * Deactivate dual-monitor treatment
1764 * Number of CR3-target values
1765 * Shutdown activity state
1766 * Wait-for-SIPI activity state
1767 * PAUSE-loop exiting (Westmere and newer)
1768 * EPT-violation #VE (Broadwell and newer)
1769 * Inject event with insn length=0 (Skylake and newer)
1770 * Conceal non-root operation from PT
1771 * Conceal VM exits from PT
1772 * Conceal VM entries from PT
1773 * Enable ENCLS exiting
1774 * Mode-based execute control (XS/XU)
1775 s TSC scaling (Skylake Server and newer)
1776 * GPA translation for PT (IceLake and newer)
1777 * User wait and pause
1778 * ENCLV exiting
1779 * Load IA32_RTIT_CTL
1780 * Clear IA32_RTIT_CTL
1781 * Advanced VM-exit information for EPT violations
1782 * Sub-page write permissions
1783 * PT in VMX operation
1784 */
1785
9576de75 1786static X86CPUDefinition builtin_x86_defs[] = {
c6dc6f63
AP		 1787 {
1788 .name = "qemu64",
3046bb5d 1789 .level = 0xd,
99b88a17 1790 .vendor = CPUID_VENDOR_AMD,
c6dc6f63 1791 .family = 6,
f8e6a11a 1792 .model = 6,
c6dc6f63 1793 .stepping = 3,
0514ef2f 1794 .features[FEAT_1_EDX] =
27861ecc 1795 PPRO_FEATURES |
c6dc6f63 1796 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63 1797 CPUID_PSE36,
0514ef2f 1798 .features[FEAT_1_ECX] =
6aa91e4a 1799 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
0514ef2f 1800 .features[FEAT_8000_0001_EDX] =
c6dc6f63 1801 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1802 .features[FEAT_8000_0001_ECX] =
71195672 1803 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
c6dc6f63 1804 .xlevel = 0x8000000A,
9cf2cc3d 1805 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 1806 },
1807 {
1808 .name = "phenom",
1809 .level = 5,
99b88a17 1810 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 1811 .family = 16,
1812 .model = 2,
1813 .stepping = 3,
b9fc20bc 1814 /* Missing: CPUID_HT */
0514ef2f 1815 .features[FEAT_1_EDX] =
27861ecc 1816 PPRO_FEATURES |
c6dc6f63 1817 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc 1818 CPUID_PSE36 | CPUID_VME,
0514ef2f 1819 .features[FEAT_1_ECX] =
27861ecc 1820 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
c6dc6f63 1821 CPUID_EXT_POPCNT,
0514ef2f 1822 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1823 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1824 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 1825 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 1826 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1827 CPUID_EXT3_CR8LEG,
1828 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1829 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
0514ef2f 1830 .features[FEAT_8000_0001_ECX] =
27861ecc 1831 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
c6dc6f63 1832 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
b9fc20bc 1833 /* Missing: CPUID_SVM_LBRV */
0514ef2f 1834 .features[FEAT_SVM] =
b9fc20bc 1835 CPUID_SVM_NPT,
c6dc6f63
AP		 1836 .xlevel = 0x8000001A,
1837 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1838 },
1839 {
1840 .name = "core2duo",
1841 .level = 10,
99b88a17 1842 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1843 .family = 6,
1844 .model = 15,
1845 .stepping = 11,
b9fc20bc 1846 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1847 .features[FEAT_1_EDX] =
27861ecc 1848 PPRO_FEATURES |
c6dc6f63 1849 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
b9fc20bc
EH		 1850 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1851 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
e93abc14 1852 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1853 .features[FEAT_1_ECX] =
27861ecc 1854 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
e93abc14 1855 CPUID_EXT_CX16,
0514ef2f 1856 .features[FEAT_8000_0001_EDX] =
27861ecc 1857 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 1858 .features[FEAT_8000_0001_ECX] =
27861ecc 1859 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 1860 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1861 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1862 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1863 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1864 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1865 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1866 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1867 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1868 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1869 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1870 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1871 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1872 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1873 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1874 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1875 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1876 .features[FEAT_VMX_SECONDARY_CTLS] =
1877 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
c6dc6f63
AP		 1878 .xlevel = 0x80000008,
1879 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1880 },
1881 {
1882 .name = "kvm64",
3046bb5d 1883 .level = 0xd,
99b88a17 1884 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1885 .family = 15,
1886 .model = 6,
1887 .stepping = 1,
b3a4f0b1 1888 /* Missing: CPUID_HT */
0514ef2f 1889 .features[FEAT_1_EDX] =
b3a4f0b1 1890 PPRO_FEATURES | CPUID_VME |
c6dc6f63
AP		 1891 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1892 CPUID_PSE36,
1893 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
0514ef2f 1894 .features[FEAT_1_ECX] =
27861ecc 1895 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
c6dc6f63 1896 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
0514ef2f 1897 .features[FEAT_8000_0001_EDX] =
c6dc6f63
AP		 1898 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1899 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1900 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1901 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1902 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
0514ef2f 1903 .features[FEAT_8000_0001_ECX] =
27861ecc 1904 0,
0723cc8a
PB		 1905 /* VMX features from Cedar Mill/Prescott */
1906 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1907 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1908 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1909 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1910 VMX_PIN_BASED_NMI_EXITING,
1911 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1912 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1913 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1914 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1915 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1916 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1917 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1918 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
c6dc6f63
AP		 1919 .xlevel = 0x80000008,
1920 .model_id = "Common KVM processor"
1921 },
c6dc6f63
AP		 1922 {
1923 .name = "qemu32",
1924 .level = 4,
99b88a17 1925 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 1926 .family = 6,
f8e6a11a 1927 .model = 6,
c6dc6f63 1928 .stepping = 3,
0514ef2f 1929 .features[FEAT_1_EDX] =
27861ecc 1930 PPRO_FEATURES,
0514ef2f 1931 .features[FEAT_1_ECX] =
6aa91e4a 1932 CPUID_EXT_SSE3,
58012d66 1933 .xlevel = 0x80000004,
9cf2cc3d 1934 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63 1935 },
eafaf1e5
AP		 1936 {
1937 .name = "kvm32",
1938 .level = 5,
99b88a17 1939 .vendor = CPUID_VENDOR_INTEL,
eafaf1e5
AP		 1940 .family = 15,
1941 .model = 6,
1942 .stepping = 1,
0514ef2f 1943 .features[FEAT_1_EDX] =
b3a4f0b1 1944 PPRO_FEATURES | CPUID_VME |
eafaf1e5 1945 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
0514ef2f 1946 .features[FEAT_1_ECX] =
27861ecc 1947 CPUID_EXT_SSE3,
0514ef2f 1948 .features[FEAT_8000_0001_ECX] =
27861ecc 1949 0,
0723cc8a
PB		 1950 /* VMX features from Yonah */
1951 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1952 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1953 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1954 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1955 VMX_PIN_BASED_NMI_EXITING,
1956 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1957 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1958 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1959 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1960 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1961 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1962 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
eafaf1e5
AP		 1963 .xlevel = 0x80000008,
1964 .model_id = "Common 32-bit KVM processor"
1965 },
c6dc6f63
AP		 1966 {
1967 .name = "coreduo",
1968 .level = 10,
99b88a17 1969 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 1970 .family = 6,
1971 .model = 14,
1972 .stepping = 8,
b9fc20bc 1973 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 1974 .features[FEAT_1_EDX] =
27861ecc 1975 PPRO_FEATURES | CPUID_VME |
b9fc20bc
EH		 1976 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1977 CPUID_SS,
1978 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
e93abc14 1979 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
0514ef2f 1980 .features[FEAT_1_ECX] =
e93abc14 1981 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
0514ef2f 1982 .features[FEAT_8000_0001_EDX] =
27861ecc 1983 CPUID_EXT2_NX,
0723cc8a
PB		 1984 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1985 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1986 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1987 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1988 VMX_PIN_BASED_NMI_EXITING,
1989 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1990 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1991 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1992 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1993 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1994 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1995 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
c6dc6f63
AP		 1996 .xlevel = 0x80000008,
1997 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1998 },
1999 {
2000 .name = "486",
58012d66 2001 .level = 1,
99b88a17 2002 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63 2003 .family = 4,
b2a856d9 2004 .model = 8,
c6dc6f63 2005 .stepping = 0,
0514ef2f 2006 .features[FEAT_1_EDX] =
27861ecc 2007 I486_FEATURES,
c6dc6f63 2008 .xlevel = 0,
807e9869 2009 .model_id = "",
c6dc6f63
AP		 2010 },
2011 {
2012 .name = "pentium",
2013 .level = 1,
99b88a17 2014 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2015 .family = 5,
2016 .model = 4,
2017 .stepping = 3,
0514ef2f 2018 .features[FEAT_1_EDX] =
27861ecc 2019 PENTIUM_FEATURES,
c6dc6f63 2020 .xlevel = 0,
807e9869 2021 .model_id = "",
c6dc6f63
AP		 2022 },
2023 {
2024 .name = "pentium2",
2025 .level = 2,
99b88a17 2026 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2027 .family = 6,
2028 .model = 5,
2029 .stepping = 2,
0514ef2f 2030 .features[FEAT_1_EDX] =
27861ecc 2031 PENTIUM2_FEATURES,
c6dc6f63 2032 .xlevel = 0,
807e9869 2033 .model_id = "",
c6dc6f63
AP		 2034 },
2035 {
2036 .name = "pentium3",
3046bb5d 2037 .level = 3,
99b88a17 2038 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2039 .family = 6,
2040 .model = 7,
2041 .stepping = 3,
0514ef2f 2042 .features[FEAT_1_EDX] =
27861ecc 2043 PENTIUM3_FEATURES,
c6dc6f63 2044 .xlevel = 0,
807e9869 2045 .model_id = "",
c6dc6f63
AP		 2046 },
2047 {
2048 .name = "athlon",
2049 .level = 2,
99b88a17 2050 .vendor = CPUID_VENDOR_AMD,
c6dc6f63
AP		 2051 .family = 6,
2052 .model = 2,
2053 .stepping = 3,
0514ef2f 2054 .features[FEAT_1_EDX] =
27861ecc 2055 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
60032ac0 2056 CPUID_MCA,
0514ef2f 2057 .features[FEAT_8000_0001_EDX] =
60032ac0 2058 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 2059 .xlevel = 0x80000008,
9cf2cc3d 2060 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
c6dc6f63
AP		 2061 },
2062 {
2063 .name = "n270",
3046bb5d 2064 .level = 10,
99b88a17 2065 .vendor = CPUID_VENDOR_INTEL,
c6dc6f63
AP		 2066 .family = 6,
2067 .model = 28,
2068 .stepping = 2,
b9fc20bc 2069 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
0514ef2f 2070 .features[FEAT_1_EDX] =
27861ecc 2071 PPRO_FEATURES |
b9fc20bc
EH		 2072 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2073 CPUID_ACPI | CPUID_SS,
c6dc6f63 2074 /* Some CPUs got no CPUID_SEP */
b9fc20bc
EH		 2075 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2076 * CPUID_EXT_XTPR */
0514ef2f 2077 .features[FEAT_1_ECX] =
27861ecc 2078 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
4458c236 2079 CPUID_EXT_MOVBE,
0514ef2f 2080 .features[FEAT_8000_0001_EDX] =
60032ac0 2081 CPUID_EXT2_NX,
0514ef2f 2082 .features[FEAT_8000_0001_ECX] =
27861ecc 2083 CPUID_EXT3_LAHF_LM,
3046bb5d 2084 .xlevel = 0x80000008,
c6dc6f63
AP		 2085 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2086 },
3eca4642
EH		 2087 {
2088 .name = "Conroe",
3046bb5d 2089 .level = 10,
99b88a17 2090 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2091 .family = 6,
ffce9ebb 2092 .model = 15,
3eca4642 2093 .stepping = 3,
0514ef2f 2094 .features[FEAT_1_EDX] =
b3a4f0b1 2095 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2096 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2097 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2098 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2099 CPUID_DE | CPUID_FP87,
0514ef2f 2100 .features[FEAT_1_ECX] =
27861ecc 2101 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2102 .features[FEAT_8000_0001_EDX] =
27861ecc 2103 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2104 .features[FEAT_8000_0001_ECX] =
27861ecc 2105 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2106 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2107 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2108 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2109 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2110 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2111 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2112 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2113 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2114 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2115 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2116 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2117 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2118 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2119 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2120 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2121 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2122 .features[FEAT_VMX_SECONDARY_CTLS] =
2123 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
3046bb5d 2124 .xlevel = 0x80000008,
3eca4642
EH		 2125 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2126 },
2127 {
2128 .name = "Penryn",
3046bb5d 2129 .level = 10,
99b88a17 2130 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2131 .family = 6,
ffce9ebb 2132 .model = 23,
3eca4642 2133 .stepping = 3,
0514ef2f 2134 .features[FEAT_1_EDX] =
b3a4f0b1 2135 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2136 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2137 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2138 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2139 CPUID_DE | CPUID_FP87,
0514ef2f 2140 .features[FEAT_1_ECX] =
27861ecc 2141 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
b3fb3a20 2142 CPUID_EXT_SSE3,
0514ef2f 2143 .features[FEAT_8000_0001_EDX] =
27861ecc 2144 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 2145 .features[FEAT_8000_0001_ECX] =
27861ecc 2146 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2147 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2148 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2149 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2150 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2151 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2152 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2153 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2154 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2155 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2156 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2157 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2158 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2159 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2160 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2161 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2162 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2163 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2164 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2165 .features[FEAT_VMX_SECONDARY_CTLS] =
2166 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2167 VMX_SECONDARY_EXEC_WBINVD_EXITING,
3046bb5d 2168 .xlevel = 0x80000008,
3eca4642
EH		 2169 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2170 },
2171 {
2172 .name = "Nehalem",
3046bb5d 2173 .level = 11,
99b88a17 2174 .vendor = CPUID_VENDOR_INTEL,
3eca4642 2175 .family = 6,
ffce9ebb 2176 .model = 26,
3eca4642 2177 .stepping = 3,
0514ef2f 2178 .features[FEAT_1_EDX] =
b3a4f0b1 2179 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2180 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2181 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2182 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2183 CPUID_DE | CPUID_FP87,
0514ef2f 2184 .features[FEAT_1_ECX] =
27861ecc 2185 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
b3fb3a20 2186 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
0514ef2f 2187 .features[FEAT_8000_0001_EDX] =
27861ecc 2188 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2189 .features[FEAT_8000_0001_ECX] =
27861ecc 2190 CPUID_EXT3_LAHF_LM,
0723cc8a
PB		 2191 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2192 MSR_VMX_BASIC_TRUE_CTLS,
2193 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2194 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2195 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2196 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2197 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2198 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2199 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2200 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2201 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2202 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2203 .features[FEAT_VMX_EXIT_CTLS] =
2204 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2205 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2206 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2207 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2208 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2209 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2210 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2211 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2212 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2213 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2214 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2215 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2216 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2217 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2218 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2219 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2220 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2221 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2222 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2223 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2224 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2225 .features[FEAT_VMX_SECONDARY_CTLS] =
2226 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2227 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2228 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2229 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2230 VMX_SECONDARY_EXEC_ENABLE_VPID,
3046bb5d 2231 .xlevel = 0x80000008,
3eca4642 2232 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
d86a7088
EH		 2233 .versions = (X86CPUVersionDefinition[]) {
2234 { .version = 1 },
2235 {
2236 .version = 2,
53db89d9 2237 .alias = "Nehalem-IBRS",
d86a7088
EH		 2238 .props = (PropValue[]) {
2239 { "spec-ctrl", "on" },
2240 { "model-id",
2241 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2242 { /* end of list */ }
2243 }
2244 },
2245 { /* end of list */ }
2246 }
3eca4642
EH		 2247 },
2248 {
2249 .name = "Westmere",
2250 .level = 11,
99b88a17 2251 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2252 .family = 6,
2253 .model = 44,
2254 .stepping = 1,
0514ef2f 2255 .features[FEAT_1_EDX] =
b3a4f0b1 2256 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2257 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2258 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2259 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2260 CPUID_DE | CPUID_FP87,
0514ef2f 2261 .features[FEAT_1_ECX] =
27861ecc 2262 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
b3fb3a20
EH		 2263 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2264 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 2265 .features[FEAT_8000_0001_EDX] =
27861ecc 2266 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
0514ef2f 2267 .features[FEAT_8000_0001_ECX] =
27861ecc 2268 CPUID_EXT3_LAHF_LM,
28b8e4d0
JK		 2269 .features[FEAT_6_EAX] =
2270 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2271 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2272 MSR_VMX_BASIC_TRUE_CTLS,
2273 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2274 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2275 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2276 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2277 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2278 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2279 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2280 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2281 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2282 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2283 .features[FEAT_VMX_EXIT_CTLS] =
2284 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2285 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2286 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2287 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2288 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2289 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2290 MSR_VMX_MISC_STORE_LMA,
2291 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2292 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2293 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2294 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2295 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2296 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2297 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2298 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2299 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2300 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2301 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2302 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2303 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2304 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2305 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2306 .features[FEAT_VMX_SECONDARY_CTLS] =
2307 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2308 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2309 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2310 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2311 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2312 .xlevel = 0x80000008,
3eca4642 2313 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
d86a7088
EH		 2314 .versions = (X86CPUVersionDefinition[]) {
2315 { .version = 1 },
2316 {
2317 .version = 2,
53db89d9 2318 .alias = "Westmere-IBRS",
d86a7088
EH		 2319 .props = (PropValue[]) {
2320 { "spec-ctrl", "on" },
2321 { "model-id",
2322 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2323 { /* end of list */ }
2324 }
2325 },
2326 { /* end of list */ }
2327 }
3eca4642
EH		 2328 },
2329 {
2330 .name = "SandyBridge",
2331 .level = 0xd,
99b88a17 2332 .vendor = CPUID_VENDOR_INTEL,
3eca4642
EH		 2333 .family = 6,
2334 .model = 42,
2335 .stepping = 1,
0514ef2f 2336 .features[FEAT_1_EDX] =
b3a4f0b1 2337 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2338 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2339 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2340 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2341 CPUID_DE | CPUID_FP87,
0514ef2f 2342 .features[FEAT_1_ECX] =
27861ecc 2343 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2344 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2345 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2346 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2347 CPUID_EXT_SSE3,
0514ef2f 2348 .features[FEAT_8000_0001_EDX] =
27861ecc 2349 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2350 CPUID_EXT2_SYSCALL,
0514ef2f 2351 .features[FEAT_8000_0001_ECX] =
27861ecc 2352 CPUID_EXT3_LAHF_LM,
0bb0b2d2
PB		 2353 .features[FEAT_XSAVE] =
2354 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2355 .features[FEAT_6_EAX] =
2356 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2357 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2358 MSR_VMX_BASIC_TRUE_CTLS,
2359 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2360 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2361 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2362 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2363 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2364 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2365 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2366 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2367 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2368 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2369 .features[FEAT_VMX_EXIT_CTLS] =
2370 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2371 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2372 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2373 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2374 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2375 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2376 MSR_VMX_MISC_STORE_LMA,
2377 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2378 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2379 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2380 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2381 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2382 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2383 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2384 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2385 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2386 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2387 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2388 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2389 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2390 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2391 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2392 .features[FEAT_VMX_SECONDARY_CTLS] =
2393 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2394 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2395 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2396 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2397 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
3046bb5d 2398 .xlevel = 0x80000008,
3eca4642 2399 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
d86a7088
EH		 2400 .versions = (X86CPUVersionDefinition[]) {
2401 { .version = 1 },
2402 {
2403 .version = 2,
53db89d9 2404 .alias = "SandyBridge-IBRS",
d86a7088
EH		 2405 .props = (PropValue[]) {
2406 { "spec-ctrl", "on" },
2407 { "model-id",
2408 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2409 { /* end of list */ }
2410 }
2411 },
2412 { /* end of list */ }
2413 }
3eca4642 2414 },
2f9ac42a
PB		 2415 {
2416 .name = "IvyBridge",
2417 .level = 0xd,
2418 .vendor = CPUID_VENDOR_INTEL,
2419 .family = 6,
2420 .model = 58,
2421 .stepping = 9,
2422 .features[FEAT_1_EDX] =
2423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2427 CPUID_DE | CPUID_FP87,
2428 .features[FEAT_1_ECX] =
2429 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2430 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2431 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2432 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2433 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2434 .features[FEAT_7_0_EBX] =
2435 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2436 CPUID_7_0_EBX_ERMS,
2437 .features[FEAT_8000_0001_EDX] =
2438 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2439 CPUID_EXT2_SYSCALL,
2440 .features[FEAT_8000_0001_ECX] =
2441 CPUID_EXT3_LAHF_LM,
2442 .features[FEAT_XSAVE] =
2443 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2444 .features[FEAT_6_EAX] =
2445 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2446 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2447 MSR_VMX_BASIC_TRUE_CTLS,
2448 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2449 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2450 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2451 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2452 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2453 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2454 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2455 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2456 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2457 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2458 .features[FEAT_VMX_EXIT_CTLS] =
2459 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2460 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2461 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2462 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2463 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2464 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2465 MSR_VMX_MISC_STORE_LMA,
2466 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2467 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2468 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2469 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2470 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2471 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2472 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2473 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2474 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2475 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2476 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2477 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2478 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2479 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2480 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2481 .features[FEAT_VMX_SECONDARY_CTLS] =
2482 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2483 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2484 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2485 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2486 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2487 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2488 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2489 VMX_SECONDARY_EXEC_RDRAND_EXITING,
3046bb5d 2490 .xlevel = 0x80000008,
2f9ac42a 2491 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
d86a7088
EH		 2492 .versions = (X86CPUVersionDefinition[]) {
2493 { .version = 1 },
2494 {
2495 .version = 2,
53db89d9 2496 .alias = "IvyBridge-IBRS",
d86a7088
EH		 2497 .props = (PropValue[]) {
2498 { "spec-ctrl", "on" },
2499 { "model-id",
2500 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2501 { /* end of list */ }
2502 }
2503 },
2504 { /* end of list */ }
2505 }
2f9ac42a 2506 },
ac96c413 2507 {
37507094
EH		 2508 .name = "Haswell",
2509 .level = 0xd,
99b88a17 2510 .vendor = CPUID_VENDOR_INTEL,
37507094
EH		 2511 .family = 6,
2512 .model = 60,
ec56a4a7 2513 .stepping = 4,
0514ef2f 2514 .features[FEAT_1_EDX] =
b3a4f0b1 2515 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 2516 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2517 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2518 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2519 CPUID_DE | CPUID_FP87,
0514ef2f 2520 .features[FEAT_1_ECX] =
27861ecc 2521 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 2522 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2523 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2524 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2525 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2526 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
0514ef2f 2527 .features[FEAT_8000_0001_EDX] =
27861ecc 2528 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
b3fb3a20 2529 CPUID_EXT2_SYSCALL,
0514ef2f 2530 .features[FEAT_8000_0001_ECX] =
becb6667 2531 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
0514ef2f 2532 .features[FEAT_7_0_EBX] =
27861ecc 2533 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598
EH		 2534 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2535 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2536 CPUID_7_0_EBX_RTM,
0bb0b2d2
PB		 2537 .features[FEAT_XSAVE] =
2538 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2539 .features[FEAT_6_EAX] =
2540 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2541 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2542 MSR_VMX_BASIC_TRUE_CTLS,
2543 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2544 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2545 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2546 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2547 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2548 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2549 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2550 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2551 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2552 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2553 .features[FEAT_VMX_EXIT_CTLS] =
2554 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2555 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2556 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2557 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2558 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2560 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2561 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2562 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2563 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2564 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2565 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2566 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2567 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2568 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2569 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2570 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2571 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2572 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2573 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2574 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2575 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2576 .features[FEAT_VMX_SECONDARY_CTLS] =
2577 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2578 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2579 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2580 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2581 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2582 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2583 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2584 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2585 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2586 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2587 .xlevel = 0x80000008,
37507094 2588 .model_id = "Intel Core Processor (Haswell)",
d86a7088
EH		 2589 .versions = (X86CPUVersionDefinition[]) {
2590 { .version = 1 },
2591 {
2592 .version = 2,
53db89d9 2593 .alias = "Haswell-noTSX",
d86a7088
EH		 2594 .props = (PropValue[]) {
2595 { "hle", "off" },
2596 { "rtm", "off" },
2597 { "stepping", "1" },
2598 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2599 { /* end of list */ }
2600 },
2601 },
2602 {
2603 .version = 3,
53db89d9 2604 .alias = "Haswell-IBRS",
d86a7088
EH		 2605 .props = (PropValue[]) {
2606 /* Restore TSX features removed by -v2 above */
2607 { "hle", "on" },
2608 { "rtm", "on" },
2609 /*
2610 * Haswell and Haswell-IBRS had stepping=4 in
2611 * QEMU 4.0 and older
2612 */
2613 { "stepping", "4" },
2614 { "spec-ctrl", "on" },
2615 { "model-id",
2616 "Intel Core Processor (Haswell, IBRS)" },
2617 { /* end of list */ }
2618 }
2619 },
2620 {
2621 .version = 4,
53db89d9 2622 .alias = "Haswell-noTSX-IBRS",
d86a7088
EH		 2623 .props = (PropValue[]) {
2624 { "hle", "off" },
2625 { "rtm", "off" },
2626 /* spec-ctrl was already enabled by -v3 above */
2627 { "stepping", "1" },
2628 { "model-id",
2629 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2630 { /* end of list */ }
2631 }
2632 },
2633 { /* end of list */ }
2634 }
37507094 2635 },
ece01354
EH		 2636 {
2637 .name = "Broadwell",
2638 .level = 0xd,
2639 .vendor = CPUID_VENDOR_INTEL,
2640 .family = 6,
2641 .model = 61,
2642 .stepping = 2,
2643 .features[FEAT_1_EDX] =
b3a4f0b1 2644 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
ece01354
EH		 2645 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2646 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2647 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2648 CPUID_DE | CPUID_FP87,
2649 .features[FEAT_1_ECX] =
2650 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2651 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2652 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2653 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2654 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
78a611f1 2655 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
ece01354
EH		 2656 .features[FEAT_8000_0001_EDX] =
2657 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2658 CPUID_EXT2_SYSCALL,
2659 .features[FEAT_8000_0001_ECX] =
becb6667 2660 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
ece01354
EH		 2661 .features[FEAT_7_0_EBX] =
2662 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1ee91598 2663 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
ece01354 2664 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1ee91598 2665 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ece01354 2666 CPUID_7_0_EBX_SMAP,
0bb0b2d2
PB		 2667 .features[FEAT_XSAVE] =
2668 CPUID_XSAVE_XSAVEOPT,
28b8e4d0
JK		 2669 .features[FEAT_6_EAX] =
2670 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2671 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2672 MSR_VMX_BASIC_TRUE_CTLS,
2673 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2674 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2675 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2676 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2677 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2678 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2679 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2680 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2681 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2682 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2683 .features[FEAT_VMX_EXIT_CTLS] =
2684 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2685 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2686 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2687 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2688 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2689 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2690 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2691 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2692 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2693 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2694 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2695 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2696 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2697 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2698 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2699 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2700 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2701 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2702 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2703 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2704 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2705 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2706 .features[FEAT_VMX_SECONDARY_CTLS] =
2707 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2708 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2709 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2710 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2711 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2712 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2713 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2714 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2715 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2716 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2717 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3046bb5d 2718 .xlevel = 0x80000008,
ece01354 2719 .model_id = "Intel Core Processor (Broadwell)",
d86a7088
EH		 2720 .versions = (X86CPUVersionDefinition[]) {
2721 { .version = 1 },
2722 {
2723 .version = 2,
53db89d9 2724 .alias = "Broadwell-noTSX",
d86a7088
EH		 2725 .props = (PropValue[]) {
2726 { "hle", "off" },
2727 { "rtm", "off" },
2728 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2729 { /* end of list */ }
2730 },
2731 },
2732 {
2733 .version = 3,
53db89d9 2734 .alias = "Broadwell-IBRS",
d86a7088
EH		 2735 .props = (PropValue[]) {
2736 /* Restore TSX features removed by -v2 above */
2737 { "hle", "on" },
2738 { "rtm", "on" },
2739 { "spec-ctrl", "on" },
2740 { "model-id",
2741 "Intel Core Processor (Broadwell, IBRS)" },
2742 { /* end of list */ }
2743 }
2744 },
2745 {
2746 .version = 4,
53db89d9 2747 .alias = "Broadwell-noTSX-IBRS",
d86a7088
EH		 2748 .props = (PropValue[]) {
2749 { "hle", "off" },
2750 { "rtm", "off" },
2751 /* spec-ctrl was already enabled by -v3 above */
2752 { "model-id",
2753 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2754 { /* end of list */ }
2755 }
2756 },
2757 { /* end of list */ }
2758 }
ece01354 2759 },
f6f949e9
EH		 2760 {
2761 .name = "Skylake-Client",
2762 .level = 0xd,
2763 .vendor = CPUID_VENDOR_INTEL,
2764 .family = 6,
2765 .model = 94,
2766 .stepping = 3,
2767 .features[FEAT_1_EDX] =
2768 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2769 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2770 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2771 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2772 CPUID_DE | CPUID_FP87,
2773 .features[FEAT_1_ECX] =
2774 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2775 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2776 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2777 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2778 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2779 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2780 .features[FEAT_8000_0001_EDX] =
2781 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2782 CPUID_EXT2_SYSCALL,
2783 .features[FEAT_8000_0001_ECX] =
2784 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2785 .features[FEAT_7_0_EBX] =
2786 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2787 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2788 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2789 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2790 CPUID_7_0_EBX_SMAP,
f6f949e9 2791 /* Missing: XSAVES (not supported by some Linux versions,
cf70879f 2792 * including v4.1 to v4.12).
f6f949e9
EH		 2793 * KVM doesn't yet expose any XSAVES state save component,
2794 * and the only one defined in Skylake (processor tracing)
2795 * probably will block migration anyway.
2796 */
2797 .features[FEAT_XSAVE] =
2798 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2799 CPUID_XSAVE_XGETBV1,
2800 .features[FEAT_6_EAX] =
2801 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2802 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2803 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2804 MSR_VMX_BASIC_TRUE_CTLS,
2805 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2806 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2807 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2808 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2809 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2810 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2811 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2812 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2813 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2814 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2815 .features[FEAT_VMX_EXIT_CTLS] =
2816 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2817 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2818 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2819 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2820 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2821 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2822 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2823 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2824 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2825 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2826 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2827 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2828 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2829 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2830 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2831 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2832 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2833 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2834 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2835 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2836 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2837 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2838 .features[FEAT_VMX_SECONDARY_CTLS] =
2839 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2840 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2841 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2842 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2843 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2844 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2845 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2846 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
f6f949e9
EH		 2847 .xlevel = 0x80000008,
2848 .model_id = "Intel Core Processor (Skylake)",
d86a7088
EH		 2849 .versions = (X86CPUVersionDefinition[]) {
2850 { .version = 1 },
2851 {
2852 .version = 2,
53db89d9 2853 .alias = "Skylake-Client-IBRS",
d86a7088
EH		 2854 .props = (PropValue[]) {
2855 { "spec-ctrl", "on" },
2856 { "model-id",
2857 "Intel Core Processor (Skylake, IBRS)" },
2858 { /* end of list */ }
2859 }
2860 },
9ab2237f
EH		 2861 {
2862 .version = 3,
02fa60d1 2863 .alias = "Skylake-Client-noTSX-IBRS",
9ab2237f
EH		 2864 .props = (PropValue[]) {
2865 { "hle", "off" },
2866 { "rtm", "off" },
673b0add
KC		 2867 { "model-id",
2868 "Intel Core Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2869 { /* end of list */ }
2870 }
2871 },
d86a7088
EH		 2872 { /* end of list */ }
2873 }
f6f949e9 2874 },
53f9a6f4
BF		 2875 {
2876 .name = "Skylake-Server",
2877 .level = 0xd,
2878 .vendor = CPUID_VENDOR_INTEL,
2879 .family = 6,
2880 .model = 85,
2881 .stepping = 4,
2882 .features[FEAT_1_EDX] =
2883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2887 CPUID_DE | CPUID_FP87,
2888 .features[FEAT_1_ECX] =
2889 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2890 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2891 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2892 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2893 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2894 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2895 .features[FEAT_8000_0001_EDX] =
2896 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2897 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2898 .features[FEAT_8000_0001_ECX] =
2899 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2900 .features[FEAT_7_0_EBX] =
2901 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2902 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2903 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2904 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 2905 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
53f9a6f4
BF		 2906 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2907 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
c68bcb3a 2908 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
09b9ee64
TX		 2909 .features[FEAT_7_0_ECX] =
2910 CPUID_7_0_ECX_PKU,
53f9a6f4
BF		 2911 /* Missing: XSAVES (not supported by some Linux versions,
2912 * including v4.1 to v4.12).
2913 * KVM doesn't yet expose any XSAVES state save component,
2914 * and the only one defined in Skylake (processor tracing)
2915 * probably will block migration anyway.
2916 */
2917 .features[FEAT_XSAVE] =
2918 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2919 CPUID_XSAVE_XGETBV1,
2920 .features[FEAT_6_EAX] =
2921 CPUID_6_EAX_ARAT,
0723cc8a
PB		 2922 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2923 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2924 MSR_VMX_BASIC_TRUE_CTLS,
2925 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2926 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2927 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2928 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2929 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2930 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2931 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2932 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2933 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2934 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2935 .features[FEAT_VMX_EXIT_CTLS] =
2936 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2937 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2938 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2939 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2940 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2941 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2942 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2943 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2944 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2945 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2946 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2947 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2948 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2949 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2950 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2951 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2952 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2953 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2954 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2955 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2956 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2957 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2958 .features[FEAT_VMX_SECONDARY_CTLS] =
2959 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2960 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2961 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2962 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2963 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2964 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2965 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2966 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 2967 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2968 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
53f9a6f4
BF		 2969 .xlevel = 0x80000008,
2970 .model_id = "Intel Xeon Processor (Skylake)",
d86a7088
EH		 2971 .versions = (X86CPUVersionDefinition[]) {
2972 { .version = 1 },
2973 {
2974 .version = 2,
53db89d9 2975 .alias = "Skylake-Server-IBRS",
d86a7088
EH		 2976 .props = (PropValue[]) {
2977 /* clflushopt was not added to Skylake-Server-IBRS */
2978 /* TODO: add -v3 including clflushopt */
2979 { "clflushopt", "off" },
2980 { "spec-ctrl", "on" },
2981 { "model-id",
2982 "Intel Xeon Processor (Skylake, IBRS)" },
2983 { /* end of list */ }
2984 }
2985 },
9ab2237f
EH		 2986 {
2987 .version = 3,
02fa60d1 2988 .alias = "Skylake-Server-noTSX-IBRS",
9ab2237f
EH		 2989 .props = (PropValue[]) {
2990 { "hle", "off" },
2991 { "rtm", "off" },
673b0add
KC		 2992 { "model-id",
2993 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
9ab2237f
EH		 2994 { /* end of list */ }
2995 }
2996 },
d86a7088
EH		 2997 { /* end of list */ }
2998 }
53f9a6f4 2999 },
c7a88b52
TX		 3000 {
3001 .name = "Cascadelake-Server",
3002 .level = 0xd,
3003 .vendor = CPUID_VENDOR_INTEL,
3004 .family = 6,
3005 .model = 85,
b0a19803 3006 .stepping = 6,
c7a88b52
TX		 3007 .features[FEAT_1_EDX] =
3008 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3009 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3010 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3011 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3012 CPUID_DE | CPUID_FP87,
3013 .features[FEAT_1_ECX] =
3014 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3015 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3016 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3017 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3018 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3019 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3020 .features[FEAT_8000_0001_EDX] =
3021 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3022 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3023 .features[FEAT_8000_0001_ECX] =
3024 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3025 .features[FEAT_7_0_EBX] =
3026 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3027 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3028 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3029 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3030 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
c7a88b52
TX		 3031 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3032 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3033 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
c7a88b52 3034 .features[FEAT_7_0_ECX] =
bb4928c7 3035 CPUID_7_0_ECX_PKU |
c7a88b52
TX		 3036 CPUID_7_0_ECX_AVX512VNNI,
3037 .features[FEAT_7_0_EDX] =
3038 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3039 /* Missing: XSAVES (not supported by some Linux versions,
3040 * including v4.1 to v4.12).
3041 * KVM doesn't yet expose any XSAVES state save component,
3042 * and the only one defined in Skylake (processor tracing)
3043 * probably will block migration anyway.
3044 */
3045 .features[FEAT_XSAVE] =
3046 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3047 CPUID_XSAVE_XGETBV1,
3048 .features[FEAT_6_EAX] =
3049 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3050 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3051 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3052 MSR_VMX_BASIC_TRUE_CTLS,
3053 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3054 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3055 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3056 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3057 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3058 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3059 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3060 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3061 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3063 .features[FEAT_VMX_EXIT_CTLS] =
3064 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3065 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3066 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3067 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3068 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3069 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3070 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3071 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3072 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3073 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3074 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3075 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3076 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3077 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3078 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3079 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3080 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3081 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3082 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3083 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3084 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3085 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3086 .features[FEAT_VMX_SECONDARY_CTLS] =
3087 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3088 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3089 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3090 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3091 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3092 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3093 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3094 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
c6f3215f
PB		 3095 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3096 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
c7a88b52
TX		 3097 .xlevel = 0x80000008,
3098 .model_id = "Intel Xeon Processor (Cascadelake)",
fd63c6d1
EH		 3099 .versions = (X86CPUVersionDefinition[]) {
3100 { .version = 1 },
3101 { .version = 2,
3102 .props = (PropValue[]) {
3103 { "arch-capabilities", "on" },
3104 { "rdctl-no", "on" },
3105 { "ibrs-all", "on" },
3106 { "skip-l1dfl-vmentry", "on" },
3107 { "mds-no", "on" },
3108 { /* end of list */ }
3109 },
3110 },
9ab2237f 3111 { .version = 3,
02fa60d1 3112 .alias = "Cascadelake-Server-noTSX",
9ab2237f
EH		 3113 .props = (PropValue[]) {
3114 { "hle", "off" },
3115 { "rtm", "off" },
3116 { /* end of list */ }
3117 },
3118 },
fd63c6d1
EH		 3119 { /* end of list */ }
3120 }
c7a88b52 3121 },
22a866b6
CZ		 3122 {
3123 .name = "Cooperlake",
3124 .level = 0xd,
3125 .vendor = CPUID_VENDOR_INTEL,
3126 .family = 6,
3127 .model = 85,
3128 .stepping = 10,
3129 .features[FEAT_1_EDX] =
3130 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3131 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3132 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3133 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3134 CPUID_DE | CPUID_FP87,
3135 .features[FEAT_1_ECX] =
3136 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3137 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3138 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3139 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3140 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3141 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3142 .features[FEAT_8000_0001_EDX] =
3143 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3144 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3145 .features[FEAT_8000_0001_ECX] =
3146 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3147 .features[FEAT_7_0_EBX] =
3148 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3149 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3150 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3151 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3152 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3153 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3154 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3155 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3156 .features[FEAT_7_0_ECX] =
3157 CPUID_7_0_ECX_PKU |
3158 CPUID_7_0_ECX_AVX512VNNI,
3159 .features[FEAT_7_0_EDX] =
3160 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3161 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3162 .features[FEAT_ARCH_CAPABILITIES] =
3163 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
2dea9d9c
XL		 3164 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3165 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
22a866b6
CZ		 3166 .features[FEAT_7_1_EAX] =
3167 CPUID_7_1_EAX_AVX512_BF16,
3168 /*
3169 * Missing: XSAVES (not supported by some Linux versions,
3170 * including v4.1 to v4.12).
3171 * KVM doesn't yet expose any XSAVES state save component,
3172 * and the only one defined in Skylake (processor tracing)
3173 * probably will block migration anyway.
3174 */
3175 .features[FEAT_XSAVE] =
3176 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3177 CPUID_XSAVE_XGETBV1,
3178 .features[FEAT_6_EAX] =
3179 CPUID_6_EAX_ARAT,
2dea9d9c
XL		 3180 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3181 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3182 MSR_VMX_BASIC_TRUE_CTLS,
3183 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3184 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3185 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3186 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3187 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3188 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3189 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3190 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3191 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3192 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3193 .features[FEAT_VMX_EXIT_CTLS] =
3194 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3195 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3196 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3197 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3198 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3199 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3200 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3201 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3202 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3203 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3204 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3205 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3206 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3207 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3208 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3209 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3210 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3211 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3212 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3213 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3214 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3215 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3216 .features[FEAT_VMX_SECONDARY_CTLS] =
3217 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3218 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3219 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3220 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3221 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3222 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3223 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3224 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3225 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3226 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3227 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
22a866b6
CZ		 3228 .xlevel = 0x80000008,
3229 .model_id = "Intel Xeon Processor (Cooperlake)",
3230 },
8a11c62d
RH		 3231 {
3232 .name = "Icelake-Client",
3233 .level = 0xd,
3234 .vendor = CPUID_VENDOR_INTEL,
3235 .family = 6,
3236 .model = 126,
3237 .stepping = 0,
3238 .features[FEAT_1_EDX] =
3239 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3240 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3241 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3242 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3243 CPUID_DE | CPUID_FP87,
3244 .features[FEAT_1_ECX] =
3245 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3246 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3247 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3248 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3249 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3250 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3251 .features[FEAT_8000_0001_EDX] =
3252 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3253 CPUID_EXT2_SYSCALL,
3254 .features[FEAT_8000_0001_ECX] =
3255 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3256 .features[FEAT_8000_0008_EBX] =
3257 CPUID_8000_0008_EBX_WBNOINVD,
3258 .features[FEAT_7_0_EBX] =
3259 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3260 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3261 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3262 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
4c257911 3263 CPUID_7_0_EBX_SMAP,
8a11c62d 3264 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3265 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3266 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3267 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3268 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3269 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3270 .features[FEAT_7_0_EDX] =
3271 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3272 /* Missing: XSAVES (not supported by some Linux versions,
3273 * including v4.1 to v4.12).
3274 * KVM doesn't yet expose any XSAVES state save component,
3275 * and the only one defined in Skylake (processor tracing)
3276 * probably will block migration anyway.
3277 */
3278 .features[FEAT_XSAVE] =
3279 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3280 CPUID_XSAVE_XGETBV1,
3281 .features[FEAT_6_EAX] =
3282 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3283 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3284 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3285 MSR_VMX_BASIC_TRUE_CTLS,
3286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3289 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3291 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3293 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3296 .features[FEAT_VMX_EXIT_CTLS] =
3297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3299 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3300 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3302 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3303 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3304 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3305 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3306 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3307 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3308 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3309 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3310 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3311 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3312 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3313 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3314 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3315 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3316 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3317 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3318 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3319 .features[FEAT_VMX_SECONDARY_CTLS] =
3320 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3321 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3322 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3323 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3324 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3325 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3326 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3327 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8a11c62d
RH		 3328 .xlevel = 0x80000008,
3329 .model_id = "Intel Core Processor (Icelake)",
9ab2237f
EH		 3330 .versions = (X86CPUVersionDefinition[]) {
3331 { .version = 1 },
3332 {
3333 .version = 2,
02fa60d1 3334 .alias = "Icelake-Client-noTSX",
9ab2237f
EH		 3335 .props = (PropValue[]) {
3336 { "hle", "off" },
3337 { "rtm", "off" },
3338 { /* end of list */ }
3339 },
3340 },
3341 { /* end of list */ }
3342 }
8a11c62d
RH		 3343 },
3344 {
3345 .name = "Icelake-Server",
3346 .level = 0xd,
3347 .vendor = CPUID_VENDOR_INTEL,
3348 .family = 6,
3349 .model = 134,
3350 .stepping = 0,
3351 .features[FEAT_1_EDX] =
3352 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3353 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3354 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3355 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3356 CPUID_DE | CPUID_FP87,
3357 .features[FEAT_1_ECX] =
3358 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3359 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3360 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3361 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3362 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3363 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3364 .features[FEAT_8000_0001_EDX] =
3365 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3366 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3367 .features[FEAT_8000_0001_ECX] =
3368 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3369 .features[FEAT_8000_0008_EBX] =
3370 CPUID_8000_0008_EBX_WBNOINVD,
3371 .features[FEAT_7_0_EBX] =
3372 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3373 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3374 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3375 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
ecb85fe4 3376 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
8a11c62d
RH		 3377 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3378 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
4c257911 3379 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
8a11c62d 3380 .features[FEAT_7_0_ECX] =
e7694a5e
TX		 3381 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3382 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
8a11c62d
RH		 3383 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3384 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3385 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3386 .features[FEAT_7_0_EDX] =
76e5a4d5 3387 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
8a11c62d
RH		 3388 /* Missing: XSAVES (not supported by some Linux versions,
3389 * including v4.1 to v4.12).
3390 * KVM doesn't yet expose any XSAVES state save component,
3391 * and the only one defined in Skylake (processor tracing)
3392 * probably will block migration anyway.
3393 */
3394 .features[FEAT_XSAVE] =
3395 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3396 CPUID_XSAVE_XGETBV1,
3397 .features[FEAT_6_EAX] =
3398 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3399 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3400 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3401 MSR_VMX_BASIC_TRUE_CTLS,
3402 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3403 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3404 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3405 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3406 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3407 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3408 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3409 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3410 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3411 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3412 .features[FEAT_VMX_EXIT_CTLS] =
3413 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3414 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3415 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3416 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3417 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3418 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3419 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3420 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3421 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3422 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3423 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3424 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3425 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3426 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3427 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3428 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3429 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3430 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3431 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3432 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3433 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3434 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3435 .features[FEAT_VMX_SECONDARY_CTLS] =
3436 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3437 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3438 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3439 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3440 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3441 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3442 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3443 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3444 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
8a11c62d
RH		 3445 .xlevel = 0x80000008,
3446 .model_id = "Intel Xeon Processor (Icelake)",
9ab2237f
EH		 3447 .versions = (X86CPUVersionDefinition[]) {
3448 { .version = 1 },
3449 {
3450 .version = 2,
02fa60d1 3451 .alias = "Icelake-Server-noTSX",
9ab2237f
EH		 3452 .props = (PropValue[]) {
3453 { "hle", "off" },
3454 { "rtm", "off" },
3455 { /* end of list */ }
3456 },
3457 },
3458 { /* end of list */ }
3459 }
8a11c62d 3460 },
8b44d860
TX		 3461 {
3462 .name = "Denverton",
3463 .level = 21,
3464 .vendor = CPUID_VENDOR_INTEL,
3465 .family = 6,
3466 .model = 95,
3467 .stepping = 1,
3468 .features[FEAT_1_EDX] =
3469 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3470 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3471 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3472 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3473 CPUID_SSE | CPUID_SSE2,
3474 .features[FEAT_1_ECX] =
3475 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3476 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3477 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3478 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3479 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3480 .features[FEAT_8000_0001_EDX] =
3481 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3482 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3483 .features[FEAT_8000_0001_ECX] =
3484 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3485 .features[FEAT_7_0_EBX] =
3486 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3487 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3488 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3489 .features[FEAT_7_0_EDX] =
3490 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3491 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3492 /*
3493 * Missing: XSAVES (not supported by some Linux versions,
3494 * including v4.1 to v4.12).
3495 * KVM doesn't yet expose any XSAVES state save component,
3496 * and the only one defined in Skylake (processor tracing)
3497 * probably will block migration anyway.
3498 */
3499 .features[FEAT_XSAVE] =
3500 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3501 .features[FEAT_6_EAX] =
3502 CPUID_6_EAX_ARAT,
3503 .features[FEAT_ARCH_CAPABILITIES] =
3504 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
0723cc8a
PB		 3505 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3506 MSR_VMX_BASIC_TRUE_CTLS,
3507 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3508 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3509 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3510 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3511 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3512 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3513 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3514 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3515 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3516 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3517 .features[FEAT_VMX_EXIT_CTLS] =
3518 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3519 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3520 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3521 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3522 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3523 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3524 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3525 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3526 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3527 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3528 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3529 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3530 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3531 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3532 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3533 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3534 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3535 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3536 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3537 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3538 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3539 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3540 .features[FEAT_VMX_SECONDARY_CTLS] =
3541 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3542 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3543 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3544 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3545 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3546 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3547 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3548 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3549 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3550 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3551 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
8b44d860
TX		 3552 .xlevel = 0x80000008,
3553 .model_id = "Intel Atom Processor (Denverton)",
ab0c942c
TX		 3554 .versions = (X86CPUVersionDefinition[]) {
3555 { .version = 1 },
3556 {
3557 .version = 2,
3558 .props = (PropValue[]) {
3559 { "monitor", "off" },
3560 { "mpx", "off" },
3561 { /* end of list */ },
3562 },
3563 },
3564 { /* end of list */ },
3565 },
8b44d860 3566 },
0b18874b 3567 {
ff656fcd 3568 .name = "Snowridge",
0b18874b
PL		 3569 .level = 27,
3570 .vendor = CPUID_VENDOR_INTEL,
3571 .family = 6,
3572 .model = 134,
3573 .stepping = 1,
3574 .features[FEAT_1_EDX] =
3575 /* missing: CPUID_PN CPUID_IA64 */
3576 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3577 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3578 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3579 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3580 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3581 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3582 CPUID_MMX |
3583 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3584 .features[FEAT_1_ECX] =
3585 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
0b18874b
PL		 3586 CPUID_EXT_SSSE3 |
3587 CPUID_EXT_CX16 |
3588 CPUID_EXT_SSE41 |
3589 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3590 CPUID_EXT_POPCNT |
3591 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3592 CPUID_EXT_RDRAND,
3593 .features[FEAT_8000_0001_EDX] =
3594 CPUID_EXT2_SYSCALL |
3595 CPUID_EXT2_NX |
3596 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3597 CPUID_EXT2_LM,
3598 .features[FEAT_8000_0001_ECX] =
3599 CPUID_EXT3_LAHF_LM |
3600 CPUID_EXT3_3DNOWPREFETCH,
3601 .features[FEAT_7_0_EBX] =
3602 CPUID_7_0_EBX_FSGSBASE |
3603 CPUID_7_0_EBX_SMEP |
3604 CPUID_7_0_EBX_ERMS |
3605 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3606 CPUID_7_0_EBX_RDSEED |
3607 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3608 CPUID_7_0_EBX_CLWB |
3609 CPUID_7_0_EBX_SHA_NI,
3610 .features[FEAT_7_0_ECX] =
3611 CPUID_7_0_ECX_UMIP |
3612 /* missing bit 5 */
3613 CPUID_7_0_ECX_GFNI |
3614 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3615 CPUID_7_0_ECX_MOVDIR64B,
3616 .features[FEAT_7_0_EDX] =
3617 CPUID_7_0_EDX_SPEC_CTRL |
3618 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3619 CPUID_7_0_EDX_CORE_CAPABILITY,
3620 .features[FEAT_CORE_CAPABILITY] =
3621 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3622 /*
3623 * Missing: XSAVES (not supported by some Linux versions,
3624 * including v4.1 to v4.12).
3625 * KVM doesn't yet expose any XSAVES state save component,
3626 * and the only one defined in Skylake (processor tracing)
3627 * probably will block migration anyway.
3628 */
3629 .features[FEAT_XSAVE] =
3630 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3631 CPUID_XSAVE_XGETBV1,
3632 .features[FEAT_6_EAX] =
3633 CPUID_6_EAX_ARAT,
0723cc8a
PB		 3634 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3635 MSR_VMX_BASIC_TRUE_CTLS,
3636 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3637 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3638 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3639 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3640 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3641 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3642 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3643 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3644 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3645 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3646 .features[FEAT_VMX_EXIT_CTLS] =
3647 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3648 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3649 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3650 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3651 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3652 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3653 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3654 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3655 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3656 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3657 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3658 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3659 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3660 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3661 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3662 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3663 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3664 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3665 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3666 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3667 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3668 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3669 .features[FEAT_VMX_SECONDARY_CTLS] =
3670 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3671 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3672 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3673 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3674 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3675 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3676 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3677 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3678 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3679 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3680 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
0b18874b
PL		 3681 .xlevel = 0x80000008,
3682 .model_id = "Intel Atom Processor (SnowRidge)",
69edb0f3
XL		 3683 .versions = (X86CPUVersionDefinition[]) {
3684 { .version = 1 },
3685 {
3686 .version = 2,
3687 .props = (PropValue[]) {
3688 { "mpx", "off" },
3689 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3690 { /* end of list */ },
3691 },
3692 },
3693 { /* end of list */ },
3694 },
0b18874b 3695 },
a1849515
BF		 3696 {
3697 .name = "KnightsMill",
3698 .level = 0xd,
3699 .vendor = CPUID_VENDOR_INTEL,
3700 .family = 6,
3701 .model = 133,
3702 .stepping = 0,
3703 .features[FEAT_1_EDX] =
3704 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3705 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3706 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3707 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3708 CPUID_PSE | CPUID_DE | CPUID_FP87,
3709 .features[FEAT_1_ECX] =
3710 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3711 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3712 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3713 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3714 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3715 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3716 .features[FEAT_8000_0001_EDX] =
3717 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3718 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3719 .features[FEAT_8000_0001_ECX] =
3720 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3721 .features[FEAT_7_0_EBX] =
3722 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3723 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3724 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3725 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3726 CPUID_7_0_EBX_AVX512ER,
3727 .features[FEAT_7_0_ECX] =
3728 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3729 .features[FEAT_7_0_EDX] =
3730 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3731 .features[FEAT_XSAVE] =
3732 CPUID_XSAVE_XSAVEOPT,
3733 .features[FEAT_6_EAX] =
3734 CPUID_6_EAX_ARAT,
3735 .xlevel = 0x80000008,
3736 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3737 },
3eca4642
EH		 3738 {
3739 .name = "Opteron_G1",
3740 .level = 5,
99b88a17 3741 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3742 .family = 15,
3743 .model = 6,
3744 .stepping = 1,
0514ef2f 3745 .features[FEAT_1_EDX] =
b3a4f0b1 3746 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3750 CPUID_DE | CPUID_FP87,
0514ef2f 3751 .features[FEAT_1_ECX] =
27861ecc 3752 CPUID_EXT_SSE3,
0514ef2f 3753 .features[FEAT_8000_0001_EDX] =
2a923a29 3754 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3eca4642
EH		 3755 .xlevel = 0x80000008,
3756 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3757 },
3758 {
3759 .name = "Opteron_G2",
3760 .level = 5,
99b88a17 3761 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3762 .family = 15,
3763 .model = 6,
3764 .stepping = 1,
0514ef2f 3765 .features[FEAT_1_EDX] =
b3a4f0b1 3766 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3767 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3768 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3769 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3770 CPUID_DE | CPUID_FP87,
0514ef2f 3771 .features[FEAT_1_ECX] =
27861ecc 3772 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
0514ef2f 3773 .features[FEAT_8000_0001_EDX] =
2a923a29 3774 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
0514ef2f 3775 .features[FEAT_8000_0001_ECX] =
27861ecc 3776 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3777 .xlevel = 0x80000008,
3778 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3779 },
3780 {
3781 .name = "Opteron_G3",
3782 .level = 5,
99b88a17 3783 .vendor = CPUID_VENDOR_AMD,
339892d7
EY		 3784 .family = 16,
3785 .model = 2,
3786 .stepping = 3,
0514ef2f 3787 .features[FEAT_1_EDX] =
b3a4f0b1 3788 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3789 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3790 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3791 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3792 CPUID_DE | CPUID_FP87,
0514ef2f 3793 .features[FEAT_1_ECX] =
27861ecc 3794 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
b3fb3a20 3795 CPUID_EXT_SSE3,
0514ef2f 3796 .features[FEAT_8000_0001_EDX] =
483c6ad4
BP		 3797 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3798 CPUID_EXT2_RDTSCP,
0514ef2f 3799 .features[FEAT_8000_0001_ECX] =
27861ecc 3800 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
b3fb3a20 3801 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3eca4642
EH		 3802 .xlevel = 0x80000008,
3803 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3804 },
3805 {
3806 .name = "Opteron_G4",
3807 .level = 0xd,
99b88a17 3808 .vendor = CPUID_VENDOR_AMD,
3eca4642
EH		 3809 .family = 21,
3810 .model = 1,
3811 .stepping = 2,
0514ef2f 3812 .features[FEAT_1_EDX] =
b3a4f0b1 3813 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3814 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3815 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3816 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3817 CPUID_DE | CPUID_FP87,
0514ef2f 3818 .features[FEAT_1_ECX] =
27861ecc 3819 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
b3fb3a20
EH		 3820 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3821 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3822 CPUID_EXT_SSE3,
0514ef2f 3823 .features[FEAT_8000_0001_EDX] =
2a923a29 3824 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3825 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3826 .features[FEAT_8000_0001_ECX] =
27861ecc 3827 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3828 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3829 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3830 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3831 .features[FEAT_SVM] =
3832 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3833 /* no xsaveopt! */
3eca4642
EH		 3834 .xlevel = 0x8000001A,
3835 .model_id = "AMD Opteron 62xx class CPU",
3836 },
021941b9
AP		 3837 {
3838 .name = "Opteron_G5",
3839 .level = 0xd,
99b88a17 3840 .vendor = CPUID_VENDOR_AMD,
021941b9
AP		 3841 .family = 21,
3842 .model = 2,
3843 .stepping = 0,
0514ef2f 3844 .features[FEAT_1_EDX] =
b3a4f0b1 3845 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
b3fb3a20
EH		 3846 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3847 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3848 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3849 CPUID_DE | CPUID_FP87,
0514ef2f 3850 .features[FEAT_1_ECX] =
27861ecc 3851 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
b3fb3a20
EH		 3852 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3853 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3854 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
0514ef2f 3855 .features[FEAT_8000_0001_EDX] =
2a923a29 3856 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
483c6ad4 3857 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
0514ef2f 3858 .features[FEAT_8000_0001_ECX] =
27861ecc 3859 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
b3fb3a20
EH		 3860 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3861 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3862 CPUID_EXT3_LAHF_LM,
9fe8b7be
VK		 3863 .features[FEAT_SVM] =
3864 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
0bb0b2d2 3865 /* no xsaveopt! */
021941b9
AP		 3866 .xlevel = 0x8000001A,
3867 .model_id = "AMD Opteron 63xx class CPU",
3868 },
2e2efc7d
BS		 3869 {
3870 .name = "EPYC",
3871 .level = 0xd,
3872 .vendor = CPUID_VENDOR_AMD,
3873 .family = 23,
3874 .model = 1,
3875 .stepping = 2,
3876 .features[FEAT_1_EDX] =
3877 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3878 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3879 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3880 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3881 CPUID_VME | CPUID_FP87,
3882 .features[FEAT_1_ECX] =
3883 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3884 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3885 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3886 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3887 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3888 .features[FEAT_8000_0001_EDX] =
3889 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3890 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3891 CPUID_EXT2_SYSCALL,
3892 .features[FEAT_8000_0001_ECX] =
3893 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3894 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
e0051647
BM		 3895 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3896 CPUID_EXT3_TOPOEXT,
2e2efc7d
BS		 3897 .features[FEAT_7_0_EBX] =
3898 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3899 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3900 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3901 CPUID_7_0_EBX_SHA_NI,
2e2efc7d
BS		 3902 .features[FEAT_XSAVE] =
3903 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3904 CPUID_XSAVE_XGETBV1,
3905 .features[FEAT_6_EAX] =
3906 CPUID_6_EAX_ARAT,
9fe8b7be
VK		 3907 .features[FEAT_SVM] =
3908 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
e0051647 3909 .xlevel = 0x8000001E,
2e2efc7d 3910 .model_id = "AMD EPYC Processor",
fe52acd2 3911 .cache_info = &epyc_cache_info,
d86a7088
EH		 3912 .versions = (X86CPUVersionDefinition[]) {
3913 { .version = 1 },
3914 {
3915 .version = 2,
53db89d9 3916 .alias = "EPYC-IBPB",
d86a7088
EH		 3917 .props = (PropValue[]) {
3918 { "ibpb", "on" },
3919 { "model-id",
3920 "AMD EPYC Processor (with IBPB)" },
3921 { /* end of list */ }
3922 }
3923 },
a16e8dbc
MB		 3924 {
3925 .version = 3,
3926 .props = (PropValue[]) {
3927 { "ibpb", "on" },
3928 { "perfctr-core", "on" },
3929 { "clzero", "on" },
3930 { "xsaveerptr", "on" },
3931 { "xsaves", "on" },
3932 { "model-id",
3933 "AMD EPYC Processor" },
3934 { /* end of list */ }
3935 }
3936 },
d86a7088
EH		 3937 { /* end of list */ }
3938 }
2e2efc7d 3939 },
8d031cec
PW		 3940 {
3941 .name = "Dhyana",
3942 .level = 0xd,
3943 .vendor = CPUID_VENDOR_HYGON,
3944 .family = 24,
3945 .model = 0,
3946 .stepping = 1,
3947 .features[FEAT_1_EDX] =
3948 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3949 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3950 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3951 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3952 CPUID_VME | CPUID_FP87,
3953 .features[FEAT_1_ECX] =
3954 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3955 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
3956 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3957 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3958 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
3959 .features[FEAT_8000_0001_EDX] =
3960 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3961 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3962 CPUID_EXT2_SYSCALL,
3963 .features[FEAT_8000_0001_ECX] =
3964 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3965 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3966 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3967 CPUID_EXT3_TOPOEXT,
3968 .features[FEAT_8000_0008_EBX] =
3969 CPUID_8000_0008_EBX_IBPB,
3970 .features[FEAT_7_0_EBX] =
3971 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3972 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3973 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
3974 /*
3975 * Missing: XSAVES (not supported by some Linux versions,
3976 * including v4.1 to v4.12).
3977 * KVM doesn't yet expose any XSAVES state save component.
3978 */
3979 .features[FEAT_XSAVE] =
3980 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3981 CPUID_XSAVE_XGETBV1,
3982 .features[FEAT_6_EAX] =
3983 CPUID_6_EAX_ARAT,
3984 .features[FEAT_SVM] =
3985 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3986 .xlevel = 0x8000001E,
3987 .model_id = "Hygon Dhyana Processor",
3988 .cache_info = &epyc_cache_info,
3989 },
143c30d4
MB		 3990 {
3991 .name = "EPYC-Rome",
3992 .level = 0xd,
3993 .vendor = CPUID_VENDOR_AMD,
3994 .family = 23,
3995 .model = 49,
3996 .stepping = 0,
3997 .features[FEAT_1_EDX] =
3998 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3999 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4000 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4001 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4002 CPUID_VME | CPUID_FP87,
4003 .features[FEAT_1_ECX] =
4004 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4005 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4006 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4007 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4008 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4009 .features[FEAT_8000_0001_EDX] =
4010 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4011 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4012 CPUID_EXT2_SYSCALL,
4013 .features[FEAT_8000_0001_ECX] =
4014 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4015 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4016 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4017 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4018 .features[FEAT_8000_0008_EBX] =
4019 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4020 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4021 CPUID_8000_0008_EBX_STIBP,
4022 .features[FEAT_7_0_EBX] =
4023 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4024 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4025 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4026 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4027 .features[FEAT_7_0_ECX] =
4028 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4029 .features[FEAT_XSAVE] =
4030 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4031 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4032 .features[FEAT_6_EAX] =
4033 CPUID_6_EAX_ARAT,
4034 .features[FEAT_SVM] =
4035 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4036 .xlevel = 0x8000001E,
4037 .model_id = "AMD EPYC-Rome Processor",
4038 .cache_info = &epyc_rome_cache_info,
4039 },
c6dc6f63
AP		 4040};
4041
5114e842
EH		 4042/* KVM-specific features that are automatically added/removed
4043 * from all CPU models when KVM is enabled.
4044 */
4045static PropValue kvm_default_props[] = {
4046 { "kvmclock", "on" },
4047 { "kvm-nopiodelay", "on" },
4048 { "kvm-asyncpf", "on" },
4049 { "kvm-steal-time", "on" },
4050 { "kvm-pv-eoi", "on" },
4051 { "kvmclock-stable-bit", "on" },
4052 { "x2apic", "on" },
4053 { "acpi", "off" },
4054 { "monitor", "off" },
4055 { "svm", "off" },
4056 { NULL, NULL },
4057};
4058
04d99c3c
EH		 4059/* TCG-specific defaults that override all CPU models when using TCG
4060 */
4061static PropValue tcg_default_props[] = {
4062 { "vme", "off" },
4063 { NULL, NULL },
4064};
4065
4066
ad183928
EH		 4067/*
4068 * We resolve CPU model aliases using -v1 when using "-machine
4069 * none", but this is just for compatibility while libvirt isn't
4070 * adapted to resolve CPU model versions before creating VMs.
4071 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4072 */
4073X86CPUVersion default_cpu_version = 1;
0788a56b
EH		 4074
4075void x86_cpu_set_default_version(X86CPUVersion version)
4076{
4077 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4078 assert(version != CPU_VERSION_AUTO);
4079 default_cpu_version = version;
4080}
4081
dcafd1ef
EH		 4082static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4083{
4084 int v = 0;
4085 const X86CPUVersionDefinition *vdef =
4086 x86_cpu_def_get_versions(model->cpudef);
4087 while (vdef->version) {
4088 v = vdef->version;
4089 vdef++;
4090 }
4091 return v;
4092}
4093
4094/* Return the actual version being used for a specific CPU model */
4095static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4096{
4097 X86CPUVersion v = model->version;
0788a56b
EH		 4098 if (v == CPU_VERSION_AUTO) {
4099 v = default_cpu_version;
4100 }
dcafd1ef
EH		 4101 if (v == CPU_VERSION_LATEST) {
4102 return x86_cpu_model_last_version(model);
4103 }
4104 return v;
4105}
4106
5114e842
EH		 4107void x86_cpu_change_kvm_default(const char *prop, const char *value)
4108{
4109 PropValue *pv;
4110 for (pv = kvm_default_props; pv->prop; pv++) {
4111 if (!strcmp(pv->prop, prop)) {
4112 pv->value = value;
4113 break;
4114 }
4115 }
4116
4117 /* It is valid to call this function only for properties that
4118 * are already present in the kvm_default_props table.
4119 */
4120 assert(pv->prop);
4121}
4122
ede146c2 4123static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4d1b279b
EH		 4124 bool migratable_only);
4125
40bfe48f
HZ		 4126static bool lmce_supported(void)
4127{
c62f2630 4128 uint64_t mce_cap = 0;
40bfe48f 4129
c62f2630 4130#ifdef CONFIG_KVM
40bfe48f
HZ		 4131 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4132 return false;
4133 }
c62f2630 4134#endif
40bfe48f
HZ		 4135
4136 return !!(mce_cap & MCG_LMCE_P);
4137}
4138
7d8050b5
EH		 4139#define CPUID_MODEL_ID_SZ 48
4140
4141/**
4142 * cpu_x86_fill_model_id:
4143 * Get CPUID model ID string from host CPU.
4144 *
4145 * @str should have at least CPUID_MODEL_ID_SZ bytes
4146 *
4147 * The function does NOT add a null terminator to the string
4148 * automatically.
4149 */
c6dc6f63
AP		 4150static int cpu_x86_fill_model_id(char *str)
4151{
4152 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4153 int i;
4154
4155 for (i = 0; i < 3; i++) {
4156 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4157 memcpy(str + i * 16 + 0, &eax, 4);
4158 memcpy(str + i * 16 + 4, &ebx, 4);
4159 memcpy(str + i * 16 + 8, &ecx, 4);
4160 memcpy(str + i * 16 + 12, &edx, 4);
4161 }
4162 return 0;
4163}
4164
c62f2630 4165static Property max_x86_cpu_properties[] = {
120eee7d 4166 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
e265e3e4 4167 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
84f1b92f
EH		 4168 DEFINE_PROP_END_OF_LIST()
4169};
4170
c62f2630 4171static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
c6dc6f63 4172{
84f1b92f 4173 DeviceClass *dc = DEVICE_CLASS(oc);
d940ee9b 4174 X86CPUClass *xcc = X86_CPU_CLASS(oc);
c6dc6f63 4175
f48c8837 4176 xcc->ordering = 9;
6e746f30 4177
ee465a3e 4178 xcc->model_description =
c62f2630 4179 "Enables all features supported by the accelerator in the current host";
d940ee9b 4180
4f67d30b 4181 device_class_set_props(dc, max_x86_cpu_properties);
d940ee9b
EH		 4182}
4183
c62f2630 4184static void max_x86_cpu_initfn(Object *obj)
d940ee9b
EH		 4185{
4186 X86CPU *cpu = X86_CPU(obj);
4187 CPUX86State *env = &cpu->env;
4188 KVMState *s = kvm_state;
d940ee9b 4189
4d1b279b
EH		 4190 /* We can't fill the features array here because we don't know yet if
4191 * "migratable" is true or false.
4192 */
44bd8e53 4193 cpu->max_features = true;
4d1b279b 4194
d6dcc558 4195 if (accel_uses_host_cpuid()) {
bd182022
EH		 4196 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4197 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4198 int family, model, stepping;
0bacd8b3 4199
bd182022 4200 host_vendor_fms(vendor, &family, &model, &stepping);
bd182022 4201 cpu_x86_fill_model_id(model_id);
0bacd8b3 4202
bd182022
EH		 4203 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
4204 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
4205 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
4206 object_property_set_int(OBJECT(cpu), stepping, "stepping",
4207 &error_abort);
4208 object_property_set_str(OBJECT(cpu), model_id, "model-id",
4209 &error_abort);
0bacd8b3 4210
d6dcc558
SAGDR		 4211 if (kvm_enabled()) {
4212 env->cpuid_min_level =
4213 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4214 env->cpuid_min_xlevel =
4215 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4216 env->cpuid_min_xlevel2 =
4217 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4218 } else {
4219 env->cpuid_min_level =
4220 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4221 env->cpuid_min_xlevel =
4222 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4223 env->cpuid_min_xlevel2 =
4224 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4225 }
40bfe48f
HZ		 4226
4227 if (lmce_supported()) {
4228 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
4229 }
6900d1cc
EH		 4230 } else {
4231 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
4232 "vendor", &error_abort);
4233 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
4234 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
4235 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
4236 object_property_set_str(OBJECT(cpu),
4237 "QEMU TCG CPU version " QEMU_HW_VERSION,
4238 "model-id", &error_abort);
e4356010 4239 }
2a573259 4240
d940ee9b 4241 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
c6dc6f63
AP		 4242}
4243
c62f2630
EH		 4244static const TypeInfo max_x86_cpu_type_info = {
4245 .name = X86_CPU_TYPE_NAME("max"),
4246 .parent = TYPE_X86_CPU,
4247 .instance_init = max_x86_cpu_initfn,
4248 .class_init = max_x86_cpu_class_init,
4249};
4250
d6dcc558 4251#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
c62f2630
EH		 4252static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4253{
4254 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4255
d6dcc558 4256 xcc->host_cpuid_required = true;
c62f2630
EH		 4257 xcc->ordering = 8;
4258
02693cc4
GK		 4259#if defined(CONFIG_KVM)
4260 xcc->model_description =
4261 "KVM processor with all supported host features ";
4262#elif defined(CONFIG_HVF)
4263 xcc->model_description =
4264 "HVF processor with all supported host features ";
4265#endif
c62f2630
EH		 4266}
4267
d940ee9b
EH		 4268static const TypeInfo host_x86_cpu_type_info = {
4269 .name = X86_CPU_TYPE_NAME("host"),
c62f2630 4270 .parent = X86_CPU_TYPE_NAME("max"),
d940ee9b
EH		 4271 .class_init = host_x86_cpu_class_init,
4272};
4273
4274#endif
4275
07585923
RH		 4276static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4277{
4278 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4279
4280 switch (f->type) {
4281 case CPUID_FEATURE_WORD:
4282 {
4283 const char *reg = get_register_name_32(f->cpuid.reg);
4284 assert(reg);
4285 return g_strdup_printf("CPUID.%02XH:%s",
4286 f->cpuid.eax, reg);
4287 }
4288 case MSR_FEATURE_WORD:
4289 return g_strdup_printf("MSR(%02XH)",
4290 f->msr.index);
4291 }
4292
4293 return NULL;
4294}
4295
245edd0c 4296static bool x86_cpu_have_filtered_features(X86CPU *cpu)
c6dc6f63 4297{
245edd0c
PB		 4298 FeatureWord w;
4299
4300 for (w = 0; w < FEATURE_WORDS; w++) {
4301 if (cpu->filtered_features[w]) {
4302 return true;
4303 }
4304 }
4305
4306 return false;
4307}
4308
ede146c2 4309static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
245edd0c
PB		 4310 const char *verbose_prefix)
4311{
4312 CPUX86State *env = &cpu->env;
8459e396 4313 FeatureWordInfo *f = &feature_word_info[w];
c6dc6f63
AP		 4314 int i;
4315
245edd0c
PB		 4316 if (!cpu->force_features) {
4317 env->features[w] &= ~mask;
4318 }
4319 cpu->filtered_features[w] |= mask;
4320
4321 if (!verbose_prefix) {
4322 return;
4323 }
4324
ede146c2
PB		 4325 for (i = 0; i < 64; ++i) {
4326 if ((1ULL << i) & mask) {
88703ce2 4327 g_autofree char *feat_word_str = feature_word_description(f, i);
245edd0c
PB		 4328 warn_report("%s: %s%s%s [bit %d]",
4329 verbose_prefix,
07585923 4330 feat_word_str,
8297be80
AF		 4331 f->feat_names[i] ? "." : "",
4332 f->feat_names[i] ? f->feat_names[i] : "", i);
c6dc6f63 4333 }
857aee33 4334 }
c6dc6f63
AP		 4335}
4336
d7bce999
EB		 4337static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4338 const char *name, void *opaque,
4339 Error **errp)
95b8519d
AF		 4340{
4341 X86CPU *cpu = X86_CPU(obj);
4342 CPUX86State *env = &cpu->env;
4343 int64_t value;
4344
4345 value = (env->cpuid_version >> 8) & 0xf;
4346 if (value == 0xf) {
4347 value += (env->cpuid_version >> 20) & 0xff;
4348 }
51e72bc1 4349 visit_type_int(v, name, &value, errp);
95b8519d
AF		 4350}
4351
d7bce999
EB		 4352static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4353 const char *name, void *opaque,
4354 Error **errp)
ed5e1ec3 4355{
71ad61d3
AF		 4356 X86CPU *cpu = X86_CPU(obj);
4357 CPUX86State *env = &cpu->env;
4358 const int64_t min = 0;
4359 const int64_t max = 0xff + 0xf;
65cd9064 4360 Error *local_err = NULL;
71ad61d3
AF		 4361 int64_t value;
4362
51e72bc1 4363 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 4364 if (local_err) {
4365 error_propagate(errp, local_err);
71ad61d3
AF		 4366 return;
4367 }
4368 if (value < min || value > max) {
c6bd8c70
MA		 4369 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4370 name ? name : "null", value, min, max);
71ad61d3
AF		 4371 return;
4372 }
4373
ed5e1ec3 4374 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 4375 if (value > 0x0f) {
4376 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 4377 } else {
71ad61d3 4378 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 4379 }
4380}
4381
d7bce999
EB		 4382static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4383 const char *name, void *opaque,
4384 Error **errp)
67e30c83
AF		 4385{
4386 X86CPU *cpu = X86_CPU(obj);
4387 CPUX86State *env = &cpu->env;
4388 int64_t value;
4389
4390 value = (env->cpuid_version >> 4) & 0xf;
4391 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
51e72bc1 4392 visit_type_int(v, name, &value, errp);
67e30c83
AF		 4393}
4394
d7bce999
EB		 4395static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4396 const char *name, void *opaque,
4397 Error **errp)
b0704cbd 4398{
c5291a4f
AF		 4399 X86CPU *cpu = X86_CPU(obj);
4400 CPUX86State *env = &cpu->env;
4401 const int64_t min = 0;
4402 const int64_t max = 0xff;
65cd9064 4403 Error *local_err = NULL;
c5291a4f
AF		 4404 int64_t value;
4405
51e72bc1 4406 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 4407 if (local_err) {
4408 error_propagate(errp, local_err);
c5291a4f
AF		 4409 return;
4410 }
4411 if (value < min || value > max) {
c6bd8c70
MA		 4412 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4413 name ? name : "null", value, min, max);
c5291a4f
AF		 4414 return;
4415 }
4416
b0704cbd 4417 env->cpuid_version &= ~0xf00f0;
c5291a4f 4418 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 4419}
4420
35112e41 4421static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
d7bce999 4422 const char *name, void *opaque,
35112e41
AF		 4423 Error **errp)
4424{
4425 X86CPU *cpu = X86_CPU(obj);
4426 CPUX86State *env = &cpu->env;
4427 int64_t value;
4428
4429 value = env->cpuid_version & 0xf;
51e72bc1 4430 visit_type_int(v, name, &value, errp);
35112e41
AF		 4431}
4432
036e2222 4433static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
d7bce999 4434 const char *name, void *opaque,
036e2222 4435 Error **errp)
38c3dc46 4436{
036e2222
AF		 4437 X86CPU *cpu = X86_CPU(obj);
4438 CPUX86State *env = &cpu->env;
4439 const int64_t min = 0;
4440 const int64_t max = 0xf;
65cd9064 4441 Error *local_err = NULL;
036e2222
AF		 4442 int64_t value;
4443
51e72bc1 4444 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 4445 if (local_err) {
4446 error_propagate(errp, local_err);
036e2222
AF		 4447 return;
4448 }
4449 if (value < min || value > max) {
c6bd8c70
MA		 4450 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4451 name ? name : "null", value, min, max);
036e2222
AF		 4452 return;
4453 }
4454
38c3dc46 4455 env->cpuid_version &= ~0xf;
036e2222 4456 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 4457}
4458
d480e1af
AF		 4459static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4460{
4461 X86CPU *cpu = X86_CPU(obj);
4462 CPUX86State *env = &cpu->env;
4463 char *value;
d480e1af 4464
e42a92ae 4465 value = g_malloc(CPUID_VENDOR_SZ + 1);
99b88a17
IM		 4466 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4467 env->cpuid_vendor3);
d480e1af
AF		 4468 return value;
4469}
4470
4471static void x86_cpuid_set_vendor(Object *obj, const char *value,
4472 Error **errp)
4473{
4474 X86CPU *cpu = X86_CPU(obj);
4475 CPUX86State *env = &cpu->env;
4476 int i;
4477
9df694ee 4478 if (strlen(value) != CPUID_VENDOR_SZ) {
c6bd8c70 4479 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
d480e1af
AF		 4480 return;
4481 }
4482
4483 env->cpuid_vendor1 = 0;
4484 env->cpuid_vendor2 = 0;
4485 env->cpuid_vendor3 = 0;
4486 for (i = 0; i < 4; i++) {
4487 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4488 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4489 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4490 }
d480e1af
AF		 4491}
4492
63e886eb
AF		 4493static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4494{
4495 X86CPU *cpu = X86_CPU(obj);
4496 CPUX86State *env = &cpu->env;
4497 char *value;
4498 int i;
4499
4500 value = g_malloc(48 + 1);
4501 for (i = 0; i < 48; i++) {
4502 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4503 }
4504 value[48] = '\0';
4505 return value;
4506}
4507
938d4c25
AF		 4508static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4509 Error **errp)
dcce6675 4510{
938d4c25
AF		 4511 X86CPU *cpu = X86_CPU(obj);
4512 CPUX86State *env = &cpu->env;
dcce6675
AF		 4513 int c, len, i;
4514
4515 if (model_id == NULL) {
4516 model_id = "";
4517 }
4518 len = strlen(model_id);
d0a6acf4 4519 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 4520 for (i = 0; i < 48; i++) {
4521 if (i >= len) {
4522 c = '\0';
4523 } else {
4524 c = (uint8_t)model_id[i];
4525 }
4526 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4527 }
4528}
4529
d7bce999
EB		 4530static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4531 void *opaque, Error **errp)
89e48965
AF		 4532{
4533 X86CPU *cpu = X86_CPU(obj);
4534 int64_t value;
4535
4536 value = cpu->env.tsc_khz * 1000;
51e72bc1 4537 visit_type_int(v, name, &value, errp);
89e48965
AF		 4538}
4539
d7bce999
EB		 4540static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4541 void *opaque, Error **errp)
89e48965
AF		 4542{
4543 X86CPU *cpu = X86_CPU(obj);
4544 const int64_t min = 0;
2e84849a 4545 const int64_t max = INT64_MAX;
65cd9064 4546 Error *local_err = NULL;
89e48965
AF		 4547 int64_t value;
4548
51e72bc1 4549 visit_type_int(v, name, &value, &local_err);
65cd9064
MA		 4550 if (local_err) {
4551 error_propagate(errp, local_err);
89e48965
AF		 4552 return;
4553 }
4554 if (value < min || value > max) {
c6bd8c70
MA		 4555 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4556 name ? name : "null", value, min, max);
89e48965
AF		 4557 return;
4558 }
4559
36f96c4b 4560 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
89e48965
AF		 4561}
4562
7e5292b5 4563/* Generic getter for "feature-words" and "filtered-features" properties */
d7bce999
EB		 4564static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4565 const char *name, void *opaque,
4566 Error **errp)
8e8aba50 4567{
ede146c2 4568 uint64_t *array = (uint64_t *)opaque;
8e8aba50 4569 FeatureWord w;
8e8aba50
EH		 4570 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4571 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4572 X86CPUFeatureWordInfoList *list = NULL;
4573
4574 for (w = 0; w < FEATURE_WORDS; w++) {
4575 FeatureWordInfo *wi = &feature_word_info[w];
07585923
RH		 4576 /*
4577 * We didn't have MSR features when "feature-words" was
4578 * introduced. Therefore skipped other type entries.
4579 */
4580 if (wi->type != CPUID_FEATURE_WORD) {
4581 continue;
4582 }
8e8aba50 4583 X86CPUFeatureWordInfo *qwi = &word_infos[w];
07585923
RH		 4584 qwi->cpuid_input_eax = wi->cpuid.eax;
4585 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4586 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4587 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
7e5292b5 4588 qwi->features = array[w];
8e8aba50
EH		 4589
4590 /* List will be in reverse order, but order shouldn't matter */
4591 list_entries[w].next = list;
4592 list_entries[w].value = &word_infos[w];
4593 list = &list_entries[w];
4594 }
4595
6b62d961 4596 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
8e8aba50
EH		 4597}
4598
72ac2e87
IM		 4599/* Convert all '_' in a feature string option name to '-', to make feature
4600 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4601 */
4602static inline void feat2prop(char *s)
4603{
4604 while ((s = strchr(s, '_'))) {
4605 *s = '-';
4606 }
4607}
4608
b54c9377
EH		 4609/* Return the feature property name for a feature flag bit */
4610static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4611{
ede146c2 4612 const char *name;
b54c9377
EH		 4613 /* XSAVE components are automatically enabled by other features,
4614 * so return the original feature name instead
4615 */
4616 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4617 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4618
4619 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4620 x86_ext_save_areas[comp].bits) {
4621 w = x86_ext_save_areas[comp].feature;
4622 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4623 }
4624 }
4625
ede146c2 4626 assert(bitnr < 64);
b54c9377 4627 assert(w < FEATURE_WORDS);
ede146c2
PB		 4628 name = feature_word_info[w].feat_names[bitnr];
4629 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4630 return name;
b54c9377
EH		 4631}
4632
dc15c051
IM		 4633/* Compatibily hack to maintain legacy +-feat semantic,
4634 * where +-feat overwrites any feature set by
4635 * feat=on|feat even if the later is parsed after +-feat
4636 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4637 */
2fae0d96 4638static GList *plus_features, *minus_features;
dc15c051 4639
83a00f60
EH		 4640static gint compare_string(gconstpointer a, gconstpointer b)
4641{
4642 return g_strcmp0(a, b);
4643}
4644
8f961357
EH		 4645/* Parse "+feature,-feature,feature=foo" CPU feature string
4646 */
62a48a2a 4647static void x86_cpu_parse_featurestr(const char *typename, char *features,
94a444b2 4648 Error **errp)
8f961357 4649{
8f961357 4650 char *featurestr; /* Single 'key=value" string being parsed */
62a48a2a 4651 static bool cpu_globals_initialized;
83a00f60 4652 bool ambiguous = false;
62a48a2a
IM		 4653
4654 if (cpu_globals_initialized) {
4655 return;
4656 }
4657 cpu_globals_initialized = true;
8f961357 4658
f6750e95
EH		 4659 if (!features) {
4660 return;
4661 }
4662
4663 for (featurestr = strtok(features, ",");
685479bd 4664 featurestr;
f6750e95
EH		 4665 featurestr = strtok(NULL, ",")) {
4666 const char *name;
4667 const char *val = NULL;
4668 char *eq = NULL;
cf2887c9 4669 char num[32];
62a48a2a 4670 GlobalProperty *prop;
c6dc6f63 4671
f6750e95 4672 /* Compatibility syntax: */
c6dc6f63 4673 if (featurestr[0] == '+') {
2fae0d96
EH		 4674 plus_features = g_list_append(plus_features,
4675 g_strdup(featurestr + 1));
f6750e95 4676 continue;
c6dc6f63 4677 } else if (featurestr[0] == '-') {
2fae0d96
EH		 4678 minus_features = g_list_append(minus_features,
4679 g_strdup(featurestr + 1));
f6750e95
EH		 4680 continue;
4681 }
4682
4683 eq = strchr(featurestr, '=');
4684 if (eq) {
4685 *eq++ = 0;
4686 val = eq;
c6dc6f63 4687 } else {
f6750e95 4688 val = "on";
a91987c2 4689 }
f6750e95
EH		 4690
4691 feat2prop(featurestr);
4692 name = featurestr;
4693
83a00f60 4694 if (g_list_find_custom(plus_features, name, compare_string)) {
3dc6f869
AF		 4695 warn_report("Ambiguous CPU model string. "
4696 "Don't mix both \"+%s\" and \"%s=%s\"",
4697 name, name, val);
83a00f60
EH		 4698 ambiguous = true;
4699 }
4700 if (g_list_find_custom(minus_features, name, compare_string)) {
3dc6f869
AF		 4701 warn_report("Ambiguous CPU model string. "
4702 "Don't mix both \"-%s\" and \"%s=%s\"",
4703 name, name, val);
83a00f60
EH		 4704 ambiguous = true;
4705 }
4706
f6750e95
EH		 4707 /* Special case: */
4708 if (!strcmp(name, "tsc-freq")) {
f17fd4fd 4709 int ret;
f46bfdbf 4710 uint64_t tsc_freq;
f6750e95 4711
f17fd4fd 4712 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
f46bfdbf 4713 if (ret < 0 || tsc_freq > INT64_MAX) {
f6750e95
EH		 4714 error_setg(errp, "bad numerical value %s", val);
4715 return;
4716 }
4717 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4718 val = num;
4719 name = "tsc-frequency";
c6dc6f63 4720 }
f6750e95 4721
62a48a2a
IM		 4722 prop = g_new0(typeof(*prop), 1);
4723 prop->driver = typename;
4724 prop->property = g_strdup(name);
4725 prop->value = g_strdup(val);
62a48a2a 4726 qdev_prop_register_global(prop);
f6750e95
EH		 4727 }
4728
83a00f60 4729 if (ambiguous) {
3dc6f869
AF		 4730 warn_report("Compatibility of ambiguous CPU model "
4731 "strings won't be kept on future QEMU versions");
83a00f60 4732 }
c6dc6f63
AP		 4733}
4734
b8d834a0 4735static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
245edd0c 4736static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
b54c9377 4737
5a853fc5
EH		 4738/* Build a list with the name of all features on a feature word array */
4739static void x86_cpu_list_feature_names(FeatureWordArray features,
4740 strList **feat_names)
4741{
4742 FeatureWord w;
4743 strList **next = feat_names;
4744
4745 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 4746 uint64_t filtered = features[w];
5a853fc5 4747 int i;
ede146c2
PB		 4748 for (i = 0; i < 64; i++) {
4749 if (filtered & (1ULL << i)) {
5a853fc5
EH		 4750 strList *new = g_new0(strList, 1);
4751 new->value = g_strdup(x86_cpu_feature_name(w, i));
4752 *next = new;
4753 next = &new->next;
4754 }
4755 }
4756 }
4757}
4758
506174bf
EH		 4759static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4760 const char *name, void *opaque,
4761 Error **errp)
4762{
4763 X86CPU *xc = X86_CPU(obj);
4764 strList *result = NULL;
4765
4766 x86_cpu_list_feature_names(xc->filtered_features, &result);
4767 visit_type_strList(v, "unavailable-features", &result, errp);
4768}
4769
b54c9377
EH		 4770/* Check for missing features that may prevent the CPU class from
4771 * running using the current machine and accelerator.
4772 */
4773static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4774 strList **missing_feats)
4775{
4776 X86CPU *xc;
b54c9377
EH		 4777 Error *err = NULL;
4778 strList **next = missing_feats;
4779
d6dcc558 4780 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
b54c9377 4781 strList *new = g_new0(strList, 1);
3c254ab8 4782 new->value = g_strdup("kvm");
b54c9377
EH		 4783 *missing_feats = new;
4784 return;
4785 }
4786
3c75e12e 4787 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
b54c9377 4788
b8d834a0 4789 x86_cpu_expand_features(xc, &err);
b54c9377 4790 if (err) {
b8d834a0 4791 /* Errors at x86_cpu_expand_features should never happen,
b54c9377
EH		 4792 * but in case it does, just report the model as not
4793 * runnable at all using the "type" property.
4794 */
4795 strList *new = g_new0(strList, 1);
4796 new->value = g_strdup("type");
4797 *next = new;
4798 next = &new->next;
4799 }
4800
245edd0c 4801 x86_cpu_filter_features(xc, false);
b54c9377 4802
5a853fc5 4803 x86_cpu_list_feature_names(xc->filtered_features, next);
b54c9377
EH		 4804
4805 object_unref(OBJECT(xc));
4806}
4807
8c3329e5 4808/* Print all cpuid feature names in featureset
c6dc6f63 4809 */
0442428a 4810static void listflags(GList *features)
0856579c 4811{
cc643b1e
DB		 4812 size_t len = 0;
4813 GList *tmp;
4814
4815 for (tmp = features; tmp; tmp = tmp->next) {
4816 const char *name = tmp->data;
4817 if ((len + strlen(name) + 1) >= 75) {
0442428a 4818 qemu_printf("\n");
cc643b1e 4819 len = 0;
c6dc6f63 4820 }
0442428a 4821 qemu_printf("%s%s", len == 0 ? " " : " ", name);
cc643b1e 4822 len += strlen(name) + 1;
8c3329e5 4823 }
0442428a 4824 qemu_printf("\n");
c6dc6f63
AP		 4825}
4826
f48c8837 4827/* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
ee465a3e
EH		 4828static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4829{
4830 ObjectClass *class_a = (ObjectClass *)a;
4831 ObjectClass *class_b = (ObjectClass *)b;
4832 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4833 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
c7dbff4b 4834 int ret;
ee465a3e 4835
f48c8837 4836 if (cc_a->ordering != cc_b->ordering) {
c7dbff4b 4837 ret = cc_a->ordering - cc_b->ordering;
ee465a3e 4838 } else {
88703ce2
EH		 4839 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4840 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
c7dbff4b 4841 ret = strcmp(name_a, name_b);
ee465a3e 4842 }
c7dbff4b 4843 return ret;
ee465a3e
EH		 4844}
4845
4846static GSList *get_sorted_cpu_model_list(void)
4847{
4848 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4849 list = g_slist_sort(list, x86_cpu_list_compare);
4850 return list;
4851}
4852
164e779c
EH		 4853static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4854{
3c75e12e 4855 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
164e779c
EH		 4856 char *r = object_property_get_str(obj, "model-id", &error_abort);
4857 object_unref(obj);
4858 return r;
4859}
4860
0788a56b
EH		 4861static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4862{
4863 X86CPUVersion version;
4864
4865 if (!cc->model || !cc->model->is_alias) {
4866 return NULL;
4867 }
4868 version = x86_cpu_model_resolve_version(cc->model);
4869 if (version <= 0) {
4870 return NULL;
4871 }
4872 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4873}
4874
ee465a3e
EH		 4875static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4876{
4877 ObjectClass *oc = data;
4878 X86CPUClass *cc = X86_CPU_CLASS(oc);
88703ce2
EH		 4879 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4880 g_autofree char *desc = g_strdup(cc->model_description);
4881 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
c63938df 4882 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
164e779c 4883
0788a56b
EH		 4884 if (!desc && alias_of) {
4885 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4886 desc = g_strdup("(alias configured by machine type)");
4887 } else {
4888 desc = g_strdup_printf("(alias of %s)", alias_of);
4889 }
4890 }
c63938df
TX		 4891 if (!desc && cc->model && cc->model->note) {
4892 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4893 }
164e779c 4894 if (!desc) {
c63938df 4895 desc = g_strdup_printf("%s", model_id);
ee465a3e
EH		 4896 }
4897
c63938df 4898 qemu_printf("x86 %-20s %-58s\n", name, desc);
ee465a3e
EH		 4899}
4900
4901/* list available CPU models and flags */
0442428a 4902void x86_cpu_list(void)
c6dc6f63 4903{
cc643b1e 4904 int i, j;
ee465a3e 4905 GSList *list;
cc643b1e 4906 GList *names = NULL;
c6dc6f63 4907
0442428a 4908 qemu_printf("Available CPUs:\n");
ee465a3e 4909 list = get_sorted_cpu_model_list();
0442428a 4910 g_slist_foreach(list, x86_cpu_list_entry, NULL);
ee465a3e 4911 g_slist_free(list);
21ad7789 4912
cc643b1e 4913 names = NULL;
3af60be2
JK		 4914 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4915 FeatureWordInfo *fw = &feature_word_info[i];
ede146c2 4916 for (j = 0; j < 64; j++) {
cc643b1e
DB		 4917 if (fw->feat_names[j]) {
4918 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4919 }
4920 }
3af60be2 4921 }
cc643b1e
DB		 4922
4923 names = g_list_sort(names, (GCompareFunc)strcmp);
4924
0442428a
MA		 4925 qemu_printf("\nRecognized CPUID flags:\n");
4926 listflags(names);
4927 qemu_printf("\n");
cc643b1e 4928 g_list_free(names);
c6dc6f63
AP		 4929}
4930
ee465a3e
EH		 4931static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4932{
4933 ObjectClass *oc = data;
4934 X86CPUClass *cc = X86_CPU_CLASS(oc);
4935 CpuDefinitionInfoList **cpu_list = user_data;
4936 CpuDefinitionInfoList *entry;
4937 CpuDefinitionInfo *info;
4938
4939 info = g_malloc0(sizeof(*info));
4940 info->name = x86_cpu_class_get_model_name(cc);
b54c9377
EH		 4941 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4942 info->has_unavailable_features = true;
8ed877b7 4943 info->q_typename = g_strdup(object_class_get_name(oc));
bd72159d
EH		 4944 info->migration_safe = cc->migration_safe;
4945 info->has_migration_safe = true;
5adbed30 4946 info->q_static = cc->static_model;
0788a56b
EH		 4947 /*
4948 * Old machine types won't report aliases, so that alias translation
4949 * doesn't break compatibility with previous QEMU versions.
4950 */
4951 if (default_cpu_version != CPU_VERSION_LEGACY) {
4952 info->alias_of = x86_cpu_class_get_alias_of(cc);
4953 info->has_alias_of = !!info->alias_of;
4954 }
ee465a3e
EH		 4955
4956 entry = g_malloc0(sizeof(*entry));
4957 entry->value = info;
4958 entry->next = *cpu_list;
4959 *cpu_list = entry;
4960}
4961
25a9d6ca 4962CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
e3966126
AL		 4963{
4964 CpuDefinitionInfoList *cpu_list = NULL;
ee465a3e
EH		 4965 GSList *list = get_sorted_cpu_model_list();
4966 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4967 g_slist_free(list);
e3966126
AL		 4968 return cpu_list;
4969}
4970
ede146c2 4971static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
84f1b92f 4972 bool migratable_only)
27418adf
EH		 4973{
4974 FeatureWordInfo *wi = &feature_word_info[w];
ede146c2 4975 uint64_t r = 0;
27418adf 4976
fefb41bf 4977 if (kvm_enabled()) {
07585923
RH		 4978 switch (wi->type) {
4979 case CPUID_FEATURE_WORD:
4980 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4981 wi->cpuid.ecx,
4982 wi->cpuid.reg);
4983 break;
4984 case MSR_FEATURE_WORD:
d86f9636
RH		 4985 r = kvm_arch_get_supported_msr_feature(kvm_state,
4986 wi->msr.index);
07585923
RH		 4987 break;
4988 }
d6dcc558 4989 } else if (hvf_enabled()) {
07585923
RH		 4990 if (wi->type != CPUID_FEATURE_WORD) {
4991 return 0;
4992 }
4993 r = hvf_get_supported_cpuid(wi->cpuid.eax,
4994 wi->cpuid.ecx,
4995 wi->cpuid.reg);
fefb41bf 4996 } else if (tcg_enabled()) {
84f1b92f 4997 r = wi->tcg_features;
fefb41bf
EH		 4998 } else {
4999 return ~0;
5000 }
84f1b92f
EH		 5001 if (migratable_only) {
5002 r &= x86_cpu_get_migratable_flags(w);
5003 }
5004 return r;
27418adf
EH		 5005}
5006
5114e842
EH		 5007static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5008{
5009 PropValue *pv;
5010 for (pv = props; pv->prop; pv++) {
5011 if (!pv->value) {
5012 continue;
5013 }
5014 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
5015 &error_abort);
5016 }
5017}
5018
dcafd1ef
EH		 5019/* Apply properties for the CPU model version specified in model */
5020static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5021{
5022 const X86CPUVersionDefinition *vdef;
5023 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5024
5025 if (version == CPU_VERSION_LEGACY) {
5026 return;
5027 }
5028
5029 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5030 PropValue *p;
5031
5032 for (p = vdef->props; p && p->prop; p++) {
5033 object_property_parse(OBJECT(cpu), p->value, p->prop,
5034 &error_abort);
5035 }
5036
5037 if (vdef->version == version) {
5038 break;
5039 }
5040 }
5041
5042 /*
5043 * If we reached the end of the list, version number was invalid
5044 */
5045 assert(vdef->version == version);
5046}
5047
f99fd7ca 5048/* Load data from X86CPUDefinition into a X86CPU object
c080e30e 5049 */
dcafd1ef 5050static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
c6dc6f63 5051{
dcafd1ef 5052 X86CPUDefinition *def = model->cpudef;
61dcd775 5053 CPUX86State *env = &cpu->env;
74f54bc4
EH		 5054 const char *vendor;
5055 char host_vendor[CPUID_VENDOR_SZ + 1];
e1c224b4 5056 FeatureWord w;
c6dc6f63 5057
f99fd7ca
EH		 5058 /*NOTE: any property set by this function should be returned by
5059 * x86_cpu_static_props(), so static expansion of
5060 * query-cpu-model-expansion is always complete.
5061 */
5062
c39c0edf 5063 /* CPU models only set _minimum_ values for level/xlevel: */
709fa704
MAL		 5064 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
5065 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
c39c0edf 5066
2d64255b
AF		 5067 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
5068 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
5069 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2d64255b 5070 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
e1c224b4
EH		 5071 for (w = 0; w < FEATURE_WORDS; w++) {
5072 env->features[w] = def->features[w];
5073 }
82beb536 5074
a9f27ea9
EH		 5075 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5076 cpu->legacy_cache = !def->cache_info;
ab8f992e 5077
9576de75 5078 /* Special cases not set in the X86CPUDefinition structs: */
d6dcc558 5079 /* TODO: in-kernel irqchip for hvf */
82beb536 5080 if (kvm_enabled()) {
492a4c94
LT		 5081 if (!kvm_irqchip_in_kernel()) {
5082 x86_cpu_change_kvm_default("x2apic", "off");
5083 }
5084
5114e842 5085 x86_cpu_apply_props(cpu, kvm_default_props);
04d99c3c
EH		 5086 } else if (tcg_enabled()) {
5087 x86_cpu_apply_props(cpu, tcg_default_props);
82beb536 5088 }
5fcca9ff 5089
82beb536 5090 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
7c08db30
EH		 5091
5092 /* sysenter isn't supported in compatibility mode on AMD,
5093 * syscall isn't supported in compatibility mode on Intel.
5094 * Normally we advertise the actual CPU vendor, but you can
5095 * override this using the 'vendor' property if you want to use
5096 * KVM's sysenter/syscall emulation in compatibility mode and
5097 * when doing cross vendor migration
5098 */
74f54bc4 5099 vendor = def->vendor;
d6dcc558 5100 if (accel_uses_host_cpuid()) {
7c08db30
EH		 5101 uint32_t ebx = 0, ecx = 0, edx = 0;
5102 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5103 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5104 vendor = host_vendor;
5105 }
5106
5107 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
5108
dcafd1ef 5109 x86_cpu_apply_version_props(cpu, model);
c6dc6f63
AP		 5110}
5111
96f75b59 5112#ifndef CONFIG_USER_ONLY
f99fd7ca 5113/* Return a QDict containing keys for all properties that can be included
dcafd1ef 5114 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
f99fd7ca
EH		 5115 * must be included in the dictionary.
5116 */
5117static QDict *x86_cpu_static_props(void)
5118{
5119 FeatureWord w;
5120 int i;
5121 static const char *props[] = {
5122 "min-level",
5123 "min-xlevel",
5124 "family",
5125 "model",
5126 "stepping",
5127 "model-id",
5128 "vendor",
5129 "lmce",
5130 NULL,
5131 };
5132 static QDict *d;
5133
5134 if (d) {
5135 return d;
5136 }
5137
5138 d = qdict_new();
5139 for (i = 0; props[i]; i++) {
0f9afc2a 5140 qdict_put_null(d, props[i]);
f99fd7ca
EH		 5141 }
5142
5143 for (w = 0; w < FEATURE_WORDS; w++) {
5144 FeatureWordInfo *fi = &feature_word_info[w];
5145 int bit;
ede146c2 5146 for (bit = 0; bit < 64; bit++) {
f99fd7ca
EH		 5147 if (!fi->feat_names[bit]) {
5148 continue;
5149 }
0f9afc2a 5150 qdict_put_null(d, fi->feat_names[bit]);
f99fd7ca
EH		 5151 }
5152 }
5153
5154 return d;
5155}
5156
5157/* Add an entry to @props dict, with the value for property. */
5158static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5159{
5160 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5161 &error_abort);
5162
5163 qdict_put_obj(props, prop, value);
5164}
5165
5166/* Convert CPU model data from X86CPU object to a property dictionary
5167 * that can recreate exactly the same CPU model.
5168 */
5169static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5170{
5171 QDict *sprops = x86_cpu_static_props();
5172 const QDictEntry *e;
5173
5174 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5175 const char *prop = qdict_entry_key(e);
5176 x86_cpu_expand_prop(cpu, props, prop);
5177 }
5178}
5179
b8097deb
EH		 5180/* Convert CPU model data from X86CPU object to a property dictionary
5181 * that can recreate exactly the same CPU model, including every
5182 * writeable QOM property.
5183 */
5184static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5185{
5186 ObjectPropertyIterator iter;
5187 ObjectProperty *prop;
5188
5189 object_property_iter_init(&iter, OBJECT(cpu));
5190 while ((prop = object_property_iter_next(&iter))) {
5191 /* skip read-only or write-only properties */
5192 if (!prop->get || !prop->set) {
5193 continue;
5194 }
5195
5196 /* "hotplugged" is the only property that is configurable
5197 * on the command-line but will be set differently on CPUs
5198 * created using "-cpu ... -smp ..." and by CPUs created
5199 * on the fly by x86_cpu_from_model() for querying. Skip it.
5200 */
5201 if (!strcmp(prop->name, "hotplugged")) {
5202 continue;
5203 }
5204 x86_cpu_expand_prop(cpu, props, prop->name);
5205 }
5206}
5207
f99fd7ca
EH		 5208static void object_apply_props(Object *obj, QDict *props, Error **errp)
5209{
5210 const QDictEntry *prop;
5211 Error *err = NULL;
5212
5213 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5214 object_property_set_qobject(obj, qdict_entry_value(prop),
5215 qdict_entry_key(prop), &err);
5216 if (err) {
5217 break;
5218 }
5219 }
5220
5221 error_propagate(errp, err);
5222}
5223
5224/* Create X86CPU object according to model+props specification */
5225static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5226{
5227 X86CPU *xc = NULL;
5228 X86CPUClass *xcc;
5229 Error *err = NULL;
5230
5231 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5232 if (xcc == NULL) {
5233 error_setg(&err, "CPU model '%s' not found", model);
5234 goto out;
5235 }
5236
3c75e12e 5237 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
f99fd7ca
EH		 5238 if (props) {
5239 object_apply_props(OBJECT(xc), props, &err);
5240 if (err) {
5241 goto out;
5242 }
5243 }
5244
5245 x86_cpu_expand_features(xc, &err);
5246 if (err) {
5247 goto out;
5248 }
5249
5250out:
5251 if (err) {
5252 error_propagate(errp, err);
5253 object_unref(OBJECT(xc));
5254 xc = NULL;
5255 }
5256 return xc;
5257}
5258
5259CpuModelExpansionInfo *
96f75b59 5260qmp_query_cpu_model_expansion(CpuModelExpansionType type,
f99fd7ca
EH		 5261 CpuModelInfo *model,
5262 Error **errp)
5263{
5264 X86CPU *xc = NULL;
5265 Error *err = NULL;
5266 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5267 QDict *props = NULL;
5268 const char *base_name;
5269
5270 xc = x86_cpu_from_model(model->name,
5271 model->has_props ?
7dc847eb 5272 qobject_to(QDict, model->props) :
f99fd7ca
EH		 5273 NULL, &err);
5274 if (err) {
5275 goto out;
5276 }
5277
b8097deb 5278 props = qdict_new();
e38bf612
EH		 5279 ret->model = g_new0(CpuModelInfo, 1);
5280 ret->model->props = QOBJECT(props);
5281 ret->model->has_props = true;
f99fd7ca
EH		 5282
5283 switch (type) {
5284 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5285 /* Static expansion will be based on "base" only */
5286 base_name = "base";
b8097deb 5287 x86_cpu_to_dict(xc, props);
f99fd7ca
EH		 5288 break;
5289 case CPU_MODEL_EXPANSION_TYPE_FULL:
5290 /* As we don't return every single property, full expansion needs
5291 * to keep the original model name+props, and add extra
5292 * properties on top of that.
5293 */
5294 base_name = model->name;
b8097deb 5295 x86_cpu_to_dict_full(xc, props);
f99fd7ca
EH		 5296 break;
5297 default:
df68a7f3 5298 error_setg(&err, "Unsupported expansion type");
f99fd7ca
EH		 5299 goto out;
5300 }
5301
f99fd7ca
EH		 5302 x86_cpu_to_dict(xc, props);
5303
f99fd7ca 5304 ret->model->name = g_strdup(base_name);
f99fd7ca
EH		 5305
5306out:
5307 object_unref(OBJECT(xc));
5308 if (err) {
5309 error_propagate(errp, err);
5310 qapi_free_CpuModelExpansionInfo(ret);
5311 ret = NULL;
5312 }
5313 return ret;
5314}
96f75b59 5315#endif /* !CONFIG_USER_ONLY */
f99fd7ca 5316
00fcd100
AB		 5317static gchar *x86_gdb_arch_name(CPUState *cs)
5318{
5319#ifdef TARGET_X86_64
5320 return g_strdup("i386:x86-64");
5321#else
5322 return g_strdup("i386");
5323#endif
5324}
5325
d940ee9b
EH		 5326static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5327{
dcafd1ef 5328 X86CPUModel *model = data;
d940ee9b
EH		 5329 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5330
dcafd1ef 5331 xcc->model = model;
bd72159d 5332 xcc->migration_safe = true;
d940ee9b
EH		 5333}
5334
dcafd1ef 5335static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
d940ee9b 5336{
88703ce2 5337 g_autofree char *typename = x86_cpu_type_name(name);
d940ee9b
EH		 5338 TypeInfo ti = {
5339 .name = typename,
5340 .parent = TYPE_X86_CPU,
5341 .class_init = x86_cpu_cpudef_class_init,
dcafd1ef 5342 .class_data = model,
d940ee9b
EH		 5343 };
5344
dcafd1ef 5345 type_register(&ti);
dcafd1ef
EH		 5346}
5347
5348static void x86_register_cpudef_types(X86CPUDefinition *def)
5349{
5350 X86CPUModel *m;
5351 const X86CPUVersionDefinition *vdef;
dcafd1ef 5352
2a923a29
EH		 5353 /* AMD aliases are handled at runtime based on CPUID vendor, so
5354 * they shouldn't be set on the CPU model table.
5355 */
5356 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
807e9869
EH		 5357 /* catch mistakes instead of silently truncating model_id when too long */
5358 assert(def->model_id && strlen(def->model_id) <= 48);
5359
dcafd1ef
EH		 5360 /* Unversioned model: */
5361 m = g_new0(X86CPUModel, 1);
5362 m->cpudef = def;
0788a56b
EH		 5363 m->version = CPU_VERSION_AUTO;
5364 m->is_alias = true;
dcafd1ef
EH		 5365 x86_register_cpu_model_type(def->name, m);
5366
5367 /* Versioned models: */
5368
5369 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5370 X86CPUModel *m = g_new0(X86CPUModel, 1);
88703ce2
EH		 5371 g_autofree char *name =
5372 x86_cpu_versioned_model_name(def, vdef->version);
dcafd1ef
EH		 5373 m->cpudef = def;
5374 m->version = vdef->version;
c63938df 5375 m->note = vdef->note;
dcafd1ef 5376 x86_register_cpu_model_type(name, m);
53db89d9
EH		 5377
5378 if (vdef->alias) {
5379 X86CPUModel *am = g_new0(X86CPUModel, 1);
5380 am->cpudef = def;
5381 am->version = vdef->version;
0788a56b 5382 am->is_alias = true;
53db89d9
EH		 5383 x86_register_cpu_model_type(vdef->alias, am);
5384 }
dcafd1ef 5385 }
2a923a29 5386
d940ee9b
EH		 5387}
5388
c6dc6f63 5389#if !defined(CONFIG_USER_ONLY)
c6dc6f63 5390
0e26b7b8
BS		 5391void cpu_clear_apic_feature(CPUX86State *env)
5392{
0514ef2f 5393 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
0e26b7b8
BS		 5394}
5395
c6dc6f63
AP		 5396#endif /* !CONFIG_USER_ONLY */
5397
c6dc6f63
AP		 5398void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5399 uint32_t *eax, uint32_t *ebx,
5400 uint32_t *ecx, uint32_t *edx)
5401{
6aa9e42f
RH		 5402 X86CPU *cpu = env_archcpu(env);
5403 CPUState *cs = env_cpu(env);
d65af288 5404 uint32_t die_offset;
4ed3d478 5405 uint32_t limit;
1ce36bfe 5406 uint32_t signature[3];
f20dec0b
BM		 5407 X86CPUTopoInfo topo_info;
5408
dd08ef03 5409 topo_info.nodes_per_pkg = env->nr_nodes;
f20dec0b
BM		 5410 topo_info.dies_per_pkg = env->nr_dies;
5411 topo_info.cores_per_die = cs->nr_cores;
5412 topo_info.threads_per_core = cs->nr_threads;
a60f24b5 5413
4ed3d478
DB		 5414 /* Calculate & apply limits for different index ranges */
5415 if (index >= 0xC0000000) {
5416 limit = env->cpuid_xlevel2;
5417 } else if (index >= 0x80000000) {
5418 limit = env->cpuid_xlevel;
1ce36bfe
DB		 5419 } else if (index >= 0x40000000) {
5420 limit = 0x40000001;
c6dc6f63 5421 } else {
4ed3d478
DB		 5422 limit = env->cpuid_level;
5423 }
5424
5425 if (index > limit) {
5426 /* Intel documentation states that invalid EAX input will
5427 * return the same information as EAX=cpuid_level
5428 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5429 */
5430 index = env->cpuid_level;
c6dc6f63
AP		 5431 }
5432
5433 switch(index) {
5434 case 0:
5435 *eax = env->cpuid_level;
5eb2f7a4
EH		 5436 *ebx = env->cpuid_vendor1;
5437 *edx = env->cpuid_vendor2;
5438 *ecx = env->cpuid_vendor3;
c6dc6f63
AP		 5439 break;
5440 case 1:
5441 *eax = env->cpuid_version;
7e72a45c
EH		 5442 *ebx = (cpu->apic_id << 24) |
5443 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
0514ef2f 5444 *ecx = env->features[FEAT_1_ECX];
19dc85db
RH		 5445 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5446 *ecx |= CPUID_EXT_OSXSAVE;
5447 }
0514ef2f 5448 *edx = env->features[FEAT_1_EDX];
ce3960eb
AF		 5449 if (cs->nr_cores * cs->nr_threads > 1) {
5450 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
19dc85db 5451 *edx |= CPUID_HT;
c6dc6f63
AP		 5452 }
5453 break;
5454 case 2:
5455 /* cache info: needed for Pentium Pro compatibility */
787aaf57
BC		 5456 if (cpu->cache_info_passthrough) {
5457 host_cpuid(index, 0, eax, ebx, ecx, edx);
5458 break;
5459 }
5e891bf8 5460 *eax = 1; /* Number of CPUID[EAX=2] calls required */
c6dc6f63 5461 *ebx = 0;
14c985cf
LM		 5462 if (!cpu->enable_l3_cache) {
5463 *ecx = 0;
5464 } else {
a9f27ea9 5465 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
14c985cf 5466 }
a9f27ea9
EH		 5467 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5468 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5469 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
c6dc6f63
AP		 5470 break;
5471 case 4:
5472 /* cache info: needed for Core compatibility */
787aaf57
BC		 5473 if (cpu->cache_info_passthrough) {
5474 host_cpuid(index, count, eax, ebx, ecx, edx);
7e3482f8 5475 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
76c2975a 5476 *eax &= ~0xFC000000;
7e3482f8
EH		 5477 if ((*eax & 31) && cs->nr_cores > 1) {
5478 *eax |= (cs->nr_cores - 1) << 26;
5479 }
c6dc6f63 5480 } else {
2f7a21c4 5481 *eax = 0;
76c2975a 5482 switch (count) {
c6dc6f63 5483 case 0: /* L1 dcache info */
a9f27ea9
EH		 5484 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5485 1, cs->nr_cores,
7e3482f8 5486 eax, ebx, ecx, edx);
c6dc6f63
AP		 5487 break;
5488 case 1: /* L1 icache info */
a9f27ea9
EH		 5489 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5490 1, cs->nr_cores,
7e3482f8 5491 eax, ebx, ecx, edx);
c6dc6f63
AP		 5492 break;
5493 case 2: /* L2 cache info */
a9f27ea9
EH		 5494 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5495 cs->nr_threads, cs->nr_cores,
7e3482f8 5496 eax, ebx, ecx, edx);
c6dc6f63 5497 break;
14c985cf 5498 case 3: /* L3 cache info */
f20dec0b 5499 die_offset = apicid_die_offset(&topo_info);
7e3482f8 5500 if (cpu->enable_l3_cache) {
a9f27ea9 5501 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
d65af288 5502 (1 << die_offset), cs->nr_cores,
7e3482f8 5503 eax, ebx, ecx, edx);
14c985cf
LM		 5504 break;
5505 }
7e3482f8 5506 /* fall through */
c6dc6f63 5507 default: /* end of info */
7e3482f8 5508 *eax = *ebx = *ecx = *edx = 0;
c6dc6f63 5509 break;
76c2975a
PB		 5510 }
5511 }
c6dc6f63
AP		 5512 break;
5513 case 5:
2266d443
MT		 5514 /* MONITOR/MWAIT Leaf */
5515 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5516 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5517 *ecx = cpu->mwait.ecx; /* flags */
5518 *edx = cpu->mwait.edx; /* mwait substates */
c6dc6f63
AP		 5519 break;
5520 case 6:
5521 /* Thermal and Power Leaf */
28b8e4d0 5522 *eax = env->features[FEAT_6_EAX];
c6dc6f63
AP		 5523 *ebx = 0;
5524 *ecx = 0;
5525 *edx = 0;
5526 break;
f7911686 5527 case 7:
13526728
EH		 5528 /* Structured Extended Feature Flags Enumeration Leaf */
5529 if (count == 0) {
80db491d
JL		 5530 /* Maximum ECX value for sub-leaves */
5531 *eax = env->cpuid_level_func7;
0514ef2f 5532 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
f74eefe0 5533 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
0f70ed47
PB		 5534 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5535 *ecx |= CPUID_7_0_ECX_OSPKE;
5536 }
95ea69fb 5537 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
80db491d
JL		 5538 } else if (count == 1) {
5539 *eax = env->features[FEAT_7_1_EAX];
5540 *ebx = 0;
5541 *ecx = 0;
5542 *edx = 0;
f7911686
YW		 5543 } else {
5544 *eax = 0;
5545 *ebx = 0;
5546 *ecx = 0;
5547 *edx = 0;
5548 }
5549 break;
c6dc6f63
AP		 5550 case 9:
5551 /* Direct Cache Access Information Leaf */
5552 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5553 *ebx = 0;
5554 *ecx = 0;
5555 *edx = 0;
5556 break;
5557 case 0xA:
5558 /* Architectural Performance Monitoring Leaf */
9337e3b6 5559 if (kvm_enabled() && cpu->enable_pmu) {
a60f24b5 5560 KVMState *s = cs->kvm_state;
a0fa8208
GN		 5561
5562 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5563 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5564 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5565 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
d6dcc558
SAGDR		 5566 } else if (hvf_enabled() && cpu->enable_pmu) {
5567 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5568 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5569 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5570 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
a0fa8208
GN		 5571 } else {
5572 *eax = 0;
5573 *ebx = 0;
5574 *ecx = 0;
5575 *edx = 0;
5576 }
c6dc6f63 5577 break;
5232d00a
RK		 5578 case 0xB:
5579 /* Extended Topology Enumeration Leaf */
5580 if (!cpu->enable_cpuid_0xb) {
5581 *eax = *ebx = *ecx = *edx = 0;
5582 break;
5583 }
5584
5585 *ecx = count & 0xff;
5586 *edx = cpu->apic_id;
5587
5588 switch (count) {
5589 case 0:
f20dec0b 5590 *eax = apicid_core_offset(&topo_info);
eab60fb9 5591 *ebx = cs->nr_threads;
5232d00a
RK		 5592 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5593 break;
5594 case 1:
f20dec0b 5595 *eax = apicid_pkg_offset(&topo_info);
eab60fb9 5596 *ebx = cs->nr_cores * cs->nr_threads;
5232d00a
RK		 5597 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5598 break;
5599 default:
5600 *eax = 0;
5601 *ebx = 0;
5602 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5603 }
5604
a94e1428
LX		 5605 assert(!(*eax & ~0x1f));
5606 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5607 break;
5608 case 0x1F:
5609 /* V2 Extended Topology Enumeration Leaf */
5610 if (env->nr_dies < 2) {
5611 *eax = *ebx = *ecx = *edx = 0;
5612 break;
5613 }
5614
5615 *ecx = count & 0xff;
5616 *edx = cpu->apic_id;
5617 switch (count) {
5618 case 0:
f20dec0b 5619 *eax = apicid_core_offset(&topo_info);
a94e1428
LX		 5620 *ebx = cs->nr_threads;
5621 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5622 break;
5623 case 1:
f20dec0b 5624 *eax = apicid_die_offset(&topo_info);
a94e1428
LX		 5625 *ebx = cs->nr_cores * cs->nr_threads;
5626 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5627 break;
5628 case 2:
f20dec0b 5629 *eax = apicid_pkg_offset(&topo_info);
a94e1428
LX		 5630 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5631 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5632 break;
5633 default:
5634 *eax = 0;
5635 *ebx = 0;
5636 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5637 }
5232d00a
RK		 5638 assert(!(*eax & ~0x1f));
5639 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5640 break;
2560f19f 5641 case 0xD: {
51e49430 5642 /* Processor Extended State */
2560f19f
PB		 5643 *eax = 0;
5644 *ebx = 0;
5645 *ecx = 0;
5646 *edx = 0;
19dc85db 5647 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
51e49430
SY		 5648 break;
5649 }
4928cd6d 5650
2560f19f 5651 if (count == 0) {
96193c22
EH		 5652 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5653 *eax = env->features[FEAT_XSAVE_COMP_LO];
5654 *edx = env->features[FEAT_XSAVE_COMP_HI];
76ecd7a5
BS		 5655 /*
5656 * The initial value of xcr0 and ebx == 0, On host without kvm
5657 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5658 * even through guest update xcr0, this will crash some legacy guest
5659 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5660 */
5661 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
2560f19f 5662 } else if (count == 1) {
0bb0b2d2 5663 *eax = env->features[FEAT_XSAVE];
f4f1110e 5664 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
96193c22
EH		 5665 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5666 const ExtSaveArea *esa = &x86_ext_save_areas[count];
33f373d7
LJ		 5667 *eax = esa->size;
5668 *ebx = esa->offset;
2560f19f 5669 }
51e49430
SY		 5670 }
5671 break;
2560f19f 5672 }
e37a5c7f
CP		 5673 case 0x14: {
5674 /* Intel Processor Trace Enumeration */
5675 *eax = 0;
5676 *ebx = 0;
5677 *ecx = 0;
5678 *edx = 0;
5679 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5680 !kvm_enabled()) {
5681 break;
5682 }
5683
5684 if (count == 0) {
5685 *eax = INTEL_PT_MAX_SUBLEAF;
5686 *ebx = INTEL_PT_MINIMAL_EBX;
5687 *ecx = INTEL_PT_MINIMAL_ECX;
5688 } else if (count == 1) {
5689 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5690 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5691 }
5692 break;
5693 }
1ce36bfe
DB		 5694 case 0x40000000:
5695 /*
5696 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5697 * set here, but we restrict to TCG none the less.
5698 */
5699 if (tcg_enabled() && cpu->expose_tcg) {
5700 memcpy(signature, "TCGTCGTCGTCG", 12);
5701 *eax = 0x40000001;
5702 *ebx = signature[0];
5703 *ecx = signature[1];
5704 *edx = signature[2];
5705 } else {
5706 *eax = 0;
5707 *ebx = 0;
5708 *ecx = 0;
5709 *edx = 0;
5710 }
5711 break;
5712 case 0x40000001:
5713 *eax = 0;
5714 *ebx = 0;
5715 *ecx = 0;
5716 *edx = 0;
5717 break;
c6dc6f63
AP		 5718 case 0x80000000:
5719 *eax = env->cpuid_xlevel;
5720 *ebx = env->cpuid_vendor1;
5721 *edx = env->cpuid_vendor2;
5722 *ecx = env->cpuid_vendor3;
5723 break;
5724 case 0x80000001:
5725 *eax = env->cpuid_version;
5726 *ebx = 0;
0514ef2f
EH		 5727 *ecx = env->features[FEAT_8000_0001_ECX];
5728 *edx = env->features[FEAT_8000_0001_EDX];
c6dc6f63
AP		 5729
5730 /* The Linux kernel checks for the CMPLegacy bit and
5731 * discards multiple thread information if it is set.
cb8d4c8f 5732 * So don't set it here for Intel to make Linux guests happy.
c6dc6f63 5733 */
ce3960eb 5734 if (cs->nr_cores * cs->nr_threads > 1) {
5eb2f7a4
EH		 5735 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5736 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5737 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
c6dc6f63
AP		 5738 *ecx |= 1 << 1; /* CmpLegacy bit */
5739 }
5740 }
c6dc6f63
AP		 5741 break;
5742 case 0x80000002:
5743 case 0x80000003:
5744 case 0x80000004:
5745 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5746 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5747 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5748 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5749 break;
5750 case 0x80000005:
5751 /* cache info (L1 cache) */
787aaf57
BC		 5752 if (cpu->cache_info_passthrough) {
5753 host_cpuid(index, 0, eax, ebx, ecx, edx);
5754 break;
5755 }
5e891bf8
EH		 5756 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
5757 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5758 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
5759 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5760 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5761 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
c6dc6f63
AP		 5762 break;
5763 case 0x80000006:
5764 /* cache info (L2 cache) */
787aaf57
BC		 5765 if (cpu->cache_info_passthrough) {
5766 host_cpuid(index, 0, eax, ebx, ecx, edx);
5767 break;
5768 }
5e891bf8
EH		 5769 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
5770 (L2_DTLB_2M_ENTRIES << 16) | \
5771 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
5772 (L2_ITLB_2M_ENTRIES);
5773 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
5774 (L2_DTLB_4K_ENTRIES << 16) | \
5775 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
5776 (L2_ITLB_4K_ENTRIES);
a9f27ea9
EH		 5777 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5778 cpu->enable_l3_cache ?
5779 env->cache_info_amd.l3_cache : NULL,
5780 ecx, edx);
c6dc6f63 5781 break;
303752a9
MT		 5782 case 0x80000007:
5783 *eax = 0;
5784 *ebx = 0;
5785 *ecx = 0;
5786 *edx = env->features[FEAT_8000_0007_EDX];
5787 break;
c6dc6f63
AP		 5788 case 0x80000008:
5789 /* virtual & phys address size in low 2 bytes. */
0514ef2f 5790 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6c7c3c21
KS		 5791 /* 64 bit processor */
5792 *eax = cpu->phys_bits; /* configurable physical bits */
5793 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5794 *eax |= 0x00003900; /* 57 bits virtual */
5795 } else {
5796 *eax |= 0x00003000; /* 48 bits virtual */
5797 }
c6dc6f63 5798 } else {
af45907a 5799 *eax = cpu->phys_bits;
c6dc6f63 5800 }
1b3420e1 5801 *ebx = env->features[FEAT_8000_0008_EBX];
c6dc6f63
AP		 5802 *ecx = 0;
5803 *edx = 0;
ce3960eb
AF		 5804 if (cs->nr_cores * cs->nr_threads > 1) {
5805 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
c6dc6f63
AP		 5806 }
5807 break;
5808 case 0x8000000A:
0514ef2f 5809 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
9f3fb565
EH		 5810 *eax = 0x00000001; /* SVM Revision */
5811 *ebx = 0x00000010; /* nr of ASIDs */
5812 *ecx = 0;
0514ef2f 5813 *edx = env->features[FEAT_SVM]; /* optional features */
9f3fb565
EH		 5814 } else {
5815 *eax = 0;
5816 *ebx = 0;
5817 *ecx = 0;
5818 *edx = 0;
5819 }
c6dc6f63 5820 break;
8f4202fb
BM		 5821 case 0x8000001D:
5822 *eax = 0;
a4e0b436
SL		 5823 if (cpu->cache_info_passthrough) {
5824 host_cpuid(index, count, eax, ebx, ecx, edx);
5825 break;
5826 }
8f4202fb
BM		 5827 switch (count) {
5828 case 0: /* L1 dcache info */
dd08ef03
BM		 5829 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5830 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5831 break;
5832 case 1: /* L1 icache info */
dd08ef03
BM		 5833 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5834 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5835 break;
5836 case 2: /* L2 cache info */
dd08ef03
BM		 5837 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5838 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5839 break;
5840 case 3: /* L3 cache info */
dd08ef03
BM		 5841 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5842 &topo_info, eax, ebx, ecx, edx);
8f4202fb
BM		 5843 break;
5844 default: /* end of info */
5845 *eax = *ebx = *ecx = *edx = 0;
5846 break;
5847 }
5848 break;
ed78467a
BM		 5849 case 0x8000001E:
5850 assert(cpu->core_id <= 255);
dd08ef03 5851 encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx);
ed78467a 5852 break;
b3baa152
BW		 5853 case 0xC0000000:
5854 *eax = env->cpuid_xlevel2;
5855 *ebx = 0;
5856 *ecx = 0;
5857 *edx = 0;
5858 break;
5859 case 0xC0000001:
5860 /* Support for VIA CPU's CPUID instruction */
5861 *eax = env->cpuid_version;
5862 *ebx = 0;
5863 *ecx = 0;
0514ef2f 5864 *edx = env->features[FEAT_C000_0001_EDX];
b3baa152
BW		 5865 break;
5866 case 0xC0000002:
5867 case 0xC0000003:
5868 case 0xC0000004:
5869 /* Reserved for the future, and now filled with zero */
5870 *eax = 0;
5871 *ebx = 0;
5872 *ecx = 0;
5873 *edx = 0;
5874 break;
6cb8f2a6
BS		 5875 case 0x8000001F:
5876 *eax = sev_enabled() ? 0x2 : 0;
5877 *ebx = sev_get_cbit_position();
5878 *ebx |= sev_get_reduced_phys_bits() << 6;
5879 *ecx = 0;
5880 *edx = 0;
5881 break;
c6dc6f63
AP		 5882 default:
5883 /* reserved values: zero */
5884 *eax = 0;
5885 *ebx = 0;
5886 *ecx = 0;
5887 *edx = 0;
5888 break;
5889 }
5890}
5fd2087a 5891
781c67ca 5892static void x86_cpu_reset(DeviceState *dev)
5fd2087a 5893{
781c67ca 5894 CPUState *s = CPU(dev);
5fd2087a
AF		 5895 X86CPU *cpu = X86_CPU(s);
5896 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5897 CPUX86State *env = &cpu->env;
a114d25d
RH		 5898 target_ulong cr4;
5899 uint64_t xcr0;
c1958aea
AF		 5900 int i;
5901
781c67ca 5902 xcc->parent_reset(dev);
5fd2087a 5903
5e992a8e 5904 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
c1958aea 5905
c1958aea
AF		 5906 env->old_exception = -1;
5907
5908 /* init to reset state */
5909
c1958aea
AF		 5910 env->hflags2 |= HF2_GIF_MASK;
5911
5912 cpu_x86_update_cr0(env, 0x60000010);
5913 env->a20_mask = ~0x0;
5914 env->smbase = 0x30000;
e13713db 5915 env->msr_smi_count = 0;
c1958aea
AF		 5916
5917 env->idt.limit = 0xffff;
5918 env->gdt.limit = 0xffff;
5919 env->ldt.limit = 0xffff;
5920 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5921 env->tr.limit = 0xffff;
5922 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5923
5924 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5925 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5926 DESC_R_MASK | DESC_A_MASK);
5927 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5928 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5929 DESC_A_MASK);
5930 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5931 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5932 DESC_A_MASK);
5933 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5934 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5935 DESC_A_MASK);
5936 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5937 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5938 DESC_A_MASK);
5939 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5940 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5941 DESC_A_MASK);
5942
5943 env->eip = 0xfff0;
5944 env->regs[R_EDX] = env->cpuid_version;
5945
5946 env->eflags = 0x2;
5947
5948 /* FPU init */
5949 for (i = 0; i < 8; i++) {
5950 env->fptags[i] = 1;
5951 }
5bde1407 5952 cpu_set_fpuc(env, 0x37f);
c1958aea
AF		 5953
5954 env->mxcsr = 0x1f80;
a114d25d
RH		 5955 /* All units are in INIT state. */
5956 env->xstate_bv = 0;
c1958aea
AF		 5957
5958 env->pat = 0x0007040600070406ULL;
5959 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4cfd7bab
WL		 5960 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5961 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5962 }
c1958aea
AF		 5963
5964 memset(env->dr, 0, sizeof(env->dr));
5965 env->dr[6] = DR6_FIXED_1;
5966 env->dr[7] = DR7_FIXED_1;
b3310ab3 5967 cpu_breakpoint_remove_all(s, BP_CPU);
75a34036 5968 cpu_watchpoint_remove_all(s, BP_CPU);
dd673288 5969
a114d25d 5970 cr4 = 0;
cfc3b074 5971 xcr0 = XSTATE_FP_MASK;
a114d25d
RH		 5972
5973#ifdef CONFIG_USER_ONLY
5974 /* Enable all the features for user-mode. */
5975 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
cfc3b074 5976 xcr0 |= XSTATE_SSE_MASK;
a114d25d 5977 }
0f70ed47
PB		 5978 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
5979 const ExtSaveArea *esa = &x86_ext_save_areas[i];
9646f492 5980 if (env->features[esa->feature] & esa->bits) {
0f70ed47
PB		 5981 xcr0 |= 1ull << i;
5982 }
a114d25d 5983 }
0f70ed47 5984
a114d25d
RH		 5985 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
5986 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
5987 }
07929f2a
RH		 5988 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
5989 cr4 |= CR4_FSGSBASE_MASK;
5990 }
a114d25d
RH		 5991#endif
5992
5993 env->xcr0 = xcr0;
5994 cpu_x86_update_cr4(env, cr4);
0522604b 5995
9db2efd9
AW		 5996 /*
5997 * SDM 11.11.5 requires:
5998 * - IA32_MTRR_DEF_TYPE MSR.E = 0
5999 * - IA32_MTRR_PHYSMASKn.V = 0
6000 * All other bits are undefined. For simplification, zero it all.
6001 */
6002 env->mtrr_deftype = 0;
6003 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6004 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6005
b7394c83 6006 env->interrupt_injected = -1;
fd13f23b
LA		 6007 env->exception_nr = -1;
6008 env->exception_pending = 0;
6009 env->exception_injected = 0;
6010 env->exception_has_payload = false;
6011 env->exception_payload = 0;
b7394c83 6012 env->nmi_injected = false;
dd673288
IM		 6013#if !defined(CONFIG_USER_ONLY)
6014 /* We hard-wire the BSP to the first CPU. */
9cb11fd7 6015 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
dd673288 6016
259186a7 6017 s->halted = !cpu_is_bsp(cpu);
50a2c6e5
PB		 6018
6019 if (kvm_enabled()) {
6020 kvm_arch_reset_vcpu(cpu);
6021 }
d6dcc558
SAGDR		 6022 else if (hvf_enabled()) {
6023 hvf_reset_vcpu(s);
6024 }
dd673288 6025#endif
5fd2087a
AF		 6026}
6027
dd673288
IM		 6028#ifndef CONFIG_USER_ONLY
6029bool cpu_is_bsp(X86CPU *cpu)
6030{
02e51483 6031 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
dd673288 6032}
65dee380
IM		 6033
6034/* TODO: remove me, when reset over QOM tree is implemented */
6035static void x86_cpu_machine_reset_cb(void *opaque)
6036{
6037 X86CPU *cpu = opaque;
6038 cpu_reset(CPU(cpu));
6039}
dd673288
IM		 6040#endif
6041
de024815
AF		 6042static void mce_init(X86CPU *cpu)
6043{
6044 CPUX86State *cenv = &cpu->env;
6045 unsigned int bank;
6046
6047 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
0514ef2f 6048 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
de024815 6049 (CPUID_MCE | CPUID_MCA)) {
87f8b626
AR		 6050 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6051 (cpu->enable_lmce ? MCG_LMCE_P : 0);
de024815
AF		 6052 cenv->mcg_ctl = ~(uint64_t)0;
6053 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6054 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6055 }
6056 }
6057}
6058
bdeec802 6059#ifndef CONFIG_USER_ONLY
2f114315 6060APICCommonClass *apic_get_class(void)
bdeec802 6061{
bdeec802
IM		 6062 const char *apic_type = "apic";
6063
d6dcc558 6064 /* TODO: in-kernel irqchip for hvf */
15eafc2e 6065 if (kvm_apic_in_kernel()) {
bdeec802
IM		 6066 apic_type = "kvm-apic";
6067 } else if (xen_enabled()) {
6068 apic_type = "xen-apic";
6069 }
6070
2f114315
RK		 6071 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6072}
6073
6074static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6075{
6076 APICCommonState *apic;
6077 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6078
3c75e12e 6079 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
bdeec802 6080
6816b1b3
IM		 6081 object_property_add_child(OBJECT(cpu), "lapic",
6082 OBJECT(cpu->apic_state), &error_abort);
67e55caa 6083 object_unref(OBJECT(cpu->apic_state));
6816b1b3 6084
33d7a288 6085 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
bdeec802 6086 /* TODO: convert to link<> */
02e51483 6087 apic = APIC_COMMON(cpu->apic_state);
60671e58 6088 apic->cpu = cpu;
8d42d2d3 6089 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
d3c64d6a
IM		 6090}
6091
6092static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6093{
8d42d2d3
CF		 6094 APICCommonState *apic;
6095 static bool apic_mmio_map_once;
6096
02e51483 6097 if (cpu->apic_state == NULL) {
d3c64d6a
IM		 6098 return;
6099 }
6e8e2651
MA		 6100 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
6101 errp);
8d42d2d3
CF		 6102
6103 /* Map APIC MMIO area */
6104 apic = APIC_COMMON(cpu->apic_state);
6105 if (!apic_mmio_map_once) {
6106 memory_region_add_subregion_overlap(get_system_memory(),
6107 apic->apicbase &
6108 MSR_IA32_APICBASE_BASE,
6109 &apic->io_memory,
6110 0x1000);
6111 apic_mmio_map_once = true;
6112 }
bdeec802 6113}
f809c605
PB		 6114
6115static void x86_cpu_machine_done(Notifier *n, void *unused)
6116{
6117 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6118 MemoryRegion *smram =
6119 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6120
6121 if (smram) {
6122 cpu->smram = g_new(MemoryRegion, 1);
6123 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6124 smram, 0, 1ull << 32);
f8c45c65 6125 memory_region_set_enabled(cpu->smram, true);
f809c605
PB		 6126 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6127 }
6128}
d3c64d6a
IM		 6129#else
6130static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6131{
6132}
bdeec802
IM		 6133#endif
6134
11f6fee5
DDAG		 6135/* Note: Only safe for use on x86(-64) hosts */
6136static uint32_t x86_host_phys_bits(void)
6137{
6138 uint32_t eax;
6139 uint32_t host_phys_bits;
6140
6141 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6142 if (eax >= 0x80000008) {
6143 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6144 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6145 * at 23:16 that can specify a maximum physical address bits for
6146 * the guest that can override this value; but I've not seen
6147 * anything with that set.
6148 */
6149 host_phys_bits = eax & 0xff;
6150 } else {
6151 /* It's an odd 64 bit machine that doesn't have the leaf for
6152 * physical address bits; fall back to 36 that's most older
6153 * Intel.
6154 */
6155 host_phys_bits = 36;
6156 }
6157
6158 return host_phys_bits;
6159}
e48638fd 6160
c39c0edf
EH		 6161static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6162{
6163 if (*min < value) {
6164 *min = value;
6165 }
6166}
6167
6168/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6169static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6170{
6171 CPUX86State *env = &cpu->env;
6172 FeatureWordInfo *fi = &feature_word_info[w];
07585923 6173 uint32_t eax = fi->cpuid.eax;
c39c0edf
EH		 6174 uint32_t region = eax & 0xF0000000;
6175
07585923 6176 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
c39c0edf
EH		 6177 if (!env->features[w]) {
6178 return;
6179 }
6180
6181 switch (region) {
6182 case 0x00000000:
6183 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6184 break;
6185 case 0x80000000:
6186 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6187 break;
6188 case 0xC0000000:
6189 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6190 break;
6191 }
80db491d
JL		 6192
6193 if (eax == 7) {
6194 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6195 fi->cpuid.ecx);
6196 }
c39c0edf
EH		 6197}
6198
2ca8a8be
EH		 6199/* Calculate XSAVE components based on the configured CPU feature flags */
6200static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6201{
6202 CPUX86State *env = &cpu->env;
6203 int i;
96193c22 6204 uint64_t mask;
2ca8a8be
EH		 6205
6206 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6207 return;
6208 }
6209
e3c9022b
EH		 6210 mask = 0;
6211 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2ca8a8be
EH		 6212 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6213 if (env->features[esa->feature] & esa->bits) {
96193c22 6214 mask |= (1ULL << i);
2ca8a8be
EH		 6215 }
6216 }
6217
96193c22
EH		 6218 env->features[FEAT_XSAVE_COMP_LO] = mask;
6219 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
2ca8a8be
EH		 6220}
6221
b8d834a0
EH		 6222/***** Steps involved on loading and filtering CPUID data
6223 *
6224 * When initializing and realizing a CPU object, the steps
6225 * involved in setting up CPUID data are:
6226 *
6227 * 1) Loading CPU model definition (X86CPUDefinition). This is
dcafd1ef 6228 * implemented by x86_cpu_load_model() and should be completely
b8d834a0
EH		 6229 * transparent, as it is done automatically by instance_init.
6230 * No code should need to look at X86CPUDefinition structs
6231 * outside instance_init.
6232 *
6233 * 2) CPU expansion. This is done by realize before CPUID
6234 * filtering, and will make sure host/accelerator data is
6235 * loaded for CPU models that depend on host capabilities
6236 * (e.g. "host"). Done by x86_cpu_expand_features().
6237 *
6238 * 3) CPUID filtering. This initializes extra data related to
6239 * CPUID, and checks if the host supports all capabilities
6240 * required by the CPU. Runnability of a CPU model is
6241 * determined at this step. Done by x86_cpu_filter_features().
6242 *
6243 * Some operations don't require all steps to be performed.
6244 * More precisely:
6245 *
6246 * - CPU instance creation (instance_init) will run only CPU
6247 * model loading. CPU expansion can't run at instance_init-time
6248 * because host/accelerator data may be not available yet.
6249 * - CPU realization will perform both CPU model expansion and CPUID
6250 * filtering, and return an error in case one of them fails.
6251 * - query-cpu-definitions needs to run all 3 steps. It needs
6252 * to run CPUID filtering, as the 'unavailable-features'
6253 * field is set based on the filtering results.
6254 * - The query-cpu-model-expansion QMP command only needs to run
6255 * CPU model loading and CPU expansion. It should not filter
6256 * any CPUID data based on host capabilities.
6257 */
6258
6259/* Expand CPU configuration data, based on configured features
6260 * and host/accelerator capabilities when appropriate.
6261 */
6262static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
7a059953 6263{
b34d12d1 6264 CPUX86State *env = &cpu->env;
dc15c051 6265 FeatureWord w;
99e24dbd 6266 int i;
2fae0d96 6267 GList *l;
41f3d4d6 6268 Error *local_err = NULL;
9886e834 6269
99e24dbd
PB		 6270 for (l = plus_features; l; l = l->next) {
6271 const char *prop = l->data;
6272 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
6273 if (local_err) {
6274 goto out;
6275 }
6276 }
6277
6278 for (l = minus_features; l; l = l->next) {
6279 const char *prop = l->data;
6280 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
6281 if (local_err) {
6282 goto out;
6283 }
6284 }
6285
d4a606b3
EH		 6286 /*TODO: Now cpu->max_features doesn't overwrite features
6287 * set using QOM properties, and we can convert
dc15c051
IM		 6288 * plus_features & minus_features to global properties
6289 * inside x86_cpu_parse_featurestr() too.
6290 */
44bd8e53 6291 if (cpu->max_features) {
dc15c051 6292 for (w = 0; w < FEATURE_WORDS; w++) {
d4a606b3
EH		 6293 /* Override only features that weren't set explicitly
6294 * by the user.
6295 */
6296 env->features[w] |=
6297 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
0d914f39
EH		 6298 ~env->user_features[w] & \
6299 ~feature_word_info[w].no_autoenable_flags;
dc15c051
IM		 6300 }
6301 }
6302
99e24dbd
PB		 6303 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6304 FeatureDep *d = &feature_dependencies[i];
6305 if (!(env->features[d->from.index] & d->from.mask)) {
ede146c2 6306 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
2fae0d96 6307
99e24dbd
PB		 6308 /* Not an error unless the dependent feature was added explicitly. */
6309 mark_unavailable_features(cpu, d->to.index,
6310 unavailable_features & env->user_features[d->to.index],
6311 "This feature depends on other features that were not requested");
6312
6313 env->user_features[d->to.index] |= unavailable_features;
6314 env->features[d->to.index] &= ~unavailable_features;
2fae0d96 6315 }
dc15c051
IM		 6316 }
6317
aec661de
EH		 6318 if (!kvm_enabled() || !cpu->expose_kvm) {
6319 env->features[FEAT_KVM] = 0;
6320 }
6321
2ca8a8be 6322 x86_cpu_enable_xsave_components(cpu);
c39c0edf
EH		 6323
6324 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6325 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6326 if (cpu->full_cpuid_auto_level) {
6327 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6328 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6329 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6330 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
80db491d 6331 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
c39c0edf
EH		 6332 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6333 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6334 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
1b3420e1 6335 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
c39c0edf
EH		 6336 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6337 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6338 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
f24c3a79
LK		 6339
6340 /* Intel Processor Trace requires CPUID[0x14] */
6341 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6342 kvm_enabled() && cpu->intel_pt_auto_level) {
6343 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6344 }
6345
a94e1428
LX		 6346 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6347 if (env->nr_dies > 1) {
6348 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6349 }
6350
0c3d7c00
EH		 6351 /* SVM requires CPUID[0x8000000A] */
6352 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6353 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6354 }
6cb8f2a6
BS		 6355
6356 /* SEV requires CPUID[0x8000001F] */
6357 if (sev_enabled()) {
6358 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6359 }
c39c0edf
EH		 6360 }
6361
6362 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
80db491d
JL		 6363 if (env->cpuid_level_func7 == UINT32_MAX) {
6364 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6365 }
c39c0edf
EH		 6366 if (env->cpuid_level == UINT32_MAX) {
6367 env->cpuid_level = env->cpuid_min_level;
6368 }
6369 if (env->cpuid_xlevel == UINT32_MAX) {
6370 env->cpuid_xlevel = env->cpuid_min_xlevel;
6371 }
6372 if (env->cpuid_xlevel2 == UINT32_MAX) {
6373 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
b34d12d1 6374 }
7a059953 6375
41f3d4d6
EH		 6376out:
6377 if (local_err != NULL) {
6378 error_propagate(errp, local_err);
6379 }
6380}
6381
b8d834a0
EH		 6382/*
6383 * Finishes initialization of CPUID data, filters CPU feature
6384 * words based on host availability of each feature.
6385 *
6386 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6387 */
245edd0c 6388static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
b8d834a0
EH		 6389{
6390 CPUX86State *env = &cpu->env;
6391 FeatureWord w;
245edd0c
PB		 6392 const char *prefix = NULL;
6393
6394 if (verbose) {
6395 prefix = accel_uses_host_cpuid()
6396 ? "host doesn't support requested feature"
6397 : "TCG doesn't support requested feature";
6398 }
b8d834a0
EH		 6399
6400 for (w = 0; w < FEATURE_WORDS; w++) {
ede146c2 6401 uint64_t host_feat =
b8d834a0 6402 x86_cpu_get_supported_feature_word(w, false);
ede146c2
PB		 6403 uint64_t requested_features = env->features[w];
6404 uint64_t unavailable_features = requested_features & ~host_feat;
245edd0c 6405 mark_unavailable_features(cpu, w, unavailable_features, prefix);
b8d834a0
EH		 6406 }
6407
e37a5c7f
CP		 6408 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6409 kvm_enabled()) {
6410 KVMState *s = CPU(cpu)->kvm_state;
6411 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6412 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6413 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6414 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6415 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6416
6417 if (!eax_0 ||
6418 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6419 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6420 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6421 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6422 INTEL_PT_ADDR_RANGES_NUM) ||
6423 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
c078ca96
LK		 6424 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6425 (ecx_0 & INTEL_PT_IP_LIP)) {
e37a5c7f
CP		 6426 /*
6427 * Processor Trace capabilities aren't configurable, so if the
6428 * host can't emulate the capabilities we report on
6429 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6430 */
245edd0c 6431 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
e37a5c7f
CP		 6432 }
6433 }
b8d834a0
EH		 6434}
6435
41f3d4d6
EH		 6436static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6437{
6438 CPUState *cs = CPU(dev);
6439 X86CPU *cpu = X86_CPU(dev);
6440 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6441 CPUX86State *env = &cpu->env;
6442 Error *local_err = NULL;
6443 static bool ht_warned;
6444
2266d443
MT		 6445 if (xcc->host_cpuid_required) {
6446 if (!accel_uses_host_cpuid()) {
88703ce2 6447 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
2266d443 6448 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2266d443
MT		 6449 goto out;
6450 }
be02cda3 6451 }
2266d443 6452
be02cda3 6453 if (cpu->max_features && accel_uses_host_cpuid()) {
2266d443
MT		 6454 if (enable_cpu_pm) {
6455 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6456 &cpu->mwait.ecx, &cpu->mwait.edx);
6457 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6458 }
32c87d70
PB		 6459 if (kvm_enabled() && cpu->ucode_rev == 0) {
6460 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6461 MSR_IA32_UCODE_REV);
6462 }
41f3d4d6
EH		 6463 }
6464
4e45aff3
PB		 6465 if (cpu->ucode_rev == 0) {
6466 /* The default is the same as KVM's. */
6467 if (IS_AMD_CPU(env)) {
6468 cpu->ucode_rev = 0x01000065;
6469 } else {
6470 cpu->ucode_rev = 0x100000000ULL;
6471 }
6472 }
6473
2266d443
MT		 6474 /* mwait extended info: needed for Core compatibility */
6475 /* We always wake on interrupt even if host does not have the capability */
6476 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6477
41f3d4d6
EH		 6478 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6479 error_setg(errp, "apic-id property was not initialized properly");
6480 return;
6481 }
6482
b8d834a0 6483 x86_cpu_expand_features(cpu, &local_err);
41f3d4d6
EH		 6484 if (local_err) {
6485 goto out;
6486 }
6487
245edd0c
PB		 6488 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6489
6490 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6491 error_setg(&local_err,
6492 accel_uses_host_cpuid() ?
6493 "Host doesn't support requested features" :
6494 "TCG doesn't support requested features");
6495 goto out;
9997cf7b
EH		 6496 }
6497
9b15cd9e
IM		 6498 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6499 * CPUID[1].EDX.
6500 */
e48638fd 6501 if (IS_AMD_CPU(env)) {
0514ef2f
EH		 6502 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6503 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
9b15cd9e
IM		 6504 & CPUID_EXT2_AMD_ALIASES);
6505 }
6506
11f6fee5
DDAG		 6507 /* For 64bit systems think about the number of physical bits to present.
6508 * ideally this should be the same as the host; anything other than matching
6509 * the host can cause incorrect guest behaviour.
6510 * QEMU used to pick the magic value of 40 bits that corresponds to
6511 * consumer AMD devices but nothing else.
6512 */
af45907a 6513 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
d6dcc558 6514 if (accel_uses_host_cpuid()) {
11f6fee5
DDAG		 6515 uint32_t host_phys_bits = x86_host_phys_bits();
6516 static bool warned;
6517
11f6fee5
DDAG		 6518 /* Print a warning if the user set it to a value that's not the
6519 * host value.
6520 */
6521 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6522 !warned) {
3dc6f869
AF		 6523 warn_report("Host physical bits (%u)"
6524 " does not match phys-bits property (%u)",
6525 host_phys_bits, cpu->phys_bits);
11f6fee5
DDAG		 6526 warned = true;
6527 }
6528
fea30652
EH		 6529 if (cpu->host_phys_bits) {
6530 /* The user asked for us to use the host physical bits */
6531 cpu->phys_bits = host_phys_bits;
6532 if (cpu->host_phys_bits_limit &&
6533 cpu->phys_bits > cpu->host_phys_bits_limit) {
6534 cpu->phys_bits = cpu->host_phys_bits_limit;
6535 }
6536 }
6537
11f6fee5
DDAG		 6538 if (cpu->phys_bits &&
6539 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6540 cpu->phys_bits < 32)) {
af45907a
DDAG		 6541 error_setg(errp, "phys-bits should be between 32 and %u "
6542 " (but is %u)",
6543 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6544 return;
6545 }
6546 } else {
11f6fee5 6547 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
af45907a
DDAG		 6548 error_setg(errp, "TCG only supports phys-bits=%u",
6549 TCG_PHYS_ADDR_BITS);
6550 return;
6551 }
6552 }
11f6fee5
DDAG		 6553 /* 0 means it was not explicitly set by the user (or by machine
6554 * compat_props or by the host code above). In this case, the default
6555 * is the value used by TCG (40).
6556 */
6557 if (cpu->phys_bits == 0) {
6558 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6559 }
af45907a
DDAG		 6560 } else {
6561 /* For 32 bit systems don't use the user set value, but keep
6562 * phys_bits consistent with what we tell the guest.
6563 */
6564 if (cpu->phys_bits != 0) {
6565 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6566 return;
6567 }
fefb41bf 6568
af45907a
DDAG		 6569 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6570 cpu->phys_bits = 36;
6571 } else {
6572 cpu->phys_bits = 32;
6573 }
6574 }
a9f27ea9
EH		 6575
6576 /* Cache information initialization */
6577 if (!cpu->legacy_cache) {
dcafd1ef 6578 if (!xcc->model || !xcc->model->cpudef->cache_info) {
88703ce2 6579 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
a9f27ea9
EH		 6580 error_setg(errp,
6581 "CPU model '%s' doesn't support legacy-cache=off", name);
a9f27ea9
EH		 6582 return;
6583 }
6584 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
dcafd1ef 6585 *xcc->model->cpudef->cache_info;
a9f27ea9
EH		 6586 } else {
6587 /* Build legacy cache information */
6588 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6589 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6590 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6591 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6592
6593 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6594 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6595 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6596 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6597
6598 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6599 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6600 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6601 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6602 }
6603
6604
ce5b1bbf
LV		 6605 cpu_exec_realizefn(cs, &local_err);
6606 if (local_err != NULL) {
6607 error_propagate(errp, local_err);
6608 return;
6609 }
42ecabaa 6610
65dee380 6611#ifndef CONFIG_USER_ONLY
0e11fc69 6612 MachineState *ms = MACHINE(qdev_get_machine());
65dee380 6613 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
bdeec802 6614
0e11fc69 6615 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
d3c64d6a 6616 x86_cpu_apic_create(cpu, &local_err);
2b6f294c 6617 if (local_err != NULL) {
4dc1f449 6618 goto out;
bdeec802
IM		 6619 }
6620 }
65dee380
IM		 6621#endif
6622
7a059953 6623 mce_init(cpu);
2001d0cd
PB		 6624
6625#ifndef CONFIG_USER_ONLY
6626 if (tcg_enabled()) {
f809c605 6627 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
2001d0cd 6628 cpu->cpu_as_root = g_new(MemoryRegion, 1);
f809c605
PB		 6629
6630 /* Outer container... */
6631 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
2001d0cd 6632 memory_region_set_enabled(cpu->cpu_as_root, true);
f809c605
PB		 6633
6634 /* ... with two regions inside: normal system memory with low
6635 * priority, and...
6636 */
6637 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6638 get_system_memory(), 0, ~0ull);
6639 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6640 memory_region_set_enabled(cpu->cpu_as_mem, true);
f8c45c65
PB		 6641
6642 cs->num_ases = 2;
80ceb07a
PX		 6643 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6644 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
f809c605
PB		 6645
6646 /* ... SMRAM with higher priority, linked from /machine/smram. */
6647 cpu->machine_done.notify = x86_cpu_machine_done;
6648 qemu_add_machine_init_done_notifier(&cpu->machine_done);
2001d0cd
PB		 6649 }
6650#endif
6651
14a10fc3 6652 qemu_init_vcpu(cs);
d3c64d6a 6653
6b2942f9
BM		 6654 /*
6655 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6656 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6657 * based on inputs (sockets,cores,threads), it is still better to give
e48638fd
WH		 6658 * users a warning.
6659 *
6660 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6661 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6662 */
0765691e
MA		 6663 if (IS_AMD_CPU(env) &&
6664 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6665 cs->nr_threads > 1 && !ht_warned) {
6666 warn_report("This family of AMD CPU doesn't support "
6667 "hyperthreading(%d)",
6668 cs->nr_threads);
6669 error_printf("Please configure -smp options properly"
6670 " or try enabling topoext feature.\n");
6671 ht_warned = true;
e48638fd
WH		 6672 }
6673
d3c64d6a
IM		 6674 x86_cpu_apic_realize(cpu, &local_err);
6675 if (local_err != NULL) {
6676 goto out;
6677 }
14a10fc3 6678 cpu_reset(cs);
2b6f294c 6679
4dc1f449 6680 xcc->parent_realize(dev, &local_err);
2001d0cd 6681
4dc1f449
IM		 6682out:
6683 if (local_err != NULL) {
6684 error_propagate(errp, local_err);
6685 return;
6686 }
7a059953
AF		 6687}
6688
c884776e
IM		 6689static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
6690{
6691 X86CPU *cpu = X86_CPU(dev);
7bbc124e
LV		 6692 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6693 Error *local_err = NULL;
c884776e
IM		 6694
6695#ifndef CONFIG_USER_ONLY
6696 cpu_remove_sync(CPU(dev));
6697 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6698#endif
6699
6700 if (cpu->apic_state) {
6701 object_unparent(OBJECT(cpu->apic_state));
6702 cpu->apic_state = NULL;
6703 }
7bbc124e
LV		 6704
6705 xcc->parent_unrealize(dev, &local_err);
6706 if (local_err != NULL) {
6707 error_propagate(errp, local_err);
6708 return;
6709 }
c884776e
IM		 6710}
6711
38e5c119 6712typedef struct BitProperty {
a7b0ffac 6713 FeatureWord w;
ede146c2 6714 uint64_t mask;
38e5c119
EH		 6715} BitProperty;
6716
d7bce999
EB		 6717static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6718 void *opaque, Error **errp)
38e5c119 6719{
a7b0ffac 6720 X86CPU *cpu = X86_CPU(obj);
38e5c119 6721 BitProperty *fp = opaque;
ede146c2 6722 uint64_t f = cpu->env.features[fp->w];
a7b0ffac 6723 bool value = (f & fp->mask) == fp->mask;
51e72bc1 6724 visit_type_bool(v, name, &value, errp);
38e5c119
EH		 6725}
6726
d7bce999
EB		 6727static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6728 void *opaque, Error **errp)
38e5c119
EH		 6729{
6730 DeviceState *dev = DEVICE(obj);
a7b0ffac 6731 X86CPU *cpu = X86_CPU(obj);
38e5c119
EH		 6732 BitProperty *fp = opaque;
6733 Error *local_err = NULL;
6734 bool value;
6735
6736 if (dev->realized) {
6737 qdev_prop_set_after_realize(dev, name, errp);
6738 return;
6739 }
6740
51e72bc1 6741 visit_type_bool(v, name, &value, &local_err);
38e5c119
EH		 6742 if (local_err) {
6743 error_propagate(errp, local_err);
6744 return;
6745 }
6746
6747 if (value) {
a7b0ffac 6748 cpu->env.features[fp->w] |= fp->mask;
38e5c119 6749 } else {
a7b0ffac 6750 cpu->env.features[fp->w] &= ~fp->mask;
38e5c119 6751 }
d4a606b3 6752 cpu->env.user_features[fp->w] |= fp->mask;
38e5c119
EH		 6753}
6754
6755static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6756 void *opaque)
6757{
6758 BitProperty *prop = opaque;
6759 g_free(prop);
6760}
6761
6762/* Register a boolean property to get/set a single bit in a uint32_t field.
6763 *
6764 * The same property name can be registered multiple times to make it affect
6765 * multiple bits in the same FeatureWord. In that case, the getter will return
6766 * true only if all bits are set.
6767 */
6768static void x86_cpu_register_bit_prop(X86CPU *cpu,
6769 const char *prop_name,
a7b0ffac 6770 FeatureWord w,
38e5c119
EH		 6771 int bitnr)
6772{
6773 BitProperty *fp;
6774 ObjectProperty *op;
ede146c2 6775 uint64_t mask = (1ULL << bitnr);
38e5c119
EH		 6776
6777 op = object_property_find(OBJECT(cpu), prop_name, NULL);
6778 if (op) {
6779 fp = op->opaque;
a7b0ffac 6780 assert(fp->w == w);
38e5c119
EH		 6781 fp->mask |= mask;
6782 } else {
6783 fp = g_new0(BitProperty, 1);
a7b0ffac 6784 fp->w = w;
38e5c119
EH		 6785 fp->mask = mask;
6786 object_property_add(OBJECT(cpu), prop_name, "bool",
6787 x86_cpu_get_bit_prop,
6788 x86_cpu_set_bit_prop,
6789 x86_cpu_release_bit_prop, fp, &error_abort);
6790 }
6791}
6792
6793static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6794 FeatureWord w,
6795 int bitnr)
6796{
38e5c119 6797 FeatureWordInfo *fi = &feature_word_info[w];
16d2fcaa 6798 const char *name = fi->feat_names[bitnr];
38e5c119 6799
16d2fcaa 6800 if (!name) {
38e5c119
EH		 6801 return;
6802 }
6803
fc7dfd20
EH		 6804 /* Property names should use "-" instead of "_".
6805 * Old names containing underscores are registered as aliases
6806 * using object_property_add_alias()
6807 */
16d2fcaa
EH		 6808 assert(!strchr(name, '_'));
6809 /* aliases don't use "|" delimiters anymore, they are registered
6810 * manually using object_property_add_alias() */
6811 assert(!strchr(name, '|'));
a7b0ffac 6812 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
38e5c119
EH		 6813}
6814
d187e08d
AN		 6815static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6816{
6817 X86CPU *cpu = X86_CPU(cs);
6818 CPUX86State *env = &cpu->env;
6819 GuestPanicInformation *panic_info = NULL;
6820
5e953812 6821 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
d187e08d
AN		 6822 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6823
e8ed97a6 6824 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
d187e08d 6825
5e953812 6826 assert(HV_CRASH_PARAMS >= 5);
e8ed97a6
AN		 6827 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6828 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6829 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6830 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6831 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
d187e08d
AN		 6832 }
6833
6834 return panic_info;
6835}
6836static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6837 const char *name, void *opaque,
6838 Error **errp)
6839{
6840 CPUState *cs = CPU(obj);
6841 GuestPanicInformation *panic_info;
6842
6843 if (!cs->crash_occurred) {
6844 error_setg(errp, "No crash occured");
6845 return;
6846 }
6847
6848 panic_info = x86_cpu_get_crash_info(cs);
6849 if (panic_info == NULL) {
6850 error_setg(errp, "No crash information");
6851 return;
6852 }
6853
6854 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6855 errp);
6856 qapi_free_GuestPanicInformation(panic_info);
6857}
6858
de024815
AF		 6859static void x86_cpu_initfn(Object *obj)
6860{
6861 X86CPU *cpu = X86_CPU(obj);
d940ee9b 6862 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
de024815 6863 CPUX86State *env = &cpu->env;
38e5c119 6864 FeatureWord w;
de024815 6865
c26ae610 6866 env->nr_dies = 1;
c24a41bb 6867 env->nr_nodes = 1;
7506ed90 6868 cpu_set_cpustate_pointers(cpu);
71ad61d3
AF		 6869
6870 object_property_add(obj, "family", "int",
95b8519d 6871 x86_cpuid_version_get_family,
71ad61d3 6872 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 6873 object_property_add(obj, "model", "int",
67e30c83 6874 x86_cpuid_version_get_model,
c5291a4f 6875 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 6876 object_property_add(obj, "stepping", "int",
35112e41 6877 x86_cpuid_version_get_stepping,
036e2222 6878 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
d480e1af
AF		 6879 object_property_add_str(obj, "vendor",
6880 x86_cpuid_get_vendor,
6881 x86_cpuid_set_vendor, NULL);
938d4c25 6882 object_property_add_str(obj, "model-id",
63e886eb 6883 x86_cpuid_get_model_id,
938d4c25 6884 x86_cpuid_set_model_id, NULL);
89e48965
AF		 6885 object_property_add(obj, "tsc-frequency", "int",
6886 x86_cpuid_get_tsc_freq,
6887 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
8e8aba50
EH		 6888 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6889 x86_cpu_get_feature_words,
7e5292b5
EH		 6890 NULL, NULL, (void *)env->features, NULL);
6891 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6892 x86_cpu_get_feature_words,
6893 NULL, NULL, (void *)cpu->filtered_features, NULL);
506174bf
EH		 6894 /*
6895 * The "unavailable-features" property has the same semantics as
6896 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6897 * QMP command: they list the features that would have prevented the
6898 * CPU from running if the "enforce" flag was set.
6899 */
6900 object_property_add(obj, "unavailable-features", "strList",
6901 x86_cpu_get_unavailable_features,
6902 NULL, NULL, NULL, &error_abort);
71ad61d3 6903
d187e08d
AN		 6904 object_property_add(obj, "crash-information", "GuestPanicInformation",
6905 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
6906
38e5c119
EH		 6907 for (w = 0; w < FEATURE_WORDS; w++) {
6908 int bitnr;
6909
ede146c2 6910 for (bitnr = 0; bitnr < 64; bitnr++) {
38e5c119
EH		 6911 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6912 }
6913 }
6914
16d2fcaa
EH		 6915 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
6916 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
6917 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
6918 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
6919 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
6920 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
6921 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
6922
54b8dc7c
EH		 6923 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
6924 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
6925 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
6926 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
6927 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
6928 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
6929 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
6930 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
6931 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
6932 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
6933 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
6934 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
6935 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
6936 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
d645e132
MT		 6937 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control",
6938 &error_abort);
54b8dc7c
EH		 6939 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
6940 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
6941 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
6942 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
6943 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
6944 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
6945 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
6946
dcafd1ef
EH		 6947 if (xcc->model) {
6948 x86_cpu_load_model(cpu, xcc->model, &error_abort);
0bacd8b3 6949 }
de024815
AF		 6950}
6951
997395d3
IM		 6952static int64_t x86_cpu_get_arch_id(CPUState *cs)
6953{
6954 X86CPU *cpu = X86_CPU(cs);
997395d3 6955
7e72a45c 6956 return cpu->apic_id;
997395d3
IM		 6957}
6958
444d5590
AF		 6959static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6960{
6961 X86CPU *cpu = X86_CPU(cs);
6962
6963 return cpu->env.cr[0] & CR0_PG_MASK;
6964}
6965
f45748f1
AF		 6966static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6967{
6968 X86CPU *cpu = X86_CPU(cs);
6969
6970 cpu->env.eip = value;
6971}
6972
bdf7ae5b
AF		 6973static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
6974{
6975 X86CPU *cpu = X86_CPU(cs);
6976
6977 cpu->env.eip = tb->pc - tb->cs_base;
6978}
6979
92d5f1a4 6980int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
8c2e1b00
AF		 6981{
6982 X86CPU *cpu = X86_CPU(cs);
6983 CPUX86State *env = &cpu->env;
6984
92d5f1a4
PB		 6985#if !defined(CONFIG_USER_ONLY)
6986 if (interrupt_request & CPU_INTERRUPT_POLL) {
6987 return CPU_INTERRUPT_POLL;
6988 }
6989#endif
6990 if (interrupt_request & CPU_INTERRUPT_SIPI) {
6991 return CPU_INTERRUPT_SIPI;
6992 }
6993
6994 if (env->hflags2 & HF2_GIF_MASK) {
6995 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6996 !(env->hflags & HF_SMM_MASK)) {
6997 return CPU_INTERRUPT_SMI;
6998 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6999 !(env->hflags2 & HF2_NMI_MASK)) {
7000 return CPU_INTERRUPT_NMI;
7001 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7002 return CPU_INTERRUPT_MCE;
7003 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7004 (((env->hflags2 & HF2_VINTR_MASK) &&
7005 (env->hflags2 & HF2_HIF_MASK)) ||
7006 (!(env->hflags2 & HF2_VINTR_MASK) &&
7007 (env->eflags & IF_MASK &&
7008 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7009 return CPU_INTERRUPT_HARD;
7010#if !defined(CONFIG_USER_ONLY)
7011 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7012 (env->eflags & IF_MASK) &&
7013 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7014 return CPU_INTERRUPT_VIRQ;
7015#endif
7016 }
7017 }
7018
7019 return 0;
7020}
7021
7022static bool x86_cpu_has_work(CPUState *cs)
7023{
7024 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
8c2e1b00
AF		 7025}
7026
f50f3dd5
RH		 7027static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7028{
7029 X86CPU *cpu = X86_CPU(cs);
7030 CPUX86State *env = &cpu->env;
7031
7032 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7033 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7034 : bfd_mach_i386_i8086);
7035 info->print_insn = print_insn_i386;
b666d2a4
RH		 7036
7037 info->cap_arch = CS_ARCH_X86;
7038 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7039 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7040 : CS_MODE_16);
15fa1a0a
RH		 7041 info->cap_insn_unit = 1;
7042 info->cap_insn_split = 8;
f50f3dd5
RH		 7043}
7044
35b1b927
TW		 7045void x86_update_hflags(CPUX86State *env)
7046{
7047 uint32_t hflags;
7048#define HFLAG_COPY_MASK \
7049 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7050 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7051 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7052 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7053
7054 hflags = env->hflags & HFLAG_COPY_MASK;
7055 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7056 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7057 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7058 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7059 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7060
7061 if (env->cr[4] & CR4_OSFXSR_MASK) {
7062 hflags |= HF_OSFXSR_MASK;
7063 }
7064
7065 if (env->efer & MSR_EFER_LMA) {
7066 hflags |= HF_LMA_MASK;
7067 }
7068
7069 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7070 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7071 } else {
7072 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7073 (DESC_B_SHIFT - HF_CS32_SHIFT);
7074 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7075 (DESC_B_SHIFT - HF_SS32_SHIFT);
7076 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7077 !(hflags & HF_CS32_MASK)) {
7078 hflags |= HF_ADDSEG_MASK;
7079 } else {
7080 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7081 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7082 }
7083 }
7084 env->hflags = hflags;
7085}
7086
9337e3b6 7087static Property x86_cpu_properties[] = {
2da00e31
IM		 7088#ifdef CONFIG_USER_ONLY
7089 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7090 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
d89c2b8b
IM		 7091 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7092 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
176d2cda 7093 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
d89c2b8b 7094 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
2da00e31
IM		 7095#else
7096 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
d89c2b8b
IM		 7097 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7098 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
176d2cda 7099 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
d89c2b8b 7100 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
2da00e31 7101#endif
15f8b142 7102 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
9337e3b6 7103 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2d384d7c 7104
915aee93
RK		 7105 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7106 HYPERV_SPINLOCK_NEVER_RETRY),
2d384d7c
VK		 7107 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7108 HYPERV_FEAT_RELAXED, 0),
7109 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7110 HYPERV_FEAT_VAPIC, 0),
7111 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7112 HYPERV_FEAT_TIME, 0),
7113 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7114 HYPERV_FEAT_CRASH, 0),
7115 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7116 HYPERV_FEAT_RESET, 0),
7117 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7118 HYPERV_FEAT_VPINDEX, 0),
7119 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7120 HYPERV_FEAT_RUNTIME, 0),
7121 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7122 HYPERV_FEAT_SYNIC, 0),
7123 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7124 HYPERV_FEAT_STIMER, 0),
7125 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7126 HYPERV_FEAT_FREQUENCIES, 0),
7127 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7128 HYPERV_FEAT_REENLIGHTENMENT, 0),
7129 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7130 HYPERV_FEAT_TLBFLUSH, 0),
7131 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7132 HYPERV_FEAT_EVMCS, 0),
7133 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7134 HYPERV_FEAT_IPI, 0),
128531d9
VK		 7135 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7136 HYPERV_FEAT_STIMER_DIRECT, 0),
30d6ff66
VK		 7137 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7138 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
e48ddcc6 7139 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
2d384d7c 7140
15e41345 7141 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
912ffc47 7142 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
dac1deae 7143 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
f522d2ac 7144 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
af45907a 7145 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
11f6fee5 7146 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
258fe08b 7147 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
fcc35e7c 7148 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
80db491d
JL		 7149 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7150 UINT32_MAX),
c39c0edf
EH		 7151 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7152 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7153 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7154 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7155 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7156 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
4e45aff3 7157 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
c39c0edf 7158 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
1c4a55db 7159 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5232d00a 7160 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
87f8b626 7161 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
14c985cf 7162 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
fc3a1fd7
DDAG		 7163 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7164 false),
0b564e6f 7165 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
1ce36bfe 7166 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
990e0be2
PB		 7167 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7168 true),
ab8f992e 7169 /*
a9f27ea9
EH		 7170 * lecacy_cache defaults to true unless the CPU model provides its
7171 * own cache information (see x86_cpu_load_def()).
ab8f992e 7172 */
a9f27ea9 7173 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
6c69dfb6
GA		 7174
7175 /*
7176 * From "Requirements for Implementing the Microsoft
7177 * Hypervisor Interface":
7178 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7179 *
7180 * "Starting with Windows Server 2012 and Windows 8, if
7181 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7182 * the hypervisor imposes no specific limit to the number of VPs.
7183 * In this case, Windows Server 2012 guest VMs may use more than
7184 * 64 VPs, up to the maximum supported number of processors applicable
7185 * to the specific Windows version being used."
7186 */
7187 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
9b4cf107
RK		 7188 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7189 false),
f24c3a79
LK		 7190 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7191 true),
9337e3b6
EH		 7192 DEFINE_PROP_END_OF_LIST()
7193};
7194
5fd2087a
AF		 7195static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7196{
7197 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7198 CPUClass *cc = CPU_CLASS(oc);
2b6f294c
AF		 7199 DeviceClass *dc = DEVICE_CLASS(oc);
7200
bf853881
PMD		 7201 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7202 &xcc->parent_realize);
7203 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7204 &xcc->parent_unrealize);
4f67d30b 7205 device_class_set_props(dc, x86_cpu_properties);
5fd2087a 7206
781c67ca 7207 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
91b1df8c 7208 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
f56e3a14 7209
500050d1 7210 cc->class_by_name = x86_cpu_class_by_name;
94a444b2 7211 cc->parse_features = x86_cpu_parse_featurestr;
8c2e1b00 7212 cc->has_work = x86_cpu_has_work;
79c664f6 7213#ifdef CONFIG_TCG
97a8ea5a 7214 cc->do_interrupt = x86_cpu_do_interrupt;
42f53fea 7215 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
79c664f6 7216#endif
878096ee 7217 cc->dump_state = x86_cpu_dump_state;
c86f106b 7218 cc->get_crash_info = x86_cpu_get_crash_info;
f45748f1 7219 cc->set_pc = x86_cpu_set_pc;
bdf7ae5b 7220 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5b50e790
AF		 7221 cc->gdb_read_register = x86_cpu_gdb_read_register;
7222 cc->gdb_write_register = x86_cpu_gdb_write_register;
444d5590
AF		 7223 cc->get_arch_id = x86_cpu_get_arch_id;
7224 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5d004421 7225#ifndef CONFIG_USER_ONLY
f8c45c65 7226 cc->asidx_from_attrs = x86_asidx_from_attrs;
a23bbfda 7227 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
56f99750 7228 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
c72bf468
JF		 7229 cc->write_elf64_note = x86_cpu_write_elf64_note;
7230 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7231 cc->write_elf32_note = x86_cpu_write_elf32_note;
7232 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
00b941e5 7233 cc->vmsd = &vmstate_x86_cpu;
c72bf468 7234#endif
00fcd100
AB		 7235 cc->gdb_arch_name = x86_gdb_arch_name;
7236#ifdef TARGET_X86_64
b8158192 7237 cc->gdb_core_xml_file = "i386-64bit.xml";
7b0f97ba 7238 cc->gdb_num_core_regs = 66;
00fcd100 7239#else
b8158192 7240 cc->gdb_core_xml_file = "i386-32bit.xml";
7b0f97ba 7241 cc->gdb_num_core_regs = 50;
00fcd100 7242#endif
79c664f6 7243#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
86025ee4
PM		 7244 cc->debug_excp_handler = breakpoint_handler;
7245#endif
374e0cd4
RH		 7246 cc->cpu_exec_enter = x86_cpu_exec_enter;
7247 cc->cpu_exec_exit = x86_cpu_exec_exit;
74d7fc7f 7248#ifdef CONFIG_TCG
55c3ceef 7249 cc->tcg_initialize = tcg_x86_init;
5d004421 7250 cc->tlb_fill = x86_cpu_tlb_fill;
74d7fc7f 7251#endif
f50f3dd5 7252 cc->disas_set_info = x86_disas_set_info;
4c315c27 7253
e90f2a8c 7254 dc->user_creatable = true;
5fd2087a
AF		 7255}
7256
7257static const TypeInfo x86_cpu_type_info = {
7258 .name = TYPE_X86_CPU,
7259 .parent = TYPE_CPU,
7260 .instance_size = sizeof(X86CPU),
de024815 7261 .instance_init = x86_cpu_initfn,
d940ee9b 7262 .abstract = true,
5fd2087a
AF		 7263 .class_size = sizeof(X86CPUClass),
7264 .class_init = x86_cpu_common_class_init,
7265};
7266
5adbed30
EH		 7267
7268/* "base" CPU model, used by query-cpu-model-expansion */
7269static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7270{
7271 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7272
7273 xcc->static_model = true;
7274 xcc->migration_safe = true;
7275 xcc->model_description = "base CPU model type with no features enabled";
7276 xcc->ordering = 8;
7277}
7278
7279static const TypeInfo x86_base_cpu_type_info = {
7280 .name = X86_CPU_TYPE_NAME("base"),
7281 .parent = TYPE_X86_CPU,
7282 .class_init = x86_cpu_base_class_init,
7283};
7284
5fd2087a
AF		 7285static void x86_cpu_register_types(void)
7286{
d940ee9b
EH		 7287 int i;
7288
5fd2087a 7289 type_register_static(&x86_cpu_type_info);
d940ee9b 7290 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
dcafd1ef 7291 x86_register_cpudef_types(&builtin_x86_defs[i]);
d940ee9b 7292 }
c62f2630 7293 type_register_static(&max_x86_cpu_type_info);
5adbed30 7294 type_register_static(&x86_base_cpu_type_info);
d6dcc558 7295#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
d940ee9b
EH		 7296 type_register_static(&host_x86_cpu_type_info);
7297#endif
5fd2087a
AF		 7298}
7299
7300type_init(x86_cpu_register_types)
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